./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.03.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 678e0110 Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.03.cil.c -s /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 447c919af4e106e36f468570351956f4c77293d2 ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.24-678e011 [2019-11-20 10:36:33,238 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-20 10:36:33,240 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-20 10:36:33,253 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-20 10:36:33,253 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-20 10:36:33,254 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-20 10:36:33,256 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-20 10:36:33,258 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-20 10:36:33,261 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-20 10:36:33,262 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-20 10:36:33,263 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-20 10:36:33,265 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-20 10:36:33,265 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-20 10:36:33,266 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-20 10:36:33,268 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-20 10:36:33,269 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-20 10:36:33,270 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-20 10:36:33,271 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-20 10:36:33,274 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-20 10:36:33,277 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-20 10:36:33,279 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-20 10:36:33,281 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-20 10:36:33,282 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-20 10:36:33,284 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-20 10:36:33,287 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-20 10:36:33,288 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-20 10:36:33,288 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-20 10:36:33,289 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-20 10:36:33,290 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-20 10:36:33,291 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-20 10:36:33,291 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-20 10:36:33,292 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-20 10:36:33,293 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-20 10:36:33,294 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-20 10:36:33,295 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-20 10:36:33,295 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-20 10:36:33,296 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-20 10:36:33,296 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-20 10:36:33,297 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-20 10:36:33,298 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-20 10:36:33,299 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-20 10:36:33,300 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2019-11-20 10:36:33,318 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-20 10:36:33,319 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-20 10:36:33,320 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-20 10:36:33,320 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-20 10:36:33,321 INFO L138 SettingsManager]: * Use SBE=true [2019-11-20 10:36:33,321 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2019-11-20 10:36:33,321 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2019-11-20 10:36:33,322 INFO L138 SettingsManager]: * Use old map elimination=false [2019-11-20 10:36:33,322 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2019-11-20 10:36:33,322 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2019-11-20 10:36:33,322 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2019-11-20 10:36:33,323 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-20 10:36:33,323 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-20 10:36:33,323 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2019-11-20 10:36:33,324 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-20 10:36:33,324 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-20 10:36:33,324 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-20 10:36:33,324 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2019-11-20 10:36:33,325 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2019-11-20 10:36:33,325 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2019-11-20 10:36:33,325 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-20 10:36:33,325 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-20 10:36:33,326 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2019-11-20 10:36:33,326 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-20 10:36:33,326 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2019-11-20 10:36:33,326 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-20 10:36:33,327 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-20 10:36:33,327 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2019-11-20 10:36:33,327 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-20 10:36:33,328 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-20 10:36:33,328 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2019-11-20 10:36:33,329 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2019-11-20 10:36:33,329 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 447c919af4e106e36f468570351956f4c77293d2 [2019-11-20 10:36:33,504 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-20 10:36:33,517 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-20 10:36:33,521 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-20 10:36:33,522 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-20 10:36:33,523 INFO L275 PluginConnector]: CDTParser initialized [2019-11-20 10:36:33,524 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/../../sv-benchmarks/c/systemc/transmitter.03.cil.c [2019-11-20 10:36:33,593 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/data/70db45d1d/0b24b3c3b1554d9c90200cd925af72df/FLAG0937690a9 [2019-11-20 10:36:34,048 INFO L306 CDTParser]: Found 1 translation units. [2019-11-20 10:36:34,048 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/sv-benchmarks/c/systemc/transmitter.03.cil.c [2019-11-20 10:36:34,071 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/data/70db45d1d/0b24b3c3b1554d9c90200cd925af72df/FLAG0937690a9 [2019-11-20 10:36:34,469 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/data/70db45d1d/0b24b3c3b1554d9c90200cd925af72df [2019-11-20 10:36:34,472 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-20 10:36:34,474 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-20 10:36:34,475 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-20 10:36:34,475 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-20 10:36:34,479 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-20 10:36:34,480 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 10:36:34" (1/1) ... [2019-11-20 10:36:34,483 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7e5d0f2b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:36:34, skipping insertion in model container [2019-11-20 10:36:34,484 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.11 10:36:34" (1/1) ... [2019-11-20 10:36:34,492 INFO L142 MainTranslator]: Starting translation in SV-COMP mode [2019-11-20 10:36:34,554 INFO L173 MainTranslator]: Built tables and reachable declarations [2019-11-20 10:36:34,870 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-20 10:36:34,881 INFO L188 MainTranslator]: Completed pre-run [2019-11-20 10:36:34,938 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-20 10:36:34,959 INFO L192 MainTranslator]: Completed translation [2019-11-20 10:36:34,960 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:36:34 WrapperNode [2019-11-20 10:36:34,960 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-20 10:36:34,961 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-20 10:36:34,961 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-20 10:36:34,961 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-20 10:36:34,970 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:36:34" (1/1) ... [2019-11-20 10:36:34,978 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:36:34" (1/1) ... [2019-11-20 10:36:35,017 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-20 10:36:35,017 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-20 10:36:35,017 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-20 10:36:35,017 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-20 10:36:35,027 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:36:34" (1/1) ... [2019-11-20 10:36:35,027 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:36:34" (1/1) ... [2019-11-20 10:36:35,032 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:36:34" (1/1) ... [2019-11-20 10:36:35,033 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:36:34" (1/1) ... [2019-11-20 10:36:35,043 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:36:34" (1/1) ... [2019-11-20 10:36:35,072 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:36:34" (1/1) ... [2019-11-20 10:36:35,078 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:36:34" (1/1) ... [2019-11-20 10:36:35,083 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-20 10:36:35,083 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-20 10:36:35,084 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-20 10:36:35,084 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-20 10:36:35,085 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:36:34" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:35,161 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-20 10:36:35,161 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-20 10:36:36,212 INFO L280 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-20 10:36:36,213 INFO L285 CfgBuilder]: Removed 119 assume(true) statements. [2019-11-20 10:36:36,214 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 10:36:36 BoogieIcfgContainer [2019-11-20 10:36:36,214 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-20 10:36:36,215 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2019-11-20 10:36:36,215 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2019-11-20 10:36:36,221 INFO L275 PluginConnector]: BuchiAutomizer initialized [2019-11-20 10:36:36,222 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-11-20 10:36:36,222 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 20.11 10:36:34" (1/3) ... [2019-11-20 10:36:36,224 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6554df8b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 20.11 10:36:36, skipping insertion in model container [2019-11-20 10:36:36,224 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-11-20 10:36:36,224 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.11 10:36:34" (2/3) ... [2019-11-20 10:36:36,225 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6554df8b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 20.11 10:36:36, skipping insertion in model container [2019-11-20 10:36:36,225 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-11-20 10:36:36,225 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 10:36:36" (3/3) ... [2019-11-20 10:36:36,228 INFO L371 chiAutomizerObserver]: Analyzing ICFG transmitter.03.cil.c [2019-11-20 10:36:36,281 INFO L356 BuchiCegarLoop]: Interprodecural is true [2019-11-20 10:36:36,282 INFO L357 BuchiCegarLoop]: Hoare is false [2019-11-20 10:36:36,282 INFO L358 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2019-11-20 10:36:36,283 INFO L359 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-20 10:36:36,283 INFO L360 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-20 10:36:36,283 INFO L361 BuchiCegarLoop]: Difference is false [2019-11-20 10:36:36,283 INFO L362 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-20 10:36:36,284 INFO L365 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2019-11-20 10:36:36,327 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 275 states. [2019-11-20 10:36:36,373 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 222 [2019-11-20 10:36:36,374 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-20 10:36:36,374 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-20 10:36:36,385 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:36,385 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:36,385 INFO L424 BuchiCegarLoop]: ======== Iteration 1============ [2019-11-20 10:36:36,385 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 275 states. [2019-11-20 10:36:36,396 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 222 [2019-11-20 10:36:36,397 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-20 10:36:36,397 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-20 10:36:36,400 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:36,400 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:36,407 INFO L794 eck$LassoCheckResult]: Stem: 90#ULTIMATE.startENTRYtrue ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 9#L-1true havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 116#L605true havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 87#L264true assume !(1 == ~m_i~0);~m_st~0 := 2; 167#L271-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 178#L276-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 73#L281-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 85#L286-1true assume !(0 == ~M_E~0); 190#L408-1true assume !(0 == ~T1_E~0); 66#L413-1true assume !(0 == ~T2_E~0); 105#L418-1true assume !(0 == ~T3_E~0); 138#L423-1true assume !(0 == ~E_1~0); 25#L428-1true assume 0 == ~E_2~0;~E_2~0 := 1; 32#L433-1true assume !(0 == ~E_3~0); 209#L438-1true havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 81#L187true assume !(1 == ~m_pc~0); 98#L187-2true is_master_triggered_~__retres1~0 := 0; 82#L198true is_master_triggered_#res := is_master_triggered_~__retres1~0; 175#L199true activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 128#L500true assume !(0 != activate_threads_~tmp~1); 133#L500-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 253#L206true assume 1 == ~t1_pc~0; 34#L207true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 254#L217true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 35#L218true activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 156#L508true assume !(0 != activate_threads_~tmp___0~0); 158#L508-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 134#L225true assume !(1 == ~t2_pc~0); 129#L225-2true is_transmit2_triggered_~__retres1~2 := 0; 135#L236true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 69#L237true activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 20#L516true assume !(0 != activate_threads_~tmp___1~0); 22#L516-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 268#L244true assume 1 == ~t3_pc~0; 232#L245true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 151#L255true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 233#L256true activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 176#L524true assume !(0 != activate_threads_~tmp___2~0); 179#L524-2true assume !(1 == ~M_E~0); 102#L451-1true assume 1 == ~T1_E~0;~T1_E~0 := 2; 136#L456-1true assume !(1 == ~T2_E~0); 23#L461-1true assume !(1 == ~T3_E~0); 31#L466-1true assume !(1 == ~E_1~0); 204#L471-1true assume !(1 == ~E_2~0); 236#L476-1true assume !(1 == ~E_3~0); 36#L642-1true [2019-11-20 10:36:36,408 INFO L796 eck$LassoCheckResult]: Loop: 36#L642-1true assume !false; 4#L643true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 211#L383true assume false; 142#L398true start_simulation_~kernel_st~0 := 2; 83#L264-1true start_simulation_~kernel_st~0 := 3; 191#L408-2true assume 0 == ~M_E~0;~M_E~0 := 1; 180#L408-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 76#L413-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 111#L418-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 124#L423-3true assume 0 == ~E_1~0;~E_1~0 := 1; 10#L428-3true assume 0 == ~E_2~0;~E_2~0 := 1; 30#L433-3true assume 0 == ~E_3~0;~E_3~0 := 1; 41#L438-3true havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 53#L187-12true assume !(1 == ~m_pc~0); 71#L187-14true is_master_triggered_~__retres1~0 := 0; 94#L198-4true is_master_triggered_#res := is_master_triggered_~__retres1~0; 185#L199-4true activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 114#L500-12true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 118#L500-14true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 235#L206-12true assume 1 == ~t1_pc~0; 42#L207-4true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 244#L217-4true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 43#L218-4true activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 274#L508-12true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 257#L508-14true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 113#L225-12true assume 1 == ~t2_pc~0; 194#L226-4true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 106#L236-4true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 195#L237-4true activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 5#L516-12true assume !(0 != activate_threads_~tmp___1~0); 6#L516-14true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 241#L244-12true assume 1 == ~t3_pc~0; 201#L245-4true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 259#L255-4true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 202#L256-4true activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 163#L524-12true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 153#L524-14true assume 1 == ~M_E~0;~M_E~0 := 2; 107#L451-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 139#L456-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 27#L461-3true assume !(1 == ~T3_E~0); 33#L466-3true assume 1 == ~E_1~0;~E_1~0 := 2; 38#L471-3true assume 1 == ~E_2~0;~E_2~0 := 2; 216#L476-3true assume 1 == ~E_3~0;~E_3~0 := 2; 245#L481-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 152#L299-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 147#L321-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 223#L322-1true start_simulation_#t~ret10 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 57#L661true assume !(0 == start_simulation_~tmp~3); 196#L661-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 267#L299-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 150#L321-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 226#L322-2true stop_simulation_#t~ret9 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 115#L616true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 188#L623true stop_simulation_#res := stop_simulation_~__retres2~0; 275#L624true start_simulation_#t~ret11 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 240#L674true assume !(0 != start_simulation_~tmp___0~1); 36#L642-1true [2019-11-20 10:36:36,414 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:36,414 INFO L82 PathProgramCache]: Analyzing trace with hash 1271326673, now seen corresponding path program 1 times [2019-11-20 10:36:36,421 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:36,421 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1841349932] [2019-11-20 10:36:36,421 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:36,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:36,561 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 10:36:36,562 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1841349932] [2019-11-20 10:36:36,563 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 10:36:36,563 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 10:36:36,565 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1430673010] [2019-11-20 10:36:36,570 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-20 10:36:36,570 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:36,570 INFO L82 PathProgramCache]: Analyzing trace with hash -519643673, now seen corresponding path program 1 times [2019-11-20 10:36:36,571 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:36,571 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1057279943] [2019-11-20 10:36:36,571 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:36,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:36,591 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 10:36:36,592 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1057279943] [2019-11-20 10:36:36,592 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 10:36:36,592 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 10:36:36,592 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [956906550] [2019-11-20 10:36:36,594 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-20 10:36:36,595 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 10:36:36,610 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 10:36:36,611 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 10:36:36,613 INFO L87 Difference]: Start difference. First operand 275 states. Second operand 3 states. [2019-11-20 10:36:36,647 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 10:36:36,647 INFO L93 Difference]: Finished difference Result 275 states and 415 transitions. [2019-11-20 10:36:36,648 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 10:36:36,650 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 275 states and 415 transitions. [2019-11-20 10:36:36,660 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 221 [2019-11-20 10:36:36,669 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 275 states to 270 states and 410 transitions. [2019-11-20 10:36:36,671 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 270 [2019-11-20 10:36:36,672 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 270 [2019-11-20 10:36:36,673 INFO L73 IsDeterministic]: Start isDeterministic. Operand 270 states and 410 transitions. [2019-11-20 10:36:36,676 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-20 10:36:36,677 INFO L688 BuchiCegarLoop]: Abstraction has 270 states and 410 transitions. [2019-11-20 10:36:36,702 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 270 states and 410 transitions. [2019-11-20 10:36:36,726 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 270 to 270. [2019-11-20 10:36:36,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 270 states. [2019-11-20 10:36:36,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 270 states to 270 states and 410 transitions. [2019-11-20 10:36:36,729 INFO L711 BuchiCegarLoop]: Abstraction has 270 states and 410 transitions. [2019-11-20 10:36:36,729 INFO L591 BuchiCegarLoop]: Abstraction has 270 states and 410 transitions. [2019-11-20 10:36:36,730 INFO L424 BuchiCegarLoop]: ======== Iteration 2============ [2019-11-20 10:36:36,730 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 270 states and 410 transitions. [2019-11-20 10:36:36,732 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 221 [2019-11-20 10:36:36,732 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-20 10:36:36,733 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-20 10:36:36,735 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:36,736 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:36,736 INFO L794 eck$LassoCheckResult]: Stem: 724#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 570#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 571#L605 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 718#L264 assume 1 == ~m_i~0;~m_st~0 := 0; 719#L271-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 791#L276-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 689#L281-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 690#L286-1 assume !(0 == ~M_E~0); 717#L408-1 assume !(0 == ~T1_E~0); 677#L413-1 assume !(0 == ~T2_E~0); 678#L418-1 assume !(0 == ~T3_E~0); 738#L423-1 assume !(0 == ~E_1~0); 603#L428-1 assume 0 == ~E_2~0;~E_2~0 := 1; 604#L433-1 assume !(0 == ~E_3~0); 611#L438-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 706#L187 assume !(1 == ~m_pc~0); 707#L187-2 is_master_triggered_~__retres1~0 := 0; 709#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 710#L199 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 759#L500 assume !(0 != activate_threads_~tmp~1); 760#L500-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 762#L206 assume 1 == ~t1_pc~0; 613#L207 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 614#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 616#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 617#L508 assume !(0 != activate_threads_~tmp___0~0); 781#L508-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 763#L225 assume !(1 == ~t2_pc~0); 680#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 681#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 684#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 595#L516 assume !(0 != activate_threads_~tmp___1~0); 596#L516-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 598#L244 assume 1 == ~t3_pc~0; 823#L245 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 775#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 776#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 795#L524 assume !(0 != activate_threads_~tmp___2~0); 796#L524-2 assume !(1 == ~M_E~0); 735#L451-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 736#L456-1 assume !(1 == ~T2_E~0); 599#L461-1 assume !(1 == ~T3_E~0); 600#L466-1 assume !(1 == ~E_1~0); 610#L471-1 assume !(1 == ~E_2~0); 812#L476-1 assume !(1 == ~E_3~0); 618#L642-1 [2019-11-20 10:36:36,737 INFO L796 eck$LassoCheckResult]: Loop: 618#L642-1 assume !false; 561#L643 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 562#L383 assume !false; 768#L332 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 769#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 577#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 770#L322 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 691#L336 assume !(0 != eval_~tmp~0); 693#L398 start_simulation_~kernel_st~0 := 2; 711#L264-1 start_simulation_~kernel_st~0 := 3; 712#L408-2 assume 0 == ~M_E~0;~M_E~0 := 1; 797#L408-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 695#L413-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 696#L418-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 743#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 572#L428-3 assume 0 == ~E_2~0;~E_2~0 := 1; 573#L433-3 assume 0 == ~E_3~0;~E_3~0 := 1; 609#L438-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 627#L187-12 assume 1 == ~m_pc~0; 651#L188-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 688#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 728#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 750#L500-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 751#L500-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 752#L206-12 assume 1 == ~t1_pc~0; 628#L207-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 629#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 631#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 632#L508-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 826#L508-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 746#L225-12 assume !(1 == ~t2_pc~0); 720#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 721#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 739#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 563#L516-12 assume !(0 != activate_threads_~tmp___1~0); 564#L516-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 565#L244-12 assume 1 == ~t3_pc~0; 805#L245-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 806#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 808#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 786#L524-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 778#L524-14 assume 1 == ~M_E~0;~M_E~0 := 2; 740#L451-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 741#L456-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 605#L461-3 assume !(1 == ~T3_E~0); 606#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 612#L471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 621#L476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 821#L481-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 777#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 583#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 772#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 659#L661 assume !(0 == start_simulation_~tmp~3); 608#L661-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 799#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 590#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 774#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 748#L616 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 749#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 798#L624 start_simulation_#t~ret11 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 825#L674 assume !(0 != start_simulation_~tmp___0~1); 618#L642-1 [2019-11-20 10:36:36,737 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:36,737 INFO L82 PathProgramCache]: Analyzing trace with hash 1023180179, now seen corresponding path program 1 times [2019-11-20 10:36:36,737 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:36,737 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1325312205] [2019-11-20 10:36:36,738 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:36,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:36,770 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 10:36:36,771 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1325312205] [2019-11-20 10:36:36,771 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 10:36:36,771 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 10:36:36,771 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [694898971] [2019-11-20 10:36:36,772 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-20 10:36:36,772 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:36,772 INFO L82 PathProgramCache]: Analyzing trace with hash 213876970, now seen corresponding path program 1 times [2019-11-20 10:36:36,772 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:36,772 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1938335892] [2019-11-20 10:36:36,773 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:36,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:36,859 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 10:36:36,860 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1938335892] [2019-11-20 10:36:36,860 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 10:36:36,860 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 10:36:36,860 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [16389315] [2019-11-20 10:36:36,861 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-20 10:36:36,861 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 10:36:36,861 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 10:36:36,862 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 10:36:36,862 INFO L87 Difference]: Start difference. First operand 270 states and 410 transitions. cyclomatic complexity: 141 Second operand 3 states. [2019-11-20 10:36:36,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 10:36:36,881 INFO L93 Difference]: Finished difference Result 270 states and 409 transitions. [2019-11-20 10:36:36,881 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 10:36:36,882 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 270 states and 409 transitions. [2019-11-20 10:36:36,885 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 221 [2019-11-20 10:36:36,889 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 270 states to 270 states and 409 transitions. [2019-11-20 10:36:36,889 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 270 [2019-11-20 10:36:36,890 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 270 [2019-11-20 10:36:36,890 INFO L73 IsDeterministic]: Start isDeterministic. Operand 270 states and 409 transitions. [2019-11-20 10:36:36,893 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-20 10:36:36,893 INFO L688 BuchiCegarLoop]: Abstraction has 270 states and 409 transitions. [2019-11-20 10:36:36,894 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 270 states and 409 transitions. [2019-11-20 10:36:36,906 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 270 to 270. [2019-11-20 10:36:36,906 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 270 states. [2019-11-20 10:36:36,907 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 270 states to 270 states and 409 transitions. [2019-11-20 10:36:36,908 INFO L711 BuchiCegarLoop]: Abstraction has 270 states and 409 transitions. [2019-11-20 10:36:36,908 INFO L591 BuchiCegarLoop]: Abstraction has 270 states and 409 transitions. [2019-11-20 10:36:36,908 INFO L424 BuchiCegarLoop]: ======== Iteration 3============ [2019-11-20 10:36:36,908 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 270 states and 409 transitions. [2019-11-20 10:36:36,910 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 221 [2019-11-20 10:36:36,911 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-20 10:36:36,911 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-20 10:36:36,913 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:36,913 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:36,913 INFO L794 eck$LassoCheckResult]: Stem: 1271#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 1117#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1118#L605 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1265#L264 assume 1 == ~m_i~0;~m_st~0 := 0; 1266#L271-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1338#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1236#L281-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1237#L286-1 assume !(0 == ~M_E~0); 1264#L408-1 assume !(0 == ~T1_E~0); 1224#L413-1 assume !(0 == ~T2_E~0); 1225#L418-1 assume !(0 == ~T3_E~0); 1285#L423-1 assume !(0 == ~E_1~0); 1150#L428-1 assume 0 == ~E_2~0;~E_2~0 := 1; 1151#L433-1 assume !(0 == ~E_3~0); 1158#L438-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1253#L187 assume !(1 == ~m_pc~0); 1254#L187-2 is_master_triggered_~__retres1~0 := 0; 1256#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1257#L199 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1306#L500 assume !(0 != activate_threads_~tmp~1); 1307#L500-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1309#L206 assume 1 == ~t1_pc~0; 1160#L207 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1161#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1163#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1164#L508 assume !(0 != activate_threads_~tmp___0~0); 1328#L508-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1310#L225 assume !(1 == ~t2_pc~0); 1227#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 1228#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1231#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1142#L516 assume !(0 != activate_threads_~tmp___1~0); 1143#L516-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1145#L244 assume 1 == ~t3_pc~0; 1370#L245 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1322#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1323#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1342#L524 assume !(0 != activate_threads_~tmp___2~0); 1343#L524-2 assume !(1 == ~M_E~0); 1282#L451-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1283#L456-1 assume !(1 == ~T2_E~0); 1146#L461-1 assume !(1 == ~T3_E~0); 1147#L466-1 assume !(1 == ~E_1~0); 1157#L471-1 assume !(1 == ~E_2~0); 1360#L476-1 assume !(1 == ~E_3~0); 1165#L642-1 [2019-11-20 10:36:36,914 INFO L796 eck$LassoCheckResult]: Loop: 1165#L642-1 assume !false; 1108#L643 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 1109#L383 assume !false; 1315#L332 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1316#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1124#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1317#L322 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1238#L336 assume !(0 != eval_~tmp~0); 1240#L398 start_simulation_~kernel_st~0 := 2; 1258#L264-1 start_simulation_~kernel_st~0 := 3; 1259#L408-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1344#L408-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1242#L413-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1243#L418-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1290#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1119#L428-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1120#L433-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1156#L438-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1174#L187-12 assume 1 == ~m_pc~0; 1198#L188-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1235#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1275#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1297#L500-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1298#L500-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1299#L206-12 assume 1 == ~t1_pc~0; 1175#L207-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1176#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1178#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1179#L508-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1373#L508-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1293#L225-12 assume !(1 == ~t2_pc~0); 1267#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 1268#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1286#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1110#L516-12 assume !(0 != activate_threads_~tmp___1~0); 1111#L516-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1112#L244-12 assume 1 == ~t3_pc~0; 1352#L245-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1353#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1355#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1333#L524-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1325#L524-14 assume 1 == ~M_E~0;~M_E~0 := 2; 1287#L451-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1288#L456-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1152#L461-3 assume !(1 == ~T3_E~0); 1153#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1159#L471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1166#L476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1368#L481-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1324#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1130#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1319#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 1206#L661 assume !(0 == start_simulation_~tmp~3); 1155#L661-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1346#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1137#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1321#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 1295#L616 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1296#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 1345#L624 start_simulation_#t~ret11 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 1372#L674 assume !(0 != start_simulation_~tmp___0~1); 1165#L642-1 [2019-11-20 10:36:36,914 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:36,914 INFO L82 PathProgramCache]: Analyzing trace with hash -1899979819, now seen corresponding path program 1 times [2019-11-20 10:36:36,915 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:36,915 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2035888442] [2019-11-20 10:36:36,915 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:36,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:36,958 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 10:36:36,959 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2035888442] [2019-11-20 10:36:36,959 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 10:36:36,959 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 10:36:36,959 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [167930018] [2019-11-20 10:36:36,960 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-20 10:36:36,960 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:36,960 INFO L82 PathProgramCache]: Analyzing trace with hash 213876970, now seen corresponding path program 2 times [2019-11-20 10:36:36,961 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:36,961 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1298754906] [2019-11-20 10:36:36,961 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:36,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:37,056 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 10:36:37,056 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1298754906] [2019-11-20 10:36:37,056 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 10:36:37,057 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 10:36:37,057 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1829170816] [2019-11-20 10:36:37,057 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-20 10:36:37,058 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 10:36:37,058 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 10:36:37,058 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 10:36:37,058 INFO L87 Difference]: Start difference. First operand 270 states and 409 transitions. cyclomatic complexity: 140 Second operand 3 states. [2019-11-20 10:36:37,073 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 10:36:37,073 INFO L93 Difference]: Finished difference Result 270 states and 408 transitions. [2019-11-20 10:36:37,074 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 10:36:37,074 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 270 states and 408 transitions. [2019-11-20 10:36:37,077 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 221 [2019-11-20 10:36:37,086 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 270 states to 270 states and 408 transitions. [2019-11-20 10:36:37,087 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 270 [2019-11-20 10:36:37,087 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 270 [2019-11-20 10:36:37,087 INFO L73 IsDeterministic]: Start isDeterministic. Operand 270 states and 408 transitions. [2019-11-20 10:36:37,089 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-20 10:36:37,089 INFO L688 BuchiCegarLoop]: Abstraction has 270 states and 408 transitions. [2019-11-20 10:36:37,090 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 270 states and 408 transitions. [2019-11-20 10:36:37,106 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 270 to 270. [2019-11-20 10:36:37,106 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 270 states. [2019-11-20 10:36:37,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 270 states to 270 states and 408 transitions. [2019-11-20 10:36:37,108 INFO L711 BuchiCegarLoop]: Abstraction has 270 states and 408 transitions. [2019-11-20 10:36:37,108 INFO L591 BuchiCegarLoop]: Abstraction has 270 states and 408 transitions. [2019-11-20 10:36:37,108 INFO L424 BuchiCegarLoop]: ======== Iteration 4============ [2019-11-20 10:36:37,108 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 270 states and 408 transitions. [2019-11-20 10:36:37,113 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 221 [2019-11-20 10:36:37,113 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-20 10:36:37,113 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-20 10:36:37,121 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:37,121 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:37,123 INFO L794 eck$LassoCheckResult]: Stem: 1818#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 1664#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1665#L605 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1812#L264 assume 1 == ~m_i~0;~m_st~0 := 0; 1813#L271-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1885#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1783#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1784#L286-1 assume !(0 == ~M_E~0); 1811#L408-1 assume !(0 == ~T1_E~0); 1771#L413-1 assume !(0 == ~T2_E~0); 1772#L418-1 assume !(0 == ~T3_E~0); 1832#L423-1 assume !(0 == ~E_1~0); 1697#L428-1 assume 0 == ~E_2~0;~E_2~0 := 1; 1698#L433-1 assume !(0 == ~E_3~0); 1705#L438-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1800#L187 assume !(1 == ~m_pc~0); 1801#L187-2 is_master_triggered_~__retres1~0 := 0; 1803#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1804#L199 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1853#L500 assume !(0 != activate_threads_~tmp~1); 1854#L500-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1856#L206 assume 1 == ~t1_pc~0; 1707#L207 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1708#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1710#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1711#L508 assume !(0 != activate_threads_~tmp___0~0); 1875#L508-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1857#L225 assume !(1 == ~t2_pc~0); 1774#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 1775#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1778#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1689#L516 assume !(0 != activate_threads_~tmp___1~0); 1690#L516-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1692#L244 assume 1 == ~t3_pc~0; 1917#L245 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1869#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1870#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1889#L524 assume !(0 != activate_threads_~tmp___2~0); 1890#L524-2 assume !(1 == ~M_E~0); 1829#L451-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1830#L456-1 assume !(1 == ~T2_E~0); 1693#L461-1 assume !(1 == ~T3_E~0); 1694#L466-1 assume !(1 == ~E_1~0); 1704#L471-1 assume !(1 == ~E_2~0); 1907#L476-1 assume !(1 == ~E_3~0); 1712#L642-1 [2019-11-20 10:36:37,124 INFO L796 eck$LassoCheckResult]: Loop: 1712#L642-1 assume !false; 1655#L643 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 1656#L383 assume !false; 1862#L332 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1863#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1671#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1864#L322 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1785#L336 assume !(0 != eval_~tmp~0); 1787#L398 start_simulation_~kernel_st~0 := 2; 1805#L264-1 start_simulation_~kernel_st~0 := 3; 1806#L408-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1891#L408-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1789#L413-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1790#L418-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1837#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1666#L428-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1667#L433-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1703#L438-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1721#L187-12 assume 1 == ~m_pc~0; 1745#L188-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1782#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1822#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1844#L500-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1845#L500-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1846#L206-12 assume 1 == ~t1_pc~0; 1722#L207-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1723#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1725#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1726#L508-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1920#L508-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1840#L225-12 assume 1 == ~t2_pc~0; 1841#L226-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1815#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1833#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1657#L516-12 assume !(0 != activate_threads_~tmp___1~0); 1658#L516-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1659#L244-12 assume 1 == ~t3_pc~0; 1899#L245-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1900#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1902#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1880#L524-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1872#L524-14 assume 1 == ~M_E~0;~M_E~0 := 2; 1834#L451-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1835#L456-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1699#L461-3 assume !(1 == ~T3_E~0); 1700#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1706#L471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1713#L476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1915#L481-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1871#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1677#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1866#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 1753#L661 assume !(0 == start_simulation_~tmp~3); 1702#L661-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1893#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1684#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1868#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 1842#L616 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1843#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 1892#L624 start_simulation_#t~ret11 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 1919#L674 assume !(0 != start_simulation_~tmp___0~1); 1712#L642-1 [2019-11-20 10:36:37,124 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:37,124 INFO L82 PathProgramCache]: Analyzing trace with hash -54612653, now seen corresponding path program 1 times [2019-11-20 10:36:37,125 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:37,125 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1201134137] [2019-11-20 10:36:37,125 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:37,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:37,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 10:36:37,206 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1201134137] [2019-11-20 10:36:37,206 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 10:36:37,206 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 10:36:37,207 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [618052012] [2019-11-20 10:36:37,207 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-20 10:36:37,207 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:37,208 INFO L82 PathProgramCache]: Analyzing trace with hash 1985347945, now seen corresponding path program 1 times [2019-11-20 10:36:37,208 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:37,208 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [921635376] [2019-11-20 10:36:37,208 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:37,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:37,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 10:36:37,249 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [921635376] [2019-11-20 10:36:37,249 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 10:36:37,249 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 10:36:37,250 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [199641755] [2019-11-20 10:36:37,250 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-20 10:36:37,250 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 10:36:37,251 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 10:36:37,251 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 10:36:37,251 INFO L87 Difference]: Start difference. First operand 270 states and 408 transitions. cyclomatic complexity: 139 Second operand 3 states. [2019-11-20 10:36:37,299 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 10:36:37,299 INFO L93 Difference]: Finished difference Result 270 states and 398 transitions. [2019-11-20 10:36:37,300 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 10:36:37,300 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 270 states and 398 transitions. [2019-11-20 10:36:37,306 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 221 [2019-11-20 10:36:37,309 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 270 states to 270 states and 398 transitions. [2019-11-20 10:36:37,309 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 270 [2019-11-20 10:36:37,310 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 270 [2019-11-20 10:36:37,310 INFO L73 IsDeterministic]: Start isDeterministic. Operand 270 states and 398 transitions. [2019-11-20 10:36:37,311 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-20 10:36:37,311 INFO L688 BuchiCegarLoop]: Abstraction has 270 states and 398 transitions. [2019-11-20 10:36:37,312 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 270 states and 398 transitions. [2019-11-20 10:36:37,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 270 to 270. [2019-11-20 10:36:37,320 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 270 states. [2019-11-20 10:36:37,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 270 states to 270 states and 398 transitions. [2019-11-20 10:36:37,333 INFO L711 BuchiCegarLoop]: Abstraction has 270 states and 398 transitions. [2019-11-20 10:36:37,334 INFO L591 BuchiCegarLoop]: Abstraction has 270 states and 398 transitions. [2019-11-20 10:36:37,334 INFO L424 BuchiCegarLoop]: ======== Iteration 5============ [2019-11-20 10:36:37,334 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 270 states and 398 transitions. [2019-11-20 10:36:37,336 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 221 [2019-11-20 10:36:37,337 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-20 10:36:37,337 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-20 10:36:37,338 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:37,338 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:37,339 INFO L794 eck$LassoCheckResult]: Stem: 2362#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 2211#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2212#L605 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2356#L264 assume 1 == ~m_i~0;~m_st~0 := 0; 2357#L271-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2432#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2327#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2328#L286-1 assume !(0 == ~M_E~0); 2355#L408-1 assume !(0 == ~T1_E~0); 2316#L413-1 assume !(0 == ~T2_E~0); 2317#L418-1 assume !(0 == ~T3_E~0); 2377#L423-1 assume !(0 == ~E_1~0); 2244#L428-1 assume !(0 == ~E_2~0); 2245#L433-1 assume !(0 == ~E_3~0); 2252#L438-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2344#L187 assume !(1 == ~m_pc~0); 2345#L187-2 is_master_triggered_~__retres1~0 := 0; 2347#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2348#L199 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 2399#L500 assume !(0 != activate_threads_~tmp~1); 2400#L500-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2403#L206 assume 1 == ~t1_pc~0; 2254#L207 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2255#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2257#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2258#L508 assume !(0 != activate_threads_~tmp___0~0); 2422#L508-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2404#L225 assume !(1 == ~t2_pc~0); 2319#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 2401#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2323#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2236#L516 assume !(0 != activate_threads_~tmp___1~0); 2237#L516-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2239#L244 assume 1 == ~t3_pc~0; 2464#L245 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2416#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2417#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2436#L524 assume !(0 != activate_threads_~tmp___2~0); 2437#L524-2 assume !(1 == ~M_E~0); 2373#L451-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2374#L456-1 assume !(1 == ~T2_E~0); 2240#L461-1 assume !(1 == ~T3_E~0); 2241#L466-1 assume !(1 == ~E_1~0); 2251#L471-1 assume !(1 == ~E_2~0); 2454#L476-1 assume !(1 == ~E_3~0); 2259#L642-1 [2019-11-20 10:36:37,339 INFO L796 eck$LassoCheckResult]: Loop: 2259#L642-1 assume !false; 2202#L643 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 2203#L383 assume !false; 2409#L332 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2410#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2218#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2411#L322 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2329#L336 assume !(0 != eval_~tmp~0); 2331#L398 start_simulation_~kernel_st~0 := 2; 2349#L264-1 start_simulation_~kernel_st~0 := 3; 2350#L408-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2438#L408-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2333#L413-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2334#L418-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2383#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2213#L428-3 assume !(0 == ~E_2~0); 2214#L433-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2250#L438-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2268#L187-12 assume 1 == ~m_pc~0; 2292#L188-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2321#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2366#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 2388#L500-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2389#L500-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2392#L206-12 assume 1 == ~t1_pc~0; 2269#L207-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2270#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2272#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2273#L508-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2467#L508-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2386#L225-12 assume !(1 == ~t2_pc~0); 2358#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 2359#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2378#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2204#L516-12 assume !(0 != activate_threads_~tmp___1~0); 2205#L516-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2206#L244-12 assume !(1 == ~t3_pc~0); 2448#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 2447#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2449#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2427#L524-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2419#L524-14 assume 1 == ~M_E~0;~M_E~0 := 2; 2379#L451-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2380#L456-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2246#L461-3 assume !(1 == ~T3_E~0); 2247#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2253#L471-3 assume !(1 == ~E_2~0); 2260#L476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2462#L481-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2418#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2224#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2413#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 2300#L661 assume !(0 == start_simulation_~tmp~3); 2249#L661-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2440#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2231#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2415#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 2390#L616 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2391#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 2439#L624 start_simulation_#t~ret11 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 2466#L674 assume !(0 != start_simulation_~tmp___0~1); 2259#L642-1 [2019-11-20 10:36:37,340 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:37,340 INFO L82 PathProgramCache]: Analyzing trace with hash -126999211, now seen corresponding path program 1 times [2019-11-20 10:36:37,340 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:37,340 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1599999423] [2019-11-20 10:36:37,341 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:37,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:37,395 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 10:36:37,395 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1599999423] [2019-11-20 10:36:37,396 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 10:36:37,396 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 10:36:37,396 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [788757253] [2019-11-20 10:36:37,397 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-20 10:36:37,397 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:37,397 INFO L82 PathProgramCache]: Analyzing trace with hash -1195318037, now seen corresponding path program 1 times [2019-11-20 10:36:37,397 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:37,398 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1391138113] [2019-11-20 10:36:37,398 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:37,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:37,436 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 10:36:37,436 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1391138113] [2019-11-20 10:36:37,437 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 10:36:37,437 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 10:36:37,437 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [647001771] [2019-11-20 10:36:37,438 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-20 10:36:37,438 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 10:36:37,438 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 10:36:37,439 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 10:36:37,439 INFO L87 Difference]: Start difference. First operand 270 states and 398 transitions. cyclomatic complexity: 129 Second operand 3 states. [2019-11-20 10:36:37,514 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 10:36:37,514 INFO L93 Difference]: Finished difference Result 457 states and 666 transitions. [2019-11-20 10:36:37,515 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 10:36:37,515 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 457 states and 666 transitions. [2019-11-20 10:36:37,520 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 407 [2019-11-20 10:36:37,525 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 457 states to 457 states and 666 transitions. [2019-11-20 10:36:37,525 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 457 [2019-11-20 10:36:37,526 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 457 [2019-11-20 10:36:37,526 INFO L73 IsDeterministic]: Start isDeterministic. Operand 457 states and 666 transitions. [2019-11-20 10:36:37,528 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-20 10:36:37,528 INFO L688 BuchiCegarLoop]: Abstraction has 457 states and 666 transitions. [2019-11-20 10:36:37,529 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 457 states and 666 transitions. [2019-11-20 10:36:37,540 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 457 to 455. [2019-11-20 10:36:37,540 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 455 states. [2019-11-20 10:36:37,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 455 states to 455 states and 664 transitions. [2019-11-20 10:36:37,543 INFO L711 BuchiCegarLoop]: Abstraction has 455 states and 664 transitions. [2019-11-20 10:36:37,543 INFO L591 BuchiCegarLoop]: Abstraction has 455 states and 664 transitions. [2019-11-20 10:36:37,543 INFO L424 BuchiCegarLoop]: ======== Iteration 6============ [2019-11-20 10:36:37,543 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 455 states and 664 transitions. [2019-11-20 10:36:37,547 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 405 [2019-11-20 10:36:37,547 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-20 10:36:37,548 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-20 10:36:37,549 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:37,549 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:37,550 INFO L794 eck$LassoCheckResult]: Stem: 3094#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 2945#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2946#L605 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3088#L264 assume 1 == ~m_i~0;~m_st~0 := 0; 3089#L271-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3166#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3059#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3060#L286-1 assume !(0 == ~M_E~0); 3085#L408-1 assume !(0 == ~T1_E~0); 3048#L413-1 assume !(0 == ~T2_E~0); 3049#L418-1 assume !(0 == ~T3_E~0); 3110#L423-1 assume !(0 == ~E_1~0); 2977#L428-1 assume !(0 == ~E_2~0); 2978#L433-1 assume !(0 == ~E_3~0); 2985#L438-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3076#L187 assume !(1 == ~m_pc~0); 3077#L187-2 is_master_triggered_~__retres1~0 := 0; 3079#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3080#L199 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 3132#L500 assume !(0 != activate_threads_~tmp~1); 3133#L500-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3137#L206 assume !(1 == ~t1_pc~0); 3213#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 3214#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2987#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2988#L508 assume !(0 != activate_threads_~tmp___0~0); 3156#L508-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3138#L225 assume !(1 == ~t2_pc~0); 3051#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 3134#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3053#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2969#L516 assume !(0 != activate_threads_~tmp___1~0); 2970#L516-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2972#L244 assume 1 == ~t3_pc~0; 3205#L245 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3150#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3151#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3169#L524 assume !(0 != activate_threads_~tmp___2~0); 3170#L524-2 assume !(1 == ~M_E~0); 3106#L451-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3107#L456-1 assume !(1 == ~T2_E~0); 2973#L461-1 assume !(1 == ~T3_E~0); 2974#L466-1 assume !(1 == ~E_1~0); 2984#L471-1 assume !(1 == ~E_2~0); 3189#L476-1 assume !(1 == ~E_3~0); 3208#L642-1 [2019-11-20 10:36:37,550 INFO L796 eck$LassoCheckResult]: Loop: 3208#L642-1 assume !false; 2936#L643 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 2937#L383 assume !false; 3143#L332 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3144#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2952#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3145#L322 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 3061#L336 assume !(0 != eval_~tmp~0); 3063#L398 start_simulation_~kernel_st~0 := 2; 3081#L264-1 start_simulation_~kernel_st~0 := 3; 3082#L408-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3172#L408-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3065#L413-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3066#L418-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3116#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2947#L428-3 assume !(0 == ~E_2~0); 2948#L433-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2983#L438-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2999#L187-12 assume !(1 == ~m_pc~0); 3024#L187-14 is_master_triggered_~__retres1~0 := 0; 3057#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3098#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 3121#L500-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3122#L500-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3125#L206-12 assume !(1 == ~t1_pc~0); 3207#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 3353#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3352#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3219#L508-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3216#L508-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3119#L225-12 assume !(1 == ~t2_pc~0); 3090#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 3091#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3111#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2938#L516-12 assume !(0 != activate_threads_~tmp___1~0); 2939#L516-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2940#L244-12 assume !(1 == ~t3_pc~0); 3184#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 3183#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3185#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3161#L524-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3153#L524-14 assume 1 == ~M_E~0;~M_E~0 := 2; 3112#L451-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3113#L456-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2979#L461-3 assume !(1 == ~T3_E~0); 2980#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2986#L471-3 assume !(1 == ~E_2~0); 2993#L476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3200#L481-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3152#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2958#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3147#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 3031#L661 assume !(0 == start_simulation_~tmp~3); 3033#L661-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3365#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 3364#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3363#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 3362#L616 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3361#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 3360#L624 start_simulation_#t~ret11 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 3359#L674 assume !(0 != start_simulation_~tmp___0~1); 3208#L642-1 [2019-11-20 10:36:37,550 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:37,551 INFO L82 PathProgramCache]: Analyzing trace with hash -1717394188, now seen corresponding path program 1 times [2019-11-20 10:36:37,551 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:37,551 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [144861300] [2019-11-20 10:36:37,551 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:37,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:37,585 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 10:36:37,586 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [144861300] [2019-11-20 10:36:37,586 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 10:36:37,586 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 10:36:37,587 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [308818897] [2019-11-20 10:36:37,587 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-20 10:36:37,587 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:37,588 INFO L82 PathProgramCache]: Analyzing trace with hash 1828472237, now seen corresponding path program 1 times [2019-11-20 10:36:37,588 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:37,588 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2126542689] [2019-11-20 10:36:37,588 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:37,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:37,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 10:36:37,628 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2126542689] [2019-11-20 10:36:37,628 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 10:36:37,628 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 10:36:37,629 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1862943395] [2019-11-20 10:36:37,629 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-20 10:36:37,629 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 10:36:37,630 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 10:36:37,630 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 10:36:37,630 INFO L87 Difference]: Start difference. First operand 455 states and 664 transitions. cyclomatic complexity: 211 Second operand 3 states. [2019-11-20 10:36:37,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 10:36:37,693 INFO L93 Difference]: Finished difference Result 852 states and 1228 transitions. [2019-11-20 10:36:37,694 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 10:36:37,694 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 852 states and 1228 transitions. [2019-11-20 10:36:37,703 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 797 [2019-11-20 10:36:37,712 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 852 states to 852 states and 1228 transitions. [2019-11-20 10:36:37,713 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 852 [2019-11-20 10:36:37,714 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 852 [2019-11-20 10:36:37,714 INFO L73 IsDeterministic]: Start isDeterministic. Operand 852 states and 1228 transitions. [2019-11-20 10:36:37,716 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-20 10:36:37,716 INFO L688 BuchiCegarLoop]: Abstraction has 852 states and 1228 transitions. [2019-11-20 10:36:37,718 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 852 states and 1228 transitions. [2019-11-20 10:36:37,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 852 to 844. [2019-11-20 10:36:37,736 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 844 states. [2019-11-20 10:36:37,740 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 844 states to 844 states and 1218 transitions. [2019-11-20 10:36:37,740 INFO L711 BuchiCegarLoop]: Abstraction has 844 states and 1218 transitions. [2019-11-20 10:36:37,740 INFO L591 BuchiCegarLoop]: Abstraction has 844 states and 1218 transitions. [2019-11-20 10:36:37,741 INFO L424 BuchiCegarLoop]: ======== Iteration 7============ [2019-11-20 10:36:37,741 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 844 states and 1218 transitions. [2019-11-20 10:36:37,747 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 793 [2019-11-20 10:36:37,747 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-20 10:36:37,747 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-20 10:36:37,749 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:37,749 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:37,749 INFO L794 eck$LassoCheckResult]: Stem: 4408#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 4259#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 4260#L605 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4402#L264 assume 1 == ~m_i~0;~m_st~0 := 0; 4403#L271-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4484#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4373#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4374#L286-1 assume !(0 == ~M_E~0); 4401#L408-1 assume !(0 == ~T1_E~0); 4362#L413-1 assume !(0 == ~T2_E~0); 4363#L418-1 assume !(0 == ~T3_E~0); 4426#L423-1 assume !(0 == ~E_1~0); 4292#L428-1 assume !(0 == ~E_2~0); 4293#L433-1 assume !(0 == ~E_3~0); 4301#L438-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4390#L187 assume !(1 == ~m_pc~0); 4391#L187-2 is_master_triggered_~__retres1~0 := 0; 4393#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4394#L199 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 4450#L500 assume !(0 != activate_threads_~tmp~1); 4451#L500-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4454#L206 assume !(1 == ~t1_pc~0); 4538#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 4539#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4303#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 4304#L508 assume !(0 != activate_threads_~tmp___0~0); 4474#L508-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4455#L225 assume !(1 == ~t2_pc~0); 4365#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 4452#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4368#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4284#L516 assume !(0 != activate_threads_~tmp___1~0); 4285#L516-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4287#L244 assume !(1 == ~t3_pc~0); 4546#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 4468#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4469#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4489#L524 assume !(0 != activate_threads_~tmp___2~0); 4490#L524-2 assume !(1 == ~M_E~0); 4421#L451-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4422#L456-1 assume !(1 == ~T2_E~0); 4288#L461-1 assume !(1 == ~T3_E~0); 4289#L466-1 assume !(1 == ~E_1~0); 4300#L471-1 assume !(1 == ~E_2~0); 4513#L476-1 assume !(1 == ~E_3~0); 4305#L642-1 [2019-11-20 10:36:37,750 INFO L796 eck$LassoCheckResult]: Loop: 4305#L642-1 assume !false; 4250#L643 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 4251#L383 assume !false; 4461#L332 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 4462#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 4266#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 4463#L322 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 4375#L336 assume !(0 != eval_~tmp~0); 4377#L398 start_simulation_~kernel_st~0 := 2; 5078#L264-1 start_simulation_~kernel_st~0 := 3; 4980#L408-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4491#L408-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4379#L413-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4380#L418-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4432#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4261#L428-3 assume !(0 == ~E_2~0); 4262#L433-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4299#L438-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4314#L187-12 assume 1 == ~m_pc~0; 4338#L188-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 4372#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4413#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 4439#L500-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4440#L500-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4442#L206-12 assume !(1 == ~t1_pc~0); 4529#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 4530#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4318#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 4319#L508-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4542#L508-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4435#L225-12 assume !(1 == ~t2_pc~0); 4404#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 4405#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4427#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4252#L516-12 assume !(0 != activate_threads_~tmp___1~0); 4253#L516-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4254#L244-12 assume !(1 == ~t3_pc~0); 4533#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 4534#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4507#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4479#L524-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4471#L524-14 assume 1 == ~M_E~0;~M_E~0 := 2; 4428#L451-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4429#L456-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4294#L461-3 assume !(1 == ~T3_E~0); 4295#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4302#L471-3 assume !(1 == ~E_2~0); 4308#L476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4522#L481-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 4470#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 4272#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 4465#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 4346#L661 assume !(0 == start_simulation_~tmp~3); 4298#L661-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 4498#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 4279#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 4467#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 4437#L616 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4438#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 4493#L624 start_simulation_#t~ret11 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 4535#L674 assume !(0 != start_simulation_~tmp___0~1); 4305#L642-1 [2019-11-20 10:36:37,750 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:37,750 INFO L82 PathProgramCache]: Analyzing trace with hash 1289378579, now seen corresponding path program 1 times [2019-11-20 10:36:37,751 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:37,751 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [10970268] [2019-11-20 10:36:37,751 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:37,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:37,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 10:36:37,799 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [10970268] [2019-11-20 10:36:37,799 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 10:36:37,800 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 10:36:37,800 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1387676126] [2019-11-20 10:36:37,800 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-20 10:36:37,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:37,801 INFO L82 PathProgramCache]: Analyzing trace with hash -70058068, now seen corresponding path program 1 times [2019-11-20 10:36:37,801 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:37,801 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1713907076] [2019-11-20 10:36:37,801 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:37,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:37,861 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 10:36:37,861 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1713907076] [2019-11-20 10:36:37,862 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 10:36:37,862 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 10:36:37,862 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1785447598] [2019-11-20 10:36:37,862 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-20 10:36:37,863 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 10:36:37,868 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 10:36:37,868 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 10:36:37,869 INFO L87 Difference]: Start difference. First operand 844 states and 1218 transitions. cyclomatic complexity: 378 Second operand 3 states. [2019-11-20 10:36:37,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 10:36:37,900 INFO L93 Difference]: Finished difference Result 844 states and 1204 transitions. [2019-11-20 10:36:37,901 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 10:36:37,901 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 844 states and 1204 transitions. [2019-11-20 10:36:37,909 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 793 [2019-11-20 10:36:37,918 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 844 states to 844 states and 1204 transitions. [2019-11-20 10:36:37,918 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 844 [2019-11-20 10:36:37,919 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 844 [2019-11-20 10:36:37,920 INFO L73 IsDeterministic]: Start isDeterministic. Operand 844 states and 1204 transitions. [2019-11-20 10:36:37,922 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-20 10:36:37,922 INFO L688 BuchiCegarLoop]: Abstraction has 844 states and 1204 transitions. [2019-11-20 10:36:37,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 844 states and 1204 transitions. [2019-11-20 10:36:37,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 844 to 844. [2019-11-20 10:36:37,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 844 states. [2019-11-20 10:36:37,945 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 844 states to 844 states and 1204 transitions. [2019-11-20 10:36:37,945 INFO L711 BuchiCegarLoop]: Abstraction has 844 states and 1204 transitions. [2019-11-20 10:36:37,945 INFO L591 BuchiCegarLoop]: Abstraction has 844 states and 1204 transitions. [2019-11-20 10:36:37,945 INFO L424 BuchiCegarLoop]: ======== Iteration 8============ [2019-11-20 10:36:37,945 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 844 states and 1204 transitions. [2019-11-20 10:36:37,951 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 793 [2019-11-20 10:36:37,951 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-20 10:36:37,951 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-20 10:36:37,954 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:37,955 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:37,955 INFO L794 eck$LassoCheckResult]: Stem: 6103#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 5954#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 5955#L605 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6097#L264 assume 1 == ~m_i~0;~m_st~0 := 0; 6098#L271-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6180#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6067#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6068#L286-1 assume !(0 == ~M_E~0); 6094#L408-1 assume !(0 == ~T1_E~0); 6055#L413-1 assume !(0 == ~T2_E~0); 6056#L418-1 assume !(0 == ~T3_E~0); 6119#L423-1 assume !(0 == ~E_1~0); 5986#L428-1 assume !(0 == ~E_2~0); 5987#L433-1 assume !(0 == ~E_3~0); 5994#L438-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6085#L187 assume !(1 == ~m_pc~0); 6086#L187-2 is_master_triggered_~__retres1~0 := 0; 6088#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6089#L199 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 6142#L500 assume !(0 != activate_threads_~tmp~1); 6143#L500-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6146#L206 assume !(1 == ~t1_pc~0); 6227#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 6228#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5996#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 5997#L508 assume !(0 != activate_threads_~tmp___0~0); 6169#L508-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6147#L225 assume !(1 == ~t2_pc~0); 6058#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 6144#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6061#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 5978#L516 assume !(0 != activate_threads_~tmp___1~0); 5979#L516-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5981#L244 assume !(1 == ~t3_pc~0); 6235#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 6163#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6164#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6184#L524 assume !(0 != activate_threads_~tmp___2~0); 6185#L524-2 assume !(1 == ~M_E~0); 6115#L451-1 assume !(1 == ~T1_E~0); 6116#L456-1 assume !(1 == ~T2_E~0); 5982#L461-1 assume !(1 == ~T3_E~0); 5983#L466-1 assume !(1 == ~E_1~0); 5993#L471-1 assume !(1 == ~E_2~0); 6204#L476-1 assume !(1 == ~E_3~0); 5998#L642-1 [2019-11-20 10:36:37,955 INFO L796 eck$LassoCheckResult]: Loop: 5998#L642-1 assume !false; 5945#L643 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 5946#L383 assume !false; 6152#L332 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 6153#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 5961#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 6154#L322 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 6069#L336 assume !(0 != eval_~tmp~0); 6071#L398 start_simulation_~kernel_st~0 := 2; 6090#L264-1 start_simulation_~kernel_st~0 := 3; 6091#L408-2 assume 0 == ~M_E~0;~M_E~0 := 1; 6187#L408-4 assume !(0 == ~T1_E~0); 6073#L413-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6074#L418-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6126#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5956#L428-3 assume !(0 == ~E_2~0); 5957#L433-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5992#L438-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6007#L187-12 assume !(1 == ~m_pc~0); 6032#L187-14 is_master_triggered_~__retres1~0 := 0; 6065#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6107#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 6131#L500-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6132#L500-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6135#L206-12 assume !(1 == ~t1_pc~0); 6219#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 6732#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6731#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 6730#L508-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6729#L508-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6728#L225-12 assume !(1 == ~t2_pc~0); 6726#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 6725#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6724#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 6723#L516-12 assume !(0 != activate_threads_~tmp___1~0); 6722#L516-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6721#L244-12 assume !(1 == ~t3_pc~0); 6720#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 6719#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6718#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6717#L524-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6716#L524-14 assume 1 == ~M_E~0;~M_E~0 := 2; 6708#L451-3 assume !(1 == ~T1_E~0); 6707#L456-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6706#L461-3 assume !(1 == ~T3_E~0); 6705#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6704#L471-3 assume !(1 == ~E_2~0); 6703#L476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6701#L481-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 6697#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 6693#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 6692#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 6688#L661 assume !(0 == start_simulation_~tmp~3); 6689#L661-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 6740#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 6161#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 6162#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 6133#L616 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6134#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 6190#L624 start_simulation_#t~ret11 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 6223#L674 assume !(0 != start_simulation_~tmp___0~1); 5998#L642-1 [2019-11-20 10:36:37,955 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:37,955 INFO L82 PathProgramCache]: Analyzing trace with hash 1346636881, now seen corresponding path program 1 times [2019-11-20 10:36:37,956 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:37,957 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1989158126] [2019-11-20 10:36:37,958 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:37,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:37,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:38,010 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-20 10:36:38,011 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:38,011 INFO L82 PathProgramCache]: Analyzing trace with hash -341551763, now seen corresponding path program 1 times [2019-11-20 10:36:38,011 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:38,011 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [765639768] [2019-11-20 10:36:38,012 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:38,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:38,048 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 10:36:38,048 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [765639768] [2019-11-20 10:36:38,048 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 10:36:38,048 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 10:36:38,051 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [496974228] [2019-11-20 10:36:38,052 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-20 10:36:38,052 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 10:36:38,052 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 10:36:38,052 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 10:36:38,053 INFO L87 Difference]: Start difference. First operand 844 states and 1204 transitions. cyclomatic complexity: 364 Second operand 3 states. [2019-11-20 10:36:38,086 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 10:36:38,087 INFO L93 Difference]: Finished difference Result 1013 states and 1436 transitions. [2019-11-20 10:36:38,087 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 10:36:38,087 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1013 states and 1436 transitions. [2019-11-20 10:36:38,099 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 929 [2019-11-20 10:36:38,110 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1013 states to 1013 states and 1436 transitions. [2019-11-20 10:36:38,110 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1013 [2019-11-20 10:36:38,112 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1013 [2019-11-20 10:36:38,112 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1013 states and 1436 transitions. [2019-11-20 10:36:38,114 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-20 10:36:38,114 INFO L688 BuchiCegarLoop]: Abstraction has 1013 states and 1436 transitions. [2019-11-20 10:36:38,115 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1013 states and 1436 transitions. [2019-11-20 10:36:38,132 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1013 to 1013. [2019-11-20 10:36:38,133 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1013 states. [2019-11-20 10:36:38,138 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1013 states to 1013 states and 1436 transitions. [2019-11-20 10:36:38,138 INFO L711 BuchiCegarLoop]: Abstraction has 1013 states and 1436 transitions. [2019-11-20 10:36:38,138 INFO L591 BuchiCegarLoop]: Abstraction has 1013 states and 1436 transitions. [2019-11-20 10:36:38,138 INFO L424 BuchiCegarLoop]: ======== Iteration 9============ [2019-11-20 10:36:38,138 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1013 states and 1436 transitions. [2019-11-20 10:36:38,146 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 929 [2019-11-20 10:36:38,146 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-20 10:36:38,146 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-20 10:36:38,147 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:38,147 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:38,153 INFO L794 eck$LassoCheckResult]: Stem: 7970#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 7817#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 7818#L605 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7964#L264 assume 1 == ~m_i~0;~m_st~0 := 0; 7965#L271-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8057#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7935#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7936#L286-1 assume !(0 == ~M_E~0); 7961#L408-1 assume !(0 == ~T1_E~0); 7924#L413-1 assume !(0 == ~T2_E~0); 7925#L418-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7990#L423-1 assume !(0 == ~E_1~0); 8026#L428-1 assume !(0 == ~E_2~0); 8446#L433-1 assume !(0 == ~E_3~0); 8090#L438-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7952#L187 assume !(1 == ~m_pc~0); 7953#L187-2 is_master_triggered_~__retres1~0 := 0; 7981#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8431#L199 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 8427#L500 assume !(0 != activate_threads_~tmp~1); 8425#L500-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8424#L206 assume !(1 == ~t1_pc~0); 8423#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 8422#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8421#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 8045#L508 assume !(0 != activate_threads_~tmp___0~0); 8046#L508-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8023#L225 assume !(1 == ~t2_pc~0); 7927#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 8020#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7929#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 7842#L516 assume !(0 != activate_threads_~tmp___1~0); 7843#L516-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7846#L244 assume !(1 == ~t3_pc~0); 8117#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 8118#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8134#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 8060#L524 assume !(0 != activate_threads_~tmp___2~0); 8061#L524-2 assume !(1 == ~M_E~0); 7986#L451-1 assume !(1 == ~T1_E~0); 7987#L456-1 assume !(1 == ~T2_E~0); 7847#L461-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7848#L466-1 assume !(1 == ~E_1~0); 7858#L471-1 assume !(1 == ~E_2~0); 8083#L476-1 assume !(1 == ~E_3~0); 8105#L642-1 [2019-11-20 10:36:38,154 INFO L796 eck$LassoCheckResult]: Loop: 8105#L642-1 assume !false; 8377#L643 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 8320#L383 assume !false; 8376#L332 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 8369#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 8365#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 8362#L322 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 8359#L336 assume !(0 != eval_~tmp~0); 8360#L398 start_simulation_~kernel_st~0 := 2; 8789#L264-1 start_simulation_~kernel_st~0 := 3; 8788#L408-2 assume 0 == ~M_E~0;~M_E~0 := 1; 8787#L408-4 assume !(0 == ~T1_E~0); 7941#L413-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7942#L418-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7997#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8816#L428-3 assume !(0 == ~E_2~0); 8815#L433-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8814#L438-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7899#L187-12 assume 1 == ~m_pc~0; 7900#L188-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 7933#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8790#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 8791#L500-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8008#L500-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8009#L206-12 assume !(1 == ~t1_pc~0); 8808#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 8807#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7879#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 7880#L508-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 8113#L508-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8114#L225-12 assume !(1 == ~t2_pc~0); 7966#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 7967#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7992#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 7810#L516-12 assume !(0 != activate_threads_~tmp___1~0); 7811#L516-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7812#L244-12 assume !(1 == ~t3_pc~0); 8783#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 8782#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8781#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 8779#L524-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 8777#L524-14 assume 1 == ~M_E~0;~M_E~0 := 2; 8775#L451-3 assume !(1 == ~T1_E~0); 8027#L456-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7853#L461-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7854#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7867#L471-3 assume !(1 == ~E_2~0); 7868#L476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8095#L481-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 8041#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 7830#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 8035#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 7908#L661 assume !(0 == start_simulation_~tmp~3); 7856#L661-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 8391#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 8387#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 8386#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 8385#L616 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 8383#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 8382#L624 start_simulation_#t~ret11 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 8378#L674 assume !(0 != start_simulation_~tmp___0~1); 8105#L642-1 [2019-11-20 10:36:38,154 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:38,154 INFO L82 PathProgramCache]: Analyzing trace with hash -2104384495, now seen corresponding path program 1 times [2019-11-20 10:36:38,154 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:38,155 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1638018398] [2019-11-20 10:36:38,155 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:38,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:38,174 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 10:36:38,174 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1638018398] [2019-11-20 10:36:38,174 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 10:36:38,175 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 10:36:38,175 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [874024244] [2019-11-20 10:36:38,175 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-20 10:36:38,175 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:38,176 INFO L82 PathProgramCache]: Analyzing trace with hash -651734166, now seen corresponding path program 1 times [2019-11-20 10:36:38,176 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:38,176 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [267946517] [2019-11-20 10:36:38,176 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:38,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:38,230 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 10:36:38,230 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [267946517] [2019-11-20 10:36:38,230 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 10:36:38,230 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 10:36:38,231 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1832303005] [2019-11-20 10:36:38,231 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-20 10:36:38,231 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 10:36:38,231 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 10:36:38,232 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 10:36:38,232 INFO L87 Difference]: Start difference. First operand 1013 states and 1436 transitions. cyclomatic complexity: 427 Second operand 3 states. [2019-11-20 10:36:38,261 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 10:36:38,261 INFO L93 Difference]: Finished difference Result 844 states and 1190 transitions. [2019-11-20 10:36:38,262 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 10:36:38,262 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 844 states and 1190 transitions. [2019-11-20 10:36:38,270 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 793 [2019-11-20 10:36:38,278 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 844 states to 844 states and 1190 transitions. [2019-11-20 10:36:38,279 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 844 [2019-11-20 10:36:38,280 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 844 [2019-11-20 10:36:38,280 INFO L73 IsDeterministic]: Start isDeterministic. Operand 844 states and 1190 transitions. [2019-11-20 10:36:38,284 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-20 10:36:38,284 INFO L688 BuchiCegarLoop]: Abstraction has 844 states and 1190 transitions. [2019-11-20 10:36:38,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 844 states and 1190 transitions. [2019-11-20 10:36:38,300 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 844 to 844. [2019-11-20 10:36:38,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 844 states. [2019-11-20 10:36:38,304 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 844 states to 844 states and 1190 transitions. [2019-11-20 10:36:38,304 INFO L711 BuchiCegarLoop]: Abstraction has 844 states and 1190 transitions. [2019-11-20 10:36:38,304 INFO L591 BuchiCegarLoop]: Abstraction has 844 states and 1190 transitions. [2019-11-20 10:36:38,305 INFO L424 BuchiCegarLoop]: ======== Iteration 10============ [2019-11-20 10:36:38,305 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 844 states and 1190 transitions. [2019-11-20 10:36:38,311 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 793 [2019-11-20 10:36:38,311 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-20 10:36:38,313 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-20 10:36:38,314 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:38,314 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:38,315 INFO L794 eck$LassoCheckResult]: Stem: 9832#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 9683#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 9684#L605 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9826#L264 assume 1 == ~m_i~0;~m_st~0 := 0; 9827#L271-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9909#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9796#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9797#L286-1 assume !(0 == ~M_E~0); 9823#L408-1 assume !(0 == ~T1_E~0); 9784#L413-1 assume !(0 == ~T2_E~0); 9785#L418-1 assume !(0 == ~T3_E~0); 9848#L423-1 assume !(0 == ~E_1~0); 9715#L428-1 assume !(0 == ~E_2~0); 9716#L433-1 assume !(0 == ~E_3~0); 9723#L438-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9814#L187 assume !(1 == ~m_pc~0); 9815#L187-2 is_master_triggered_~__retres1~0 := 0; 9817#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9818#L199 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 9871#L500 assume !(0 != activate_threads_~tmp~1); 9872#L500-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9875#L206 assume !(1 == ~t1_pc~0); 9956#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 9957#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9725#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 9726#L508 assume !(0 != activate_threads_~tmp___0~0); 9898#L508-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9876#L225 assume !(1 == ~t2_pc~0); 9787#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 9873#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9790#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 9707#L516 assume !(0 != activate_threads_~tmp___1~0); 9708#L516-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9710#L244 assume !(1 == ~t3_pc~0); 9964#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 9892#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9893#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 9913#L524 assume !(0 != activate_threads_~tmp___2~0); 9914#L524-2 assume !(1 == ~M_E~0); 9844#L451-1 assume !(1 == ~T1_E~0); 9845#L456-1 assume !(1 == ~T2_E~0); 9711#L461-1 assume !(1 == ~T3_E~0); 9712#L466-1 assume !(1 == ~E_1~0); 9722#L471-1 assume !(1 == ~E_2~0); 9933#L476-1 assume !(1 == ~E_3~0); 9727#L642-1 [2019-11-20 10:36:38,315 INFO L796 eck$LassoCheckResult]: Loop: 9727#L642-1 assume !false; 9674#L643 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 9675#L383 assume !false; 9881#L332 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 9882#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 9690#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 9883#L322 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 9798#L336 assume !(0 != eval_~tmp~0); 9800#L398 start_simulation_~kernel_st~0 := 2; 9819#L264-1 start_simulation_~kernel_st~0 := 3; 9820#L408-2 assume 0 == ~M_E~0;~M_E~0 := 1; 9916#L408-4 assume !(0 == ~T1_E~0); 9802#L413-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9803#L418-3 assume !(0 == ~T3_E~0); 9855#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9685#L428-3 assume !(0 == ~E_2~0); 9686#L433-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9721#L438-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9736#L187-12 assume 1 == ~m_pc~0; 9760#L188-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 9794#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9836#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 9860#L500-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 9861#L500-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9864#L206-12 assume !(1 == ~t1_pc~0); 9948#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 10461#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10460#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 10459#L508-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10458#L508-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10457#L225-12 assume !(1 == ~t2_pc~0); 10455#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 10454#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10453#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 10452#L516-12 assume !(0 != activate_threads_~tmp___1~0); 10451#L516-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10450#L244-12 assume !(1 == ~t3_pc~0); 10449#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 10448#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10447#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 10446#L524-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 10445#L524-14 assume 1 == ~M_E~0;~M_E~0 := 2; 10437#L451-3 assume !(1 == ~T1_E~0); 10436#L456-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10435#L461-3 assume !(1 == ~T3_E~0); 10434#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10433#L471-3 assume !(1 == ~E_2~0); 10432#L476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10430#L481-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 10426#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 10422#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 10421#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 10417#L661 assume !(0 == start_simulation_~tmp~3); 10418#L661-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 10469#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 9890#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 9891#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 9862#L616 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9863#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 9919#L624 start_simulation_#t~ret11 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 9952#L674 assume !(0 != start_simulation_~tmp___0~1); 9727#L642-1 [2019-11-20 10:36:38,316 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:38,316 INFO L82 PathProgramCache]: Analyzing trace with hash 1346636881, now seen corresponding path program 2 times [2019-11-20 10:36:38,316 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:38,317 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [310061719] [2019-11-20 10:36:38,317 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:38,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:38,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:38,341 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-20 10:36:38,342 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:38,342 INFO L82 PathProgramCache]: Analyzing trace with hash -300920022, now seen corresponding path program 1 times [2019-11-20 10:36:38,343 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:38,343 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1104635028] [2019-11-20 10:36:38,343 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:38,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:38,404 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 10:36:38,405 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1104635028] [2019-11-20 10:36:38,405 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 10:36:38,405 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 10:36:38,406 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [245245920] [2019-11-20 10:36:38,406 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-20 10:36:38,406 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 10:36:38,406 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 10:36:38,407 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 10:36:38,407 INFO L87 Difference]: Start difference. First operand 844 states and 1190 transitions. cyclomatic complexity: 350 Second operand 5 states. [2019-11-20 10:36:38,596 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 10:36:38,596 INFO L93 Difference]: Finished difference Result 1457 states and 2029 transitions. [2019-11-20 10:36:38,597 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-11-20 10:36:38,597 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1457 states and 2029 transitions. [2019-11-20 10:36:38,610 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1402 [2019-11-20 10:36:38,622 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1457 states to 1457 states and 2029 transitions. [2019-11-20 10:36:38,623 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1457 [2019-11-20 10:36:38,626 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1457 [2019-11-20 10:36:38,627 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1457 states and 2029 transitions. [2019-11-20 10:36:38,630 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-20 10:36:38,630 INFO L688 BuchiCegarLoop]: Abstraction has 1457 states and 2029 transitions. [2019-11-20 10:36:38,632 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1457 states and 2029 transitions. [2019-11-20 10:36:38,648 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1457 to 856. [2019-11-20 10:36:38,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 856 states. [2019-11-20 10:36:38,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 856 states to 856 states and 1202 transitions. [2019-11-20 10:36:38,652 INFO L711 BuchiCegarLoop]: Abstraction has 856 states and 1202 transitions. [2019-11-20 10:36:38,652 INFO L591 BuchiCegarLoop]: Abstraction has 856 states and 1202 transitions. [2019-11-20 10:36:38,652 INFO L424 BuchiCegarLoop]: ======== Iteration 11============ [2019-11-20 10:36:38,653 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 856 states and 1202 transitions. [2019-11-20 10:36:38,658 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 805 [2019-11-20 10:36:38,658 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-20 10:36:38,658 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-20 10:36:38,665 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:38,665 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:38,665 INFO L794 eck$LassoCheckResult]: Stem: 12151#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 12001#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 12002#L605 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12145#L264 assume 1 == ~m_i~0;~m_st~0 := 0; 12146#L271-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12238#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12117#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12118#L286-1 assume !(0 == ~M_E~0); 12142#L408-1 assume !(0 == ~T1_E~0); 12106#L413-1 assume !(0 == ~T2_E~0); 12107#L418-1 assume !(0 == ~T3_E~0); 12169#L423-1 assume !(0 == ~E_1~0); 12033#L428-1 assume !(0 == ~E_2~0); 12034#L433-1 assume !(0 == ~E_3~0); 12041#L438-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12133#L187 assume !(1 == ~m_pc~0); 12134#L187-2 is_master_triggered_~__retres1~0 := 0; 12136#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12137#L199 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 12196#L500 assume !(0 != activate_threads_~tmp~1); 12197#L500-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12201#L206 assume !(1 == ~t1_pc~0); 12303#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 12304#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12044#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 12045#L508 assume !(0 != activate_threads_~tmp___0~0); 12227#L508-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12202#L225 assume !(1 == ~t2_pc~0); 12109#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 12198#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12111#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 12025#L516 assume !(0 != activate_threads_~tmp___1~0); 12026#L516-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12028#L244 assume !(1 == ~t3_pc~0); 12314#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 12220#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12221#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 12243#L524 assume !(0 != activate_threads_~tmp___2~0); 12244#L524-2 assume !(1 == ~M_E~0); 12163#L451-1 assume !(1 == ~T1_E~0); 12164#L456-1 assume !(1 == ~T2_E~0); 12029#L461-1 assume !(1 == ~T3_E~0); 12030#L466-1 assume !(1 == ~E_1~0); 12040#L471-1 assume !(1 == ~E_2~0); 12267#L476-1 assume !(1 == ~E_3~0); 12046#L642-1 [2019-11-20 10:36:38,665 INFO L796 eck$LassoCheckResult]: Loop: 12046#L642-1 assume !false; 11991#L643 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 11992#L383 assume !false; 12465#L332 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 12460#L299 assume !(0 == ~m_st~0); 12455#L303 assume !(0 == ~t1_st~0); 12449#L307 assume !(0 == ~t2_st~0); 12444#L311 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 12440#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 12437#L322 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 12434#L336 assume !(0 != eval_~tmp~0); 12432#L398 start_simulation_~kernel_st~0 := 2; 12430#L264-1 start_simulation_~kernel_st~0 := 3; 12428#L408-2 assume 0 == ~M_E~0;~M_E~0 := 1; 12426#L408-4 assume !(0 == ~T1_E~0); 12424#L413-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12423#L418-3 assume !(0 == ~T3_E~0); 12421#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12419#L428-3 assume !(0 == ~E_2~0); 12401#L433-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12399#L438-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12398#L187-12 assume 1 == ~m_pc~0; 12396#L188-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 12395#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12394#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 12183#L500-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 12184#L500-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12289#L206-12 assume !(1 == ~t1_pc~0); 12287#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 12288#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12060#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 12061#L508-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 12309#L508-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12310#L225-12 assume !(1 == ~t2_pc~0); 12147#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 12148#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12251#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 12252#L516-12 assume !(0 != activate_threads_~tmp___1~0); 11995#L516-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11996#L244-12 assume !(1 == ~t3_pc~0); 12292#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 12293#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12262#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 12263#L524-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 12223#L524-14 assume 1 == ~M_E~0;~M_E~0 := 2; 12224#L451-3 assume !(1 == ~T1_E~0); 12205#L456-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12206#L461-3 assume !(1 == ~T3_E~0); 12042#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12043#L471-3 assume !(1 == ~E_2~0); 12280#L476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12281#L481-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 12222#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 12014#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 12217#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 12089#L661 assume !(0 == start_simulation_~tmp~3); 12091#L661-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 12316#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 12020#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 12219#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 12185#L616 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 12186#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 12249#L624 start_simulation_#t~ret11 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 12294#L674 assume !(0 != start_simulation_~tmp___0~1); 12046#L642-1 [2019-11-20 10:36:38,666 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:38,666 INFO L82 PathProgramCache]: Analyzing trace with hash 1346636881, now seen corresponding path program 3 times [2019-11-20 10:36:38,666 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:38,667 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [311845674] [2019-11-20 10:36:38,667 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:38,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:38,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:38,704 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-20 10:36:38,704 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:38,705 INFO L82 PathProgramCache]: Analyzing trace with hash -1831693836, now seen corresponding path program 1 times [2019-11-20 10:36:38,705 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:38,705 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [842393424] [2019-11-20 10:36:38,705 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:38,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:38,790 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 10:36:38,790 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [842393424] [2019-11-20 10:36:38,790 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 10:36:38,791 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 10:36:38,791 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [267356850] [2019-11-20 10:36:38,791 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-20 10:36:38,791 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 10:36:38,792 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 10:36:38,792 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 10:36:38,792 INFO L87 Difference]: Start difference. First operand 856 states and 1202 transitions. cyclomatic complexity: 350 Second operand 5 states. [2019-11-20 10:36:39,010 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 10:36:39,011 INFO L93 Difference]: Finished difference Result 1574 states and 2191 transitions. [2019-11-20 10:36:39,011 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 10:36:39,011 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1574 states and 2191 transitions. [2019-11-20 10:36:39,024 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1523 [2019-11-20 10:36:39,038 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1574 states to 1574 states and 2191 transitions. [2019-11-20 10:36:39,038 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1574 [2019-11-20 10:36:39,040 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1574 [2019-11-20 10:36:39,040 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1574 states and 2191 transitions. [2019-11-20 10:36:39,043 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-20 10:36:39,043 INFO L688 BuchiCegarLoop]: Abstraction has 1574 states and 2191 transitions. [2019-11-20 10:36:39,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1574 states and 2191 transitions. [2019-11-20 10:36:39,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1574 to 886. [2019-11-20 10:36:39,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 886 states. [2019-11-20 10:36:39,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 886 states to 886 states and 1223 transitions. [2019-11-20 10:36:39,067 INFO L711 BuchiCegarLoop]: Abstraction has 886 states and 1223 transitions. [2019-11-20 10:36:39,067 INFO L591 BuchiCegarLoop]: Abstraction has 886 states and 1223 transitions. [2019-11-20 10:36:39,067 INFO L424 BuchiCegarLoop]: ======== Iteration 12============ [2019-11-20 10:36:39,068 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 886 states and 1223 transitions. [2019-11-20 10:36:39,072 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 835 [2019-11-20 10:36:39,073 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-20 10:36:39,073 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-20 10:36:39,074 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:39,074 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:39,074 INFO L794 eck$LassoCheckResult]: Stem: 14594#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 14444#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 14445#L605 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 14588#L264 assume 1 == ~m_i~0;~m_st~0 := 0; 14589#L271-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14674#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14560#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14561#L286-1 assume !(0 == ~M_E~0); 14585#L408-1 assume !(0 == ~T1_E~0); 14549#L413-1 assume !(0 == ~T2_E~0); 14550#L418-1 assume !(0 == ~T3_E~0); 14612#L423-1 assume !(0 == ~E_1~0); 14476#L428-1 assume !(0 == ~E_2~0); 14477#L433-1 assume !(0 == ~E_3~0); 14484#L438-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14576#L187 assume !(1 == ~m_pc~0); 14577#L187-2 is_master_triggered_~__retres1~0 := 0; 14579#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14580#L199 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 14635#L500 assume !(0 != activate_threads_~tmp~1); 14636#L500-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14639#L206 assume !(1 == ~t1_pc~0); 14739#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 14740#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14487#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 14488#L508 assume !(0 != activate_threads_~tmp___0~0); 14664#L508-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14640#L225 assume !(1 == ~t2_pc~0); 14552#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 14637#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14554#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 14468#L516 assume !(0 != activate_threads_~tmp___1~0); 14469#L516-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14471#L244 assume !(1 == ~t3_pc~0); 14748#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 14658#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14659#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 14679#L524 assume !(0 != activate_threads_~tmp___2~0); 14680#L524-2 assume !(1 == ~M_E~0); 14607#L451-1 assume !(1 == ~T1_E~0); 14608#L456-1 assume !(1 == ~T2_E~0); 14472#L461-1 assume !(1 == ~T3_E~0); 14473#L466-1 assume !(1 == ~E_1~0); 14483#L471-1 assume !(1 == ~E_2~0); 14699#L476-1 assume !(1 == ~E_3~0); 14728#L642-1 [2019-11-20 10:36:39,074 INFO L796 eck$LassoCheckResult]: Loop: 14728#L642-1 assume !false; 14838#L643 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 14822#L383 assume !false; 14823#L332 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 14819#L299 assume !(0 == ~m_st~0); 14818#L303 assume !(0 == ~t1_st~0); 14817#L307 assume !(0 == ~t2_st~0); 14815#L311 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 14813#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 14814#L322 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 14809#L336 assume !(0 != eval_~tmp~0); 14807#L398 start_simulation_~kernel_st~0 := 2; 14808#L264-1 start_simulation_~kernel_st~0 := 3; 14803#L408-2 assume 0 == ~M_E~0;~M_E~0 := 1; 14804#L408-4 assume !(0 == ~T1_E~0); 14799#L413-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14800#L418-3 assume !(0 == ~T3_E~0); 14795#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14796#L428-3 assume !(0 == ~E_2~0); 14791#L433-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14792#L438-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14786#L187-12 assume 1 == ~m_pc~0; 14787#L188-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 14781#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14782#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 14623#L500-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 14624#L500-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14627#L206-12 assume !(1 == ~t1_pc~0); 15112#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 15110#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15107#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 15105#L508-12 assume !(0 != activate_threads_~tmp___0~0); 15103#L508-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15101#L225-12 assume !(1 == ~t2_pc~0); 15098#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 15096#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15094#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 15091#L516-12 assume !(0 != activate_threads_~tmp___1~0); 15089#L516-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15087#L244-12 assume !(1 == ~t3_pc~0); 15084#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 15081#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15078#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 15073#L524-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 15067#L524-14 assume 1 == ~M_E~0;~M_E~0 := 2; 15064#L451-3 assume !(1 == ~T1_E~0); 15061#L456-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15058#L461-3 assume !(1 == ~T3_E~0); 15056#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15037#L471-3 assume !(1 == ~E_2~0); 15030#L476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15026#L481-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 15000#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 14991#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 14986#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 14972#L661 assume !(0 == start_simulation_~tmp~3); 14966#L661-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 14959#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 14954#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 14953#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 14889#L616 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 14890#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 14862#L624 start_simulation_#t~ret11 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 14863#L674 assume !(0 != start_simulation_~tmp___0~1); 14728#L642-1 [2019-11-20 10:36:39,074 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:39,075 INFO L82 PathProgramCache]: Analyzing trace with hash 1346636881, now seen corresponding path program 4 times [2019-11-20 10:36:39,075 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:39,075 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1094078267] [2019-11-20 10:36:39,075 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:39,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:39,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:39,090 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-20 10:36:39,090 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:39,091 INFO L82 PathProgramCache]: Analyzing trace with hash -1904080394, now seen corresponding path program 1 times [2019-11-20 10:36:39,091 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:39,091 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [514404381] [2019-11-20 10:36:39,091 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:39,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:39,140 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 10:36:39,140 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [514404381] [2019-11-20 10:36:39,140 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 10:36:39,141 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-20 10:36:39,141 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1668454845] [2019-11-20 10:36:39,141 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-20 10:36:39,141 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 10:36:39,141 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-20 10:36:39,142 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-20 10:36:39,142 INFO L87 Difference]: Start difference. First operand 886 states and 1223 transitions. cyclomatic complexity: 341 Second operand 5 states. [2019-11-20 10:36:39,305 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 10:36:39,305 INFO L93 Difference]: Finished difference Result 1461 states and 2015 transitions. [2019-11-20 10:36:39,306 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-20 10:36:39,306 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1461 states and 2015 transitions. [2019-11-20 10:36:39,316 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1406 [2019-11-20 10:36:39,327 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1461 states to 1461 states and 2015 transitions. [2019-11-20 10:36:39,327 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1461 [2019-11-20 10:36:39,329 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1461 [2019-11-20 10:36:39,329 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1461 states and 2015 transitions. [2019-11-20 10:36:39,331 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-20 10:36:39,332 INFO L688 BuchiCegarLoop]: Abstraction has 1461 states and 2015 transitions. [2019-11-20 10:36:39,333 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1461 states and 2015 transitions. [2019-11-20 10:36:39,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1461 to 913. [2019-11-20 10:36:39,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 913 states. [2019-11-20 10:36:39,363 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 913 states to 913 states and 1240 transitions. [2019-11-20 10:36:39,363 INFO L711 BuchiCegarLoop]: Abstraction has 913 states and 1240 transitions. [2019-11-20 10:36:39,363 INFO L591 BuchiCegarLoop]: Abstraction has 913 states and 1240 transitions. [2019-11-20 10:36:39,363 INFO L424 BuchiCegarLoop]: ======== Iteration 13============ [2019-11-20 10:36:39,363 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 913 states and 1240 transitions. [2019-11-20 10:36:39,369 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 862 [2019-11-20 10:36:39,369 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-20 10:36:39,369 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-20 10:36:39,370 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:39,370 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:39,370 INFO L794 eck$LassoCheckResult]: Stem: 16957#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 16805#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 16806#L605 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 16951#L264 assume 1 == ~m_i~0;~m_st~0 := 0; 16952#L271-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17035#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16922#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16923#L286-1 assume !(0 == ~M_E~0); 16950#L408-1 assume !(0 == ~T1_E~0); 16911#L413-1 assume !(0 == ~T2_E~0); 16912#L418-1 assume !(0 == ~T3_E~0); 16973#L423-1 assume !(0 == ~E_1~0); 16839#L428-1 assume !(0 == ~E_2~0); 16840#L433-1 assume !(0 == ~E_3~0); 16849#L438-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16938#L187 assume !(1 == ~m_pc~0); 16939#L187-2 is_master_triggered_~__retres1~0 := 0; 16941#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16942#L199 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 16996#L500 assume !(0 != activate_threads_~tmp~1); 16997#L500-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17001#L206 assume !(1 == ~t1_pc~0); 17092#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 17093#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16851#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 16852#L508 assume !(0 != activate_threads_~tmp___0~0); 17024#L508-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 17002#L225 assume !(1 == ~t2_pc~0); 16914#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 16998#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16918#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 16831#L516 assume !(0 != activate_threads_~tmp___1~0); 16832#L516-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16834#L244 assume !(1 == ~t3_pc~0); 17103#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 17018#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 17019#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 17039#L524 assume !(0 != activate_threads_~tmp___2~0); 17040#L524-2 assume !(1 == ~M_E~0); 16969#L451-1 assume !(1 == ~T1_E~0); 16970#L456-1 assume !(1 == ~T2_E~0); 16835#L461-1 assume !(1 == ~T3_E~0); 16836#L466-1 assume !(1 == ~E_1~0); 16848#L471-1 assume !(1 == ~E_2~0); 17060#L476-1 assume !(1 == ~E_3~0); 17083#L642-1 [2019-11-20 10:36:39,371 INFO L796 eck$LassoCheckResult]: Loop: 17083#L642-1 assume !false; 17485#L643 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 17482#L383 assume !false; 17481#L332 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 17479#L299 assume !(0 == ~m_st~0); 17480#L303 assume !(0 == ~t1_st~0); 17476#L307 assume !(0 == ~t2_st~0); 17478#L311 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 17474#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 17470#L322 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 17471#L336 assume !(0 != eval_~tmp~0); 17648#L398 start_simulation_~kernel_st~0 := 2; 17647#L264-1 start_simulation_~kernel_st~0 := 3; 17646#L408-2 assume 0 == ~M_E~0;~M_E~0 := 1; 17645#L408-4 assume !(0 == ~T1_E~0); 17644#L413-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17643#L418-3 assume !(0 == ~T3_E~0); 17642#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17641#L428-3 assume !(0 == ~E_2~0); 17640#L433-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17639#L438-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17638#L187-12 assume 1 == ~m_pc~0; 17636#L188-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 17635#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17634#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 17633#L500-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 17631#L500-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17082#L206-12 assume !(1 == ~t1_pc~0); 17080#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 17081#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16866#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 16867#L508-12 assume !(0 != activate_threads_~tmp___0~0); 17096#L508-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16983#L225-12 assume !(1 == ~t2_pc~0); 16953#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 16954#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16974#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 16798#L516-12 assume !(0 != activate_threads_~tmp___1~0); 16799#L516-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16800#L244-12 assume !(1 == ~t3_pc~0); 17088#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 17430#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 17429#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 17428#L524-12 assume !(0 != activate_threads_~tmp___2~0); 17427#L524-14 assume 1 == ~M_E~0;~M_E~0 := 2; 17426#L451-3 assume !(1 == ~T1_E~0); 17425#L456-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17424#L461-3 assume !(1 == ~T3_E~0); 17423#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17422#L471-3 assume !(1 == ~E_2~0); 17421#L476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17420#L481-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 17418#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 17415#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 17414#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 17412#L661 assume !(0 == start_simulation_~tmp~3); 17413#L661-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 17497#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 17496#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 17495#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 17493#L616 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 17491#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 17489#L624 start_simulation_#t~ret11 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 17487#L674 assume !(0 != start_simulation_~tmp___0~1); 17083#L642-1 [2019-11-20 10:36:39,371 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:39,371 INFO L82 PathProgramCache]: Analyzing trace with hash 1346636881, now seen corresponding path program 5 times [2019-11-20 10:36:39,371 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:39,371 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [419616716] [2019-11-20 10:36:39,371 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:39,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:39,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:39,387 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-20 10:36:39,387 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:39,387 INFO L82 PathProgramCache]: Analyzing trace with hash -1481378568, now seen corresponding path program 1 times [2019-11-20 10:36:39,387 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:39,388 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [648842555] [2019-11-20 10:36:39,388 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:39,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:39,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:39,411 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-20 10:36:39,411 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:39,412 INFO L82 PathProgramCache]: Analyzing trace with hash 493715784, now seen corresponding path program 1 times [2019-11-20 10:36:39,412 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:39,412 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1353773887] [2019-11-20 10:36:39,412 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:39,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:39,450 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 10:36:39,450 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1353773887] [2019-11-20 10:36:39,450 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 10:36:39,451 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 10:36:39,451 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [845773022] [2019-11-20 10:36:40,199 WARN L191 SmtUtils]: Spent 739.00 ms on a formula simplification. DAG size of input: 134 DAG size of output: 123 [2019-11-20 10:36:40,412 WARN L191 SmtUtils]: Spent 201.00 ms on a formula simplification that was a NOOP. DAG size: 103 [2019-11-20 10:36:40,425 INFO L210 LassoAnalysis]: Preferences: [2019-11-20 10:36:40,425 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2019-11-20 10:36:40,426 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-11-20 10:36:40,426 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2019-11-20 10:36:40,426 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2019-11-20 10:36:40,426 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:40,426 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2019-11-20 10:36:40,426 INFO L132 ssoRankerPreferences]: Path of dumped script: [2019-11-20 10:36:40,426 INFO L133 ssoRankerPreferences]: Filename of dumped script: transmitter.03.cil.c_Iteration13_Loop [2019-11-20 10:36:40,427 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2019-11-20 10:36:40,427 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-11-20 10:36:40,460 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,473 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,477 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,484 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,487 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,490 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,492 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,497 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,500 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,504 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,513 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,516 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,520 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,530 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,534 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,542 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,545 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,553 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,561 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,575 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,578 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,585 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,589 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,592 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,600 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,603 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,607 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,611 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,615 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,620 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,630 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,637 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,647 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,651 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,654 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,657 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,661 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,665 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,667 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,676 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,679 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,682 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:40,685 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,313 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-11-20 10:36:41,314 INFO L404 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:41,323 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-20 10:36:41,323 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:41,349 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-20 10:36:41,350 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit2_triggered_#res=0, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=0} Honda state: {ULTIMATE.start_is_transmit2_triggered_#res=0, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:41,377 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-20 10:36:41,377 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:41,389 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-20 10:36:41,389 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~kernel_st~0=3} Honda state: {ULTIMATE.start_start_simulation_~kernel_st~0=3} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:41,406 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-20 10:36:41,406 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:41,412 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-20 10:36:41,412 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t2_st~0=7} Honda state: {~t2_st~0=7} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:41,432 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-20 10:36:41,432 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:41,443 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-20 10:36:41,444 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret5=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret5=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:41,462 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-20 10:36:41,462 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:41,472 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-20 10:36:41,472 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_3~0=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_3~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:41,491 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-20 10:36:41,491 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-11-20 10:36:41,497 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-20 10:36:41,497 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret10=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret10=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:41,509 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-20 10:36:41,510 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-11-20 10:36:41,518 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-20 10:36:41,518 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_pc~0=-8} Honda state: {~t1_pc~0=-8} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:41,621 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-20 10:36:41,621 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:41,627 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-20 10:36:41,627 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret11=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret11=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:41,643 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-20 10:36:41,643 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:41,649 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-20 10:36:41,649 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t3_pc~0=-8} Honda state: {~t3_pc~0=-8} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:41,666 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-20 10:36:41,666 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:41,688 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2019-11-20 10:36:41,688 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:41,694 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2019-11-20 10:36:41,697 INFO L210 LassoAnalysis]: Preferences: [2019-11-20 10:36:41,697 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2019-11-20 10:36:41,697 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-11-20 10:36:41,697 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2019-11-20 10:36:41,697 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2019-11-20 10:36:41,697 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:41,698 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2019-11-20 10:36:41,698 INFO L132 ssoRankerPreferences]: Path of dumped script: [2019-11-20 10:36:41,698 INFO L133 ssoRankerPreferences]: Filename of dumped script: transmitter.03.cil.c_Iteration13_Loop [2019-11-20 10:36:41,698 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2019-11-20 10:36:41,698 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-11-20 10:36:41,702 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,706 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,714 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,716 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,719 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,722 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,725 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,728 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,731 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,740 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,743 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,745 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,752 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,756 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,773 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,779 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,785 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,787 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,794 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,796 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,800 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,807 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,815 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,818 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,835 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,839 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,844 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,848 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,857 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,883 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,886 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,895 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,901 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,905 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,908 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,923 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,927 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,931 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,934 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,937 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,945 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,949 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:41,953 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:42,623 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-11-20 10:36:42,631 INFO L489 LassoAnalysis]: Using template 'affine'. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:42,641 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-20 10:36:42,644 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-20 10:36:42,644 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-20 10:36:42,645 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-20 10:36:42,645 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-20 10:36:42,645 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-20 10:36:42,648 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-20 10:36:42,649 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-20 10:36:42,652 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:42,661 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-20 10:36:42,663 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-20 10:36:42,663 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-20 10:36:42,664 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-20 10:36:42,664 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2019-11-20 10:36:42,664 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. Waiting until toolchain timeout for monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:42,665 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2019-11-20 10:36:42,665 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-20 10:36:42,668 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:42,677 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-20 10:36:42,679 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-20 10:36:42,679 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-20 10:36:42,680 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-20 10:36:42,680 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-20 10:36:42,680 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-20 10:36:42,681 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-20 10:36:42,681 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-20 10:36:42,683 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:42,693 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-20 10:36:42,695 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-20 10:36:42,695 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-20 10:36:42,695 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-20 10:36:42,696 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-20 10:36:42,696 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-20 10:36:42,696 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-20 10:36:42,697 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-20 10:36:42,702 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 17 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:42,716 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-20 10:36:42,718 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-20 10:36:42,719 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-20 10:36:42,719 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-20 10:36:42,719 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-20 10:36:42,719 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-20 10:36:42,720 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-20 10:36:42,721 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. Waiting until toolchain timeout for monitored process 17 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:42,725 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 18 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:42,738 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-20 10:36:42,740 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-20 10:36:42,740 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-20 10:36:42,740 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-20 10:36:42,740 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2019-11-20 10:36:42,740 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-20 10:36:42,742 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2019-11-20 10:36:42,742 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-20 10:36:42,744 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 19 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:42,762 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-20 10:36:42,763 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-20 10:36:42,764 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-20 10:36:42,764 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-20 10:36:42,764 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-20 10:36:42,764 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-20 10:36:42,765 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-20 10:36:42,765 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-20 10:36:42,769 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 20 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:42,782 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-20 10:36:42,784 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-20 10:36:42,784 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-20 10:36:42,784 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-20 10:36:42,784 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2019-11-20 10:36:42,784 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-20 10:36:42,792 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2019-11-20 10:36:42,792 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-20 10:36:42,795 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 21 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:42,809 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-20 10:36:42,812 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-20 10:36:42,812 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-20 10:36:42,812 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-20 10:36:42,812 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-20 10:36:42,812 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-20 10:36:42,814 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-20 10:36:42,814 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-20 10:36:42,821 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2019-11-20 10:36:42,829 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2019-11-20 10:36:42,829 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 22 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:42,846 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2019-11-20 10:36:42,846 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2019-11-20 10:36:42,846 INFO L510 LassoAnalysis]: Proved termination. [2019-11-20 10:36:42,847 INFO L512 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_3~0) = -1*~E_3~0 + 1 Supporting invariants [] Waiting until toolchain timeout for monitored process 22 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:42,852 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2019-11-20 10:36:42,926 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:42,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:42,957 INFO L255 TraceCheckSpWp]: Trace formula consists of 120 conjuncts, 2 conjunts are in the unsatisfiable core [2019-11-20 10:36:42,960 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 10:36:42,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:42,998 INFO L255 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 4 conjunts are in the unsatisfiable core [2019-11-20 10:36:43,000 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 10:36:43,042 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 10:36:43,047 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2019-11-20 10:36:43,047 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 913 states and 1240 transitions. cyclomatic complexity: 331 Second operand 5 states. [2019-11-20 10:36:43,222 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 913 states and 1240 transitions. cyclomatic complexity: 331. Second operand 5 states. Result 3297 states and 4508 transitions. Complement of second has 5 states. [2019-11-20 10:36:43,222 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2019-11-20 10:36:43,223 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2019-11-20 10:36:43,225 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 663 transitions. [2019-11-20 10:36:43,226 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 663 transitions. Stem has 45 letters. Loop has 64 letters. [2019-11-20 10:36:43,230 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-11-20 10:36:43,230 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 663 transitions. Stem has 109 letters. Loop has 64 letters. [2019-11-20 10:36:43,232 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-11-20 10:36:43,232 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 663 transitions. Stem has 45 letters. Loop has 128 letters. [2019-11-20 10:36:43,233 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-11-20 10:36:43,234 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3297 states and 4508 transitions. [2019-11-20 10:36:43,262 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 2462 [2019-11-20 10:36:43,290 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3297 states to 3293 states and 4504 transitions. [2019-11-20 10:36:43,291 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2526 [2019-11-20 10:36:43,294 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2539 [2019-11-20 10:36:43,295 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3293 states and 4504 transitions. [2019-11-20 10:36:43,295 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-11-20 10:36:43,295 INFO L688 BuchiCegarLoop]: Abstraction has 3293 states and 4504 transitions. [2019-11-20 10:36:43,299 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3293 states and 4504 transitions. [2019-11-20 10:36:43,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3293 to 2410. [2019-11-20 10:36:43,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2410 states. [2019-11-20 10:36:43,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2410 states to 2410 states and 3296 transitions. [2019-11-20 10:36:43,359 INFO L711 BuchiCegarLoop]: Abstraction has 2410 states and 3296 transitions. [2019-11-20 10:36:43,359 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 10:36:43,359 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 10:36:43,359 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 10:36:43,359 INFO L87 Difference]: Start difference. First operand 2410 states and 3296 transitions. Second operand 3 states. [2019-11-20 10:36:43,433 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 10:36:43,433 INFO L93 Difference]: Finished difference Result 4300 states and 5733 transitions. [2019-11-20 10:36:43,433 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 10:36:43,434 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4300 states and 5733 transitions. [2019-11-20 10:36:43,462 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2888 [2019-11-20 10:36:43,502 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4300 states to 4300 states and 5733 transitions. [2019-11-20 10:36:43,502 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2952 [2019-11-20 10:36:43,506 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2952 [2019-11-20 10:36:43,507 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4300 states and 5733 transitions. [2019-11-20 10:36:43,507 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-11-20 10:36:43,508 INFO L688 BuchiCegarLoop]: Abstraction has 4300 states and 5733 transitions. [2019-11-20 10:36:43,513 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4300 states and 5733 transitions. [2019-11-20 10:36:43,580 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4300 to 3988. [2019-11-20 10:36:43,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3988 states. [2019-11-20 10:36:43,594 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3988 states to 3988 states and 5361 transitions. [2019-11-20 10:36:43,594 INFO L711 BuchiCegarLoop]: Abstraction has 3988 states and 5361 transitions. [2019-11-20 10:36:43,595 INFO L591 BuchiCegarLoop]: Abstraction has 3988 states and 5361 transitions. [2019-11-20 10:36:43,595 INFO L424 BuchiCegarLoop]: ======== Iteration 14============ [2019-11-20 10:36:43,595 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3988 states and 5361 transitions. [2019-11-20 10:36:43,609 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2680 [2019-11-20 10:36:43,609 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-20 10:36:43,609 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-20 10:36:43,611 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:43,611 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:43,611 INFO L794 eck$LassoCheckResult]: Stem: 28351#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 28084#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 28085#L605 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 28341#L264 assume 1 == ~m_i~0;~m_st~0 := 0; 28342#L271-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28516#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28295#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28296#L286-1 assume !(0 == ~M_E~0); 28340#L408-1 assume !(0 == ~T1_E~0); 28277#L413-1 assume !(0 == ~T2_E~0); 28278#L418-1 assume !(0 == ~T3_E~0); 28388#L423-1 assume !(0 == ~E_1~0); 28142#L428-1 assume !(0 == ~E_2~0); 28143#L433-1 assume !(0 == ~E_3~0); 28158#L438-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 28323#L187 assume !(1 == ~m_pc~0); 28324#L187-2 is_master_triggered_~__retres1~0 := 0; 28326#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 28327#L199 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 28439#L500 assume !(0 != activate_threads_~tmp~1); 28440#L500-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 28445#L206 assume !(1 == ~t1_pc~0); 28643#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 28644#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 28162#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 28163#L508 assume !(0 != activate_threads_~tmp___0~0); 28496#L508-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 28446#L225 assume !(1 == ~t2_pc~0); 28282#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 28441#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 28294#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 28131#L516 assume !(0 != activate_threads_~tmp___1~0); 28132#L516-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 28135#L244 assume !(1 == ~t3_pc~0); 28659#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 28483#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 28484#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 28530#L524 assume !(0 != activate_threads_~tmp___2~0); 28531#L524-2 assume !(1 == ~M_E~0); 28382#L451-1 assume !(1 == ~T1_E~0); 28383#L456-1 assume !(1 == ~T2_E~0); 28136#L461-1 assume !(1 == ~T3_E~0); 28137#L466-1 assume !(1 == ~E_1~0); 28157#L471-1 assume !(1 == ~E_2~0); 28581#L476-1 assume 1 == ~E_3~0;~E_3~0 := 2; 28622#L642-1 [2019-11-20 10:36:43,612 INFO L796 eck$LassoCheckResult]: Loop: 28622#L642-1 assume !false; 30551#L643 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 30208#L383 assume !false; 30546#L332 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 30520#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 30517#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 29857#L322 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 29858#L336 assume 0 != eval_~tmp~0; 29844#L336-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 29845#L344 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1; 30231#L43 assume !(0 == ~m_pc~0); 30526#L46 assume 1 == ~m_pc~0; 29753#L47 assume !false; 29754#L63 ~m_pc~0 := 1;~m_st~0 := 2; 30113#L341 assume !(0 == ~t1_st~0); 30106#L355 assume !(0 == ~t2_st~0); 30105#L369 assume !(0 == ~t3_st~0); 30103#L383 assume !false; 30530#L332 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 30531#L299 assume !(0 == ~m_st~0); 30545#L303 assume !(0 == ~t1_st~0); 30542#L307 assume !(0 == ~t2_st~0); 30543#L311 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 30544#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 30682#L322 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 30680#L336 assume !(0 != eval_~tmp~0); 30678#L398 start_simulation_~kernel_st~0 := 2; 30676#L264-1 start_simulation_~kernel_st~0 := 3; 30674#L408-2 assume 0 == ~M_E~0;~M_E~0 := 1; 30672#L408-4 assume !(0 == ~T1_E~0); 30671#L413-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30669#L418-3 assume !(0 == ~T3_E~0); 30665#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30663#L428-3 assume !(0 == ~E_2~0); 30662#L433-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30661#L438-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30660#L187-12 assume 1 == ~m_pc~0; 30658#L188-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 30656#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 30653#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 30650#L500-12 assume !(0 != activate_threads_~tmp~1); 30648#L500-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30645#L206-12 assume !(1 == ~t1_pc~0); 30643#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 30641#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30639#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 30637#L508-12 assume !(0 != activate_threads_~tmp___0~0); 30635#L508-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 30633#L225-12 assume !(1 == ~t2_pc~0); 30630#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 30627#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 30625#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 30623#L516-12 assume !(0 != activate_threads_~tmp___1~0); 30621#L516-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 30619#L244-12 assume !(1 == ~t3_pc~0); 30617#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 30615#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 30613#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 30611#L524-12 assume !(0 != activate_threads_~tmp___2~0); 30609#L524-14 assume 1 == ~M_E~0;~M_E~0 := 2; 30607#L451-3 assume !(1 == ~T1_E~0); 30605#L456-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30603#L461-3 assume !(1 == ~T3_E~0); 30601#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30599#L471-3 assume !(1 == ~E_2~0); 30597#L476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30595#L481-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 30593#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 30594#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 30670#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 30667#L661 assume !(0 == start_simulation_~tmp~3); 30664#L661-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 30571#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 30568#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 30569#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 30562#L616 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 30563#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 30556#L624 start_simulation_#t~ret11 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 30557#L674 assume !(0 != start_simulation_~tmp___0~1); 28622#L642-1 [2019-11-20 10:36:43,612 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:43,612 INFO L82 PathProgramCache]: Analyzing trace with hash 1346636879, now seen corresponding path program 1 times [2019-11-20 10:36:43,613 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:43,613 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1369879659] [2019-11-20 10:36:43,613 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:43,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:43,639 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 10:36:43,639 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1369879659] [2019-11-20 10:36:43,639 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 10:36:43,639 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-11-20 10:36:43,639 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1240522078] [2019-11-20 10:36:43,640 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-20 10:36:43,640 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:43,640 INFO L82 PathProgramCache]: Analyzing trace with hash 996986456, now seen corresponding path program 1 times [2019-11-20 10:36:43,640 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:43,640 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1864767910] [2019-11-20 10:36:43,640 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:43,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:43,703 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-11-20 10:36:43,704 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1864767910] [2019-11-20 10:36:43,704 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 10:36:43,704 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-20 10:36:43,704 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2008949365] [2019-11-20 10:36:43,705 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-20 10:36:43,705 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 10:36:43,705 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 10:36:43,706 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 10:36:43,706 INFO L87 Difference]: Start difference. First operand 3988 states and 5361 transitions. cyclomatic complexity: 1385 Second operand 3 states. [2019-11-20 10:36:43,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 10:36:43,763 INFO L93 Difference]: Finished difference Result 3860 states and 5099 transitions. [2019-11-20 10:36:43,763 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 10:36:43,763 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3860 states and 5099 transitions. [2019-11-20 10:36:43,783 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2608 [2019-11-20 10:36:43,804 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3860 states to 2672 states and 3528 transitions. [2019-11-20 10:36:43,804 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2672 [2019-11-20 10:36:43,807 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2672 [2019-11-20 10:36:43,808 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2672 states and 3528 transitions. [2019-11-20 10:36:43,812 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-20 10:36:43,813 INFO L688 BuchiCegarLoop]: Abstraction has 2672 states and 3528 transitions. [2019-11-20 10:36:43,816 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2672 states and 3528 transitions. [2019-11-20 10:36:43,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2672 to 1483. [2019-11-20 10:36:43,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1483 states. [2019-11-20 10:36:43,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1483 states to 1483 states and 1949 transitions. [2019-11-20 10:36:43,849 INFO L711 BuchiCegarLoop]: Abstraction has 1483 states and 1949 transitions. [2019-11-20 10:36:43,849 INFO L591 BuchiCegarLoop]: Abstraction has 1483 states and 1949 transitions. [2019-11-20 10:36:43,849 INFO L424 BuchiCegarLoop]: ======== Iteration 15============ [2019-11-20 10:36:43,850 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1483 states and 1949 transitions. [2019-11-20 10:36:43,855 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1428 [2019-11-20 10:36:43,855 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-20 10:36:43,855 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-20 10:36:43,857 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:43,857 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:43,857 INFO L794 eck$LassoCheckResult]: Stem: 36084#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 35934#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 35935#L605 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 36078#L264 assume 1 == ~m_i~0;~m_st~0 := 0; 36079#L271-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36170#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36051#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36052#L286-1 assume !(0 == ~M_E~0); 36077#L408-1 assume !(0 == ~T1_E~0); 36040#L413-1 assume !(0 == ~T2_E~0); 36041#L418-1 assume !(0 == ~T3_E~0); 36102#L423-1 assume !(0 == ~E_1~0); 35967#L428-1 assume !(0 == ~E_2~0); 35968#L433-1 assume !(0 == ~E_3~0); 35975#L438-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 36066#L187 assume !(1 == ~m_pc~0); 36067#L187-2 is_master_triggered_~__retres1~0 := 0; 36069#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 36070#L199 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 36133#L500 assume !(0 != activate_threads_~tmp~1); 36134#L500-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 36137#L206 assume !(1 == ~t1_pc~0); 36232#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 36233#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 35977#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 35978#L508 assume !(0 != activate_threads_~tmp___0~0); 36159#L508-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 36138#L225 assume !(1 == ~t2_pc~0); 36044#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 36135#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 36050#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 35959#L516 assume !(0 != activate_threads_~tmp___1~0); 35960#L516-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 35962#L244 assume !(1 == ~t3_pc~0); 36243#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 36152#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 36153#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 36175#L524 assume !(0 != activate_threads_~tmp___2~0); 36176#L524-2 assume !(1 == ~M_E~0); 36098#L451-1 assume !(1 == ~T1_E~0); 36099#L456-1 assume !(1 == ~T2_E~0); 35963#L461-1 assume !(1 == ~T3_E~0); 35964#L466-1 assume !(1 == ~E_1~0); 35974#L471-1 assume !(1 == ~E_2~0); 36199#L476-1 assume !(1 == ~E_3~0); 35979#L642-1 [2019-11-20 10:36:43,858 INFO L796 eck$LassoCheckResult]: Loop: 35979#L642-1 assume !false; 35924#L643 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 35925#L383 assume !false; 36144#L332 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 36145#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 36156#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 37243#L322 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 36053#L336 assume 0 != eval_~tmp~0; 36054#L336-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 36058#L344 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1; 35943#L43 assume !(0 == ~m_pc~0); 35944#L46 assume 1 == ~m_pc~0; 36256#L47 assume !false; 36742#L63 ~m_pc~0 := 1;~m_st~0 := 2; 36739#L341 assume !(0 == ~t1_st~0); 36719#L355 assume !(0 == ~t2_st~0); 36799#L369 assume !(0 == ~t3_st~0); 36797#L383 assume !false; 36796#L332 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 36795#L299 assume !(0 == ~m_st~0); 36794#L303 assume !(0 == ~t1_st~0); 36791#L307 assume !(0 == ~t2_st~0); 36792#L311 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 36793#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 37242#L322 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 37241#L336 assume !(0 != eval_~tmp~0); 37240#L398 start_simulation_~kernel_st~0 := 2; 37239#L264-1 start_simulation_~kernel_st~0 := 3; 37238#L408-2 assume 0 == ~M_E~0;~M_E~0 := 1; 37236#L408-4 assume !(0 == ~T1_E~0); 37233#L413-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37231#L418-3 assume !(0 == ~T3_E~0); 37229#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37226#L428-3 assume !(0 == ~E_2~0); 37224#L433-3 assume !(0 == ~E_3~0); 37222#L438-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 37221#L187-12 assume 1 == ~m_pc~0; 37219#L188-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 37218#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 37217#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 37214#L500-12 assume !(0 != activate_threads_~tmp~1); 37211#L500-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 37209#L206-12 assume !(1 == ~t1_pc~0); 37207#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 37203#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 37201#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 37199#L508-12 assume !(0 != activate_threads_~tmp___0~0); 37196#L508-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 37197#L225-12 assume !(1 == ~t2_pc~0); 37337#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 37336#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 37335#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 37334#L516-12 assume !(0 != activate_threads_~tmp___1~0); 37333#L516-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 37179#L244-12 assume !(1 == ~t3_pc~0); 37177#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 37175#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 37172#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 37173#L524-12 assume !(0 != activate_threads_~tmp___2~0); 37320#L524-14 assume 1 == ~M_E~0;~M_E~0 := 2; 37165#L451-3 assume !(1 == ~T1_E~0); 37162#L456-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37163#L461-3 assume !(1 == ~T3_E~0); 37157#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37155#L471-3 assume !(1 == ~E_2~0); 37153#L476-3 assume !(1 == ~E_3~0); 37150#L481-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 37151#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 37120#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 37118#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 37115#L661 assume !(0 == start_simulation_~tmp~3); 37112#L661-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 37110#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 36833#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 37107#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 37105#L616 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 37103#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 36254#L624 start_simulation_#t~ret11 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 36225#L674 assume !(0 != start_simulation_~tmp___0~1); 35979#L642-1 [2019-11-20 10:36:43,858 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:43,858 INFO L82 PathProgramCache]: Analyzing trace with hash 1346636881, now seen corresponding path program 6 times [2019-11-20 10:36:43,859 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:43,859 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1614546189] [2019-11-20 10:36:43,859 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:43,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:43,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:43,876 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-20 10:36:43,876 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:43,877 INFO L82 PathProgramCache]: Analyzing trace with hash 879355544, now seen corresponding path program 1 times [2019-11-20 10:36:43,877 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:43,877 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2024218248] [2019-11-20 10:36:43,877 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:43,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:43,923 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-11-20 10:36:43,923 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2024218248] [2019-11-20 10:36:43,924 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 10:36:43,924 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-20 10:36:43,924 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [679634954] [2019-11-20 10:36:43,925 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-20 10:36:43,925 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 10:36:43,925 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-20 10:36:43,925 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-20 10:36:43,925 INFO L87 Difference]: Start difference. First operand 1483 states and 1949 transitions. cyclomatic complexity: 470 Second operand 6 states. [2019-11-20 10:36:44,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 10:36:44,258 INFO L93 Difference]: Finished difference Result 3930 states and 5073 transitions. [2019-11-20 10:36:44,258 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-11-20 10:36:44,259 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3930 states and 5073 transitions. [2019-11-20 10:36:44,277 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3496 [2019-11-20 10:36:44,297 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3930 states to 3930 states and 5073 transitions. [2019-11-20 10:36:44,297 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3930 [2019-11-20 10:36:44,301 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3930 [2019-11-20 10:36:44,302 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3930 states and 5073 transitions. [2019-11-20 10:36:44,308 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-20 10:36:44,308 INFO L688 BuchiCegarLoop]: Abstraction has 3930 states and 5073 transitions. [2019-11-20 10:36:44,312 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3930 states and 5073 transitions. [2019-11-20 10:36:44,353 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3930 to 1849. [2019-11-20 10:36:44,353 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1849 states. [2019-11-20 10:36:44,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1849 states to 1849 states and 2410 transitions. [2019-11-20 10:36:44,359 INFO L711 BuchiCegarLoop]: Abstraction has 1849 states and 2410 transitions. [2019-11-20 10:36:44,359 INFO L591 BuchiCegarLoop]: Abstraction has 1849 states and 2410 transitions. [2019-11-20 10:36:44,360 INFO L424 BuchiCegarLoop]: ======== Iteration 16============ [2019-11-20 10:36:44,360 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1849 states and 2410 transitions. [2019-11-20 10:36:44,367 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1751 [2019-11-20 10:36:44,367 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-20 10:36:44,367 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-20 10:36:44,369 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:44,369 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:44,369 INFO L794 eck$LassoCheckResult]: Stem: 41521#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 41366#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 41367#L605 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 41514#L264 assume 1 == ~m_i~0;~m_st~0 := 0; 41515#L271-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41610#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41487#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41488#L286-1 assume !(0 == ~M_E~0); 41513#L408-1 assume !(0 == ~T1_E~0); 41474#L413-1 assume !(0 == ~T2_E~0); 41475#L418-1 assume !(0 == ~T3_E~0); 41546#L423-1 assume !(0 == ~E_1~0); 41398#L428-1 assume !(0 == ~E_2~0); 41399#L433-1 assume !(0 == ~E_3~0); 41406#L438-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 41502#L187 assume 1 == ~m_pc~0; 41504#L188 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 41617#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 42407#L199 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 41571#L500 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 41572#L500-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 41575#L206 assume !(1 == ~t1_pc~0); 41679#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 41680#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 41409#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 41410#L508 assume !(0 != activate_threads_~tmp___0~0); 41599#L508-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 41576#L225 assume !(1 == ~t2_pc~0); 41477#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 41573#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 41480#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 41389#L516 assume !(0 != activate_threads_~tmp___1~0); 41390#L516-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 41393#L244 assume !(1 == ~t3_pc~0); 41691#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 41593#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 41594#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 41622#L524 assume !(0 != activate_threads_~tmp___2~0); 41623#L524-2 assume !(1 == ~M_E~0); 41541#L451-1 assume !(1 == ~T1_E~0); 41542#L456-1 assume !(1 == ~T2_E~0); 41394#L461-1 assume !(1 == ~T3_E~0); 41395#L466-1 assume !(1 == ~E_1~0); 41405#L471-1 assume !(1 == ~E_2~0); 41645#L476-1 assume !(1 == ~E_3~0); 41667#L642-1 [2019-11-20 10:36:44,370 INFO L796 eck$LassoCheckResult]: Loop: 41667#L642-1 assume !false; 41356#L643 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 41357#L383 assume !false; 41583#L332 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 41584#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 41585#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 41586#L322 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 41489#L336 assume 0 != eval_~tmp~0; 41490#L336-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 41494#L344 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1; 41658#L43 assume !(0 == ~m_pc~0); 42426#L46 assume 1 == ~m_pc~0; 42408#L47 assume !false; 41675#L63 ~m_pc~0 := 1;~m_st~0 := 2; 41676#L341 assume !(0 == ~t1_st~0); 42356#L355 assume !(0 == ~t2_st~0); 42355#L369 assume !(0 == ~t3_st~0); 42353#L383 assume !false; 42432#L332 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 42430#L299 assume !(0 == ~m_st~0); 41445#L303 assume !(0 == ~t1_st~0); 41372#L307 assume !(0 == ~t2_st~0); 41374#L311 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 41660#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 42623#L322 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 42620#L336 assume !(0 != eval_~tmp~0); 41582#L398 start_simulation_~kernel_st~0 := 2; 41507#L264-1 start_simulation_~kernel_st~0 := 3; 41508#L408-2 assume 0 == ~M_E~0;~M_E~0 := 1; 41624#L408-4 assume !(0 == ~T1_E~0); 41492#L413-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 41493#L418-3 assume !(0 == ~T3_E~0); 41553#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 41368#L428-3 assume !(0 == ~E_2~0); 41369#L433-3 assume !(0 == ~E_3~0); 41404#L438-3 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 41422#L187-12 assume 1 == ~m_pc~0; 41960#L188-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 41961#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 42462#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 41558#L500-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 41559#L500-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 41666#L206-12 assume !(1 == ~t1_pc~0); 41664#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 41665#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 41426#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 41427#L508-12 assume !(0 != activate_threads_~tmp___0~0); 41698#L508-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 42565#L225-12 assume !(1 == ~t2_pc~0); 42563#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 42562#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 42561#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 42560#L516-12 assume !(0 != activate_threads_~tmp___1~0); 41360#L516-14 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 41361#L244-12 assume !(1 == ~t3_pc~0); 41673#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 42804#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 41639#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 41640#L524-12 assume !(0 != activate_threads_~tmp___2~0); 41596#L524-14 assume 1 == ~M_E~0;~M_E~0 := 2; 41548#L451-3 assume !(1 == ~T1_E~0); 41549#L456-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42802#L461-3 assume !(1 == ~T3_E~0); 41407#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41408#L471-3 assume !(1 == ~E_2~0); 41653#L476-3 assume !(1 == ~E_3~0); 41654#L481-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 41595#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 41588#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 41589#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 41456#L661 assume !(0 == start_simulation_~tmp~3); 41458#L661-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 43119#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 42272#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 43118#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 43117#L616 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 43116#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 43115#L624 start_simulation_#t~ret11 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 43114#L674 assume !(0 != start_simulation_~tmp___0~1); 41667#L642-1 [2019-11-20 10:36:44,370 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:44,370 INFO L82 PathProgramCache]: Analyzing trace with hash 1341741492, now seen corresponding path program 1 times [2019-11-20 10:36:44,370 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:44,371 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1649518573] [2019-11-20 10:36:44,371 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:44,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:44,386 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 10:36:44,386 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1649518573] [2019-11-20 10:36:44,386 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 10:36:44,386 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 10:36:44,387 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [110457807] [2019-11-20 10:36:44,387 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-20 10:36:44,387 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:44,387 INFO L82 PathProgramCache]: Analyzing trace with hash -1570244586, now seen corresponding path program 1 times [2019-11-20 10:36:44,387 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:44,387 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [760455247] [2019-11-20 10:36:44,388 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:44,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:44,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:44,412 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-20 10:36:45,138 WARN L191 SmtUtils]: Spent 720.00 ms on a formula simplification. DAG size of input: 155 DAG size of output: 138 [2019-11-20 10:36:45,329 WARN L191 SmtUtils]: Spent 185.00 ms on a formula simplification that was a NOOP. DAG size: 108 [2019-11-20 10:36:45,331 INFO L210 LassoAnalysis]: Preferences: [2019-11-20 10:36:45,331 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2019-11-20 10:36:45,331 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-11-20 10:36:45,331 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2019-11-20 10:36:45,331 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2019-11-20 10:36:45,331 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:45,331 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2019-11-20 10:36:45,332 INFO L132 ssoRankerPreferences]: Path of dumped script: [2019-11-20 10:36:45,332 INFO L133 ssoRankerPreferences]: Filename of dumped script: transmitter.03.cil.c_Iteration16_Loop [2019-11-20 10:36:45,332 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2019-11-20 10:36:45,332 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-11-20 10:36:45,335 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,342 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,344 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,351 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,356 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,359 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,365 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,370 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,372 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,375 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,381 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,383 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,385 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,387 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,390 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,403 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,407 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,417 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,420 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,426 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,429 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,434 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,444 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,446 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,448 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,454 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,457 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,459 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,468 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,475 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,477 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,481 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,487 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,493 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,500 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,509 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,511 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,515 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,518 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,536 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,538 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,546 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:45,554 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,220 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-11-20 10:36:46,220 INFO L404 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 23 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:46,233 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-20 10:36:46,234 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-11-20 10:36:46,239 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-20 10:36:46,239 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret11=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret11=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 24 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:46,256 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-20 10:36:46,256 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 24 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:46,262 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-20 10:36:46,262 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=0} Honda state: {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 25 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:46,275 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-20 10:36:46,275 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 25 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:46,284 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-20 10:36:46,284 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp~1=1, ULTIMATE.start_is_master_triggered_#res=1, ULTIMATE.start_is_master_triggered_~__retres1~0=1} Honda state: {ULTIMATE.start_activate_threads_~tmp~1=1, ULTIMATE.start_is_master_triggered_#res=1, ULTIMATE.start_is_master_triggered_~__retres1~0=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 26 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:46,296 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-20 10:36:46,296 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 26 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:46,302 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-20 10:36:46,302 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_3~0=3} Honda state: {~E_3~0=3} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 27 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:46,314 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-20 10:36:46,314 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 27 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:46,320 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-20 10:36:46,320 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t2_st~0=7} Honda state: {~t2_st~0=7} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 28 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:46,330 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-20 10:36:46,330 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 28 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:46,336 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-20 10:36:46,336 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~tmp___0~1=0, ULTIMATE.start_stop_simulation_#res=0} Honda state: {ULTIMATE.start_start_simulation_~tmp___0~1=0, ULTIMATE.start_stop_simulation_#res=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 29 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:46,346 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-20 10:36:46,347 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 29 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:46,351 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-20 10:36:46,352 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret10=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret10=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 30 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:46,362 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-20 10:36:46,362 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 30 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:46,368 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-20 10:36:46,369 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_3~0=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_3~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 31 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:46,382 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-20 10:36:46,382 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 31 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:46,389 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-20 10:36:46,389 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_pc~0=-8} Honda state: {~t1_pc~0=-8} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 32 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:46,399 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-20 10:36:46,399 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 32 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 33 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:46,414 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2019-11-20 10:36:46,414 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 33 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:46,425 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2019-11-20 10:36:46,427 INFO L210 LassoAnalysis]: Preferences: [2019-11-20 10:36:46,427 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2019-11-20 10:36:46,427 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-11-20 10:36:46,427 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2019-11-20 10:36:46,427 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2019-11-20 10:36:46,428 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:46,428 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2019-11-20 10:36:46,428 INFO L132 ssoRankerPreferences]: Path of dumped script: [2019-11-20 10:36:46,428 INFO L133 ssoRankerPreferences]: Filename of dumped script: transmitter.03.cil.c_Iteration16_Loop [2019-11-20 10:36:46,428 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2019-11-20 10:36:46,428 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-11-20 10:36:46,431 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,436 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,439 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,451 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,461 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,465 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,467 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,475 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,478 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,482 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,493 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,495 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,502 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,530 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,533 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,539 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,542 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,549 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,552 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,556 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,566 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,568 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,576 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,578 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,579 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,584 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,586 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,588 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,590 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,595 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,602 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,614 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,617 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,620 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,632 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,643 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,645 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,648 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,651 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,654 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,661 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,663 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:46,665 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-20 10:36:47,282 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-11-20 10:36:47,282 INFO L489 LassoAnalysis]: Using template 'affine'. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 34 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:47,292 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-20 10:36:47,294 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-20 10:36:47,294 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-20 10:36:47,294 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-20 10:36:47,295 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-20 10:36:47,295 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-20 10:36:47,296 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-20 10:36:47,296 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. Waiting until toolchain timeout for monitored process 34 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:47,298 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 35 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:47,305 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-20 10:36:47,307 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-20 10:36:47,307 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-20 10:36:47,307 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-20 10:36:47,308 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-20 10:36:47,308 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-20 10:36:47,309 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-20 10:36:47,309 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. Waiting until toolchain timeout for monitored process 35 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:47,313 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 36 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:47,321 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-20 10:36:47,323 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-20 10:36:47,323 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-20 10:36:47,324 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-20 10:36:47,324 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2019-11-20 10:36:47,324 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-20 10:36:47,325 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2019-11-20 10:36:47,325 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. Waiting until toolchain timeout for monitored process 36 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:47,329 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 37 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:47,336 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-20 10:36:47,338 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-20 10:36:47,338 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-20 10:36:47,338 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-20 10:36:47,339 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-20 10:36:47,339 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-20 10:36:47,341 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-20 10:36:47,342 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. Waiting until toolchain timeout for monitored process 37 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:47,346 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 38 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:47,356 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-20 10:36:47,358 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-20 10:36:47,358 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-20 10:36:47,358 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-20 10:36:47,358 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2019-11-20 10:36:47,359 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-20 10:36:47,361 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2019-11-20 10:36:47,361 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. Waiting until toolchain timeout for monitored process 38 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:47,364 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 39 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:47,371 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-20 10:36:47,373 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-20 10:36:47,373 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-20 10:36:47,373 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-20 10:36:47,373 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-20 10:36:47,374 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-20 10:36:47,374 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-20 10:36:47,374 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. Waiting until toolchain timeout for monitored process 39 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:47,377 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 40 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:47,393 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-20 10:36:47,395 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-20 10:36:47,396 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-20 10:36:47,396 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-20 10:36:47,396 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-20 10:36:47,396 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-20 10:36:47,397 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-20 10:36:47,397 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. Waiting until toolchain timeout for monitored process 40 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:47,400 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 41 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:47,409 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-20 10:36:47,411 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-20 10:36:47,411 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-20 10:36:47,412 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-20 10:36:47,412 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-20 10:36:47,412 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-20 10:36:47,413 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-20 10:36:47,413 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. Waiting until toolchain timeout for monitored process 41 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:47,415 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 42 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:47,426 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-20 10:36:47,429 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-20 10:36:47,429 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-20 10:36:47,430 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-20 10:36:47,430 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2019-11-20 10:36:47,430 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-20 10:36:47,431 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2019-11-20 10:36:47,431 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. Waiting until toolchain timeout for monitored process 42 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:47,434 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 43 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:47,446 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-20 10:36:47,448 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-20 10:36:47,448 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-20 10:36:47,449 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-20 10:36:47,449 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-20 10:36:47,449 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-20 10:36:47,451 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-20 10:36:47,451 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. Waiting until toolchain timeout for monitored process 43 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:47,455 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2019-11-20 10:36:47,458 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2019-11-20 10:36:47,458 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/z3 Starting monitored process 44 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-20 10:36:47,466 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2019-11-20 10:36:47,466 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2019-11-20 10:36:47,467 INFO L510 LassoAnalysis]: Proved termination. [2019-11-20 10:36:47,467 INFO L512 LassoAnalysis]: Termination argument consisting of: Ranking function f(~T2_E~0) = -1*~T2_E~0 + 1 Supporting invariants [] [2019-11-20 10:36:47,469 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed Waiting until toolchain timeout for monitored process 44 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-20 10:36:47,490 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:47,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:47,520 INFO L255 TraceCheckSpWp]: Trace formula consists of 124 conjuncts, 2 conjunts are in the unsatisfiable core [2019-11-20 10:36:47,525 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 10:36:47,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:47,564 INFO L255 TraceCheckSpWp]: Trace formula consists of 156 conjuncts, 4 conjunts are in the unsatisfiable core [2019-11-20 10:36:47,567 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-20 10:36:47,603 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-11-20 10:36:47,604 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2019-11-20 10:36:47,604 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 1849 states and 2410 transitions. cyclomatic complexity: 569 Second operand 5 states. [2019-11-20 10:36:47,659 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 1849 states and 2410 transitions. cyclomatic complexity: 569. Second operand 5 states. Result 3659 states and 4785 transitions. Complement of second has 4 states. [2019-11-20 10:36:47,660 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2019-11-20 10:36:47,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2019-11-20 10:36:47,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 371 transitions. [2019-11-20 10:36:47,661 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 371 transitions. Stem has 45 letters. Loop has 79 letters. [2019-11-20 10:36:47,661 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-11-20 10:36:47,661 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 371 transitions. Stem has 124 letters. Loop has 79 letters. [2019-11-20 10:36:47,662 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-11-20 10:36:47,662 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 371 transitions. Stem has 45 letters. Loop has 158 letters. [2019-11-20 10:36:47,663 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-11-20 10:36:47,663 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3659 states and 4785 transitions. [2019-11-20 10:36:47,681 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1751 [2019-11-20 10:36:47,714 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3659 states to 3659 states and 4785 transitions. [2019-11-20 10:36:47,714 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1849 [2019-11-20 10:36:47,717 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1871 [2019-11-20 10:36:47,717 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3659 states and 4785 transitions. [2019-11-20 10:36:47,717 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-11-20 10:36:47,717 INFO L688 BuchiCegarLoop]: Abstraction has 3659 states and 4785 transitions. [2019-11-20 10:36:47,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3659 states and 4785 transitions. [2019-11-20 10:36:47,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3659 to 3638. [2019-11-20 10:36:47,769 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3638 states. [2019-11-20 10:36:47,779 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3638 states to 3638 states and 4744 transitions. [2019-11-20 10:36:47,779 INFO L711 BuchiCegarLoop]: Abstraction has 3638 states and 4744 transitions. [2019-11-20 10:36:47,779 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 10:36:47,779 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 10:36:47,780 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 10:36:47,780 INFO L87 Difference]: Start difference. First operand 3638 states and 4744 transitions. Second operand 3 states. [2019-11-20 10:36:47,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 10:36:47,832 INFO L93 Difference]: Finished difference Result 3863 states and 4988 transitions. [2019-11-20 10:36:47,833 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 10:36:47,833 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3863 states and 4988 transitions. [2019-11-20 10:36:47,850 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1751 [2019-11-20 10:36:47,863 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3863 states to 3863 states and 4988 transitions. [2019-11-20 10:36:47,863 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1945 [2019-11-20 10:36:47,866 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1945 [2019-11-20 10:36:47,866 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3863 states and 4988 transitions. [2019-11-20 10:36:47,867 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-11-20 10:36:47,867 INFO L688 BuchiCegarLoop]: Abstraction has 3863 states and 4988 transitions. [2019-11-20 10:36:47,871 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3863 states and 4988 transitions. [2019-11-20 10:36:47,928 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3863 to 3635. [2019-11-20 10:36:47,928 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3635 states. [2019-11-20 10:36:47,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3635 states to 3635 states and 4720 transitions. [2019-11-20 10:36:47,939 INFO L711 BuchiCegarLoop]: Abstraction has 3635 states and 4720 transitions. [2019-11-20 10:36:47,939 INFO L591 BuchiCegarLoop]: Abstraction has 3635 states and 4720 transitions. [2019-11-20 10:36:47,939 INFO L424 BuchiCegarLoop]: ======== Iteration 17============ [2019-11-20 10:36:47,939 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3635 states and 4720 transitions. [2019-11-20 10:36:47,951 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1751 [2019-11-20 10:36:47,951 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-20 10:36:47,951 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-20 10:36:47,953 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:47,953 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:47,953 INFO L794 eck$LassoCheckResult]: Stem: 55048#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 54777#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 54778#L605 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 55037#L264 assume 1 == ~m_i~0;~m_st~0 := 0; 55038#L271-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 55216#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 54990#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 54991#L286-1 assume !(0 == ~M_E~0); 55032#L408-1 assume !(0 == ~T1_E~0); 54972#L413-1 assume !(0 == ~T2_E~0); 54973#L418-1 assume !(0 == ~T3_E~0); 55087#L423-1 assume !(0 == ~E_1~0); 54835#L428-1 assume !(0 == ~E_2~0); 54836#L433-1 assume !(0 == ~E_3~0); 54848#L438-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 55019#L187 assume !(1 == ~m_pc~0); 55020#L187-2 is_master_triggered_~__retres1~0 := 0; 55021#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 55022#L199 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 55138#L500 assume !(0 != activate_threads_~tmp~1); 55139#L500-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 55145#L206 assume !(1 == ~t1_pc~0); 55351#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 55352#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 54851#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 54852#L508 assume !(0 != activate_threads_~tmp___0~0); 55196#L508-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 55146#L225 assume !(1 == ~t2_pc~0); 54975#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 55140#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 54979#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 54823#L516 assume !(0 != activate_threads_~tmp___1~0); 54824#L516-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 54828#L244 assume !(1 == ~t3_pc~0); 55368#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 55182#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 55183#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 55226#L524 assume !(0 != activate_threads_~tmp___2~0); 55227#L524-2 assume !(1 == ~M_E~0); 55080#L451-1 assume !(1 == ~T1_E~0); 55081#L456-1 assume !(1 == ~T2_E~0); 54829#L461-1 assume !(1 == ~T3_E~0); 54830#L466-1 assume !(1 == ~E_1~0); 54847#L471-1 assume !(1 == ~E_2~0); 55275#L476-1 assume !(1 == ~E_3~0); 55325#L642-1 assume !false; 55699#L643 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 55539#L383 [2019-11-20 10:36:47,954 INFO L796 eck$LassoCheckResult]: Loop: 55539#L383 assume !false; 55695#L332 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 55690#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 55686#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 55681#L322 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 55676#L336 assume 0 != eval_~tmp~0; 55671#L336-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 55616#L344 assume !(0 != eval_~tmp_ndt_1~0); 55586#L341 assume !(0 == ~t1_st~0); 55555#L355 assume !(0 == ~t2_st~0); 55542#L369 assume !(0 == ~t3_st~0); 55539#L383 [2019-11-20 10:36:47,954 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:47,954 INFO L82 PathProgramCache]: Analyzing trace with hash 1332893523, now seen corresponding path program 1 times [2019-11-20 10:36:47,957 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:47,958 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [974840839] [2019-11-20 10:36:47,958 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:47,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:47,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:47,978 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-20 10:36:47,979 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:47,979 INFO L82 PathProgramCache]: Analyzing trace with hash 1333816928, now seen corresponding path program 1 times [2019-11-20 10:36:47,979 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:47,979 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1196225190] [2019-11-20 10:36:47,980 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:47,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:47,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:47,986 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-20 10:36:47,986 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:47,986 INFO L82 PathProgramCache]: Analyzing trace with hash 451456974, now seen corresponding path program 1 times [2019-11-20 10:36:47,986 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:47,987 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [957993740] [2019-11-20 10:36:47,987 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:47,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:48,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 10:36:48,016 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [957993740] [2019-11-20 10:36:48,016 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 10:36:48,016 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 10:36:48,016 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [91892679] [2019-11-20 10:36:48,093 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 10:36:48,094 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 10:36:48,094 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 10:36:48,094 INFO L87 Difference]: Start difference. First operand 3635 states and 4720 transitions. cyclomatic complexity: 1101 Second operand 3 states. [2019-11-20 10:36:48,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 10:36:48,159 INFO L93 Difference]: Finished difference Result 6397 states and 8202 transitions. [2019-11-20 10:36:48,160 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 10:36:48,160 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6397 states and 8202 transitions. [2019-11-20 10:36:48,189 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 2910 [2019-11-20 10:36:48,213 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6397 states to 6397 states and 8202 transitions. [2019-11-20 10:36:48,214 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3227 [2019-11-20 10:36:48,218 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3227 [2019-11-20 10:36:48,219 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6397 states and 8202 transitions. [2019-11-20 10:36:48,219 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-11-20 10:36:48,219 INFO L688 BuchiCegarLoop]: Abstraction has 6397 states and 8202 transitions. [2019-11-20 10:36:48,226 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6397 states and 8202 transitions. [2019-11-20 10:36:48,307 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6397 to 6199. [2019-11-20 10:36:48,308 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6199 states. [2019-11-20 10:36:48,329 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6199 states to 6199 states and 7962 transitions. [2019-11-20 10:36:48,329 INFO L711 BuchiCegarLoop]: Abstraction has 6199 states and 7962 transitions. [2019-11-20 10:36:48,329 INFO L591 BuchiCegarLoop]: Abstraction has 6199 states and 7962 transitions. [2019-11-20 10:36:48,330 INFO L424 BuchiCegarLoop]: ======== Iteration 18============ [2019-11-20 10:36:48,330 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6199 states and 7962 transitions. [2019-11-20 10:36:48,352 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 2811 [2019-11-20 10:36:48,352 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-20 10:36:48,352 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-20 10:36:48,353 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:48,353 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:48,354 INFO L794 eck$LassoCheckResult]: Stem: 65093#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 64817#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 64818#L605 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 65084#L264 assume 1 == ~m_i~0;~m_st~0 := 0; 65085#L271-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 65261#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 66267#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 66266#L286-1 assume !(0 == ~M_E~0); 66265#L408-1 assume !(0 == ~T1_E~0); 66264#L413-1 assume !(0 == ~T2_E~0); 66263#L418-1 assume !(0 == ~T3_E~0); 66262#L423-1 assume !(0 == ~E_1~0); 66261#L428-1 assume !(0 == ~E_2~0); 66260#L433-1 assume !(0 == ~E_3~0); 66259#L438-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 66258#L187 assume !(1 == ~m_pc~0); 66257#L187-2 is_master_triggered_~__retres1~0 := 0; 66256#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 66255#L199 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 66254#L500 assume !(0 != activate_threads_~tmp~1); 66253#L500-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 66252#L206 assume !(1 == ~t1_pc~0); 66251#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 66250#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 66249#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 66246#L508 assume !(0 != activate_threads_~tmp___0~0); 66244#L508-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 65189#L225 assume !(1 == ~t2_pc~0); 65016#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 66226#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 66224#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 64863#L516 assume !(0 != activate_threads_~tmp___1~0); 64864#L516-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 64868#L244 assume !(1 == ~t3_pc~0); 66216#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 66214#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 65365#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 65278#L524 assume !(0 != activate_threads_~tmp___2~0); 65279#L524-2 assume !(1 == ~M_E~0); 65124#L451-1 assume !(1 == ~T1_E~0); 65125#L456-1 assume !(1 == ~T2_E~0); 65190#L461-1 assume !(1 == ~T3_E~0); 66199#L466-1 assume !(1 == ~E_1~0); 66196#L471-1 assume !(1 == ~E_2~0); 66194#L476-1 assume !(1 == ~E_3~0); 66191#L642-1 assume !false; 66189#L643 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 66159#L383 [2019-11-20 10:36:48,354 INFO L796 eck$LassoCheckResult]: Loop: 66159#L383 assume !false; 66186#L332 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 66184#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 66182#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 66180#L322 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 66178#L336 assume 0 != eval_~tmp~0; 66176#L336-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 66174#L344 assume !(0 != eval_~tmp_ndt_1~0); 66169#L341 assume !(0 == ~t1_st~0); 66163#L355 assume !(0 == ~t2_st~0); 66161#L369 assume !(0 == ~t3_st~0); 66159#L383 [2019-11-20 10:36:48,354 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:48,354 INFO L82 PathProgramCache]: Analyzing trace with hash 435500245, now seen corresponding path program 1 times [2019-11-20 10:36:48,355 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:48,355 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [848567538] [2019-11-20 10:36:48,355 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:48,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:48,370 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 10:36:48,371 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [848567538] [2019-11-20 10:36:48,371 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 10:36:48,371 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 10:36:48,371 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [419669569] [2019-11-20 10:36:48,372 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-20 10:36:48,372 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:48,372 INFO L82 PathProgramCache]: Analyzing trace with hash 1333816928, now seen corresponding path program 2 times [2019-11-20 10:36:48,372 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:48,372 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1733184267] [2019-11-20 10:36:48,373 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:48,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:48,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:48,384 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-20 10:36:48,457 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 10:36:48,457 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 10:36:48,457 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 10:36:48,457 INFO L87 Difference]: Start difference. First operand 6199 states and 7962 transitions. cyclomatic complexity: 1787 Second operand 3 states. [2019-11-20 10:36:48,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 10:36:48,478 INFO L93 Difference]: Finished difference Result 4315 states and 5589 transitions. [2019-11-20 10:36:48,478 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 10:36:48,479 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4315 states and 5589 transitions. [2019-11-20 10:36:48,499 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2082 [2019-11-20 10:36:48,516 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4315 states to 4315 states and 5589 transitions. [2019-11-20 10:36:48,517 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2172 [2019-11-20 10:36:48,519 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2172 [2019-11-20 10:36:48,519 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4315 states and 5589 transitions. [2019-11-20 10:36:48,520 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-11-20 10:36:48,520 INFO L688 BuchiCegarLoop]: Abstraction has 4315 states and 5589 transitions. [2019-11-20 10:36:48,525 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4315 states and 5589 transitions. [2019-11-20 10:36:48,664 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4315 to 4315. [2019-11-20 10:36:48,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4315 states. [2019-11-20 10:36:48,676 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4315 states to 4315 states and 5589 transitions. [2019-11-20 10:36:48,679 INFO L711 BuchiCegarLoop]: Abstraction has 4315 states and 5589 transitions. [2019-11-20 10:36:48,679 INFO L591 BuchiCegarLoop]: Abstraction has 4315 states and 5589 transitions. [2019-11-20 10:36:48,679 INFO L424 BuchiCegarLoop]: ======== Iteration 19============ [2019-11-20 10:36:48,679 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4315 states and 5589 transitions. [2019-11-20 10:36:48,692 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2082 [2019-11-20 10:36:48,696 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-20 10:36:48,696 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-20 10:36:48,697 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:48,697 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:48,698 INFO L794 eck$LassoCheckResult]: Stem: 75611#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 75337#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 75338#L605 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 75602#L264 assume 1 == ~m_i~0;~m_st~0 := 0; 75603#L271-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 75769#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 75553#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 75554#L286-1 assume !(0 == ~M_E~0); 75601#L408-1 assume !(0 == ~T1_E~0); 75532#L413-1 assume !(0 == ~T2_E~0); 75533#L418-1 assume !(0 == ~T3_E~0); 75645#L423-1 assume !(0 == ~E_1~0); 75395#L428-1 assume !(0 == ~E_2~0); 75396#L433-1 assume !(0 == ~E_3~0); 75409#L438-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 75585#L187 assume !(1 == ~m_pc~0); 75586#L187-2 is_master_triggered_~__retres1~0 := 0; 75587#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 75588#L199 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 75695#L500 assume !(0 != activate_threads_~tmp~1); 75696#L500-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 75702#L206 assume !(1 == ~t1_pc~0); 75882#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 75883#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 75412#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 75413#L508 assume !(0 != activate_threads_~tmp___0~0); 75749#L508-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 75703#L225 assume !(1 == ~t2_pc~0); 75535#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 75697#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 75544#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 75383#L516 assume !(0 != activate_threads_~tmp___1~0); 75384#L516-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 75388#L244 assume !(1 == ~t3_pc~0); 75899#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 75737#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 75738#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 75785#L524 assume !(0 != activate_threads_~tmp___2~0); 75786#L524-2 assume !(1 == ~M_E~0); 75639#L451-1 assume !(1 == ~T1_E~0); 75640#L456-1 assume !(1 == ~T2_E~0); 75389#L461-1 assume !(1 == ~T3_E~0); 75390#L466-1 assume !(1 == ~E_1~0); 75408#L471-1 assume !(1 == ~E_2~0); 75832#L476-1 assume !(1 == ~E_3~0); 75862#L642-1 assume !false; 78172#L643 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 78168#L383 [2019-11-20 10:36:48,698 INFO L796 eck$LassoCheckResult]: Loop: 78168#L383 assume !false; 78166#L332 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 78164#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 78162#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 78160#L322 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 78158#L336 assume 0 != eval_~tmp~0; 78156#L336-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 78154#L344 assume !(0 != eval_~tmp_ndt_1~0); 78155#L341 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 78233#L358 assume !(0 != eval_~tmp_ndt_2~0); 78177#L355 assume !(0 == ~t2_st~0); 78171#L369 assume !(0 == ~t3_st~0); 78168#L383 [2019-11-20 10:36:48,698 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:48,699 INFO L82 PathProgramCache]: Analyzing trace with hash 1332893523, now seen corresponding path program 2 times [2019-11-20 10:36:48,699 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:48,699 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [645942574] [2019-11-20 10:36:48,699 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:48,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:48,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:48,720 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-20 10:36:48,721 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:48,721 INFO L82 PathProgramCache]: Analyzing trace with hash -1605322485, now seen corresponding path program 1 times [2019-11-20 10:36:48,721 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:48,722 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [735075086] [2019-11-20 10:36:48,722 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:48,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:48,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:48,728 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-20 10:36:48,728 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:48,729 INFO L82 PathProgramCache]: Analyzing trace with hash 1106290013, now seen corresponding path program 1 times [2019-11-20 10:36:48,729 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:48,729 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1370482817] [2019-11-20 10:36:48,729 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:48,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:48,755 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 10:36:48,756 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1370482817] [2019-11-20 10:36:48,756 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 10:36:48,756 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-20 10:36:48,756 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [282976409] [2019-11-20 10:36:48,851 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 10:36:48,852 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 10:36:48,852 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 10:36:48,852 INFO L87 Difference]: Start difference. First operand 4315 states and 5589 transitions. cyclomatic complexity: 1290 Second operand 3 states. [2019-11-20 10:36:48,923 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 10:36:48,923 INFO L93 Difference]: Finished difference Result 7339 states and 9397 transitions. [2019-11-20 10:36:48,924 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 10:36:48,924 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7339 states and 9397 transitions. [2019-11-20 10:36:48,955 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3544 [2019-11-20 10:36:48,984 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7339 states to 7339 states and 9397 transitions. [2019-11-20 10:36:48,984 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3676 [2019-11-20 10:36:48,987 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3676 [2019-11-20 10:36:48,987 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7339 states and 9397 transitions. [2019-11-20 10:36:48,990 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-11-20 10:36:48,990 INFO L688 BuchiCegarLoop]: Abstraction has 7339 states and 9397 transitions. [2019-11-20 10:36:48,998 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7339 states and 9397 transitions. [2019-11-20 10:36:49,082 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7339 to 6943. [2019-11-20 10:36:49,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6943 states. [2019-11-20 10:36:49,102 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6943 states to 6943 states and 8947 transitions. [2019-11-20 10:36:49,102 INFO L711 BuchiCegarLoop]: Abstraction has 6943 states and 8947 transitions. [2019-11-20 10:36:49,102 INFO L591 BuchiCegarLoop]: Abstraction has 6943 states and 8947 transitions. [2019-11-20 10:36:49,103 INFO L424 BuchiCegarLoop]: ======== Iteration 20============ [2019-11-20 10:36:49,103 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6943 states and 8947 transitions. [2019-11-20 10:36:49,125 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3346 [2019-11-20 10:36:49,125 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-20 10:36:49,125 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-20 10:36:49,127 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:49,127 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:49,128 INFO L794 eck$LassoCheckResult]: Stem: 87286#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 87005#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 87006#L605 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 87278#L264 assume 1 == ~m_i~0;~m_st~0 := 0; 87279#L271-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 87458#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 87229#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 87230#L286-1 assume !(0 == ~M_E~0); 87277#L408-1 assume !(0 == ~T1_E~0); 87208#L413-1 assume !(0 == ~T2_E~0); 87209#L418-1 assume !(0 == ~T3_E~0); 87325#L423-1 assume !(0 == ~E_1~0); 87059#L428-1 assume !(0 == ~E_2~0); 87060#L433-1 assume !(0 == ~E_3~0); 87074#L438-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 87261#L187 assume !(1 == ~m_pc~0); 87262#L187-2 is_master_triggered_~__retres1~0 := 0; 87263#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 87264#L199 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 87375#L500 assume !(0 != activate_threads_~tmp~1); 87376#L500-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 87383#L206 assume !(1 == ~t1_pc~0); 87597#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 87598#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 87077#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 87078#L508 assume !(0 != activate_threads_~tmp___0~0); 87435#L508-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 87384#L225 assume !(1 == ~t2_pc~0); 87215#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 87377#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 87228#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 87044#L516 assume !(0 != activate_threads_~tmp___1~0); 87045#L516-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 87050#L244 assume !(1 == ~t3_pc~0); 87617#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 87423#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 87424#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 87477#L524 assume !(0 != activate_threads_~tmp___2~0); 87478#L524-2 assume !(1 == ~M_E~0); 87319#L451-1 assume !(1 == ~T1_E~0); 87320#L456-1 assume !(1 == ~T2_E~0); 87051#L461-1 assume !(1 == ~T3_E~0); 87052#L466-1 assume !(1 == ~E_1~0); 87073#L471-1 assume !(1 == ~E_2~0); 87522#L476-1 assume !(1 == ~E_3~0); 87580#L642-1 assume !false; 89406#L643 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 90310#L383 [2019-11-20 10:36:49,128 INFO L796 eck$LassoCheckResult]: Loop: 90310#L383 assume !false; 90307#L332 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 90305#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 90303#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 90299#L322 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 90297#L336 assume 0 != eval_~tmp~0; 90295#L336-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 90292#L344 assume !(0 != eval_~tmp_ndt_1~0); 90293#L341 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 91061#L358 assume !(0 != eval_~tmp_ndt_2~0); 90374#L355 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 90371#L372 assume !(0 != eval_~tmp_ndt_3~0); 90314#L369 assume !(0 == ~t3_st~0); 90310#L383 [2019-11-20 10:36:49,129 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:49,129 INFO L82 PathProgramCache]: Analyzing trace with hash 1332893523, now seen corresponding path program 3 times [2019-11-20 10:36:49,129 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:49,129 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [78805387] [2019-11-20 10:36:49,130 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:49,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:49,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:49,147 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-20 10:36:49,147 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:49,148 INFO L82 PathProgramCache]: Analyzing trace with hash 1774485897, now seen corresponding path program 1 times [2019-11-20 10:36:49,148 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:49,148 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [468932482] [2019-11-20 10:36:49,148 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:49,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:49,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:49,166 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-20 10:36:49,167 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:49,168 INFO L82 PathProgramCache]: Analyzing trace with hash -64872585, now seen corresponding path program 1 times [2019-11-20 10:36:49,168 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:49,168 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [634061191] [2019-11-20 10:36:49,168 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:49,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-20 10:36:49,194 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-20 10:36:49,195 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [634061191] [2019-11-20 10:36:49,195 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-20 10:36:49,195 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-20 10:36:49,195 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1383193751] [2019-11-20 10:36:49,320 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-20 10:36:49,321 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-20 10:36:49,321 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-20 10:36:49,321 INFO L87 Difference]: Start difference. First operand 6943 states and 8947 transitions. cyclomatic complexity: 2020 Second operand 3 states. [2019-11-20 10:36:49,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-20 10:36:49,374 INFO L93 Difference]: Finished difference Result 8338 states and 10702 transitions. [2019-11-20 10:36:49,374 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-20 10:36:49,375 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8338 states and 10702 transitions. [2019-11-20 10:36:49,405 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4006 [2019-11-20 10:36:49,433 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8338 states to 8338 states and 10702 transitions. [2019-11-20 10:36:49,434 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4180 [2019-11-20 10:36:49,437 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4180 [2019-11-20 10:36:49,437 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8338 states and 10702 transitions. [2019-11-20 10:36:49,438 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-11-20 10:36:49,438 INFO L688 BuchiCegarLoop]: Abstraction has 8338 states and 10702 transitions. [2019-11-20 10:36:49,449 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8338 states and 10702 transitions. [2019-11-20 10:36:49,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8338 to 8338. [2019-11-20 10:36:49,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8338 states. [2019-11-20 10:36:49,558 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8338 states to 8338 states and 10702 transitions. [2019-11-20 10:36:49,559 INFO L711 BuchiCegarLoop]: Abstraction has 8338 states and 10702 transitions. [2019-11-20 10:36:49,559 INFO L591 BuchiCegarLoop]: Abstraction has 8338 states and 10702 transitions. [2019-11-20 10:36:49,559 INFO L424 BuchiCegarLoop]: ======== Iteration 21============ [2019-11-20 10:36:49,559 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8338 states and 10702 transitions. [2019-11-20 10:36:49,582 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4006 [2019-11-20 10:36:49,582 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-20 10:36:49,582 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-20 10:36:49,583 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:49,583 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-20 10:36:49,584 INFO L794 eck$LassoCheckResult]: Stem: 102566#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 102293#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 102294#L605 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 102556#L264 assume 1 == ~m_i~0;~m_st~0 := 0; 102557#L271-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 102726#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 102506#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 102507#L286-1 assume !(0 == ~M_E~0); 102555#L408-1 assume !(0 == ~T1_E~0); 102486#L413-1 assume !(0 == ~T2_E~0); 102487#L418-1 assume !(0 == ~T3_E~0); 102604#L423-1 assume !(0 == ~E_1~0); 102346#L428-1 assume !(0 == ~E_2~0); 102347#L433-1 assume !(0 == ~E_3~0); 102359#L438-1 havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 102539#L187 assume !(1 == ~m_pc~0); 102540#L187-2 is_master_triggered_~__retres1~0 := 0; 102541#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 102542#L199 activate_threads_#t~ret5 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 102651#L500 assume !(0 != activate_threads_~tmp~1); 102652#L500-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 102657#L206 assume !(1 == ~t1_pc~0); 102852#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 102853#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 102362#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 102363#L508 assume !(0 != activate_threads_~tmp___0~0); 102706#L508-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 102658#L225 assume !(1 == ~t2_pc~0); 102492#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 102653#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 102505#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 102333#L516 assume !(0 != activate_threads_~tmp___1~0); 102334#L516-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 102339#L244 assume !(1 == ~t3_pc~0); 102868#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 102692#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 102693#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 102743#L524 assume !(0 != activate_threads_~tmp___2~0); 102744#L524-2 assume !(1 == ~M_E~0); 102598#L451-1 assume !(1 == ~T1_E~0); 102599#L456-1 assume !(1 == ~T2_E~0); 102340#L461-1 assume !(1 == ~T3_E~0); 102341#L466-1 assume !(1 == ~E_1~0); 102358#L471-1 assume !(1 == ~E_2~0); 102785#L476-1 assume !(1 == ~E_3~0); 102832#L642-1 assume !false; 105863#L643 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 105864#L383 [2019-11-20 10:36:49,584 INFO L796 eck$LassoCheckResult]: Loop: 105864#L383 assume !false; 106518#L332 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 106517#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 106516#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 106515#L322 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 106514#L336 assume 0 != eval_~tmp~0; 106513#L336-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 106511#L344 assume !(0 != eval_~tmp_ndt_1~0); 105843#L341 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 105837#L358 assume !(0 != eval_~tmp_ndt_2~0); 105835#L355 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 105743#L372 assume !(0 != eval_~tmp_ndt_3~0); 105831#L369 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 106519#L386 assume !(0 != eval_~tmp_ndt_4~0); 105864#L383 [2019-11-20 10:36:49,584 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:49,584 INFO L82 PathProgramCache]: Analyzing trace with hash 1332893523, now seen corresponding path program 4 times [2019-11-20 10:36:49,585 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:49,585 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [590305753] [2019-11-20 10:36:49,585 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:49,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:49,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:49,605 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-20 10:36:49,606 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:49,606 INFO L82 PathProgramCache]: Analyzing trace with hash -825512478, now seen corresponding path program 1 times [2019-11-20 10:36:49,606 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:49,606 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1208489182] [2019-11-20 10:36:49,607 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:49,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:49,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:49,612 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-20 10:36:49,613 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-20 10:36:49,613 INFO L82 PathProgramCache]: Analyzing trace with hash -2011050572, now seen corresponding path program 1 times [2019-11-20 10:36:49,613 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-20 10:36:49,613 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [752227555] [2019-11-20 10:36:49,613 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-20 10:36:49,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:49,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-20 10:36:49,639 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-20 10:36:50,126 WARN L191 SmtUtils]: Spent 355.00 ms on a formula simplification. DAG size of input: 126 DAG size of output: 86 [2019-11-20 10:36:50,232 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 20.11 10:36:50 BoogieIcfgContainer [2019-11-20 10:36:50,233 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2019-11-20 10:36:50,233 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-20 10:36:50,233 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-20 10:36:50,233 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-20 10:36:50,234 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.11 10:36:36" (3/4) ... [2019-11-20 10:36:50,237 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2019-11-20 10:36:50,297 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_d8931c4d-ee26-4f97-8f13-536232993112/bin/uautomizer/witness.graphml [2019-11-20 10:36:50,297 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-20 10:36:50,299 INFO L168 Benchmark]: Toolchain (without parser) took 15825.33 ms. Allocated memory was 1.0 GB in the beginning and 1.4 GB in the end (delta: 389.0 MB). Free memory was 944.7 MB in the beginning and 999.2 MB in the end (delta: -54.5 MB). Peak memory consumption was 334.5 MB. Max. memory is 11.5 GB. [2019-11-20 10:36:50,299 INFO L168 Benchmark]: CDTParser took 0.32 ms. Allocated memory is still 1.0 GB. Free memory is still 962.2 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-20 10:36:50,300 INFO L168 Benchmark]: CACSL2BoogieTranslator took 485.34 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 143.7 MB). Free memory was 944.7 MB in the beginning and 1.1 GB in the end (delta: -187.0 MB). Peak memory consumption was 23.2 MB. Max. memory is 11.5 GB. [2019-11-20 10:36:50,300 INFO L168 Benchmark]: Boogie Procedure Inliner took 56.18 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-20 10:36:50,300 INFO L168 Benchmark]: Boogie Preprocessor took 66.01 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-11-20 10:36:50,301 INFO L168 Benchmark]: RCFGBuilder took 1131.09 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 65.4 MB). Peak memory consumption was 65.4 MB. Max. memory is 11.5 GB. [2019-11-20 10:36:50,301 INFO L168 Benchmark]: BuchiAutomizer took 14017.84 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 245.4 MB). Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 58.3 MB). Peak memory consumption was 303.6 MB. Max. memory is 11.5 GB. [2019-11-20 10:36:50,302 INFO L168 Benchmark]: Witness Printer took 64.25 ms. Allocated memory is still 1.4 GB. Free memory was 1.0 GB in the beginning and 999.2 MB in the end (delta: 3.5 MB). Peak memory consumption was 3.5 MB. Max. memory is 11.5 GB. [2019-11-20 10:36:50,304 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.32 ms. Allocated memory is still 1.0 GB. Free memory is still 962.2 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 485.34 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 143.7 MB). Free memory was 944.7 MB in the beginning and 1.1 GB in the end (delta: -187.0 MB). Peak memory consumption was 23.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 56.18 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 66.01 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1131.09 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 65.4 MB). Peak memory consumption was 65.4 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 14017.84 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 245.4 MB). Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 58.3 MB). Peak memory consumption was 303.6 MB. Max. memory is 11.5 GB. * Witness Printer took 64.25 ms. Allocated memory is still 1.4 GB. Free memory was 1.0 GB in the beginning and 999.2 MB in the end (delta: 3.5 MB). Peak memory consumption was 3.5 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 22 terminating modules (20 trivial, 2 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function -1 * E_3 + 1 and consists of 3 locations. One deterministic module has affine ranking function -1 * T2_E + 1 and consists of 3 locations. 20 modules have a trivial ranking function, the largest among these consists of 6 locations. The remainder module has 8338 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 13.9s and 21 iterations. TraceHistogramMax:2. Analysis of lassos took 9.3s. Construction of modules took 0.9s. Büchi inclusion checks took 1.3s. Highest rank in rank-based complementation 3. Minimization of det autom 14. Minimization of nondet autom 8. Automata minimization 1.1s AutomataMinimizationTime, 22 MinimizatonAttempts, 7155 StatesRemovedByMinimization, 13 NontrivialMinimizations. Non-live state removal took 0.7s Buchi closure took 0.0s. Biggest automaton had 8338 states and ocurred in iteration 20. Nontrivial modules had stage [2, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 6/6 HoareTripleCheckerStatistics: 9090 SDtfs, 10270 SDslu, 9235 SDs, 0 SdLazy, 577 SolverSat, 206 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.9s Time LassoAnalysisResults: nont1 unkn0 SFLI5 SFLT0 conc3 concLT1 SILN1 SILU0 SILI9 SILT1 lasso0 LassoPreprocessingBenchmarks: Lassos: inital151 mio100 ax100 hnf100 lsp7 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq209 hnf86 smp100 dnf189 smp57 tf109 neg96 sie108 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 13ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 18 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 2 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.5s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 331]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {__retres1=0, t3_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@380facf6=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@77ade156=0, tmp=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@17386d55=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@735f220=0, __retres1=0, kernel_st=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@d036443=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@55ff09e2=0, t2_st=0, E_3=2, \result=0, E_1=2, tmp_ndt_2=0, \result=0, \result=0, tmp_ndt_4=0, m_st=0, tmp___2=0, tmp___0=0, t3_pc=0, tmp=0, __retres1=0, m_pc=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6c7318a=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, E_2=2, T1_E=2, __retres1=1, tmp_ndt_1=0, M_E=2, tmp=0, tmp_ndt_3=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@75d3b450=0, __retres1=0, t2_i=1, t3_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@66e6b800=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3fd2475=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@782cc3dd=0, t1_st=0, t2_pc=0, tmp___1=0, T3_E=2, t1_i=1, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 331]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int m_st ; [L20] int t1_st ; [L21] int t2_st ; [L22] int t3_st ; [L23] int m_i ; [L24] int t1_i ; [L25] int t2_i ; [L26] int t3_i ; [L27] int M_E = 2; [L28] int T1_E = 2; [L29] int T2_E = 2; [L30] int T3_E = 2; [L31] int E_1 = 2; [L32] int E_2 = 2; [L33] int E_3 = 2; [L687] int __retres1 ; [L600] m_i = 1 [L601] t1_i = 1 [L602] t2_i = 1 [L603] t3_i = 1 [L628] int kernel_st ; [L629] int tmp ; [L630] int tmp___0 ; [L634] kernel_st = 0 [L271] COND TRUE m_i == 1 [L272] m_st = 0 [L276] COND TRUE t1_i == 1 [L277] t1_st = 0 [L281] COND TRUE t2_i == 1 [L282] t2_st = 0 [L286] COND TRUE t3_i == 1 [L287] t3_st = 0 [L408] COND FALSE !(M_E == 0) [L413] COND FALSE !(T1_E == 0) [L418] COND FALSE !(T2_E == 0) [L423] COND FALSE !(T3_E == 0) [L428] COND FALSE !(E_1 == 0) [L433] COND FALSE !(E_2 == 0) [L438] COND FALSE !(E_3 == 0) [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; [L184] int __retres1 ; [L187] COND FALSE !(m_pc == 1) [L197] __retres1 = 0 [L199] return (__retres1); [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) [L203] int __retres1 ; [L206] COND FALSE !(t1_pc == 1) [L216] __retres1 = 0 [L218] return (__retres1); [L506] tmp___0 = is_transmit1_triggered() [L508] COND FALSE !(\read(tmp___0)) [L222] int __retres1 ; [L225] COND FALSE !(t2_pc == 1) [L235] __retres1 = 0 [L237] return (__retres1); [L514] tmp___1 = is_transmit2_triggered() [L516] COND FALSE !(\read(tmp___1)) [L241] int __retres1 ; [L244] COND FALSE !(t3_pc == 1) [L254] __retres1 = 0 [L256] return (__retres1); [L522] tmp___2 = is_transmit3_triggered() [L524] COND FALSE !(\read(tmp___2)) [L451] COND FALSE !(M_E == 1) [L456] COND FALSE !(T1_E == 1) [L461] COND FALSE !(T2_E == 1) [L466] COND FALSE !(T3_E == 1) [L471] COND FALSE !(E_1 == 1) [L476] COND FALSE !(E_2 == 1) [L481] COND FALSE !(E_3 == 1) [L642] COND TRUE 1 [L645] kernel_st = 1 [L327] int tmp ; Loop: [L331] COND TRUE 1 [L296] int __retres1 ; [L299] COND TRUE m_st == 0 [L300] __retres1 = 1 [L322] return (__retres1); [L334] tmp = exists_runnable_thread() [L336] COND TRUE \read(tmp) [L341] COND TRUE m_st == 0 [L342] int tmp_ndt_1; [L343] tmp_ndt_1 = __VERIFIER_nondet_int() [L344] COND FALSE !(\read(tmp_ndt_1)) [L355] COND TRUE t1_st == 0 [L356] int tmp_ndt_2; [L357] tmp_ndt_2 = __VERIFIER_nondet_int() [L358] COND FALSE !(\read(tmp_ndt_2)) [L369] COND TRUE t2_st == 0 [L370] int tmp_ndt_3; [L371] tmp_ndt_3 = __VERIFIER_nondet_int() [L372] COND FALSE !(\read(tmp_ndt_3)) [L383] COND TRUE t3_st == 0 [L384] int tmp_ndt_4; [L385] tmp_ndt_4 = __VERIFIER_nondet_int() [L386] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...