./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.03.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 6b5699aa Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_026b7c82-44c5-4eb3-8fea-831f73543f90/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_026b7c82-44c5-4eb3-8fea-831f73543f90/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_026b7c82-44c5-4eb3-8fea-831f73543f90/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_026b7c82-44c5-4eb3-8fea-831f73543f90/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.03.cil.c -s /tmp/vcloud-vcloud-master/worker/run_dir_026b7c82-44c5-4eb3-8fea-831f73543f90/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_026b7c82-44c5-4eb3-8fea-831f73543f90/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 447c919af4e106e36f468570351956f4c77293d2 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.24-6b5699a [2019-11-25 08:56:12,474 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-25 08:56:12,475 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-25 08:56:12,485 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-25 08:56:12,485 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-25 08:56:12,486 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-25 08:56:12,487 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-25 08:56:12,489 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-25 08:56:12,491 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-25 08:56:12,492 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-25 08:56:12,493 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-25 08:56:12,494 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-25 08:56:12,494 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-25 08:56:12,495 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-25 08:56:12,496 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-25 08:56:12,497 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-25 08:56:12,498 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-25 08:56:12,499 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-25 08:56:12,501 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-25 08:56:12,503 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-25 08:56:12,504 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-25 08:56:12,505 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-25 08:56:12,506 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-25 08:56:12,507 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-25 08:56:12,509 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-25 08:56:12,510 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-25 08:56:12,510 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-25 08:56:12,511 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-25 08:56:12,511 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-25 08:56:12,512 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-25 08:56:12,512 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-25 08:56:12,513 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-25 08:56:12,513 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-25 08:56:12,514 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-25 08:56:12,515 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-25 08:56:12,515 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-25 08:56:12,515 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-25 08:56:12,516 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-25 08:56:12,516 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-25 08:56:12,517 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-25 08:56:12,517 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-25 08:56:12,518 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_026b7c82-44c5-4eb3-8fea-831f73543f90/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-25 08:56:12,530 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-25 08:56:12,530 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-25 08:56:12,531 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-25 08:56:12,531 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-25 08:56:12,531 INFO L138 SettingsManager]: * Use SBE=true [2019-11-25 08:56:12,532 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-25 08:56:12,532 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-25 08:56:12,532 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-25 08:56:12,532 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-25 08:56:12,532 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-25 08:56:12,533 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-25 08:56:12,533 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-25 08:56:12,533 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-25 08:56:12,533 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-25 08:56:12,533 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-25 08:56:12,533 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-25 08:56:12,534 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-25 08:56:12,534 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-25 08:56:12,534 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-25 08:56:12,534 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-25 08:56:12,534 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-25 08:56:12,535 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-25 08:56:12,535 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-25 08:56:12,535 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-25 08:56:12,535 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-25 08:56:12,535 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-25 08:56:12,535 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-25 08:56:12,536 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-25 08:56:12,536 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_026b7c82-44c5-4eb3-8fea-831f73543f90/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 447c919af4e106e36f468570351956f4c77293d2 [2019-11-25 08:56:12,689 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-25 08:56:12,699 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-25 08:56:12,701 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-25 08:56:12,703 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-25 08:56:12,703 INFO L275 PluginConnector]: CDTParser initialized [2019-11-25 08:56:12,703 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_026b7c82-44c5-4eb3-8fea-831f73543f90/bin/uautomizer/../../sv-benchmarks/c/systemc/transmitter.03.cil.c [2019-11-25 08:56:12,750 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_026b7c82-44c5-4eb3-8fea-831f73543f90/bin/uautomizer/data/05b31013a/44db7f0f66ef443ca45ab6cde2954782/FLAG5af0e983c [2019-11-25 08:56:13,156 INFO L306 CDTParser]: Found 1 translation units. [2019-11-25 08:56:13,156 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_026b7c82-44c5-4eb3-8fea-831f73543f90/sv-benchmarks/c/systemc/transmitter.03.cil.c [2019-11-25 08:56:13,168 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_026b7c82-44c5-4eb3-8fea-831f73543f90/bin/uautomizer/data/05b31013a/44db7f0f66ef443ca45ab6cde2954782/FLAG5af0e983c [2019-11-25 08:56:13,184 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_026b7c82-44c5-4eb3-8fea-831f73543f90/bin/uautomizer/data/05b31013a/44db7f0f66ef443ca45ab6cde2954782 [2019-11-25 08:56:13,189 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-25 08:56:13,190 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-25 08:56:13,196 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-25 08:56:13,196 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-25 08:56:13,200 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-25 08:56:13,200 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 25.11 08:56:13" (1/1) ... [2019-11-25 08:56:13,203 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6c23547a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:56:13, skipping insertion in model container [2019-11-25 08:56:13,203 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 25.11 08:56:13" (1/1) ... [2019-11-25 08:56:13,214 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-11-25 08:56:13,260 INFO L179 MainTranslator]: Built tables and reachable declarations [2019-11-25 08:56:13,556 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-25 08:56:13,568 INFO L201 MainTranslator]: Completed pre-run [2019-11-25 08:56:13,607 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-25 08:56:13,635 INFO L205 MainTranslator]: Completed translation [2019-11-25 08:56:13,636 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:56:13 WrapperNode [2019-11-25 08:56:13,636 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-25 08:56:13,636 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-25 08:56:13,636 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-25 08:56:13,637 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-25 08:56:13,643 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:56:13" (1/1) ... [2019-11-25 08:56:13,649 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:56:13" (1/1) ... [2019-11-25 08:56:13,696 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-25 08:56:13,696 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-25 08:56:13,696 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-25 08:56:13,696 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-25 08:56:13,703 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:56:13" (1/1) ... [2019-11-25 08:56:13,703 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:56:13" (1/1) ... [2019-11-25 08:56:13,707 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:56:13" (1/1) ... [2019-11-25 08:56:13,707 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:56:13" (1/1) ... [2019-11-25 08:56:13,718 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:56:13" (1/1) ... [2019-11-25 08:56:13,743 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:56:13" (1/1) ... [2019-11-25 08:56:13,746 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:56:13" (1/1) ... [2019-11-25 08:56:13,751 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-25 08:56:13,752 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-25 08:56:13,752 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-25 08:56:13,752 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-25 08:56:13,753 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:56:13" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_026b7c82-44c5-4eb3-8fea-831f73543f90/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-25 08:56:13,817 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-25 08:56:13,817 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-25 08:56:14,675 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-25 08:56:14,675 INFO L284 CfgBuilder]: Removed 119 assume(true) statements. [2019-11-25 08:56:14,676 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 08:56:14 BoogieIcfgContainer [2019-11-25 08:56:14,676 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-25 08:56:14,677 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-25 08:56:14,678 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-25 08:56:14,681 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-25 08:56:14,681 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 25.11 08:56:13" (1/3) ... [2019-11-25 08:56:14,684 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@77801283 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 25.11 08:56:14, skipping insertion in model container [2019-11-25 08:56:14,685 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:56:13" (2/3) ... [2019-11-25 08:56:14,685 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@77801283 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 25.11 08:56:14, skipping insertion in model container [2019-11-25 08:56:14,685 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 08:56:14" (3/3) ... [2019-11-25 08:56:14,687 INFO L109 eAbstractionObserver]: Analyzing ICFG transmitter.03.cil.c [2019-11-25 08:56:14,696 INFO L153 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-25 08:56:14,702 INFO L165 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-11-25 08:56:14,710 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-11-25 08:56:14,733 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-25 08:56:14,733 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-25 08:56:14,733 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-25 08:56:14,734 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-25 08:56:14,734 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-25 08:56:14,734 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-25 08:56:14,734 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-25 08:56:14,734 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-25 08:56:14,755 INFO L276 IsEmpty]: Start isEmpty. Operand 276 states. [2019-11-25 08:56:14,762 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-25 08:56:14,762 INFO L402 BasicCegarLoop]: Found error trace [2019-11-25 08:56:14,763 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:56:14,763 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-25 08:56:14,767 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:56:14,767 INFO L82 PathProgramCache]: Analyzing trace with hash -1838342379, now seen corresponding path program 1 times [2019-11-25 08:56:14,773 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:56:14,774 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [337417250] [2019-11-25 08:56:14,774 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:56:14,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:56:14,912 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:56:14,913 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [337417250] [2019-11-25 08:56:14,914 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:56:14,914 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:56:14,915 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2051507118] [2019-11-25 08:56:14,920 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-25 08:56:14,920 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:56:14,932 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:56:14,933 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:14,935 INFO L87 Difference]: Start difference. First operand 276 states. Second operand 3 states. [2019-11-25 08:56:15,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:56:15,014 INFO L93 Difference]: Finished difference Result 547 states and 857 transitions. [2019-11-25 08:56:15,021 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:56:15,022 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-25 08:56:15,023 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-25 08:56:15,047 INFO L225 Difference]: With dead ends: 547 [2019-11-25 08:56:15,047 INFO L226 Difference]: Without dead ends: 272 [2019-11-25 08:56:15,051 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:15,067 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 272 states. [2019-11-25 08:56:15,104 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 272 to 272. [2019-11-25 08:56:15,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 272 states. [2019-11-25 08:56:15,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 272 states to 272 states and 412 transitions. [2019-11-25 08:56:15,108 INFO L78 Accepts]: Start accepts. Automaton has 272 states and 412 transitions. Word has length 61 [2019-11-25 08:56:15,108 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-25 08:56:15,108 INFO L462 AbstractCegarLoop]: Abstraction has 272 states and 412 transitions. [2019-11-25 08:56:15,109 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-25 08:56:15,109 INFO L276 IsEmpty]: Start isEmpty. Operand 272 states and 412 transitions. [2019-11-25 08:56:15,111 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-25 08:56:15,111 INFO L402 BasicCegarLoop]: Found error trace [2019-11-25 08:56:15,111 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:56:15,111 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-25 08:56:15,112 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:56:15,112 INFO L82 PathProgramCache]: Analyzing trace with hash 1195707667, now seen corresponding path program 1 times [2019-11-25 08:56:15,112 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:56:15,112 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2010112930] [2019-11-25 08:56:15,112 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:56:15,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:56:15,167 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:56:15,167 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2010112930] [2019-11-25 08:56:15,167 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:56:15,168 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:56:15,168 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1640759324] [2019-11-25 08:56:15,169 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-25 08:56:15,169 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:56:15,170 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:56:15,170 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:15,170 INFO L87 Difference]: Start difference. First operand 272 states and 412 transitions. Second operand 3 states. [2019-11-25 08:56:15,252 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:56:15,252 INFO L93 Difference]: Finished difference Result 730 states and 1104 transitions. [2019-11-25 08:56:15,252 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:56:15,253 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-25 08:56:15,253 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-25 08:56:15,256 INFO L225 Difference]: With dead ends: 730 [2019-11-25 08:56:15,256 INFO L226 Difference]: Without dead ends: 466 [2019-11-25 08:56:15,258 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:15,259 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 466 states. [2019-11-25 08:56:15,287 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 466 to 464. [2019-11-25 08:56:15,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-11-25 08:56:15,289 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 694 transitions. [2019-11-25 08:56:15,289 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 694 transitions. Word has length 61 [2019-11-25 08:56:15,290 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-25 08:56:15,290 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 694 transitions. [2019-11-25 08:56:15,290 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-25 08:56:15,290 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 694 transitions. [2019-11-25 08:56:15,292 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-25 08:56:15,292 INFO L402 BasicCegarLoop]: Found error trace [2019-11-25 08:56:15,292 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:56:15,292 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-25 08:56:15,293 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:56:15,293 INFO L82 PathProgramCache]: Analyzing trace with hash 266288339, now seen corresponding path program 1 times [2019-11-25 08:56:15,293 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:56:15,293 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1751510401] [2019-11-25 08:56:15,293 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:56:15,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:56:15,331 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:56:15,332 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1751510401] [2019-11-25 08:56:15,332 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:56:15,332 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:56:15,332 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1869595998] [2019-11-25 08:56:15,333 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-25 08:56:15,333 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:56:15,333 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:56:15,333 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:15,334 INFO L87 Difference]: Start difference. First operand 464 states and 694 transitions. Second operand 3 states. [2019-11-25 08:56:15,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:56:15,368 INFO L93 Difference]: Finished difference Result 919 states and 1375 transitions. [2019-11-25 08:56:15,369 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:56:15,369 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-25 08:56:15,369 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-25 08:56:15,372 INFO L225 Difference]: With dead ends: 919 [2019-11-25 08:56:15,372 INFO L226 Difference]: Without dead ends: 464 [2019-11-25 08:56:15,373 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:15,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-11-25 08:56:15,393 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-11-25 08:56:15,393 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-11-25 08:56:15,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 686 transitions. [2019-11-25 08:56:15,395 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 686 transitions. Word has length 61 [2019-11-25 08:56:15,395 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-25 08:56:15,395 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 686 transitions. [2019-11-25 08:56:15,395 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-25 08:56:15,396 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 686 transitions. [2019-11-25 08:56:15,398 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-25 08:56:15,398 INFO L402 BasicCegarLoop]: Found error trace [2019-11-25 08:56:15,398 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:56:15,398 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-25 08:56:15,398 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:56:15,399 INFO L82 PathProgramCache]: Analyzing trace with hash 710189013, now seen corresponding path program 1 times [2019-11-25 08:56:15,399 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:56:15,399 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [141934507] [2019-11-25 08:56:15,399 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:56:15,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:56:15,433 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:56:15,433 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [141934507] [2019-11-25 08:56:15,434 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:56:15,434 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:56:15,434 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1896370023] [2019-11-25 08:56:15,435 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-25 08:56:15,435 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:56:15,435 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:56:15,435 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:15,435 INFO L87 Difference]: Start difference. First operand 464 states and 686 transitions. Second operand 3 states. [2019-11-25 08:56:15,468 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:56:15,468 INFO L93 Difference]: Finished difference Result 918 states and 1358 transitions. [2019-11-25 08:56:15,468 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:56:15,468 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-25 08:56:15,469 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-25 08:56:15,471 INFO L225 Difference]: With dead ends: 918 [2019-11-25 08:56:15,472 INFO L226 Difference]: Without dead ends: 464 [2019-11-25 08:56:15,473 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:15,474 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-11-25 08:56:15,492 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-11-25 08:56:15,492 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-11-25 08:56:15,494 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 678 transitions. [2019-11-25 08:56:15,495 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 678 transitions. Word has length 61 [2019-11-25 08:56:15,495 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-25 08:56:15,495 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 678 transitions. [2019-11-25 08:56:15,495 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-25 08:56:15,495 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 678 transitions. [2019-11-25 08:56:15,497 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-25 08:56:15,497 INFO L402 BasicCegarLoop]: Found error trace [2019-11-25 08:56:15,497 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:56:15,497 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-25 08:56:15,498 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:56:15,498 INFO L82 PathProgramCache]: Analyzing trace with hash -1623736427, now seen corresponding path program 1 times [2019-11-25 08:56:15,498 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:56:15,498 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [355989151] [2019-11-25 08:56:15,498 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:56:15,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:56:15,536 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:56:15,536 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [355989151] [2019-11-25 08:56:15,536 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:56:15,537 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:56:15,537 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1907128691] [2019-11-25 08:56:15,537 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-25 08:56:15,538 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:56:15,538 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:56:15,538 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:15,538 INFO L87 Difference]: Start difference. First operand 464 states and 678 transitions. Second operand 3 states. [2019-11-25 08:56:15,577 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:56:15,577 INFO L93 Difference]: Finished difference Result 917 states and 1341 transitions. [2019-11-25 08:56:15,578 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:56:15,578 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-25 08:56:15,578 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-25 08:56:15,581 INFO L225 Difference]: With dead ends: 917 [2019-11-25 08:56:15,581 INFO L226 Difference]: Without dead ends: 464 [2019-11-25 08:56:15,583 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:15,584 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-11-25 08:56:15,604 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-11-25 08:56:15,604 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-11-25 08:56:15,606 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 670 transitions. [2019-11-25 08:56:15,607 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 670 transitions. Word has length 61 [2019-11-25 08:56:15,607 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-25 08:56:15,607 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 670 transitions. [2019-11-25 08:56:15,607 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-25 08:56:15,607 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 670 transitions. [2019-11-25 08:56:15,610 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-25 08:56:15,610 INFO L402 BasicCegarLoop]: Found error trace [2019-11-25 08:56:15,611 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:56:15,611 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-25 08:56:15,611 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:56:15,612 INFO L82 PathProgramCache]: Analyzing trace with hash -175003691, now seen corresponding path program 1 times [2019-11-25 08:56:15,612 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:56:15,612 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [139275988] [2019-11-25 08:56:15,612 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:56:15,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:56:15,668 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:56:15,668 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [139275988] [2019-11-25 08:56:15,669 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:56:15,670 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:56:15,670 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2000093549] [2019-11-25 08:56:15,670 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-25 08:56:15,671 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:56:15,671 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:56:15,671 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:15,671 INFO L87 Difference]: Start difference. First operand 464 states and 670 transitions. Second operand 3 states. [2019-11-25 08:56:15,728 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:56:15,730 INFO L93 Difference]: Finished difference Result 916 states and 1324 transitions. [2019-11-25 08:56:15,730 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:56:15,730 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-25 08:56:15,731 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-25 08:56:15,733 INFO L225 Difference]: With dead ends: 916 [2019-11-25 08:56:15,734 INFO L226 Difference]: Without dead ends: 464 [2019-11-25 08:56:15,736 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:15,737 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-11-25 08:56:15,757 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-11-25 08:56:15,757 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-11-25 08:56:15,759 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 654 transitions. [2019-11-25 08:56:15,760 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 654 transitions. Word has length 61 [2019-11-25 08:56:15,760 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-25 08:56:15,761 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 654 transitions. [2019-11-25 08:56:15,761 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-25 08:56:15,761 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 654 transitions. [2019-11-25 08:56:15,763 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-25 08:56:15,763 INFO L402 BasicCegarLoop]: Found error trace [2019-11-25 08:56:15,763 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:56:15,764 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-25 08:56:15,764 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:56:15,767 INFO L82 PathProgramCache]: Analyzing trace with hash -1945036492, now seen corresponding path program 1 times [2019-11-25 08:56:15,768 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:56:15,768 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [617580878] [2019-11-25 08:56:15,768 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:56:15,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:56:15,829 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:56:15,832 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [617580878] [2019-11-25 08:56:15,832 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:56:15,832 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:56:15,833 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1175097696] [2019-11-25 08:56:15,834 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-25 08:56:15,834 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:56:15,842 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:56:15,843 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:15,843 INFO L87 Difference]: Start difference. First operand 464 states and 654 transitions. Second operand 3 states. [2019-11-25 08:56:15,914 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:56:15,914 INFO L93 Difference]: Finished difference Result 914 states and 1289 transitions. [2019-11-25 08:56:15,915 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:56:15,915 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-25 08:56:15,915 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-25 08:56:15,918 INFO L225 Difference]: With dead ends: 914 [2019-11-25 08:56:15,918 INFO L226 Difference]: Without dead ends: 464 [2019-11-25 08:56:15,919 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:15,920 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-11-25 08:56:15,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-11-25 08:56:15,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-11-25 08:56:15,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 638 transitions. [2019-11-25 08:56:15,941 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 638 transitions. Word has length 61 [2019-11-25 08:56:15,941 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-25 08:56:15,942 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 638 transitions. [2019-11-25 08:56:15,942 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-25 08:56:15,942 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 638 transitions. [2019-11-25 08:56:15,943 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-25 08:56:15,943 INFO L402 BasicCegarLoop]: Found error trace [2019-11-25 08:56:15,943 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:56:15,943 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-25 08:56:15,944 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:56:15,944 INFO L82 PathProgramCache]: Analyzing trace with hash -1902661357, now seen corresponding path program 1 times [2019-11-25 08:56:15,944 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:56:15,945 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1026847419] [2019-11-25 08:56:15,945 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:56:15,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:56:16,002 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:56:16,002 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1026847419] [2019-11-25 08:56:16,003 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:56:16,003 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:56:16,003 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1052054934] [2019-11-25 08:56:16,003 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-25 08:56:16,003 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:56:16,004 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:56:16,004 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:16,004 INFO L87 Difference]: Start difference. First operand 464 states and 638 transitions. Second operand 3 states. [2019-11-25 08:56:16,049 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:56:16,050 INFO L93 Difference]: Finished difference Result 915 states and 1259 transitions. [2019-11-25 08:56:16,051 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:56:16,051 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-25 08:56:16,051 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-25 08:56:16,054 INFO L225 Difference]: With dead ends: 915 [2019-11-25 08:56:16,054 INFO L226 Difference]: Without dead ends: 464 [2019-11-25 08:56:16,055 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:16,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-11-25 08:56:16,072 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-11-25 08:56:16,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-11-25 08:56:16,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 622 transitions. [2019-11-25 08:56:16,074 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 622 transitions. Word has length 61 [2019-11-25 08:56:16,074 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-25 08:56:16,075 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 622 transitions. [2019-11-25 08:56:16,075 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-25 08:56:16,075 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 622 transitions. [2019-11-25 08:56:16,075 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-25 08:56:16,076 INFO L402 BasicCegarLoop]: Found error trace [2019-11-25 08:56:16,076 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:56:16,076 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-25 08:56:16,076 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:56:16,076 INFO L82 PathProgramCache]: Analyzing trace with hash 398161233, now seen corresponding path program 1 times [2019-11-25 08:56:16,077 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:56:16,077 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1729119956] [2019-11-25 08:56:16,077 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:56:16,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:56:16,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:56:16,113 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1729119956] [2019-11-25 08:56:16,113 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:56:16,113 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:56:16,114 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [760111137] [2019-11-25 08:56:16,115 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-25 08:56:16,115 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:56:16,115 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:56:16,116 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:16,116 INFO L87 Difference]: Start difference. First operand 464 states and 622 transitions. Second operand 3 states. [2019-11-25 08:56:16,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:56:16,186 INFO L93 Difference]: Finished difference Result 1299 states and 1732 transitions. [2019-11-25 08:56:16,186 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:56:16,187 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-25 08:56:16,187 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-25 08:56:16,192 INFO L225 Difference]: With dead ends: 1299 [2019-11-25 08:56:16,192 INFO L226 Difference]: Without dead ends: 884 [2019-11-25 08:56:16,193 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:16,194 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 884 states. [2019-11-25 08:56:16,223 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 884 to 834. [2019-11-25 08:56:16,224 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 834 states. [2019-11-25 08:56:16,227 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 834 states to 834 states and 1099 transitions. [2019-11-25 08:56:16,227 INFO L78 Accepts]: Start accepts. Automaton has 834 states and 1099 transitions. Word has length 61 [2019-11-25 08:56:16,228 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-25 08:56:16,228 INFO L462 AbstractCegarLoop]: Abstraction has 834 states and 1099 transitions. [2019-11-25 08:56:16,229 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-25 08:56:16,229 INFO L276 IsEmpty]: Start isEmpty. Operand 834 states and 1099 transitions. [2019-11-25 08:56:16,230 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2019-11-25 08:56:16,230 INFO L402 BasicCegarLoop]: Found error trace [2019-11-25 08:56:16,230 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:56:16,230 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-25 08:56:16,230 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:56:16,231 INFO L82 PathProgramCache]: Analyzing trace with hash -276756042, now seen corresponding path program 1 times [2019-11-25 08:56:16,231 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:56:16,231 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1553806393] [2019-11-25 08:56:16,231 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:56:16,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:56:16,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:56:16,268 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1553806393] [2019-11-25 08:56:16,269 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:56:16,269 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:56:16,269 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [900275336] [2019-11-25 08:56:16,269 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-25 08:56:16,269 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:56:16,270 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:56:16,270 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:16,270 INFO L87 Difference]: Start difference. First operand 834 states and 1099 transitions. Second operand 3 states. [2019-11-25 08:56:16,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:56:16,359 INFO L93 Difference]: Finished difference Result 2234 states and 2945 transitions. [2019-11-25 08:56:16,360 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:56:16,360 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 62 [2019-11-25 08:56:16,360 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-25 08:56:16,368 INFO L225 Difference]: With dead ends: 2234 [2019-11-25 08:56:16,368 INFO L226 Difference]: Without dead ends: 1494 [2019-11-25 08:56:16,369 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:16,371 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1494 states. [2019-11-25 08:56:16,421 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1494 to 1424. [2019-11-25 08:56:16,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1424 states. [2019-11-25 08:56:16,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1424 states to 1424 states and 1862 transitions. [2019-11-25 08:56:16,427 INFO L78 Accepts]: Start accepts. Automaton has 1424 states and 1862 transitions. Word has length 62 [2019-11-25 08:56:16,427 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-25 08:56:16,429 INFO L462 AbstractCegarLoop]: Abstraction has 1424 states and 1862 transitions. [2019-11-25 08:56:16,429 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-25 08:56:16,430 INFO L276 IsEmpty]: Start isEmpty. Operand 1424 states and 1862 transitions. [2019-11-25 08:56:16,430 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-11-25 08:56:16,431 INFO L402 BasicCegarLoop]: Found error trace [2019-11-25 08:56:16,431 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:56:16,431 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-25 08:56:16,431 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:56:16,431 INFO L82 PathProgramCache]: Analyzing trace with hash -2032591659, now seen corresponding path program 1 times [2019-11-25 08:56:16,432 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:56:16,432 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1301330876] [2019-11-25 08:56:16,432 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:56:16,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:56:16,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:56:16,466 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1301330876] [2019-11-25 08:56:16,466 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:56:16,466 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:56:16,466 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1094929882] [2019-11-25 08:56:16,467 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-25 08:56:16,467 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:56:16,467 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:56:16,467 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:16,467 INFO L87 Difference]: Start difference. First operand 1424 states and 1862 transitions. Second operand 3 states. [2019-11-25 08:56:16,591 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:56:16,591 INFO L93 Difference]: Finished difference Result 3972 states and 5180 transitions. [2019-11-25 08:56:16,591 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:56:16,592 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 63 [2019-11-25 08:56:16,593 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-25 08:56:16,606 INFO L225 Difference]: With dead ends: 3972 [2019-11-25 08:56:16,606 INFO L226 Difference]: Without dead ends: 2642 [2019-11-25 08:56:16,609 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:16,612 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2642 states. [2019-11-25 08:56:16,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2642 to 2560. [2019-11-25 08:56:16,705 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2560 states. [2019-11-25 08:56:16,714 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2560 states to 2560 states and 3314 transitions. [2019-11-25 08:56:16,714 INFO L78 Accepts]: Start accepts. Automaton has 2560 states and 3314 transitions. Word has length 63 [2019-11-25 08:56:16,715 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-25 08:56:16,715 INFO L462 AbstractCegarLoop]: Abstraction has 2560 states and 3314 transitions. [2019-11-25 08:56:16,715 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-25 08:56:16,716 INFO L276 IsEmpty]: Start isEmpty. Operand 2560 states and 3314 transitions. [2019-11-25 08:56:16,717 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-11-25 08:56:16,717 INFO L402 BasicCegarLoop]: Found error trace [2019-11-25 08:56:16,717 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:56:16,717 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-25 08:56:16,717 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:56:16,718 INFO L82 PathProgramCache]: Analyzing trace with hash -1324102959, now seen corresponding path program 1 times [2019-11-25 08:56:16,718 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:56:16,718 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [696321891] [2019-11-25 08:56:16,718 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:56:16,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:56:16,754 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:56:16,754 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [696321891] [2019-11-25 08:56:16,754 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:56:16,754 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:56:16,754 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [235931356] [2019-11-25 08:56:16,754 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-25 08:56:16,754 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:56:16,755 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:56:16,755 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:16,755 INFO L87 Difference]: Start difference. First operand 2560 states and 3314 transitions. Second operand 3 states. [2019-11-25 08:56:16,844 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:56:16,845 INFO L93 Difference]: Finished difference Result 4968 states and 6441 transitions. [2019-11-25 08:56:16,845 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:56:16,845 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 63 [2019-11-25 08:56:16,846 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-25 08:56:16,858 INFO L225 Difference]: With dead ends: 4968 [2019-11-25 08:56:16,858 INFO L226 Difference]: Without dead ends: 2474 [2019-11-25 08:56:16,861 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:16,865 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2474 states. [2019-11-25 08:56:16,950 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2474 to 2474. [2019-11-25 08:56:16,950 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2474 states. [2019-11-25 08:56:16,959 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2474 states to 2474 states and 3208 transitions. [2019-11-25 08:56:16,959 INFO L78 Accepts]: Start accepts. Automaton has 2474 states and 3208 transitions. Word has length 63 [2019-11-25 08:56:16,959 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-25 08:56:16,960 INFO L462 AbstractCegarLoop]: Abstraction has 2474 states and 3208 transitions. [2019-11-25 08:56:16,960 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-25 08:56:16,960 INFO L276 IsEmpty]: Start isEmpty. Operand 2474 states and 3208 transitions. [2019-11-25 08:56:16,961 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2019-11-25 08:56:16,961 INFO L402 BasicCegarLoop]: Found error trace [2019-11-25 08:56:16,961 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:56:16,961 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-25 08:56:16,962 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:56:16,962 INFO L82 PathProgramCache]: Analyzing trace with hash -1607983393, now seen corresponding path program 1 times [2019-11-25 08:56:16,962 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:56:16,962 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [478876184] [2019-11-25 08:56:16,962 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:56:16,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:56:17,019 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:56:17,020 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [478876184] [2019-11-25 08:56:17,020 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:56:17,020 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:56:17,021 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [123509340] [2019-11-25 08:56:17,021 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-25 08:56:17,021 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:56:17,021 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:56:17,022 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:17,022 INFO L87 Difference]: Start difference. First operand 2474 states and 3208 transitions. Second operand 3 states. [2019-11-25 08:56:17,211 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:56:17,212 INFO L93 Difference]: Finished difference Result 7190 states and 9333 transitions. [2019-11-25 08:56:17,212 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:56:17,212 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 64 [2019-11-25 08:56:17,212 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-25 08:56:17,236 INFO L225 Difference]: With dead ends: 7190 [2019-11-25 08:56:17,236 INFO L226 Difference]: Without dead ends: 4786 [2019-11-25 08:56:17,240 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:17,246 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4786 states. [2019-11-25 08:56:17,405 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4786 to 4754. [2019-11-25 08:56:17,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4754 states. [2019-11-25 08:56:17,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4754 states to 4754 states and 6114 transitions. [2019-11-25 08:56:17,419 INFO L78 Accepts]: Start accepts. Automaton has 4754 states and 6114 transitions. Word has length 64 [2019-11-25 08:56:17,419 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-25 08:56:17,419 INFO L462 AbstractCegarLoop]: Abstraction has 4754 states and 6114 transitions. [2019-11-25 08:56:17,420 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-25 08:56:17,420 INFO L276 IsEmpty]: Start isEmpty. Operand 4754 states and 6114 transitions. [2019-11-25 08:56:17,422 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2019-11-25 08:56:17,422 INFO L402 BasicCegarLoop]: Found error trace [2019-11-25 08:56:17,423 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:56:17,423 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-25 08:56:17,423 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:56:17,423 INFO L82 PathProgramCache]: Analyzing trace with hash 93244939, now seen corresponding path program 1 times [2019-11-25 08:56:17,424 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:56:17,424 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1932403169] [2019-11-25 08:56:17,424 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:56:17,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:56:17,457 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:56:17,457 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1932403169] [2019-11-25 08:56:17,457 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:56:17,458 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:56:17,458 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1859387168] [2019-11-25 08:56:17,458 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-25 08:56:17,459 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:56:17,459 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:56:17,459 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:17,459 INFO L87 Difference]: Start difference. First operand 4754 states and 6114 transitions. Second operand 3 states. [2019-11-25 08:56:17,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:56:17,792 INFO L93 Difference]: Finished difference Result 14046 states and 18043 transitions. [2019-11-25 08:56:17,792 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:56:17,792 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 81 [2019-11-25 08:56:17,792 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-25 08:56:17,837 INFO L225 Difference]: With dead ends: 14046 [2019-11-25 08:56:17,837 INFO L226 Difference]: Without dead ends: 9384 [2019-11-25 08:56:17,845 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:17,856 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9384 states. [2019-11-25 08:56:18,223 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9384 to 9384. [2019-11-25 08:56:18,223 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9384 states. [2019-11-25 08:56:18,246 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9384 states to 9384 states and 11994 transitions. [2019-11-25 08:56:18,246 INFO L78 Accepts]: Start accepts. Automaton has 9384 states and 11994 transitions. Word has length 81 [2019-11-25 08:56:18,247 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-25 08:56:18,247 INFO L462 AbstractCegarLoop]: Abstraction has 9384 states and 11994 transitions. [2019-11-25 08:56:18,247 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-25 08:56:18,247 INFO L276 IsEmpty]: Start isEmpty. Operand 9384 states and 11994 transitions. [2019-11-25 08:56:18,253 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-11-25 08:56:18,253 INFO L402 BasicCegarLoop]: Found error trace [2019-11-25 08:56:18,253 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:56:18,253 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-25 08:56:18,254 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:56:18,254 INFO L82 PathProgramCache]: Analyzing trace with hash -447123663, now seen corresponding path program 1 times [2019-11-25 08:56:18,254 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:56:18,254 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1971832163] [2019-11-25 08:56:18,255 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:56:18,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:56:18,311 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2019-11-25 08:56:18,311 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1971832163] [2019-11-25 08:56:18,311 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:56:18,312 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:56:18,312 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1467239939] [2019-11-25 08:56:18,312 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-25 08:56:18,312 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:56:18,313 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:56:18,313 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:18,313 INFO L87 Difference]: Start difference. First operand 9384 states and 11994 transitions. Second operand 3 states. [2019-11-25 08:56:18,684 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:56:18,684 INFO L93 Difference]: Finished difference Result 22768 states and 29084 transitions. [2019-11-25 08:56:18,684 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:56:18,684 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 110 [2019-11-25 08:56:18,685 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-25 08:56:18,729 INFO L225 Difference]: With dead ends: 22768 [2019-11-25 08:56:18,729 INFO L226 Difference]: Without dead ends: 13486 [2019-11-25 08:56:18,743 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:18,760 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13486 states. [2019-11-25 08:56:19,304 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13486 to 13420. [2019-11-25 08:56:19,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13420 states. [2019-11-25 08:56:19,325 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13420 states to 13420 states and 17034 transitions. [2019-11-25 08:56:19,325 INFO L78 Accepts]: Start accepts. Automaton has 13420 states and 17034 transitions. Word has length 110 [2019-11-25 08:56:19,325 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-25 08:56:19,325 INFO L462 AbstractCegarLoop]: Abstraction has 13420 states and 17034 transitions. [2019-11-25 08:56:19,326 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-25 08:56:19,326 INFO L276 IsEmpty]: Start isEmpty. Operand 13420 states and 17034 transitions. [2019-11-25 08:56:19,334 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-11-25 08:56:19,334 INFO L402 BasicCegarLoop]: Found error trace [2019-11-25 08:56:19,334 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:56:19,334 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-25 08:56:19,335 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:56:19,335 INFO L82 PathProgramCache]: Analyzing trace with hash -2122456675, now seen corresponding path program 1 times [2019-11-25 08:56:19,335 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:56:19,336 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [286731488] [2019-11-25 08:56:19,336 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:56:19,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:56:19,385 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2019-11-25 08:56:19,385 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [286731488] [2019-11-25 08:56:19,387 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:56:19,387 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:56:19,387 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1194382264] [2019-11-25 08:56:19,388 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-25 08:56:19,388 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:56:19,388 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:56:19,388 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:19,389 INFO L87 Difference]: Start difference. First operand 13420 states and 17034 transitions. Second operand 3 states. [2019-11-25 08:56:19,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:56:19,959 INFO L93 Difference]: Finished difference Result 32624 states and 41352 transitions. [2019-11-25 08:56:19,959 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:56:19,959 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 110 [2019-11-25 08:56:19,959 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-25 08:56:19,989 INFO L225 Difference]: With dead ends: 32624 [2019-11-25 08:56:19,990 INFO L226 Difference]: Without dead ends: 19278 [2019-11-25 08:56:20,006 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:20,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19278 states. [2019-11-25 08:56:20,456 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19278 to 19180. [2019-11-25 08:56:20,456 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19180 states. [2019-11-25 08:56:20,478 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19180 states to 19180 states and 24146 transitions. [2019-11-25 08:56:20,479 INFO L78 Accepts]: Start accepts. Automaton has 19180 states and 24146 transitions. Word has length 110 [2019-11-25 08:56:20,479 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-25 08:56:20,479 INFO L462 AbstractCegarLoop]: Abstraction has 19180 states and 24146 transitions. [2019-11-25 08:56:20,479 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-25 08:56:20,479 INFO L276 IsEmpty]: Start isEmpty. Operand 19180 states and 24146 transitions. [2019-11-25 08:56:20,496 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-11-25 08:56:20,496 INFO L402 BasicCegarLoop]: Found error trace [2019-11-25 08:56:20,497 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:56:20,497 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-25 08:56:20,497 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:56:20,498 INFO L82 PathProgramCache]: Analyzing trace with hash -4233773, now seen corresponding path program 1 times [2019-11-25 08:56:20,498 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:56:20,498 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [826714172] [2019-11-25 08:56:20,498 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:56:20,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:56:20,590 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-25 08:56:20,590 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [826714172] [2019-11-25 08:56:20,590 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:56:20,591 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-25 08:56:20,591 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1190463206] [2019-11-25 08:56:20,591 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-25 08:56:20,592 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:56:20,592 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-25 08:56:20,592 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-25 08:56:20,592 INFO L87 Difference]: Start difference. First operand 19180 states and 24146 transitions. Second operand 5 states. [2019-11-25 08:56:21,565 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:56:21,565 INFO L93 Difference]: Finished difference Result 47102 states and 59685 transitions. [2019-11-25 08:56:21,565 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-25 08:56:21,565 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 110 [2019-11-25 08:56:21,566 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-25 08:56:21,614 INFO L225 Difference]: With dead ends: 47102 [2019-11-25 08:56:21,614 INFO L226 Difference]: Without dead ends: 28012 [2019-11-25 08:56:21,640 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-25 08:56:21,662 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28012 states. [2019-11-25 08:56:22,420 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28012 to 19324. [2019-11-25 08:56:22,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19324 states. [2019-11-25 08:56:22,437 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19324 states to 19324 states and 23950 transitions. [2019-11-25 08:56:22,438 INFO L78 Accepts]: Start accepts. Automaton has 19324 states and 23950 transitions. Word has length 110 [2019-11-25 08:56:22,438 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-25 08:56:22,438 INFO L462 AbstractCegarLoop]: Abstraction has 19324 states and 23950 transitions. [2019-11-25 08:56:22,438 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-25 08:56:22,438 INFO L276 IsEmpty]: Start isEmpty. Operand 19324 states and 23950 transitions. [2019-11-25 08:56:22,447 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-11-25 08:56:22,447 INFO L402 BasicCegarLoop]: Found error trace [2019-11-25 08:56:22,447 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:56:22,448 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-25 08:56:22,448 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:56:22,448 INFO L82 PathProgramCache]: Analyzing trace with hash 2012797655, now seen corresponding path program 1 times [2019-11-25 08:56:22,448 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:56:22,448 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1958620318] [2019-11-25 08:56:22,449 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:56:22,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:56:22,490 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-25 08:56:22,490 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1958620318] [2019-11-25 08:56:22,490 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:56:22,490 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-25 08:56:22,491 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1390639770] [2019-11-25 08:56:22,491 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-25 08:56:22,491 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:56:22,491 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-25 08:56:22,492 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-25 08:56:22,492 INFO L87 Difference]: Start difference. First operand 19324 states and 23950 transitions. Second operand 5 states. [2019-11-25 08:56:23,601 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:56:23,601 INFO L93 Difference]: Finished difference Result 45442 states and 56677 transitions. [2019-11-25 08:56:23,601 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-25 08:56:23,602 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 110 [2019-11-25 08:56:23,602 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-25 08:56:23,634 INFO L225 Difference]: With dead ends: 45442 [2019-11-25 08:56:23,634 INFO L226 Difference]: Without dead ends: 26232 [2019-11-25 08:56:23,645 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-25 08:56:23,662 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26232 states. [2019-11-25 08:56:24,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26232 to 19420. [2019-11-25 08:56:24,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19420 states. [2019-11-25 08:56:24,224 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19420 states to 19420 states and 23690 transitions. [2019-11-25 08:56:24,224 INFO L78 Accepts]: Start accepts. Automaton has 19420 states and 23690 transitions. Word has length 110 [2019-11-25 08:56:24,224 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-25 08:56:24,224 INFO L462 AbstractCegarLoop]: Abstraction has 19420 states and 23690 transitions. [2019-11-25 08:56:24,224 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-25 08:56:24,225 INFO L276 IsEmpty]: Start isEmpty. Operand 19420 states and 23690 transitions. [2019-11-25 08:56:24,233 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-11-25 08:56:24,233 INFO L402 BasicCegarLoop]: Found error trace [2019-11-25 08:56:24,233 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:56:24,233 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-25 08:56:24,234 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:56:24,234 INFO L82 PathProgramCache]: Analyzing trace with hash 564093659, now seen corresponding path program 1 times [2019-11-25 08:56:24,234 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:56:24,234 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1222963818] [2019-11-25 08:56:24,234 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:56:24,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:56:24,271 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:56:24,271 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1222963818] [2019-11-25 08:56:24,271 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:56:24,271 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:56:24,272 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1162526888] [2019-11-25 08:56:24,272 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-25 08:56:24,272 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:56:24,272 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:56:24,272 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:24,273 INFO L87 Difference]: Start difference. First operand 19420 states and 23690 transitions. Second operand 3 states. [2019-11-25 08:56:25,001 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:56:25,001 INFO L93 Difference]: Finished difference Result 29198 states and 35739 transitions. [2019-11-25 08:56:25,002 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:56:25,002 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 110 [2019-11-25 08:56:25,002 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-25 08:56:25,015 INFO L225 Difference]: With dead ends: 29198 [2019-11-25 08:56:25,015 INFO L226 Difference]: Without dead ends: 19420 [2019-11-25 08:56:25,020 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:25,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19420 states. [2019-11-25 08:56:25,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19420 to 19350. [2019-11-25 08:56:25,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19350 states. [2019-11-25 08:56:25,536 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19350 states to 19350 states and 23356 transitions. [2019-11-25 08:56:25,536 INFO L78 Accepts]: Start accepts. Automaton has 19350 states and 23356 transitions. Word has length 110 [2019-11-25 08:56:25,536 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-25 08:56:25,536 INFO L462 AbstractCegarLoop]: Abstraction has 19350 states and 23356 transitions. [2019-11-25 08:56:25,536 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-25 08:56:25,537 INFO L276 IsEmpty]: Start isEmpty. Operand 19350 states and 23356 transitions. [2019-11-25 08:56:25,544 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2019-11-25 08:56:25,545 INFO L402 BasicCegarLoop]: Found error trace [2019-11-25 08:56:25,545 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:56:25,545 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-25 08:56:25,545 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:56:25,546 INFO L82 PathProgramCache]: Analyzing trace with hash 770898653, now seen corresponding path program 1 times [2019-11-25 08:56:25,546 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:56:25,546 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [741923723] [2019-11-25 08:56:25,546 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:56:25,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:56:25,597 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-25 08:56:25,598 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [741923723] [2019-11-25 08:56:25,598 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:56:25,598 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-25 08:56:25,598 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [202063405] [2019-11-25 08:56:25,599 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-25 08:56:25,599 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:56:25,599 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-25 08:56:25,599 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-25 08:56:25,599 INFO L87 Difference]: Start difference. First operand 19350 states and 23356 transitions. Second operand 5 states. [2019-11-25 08:56:26,412 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:56:26,412 INFO L93 Difference]: Finished difference Result 37116 states and 45101 transitions. [2019-11-25 08:56:26,413 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-25 08:56:26,413 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 111 [2019-11-25 08:56:26,413 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-25 08:56:26,429 INFO L225 Difference]: With dead ends: 37116 [2019-11-25 08:56:26,429 INFO L226 Difference]: Without dead ends: 17840 [2019-11-25 08:56:26,441 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-25 08:56:26,455 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17840 states. [2019-11-25 08:56:27,014 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17840 to 13178. [2019-11-25 08:56:27,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13178 states. [2019-11-25 08:56:27,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13178 states to 13178 states and 15698 transitions. [2019-11-25 08:56:27,026 INFO L78 Accepts]: Start accepts. Automaton has 13178 states and 15698 transitions. Word has length 111 [2019-11-25 08:56:27,026 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-25 08:56:27,026 INFO L462 AbstractCegarLoop]: Abstraction has 13178 states and 15698 transitions. [2019-11-25 08:56:27,026 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-25 08:56:27,026 INFO L276 IsEmpty]: Start isEmpty. Operand 13178 states and 15698 transitions. [2019-11-25 08:56:27,031 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2019-11-25 08:56:27,031 INFO L402 BasicCegarLoop]: Found error trace [2019-11-25 08:56:27,031 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:56:27,031 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-25 08:56:27,031 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:56:27,032 INFO L82 PathProgramCache]: Analyzing trace with hash 273196097, now seen corresponding path program 1 times [2019-11-25 08:56:27,032 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:56:27,032 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2114852573] [2019-11-25 08:56:27,032 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:56:27,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:56:27,060 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 18 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:56:27,061 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2114852573] [2019-11-25 08:56:27,061 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:56:27,061 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:56:27,061 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [691440664] [2019-11-25 08:56:27,062 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-25 08:56:27,062 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:56:27,062 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:56:27,062 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:27,062 INFO L87 Difference]: Start difference. First operand 13178 states and 15698 transitions. Second operand 3 states. [2019-11-25 08:56:27,449 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:56:27,449 INFO L93 Difference]: Finished difference Result 21196 states and 25354 transitions. [2019-11-25 08:56:27,450 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:56:27,450 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 113 [2019-11-25 08:56:27,450 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-25 08:56:27,457 INFO L225 Difference]: With dead ends: 21196 [2019-11-25 08:56:27,457 INFO L226 Difference]: Without dead ends: 11030 [2019-11-25 08:56:27,465 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:27,472 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11030 states. [2019-11-25 08:56:27,776 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11030 to 11026. [2019-11-25 08:56:27,776 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11026 states. [2019-11-25 08:56:27,786 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11026 states to 11026 states and 13114 transitions. [2019-11-25 08:56:27,786 INFO L78 Accepts]: Start accepts. Automaton has 11026 states and 13114 transitions. Word has length 113 [2019-11-25 08:56:27,786 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-25 08:56:27,786 INFO L462 AbstractCegarLoop]: Abstraction has 11026 states and 13114 transitions. [2019-11-25 08:56:27,786 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-25 08:56:27,786 INFO L276 IsEmpty]: Start isEmpty. Operand 11026 states and 13114 transitions. [2019-11-25 08:56:27,791 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 147 [2019-11-25 08:56:27,791 INFO L402 BasicCegarLoop]: Found error trace [2019-11-25 08:56:27,792 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:56:27,792 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-25 08:56:27,792 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:56:27,792 INFO L82 PathProgramCache]: Analyzing trace with hash 1857340375, now seen corresponding path program 1 times [2019-11-25 08:56:27,793 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:56:27,793 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [245590456] [2019-11-25 08:56:27,793 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:56:27,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:56:27,831 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:56:27,832 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [245590456] [2019-11-25 08:56:27,832 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:56:27,832 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:56:27,832 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1320109408] [2019-11-25 08:56:27,833 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-25 08:56:27,833 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:56:27,833 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:56:27,833 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:27,833 INFO L87 Difference]: Start difference. First operand 11026 states and 13114 transitions. Second operand 3 states. [2019-11-25 08:56:28,240 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:56:28,241 INFO L93 Difference]: Finished difference Result 20200 states and 24102 transitions. [2019-11-25 08:56:28,241 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:56:28,241 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 146 [2019-11-25 08:56:28,242 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-25 08:56:28,248 INFO L225 Difference]: With dead ends: 20200 [2019-11-25 08:56:28,248 INFO L226 Difference]: Without dead ends: 11030 [2019-11-25 08:56:28,252 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:28,258 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11030 states. [2019-11-25 08:56:28,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11030 to 11026. [2019-11-25 08:56:28,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11026 states. [2019-11-25 08:56:28,569 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11026 states to 11026 states and 13034 transitions. [2019-11-25 08:56:28,569 INFO L78 Accepts]: Start accepts. Automaton has 11026 states and 13034 transitions. Word has length 146 [2019-11-25 08:56:28,569 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-25 08:56:28,569 INFO L462 AbstractCegarLoop]: Abstraction has 11026 states and 13034 transitions. [2019-11-25 08:56:28,570 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-25 08:56:28,570 INFO L276 IsEmpty]: Start isEmpty. Operand 11026 states and 13034 transitions. [2019-11-25 08:56:28,574 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2019-11-25 08:56:28,574 INFO L402 BasicCegarLoop]: Found error trace [2019-11-25 08:56:28,575 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:56:28,575 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-25 08:56:28,575 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:56:28,575 INFO L82 PathProgramCache]: Analyzing trace with hash 1216535548, now seen corresponding path program 1 times [2019-11-25 08:56:28,575 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:56:28,576 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1857801889] [2019-11-25 08:56:28,576 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:56:28,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:56:28,632 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-25 08:56:28,632 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1857801889] [2019-11-25 08:56:28,632 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:56:28,632 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-25 08:56:28,633 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [275391398] [2019-11-25 08:56:28,633 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-25 08:56:28,633 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:56:28,633 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-25 08:56:28,634 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-25 08:56:28,634 INFO L87 Difference]: Start difference. First operand 11026 states and 13034 transitions. Second operand 5 states. [2019-11-25 08:56:29,854 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:56:29,855 INFO L93 Difference]: Finished difference Result 35306 states and 41589 transitions. [2019-11-25 08:56:29,855 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-25 08:56:29,855 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 176 [2019-11-25 08:56:29,855 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-25 08:56:29,877 INFO L225 Difference]: With dead ends: 35306 [2019-11-25 08:56:29,877 INFO L226 Difference]: Without dead ends: 24343 [2019-11-25 08:56:29,889 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-25 08:56:29,906 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24343 states. [2019-11-25 08:56:30,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24343 to 11410. [2019-11-25 08:56:30,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11410 states. [2019-11-25 08:56:30,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11410 states to 11410 states and 13328 transitions. [2019-11-25 08:56:30,592 INFO L78 Accepts]: Start accepts. Automaton has 11410 states and 13328 transitions. Word has length 176 [2019-11-25 08:56:30,592 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-25 08:56:30,592 INFO L462 AbstractCegarLoop]: Abstraction has 11410 states and 13328 transitions. [2019-11-25 08:56:30,592 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-25 08:56:30,592 INFO L276 IsEmpty]: Start isEmpty. Operand 11410 states and 13328 transitions. [2019-11-25 08:56:30,599 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2019-11-25 08:56:30,599 INFO L402 BasicCegarLoop]: Found error trace [2019-11-25 08:56:30,599 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:56:30,599 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-25 08:56:30,600 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:56:30,600 INFO L82 PathProgramCache]: Analyzing trace with hash 2104709508, now seen corresponding path program 1 times [2019-11-25 08:56:30,600 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:56:30,600 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [20257684] [2019-11-25 08:56:30,600 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:56:30,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:56:30,662 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:56:30,663 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [20257684] [2019-11-25 08:56:30,663 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:56:30,663 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:56:30,664 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [594129084] [2019-11-25 08:56:30,664 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-25 08:56:30,664 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:56:30,664 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:56:30,665 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:30,665 INFO L87 Difference]: Start difference. First operand 11410 states and 13328 transitions. Second operand 3 states. [2019-11-25 08:56:31,398 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:56:31,399 INFO L93 Difference]: Finished difference Result 19722 states and 23103 transitions. [2019-11-25 08:56:31,399 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:56:31,399 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 176 [2019-11-25 08:56:31,399 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-25 08:56:31,405 INFO L225 Difference]: With dead ends: 19722 [2019-11-25 08:56:31,405 INFO L226 Difference]: Without dead ends: 11442 [2019-11-25 08:56:31,409 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:31,416 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11442 states. [2019-11-25 08:56:31,819 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11442 to 11410. [2019-11-25 08:56:31,819 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11410 states. [2019-11-25 08:56:31,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11410 states to 11410 states and 13120 transitions. [2019-11-25 08:56:31,829 INFO L78 Accepts]: Start accepts. Automaton has 11410 states and 13120 transitions. Word has length 176 [2019-11-25 08:56:31,829 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-25 08:56:31,829 INFO L462 AbstractCegarLoop]: Abstraction has 11410 states and 13120 transitions. [2019-11-25 08:56:31,829 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-25 08:56:31,829 INFO L276 IsEmpty]: Start isEmpty. Operand 11410 states and 13120 transitions. [2019-11-25 08:56:31,834 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-25 08:56:31,834 INFO L402 BasicCegarLoop]: Found error trace [2019-11-25 08:56:31,835 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:56:31,835 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-25 08:56:31,835 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:56:31,835 INFO L82 PathProgramCache]: Analyzing trace with hash 251088387, now seen corresponding path program 1 times [2019-11-25 08:56:31,835 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:56:31,835 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [272784921] [2019-11-25 08:56:31,835 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:56:31,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:56:31,879 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-25 08:56:31,880 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [272784921] [2019-11-25 08:56:31,880 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:56:31,880 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:56:31,880 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [442598888] [2019-11-25 08:56:31,881 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-25 08:56:31,881 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:56:31,881 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:56:31,881 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:31,882 INFO L87 Difference]: Start difference. First operand 11410 states and 13120 transitions. Second operand 3 states. [2019-11-25 08:56:32,532 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:56:32,532 INFO L93 Difference]: Finished difference Result 22664 states and 25875 transitions. [2019-11-25 08:56:32,533 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:56:32,533 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-25 08:56:32,533 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-25 08:56:32,539 INFO L225 Difference]: With dead ends: 22664 [2019-11-25 08:56:32,539 INFO L226 Difference]: Without dead ends: 6788 [2019-11-25 08:56:32,548 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:32,552 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6788 states. [2019-11-25 08:56:32,814 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6788 to 6580. [2019-11-25 08:56:32,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6580 states. [2019-11-25 08:56:32,819 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6580 states to 6580 states and 7290 transitions. [2019-11-25 08:56:32,819 INFO L78 Accepts]: Start accepts. Automaton has 6580 states and 7290 transitions. Word has length 178 [2019-11-25 08:56:32,820 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-25 08:56:32,820 INFO L462 AbstractCegarLoop]: Abstraction has 6580 states and 7290 transitions. [2019-11-25 08:56:32,820 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-25 08:56:32,820 INFO L276 IsEmpty]: Start isEmpty. Operand 6580 states and 7290 transitions. [2019-11-25 08:56:32,824 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 181 [2019-11-25 08:56:32,824 INFO L402 BasicCegarLoop]: Found error trace [2019-11-25 08:56:32,825 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:56:32,825 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-25 08:56:32,825 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:56:32,825 INFO L82 PathProgramCache]: Analyzing trace with hash -32931800, now seen corresponding path program 1 times [2019-11-25 08:56:32,826 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:56:32,826 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [78097845] [2019-11-25 08:56:32,826 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:56:32,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:56:32,877 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:56:32,877 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [78097845] [2019-11-25 08:56:32,877 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:56:32,878 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:56:32,878 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [864440341] [2019-11-25 08:56:32,879 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-25 08:56:32,879 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:56:32,879 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:56:32,879 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:32,879 INFO L87 Difference]: Start difference. First operand 6580 states and 7290 transitions. Second operand 3 states. [2019-11-25 08:56:33,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:56:33,202 INFO L93 Difference]: Finished difference Result 11554 states and 12829 transitions. [2019-11-25 08:56:33,202 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:56:33,202 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 180 [2019-11-25 08:56:33,203 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-25 08:56:33,207 INFO L225 Difference]: With dead ends: 11554 [2019-11-25 08:56:33,207 INFO L226 Difference]: Without dead ends: 6580 [2019-11-25 08:56:33,209 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:56:33,212 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6580 states. [2019-11-25 08:56:33,474 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6580 to 6580. [2019-11-25 08:56:33,474 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6580 states. [2019-11-25 08:56:33,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6580 states to 6580 states and 7212 transitions. [2019-11-25 08:56:33,480 INFO L78 Accepts]: Start accepts. Automaton has 6580 states and 7212 transitions. Word has length 180 [2019-11-25 08:56:33,480 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-25 08:56:33,480 INFO L462 AbstractCegarLoop]: Abstraction has 6580 states and 7212 transitions. [2019-11-25 08:56:33,480 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-25 08:56:33,480 INFO L276 IsEmpty]: Start isEmpty. Operand 6580 states and 7212 transitions. [2019-11-25 08:56:33,485 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 183 [2019-11-25 08:56:33,485 INFO L402 BasicCegarLoop]: Found error trace [2019-11-25 08:56:33,485 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:56:33,485 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-25 08:56:33,485 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:56:33,485 INFO L82 PathProgramCache]: Analyzing trace with hash 1382104249, now seen corresponding path program 1 times [2019-11-25 08:56:33,485 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:56:33,485 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [105298553] [2019-11-25 08:56:33,485 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:56:33,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:56:33,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:56:33,574 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:56:33,574 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-25 08:56:33,706 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 25.11 08:56:33 BoogieIcfgContainer [2019-11-25 08:56:33,707 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-25 08:56:33,707 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-25 08:56:33,707 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-25 08:56:33,708 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-25 08:56:33,714 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 08:56:14" (3/4) ... [2019-11-25 08:56:33,716 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-25 08:56:33,888 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_026b7c82-44c5-4eb3-8fea-831f73543f90/bin/uautomizer/witness.graphml [2019-11-25 08:56:33,888 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-25 08:56:33,890 INFO L168 Benchmark]: Toolchain (without parser) took 20699.48 ms. Allocated memory was 1.0 GB in the beginning and 3.1 GB in the end (delta: 2.1 GB). Free memory was 952.8 MB in the beginning and 820.5 MB in the end (delta: 132.2 MB). Peak memory consumption was 2.2 GB. Max. memory is 11.5 GB. [2019-11-25 08:56:33,890 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-25 08:56:33,890 INFO L168 Benchmark]: CACSL2BoogieTranslator took 440.19 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 142.1 MB). Free memory was 952.8 MB in the beginning and 1.1 GB in the end (delta: -178.8 MB). Peak memory consumption was 23.0 MB. Max. memory is 11.5 GB. [2019-11-25 08:56:33,891 INFO L168 Benchmark]: Boogie Procedure Inliner took 59.71 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-25 08:56:33,891 INFO L168 Benchmark]: Boogie Preprocessor took 55.48 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-11-25 08:56:33,891 INFO L168 Benchmark]: RCFGBuilder took 924.66 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 72.1 MB). Peak memory consumption was 72.1 MB. Max. memory is 11.5 GB. [2019-11-25 08:56:33,892 INFO L168 Benchmark]: TraceAbstraction took 19029.34 ms. Allocated memory was 1.2 GB in the beginning and 3.1 GB in the end (delta: 2.0 GB). Free memory was 1.1 GB in the beginning and 877.5 MB in the end (delta: 176.6 MB). Peak memory consumption was 2.1 GB. Max. memory is 11.5 GB. [2019-11-25 08:56:33,892 INFO L168 Benchmark]: Witness Printer took 180.90 ms. Allocated memory is still 3.1 GB. Free memory was 877.5 MB in the beginning and 820.5 MB in the end (delta: 57.0 MB). Peak memory consumption was 57.0 MB. Max. memory is 11.5 GB. [2019-11-25 08:56:33,894 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 440.19 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 142.1 MB). Free memory was 952.8 MB in the beginning and 1.1 GB in the end (delta: -178.8 MB). Peak memory consumption was 23.0 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 59.71 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 55.48 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 924.66 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 72.1 MB). Peak memory consumption was 72.1 MB. Max. memory is 11.5 GB. * TraceAbstraction took 19029.34 ms. Allocated memory was 1.2 GB in the beginning and 3.1 GB in the end (delta: 2.0 GB). Free memory was 1.1 GB in the beginning and 877.5 MB in the end (delta: 176.6 MB). Peak memory consumption was 2.1 GB. Max. memory is 11.5 GB. * Witness Printer took 180.90 ms. Allocated memory is still 3.1 GB. Free memory was 877.5 MB in the beginning and 820.5 MB in the end (delta: 57.0 MB). Peak memory consumption was 57.0 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int m_st ; [L20] int t1_st ; [L21] int t2_st ; [L22] int t3_st ; [L23] int m_i ; [L24] int t1_i ; [L25] int t2_i ; [L26] int t3_i ; [L27] int M_E = 2; [L28] int T1_E = 2; [L29] int T2_E = 2; [L30] int T3_E = 2; [L31] int E_1 = 2; [L32] int E_2 = 2; [L33] int E_3 = 2; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0] [L687] int __retres1 ; [L600] m_i = 1 [L601] t1_i = 1 [L602] t2_i = 1 [L603] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L628] int kernel_st ; [L629] int tmp ; [L630] int tmp___0 ; [L634] kernel_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L271] COND TRUE m_i == 1 [L272] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L276] COND TRUE t1_i == 1 [L277] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L281] COND TRUE t2_i == 1 [L282] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L286] COND TRUE t3_i == 1 [L287] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L408] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L413] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L418] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L423] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L428] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L433] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L438] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; [L184] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L187] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L197] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L199] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L203] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L206] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L216] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L218] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L506] tmp___0 = is_transmit1_triggered() [L508] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L222] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L225] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L235] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L237] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L514] tmp___1 = is_transmit2_triggered() [L516] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L241] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L244] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L254] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L256] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L522] tmp___2 = is_transmit3_triggered() [L524] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L451] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L456] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L461] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L466] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L471] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L476] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L481] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L642] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L645] kernel_st = 1 [L327] int tmp ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L331] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L296] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L299] COND TRUE m_st == 0 [L300] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L322] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L334] tmp = exists_runnable_thread() [L336] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L341] COND TRUE m_st == 0 [L342] int tmp_ndt_1; [L343] tmp_ndt_1 = __VERIFIER_nondet_int() [L344] COND FALSE !(\read(tmp_ndt_1)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L355] COND TRUE t1_st == 0 [L356] int tmp_ndt_2; [L357] tmp_ndt_2 = __VERIFIER_nondet_int() [L358] COND TRUE \read(tmp_ndt_2) [L360] t1_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L84] COND TRUE t1_pc == 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L95] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L97] t1_pc = 1 [L98] t1_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L369] COND TRUE t2_st == 0 [L370] int tmp_ndt_3; [L371] tmp_ndt_3 = __VERIFIER_nondet_int() [L372] COND TRUE \read(tmp_ndt_3) [L374] t2_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L119] COND TRUE t2_pc == 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L130] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L132] t2_pc = 1 [L133] t2_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L383] COND TRUE t3_st == 0 [L384] int tmp_ndt_4; [L385] tmp_ndt_4 = __VERIFIER_nondet_int() [L386] COND TRUE \read(tmp_ndt_4) [L388] t3_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1] [L154] COND TRUE t3_pc == 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1] [L165] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1] [L167] t3_pc = 1 [L168] t3_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L331] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L296] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L299] COND TRUE m_st == 0 [L300] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L322] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L334] tmp = exists_runnable_thread() [L336] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L341] COND TRUE m_st == 0 [L342] int tmp_ndt_1; [L343] tmp_ndt_1 = __VERIFIER_nondet_int() [L344] COND TRUE \read(tmp_ndt_1) [L346] m_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L43] COND TRUE m_pc == 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L54] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L57] E_1 = 1 [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; [L184] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L187] COND FALSE !(m_pc == 1) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L197] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L199] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L203] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L206] COND TRUE t1_pc == 1 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L207] COND TRUE E_1 == 1 [L208] __retres1 = 1 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L218] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L506] tmp___0 = is_transmit1_triggered() [L508] COND TRUE \read(tmp___0) [L509] t1_st = 0 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L222] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L225] COND TRUE t2_pc == 1 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L226] COND FALSE !(E_2 == 1) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L235] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L237] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L514] tmp___1 = is_transmit2_triggered() [L516] COND FALSE !(\read(tmp___1)) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L241] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L244] COND TRUE t3_pc == 1 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L245] COND FALSE !(E_3 == 1) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L254] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L256] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L522] tmp___2 = is_transmit3_triggered() [L524] COND FALSE !(\read(tmp___2)) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L59] E_1 = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L62] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L64] m_pc = 1 [L65] m_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L355] COND TRUE t1_st == 0 [L356] int tmp_ndt_2; [L357] tmp_ndt_2 = __VERIFIER_nondet_int() [L358] COND TRUE \read(tmp_ndt_2) [L360] t1_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L84] COND FALSE !(t1_pc == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L87] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L103] E_2 = 1 [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; [L184] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L187] COND TRUE m_pc == 1 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L188] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L197] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L199] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L203] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L206] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L207] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L216] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L218] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L506] tmp___0 = is_transmit1_triggered() [L508] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L222] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L225] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L226] COND TRUE E_2 == 1 [L227] __retres1 = 1 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L237] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L514] tmp___1 = is_transmit2_triggered() [L516] COND TRUE \read(tmp___1) [L517] t2_st = 0 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L241] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L244] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L245] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L254] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L256] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L522] tmp___2 = is_transmit3_triggered() [L524] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L105] E_2 = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L95] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L97] t1_pc = 1 [L98] t1_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L369] COND TRUE t2_st == 0 [L370] int tmp_ndt_3; [L371] tmp_ndt_3 = __VERIFIER_nondet_int() [L372] COND TRUE \read(tmp_ndt_3) [L374] t2_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L119] COND FALSE !(t2_pc == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L122] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L138] E_3 = 1 [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; [L184] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L187] COND TRUE m_pc == 1 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L188] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L197] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L199] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L203] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L206] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L207] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L216] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L218] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L506] tmp___0 = is_transmit1_triggered() [L508] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L222] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L225] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L226] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L235] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L237] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L514] tmp___1 = is_transmit2_triggered() [L516] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L241] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L244] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L245] COND TRUE E_3 == 1 [L246] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L256] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L522] tmp___2 = is_transmit3_triggered() [L524] COND TRUE \read(tmp___2) [L525] t3_st = 0 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L140] E_3 = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L130] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L132] t2_pc = 1 [L133] t2_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L383] COND TRUE t3_st == 0 [L384] int tmp_ndt_4; [L385] tmp_ndt_4 = __VERIFIER_nondet_int() [L386] COND TRUE \read(tmp_ndt_4) [L388] t3_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] [L154] COND FALSE !(t3_pc == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] [L157] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] [L11] __VERIFIER_error() VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 276 locations, 1 error locations. Result: UNSAFE, OverallTime: 18.9s, OverallIterations: 27, TraceHistogramMax: 2, AutomataDifference: 10.2s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 10884 SDtfs, 10117 SDslu, 7643 SDs, 0 SdLazy, 500 SolverSat, 248 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.6s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 92 GetRequests, 50 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=19420occurred in iteration=18, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 6.9s AutomataMinimizationTime, 26 MinimizatonAttempts, 33813 StatesRemovedByMinimization, 16 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 0.6s InterpolantComputationTime, 2694 NumberOfCodeBlocks, 2694 NumberOfCodeBlocksAsserted, 27 NumberOfCheckSat, 2486 ConstructedInterpolants, 0 QuantifiedInterpolants, 403400 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 26 InterpolantComputations, 26 PerfectInterpolantSequences, 228/228 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...