./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.02.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 6b5699aa Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_2c69e248-9022-4c2a-8724-f6c8c490df92/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_2c69e248-9022-4c2a-8724-f6c8c490df92/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_2c69e248-9022-4c2a-8724-f6c8c490df92/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_2c69e248-9022-4c2a-8724-f6c8c490df92/bin/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.02.cil-2.c -s /tmp/vcloud-vcloud-master/worker/run_dir_2c69e248-9022-4c2a-8724-f6c8c490df92/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_2c69e248-9022-4c2a-8724-f6c8c490df92/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 216b1eba72c80bc0eec8bb9ab0298bf8baf472d8 ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.24-6b5699a [2019-11-25 08:57:04,598 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-25 08:57:04,600 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-25 08:57:04,610 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-25 08:57:04,610 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-25 08:57:04,611 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-25 08:57:04,613 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-25 08:57:04,615 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-25 08:57:04,616 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-25 08:57:04,617 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-25 08:57:04,618 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-25 08:57:04,619 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-25 08:57:04,620 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-25 08:57:04,621 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-25 08:57:04,622 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-25 08:57:04,623 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-25 08:57:04,624 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-25 08:57:04,624 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-25 08:57:04,626 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-25 08:57:04,628 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-25 08:57:04,630 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-25 08:57:04,631 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-25 08:57:04,632 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-25 08:57:04,633 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-25 08:57:04,636 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-25 08:57:04,636 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-25 08:57:04,636 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-25 08:57:04,637 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-25 08:57:04,637 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-25 08:57:04,638 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-25 08:57:04,638 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-25 08:57:04,639 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-25 08:57:04,640 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-25 08:57:04,640 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-25 08:57:04,641 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-25 08:57:04,641 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-25 08:57:04,642 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-25 08:57:04,642 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-25 08:57:04,642 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-25 08:57:04,643 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-25 08:57:04,644 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-25 08:57:04,644 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_2c69e248-9022-4c2a-8724-f6c8c490df92/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2019-11-25 08:57:04,670 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-25 08:57:04,670 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-25 08:57:04,672 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-25 08:57:04,672 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-25 08:57:04,672 INFO L138 SettingsManager]: * Use SBE=true [2019-11-25 08:57:04,672 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2019-11-25 08:57:04,672 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2019-11-25 08:57:04,673 INFO L138 SettingsManager]: * Use old map elimination=false [2019-11-25 08:57:04,673 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2019-11-25 08:57:04,673 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2019-11-25 08:57:04,674 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2019-11-25 08:57:04,674 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-25 08:57:04,674 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-25 08:57:04,675 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2019-11-25 08:57:04,675 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-25 08:57:04,675 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-25 08:57:04,675 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-25 08:57:04,675 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2019-11-25 08:57:04,675 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2019-11-25 08:57:04,676 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2019-11-25 08:57:04,676 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-25 08:57:04,676 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-25 08:57:04,677 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2019-11-25 08:57:04,677 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-25 08:57:04,677 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2019-11-25 08:57:04,677 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-25 08:57:04,677 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-25 08:57:04,677 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2019-11-25 08:57:04,678 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-25 08:57:04,678 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-25 08:57:04,678 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2019-11-25 08:57:04,679 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2019-11-25 08:57:04,679 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_2c69e248-9022-4c2a-8724-f6c8c490df92/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 216b1eba72c80bc0eec8bb9ab0298bf8baf472d8 [2019-11-25 08:57:04,868 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-25 08:57:04,887 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-25 08:57:04,890 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-25 08:57:04,891 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-25 08:57:04,891 INFO L275 PluginConnector]: CDTParser initialized [2019-11-25 08:57:04,892 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_2c69e248-9022-4c2a-8724-f6c8c490df92/bin/uautomizer/../../sv-benchmarks/c/systemc/token_ring.02.cil-2.c [2019-11-25 08:57:04,952 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_2c69e248-9022-4c2a-8724-f6c8c490df92/bin/uautomizer/data/66c0aa517/d3ffc0fb634e4c96bfdaf6939b6f7d7e/FLAG876567c28 [2019-11-25 08:57:05,396 INFO L306 CDTParser]: Found 1 translation units. [2019-11-25 08:57:05,397 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_2c69e248-9022-4c2a-8724-f6c8c490df92/sv-benchmarks/c/systemc/token_ring.02.cil-2.c [2019-11-25 08:57:05,415 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_2c69e248-9022-4c2a-8724-f6c8c490df92/bin/uautomizer/data/66c0aa517/d3ffc0fb634e4c96bfdaf6939b6f7d7e/FLAG876567c28 [2019-11-25 08:57:05,915 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_2c69e248-9022-4c2a-8724-f6c8c490df92/bin/uautomizer/data/66c0aa517/d3ffc0fb634e4c96bfdaf6939b6f7d7e [2019-11-25 08:57:05,918 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-25 08:57:05,919 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-25 08:57:05,920 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-25 08:57:05,920 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-25 08:57:05,923 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-25 08:57:05,924 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 25.11 08:57:05" (1/1) ... [2019-11-25 08:57:05,927 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@33dc2604 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:57:05, skipping insertion in model container [2019-11-25 08:57:05,927 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 25.11 08:57:05" (1/1) ... [2019-11-25 08:57:05,934 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-11-25 08:57:05,981 INFO L179 MainTranslator]: Built tables and reachable declarations [2019-11-25 08:57:06,252 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-25 08:57:06,258 INFO L201 MainTranslator]: Completed pre-run [2019-11-25 08:57:06,306 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-25 08:57:06,325 INFO L205 MainTranslator]: Completed translation [2019-11-25 08:57:06,325 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:57:06 WrapperNode [2019-11-25 08:57:06,325 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-25 08:57:06,326 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-25 08:57:06,326 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-25 08:57:06,326 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-25 08:57:06,332 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:57:06" (1/1) ... [2019-11-25 08:57:06,339 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:57:06" (1/1) ... [2019-11-25 08:57:06,373 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-25 08:57:06,374 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-25 08:57:06,374 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-25 08:57:06,374 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-25 08:57:06,383 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:57:06" (1/1) ... [2019-11-25 08:57:06,383 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:57:06" (1/1) ... [2019-11-25 08:57:06,395 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:57:06" (1/1) ... [2019-11-25 08:57:06,395 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:57:06" (1/1) ... [2019-11-25 08:57:06,408 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:57:06" (1/1) ... [2019-11-25 08:57:06,422 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:57:06" (1/1) ... [2019-11-25 08:57:06,426 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:57:06" (1/1) ... [2019-11-25 08:57:06,434 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-25 08:57:06,434 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-25 08:57:06,434 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-25 08:57:06,435 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-25 08:57:06,435 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:57:06" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_2c69e248-9022-4c2a-8724-f6c8c490df92/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:57:06,510 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-25 08:57:06,511 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-25 08:57:07,269 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-25 08:57:07,269 INFO L284 CfgBuilder]: Removed 105 assume(true) statements. [2019-11-25 08:57:07,270 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 08:57:07 BoogieIcfgContainer [2019-11-25 08:57:07,271 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-25 08:57:07,271 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2019-11-25 08:57:07,271 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2019-11-25 08:57:07,274 INFO L275 PluginConnector]: BuchiAutomizer initialized [2019-11-25 08:57:07,275 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-11-25 08:57:07,275 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 25.11 08:57:05" (1/3) ... [2019-11-25 08:57:07,276 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@39dfacb2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 25.11 08:57:07, skipping insertion in model container [2019-11-25 08:57:07,276 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-11-25 08:57:07,276 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:57:06" (2/3) ... [2019-11-25 08:57:07,276 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@39dfacb2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 25.11 08:57:07, skipping insertion in model container [2019-11-25 08:57:07,277 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-11-25 08:57:07,277 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 08:57:07" (3/3) ... [2019-11-25 08:57:07,278 INFO L371 chiAutomizerObserver]: Analyzing ICFG token_ring.02.cil-2.c [2019-11-25 08:57:07,314 INFO L356 BuchiCegarLoop]: Interprodecural is true [2019-11-25 08:57:07,314 INFO L357 BuchiCegarLoop]: Hoare is false [2019-11-25 08:57:07,315 INFO L358 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2019-11-25 08:57:07,315 INFO L359 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-25 08:57:07,315 INFO L360 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-25 08:57:07,315 INFO L361 BuchiCegarLoop]: Difference is false [2019-11-25 08:57:07,315 INFO L362 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-25 08:57:07,315 INFO L365 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2019-11-25 08:57:07,337 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 223 states. [2019-11-25 08:57:07,370 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 180 [2019-11-25 08:57:07,370 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:57:07,371 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:57:07,380 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:07,381 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:07,381 INFO L424 BuchiCegarLoop]: ======== Iteration 1============ [2019-11-25 08:57:07,381 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 223 states. [2019-11-25 08:57:07,392 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 180 [2019-11-25 08:57:07,392 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:57:07,392 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:57:07,395 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:07,395 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:07,403 INFO L794 eck$LassoCheckResult]: Stem: 100#ULTIMATE.startENTRYtrue ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 8#L-1true havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 156#L518true havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 87#L226true assume !(1 == ~m_i~0);~m_st~0 := 2; 224#L233-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 130#L238-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 140#L243-1true assume !(0 == ~M_E~0); 115#L346-1true assume !(0 == ~T1_E~0); 10#L351-1true assume !(0 == ~T2_E~0); 34#L356-1true assume !(0 == ~E_M~0); 58#L361-1true assume !(0 == ~E_1~0); 190#L366-1true assume !(0 == ~E_2~0); 215#L371-1true havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 170#L168true assume 1 == ~m_pc~0; 28#L169true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 172#L179true is_master_triggered_#res := is_master_triggered_~__retres1~0; 29#L180true activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 171#L427true assume !(0 != activate_threads_~tmp~1); 54#L427-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 93#L187true assume 1 == ~t1_pc~0; 138#L188true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 94#L198true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 139#L199true activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 84#L435true assume !(0 != activate_threads_~tmp___0~0); 88#L435-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 221#L206true assume !(1 == ~t2_pc~0); 216#L206-2true is_transmit2_triggered_~__retres1~2 := 0; 222#L217true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 42#L218true activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 205#L443true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 186#L443-2true assume !(1 == ~M_E~0); 30#L384-1true assume !(1 == ~T1_E~0); 33#L389-1true assume !(1 == ~T2_E~0); 55#L394-1true assume !(1 == ~E_M~0); 187#L399-1true assume 1 == ~E_1~0;~E_1~0 := 2; 211#L404-1true assume !(1 == ~E_2~0); 7#L555-1true [2019-11-25 08:57:07,404 INFO L796 eck$LassoCheckResult]: Loop: 7#L555-1true assume !false; 96#L556true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 119#L321true assume false; 90#L336true start_simulation_~kernel_st~0 := 2; 85#L226-1true start_simulation_~kernel_st~0 := 3; 116#L346-2true assume 0 == ~M_E~0;~M_E~0 := 1; 117#L346-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 15#L351-3true assume !(0 == ~T2_E~0); 36#L356-3true assume 0 == ~E_M~0;~E_M~0 := 1; 67#L361-3true assume 0 == ~E_1~0;~E_1~0 := 1; 194#L366-3true assume 0 == ~E_2~0;~E_2~0 := 1; 220#L371-3true havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 49#L168-12true assume 1 == ~m_pc~0; 17#L169-4true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 159#L179-4true is_master_triggered_#res := is_master_triggered_~__retres1~0; 19#L180-4true activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 53#L427-12true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 37#L427-14true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 75#L187-12true assume 1 == ~t1_pc~0; 145#L188-4true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 104#L198-4true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 146#L199-4true activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 154#L435-12true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 157#L435-14true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 204#L206-12true assume !(1 == ~t2_pc~0); 203#L206-14true is_transmit2_triggered_~__retres1~2 := 0; 210#L217-4true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 61#L218-4true activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 185#L443-12true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 164#L443-14true assume !(1 == ~M_E~0); 13#L384-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 35#L389-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 64#L394-3true assume 1 == ~E_M~0;~E_M~0 := 2; 192#L399-3true assume 1 == ~E_1~0;~E_1~0 := 2; 218#L404-3true assume 1 == ~E_2~0;~E_2~0 := 2; 121#L409-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 200#L256-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 45#L273-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4#L274-1true start_simulation_#t~ret10 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 124#L574true assume !(0 == start_simulation_~tmp~3); 126#L574-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 173#L256-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 41#L273-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3#L274-2true stop_simulation_#t~ret9 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 155#L529true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 223#L536true stop_simulation_#res := stop_simulation_~__retres2~0; 160#L537true start_simulation_#t~ret11 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 51#L587true assume !(0 != start_simulation_~tmp___0~1); 7#L555-1true [2019-11-25 08:57:07,410 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:07,410 INFO L82 PathProgramCache]: Analyzing trace with hash -1720133594, now seen corresponding path program 1 times [2019-11-25 08:57:07,419 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:07,419 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [432313181] [2019-11-25 08:57:07,419 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:07,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:57:07,544 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:57:07,544 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [432313181] [2019-11-25 08:57:07,545 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:57:07,546 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:57:07,547 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [945371329] [2019-11-25 08:57:07,552 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:57:07,552 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:07,552 INFO L82 PathProgramCache]: Analyzing trace with hash 572791562, now seen corresponding path program 1 times [2019-11-25 08:57:07,553 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:07,553 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [770996452] [2019-11-25 08:57:07,553 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:07,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:57:07,570 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:57:07,571 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [770996452] [2019-11-25 08:57:07,571 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:57:07,571 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:57:07,572 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [782510714] [2019-11-25 08:57:07,573 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:57:07,574 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:57:07,588 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:57:07,589 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:57:07,591 INFO L87 Difference]: Start difference. First operand 223 states. Second operand 3 states. [2019-11-25 08:57:07,623 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:57:07,623 INFO L93 Difference]: Finished difference Result 223 states and 337 transitions. [2019-11-25 08:57:07,624 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:57:07,626 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 223 states and 337 transitions. [2019-11-25 08:57:07,631 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 178 [2019-11-25 08:57:07,638 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 223 states to 217 states and 331 transitions. [2019-11-25 08:57:07,639 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 217 [2019-11-25 08:57:07,641 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 217 [2019-11-25 08:57:07,641 INFO L73 IsDeterministic]: Start isDeterministic. Operand 217 states and 331 transitions. [2019-11-25 08:57:07,643 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:57:07,643 INFO L688 BuchiCegarLoop]: Abstraction has 217 states and 331 transitions. [2019-11-25 08:57:07,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 217 states and 331 transitions. [2019-11-25 08:57:07,680 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 217 to 217. [2019-11-25 08:57:07,680 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 217 states. [2019-11-25 08:57:07,682 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 217 states to 217 states and 331 transitions. [2019-11-25 08:57:07,684 INFO L711 BuchiCegarLoop]: Abstraction has 217 states and 331 transitions. [2019-11-25 08:57:07,684 INFO L591 BuchiCegarLoop]: Abstraction has 217 states and 331 transitions. [2019-11-25 08:57:07,684 INFO L424 BuchiCegarLoop]: ======== Iteration 2============ [2019-11-25 08:57:07,684 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 217 states and 331 transitions. [2019-11-25 08:57:07,686 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 178 [2019-11-25 08:57:07,687 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:57:07,687 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:57:07,689 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:07,689 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:07,690 INFO L794 eck$LassoCheckResult]: Stem: 615#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 466#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 467#L518 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 599#L226 assume 1 == ~m_i~0;~m_st~0 := 0; 600#L233-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 643#L238-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 644#L243-1 assume !(0 == ~M_E~0); 630#L346-1 assume !(0 == ~T1_E~0); 468#L351-1 assume !(0 == ~T2_E~0); 469#L356-1 assume !(0 == ~E_M~0); 520#L361-1 assume !(0 == ~E_1~0); 551#L366-1 assume !(0 == ~E_2~0); 668#L371-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 661#L168 assume 1 == ~m_pc~0; 509#L169 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 510#L179 is_master_triggered_#res := is_master_triggered_~__retres1~0; 512#L180 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 513#L427 assume !(0 != activate_threads_~tmp~1); 543#L427-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 544#L187 assume 1 == ~t1_pc~0; 607#L188 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 609#L198 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 610#L199 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 594#L435 assume !(0 != activate_threads_~tmp___0~0); 595#L435-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 601#L206 assume !(1 == ~t2_pc~0); 529#L206-2 is_transmit2_triggered_~__retres1~2 := 0; 528#L217 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 531#L218 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 532#L443 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 665#L443-2 assume !(1 == ~M_E~0); 514#L384-1 assume !(1 == ~T1_E~0); 515#L389-1 assume !(1 == ~T2_E~0); 519#L394-1 assume !(1 == ~E_M~0); 545#L399-1 assume 1 == ~E_1~0;~E_1~0 := 2; 666#L404-1 assume !(1 == ~E_2~0); 464#L555-1 [2019-11-25 08:57:07,690 INFO L796 eck$LassoCheckResult]: Loop: 464#L555-1 assume !false; 465#L556 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 471#L321 assume !false; 538#L284 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 539#L256 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 536#L273 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 459#L274 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 460#L288 assume !(0 != eval_~tmp~0); 603#L336 start_simulation_~kernel_st~0 := 2; 596#L226-1 start_simulation_~kernel_st~0 := 3; 597#L346-2 assume 0 == ~M_E~0;~M_E~0 := 1; 631#L346-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 479#L351-3 assume !(0 == ~T2_E~0); 480#L356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 522#L361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 565#L366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 670#L371-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 540#L168-12 assume 1 == ~m_pc~0; 485#L169-4 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 486#L179-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 488#L180-4 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 489#L427-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 523#L427-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 524#L187-12 assume 1 == ~t1_pc~0; 578#L188-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 602#L198-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 618#L199-4 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 649#L435-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 654#L435-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 656#L206-12 assume 1 == ~t2_pc~0; 553#L207-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 554#L217-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 556#L218-4 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 557#L443-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 659#L443-14 assume !(1 == ~M_E~0); 476#L384-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 477#L389-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 521#L394-3 assume 1 == ~E_M~0;~E_M~0 := 2; 562#L399-3 assume 1 == ~E_1~0;~E_1~0 := 2; 669#L404-3 assume 1 == ~E_2~0;~E_2~0 := 2; 634#L409-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 635#L256-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 535#L273-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 457#L274-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 458#L574 assume !(0 == start_simulation_~tmp~3); 637#L574-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 639#L256-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 530#L273-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 455#L274-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 456#L529 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 655#L536 stop_simulation_#res := stop_simulation_~__retres2~0; 657#L537 start_simulation_#t~ret11 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 541#L587 assume !(0 != start_simulation_~tmp___0~1); 464#L555-1 [2019-11-25 08:57:07,691 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:07,691 INFO L82 PathProgramCache]: Analyzing trace with hash -1647747036, now seen corresponding path program 1 times [2019-11-25 08:57:07,691 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:07,691 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [635395837] [2019-11-25 08:57:07,692 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:07,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:57:07,720 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:57:07,720 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [635395837] [2019-11-25 08:57:07,720 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:57:07,721 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:57:07,721 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [740033257] [2019-11-25 08:57:07,721 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:57:07,721 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:07,722 INFO L82 PathProgramCache]: Analyzing trace with hash -1082303670, now seen corresponding path program 1 times [2019-11-25 08:57:07,722 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:07,722 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [396161689] [2019-11-25 08:57:07,722 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:07,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:57:07,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:57:07,789 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [396161689] [2019-11-25 08:57:07,790 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:57:07,790 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:57:07,791 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2091988790] [2019-11-25 08:57:07,792 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:57:07,792 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:57:07,792 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:57:07,793 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:57:07,793 INFO L87 Difference]: Start difference. First operand 217 states and 331 transitions. cyclomatic complexity: 115 Second operand 3 states. [2019-11-25 08:57:07,808 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:57:07,808 INFO L93 Difference]: Finished difference Result 217 states and 330 transitions. [2019-11-25 08:57:07,809 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:57:07,809 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 217 states and 330 transitions. [2019-11-25 08:57:07,812 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 178 [2019-11-25 08:57:07,815 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 217 states to 217 states and 330 transitions. [2019-11-25 08:57:07,816 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 217 [2019-11-25 08:57:07,817 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 217 [2019-11-25 08:57:07,817 INFO L73 IsDeterministic]: Start isDeterministic. Operand 217 states and 330 transitions. [2019-11-25 08:57:07,819 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:57:07,819 INFO L688 BuchiCegarLoop]: Abstraction has 217 states and 330 transitions. [2019-11-25 08:57:07,819 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 217 states and 330 transitions. [2019-11-25 08:57:07,828 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 217 to 217. [2019-11-25 08:57:07,828 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 217 states. [2019-11-25 08:57:07,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 217 states to 217 states and 330 transitions. [2019-11-25 08:57:07,830 INFO L711 BuchiCegarLoop]: Abstraction has 217 states and 330 transitions. [2019-11-25 08:57:07,830 INFO L591 BuchiCegarLoop]: Abstraction has 217 states and 330 transitions. [2019-11-25 08:57:07,830 INFO L424 BuchiCegarLoop]: ======== Iteration 3============ [2019-11-25 08:57:07,830 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 217 states and 330 transitions. [2019-11-25 08:57:07,832 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 178 [2019-11-25 08:57:07,833 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:57:07,833 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:57:07,835 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:07,835 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:07,836 INFO L794 eck$LassoCheckResult]: Stem: 1056#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 907#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 908#L518 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1040#L226 assume 1 == ~m_i~0;~m_st~0 := 0; 1041#L233-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1084#L238-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1085#L243-1 assume !(0 == ~M_E~0); 1071#L346-1 assume !(0 == ~T1_E~0); 909#L351-1 assume !(0 == ~T2_E~0); 910#L356-1 assume !(0 == ~E_M~0); 961#L361-1 assume !(0 == ~E_1~0); 992#L366-1 assume !(0 == ~E_2~0); 1109#L371-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1102#L168 assume 1 == ~m_pc~0; 950#L169 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 951#L179 is_master_triggered_#res := is_master_triggered_~__retres1~0; 953#L180 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 954#L427 assume !(0 != activate_threads_~tmp~1); 984#L427-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 985#L187 assume 1 == ~t1_pc~0; 1048#L188 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1050#L198 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1051#L199 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1035#L435 assume !(0 != activate_threads_~tmp___0~0); 1036#L435-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1042#L206 assume !(1 == ~t2_pc~0); 970#L206-2 is_transmit2_triggered_~__retres1~2 := 0; 969#L217 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 972#L218 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 973#L443 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1106#L443-2 assume !(1 == ~M_E~0); 955#L384-1 assume !(1 == ~T1_E~0); 956#L389-1 assume !(1 == ~T2_E~0); 960#L394-1 assume !(1 == ~E_M~0); 986#L399-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1107#L404-1 assume !(1 == ~E_2~0); 905#L555-1 [2019-11-25 08:57:07,836 INFO L796 eck$LassoCheckResult]: Loop: 905#L555-1 assume !false; 906#L556 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 912#L321 assume !false; 979#L284 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 980#L256 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 977#L273 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 900#L274 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 901#L288 assume !(0 != eval_~tmp~0); 1044#L336 start_simulation_~kernel_st~0 := 2; 1037#L226-1 start_simulation_~kernel_st~0 := 3; 1038#L346-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1072#L346-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 920#L351-3 assume !(0 == ~T2_E~0); 921#L356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 963#L361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1006#L366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1111#L371-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 981#L168-12 assume !(1 == ~m_pc~0); 928#L168-14 is_master_triggered_~__retres1~0 := 0; 927#L179-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 929#L180-4 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 930#L427-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 964#L427-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 965#L187-12 assume 1 == ~t1_pc~0; 1019#L188-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1043#L198-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1059#L199-4 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1090#L435-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1095#L435-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1097#L206-12 assume 1 == ~t2_pc~0; 994#L207-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 995#L217-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 997#L218-4 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 998#L443-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1100#L443-14 assume !(1 == ~M_E~0); 917#L384-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 918#L389-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 962#L394-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1003#L399-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1110#L404-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1075#L409-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1076#L256-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 976#L273-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 898#L274-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 899#L574 assume !(0 == start_simulation_~tmp~3); 1078#L574-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1080#L256-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 971#L273-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 896#L274-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 897#L529 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1096#L536 stop_simulation_#res := stop_simulation_~__retres2~0; 1098#L537 start_simulation_#t~ret11 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 982#L587 assume !(0 != start_simulation_~tmp___0~1); 905#L555-1 [2019-11-25 08:57:07,836 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:07,836 INFO L82 PathProgramCache]: Analyzing trace with hash 1945620386, now seen corresponding path program 1 times [2019-11-25 08:57:07,837 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:07,837 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1921138899] [2019-11-25 08:57:07,837 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:07,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:57:07,884 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:57:07,885 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1921138899] [2019-11-25 08:57:07,885 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:57:07,885 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:57:07,885 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [904225799] [2019-11-25 08:57:07,885 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:57:07,886 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:07,886 INFO L82 PathProgramCache]: Analyzing trace with hash 1447847017, now seen corresponding path program 1 times [2019-11-25 08:57:07,886 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:07,886 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [359484921] [2019-11-25 08:57:07,886 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:07,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:57:07,924 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:57:07,924 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [359484921] [2019-11-25 08:57:07,925 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:57:07,925 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:57:07,925 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1830211177] [2019-11-25 08:57:07,925 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:57:07,926 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:57:07,926 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:57:07,926 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:57:07,926 INFO L87 Difference]: Start difference. First operand 217 states and 330 transitions. cyclomatic complexity: 114 Second operand 3 states. [2019-11-25 08:57:08,000 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:57:08,001 INFO L93 Difference]: Finished difference Result 383 states and 570 transitions. [2019-11-25 08:57:08,002 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:57:08,002 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 383 states and 570 transitions. [2019-11-25 08:57:08,006 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 343 [2019-11-25 08:57:08,011 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 383 states to 383 states and 570 transitions. [2019-11-25 08:57:08,011 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 383 [2019-11-25 08:57:08,012 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 383 [2019-11-25 08:57:08,012 INFO L73 IsDeterministic]: Start isDeterministic. Operand 383 states and 570 transitions. [2019-11-25 08:57:08,023 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:57:08,023 INFO L688 BuchiCegarLoop]: Abstraction has 383 states and 570 transitions. [2019-11-25 08:57:08,024 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 383 states and 570 transitions. [2019-11-25 08:57:08,044 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 383 to 364. [2019-11-25 08:57:08,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 364 states. [2019-11-25 08:57:08,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 364 states to 364 states and 544 transitions. [2019-11-25 08:57:08,052 INFO L711 BuchiCegarLoop]: Abstraction has 364 states and 544 transitions. [2019-11-25 08:57:08,053 INFO L591 BuchiCegarLoop]: Abstraction has 364 states and 544 transitions. [2019-11-25 08:57:08,053 INFO L424 BuchiCegarLoop]: ======== Iteration 4============ [2019-11-25 08:57:08,053 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 364 states and 544 transitions. [2019-11-25 08:57:08,055 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 324 [2019-11-25 08:57:08,056 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:57:08,056 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:57:08,057 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:08,057 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:08,058 INFO L794 eck$LassoCheckResult]: Stem: 1671#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 1514#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1515#L518 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1651#L226 assume 1 == ~m_i~0;~m_st~0 := 0; 1652#L233-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1706#L238-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1707#L243-1 assume !(0 == ~M_E~0); 1688#L346-1 assume !(0 == ~T1_E~0); 1516#L351-1 assume !(0 == ~T2_E~0); 1517#L356-1 assume !(0 == ~E_M~0); 1565#L361-1 assume !(0 == ~E_1~0); 1599#L366-1 assume !(0 == ~E_2~0); 1743#L371-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1733#L168 assume !(1 == ~m_pc~0); 1728#L168-2 is_master_triggered_~__retres1~0 := 0; 1729#L179 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1557#L180 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1558#L427 assume !(0 != activate_threads_~tmp~1); 1591#L427-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1592#L187 assume 1 == ~t1_pc~0; 1659#L188 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1661#L198 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1662#L199 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1646#L435 assume !(0 != activate_threads_~tmp___0~0); 1647#L435-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1653#L206 assume !(1 == ~t2_pc~0); 1574#L206-2 is_transmit2_triggered_~__retres1~2 := 0; 1573#L217 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1576#L218 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1577#L443 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1740#L443-2 assume !(1 == ~M_E~0); 1559#L384-1 assume !(1 == ~T1_E~0); 1560#L389-1 assume !(1 == ~T2_E~0); 1564#L394-1 assume !(1 == ~E_M~0); 1593#L399-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1741#L404-1 assume !(1 == ~E_2~0); 1512#L555-1 [2019-11-25 08:57:08,058 INFO L796 eck$LassoCheckResult]: Loop: 1512#L555-1 assume !false; 1513#L556 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 1519#L321 assume !false; 1772#L284 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1769#L256 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1584#L273 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1507#L274 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 1508#L288 assume !(0 != eval_~tmp~0); 1655#L336 start_simulation_~kernel_st~0 := 2; 1648#L226-1 start_simulation_~kernel_st~0 := 3; 1649#L346-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1689#L346-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1526#L351-3 assume !(0 == ~T2_E~0); 1527#L356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1567#L361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1616#L366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1745#L371-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1588#L168-12 assume !(1 == ~m_pc~0); 1578#L168-14 is_master_triggered_~__retres1~0 := 0; 1579#L179-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1536#L180-4 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1537#L427-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1568#L427-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1569#L187-12 assume 1 == ~t1_pc~0; 1629#L188-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1654#L198-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1675#L199-4 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1715#L435-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1723#L435-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1725#L206-12 assume 1 == ~t2_pc~0; 1601#L207-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1602#L217-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1604#L218-4 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1605#L443-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1730#L443-14 assume !(1 == ~M_E~0); 1523#L384-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1524#L389-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1566#L394-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1611#L399-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1744#L404-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1692#L409-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1693#L256-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1582#L273-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1583#L274-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 1781#L574 assume !(0 == start_simulation_~tmp~3); 1700#L574-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1701#L256-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1575#L273-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1503#L274-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 1504#L529 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1724#L536 stop_simulation_#res := stop_simulation_~__retres2~0; 1726#L537 start_simulation_#t~ret11 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 1589#L587 assume !(0 != start_simulation_~tmp___0~1); 1512#L555-1 [2019-11-25 08:57:08,058 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:08,058 INFO L82 PathProgramCache]: Analyzing trace with hash -1569365981, now seen corresponding path program 1 times [2019-11-25 08:57:08,059 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:08,059 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1963191188] [2019-11-25 08:57:08,059 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:08,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:57:08,099 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:57:08,099 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1963191188] [2019-11-25 08:57:08,099 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:57:08,099 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:57:08,100 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2090821696] [2019-11-25 08:57:08,100 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:57:08,100 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:08,100 INFO L82 PathProgramCache]: Analyzing trace with hash 1447847017, now seen corresponding path program 2 times [2019-11-25 08:57:08,100 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:08,101 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [844682513] [2019-11-25 08:57:08,101 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:08,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:57:08,134 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:57:08,134 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [844682513] [2019-11-25 08:57:08,135 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:57:08,135 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:57:08,135 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1993259323] [2019-11-25 08:57:08,135 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:57:08,135 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:57:08,136 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:57:08,136 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:57:08,136 INFO L87 Difference]: Start difference. First operand 364 states and 544 transitions. cyclomatic complexity: 182 Second operand 3 states. [2019-11-25 08:57:08,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:57:08,180 INFO L93 Difference]: Finished difference Result 639 states and 945 transitions. [2019-11-25 08:57:08,181 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:57:08,181 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 639 states and 945 transitions. [2019-11-25 08:57:08,187 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 594 [2019-11-25 08:57:08,193 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 639 states to 639 states and 945 transitions. [2019-11-25 08:57:08,194 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 639 [2019-11-25 08:57:08,195 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 639 [2019-11-25 08:57:08,196 INFO L73 IsDeterministic]: Start isDeterministic. Operand 639 states and 945 transitions. [2019-11-25 08:57:08,199 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:57:08,199 INFO L688 BuchiCegarLoop]: Abstraction has 639 states and 945 transitions. [2019-11-25 08:57:08,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 639 states and 945 transitions. [2019-11-25 08:57:08,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 639 to 635. [2019-11-25 08:57:08,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 635 states. [2019-11-25 08:57:08,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 635 states to 635 states and 941 transitions. [2019-11-25 08:57:08,219 INFO L711 BuchiCegarLoop]: Abstraction has 635 states and 941 transitions. [2019-11-25 08:57:08,219 INFO L591 BuchiCegarLoop]: Abstraction has 635 states and 941 transitions. [2019-11-25 08:57:08,219 INFO L424 BuchiCegarLoop]: ======== Iteration 5============ [2019-11-25 08:57:08,220 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 635 states and 941 transitions. [2019-11-25 08:57:08,227 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 590 [2019-11-25 08:57:08,227 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:57:08,228 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:57:08,229 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:08,229 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:08,230 INFO L794 eck$LassoCheckResult]: Stem: 2671#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 2524#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2525#L518 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2655#L226 assume 1 == ~m_i~0;~m_st~0 := 0; 2656#L233-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2705#L238-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2706#L243-1 assume !(0 == ~M_E~0); 2687#L346-1 assume !(0 == ~T1_E~0); 2526#L351-1 assume !(0 == ~T2_E~0); 2527#L356-1 assume !(0 == ~E_M~0); 2575#L361-1 assume !(0 == ~E_1~0); 2612#L366-1 assume !(0 == ~E_2~0); 2753#L371-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2743#L168 assume !(1 == ~m_pc~0); 2736#L168-2 is_master_triggered_~__retres1~0 := 0; 2737#L179 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2567#L180 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2568#L427 assume !(0 != activate_threads_~tmp~1); 2603#L427-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2604#L187 assume !(1 == ~t1_pc~0); 2663#L187-2 is_transmit1_triggered_~__retres1~1 := 0; 2665#L198 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2666#L199 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2651#L435 assume !(0 != activate_threads_~tmp___0~0); 2652#L435-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2657#L206 assume !(1 == ~t2_pc~0); 2585#L206-2 is_transmit2_triggered_~__retres1~2 := 0; 2584#L217 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2586#L218 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2587#L443 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2750#L443-2 assume !(1 == ~M_E~0); 2569#L384-1 assume !(1 == ~T1_E~0); 2570#L389-1 assume !(1 == ~T2_E~0); 2574#L394-1 assume !(1 == ~E_M~0); 2605#L399-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2751#L404-1 assume !(1 == ~E_2~0); 2760#L555-1 [2019-11-25 08:57:08,230 INFO L796 eck$LassoCheckResult]: Loop: 2760#L555-1 assume !false; 3001#L556 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 2529#L321 assume !false; 2980#L284 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2960#L256 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2958#L273 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2956#L274 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 2953#L288 assume !(0 != eval_~tmp~0); 2954#L336 start_simulation_~kernel_st~0 := 2; 3147#L226-1 start_simulation_~kernel_st~0 := 3; 2688#L346-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2689#L346-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3146#L351-3 assume !(0 == ~T2_E~0); 3145#L356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3144#L361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3143#L366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3142#L371-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3141#L168-12 assume !(1 == ~m_pc~0); 3140#L168-14 is_master_triggered_~__retres1~0 := 0; 3139#L179-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3138#L180-4 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3137#L427-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3136#L427-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3135#L187-12 assume !(1 == ~t1_pc~0); 3103#L187-14 is_transmit1_triggered_~__retres1~1 := 0; 3102#L198-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3101#L199-4 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3100#L435-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3099#L435-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3098#L206-12 assume !(1 == ~t2_pc~0); 3096#L206-14 is_transmit2_triggered_~__retres1~2 := 0; 3095#L217-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3094#L218-4 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3093#L443-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3092#L443-14 assume !(1 == ~M_E~0); 3091#L384-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3090#L389-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3089#L394-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3088#L399-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3087#L404-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3086#L409-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3083#L256-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 3080#L273-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3078#L274-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 3076#L574 assume !(0 == start_simulation_~tmp~3); 3074#L574-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3050#L256-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 3047#L273-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3045#L274-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 3043#L529 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3023#L536 stop_simulation_#res := stop_simulation_~__retres2~0; 3017#L537 start_simulation_#t~ret11 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 3010#L587 assume !(0 != start_simulation_~tmp___0~1); 2760#L555-1 [2019-11-25 08:57:08,231 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:08,231 INFO L82 PathProgramCache]: Analyzing trace with hash 545629540, now seen corresponding path program 1 times [2019-11-25 08:57:08,231 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:08,231 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1262845550] [2019-11-25 08:57:08,232 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:08,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:57:08,305 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:57:08,306 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1262845550] [2019-11-25 08:57:08,306 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:57:08,306 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:57:08,307 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [530399733] [2019-11-25 08:57:08,307 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:57:08,307 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:08,307 INFO L82 PathProgramCache]: Analyzing trace with hash -199692185, now seen corresponding path program 1 times [2019-11-25 08:57:08,308 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:08,308 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2031369983] [2019-11-25 08:57:08,308 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:08,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:57:08,352 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:57:08,352 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2031369983] [2019-11-25 08:57:08,352 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:57:08,353 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:57:08,353 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1677755955] [2019-11-25 08:57:08,353 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:57:08,353 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:57:08,354 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:57:08,354 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:57:08,354 INFO L87 Difference]: Start difference. First operand 635 states and 941 transitions. cyclomatic complexity: 310 Second operand 3 states. [2019-11-25 08:57:08,393 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:57:08,393 INFO L93 Difference]: Finished difference Result 635 states and 919 transitions. [2019-11-25 08:57:08,394 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:57:08,394 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 635 states and 919 transitions. [2019-11-25 08:57:08,400 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 590 [2019-11-25 08:57:08,406 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 635 states to 635 states and 919 transitions. [2019-11-25 08:57:08,407 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 635 [2019-11-25 08:57:08,407 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 635 [2019-11-25 08:57:08,408 INFO L73 IsDeterministic]: Start isDeterministic. Operand 635 states and 919 transitions. [2019-11-25 08:57:08,409 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:57:08,409 INFO L688 BuchiCegarLoop]: Abstraction has 635 states and 919 transitions. [2019-11-25 08:57:08,410 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 635 states and 919 transitions. [2019-11-25 08:57:08,420 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 635 to 635. [2019-11-25 08:57:08,420 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 635 states. [2019-11-25 08:57:08,423 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 635 states to 635 states and 919 transitions. [2019-11-25 08:57:08,424 INFO L711 BuchiCegarLoop]: Abstraction has 635 states and 919 transitions. [2019-11-25 08:57:08,424 INFO L591 BuchiCegarLoop]: Abstraction has 635 states and 919 transitions. [2019-11-25 08:57:08,424 INFO L424 BuchiCegarLoop]: ======== Iteration 6============ [2019-11-25 08:57:08,424 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 635 states and 919 transitions. [2019-11-25 08:57:08,428 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 590 [2019-11-25 08:57:08,429 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:57:08,429 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:57:08,430 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:08,430 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:08,431 INFO L794 eck$LassoCheckResult]: Stem: 3949#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 3801#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 3802#L518 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3933#L226 assume 1 == ~m_i~0;~m_st~0 := 0; 3934#L233-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3978#L238-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3979#L243-1 assume !(0 == ~M_E~0); 3964#L346-1 assume !(0 == ~T1_E~0); 3803#L351-1 assume !(0 == ~T2_E~0); 3804#L356-1 assume !(0 == ~E_M~0); 3852#L361-1 assume !(0 == ~E_1~0); 3885#L366-1 assume !(0 == ~E_2~0); 4016#L371-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4007#L168 assume !(1 == ~m_pc~0); 4003#L168-2 is_master_triggered_~__retres1~0 := 0; 4004#L179 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3844#L180 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3845#L427 assume !(0 != activate_threads_~tmp~1); 3877#L427-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3878#L187 assume !(1 == ~t1_pc~0); 3942#L187-2 is_transmit1_triggered_~__retres1~1 := 0; 3943#L198 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3944#L199 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3928#L435 assume !(0 != activate_threads_~tmp___0~0); 3929#L435-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3935#L206 assume !(1 == ~t2_pc~0); 3861#L206-2 is_transmit2_triggered_~__retres1~2 := 0; 3860#L217 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3863#L218 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3864#L443 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4013#L443-2 assume !(1 == ~M_E~0); 3846#L384-1 assume !(1 == ~T1_E~0); 3847#L389-1 assume !(1 == ~T2_E~0); 3851#L394-1 assume !(1 == ~E_M~0); 3879#L399-1 assume !(1 == ~E_1~0); 4014#L404-1 assume !(1 == ~E_2~0); 4022#L555-1 [2019-11-25 08:57:08,431 INFO L796 eck$LassoCheckResult]: Loop: 4022#L555-1 assume !false; 4131#L556 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 4129#L321 assume !false; 4128#L284 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4125#L256 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 4124#L273 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4122#L274 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 4120#L288 assume !(0 != eval_~tmp~0); 3938#L336 start_simulation_~kernel_st~0 := 2; 3930#L226-1 start_simulation_~kernel_st~0 := 3; 3931#L346-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3965#L346-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3813#L351-3 assume !(0 == ~T2_E~0); 3814#L356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3854#L361-3 assume !(0 == ~E_1~0); 3901#L366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4019#L371-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3874#L168-12 assume !(1 == ~m_pc~0); 3865#L168-14 is_master_triggered_~__retres1~0 := 0; 3866#L179-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3823#L180-4 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3824#L427-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3855#L427-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3856#L187-12 assume !(1 == ~t1_pc~0); 3914#L187-14 is_transmit1_triggered_~__retres1~1 := 0; 4421#L198-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4419#L199-4 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4417#L435-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4415#L435-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4413#L206-12 assume !(1 == ~t2_pc~0); 4410#L206-14 is_transmit2_triggered_~__retres1~2 := 0; 4408#L217-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4406#L218-4 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4404#L443-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4402#L443-14 assume !(1 == ~M_E~0); 4400#L384-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4397#L389-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4395#L394-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4393#L399-3 assume !(1 == ~E_1~0); 4391#L404-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4389#L409-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4385#L256-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 4382#L273-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4380#L274-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 4378#L574 assume !(0 == start_simulation_~tmp~3); 4376#L574-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4374#L256-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 4372#L273-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4369#L274-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 4368#L529 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4367#L536 stop_simulation_#res := stop_simulation_~__retres2~0; 4352#L537 start_simulation_#t~ret11 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 4187#L587 assume !(0 != start_simulation_~tmp___0~1); 4022#L555-1 [2019-11-25 08:57:08,431 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:08,432 INFO L82 PathProgramCache]: Analyzing trace with hash 545629602, now seen corresponding path program 1 times [2019-11-25 08:57:08,432 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:08,432 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [894475203] [2019-11-25 08:57:08,432 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:08,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:57:08,498 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:57:08,498 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [894475203] [2019-11-25 08:57:08,498 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:57:08,498 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-25 08:57:08,499 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [743023386] [2019-11-25 08:57:08,499 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:57:08,499 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:08,499 INFO L82 PathProgramCache]: Analyzing trace with hash 970044267, now seen corresponding path program 1 times [2019-11-25 08:57:08,499 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:08,500 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [146707673] [2019-11-25 08:57:08,500 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:08,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:57:08,526 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:57:08,526 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [146707673] [2019-11-25 08:57:08,526 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:57:08,527 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:57:08,527 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [499110003] [2019-11-25 08:57:08,527 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:57:08,528 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:57:08,528 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-25 08:57:08,528 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-25 08:57:08,528 INFO L87 Difference]: Start difference. First operand 635 states and 919 transitions. cyclomatic complexity: 288 Second operand 5 states. [2019-11-25 08:57:08,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:57:08,724 INFO L93 Difference]: Finished difference Result 1490 states and 2164 transitions. [2019-11-25 08:57:08,725 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-25 08:57:08,725 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1490 states and 2164 transitions. [2019-11-25 08:57:08,738 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1414 [2019-11-25 08:57:08,752 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1490 states to 1490 states and 2164 transitions. [2019-11-25 08:57:08,752 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1490 [2019-11-25 08:57:08,754 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1490 [2019-11-25 08:57:08,754 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1490 states and 2164 transitions. [2019-11-25 08:57:08,757 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:57:08,757 INFO L688 BuchiCegarLoop]: Abstraction has 1490 states and 2164 transitions. [2019-11-25 08:57:08,759 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1490 states and 2164 transitions. [2019-11-25 08:57:08,774 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1490 to 686. [2019-11-25 08:57:08,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 686 states. [2019-11-25 08:57:08,777 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 970 transitions. [2019-11-25 08:57:08,778 INFO L711 BuchiCegarLoop]: Abstraction has 686 states and 970 transitions. [2019-11-25 08:57:08,778 INFO L591 BuchiCegarLoop]: Abstraction has 686 states and 970 transitions. [2019-11-25 08:57:08,778 INFO L424 BuchiCegarLoop]: ======== Iteration 7============ [2019-11-25 08:57:08,778 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 686 states and 970 transitions. [2019-11-25 08:57:08,782 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 638 [2019-11-25 08:57:08,783 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:57:08,783 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:57:08,784 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:08,784 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:08,784 INFO L794 eck$LassoCheckResult]: Stem: 6088#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 5939#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 5940#L518 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6072#L226 assume 1 == ~m_i~0;~m_st~0 := 0; 6073#L233-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6119#L238-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6120#L243-1 assume !(0 == ~M_E~0); 6103#L346-1 assume !(0 == ~T1_E~0); 5941#L351-1 assume !(0 == ~T2_E~0); 5942#L356-1 assume !(0 == ~E_M~0); 5990#L361-1 assume !(0 == ~E_1~0); 6024#L366-1 assume !(0 == ~E_2~0); 6162#L371-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6148#L168 assume !(1 == ~m_pc~0); 6143#L168-2 is_master_triggered_~__retres1~0 := 0; 6144#L179 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5982#L180 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 5983#L427 assume !(0 != activate_threads_~tmp~1); 6016#L427-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6017#L187 assume !(1 == ~t1_pc~0); 6080#L187-2 is_transmit1_triggered_~__retres1~1 := 0; 6081#L198 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6082#L199 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 6068#L435 assume !(0 != activate_threads_~tmp___0~0); 6069#L435-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6074#L206 assume !(1 == ~t2_pc~0); 6000#L206-2 is_transmit2_triggered_~__retres1~2 := 0; 6185#L217 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6188#L218 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6176#L443 assume !(0 != activate_threads_~tmp___1~0); 6157#L443-2 assume !(1 == ~M_E~0); 5984#L384-1 assume !(1 == ~T1_E~0); 5985#L389-1 assume !(1 == ~T2_E~0); 5989#L394-1 assume !(1 == ~E_M~0); 6018#L399-1 assume !(1 == ~E_1~0); 6158#L404-1 assume !(1 == ~E_2~0); 6180#L555-1 [2019-11-25 08:57:08,785 INFO L796 eck$LassoCheckResult]: Loop: 6180#L555-1 assume !false; 6290#L556 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 6285#L321 assume !false; 6011#L284 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6012#L256 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 6009#L273 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5932#L274 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 5933#L288 assume !(0 != eval_~tmp~0); 6113#L336 start_simulation_~kernel_st~0 := 2; 6555#L226-1 start_simulation_~kernel_st~0 := 3; 6553#L346-2 assume 0 == ~M_E~0;~M_E~0 := 1; 6551#L346-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6549#L351-3 assume !(0 == ~T2_E~0); 6547#L356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6545#L361-3 assume !(0 == ~E_1~0); 6543#L366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6541#L371-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6540#L168-12 assume !(1 == ~m_pc~0); 6539#L168-14 is_master_triggered_~__retres1~0 := 0; 6538#L179-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6537#L180-4 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 6536#L427-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6535#L427-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6534#L187-12 assume !(1 == ~t1_pc~0); 6533#L187-14 is_transmit1_triggered_~__retres1~1 := 0; 6532#L198-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6531#L199-4 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 6530#L435-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6529#L435-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6528#L206-12 assume 1 == ~t2_pc~0; 6526#L207-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6524#L217-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6522#L218-4 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6520#L443-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6519#L443-14 assume !(1 == ~M_E~0); 6518#L384-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6517#L389-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6516#L394-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6515#L399-3 assume !(1 == ~E_1~0); 6462#L404-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6460#L409-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6457#L256-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 6425#L273-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6418#L274-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 6412#L574 assume !(0 == start_simulation_~tmp~3); 6403#L574-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6347#L256-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 6344#L273-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6342#L274-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 6326#L529 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6325#L536 stop_simulation_#res := stop_simulation_~__retres2~0; 6324#L537 start_simulation_#t~ret11 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 6323#L587 assume !(0 != start_simulation_~tmp___0~1); 6180#L555-1 [2019-11-25 08:57:08,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:08,785 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 1 times [2019-11-25 08:57:08,786 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:08,786 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1694672510] [2019-11-25 08:57:08,786 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:08,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:57:08,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:57:08,822 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:57:08,822 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:08,823 INFO L82 PathProgramCache]: Analyzing trace with hash -1734528052, now seen corresponding path program 1 times [2019-11-25 08:57:08,823 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:08,823 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1310804534] [2019-11-25 08:57:08,823 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:08,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:57:08,875 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:57:08,875 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1310804534] [2019-11-25 08:57:08,875 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:57:08,876 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:57:08,876 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2043458175] [2019-11-25 08:57:08,876 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:57:08,876 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:57:08,877 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:57:08,877 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:57:08,878 INFO L87 Difference]: Start difference. First operand 686 states and 970 transitions. cyclomatic complexity: 288 Second operand 3 states. [2019-11-25 08:57:08,902 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:57:08,903 INFO L93 Difference]: Finished difference Result 830 states and 1161 transitions. [2019-11-25 08:57:08,903 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:57:08,904 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1161 transitions. [2019-11-25 08:57:08,910 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 754 [2019-11-25 08:57:08,918 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1161 transitions. [2019-11-25 08:57:08,918 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2019-11-25 08:57:08,919 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2019-11-25 08:57:08,920 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1161 transitions. [2019-11-25 08:57:08,921 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:57:08,921 INFO L688 BuchiCegarLoop]: Abstraction has 830 states and 1161 transitions. [2019-11-25 08:57:08,922 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1161 transitions. [2019-11-25 08:57:08,934 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 830. [2019-11-25 08:57:08,934 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 830 states. [2019-11-25 08:57:08,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 830 states to 830 states and 1161 transitions. [2019-11-25 08:57:08,938 INFO L711 BuchiCegarLoop]: Abstraction has 830 states and 1161 transitions. [2019-11-25 08:57:08,938 INFO L591 BuchiCegarLoop]: Abstraction has 830 states and 1161 transitions. [2019-11-25 08:57:08,938 INFO L424 BuchiCegarLoop]: ======== Iteration 8============ [2019-11-25 08:57:08,938 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 830 states and 1161 transitions. [2019-11-25 08:57:08,943 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 754 [2019-11-25 08:57:08,943 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:57:08,943 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:57:08,944 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:08,944 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:08,944 INFO L794 eck$LassoCheckResult]: Stem: 7623#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 7461#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 7462#L518 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7603#L226 assume 1 == ~m_i~0;~m_st~0 := 0; 7604#L233-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7659#L238-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7660#L243-1 assume 0 == ~M_E~0;~M_E~0 := 1; 7639#L346-1 assume !(0 == ~T1_E~0); 7463#L351-1 assume !(0 == ~T2_E~0); 7464#L356-1 assume !(0 == ~E_M~0); 7513#L361-1 assume !(0 == ~E_1~0); 7548#L366-1 assume !(0 == ~E_2~0); 7710#L371-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7696#L168 assume !(1 == ~m_pc~0); 7689#L168-2 is_master_triggered_~__retres1~0 := 0; 7690#L179 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7505#L180 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 7506#L427 assume !(0 != activate_threads_~tmp~1); 7540#L427-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7541#L187 assume !(1 == ~t1_pc~0); 7613#L187-2 is_transmit1_triggered_~__retres1~1 := 0; 7614#L198 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7615#L199 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 7597#L435 assume !(0 != activate_threads_~tmp___0~0); 7598#L435-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7605#L206 assume !(1 == ~t2_pc~0); 7522#L206-2 is_transmit2_triggered_~__retres1~2 := 0; 7924#L217 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7524#L218 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 7525#L443 assume !(0 != activate_threads_~tmp___1~0); 7705#L443-2 assume 1 == ~M_E~0;~M_E~0 := 2; 7507#L384-1 assume !(1 == ~T1_E~0); 7508#L389-1 assume !(1 == ~T2_E~0); 7512#L394-1 assume !(1 == ~E_M~0); 7542#L399-1 assume !(1 == ~E_1~0); 7706#L404-1 assume !(1 == ~E_2~0); 7726#L555-1 [2019-11-25 08:57:08,945 INFO L796 eck$LassoCheckResult]: Loop: 7726#L555-1 assume !false; 8010#L556 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 8009#L321 assume !false; 8008#L284 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 8005#L256 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 8004#L273 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 8003#L274 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 8001#L288 assume !(0 != eval_~tmp~0); 7999#L336 start_simulation_~kernel_st~0 := 2; 7997#L226-1 start_simulation_~kernel_st~0 := 3; 7994#L346-2 assume !(0 == ~M_E~0); 7992#L346-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7990#L351-3 assume !(0 == ~T2_E~0); 7988#L356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7986#L361-3 assume !(0 == ~E_1~0); 7984#L366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7982#L371-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7980#L168-12 assume !(1 == ~m_pc~0); 7978#L168-14 is_master_triggered_~__retres1~0 := 0; 7976#L179-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7974#L180-4 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 7972#L427-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7970#L427-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7968#L187-12 assume !(1 == ~t1_pc~0); 7966#L187-14 is_transmit1_triggered_~__retres1~1 := 0; 7964#L198-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7962#L199-4 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 7960#L435-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7958#L435-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7957#L206-12 assume 1 == ~t2_pc~0; 7955#L207-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7953#L217-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7951#L218-4 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 7947#L443-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7945#L443-14 assume !(1 == ~M_E~0); 7944#L384-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7943#L389-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7942#L394-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7941#L399-3 assume !(1 == ~E_1~0); 7940#L404-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7939#L409-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 7937#L256-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 7935#L273-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 7934#L274-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 7932#L574 assume !(0 == start_simulation_~tmp~3); 7933#L574-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 8027#L256-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 8022#L273-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 8020#L274-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 8019#L529 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 8018#L536 stop_simulation_#res := stop_simulation_~__retres2~0; 8017#L537 start_simulation_#t~ret11 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 8015#L587 assume !(0 != start_simulation_~tmp___0~1); 7726#L555-1 [2019-11-25 08:57:08,945 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:08,945 INFO L82 PathProgramCache]: Analyzing trace with hash -2054220888, now seen corresponding path program 1 times [2019-11-25 08:57:08,945 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:08,946 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1202082514] [2019-11-25 08:57:08,946 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:08,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:57:08,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:57:08,966 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1202082514] [2019-11-25 08:57:08,966 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:57:08,966 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:57:08,967 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [677615501] [2019-11-25 08:57:08,967 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:57:08,967 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:08,967 INFO L82 PathProgramCache]: Analyzing trace with hash 1663045966, now seen corresponding path program 1 times [2019-11-25 08:57:08,967 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:08,967 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1194551471] [2019-11-25 08:57:08,968 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:08,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:57:09,010 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:57:09,011 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1194551471] [2019-11-25 08:57:09,011 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:57:09,011 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-25 08:57:09,011 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1814070446] [2019-11-25 08:57:09,012 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:57:09,012 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:57:09,012 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:57:09,012 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:57:09,012 INFO L87 Difference]: Start difference. First operand 830 states and 1161 transitions. cyclomatic complexity: 335 Second operand 3 states. [2019-11-25 08:57:09,031 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:57:09,031 INFO L93 Difference]: Finished difference Result 686 states and 956 transitions. [2019-11-25 08:57:09,032 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:57:09,032 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 686 states and 956 transitions. [2019-11-25 08:57:09,037 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 638 [2019-11-25 08:57:09,043 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 686 states to 686 states and 956 transitions. [2019-11-25 08:57:09,043 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 686 [2019-11-25 08:57:09,044 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 686 [2019-11-25 08:57:09,044 INFO L73 IsDeterministic]: Start isDeterministic. Operand 686 states and 956 transitions. [2019-11-25 08:57:09,045 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:57:09,045 INFO L688 BuchiCegarLoop]: Abstraction has 686 states and 956 transitions. [2019-11-25 08:57:09,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 686 states and 956 transitions. [2019-11-25 08:57:09,055 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 686 to 686. [2019-11-25 08:57:09,055 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 686 states. [2019-11-25 08:57:09,058 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 956 transitions. [2019-11-25 08:57:09,058 INFO L711 BuchiCegarLoop]: Abstraction has 686 states and 956 transitions. [2019-11-25 08:57:09,058 INFO L591 BuchiCegarLoop]: Abstraction has 686 states and 956 transitions. [2019-11-25 08:57:09,058 INFO L424 BuchiCegarLoop]: ======== Iteration 9============ [2019-11-25 08:57:09,059 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 686 states and 956 transitions. [2019-11-25 08:57:09,063 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 638 [2019-11-25 08:57:09,063 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:57:09,064 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:57:09,065 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:09,065 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:09,065 INFO L794 eck$LassoCheckResult]: Stem: 9135#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 8986#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 8987#L518 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9120#L226 assume 1 == ~m_i~0;~m_st~0 := 0; 9121#L233-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9165#L238-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9166#L243-1 assume !(0 == ~M_E~0); 9151#L346-1 assume !(0 == ~T1_E~0); 8988#L351-1 assume !(0 == ~T2_E~0); 8989#L356-1 assume !(0 == ~E_M~0); 9037#L361-1 assume !(0 == ~E_1~0); 9071#L366-1 assume !(0 == ~E_2~0); 9204#L371-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9195#L168 assume !(1 == ~m_pc~0); 9189#L168-2 is_master_triggered_~__retres1~0 := 0; 9190#L179 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9029#L180 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 9030#L427 assume !(0 != activate_threads_~tmp~1); 9063#L427-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9064#L187 assume !(1 == ~t1_pc~0); 9128#L187-2 is_transmit1_triggered_~__retres1~1 := 0; 9129#L198 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9130#L199 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 9115#L435 assume !(0 != activate_threads_~tmp___0~0); 9116#L435-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9122#L206 assume !(1 == ~t2_pc~0); 9047#L206-2 is_transmit2_triggered_~__retres1~2 := 0; 9215#L217 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9049#L218 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 9050#L443 assume !(0 != activate_threads_~tmp___1~0); 9201#L443-2 assume !(1 == ~M_E~0); 9031#L384-1 assume !(1 == ~T1_E~0); 9032#L389-1 assume !(1 == ~T2_E~0); 9036#L394-1 assume !(1 == ~E_M~0); 9065#L399-1 assume !(1 == ~E_1~0); 9202#L404-1 assume !(1 == ~E_2~0); 9213#L555-1 [2019-11-25 08:57:09,066 INFO L796 eck$LassoCheckResult]: Loop: 9213#L555-1 assume !false; 9264#L556 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 9262#L321 assume !false; 9260#L284 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 9255#L256 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 9253#L273 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 9250#L274 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 9247#L288 assume !(0 != eval_~tmp~0); 9248#L336 start_simulation_~kernel_st~0 := 2; 9653#L226-1 start_simulation_~kernel_st~0 := 3; 9651#L346-2 assume !(0 == ~M_E~0); 9649#L346-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9648#L351-3 assume !(0 == ~T2_E~0); 9647#L356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9646#L361-3 assume !(0 == ~E_1~0); 9645#L366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9644#L371-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9582#L168-12 assume !(1 == ~m_pc~0); 9581#L168-14 is_master_triggered_~__retres1~0 := 0; 9580#L179-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9578#L180-4 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 9577#L427-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 9576#L427-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9575#L187-12 assume !(1 == ~t1_pc~0); 9573#L187-14 is_transmit1_triggered_~__retres1~1 := 0; 9572#L198-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9571#L199-4 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 9570#L435-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9568#L435-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9566#L206-12 assume !(1 == ~t2_pc~0); 9562#L206-14 is_transmit2_triggered_~__retres1~2 := 0; 9560#L217-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9558#L218-4 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 9556#L443-12 assume !(0 != activate_threads_~tmp___1~0); 9553#L443-14 assume !(1 == ~M_E~0); 9551#L384-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9549#L389-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9547#L394-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9545#L399-3 assume !(1 == ~E_1~0); 9543#L404-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9542#L409-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 9536#L256-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 9533#L273-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 9531#L274-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 9528#L574 assume !(0 == start_simulation_~tmp~3); 9527#L574-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 9290#L256-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 9285#L273-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 9279#L274-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 9277#L529 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9275#L536 stop_simulation_#res := stop_simulation_~__retres2~0; 9274#L537 start_simulation_#t~ret11 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 9273#L587 assume !(0 != start_simulation_~tmp___0~1); 9213#L555-1 [2019-11-25 08:57:09,066 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:09,066 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 2 times [2019-11-25 08:57:09,066 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:09,067 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1046083169] [2019-11-25 08:57:09,067 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:09,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:57:09,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:57:09,081 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:57:09,081 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:09,081 INFO L82 PathProgramCache]: Analyzing trace with hash -744997461, now seen corresponding path program 1 times [2019-11-25 08:57:09,082 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:09,082 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [7509793] [2019-11-25 08:57:09,082 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:09,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:57:09,112 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:57:09,112 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [7509793] [2019-11-25 08:57:09,113 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:57:09,113 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-25 08:57:09,113 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [336993846] [2019-11-25 08:57:09,113 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:57:09,113 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:57:09,114 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-25 08:57:09,114 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-25 08:57:09,114 INFO L87 Difference]: Start difference. First operand 686 states and 956 transitions. cyclomatic complexity: 274 Second operand 5 states. [2019-11-25 08:57:09,216 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:57:09,216 INFO L93 Difference]: Finished difference Result 1180 states and 1620 transitions. [2019-11-25 08:57:09,216 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-11-25 08:57:09,217 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1180 states and 1620 transitions. [2019-11-25 08:57:09,226 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1124 [2019-11-25 08:57:09,236 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1180 states to 1180 states and 1620 transitions. [2019-11-25 08:57:09,236 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2019-11-25 08:57:09,239 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2019-11-25 08:57:09,239 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1620 transitions. [2019-11-25 08:57:09,241 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:57:09,241 INFO L688 BuchiCegarLoop]: Abstraction has 1180 states and 1620 transitions. [2019-11-25 08:57:09,242 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1620 transitions. [2019-11-25 08:57:09,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 698. [2019-11-25 08:57:09,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 698 states. [2019-11-25 08:57:09,258 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 698 states to 698 states and 968 transitions. [2019-11-25 08:57:09,258 INFO L711 BuchiCegarLoop]: Abstraction has 698 states and 968 transitions. [2019-11-25 08:57:09,258 INFO L591 BuchiCegarLoop]: Abstraction has 698 states and 968 transitions. [2019-11-25 08:57:09,258 INFO L424 BuchiCegarLoop]: ======== Iteration 10============ [2019-11-25 08:57:09,258 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 698 states and 968 transitions. [2019-11-25 08:57:09,262 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 650 [2019-11-25 08:57:09,262 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:57:09,263 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:57:09,263 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:09,263 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:09,264 INFO L794 eck$LassoCheckResult]: Stem: 11018#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 10868#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 10869#L518 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 11001#L226 assume 1 == ~m_i~0;~m_st~0 := 0; 11002#L233-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11045#L238-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11046#L243-1 assume !(0 == ~M_E~0); 11032#L346-1 assume !(0 == ~T1_E~0); 10870#L351-1 assume !(0 == ~T2_E~0); 10871#L356-1 assume !(0 == ~E_M~0); 10919#L361-1 assume !(0 == ~E_1~0); 10957#L366-1 assume !(0 == ~E_2~0); 11089#L371-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11078#L168 assume !(1 == ~m_pc~0); 11074#L168-2 is_master_triggered_~__retres1~0 := 0; 11075#L179 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10911#L180 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 10912#L427 assume !(0 != activate_threads_~tmp~1); 10949#L427-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10950#L187 assume !(1 == ~t1_pc~0); 11010#L187-2 is_transmit1_triggered_~__retres1~1 := 0; 11012#L198 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11013#L199 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 10997#L435 assume !(0 != activate_threads_~tmp___0~0); 10998#L435-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11003#L206 assume !(1 == ~t2_pc~0); 10929#L206-2 is_transmit2_triggered_~__retres1~2 := 0; 11100#L217 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11101#L218 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 11098#L443 assume !(0 != activate_threads_~tmp___1~0); 11085#L443-2 assume !(1 == ~M_E~0); 10913#L384-1 assume !(1 == ~T1_E~0); 10914#L389-1 assume !(1 == ~T2_E~0); 10918#L394-1 assume !(1 == ~E_M~0); 10951#L399-1 assume !(1 == ~E_1~0); 11086#L404-1 assume !(1 == ~E_2~0); 10866#L555-1 [2019-11-25 08:57:09,264 INFO L796 eck$LassoCheckResult]: Loop: 10866#L555-1 assume !false; 10867#L556 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 10873#L321 assume !false; 10939#L284 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 10940#L256 assume !(0 == ~m_st~0); 11048#L260 assume !(0 == ~t1_st~0); 11015#L264 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 11016#L273 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 11294#L274 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 11293#L288 assume !(0 != eval_~tmp~0); 11005#L336 start_simulation_~kernel_st~0 := 2; 11006#L226-1 start_simulation_~kernel_st~0 := 3; 11163#L346-2 assume !(0 == ~M_E~0); 11162#L346-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11161#L351-3 assume !(0 == ~T2_E~0); 11160#L356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11159#L361-3 assume !(0 == ~E_1~0); 11158#L366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11157#L371-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11155#L168-12 assume !(1 == ~m_pc~0); 11156#L168-14 is_master_triggered_~__retres1~0 := 0; 11118#L179-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11119#L180-4 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 11109#L427-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 11110#L427-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10982#L187-12 assume !(1 == ~t1_pc~0); 10983#L187-14 is_transmit1_triggered_~__retres1~1 := 0; 11004#L198-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11022#L199-4 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 11060#L435-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 11068#L435-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11070#L206-12 assume 1 == ~t2_pc~0; 10954#L207-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 10955#L217-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11467#L218-4 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 11468#L443-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 11073#L443-14 assume !(1 == ~M_E~0); 10877#L384-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10878#L389-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10920#L394-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10964#L399-3 assume !(1 == ~E_1~0); 11090#L404-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11036#L409-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 11037#L256-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 10932#L273-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 10859#L274-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 10860#L574 assume !(0 == start_simulation_~tmp~3); 11039#L574-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 11041#L256-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 10926#L273-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 10857#L274-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 10858#L529 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 11069#L536 stop_simulation_#res := stop_simulation_~__retres2~0; 11071#L537 start_simulation_#t~ret11 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 10943#L587 assume !(0 != start_simulation_~tmp___0~1); 10866#L555-1 [2019-11-25 08:57:09,264 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:09,264 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 3 times [2019-11-25 08:57:09,265 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:09,265 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [949819083] [2019-11-25 08:57:09,265 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:09,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:57:09,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:57:09,290 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:57:09,291 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:09,291 INFO L82 PathProgramCache]: Analyzing trace with hash 1819879637, now seen corresponding path program 1 times [2019-11-25 08:57:09,291 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:09,292 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [805585526] [2019-11-25 08:57:09,292 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:09,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:57:09,357 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:57:09,357 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [805585526] [2019-11-25 08:57:09,358 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:57:09,358 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-25 08:57:09,358 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2024349653] [2019-11-25 08:57:09,358 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:57:09,358 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:57:09,359 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-25 08:57:09,359 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-25 08:57:09,359 INFO L87 Difference]: Start difference. First operand 698 states and 968 transitions. cyclomatic complexity: 274 Second operand 5 states. [2019-11-25 08:57:09,510 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:57:09,510 INFO L93 Difference]: Finished difference Result 1347 states and 1851 transitions. [2019-11-25 08:57:09,511 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-25 08:57:09,511 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1347 states and 1851 transitions. [2019-11-25 08:57:09,521 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1295 [2019-11-25 08:57:09,531 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1347 states to 1347 states and 1851 transitions. [2019-11-25 08:57:09,531 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1347 [2019-11-25 08:57:09,533 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1347 [2019-11-25 08:57:09,533 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1347 states and 1851 transitions. [2019-11-25 08:57:09,535 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:57:09,535 INFO L688 BuchiCegarLoop]: Abstraction has 1347 states and 1851 transitions. [2019-11-25 08:57:09,537 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1347 states and 1851 transitions. [2019-11-25 08:57:09,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1347 to 725. [2019-11-25 08:57:09,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 725 states. [2019-11-25 08:57:09,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 725 states to 725 states and 987 transitions. [2019-11-25 08:57:09,555 INFO L711 BuchiCegarLoop]: Abstraction has 725 states and 987 transitions. [2019-11-25 08:57:09,555 INFO L591 BuchiCegarLoop]: Abstraction has 725 states and 987 transitions. [2019-11-25 08:57:09,555 INFO L424 BuchiCegarLoop]: ======== Iteration 11============ [2019-11-25 08:57:09,555 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 725 states and 987 transitions. [2019-11-25 08:57:09,559 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 677 [2019-11-25 08:57:09,559 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:57:09,559 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:57:09,563 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:09,564 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:09,564 INFO L794 eck$LassoCheckResult]: Stem: 13077#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 12926#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 12927#L518 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 13060#L226 assume 1 == ~m_i~0;~m_st~0 := 0; 13061#L233-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13107#L238-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13108#L243-1 assume !(0 == ~M_E~0); 13091#L346-1 assume !(0 == ~T1_E~0); 12928#L351-1 assume !(0 == ~T2_E~0); 12929#L356-1 assume !(0 == ~E_M~0); 12977#L361-1 assume !(0 == ~E_1~0); 13015#L366-1 assume !(0 == ~E_2~0); 13157#L371-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13146#L168 assume !(1 == ~m_pc~0); 13138#L168-2 is_master_triggered_~__retres1~0 := 0; 13139#L179 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12969#L180 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 12970#L427 assume !(0 != activate_threads_~tmp~1); 13007#L427-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13008#L187 assume !(1 == ~t1_pc~0); 13068#L187-2 is_transmit1_triggered_~__retres1~1 := 0; 13070#L198 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13071#L199 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 13056#L435 assume !(0 != activate_threads_~tmp___0~0); 13057#L435-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13062#L206 assume !(1 == ~t2_pc~0); 12988#L206-2 is_transmit2_triggered_~__retres1~2 := 0; 13167#L217 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13171#L218 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 13164#L443 assume !(0 != activate_threads_~tmp___1~0); 13153#L443-2 assume !(1 == ~M_E~0); 12971#L384-1 assume !(1 == ~T1_E~0); 12972#L389-1 assume !(1 == ~T2_E~0); 12976#L394-1 assume !(1 == ~E_M~0); 13009#L399-1 assume !(1 == ~E_1~0); 13154#L404-1 assume !(1 == ~E_2~0); 13166#L555-1 [2019-11-25 08:57:09,564 INFO L796 eck$LassoCheckResult]: Loop: 13166#L555-1 assume !false; 13416#L556 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 13248#L321 assume !false; 13413#L284 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 13410#L256 assume !(0 == ~m_st~0); 13411#L260 assume !(0 == ~t1_st~0); 13409#L264 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 13406#L273 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 13377#L274 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 13378#L288 assume !(0 != eval_~tmp~0); 13399#L336 start_simulation_~kernel_st~0 := 2; 13395#L226-1 start_simulation_~kernel_st~0 := 3; 13391#L346-2 assume !(0 == ~M_E~0); 13388#L346-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13385#L351-3 assume !(0 == ~T2_E~0); 13382#L356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13379#L361-3 assume !(0 == ~E_1~0); 13223#L366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13224#L371-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12999#L168-12 assume !(1 == ~m_pc~0); 13000#L168-14 is_master_triggered_~__retres1~0 := 0; 13438#L179-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13434#L180-4 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 13430#L427-12 assume !(0 != activate_threads_~tmp~1); 13426#L427-14 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13422#L187-12 assume !(1 == ~t1_pc~0); 13419#L187-14 is_transmit1_triggered_~__retres1~1 := 0; 13418#L198-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13415#L199-4 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 13414#L435-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 13412#L435-14 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13407#L206-12 assume 1 == ~t2_pc~0; 13403#L207-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 13401#L217-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13397#L218-4 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 13393#L443-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 13390#L443-14 assume !(1 == ~M_E~0); 13387#L384-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13384#L389-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13381#L394-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13376#L399-3 assume !(1 == ~E_1~0); 13374#L404-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13373#L409-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 13371#L256-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 13368#L273-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 13366#L274-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 13363#L574 assume !(0 == start_simulation_~tmp~3); 13364#L574-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 13442#L256-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 13439#L273-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 13435#L274-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 13431#L529 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 13427#L536 stop_simulation_#res := stop_simulation_~__retres2~0; 13423#L537 start_simulation_#t~ret11 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 13420#L587 assume !(0 != start_simulation_~tmp___0~1); 13166#L555-1 [2019-11-25 08:57:09,564 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:09,565 INFO L82 PathProgramCache]: Analyzing trace with hash -1974330332, now seen corresponding path program 4 times [2019-11-25 08:57:09,568 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:09,569 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1347263631] [2019-11-25 08:57:09,569 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:09,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:57:09,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:57:09,587 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:57:09,588 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:09,588 INFO L82 PathProgramCache]: Analyzing trace with hash 2094639251, now seen corresponding path program 1 times [2019-11-25 08:57:09,588 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:09,588 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1982705229] [2019-11-25 08:57:09,589 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:09,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:57:09,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:57:09,614 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1982705229] [2019-11-25 08:57:09,615 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:57:09,615 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:57:09,615 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2002201955] [2019-11-25 08:57:09,615 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:57:09,616 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:57:09,616 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:57:09,616 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:57:09,616 INFO L87 Difference]: Start difference. First operand 725 states and 987 transitions. cyclomatic complexity: 266 Second operand 3 states. [2019-11-25 08:57:09,655 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:57:09,655 INFO L93 Difference]: Finished difference Result 1128 states and 1507 transitions. [2019-11-25 08:57:09,655 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:57:09,655 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1128 states and 1507 transitions. [2019-11-25 08:57:09,663 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1074 [2019-11-25 08:57:09,671 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1128 states to 1128 states and 1507 transitions. [2019-11-25 08:57:09,671 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1128 [2019-11-25 08:57:09,673 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1128 [2019-11-25 08:57:09,673 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1128 states and 1507 transitions. [2019-11-25 08:57:09,675 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:57:09,675 INFO L688 BuchiCegarLoop]: Abstraction has 1128 states and 1507 transitions. [2019-11-25 08:57:09,676 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1128 states and 1507 transitions. [2019-11-25 08:57:09,692 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1128 to 1093. [2019-11-25 08:57:09,693 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1093 states. [2019-11-25 08:57:09,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1093 states to 1093 states and 1462 transitions. [2019-11-25 08:57:09,696 INFO L711 BuchiCegarLoop]: Abstraction has 1093 states and 1462 transitions. [2019-11-25 08:57:09,697 INFO L591 BuchiCegarLoop]: Abstraction has 1093 states and 1462 transitions. [2019-11-25 08:57:09,697 INFO L424 BuchiCegarLoop]: ======== Iteration 12============ [2019-11-25 08:57:09,697 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1093 states and 1462 transitions. [2019-11-25 08:57:09,702 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1039 [2019-11-25 08:57:09,702 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:57:09,702 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:57:09,703 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:09,703 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:09,703 INFO L794 eck$LassoCheckResult]: Stem: 14943#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 14785#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 14786#L518 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 14926#L226 assume 1 == ~m_i~0;~m_st~0 := 0; 14927#L233-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14973#L238-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14974#L243-1 assume !(0 == ~M_E~0); 14958#L346-1 assume !(0 == ~T1_E~0); 14787#L351-1 assume !(0 == ~T2_E~0); 14788#L356-1 assume !(0 == ~E_M~0); 14838#L361-1 assume !(0 == ~E_1~0); 14878#L366-1 assume !(0 == ~E_2~0); 15020#L371-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15006#L168 assume !(1 == ~m_pc~0); 14999#L168-2 is_master_triggered_~__retres1~0 := 0; 15000#L179 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14830#L180 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 14831#L427 assume !(0 != activate_threads_~tmp~1); 14868#L427-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14869#L187 assume !(1 == ~t1_pc~0); 14934#L187-2 is_transmit1_triggered_~__retres1~1 := 0; 14936#L198 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14937#L199 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 14920#L435 assume !(0 != activate_threads_~tmp___0~0); 14921#L435-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14928#L206 assume !(1 == ~t2_pc~0); 14848#L206-2 is_transmit2_triggered_~__retres1~2 := 0; 15040#L217 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14849#L218 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 14850#L443 assume !(0 != activate_threads_~tmp___1~0); 15017#L443-2 assume !(1 == ~M_E~0); 14832#L384-1 assume !(1 == ~T1_E~0); 14833#L389-1 assume !(1 == ~T2_E~0); 14837#L394-1 assume !(1 == ~E_M~0); 14870#L399-1 assume !(1 == ~E_1~0); 15018#L404-1 assume !(1 == ~E_2~0); 15039#L555-1 assume !false; 15633#L556 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 15729#L321 [2019-11-25 08:57:09,704 INFO L796 eck$LassoCheckResult]: Loop: 15729#L321 assume !false; 15727#L284 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 15671#L256 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 15672#L273 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 15861#L274 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 15860#L288 assume 0 != eval_~tmp~0; 15859#L288-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 14780#L296 assume !(0 != eval_~tmp_ndt_1~0); 14781#L293 assume !(0 == ~t1_st~0); 15513#L307 assume !(0 == ~t2_st~0); 15729#L321 [2019-11-25 08:57:09,704 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:09,704 INFO L82 PathProgramCache]: Analyzing trace with hash 1044101446, now seen corresponding path program 1 times [2019-11-25 08:57:09,704 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:09,704 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1398464606] [2019-11-25 08:57:09,705 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:09,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:57:09,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:57:09,717 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:57:09,717 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:09,718 INFO L82 PathProgramCache]: Analyzing trace with hash -1924934063, now seen corresponding path program 1 times [2019-11-25 08:57:09,718 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:09,718 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [159185926] [2019-11-25 08:57:09,718 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:09,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:57:09,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:57:09,724 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:57:09,724 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:09,724 INFO L82 PathProgramCache]: Analyzing trace with hash -460292778, now seen corresponding path program 1 times [2019-11-25 08:57:09,724 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:09,724 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1102696165] [2019-11-25 08:57:09,724 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:09,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:57:09,758 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:57:09,758 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1102696165] [2019-11-25 08:57:09,758 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:57:09,758 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:57:09,759 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1922749698] [2019-11-25 08:57:09,830 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:57:09,830 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:57:09,830 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:57:09,831 INFO L87 Difference]: Start difference. First operand 1093 states and 1462 transitions. cyclomatic complexity: 375 Second operand 3 states. [2019-11-25 08:57:09,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:57:09,886 INFO L93 Difference]: Finished difference Result 1970 states and 2606 transitions. [2019-11-25 08:57:09,886 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:57:09,886 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1970 states and 2606 transitions. [2019-11-25 08:57:09,898 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 1686 [2019-11-25 08:57:09,912 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1970 states to 1970 states and 2606 transitions. [2019-11-25 08:57:09,913 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1970 [2019-11-25 08:57:09,915 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1970 [2019-11-25 08:57:09,915 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1970 states and 2606 transitions. [2019-11-25 08:57:09,918 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:57:09,918 INFO L688 BuchiCegarLoop]: Abstraction has 1970 states and 2606 transitions. [2019-11-25 08:57:09,920 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1970 states and 2606 transitions. [2019-11-25 08:57:09,947 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1970 to 1918. [2019-11-25 08:57:09,948 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1918 states. [2019-11-25 08:57:09,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1918 states to 1918 states and 2542 transitions. [2019-11-25 08:57:09,954 INFO L711 BuchiCegarLoop]: Abstraction has 1918 states and 2542 transitions. [2019-11-25 08:57:09,954 INFO L591 BuchiCegarLoop]: Abstraction has 1918 states and 2542 transitions. [2019-11-25 08:57:09,954 INFO L424 BuchiCegarLoop]: ======== Iteration 13============ [2019-11-25 08:57:09,954 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1918 states and 2542 transitions. [2019-11-25 08:57:09,963 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 1634 [2019-11-25 08:57:09,963 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:57:09,963 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:57:09,964 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:09,964 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:09,964 INFO L794 eck$LassoCheckResult]: Stem: 18015#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 17856#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 17857#L518 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 17996#L226 assume 1 == ~m_i~0;~m_st~0 := 0; 17997#L233-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 18048#L238-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18049#L243-1 assume !(0 == ~M_E~0); 18032#L346-1 assume !(0 == ~T1_E~0); 17858#L351-1 assume !(0 == ~T2_E~0); 17859#L356-1 assume !(0 == ~E_M~0); 17909#L361-1 assume !(0 == ~E_1~0); 17949#L366-1 assume !(0 == ~E_2~0); 18105#L371-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 18090#L168 assume !(1 == ~m_pc~0); 18082#L168-2 is_master_triggered_~__retres1~0 := 0; 18083#L179 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17901#L180 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 17902#L427 assume !(0 != activate_threads_~tmp~1); 17939#L427-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17940#L187 assume !(1 == ~t1_pc~0); 18004#L187-2 is_transmit1_triggered_~__retres1~1 := 0; 18007#L198 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 18008#L199 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 17991#L435 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 17992#L435-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 19300#L206 assume !(1 == ~t2_pc~0); 18121#L206-2 is_transmit2_triggered_~__retres1~2 := 0; 18122#L217 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17922#L218 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 17923#L443 assume !(0 != activate_threads_~tmp___1~0); 18101#L443-2 assume !(1 == ~M_E~0); 17903#L384-1 assume !(1 == ~T1_E~0); 17904#L389-1 assume !(1 == ~T2_E~0); 17908#L394-1 assume !(1 == ~E_M~0); 19275#L399-1 assume !(1 == ~E_1~0); 19273#L404-1 assume !(1 == ~E_2~0); 19271#L555-1 assume !false; 19247#L556 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 19245#L321 [2019-11-25 08:57:09,965 INFO L796 eck$LassoCheckResult]: Loop: 19245#L321 assume !false; 19243#L284 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 19241#L256 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 19238#L273 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 19236#L274 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 19235#L288 assume 0 != eval_~tmp~0; 19231#L288-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 18180#L296 assume !(0 != eval_~tmp_ndt_1~0); 18181#L293 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 19253#L310 assume !(0 != eval_~tmp_ndt_2~0); 19251#L307 assume !(0 == ~t2_st~0); 19245#L321 [2019-11-25 08:57:09,965 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:09,965 INFO L82 PathProgramCache]: Analyzing trace with hash 79981826, now seen corresponding path program 1 times [2019-11-25 08:57:09,965 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:09,965 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [282032059] [2019-11-25 08:57:09,966 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:09,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:57:09,979 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:57:09,979 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [282032059] [2019-11-25 08:57:09,979 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:57:09,979 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:57:09,980 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1330702179] [2019-11-25 08:57:09,980 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:57:09,980 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:09,980 INFO L82 PathProgramCache]: Analyzing trace with hash 456481406, now seen corresponding path program 1 times [2019-11-25 08:57:09,980 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:09,980 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1328776666] [2019-11-25 08:57:09,980 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:09,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:57:09,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:57:09,986 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:57:10,082 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:57:10,083 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:57:10,083 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:57:10,083 INFO L87 Difference]: Start difference. First operand 1918 states and 2542 transitions. cyclomatic complexity: 633 Second operand 3 states. [2019-11-25 08:57:10,091 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:57:10,092 INFO L93 Difference]: Finished difference Result 1240 states and 1643 transitions. [2019-11-25 08:57:10,093 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:57:10,093 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1240 states and 1643 transitions. [2019-11-25 08:57:10,099 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1184 [2019-11-25 08:57:10,107 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1240 states to 1240 states and 1643 transitions. [2019-11-25 08:57:10,108 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1240 [2019-11-25 08:57:10,109 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1240 [2019-11-25 08:57:10,109 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1240 states and 1643 transitions. [2019-11-25 08:57:10,111 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:57:10,111 INFO L688 BuchiCegarLoop]: Abstraction has 1240 states and 1643 transitions. [2019-11-25 08:57:10,113 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1240 states and 1643 transitions. [2019-11-25 08:57:10,129 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1240 to 1240. [2019-11-25 08:57:10,130 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1240 states. [2019-11-25 08:57:10,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1240 states to 1240 states and 1643 transitions. [2019-11-25 08:57:10,134 INFO L711 BuchiCegarLoop]: Abstraction has 1240 states and 1643 transitions. [2019-11-25 08:57:10,134 INFO L591 BuchiCegarLoop]: Abstraction has 1240 states and 1643 transitions. [2019-11-25 08:57:10,134 INFO L424 BuchiCegarLoop]: ======== Iteration 14============ [2019-11-25 08:57:10,134 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1240 states and 1643 transitions. [2019-11-25 08:57:10,138 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1184 [2019-11-25 08:57:10,138 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:57:10,138 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:57:10,139 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:10,139 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:10,139 INFO L794 eck$LassoCheckResult]: Stem: 21181#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 21020#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 21021#L518 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 21160#L226 assume 1 == ~m_i~0;~m_st~0 := 0; 21161#L233-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21213#L238-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21214#L243-1 assume !(0 == ~M_E~0); 21196#L346-1 assume !(0 == ~T1_E~0); 21022#L351-1 assume !(0 == ~T2_E~0); 21023#L356-1 assume !(0 == ~E_M~0); 21071#L361-1 assume !(0 == ~E_1~0); 21113#L366-1 assume !(0 == ~E_2~0); 21254#L371-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21244#L168 assume !(1 == ~m_pc~0); 21237#L168-2 is_master_triggered_~__retres1~0 := 0; 21238#L179 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21063#L180 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 21064#L427 assume !(0 != activate_threads_~tmp~1); 21104#L427-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 21105#L187 assume !(1 == ~t1_pc~0); 21169#L187-2 is_transmit1_triggered_~__retres1~1 := 0; 21172#L198 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21173#L199 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 21155#L435 assume !(0 != activate_threads_~tmp___0~0); 21156#L435-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 21162#L206 assume !(1 == ~t2_pc~0); 21082#L206-2 is_transmit2_triggered_~__retres1~2 := 0; 21269#L217 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21271#L218 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 21264#L443 assume !(0 != activate_threads_~tmp___1~0); 21250#L443-2 assume !(1 == ~M_E~0); 21065#L384-1 assume !(1 == ~T1_E~0); 21066#L389-1 assume !(1 == ~T2_E~0); 21070#L394-1 assume !(1 == ~E_M~0); 21106#L399-1 assume !(1 == ~E_1~0); 21251#L404-1 assume !(1 == ~E_2~0); 21267#L555-1 assume !false; 22009#L556 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 22008#L321 [2019-11-25 08:57:10,140 INFO L796 eck$LassoCheckResult]: Loop: 22008#L321 assume !false; 22007#L284 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 22005#L256 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 22004#L273 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 22002#L274 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 22001#L288 assume 0 != eval_~tmp~0; 22000#L288-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 21015#L296 assume !(0 != eval_~tmp_ndt_1~0); 21016#L293 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 21198#L310 assume !(0 != eval_~tmp_ndt_2~0); 21200#L307 assume !(0 == ~t2_st~0); 22008#L321 [2019-11-25 08:57:10,140 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:10,140 INFO L82 PathProgramCache]: Analyzing trace with hash 1044101446, now seen corresponding path program 2 times [2019-11-25 08:57:10,140 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:10,140 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [748158470] [2019-11-25 08:57:10,141 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:10,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:57:10,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:57:10,153 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:57:10,154 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:10,154 INFO L82 PathProgramCache]: Analyzing trace with hash 456481406, now seen corresponding path program 2 times [2019-11-25 08:57:10,154 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:10,154 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1790723943] [2019-11-25 08:57:10,155 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:10,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:57:10,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:57:10,171 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:57:10,171 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:10,171 INFO L82 PathProgramCache]: Analyzing trace with hash -1384279015, now seen corresponding path program 1 times [2019-11-25 08:57:10,172 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:10,172 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2054308572] [2019-11-25 08:57:10,172 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:10,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:57:10,197 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:57:10,197 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2054308572] [2019-11-25 08:57:10,197 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:57:10,197 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:57:10,197 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [74697328] [2019-11-25 08:57:10,294 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:57:10,295 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:57:10,295 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:57:10,295 INFO L87 Difference]: Start difference. First operand 1240 states and 1643 transitions. cyclomatic complexity: 409 Second operand 3 states. [2019-11-25 08:57:10,355 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:57:10,355 INFO L93 Difference]: Finished difference Result 1981 states and 2610 transitions. [2019-11-25 08:57:10,356 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:57:10,356 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1981 states and 2610 transitions. [2019-11-25 08:57:10,366 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1911 [2019-11-25 08:57:10,380 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1981 states to 1981 states and 2610 transitions. [2019-11-25 08:57:10,380 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1981 [2019-11-25 08:57:10,382 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1981 [2019-11-25 08:57:10,382 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1981 states and 2610 transitions. [2019-11-25 08:57:10,385 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:57:10,386 INFO L688 BuchiCegarLoop]: Abstraction has 1981 states and 2610 transitions. [2019-11-25 08:57:10,387 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1981 states and 2610 transitions. [2019-11-25 08:57:10,413 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1981 to 1945. [2019-11-25 08:57:10,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1945 states. [2019-11-25 08:57:10,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1945 states to 1945 states and 2574 transitions. [2019-11-25 08:57:10,419 INFO L711 BuchiCegarLoop]: Abstraction has 1945 states and 2574 transitions. [2019-11-25 08:57:10,419 INFO L591 BuchiCegarLoop]: Abstraction has 1945 states and 2574 transitions. [2019-11-25 08:57:10,420 INFO L424 BuchiCegarLoop]: ======== Iteration 15============ [2019-11-25 08:57:10,420 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1945 states and 2574 transitions. [2019-11-25 08:57:10,425 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1875 [2019-11-25 08:57:10,426 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:57:10,426 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:57:10,426 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:10,426 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:57:10,427 INFO L794 eck$LassoCheckResult]: Stem: 24406#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 24249#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 24250#L518 havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 24387#L226 assume 1 == ~m_i~0;~m_st~0 := 0; 24388#L233-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24444#L238-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24445#L243-1 assume !(0 == ~M_E~0); 24427#L346-1 assume !(0 == ~T1_E~0); 24251#L351-1 assume !(0 == ~T2_E~0); 24252#L356-1 assume !(0 == ~E_M~0); 24299#L361-1 assume !(0 == ~E_1~0); 24335#L366-1 assume !(0 == ~E_2~0); 24492#L371-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 24477#L168 assume !(1 == ~m_pc~0); 24467#L168-2 is_master_triggered_~__retres1~0 := 0; 24468#L179 is_master_triggered_#res := is_master_triggered_~__retres1~0; 24291#L180 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 24292#L427 assume !(0 != activate_threads_~tmp~1); 24327#L427-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 24328#L187 assume !(1 == ~t1_pc~0); 24396#L187-2 is_transmit1_triggered_~__retres1~1 := 0; 24397#L198 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 24398#L199 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 24382#L435 assume !(0 != activate_threads_~tmp___0~0); 24383#L435-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 24389#L206 assume !(1 == ~t2_pc~0); 24309#L206-2 is_transmit2_triggered_~__retres1~2 := 0; 24506#L217 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 24311#L218 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 24312#L443 assume !(0 != activate_threads_~tmp___1~0); 24486#L443-2 assume !(1 == ~M_E~0); 24293#L384-1 assume !(1 == ~T1_E~0); 24294#L389-1 assume !(1 == ~T2_E~0); 24298#L394-1 assume !(1 == ~E_M~0); 24329#L399-1 assume !(1 == ~E_1~0); 24487#L404-1 assume !(1 == ~E_2~0); 24505#L555-1 assume !false; 25636#L556 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret2, eval_#t~nondet3, eval_~tmp_ndt_1~0, eval_#t~nondet4, eval_~tmp_ndt_2~0, eval_#t~nondet5, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 25633#L321 [2019-11-25 08:57:10,427 INFO L796 eck$LassoCheckResult]: Loop: 25633#L321 assume !false; 25608#L284 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 25605#L256 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 25601#L273 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 25597#L274 eval_#t~ret2 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret2;havoc eval_#t~ret2; 25594#L288 assume 0 != eval_~tmp~0; 25591#L288-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 25587#L296 assume !(0 != eval_~tmp_ndt_1~0); 25588#L293 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 25725#L310 assume !(0 != eval_~tmp_ndt_2~0); 25640#L307 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 25637#L324 assume !(0 != eval_~tmp_ndt_3~0); 25633#L321 [2019-11-25 08:57:10,428 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:10,428 INFO L82 PathProgramCache]: Analyzing trace with hash 1044101446, now seen corresponding path program 3 times [2019-11-25 08:57:10,428 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:10,428 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [584008471] [2019-11-25 08:57:10,429 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:10,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:57:10,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:57:10,440 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:57:10,441 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:10,441 INFO L82 PathProgramCache]: Analyzing trace with hash 1266018993, now seen corresponding path program 1 times [2019-11-25 08:57:10,441 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:10,441 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [108168127] [2019-11-25 08:57:10,441 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:10,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:57:10,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:57:10,447 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:57:10,448 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:57:10,448 INFO L82 PathProgramCache]: Analyzing trace with hash 37020790, now seen corresponding path program 1 times [2019-11-25 08:57:10,448 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:57:10,448 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [20259667] [2019-11-25 08:57:10,448 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:57:10,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:57:10,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:57:10,464 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:57:10,843 WARN L192 SmtUtils]: Spent 293.00 ms on a formula simplification. DAG size of input: 105 DAG size of output: 72 [2019-11-25 08:57:10,953 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 25.11 08:57:10 BoogieIcfgContainer [2019-11-25 08:57:10,953 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2019-11-25 08:57:10,954 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-25 08:57:10,954 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-25 08:57:10,954 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-25 08:57:10,955 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 08:57:07" (3/4) ... [2019-11-25 08:57:10,957 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2019-11-25 08:57:11,006 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_2c69e248-9022-4c2a-8724-f6c8c490df92/bin/uautomizer/witness.graphml [2019-11-25 08:57:11,006 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-25 08:57:11,007 INFO L168 Benchmark]: Toolchain (without parser) took 5088.36 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 193.5 MB). Free memory was 943.4 MB in the beginning and 1.1 GB in the end (delta: -124.9 MB). Peak memory consumption was 68.5 MB. Max. memory is 11.5 GB. [2019-11-25 08:57:11,008 INFO L168 Benchmark]: CDTParser took 0.18 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-25 08:57:11,008 INFO L168 Benchmark]: CACSL2BoogieTranslator took 405.85 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 138.9 MB). Free memory was 943.4 MB in the beginning and 1.1 GB in the end (delta: -190.4 MB). Peak memory consumption was 23.1 MB. Max. memory is 11.5 GB. [2019-11-25 08:57:11,008 INFO L168 Benchmark]: Boogie Procedure Inliner took 47.58 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-25 08:57:11,009 INFO L168 Benchmark]: Boogie Preprocessor took 60.11 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. [2019-11-25 08:57:11,009 INFO L168 Benchmark]: RCFGBuilder took 836.48 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 60.0 MB). Peak memory consumption was 60.0 MB. Max. memory is 11.5 GB. [2019-11-25 08:57:11,009 INFO L168 Benchmark]: BuchiAutomizer took 3682.30 ms. Allocated memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 54.5 MB). Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: -15.0 MB). Peak memory consumption was 39.5 MB. Max. memory is 11.5 GB. [2019-11-25 08:57:11,010 INFO L168 Benchmark]: Witness Printer took 52.38 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 8.4 MB). Peak memory consumption was 8.4 MB. Max. memory is 11.5 GB. [2019-11-25 08:57:11,012 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 405.85 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 138.9 MB). Free memory was 943.4 MB in the beginning and 1.1 GB in the end (delta: -190.4 MB). Peak memory consumption was 23.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 47.58 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 60.11 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 836.48 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 60.0 MB). Peak memory consumption was 60.0 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 3682.30 ms. Allocated memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 54.5 MB). Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: -15.0 MB). Peak memory consumption was 39.5 MB. Max. memory is 11.5 GB. * Witness Printer took 52.38 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 8.4 MB). Peak memory consumption was 8.4 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 14 terminating modules (14 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.14 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 1945 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 3.6s and 15 iterations. TraceHistogramMax:1. Analysis of lassos took 1.9s. Construction of modules took 0.4s. Büchi inclusion checks took 0.4s. Highest rank in rank-based complementation 0. Minimization of det autom 14. Minimization of nondet autom 0. Automata minimization 0.2s AutomataMinimizationTime, 14 MinimizatonAttempts, 2054 StatesRemovedByMinimization, 8 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had 1945 states and ocurred in iteration 14. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 4568 SDtfs, 4841 SDslu, 4728 SDs, 0 SdLazy, 316 SolverSat, 133 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.4s Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc2 concLT0 SILN1 SILU0 SILI7 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 283]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {\result=0, token=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@300f03e9=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@b0a81f2=0, tmp=1, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@543fadd=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@50566862=0, T2_E=2, kernel_st=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4dc4a6db=0, __retres1=0, tmp___0=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@56fc2fac=0, t2_st=0, t1_pc=0, E_2=2, __retres1=1, T1_E=2, \result=0, E_1=2, tmp_ndt_1=0, M_E=2, tmp_ndt_2=0, tmp=0, tmp_ndt_3=0, __retres1=0, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@35900e7f=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@33b186ba=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@27db6634=0, t1_st=0, \result=0, t2_pc=0, local=0, m_st=0, tmp___1=0, E_M=2, tmp___0=0, tmp=0, __retres1=0, t1_i=1, m_pc=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 283]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int m_st ; [L18] int t1_st ; [L19] int t2_st ; [L20] int m_i ; [L21] int t1_i ; [L22] int t2_i ; [L23] int M_E = 2; [L24] int T1_E = 2; [L25] int T2_E = 2; [L26] int E_M = 2; [L27] int E_1 = 2; [L28] int E_2 = 2; [L33] int token ; [L35] int local ; [L600] int __retres1 ; [L514] m_i = 1 [L515] t1_i = 1 [L516] t2_i = 1 [L541] int kernel_st ; [L542] int tmp ; [L543] int tmp___0 ; [L547] kernel_st = 0 [L233] COND TRUE m_i == 1 [L234] m_st = 0 [L238] COND TRUE t1_i == 1 [L239] t1_st = 0 [L243] COND TRUE t2_i == 1 [L244] t2_st = 0 [L346] COND FALSE !(M_E == 0) [L351] COND FALSE !(T1_E == 0) [L356] COND FALSE !(T2_E == 0) [L361] COND FALSE !(E_M == 0) [L366] COND FALSE !(E_1 == 0) [L371] COND FALSE !(E_2 == 0) [L419] int tmp ; [L420] int tmp___0 ; [L421] int tmp___1 ; [L165] int __retres1 ; [L168] COND FALSE !(m_pc == 1) [L178] __retres1 = 0 [L180] return (__retres1); [L425] tmp = is_master_triggered() [L427] COND FALSE !(\read(tmp)) [L184] int __retres1 ; [L187] COND FALSE !(t1_pc == 1) [L197] __retres1 = 0 [L199] return (__retres1); [L433] tmp___0 = is_transmit1_triggered() [L435] COND FALSE !(\read(tmp___0)) [L203] int __retres1 ; [L206] COND FALSE !(t2_pc == 1) [L216] __retres1 = 0 [L218] return (__retres1); [L441] tmp___1 = is_transmit2_triggered() [L443] COND FALSE !(\read(tmp___1)) [L384] COND FALSE !(M_E == 1) [L389] COND FALSE !(T1_E == 1) [L394] COND FALSE !(T2_E == 1) [L399] COND FALSE !(E_M == 1) [L404] COND FALSE !(E_1 == 1) [L409] COND FALSE !(E_2 == 1) [L555] COND TRUE 1 [L558] kernel_st = 1 [L279] int tmp ; Loop: [L283] COND TRUE 1 [L253] int __retres1 ; [L256] COND TRUE m_st == 0 [L257] __retres1 = 1 [L274] return (__retres1); [L286] tmp = exists_runnable_thread() [L288] COND TRUE \read(tmp) [L293] COND TRUE m_st == 0 [L294] int tmp_ndt_1; [L295] tmp_ndt_1 = __VERIFIER_nondet_int() [L296] COND FALSE !(\read(tmp_ndt_1)) [L307] COND TRUE t1_st == 0 [L308] int tmp_ndt_2; [L309] tmp_ndt_2 = __VERIFIER_nondet_int() [L310] COND FALSE !(\read(tmp_ndt_2)) [L321] COND TRUE t2_st == 0 [L322] int tmp_ndt_3; [L323] tmp_ndt_3 = __VERIFIER_nondet_int() [L324] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...