./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.04.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 6b5699aa Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.04.cil.c -s /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bcbeb24241e70d50816527d1472e428919d63db5 ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.24-6b5699a [2019-11-25 08:52:59,370 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-25 08:52:59,371 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-25 08:52:59,383 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-25 08:52:59,384 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-25 08:52:59,385 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-25 08:52:59,387 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-25 08:52:59,395 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-25 08:52:59,399 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-25 08:52:59,402 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-25 08:52:59,403 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-25 08:52:59,404 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-25 08:52:59,404 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-25 08:52:59,406 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-25 08:52:59,407 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-25 08:52:59,408 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-25 08:52:59,409 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-25 08:52:59,410 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-25 08:52:59,413 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-25 08:52:59,415 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-25 08:52:59,416 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-25 08:52:59,417 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-25 08:52:59,418 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-25 08:52:59,419 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-25 08:52:59,421 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-25 08:52:59,421 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-25 08:52:59,421 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-25 08:52:59,422 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-25 08:52:59,422 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-25 08:52:59,423 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-25 08:52:59,423 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-25 08:52:59,424 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-25 08:52:59,424 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-25 08:52:59,425 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-25 08:52:59,426 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-25 08:52:59,426 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-25 08:52:59,427 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-25 08:52:59,427 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-25 08:52:59,427 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-25 08:52:59,428 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-25 08:52:59,428 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-25 08:52:59,429 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2019-11-25 08:52:59,452 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-25 08:52:59,452 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-25 08:52:59,453 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-25 08:52:59,453 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-25 08:52:59,453 INFO L138 SettingsManager]: * Use SBE=true [2019-11-25 08:52:59,454 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2019-11-25 08:52:59,454 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2019-11-25 08:52:59,454 INFO L138 SettingsManager]: * Use old map elimination=false [2019-11-25 08:52:59,454 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2019-11-25 08:52:59,454 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2019-11-25 08:52:59,455 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2019-11-25 08:52:59,455 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-25 08:52:59,455 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-25 08:52:59,455 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2019-11-25 08:52:59,455 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-25 08:52:59,455 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-25 08:52:59,456 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-25 08:52:59,456 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2019-11-25 08:52:59,456 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2019-11-25 08:52:59,456 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2019-11-25 08:52:59,456 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-25 08:52:59,456 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-25 08:52:59,457 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2019-11-25 08:52:59,457 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-25 08:52:59,457 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2019-11-25 08:52:59,457 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-25 08:52:59,457 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-25 08:52:59,458 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2019-11-25 08:52:59,458 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-25 08:52:59,458 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-25 08:52:59,458 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2019-11-25 08:52:59,459 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2019-11-25 08:52:59,459 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bcbeb24241e70d50816527d1472e428919d63db5 [2019-11-25 08:52:59,588 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-25 08:52:59,598 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-25 08:52:59,601 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-25 08:52:59,602 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-25 08:52:59,603 INFO L275 PluginConnector]: CDTParser initialized [2019-11-25 08:52:59,603 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/../../sv-benchmarks/c/systemc/transmitter.04.cil.c [2019-11-25 08:52:59,661 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/data/9c0e083f2/3000c57ce18b416481856dcc99a462eb/FLAG87a6e674b [2019-11-25 08:53:00,084 INFO L306 CDTParser]: Found 1 translation units. [2019-11-25 08:53:00,087 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/sv-benchmarks/c/systemc/transmitter.04.cil.c [2019-11-25 08:53:00,104 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/data/9c0e083f2/3000c57ce18b416481856dcc99a462eb/FLAG87a6e674b [2019-11-25 08:53:00,113 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/data/9c0e083f2/3000c57ce18b416481856dcc99a462eb [2019-11-25 08:53:00,115 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-25 08:53:00,116 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-25 08:53:00,117 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-25 08:53:00,117 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-25 08:53:00,120 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-25 08:53:00,121 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 25.11 08:53:00" (1/1) ... [2019-11-25 08:53:00,123 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@58a06667 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:53:00, skipping insertion in model container [2019-11-25 08:53:00,123 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 25.11 08:53:00" (1/1) ... [2019-11-25 08:53:00,129 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-11-25 08:53:00,159 INFO L179 MainTranslator]: Built tables and reachable declarations [2019-11-25 08:53:00,432 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-25 08:53:00,437 INFO L201 MainTranslator]: Completed pre-run [2019-11-25 08:53:00,498 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-25 08:53:00,517 INFO L205 MainTranslator]: Completed translation [2019-11-25 08:53:00,517 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:53:00 WrapperNode [2019-11-25 08:53:00,517 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-25 08:53:00,518 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-25 08:53:00,518 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-25 08:53:00,518 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-25 08:53:00,524 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:53:00" (1/1) ... [2019-11-25 08:53:00,531 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:53:00" (1/1) ... [2019-11-25 08:53:00,573 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-25 08:53:00,574 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-25 08:53:00,574 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-25 08:53:00,574 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-25 08:53:00,583 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:53:00" (1/1) ... [2019-11-25 08:53:00,583 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:53:00" (1/1) ... [2019-11-25 08:53:00,589 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:53:00" (1/1) ... [2019-11-25 08:53:00,589 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:53:00" (1/1) ... [2019-11-25 08:53:00,603 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:53:00" (1/1) ... [2019-11-25 08:53:00,617 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:53:00" (1/1) ... [2019-11-25 08:53:00,621 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:53:00" (1/1) ... [2019-11-25 08:53:00,629 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-25 08:53:00,629 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-25 08:53:00,629 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-25 08:53:00,630 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-25 08:53:00,630 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:53:00" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:00,715 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-25 08:53:00,716 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-25 08:53:01,823 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-25 08:53:01,823 INFO L284 CfgBuilder]: Removed 148 assume(true) statements. [2019-11-25 08:53:01,824 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 08:53:01 BoogieIcfgContainer [2019-11-25 08:53:01,824 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-25 08:53:01,825 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2019-11-25 08:53:01,825 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2019-11-25 08:53:01,828 INFO L275 PluginConnector]: BuchiAutomizer initialized [2019-11-25 08:53:01,829 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-11-25 08:53:01,829 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 25.11 08:53:00" (1/3) ... [2019-11-25 08:53:01,831 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@779eae6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 25.11 08:53:01, skipping insertion in model container [2019-11-25 08:53:01,831 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-11-25 08:53:01,831 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:53:00" (2/3) ... [2019-11-25 08:53:01,832 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@779eae6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 25.11 08:53:01, skipping insertion in model container [2019-11-25 08:53:01,832 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-11-25 08:53:01,832 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 08:53:01" (3/3) ... [2019-11-25 08:53:01,834 INFO L371 chiAutomizerObserver]: Analyzing ICFG transmitter.04.cil.c [2019-11-25 08:53:01,875 INFO L356 BuchiCegarLoop]: Interprodecural is true [2019-11-25 08:53:01,876 INFO L357 BuchiCegarLoop]: Hoare is false [2019-11-25 08:53:01,876 INFO L358 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2019-11-25 08:53:01,878 INFO L359 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-25 08:53:01,878 INFO L360 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-25 08:53:01,878 INFO L361 BuchiCegarLoop]: Difference is false [2019-11-25 08:53:01,878 INFO L362 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-25 08:53:01,879 INFO L365 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2019-11-25 08:53:01,902 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 373 states. [2019-11-25 08:53:01,939 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 308 [2019-11-25 08:53:01,940 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:53:01,940 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:53:01,951 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:01,951 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:01,951 INFO L424 BuchiCegarLoop]: ======== Iteration 1============ [2019-11-25 08:53:01,951 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 373 states. [2019-11-25 08:53:01,969 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 308 [2019-11-25 08:53:01,969 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:53:01,969 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:53:01,973 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:01,973 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:01,980 INFO L794 eck$LassoCheckResult]: Stem: 125#ULTIMATE.startENTRYtrue ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 17#L-1true havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 301#L729true havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 162#L324true assume !(1 == ~m_i~0);~m_st~0 := 2; 256#L331-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 101#L336-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 122#L341-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 165#L346-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 19#L351-1true assume !(0 == ~M_E~0); 357#L492-1true assume !(0 == ~T1_E~0); 214#L497-1true assume !(0 == ~T2_E~0); 243#L502-1true assume !(0 == ~T3_E~0); 259#L507-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 121#L512-1true assume !(0 == ~E_1~0); 134#L517-1true assume !(0 == ~E_2~0); 176#L522-1true assume !(0 == ~E_3~0); 32#L527-1true assume !(0 == ~E_4~0); 51#L532-1true havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 340#L228true assume !(1 == ~m_pc~0); 329#L228-2true is_master_triggered_~__retres1~0 := 0; 299#L239true is_master_triggered_#res := is_master_triggered_~__retres1~0; 58#L240true activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 154#L605true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 157#L605-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 189#L247true assume 1 == ~t1_pc~0; 96#L248true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 190#L258true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 98#L259true activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 373#L613true assume !(0 != activate_threads_~tmp___0~0); 346#L613-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 207#L266true assume !(1 == ~t2_pc~0); 358#L266-2true is_transmit2_triggered_~__retres1~2 := 0; 208#L277true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 293#L278true activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 7#L621true assume !(0 != activate_threads_~tmp___1~0); 12#L621-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11#L285true assume 1 == ~t3_pc~0; 118#L286true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 13#L296true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 119#L297true activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 228#L629true assume !(0 != activate_threads_~tmp___2~0); 209#L629-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 240#L304true assume !(1 == ~t4_pc~0); 221#L304-2true is_transmit4_triggered_~__retres1~4 := 0; 239#L315true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 327#L316true activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 44#L637true assume !(0 != activate_threads_~tmp___3~0); 46#L637-2true assume !(1 == ~M_E~0); 117#L545-1true assume !(1 == ~T1_E~0); 159#L550-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 15#L555-1true assume !(1 == ~T3_E~0); 48#L560-1true assume !(1 == ~T4_E~0); 50#L565-1true assume !(1 == ~E_1~0); 260#L570-1true assume !(1 == ~E_2~0); 288#L575-1true assume !(1 == ~E_3~0); 347#L580-1true assume !(1 == ~E_4~0); 244#L766-1true [2019-11-25 08:53:01,982 INFO L796 eck$LassoCheckResult]: Loop: 244#L766-1true assume !false; 205#L767true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 179#L467true assume !true; 267#L482true start_simulation_~kernel_st~0 := 2; 167#L324-1true start_simulation_~kernel_st~0 := 3; 361#L492-2true assume !(0 == ~M_E~0); 320#L492-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 196#L497-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 233#L502-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 247#L507-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 87#L512-3true assume 0 == ~E_1~0;~E_1~0 := 1; 140#L517-3true assume 0 == ~E_2~0;~E_2~0 := 1; 186#L522-3true assume 0 == ~E_3~0;~E_3~0 := 1; 38#L527-3true assume !(0 == ~E_4~0); 53#L532-3true havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 289#L228-15true assume 1 == ~m_pc~0; 64#L229-5true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 319#L239-5true is_master_triggered_#res := is_master_triggered_~__retres1~0; 66#L240-5true activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 103#L605-15true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 111#L605-17true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 114#L247-15true assume !(1 == ~t1_pc~0); 108#L247-17true is_transmit1_triggered_~__retres1~1 := 0; 146#L258-5true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 255#L259-5true activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 314#L613-15true assume !(0 != activate_threads_~tmp___0~0); 286#L613-17true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 305#L266-15true assume !(1 == ~t2_pc~0); 338#L266-17true is_transmit2_triggered_~__retres1~2 := 0; 348#L277-5true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 268#L278-5true activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 152#L621-15true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 156#L621-17true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 193#L285-15true assume 1 == ~t3_pc~0; 131#L286-5true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 28#L296-5true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 133#L297-5true activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 372#L629-15true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 342#L629-17true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 202#L304-15true assume 1 == ~t4_pc~0; 312#L305-5true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 225#L315-5true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 310#L316-5true activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5#L637-15true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 10#L637-17true assume 1 == ~M_E~0;~M_E~0 := 2; 84#L545-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 137#L550-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 183#L555-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 34#L560-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 52#L565-3true assume 1 == ~E_1~0;~E_1~0 := 2; 269#L570-3true assume !(1 == ~E_2~0); 295#L575-3true assume 1 == ~E_3~0;~E_3~0 := 2; 354#L580-3true assume 1 == ~E_4~0;~E_4~0 := 2; 213#L585-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 252#L364-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 95#L391-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 237#L392-1true start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 71#L785true assume !(0 == start_simulation_~tmp~3); 75#L785-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 257#L364-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 99#L391-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 238#L392-2true stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 300#L740true assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 49#L747true stop_simulation_#res := stop_simulation_~__retres2~0; 170#L748true start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 124#L798true assume !(0 != start_simulation_~tmp___0~1); 244#L766-1true [2019-11-25 08:53:01,988 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:01,988 INFO L82 PathProgramCache]: Analyzing trace with hash 1688618289, now seen corresponding path program 1 times [2019-11-25 08:53:01,994 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:01,994 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [689034727] [2019-11-25 08:53:01,994 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:02,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:02,133 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:02,134 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [689034727] [2019-11-25 08:53:02,135 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:02,135 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:53:02,136 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [309024037] [2019-11-25 08:53:02,142 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:53:02,142 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:02,142 INFO L82 PathProgramCache]: Analyzing trace with hash -1580088769, now seen corresponding path program 1 times [2019-11-25 08:53:02,143 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:02,143 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [578386760] [2019-11-25 08:53:02,143 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:02,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:02,196 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:02,196 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [578386760] [2019-11-25 08:53:02,196 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:02,197 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:53:02,197 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2004399051] [2019-11-25 08:53:02,198 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:53:02,205 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:53:02,218 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:53:02,220 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:53:02,221 INFO L87 Difference]: Start difference. First operand 373 states. Second operand 3 states. [2019-11-25 08:53:02,270 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:53:02,274 INFO L93 Difference]: Finished difference Result 373 states and 564 transitions. [2019-11-25 08:53:02,274 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:53:02,276 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 373 states and 564 transitions. [2019-11-25 08:53:02,280 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2019-11-25 08:53:02,289 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 373 states to 368 states and 559 transitions. [2019-11-25 08:53:02,290 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 368 [2019-11-25 08:53:02,291 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 368 [2019-11-25 08:53:02,291 INFO L73 IsDeterministic]: Start isDeterministic. Operand 368 states and 559 transitions. [2019-11-25 08:53:02,295 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:53:02,295 INFO L688 BuchiCegarLoop]: Abstraction has 368 states and 559 transitions. [2019-11-25 08:53:02,310 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states and 559 transitions. [2019-11-25 08:53:02,335 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 368. [2019-11-25 08:53:02,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 368 states. [2019-11-25 08:53:02,337 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 559 transitions. [2019-11-25 08:53:02,338 INFO L711 BuchiCegarLoop]: Abstraction has 368 states and 559 transitions. [2019-11-25 08:53:02,339 INFO L591 BuchiCegarLoop]: Abstraction has 368 states and 559 transitions. [2019-11-25 08:53:02,339 INFO L424 BuchiCegarLoop]: ======== Iteration 2============ [2019-11-25 08:53:02,339 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 368 states and 559 transitions. [2019-11-25 08:53:02,341 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2019-11-25 08:53:02,342 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:53:02,342 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:53:02,344 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:02,344 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:02,345 INFO L794 eck$LassoCheckResult]: Stem: 961#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 782#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 783#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 996#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 997#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 932#L336-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 933#L341-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 958#L346-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 785#L351-1 assume !(0 == ~M_E~0); 786#L492-1 assume !(0 == ~T1_E~0); 1039#L497-1 assume !(0 == ~T2_E~0); 1040#L502-1 assume !(0 == ~T3_E~0); 1064#L507-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 955#L512-1 assume !(0 == ~E_1~0); 956#L517-1 assume !(0 == ~E_2~0); 972#L522-1 assume !(0 == ~E_3~0); 803#L527-1 assume !(0 == ~E_4~0); 804#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 838#L228 assume !(1 == ~m_pc~0); 847#L228-2 is_master_triggered_~__retres1~0 := 0; 846#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 848#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 849#L605 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 990#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 993#L247 assume 1 == ~t1_pc~0; 925#L248 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 926#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 928#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 929#L613 assume !(0 != activate_threads_~tmp___0~0); 1118#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1024#L266 assume !(1 == ~t2_pc~0); 1025#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 1027#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1028#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 766#L621 assume !(0 != activate_threads_~tmp___1~0); 767#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 771#L285 assume 1 == ~t3_pc~0; 772#L286 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 763#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 775#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 954#L629 assume !(0 != activate_threads_~tmp___2~0); 1029#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1030#L304 assume !(1 == ~t4_pc~0); 1045#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 1046#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1061#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 830#L637 assume !(0 != activate_threads_~tmp___3~0); 831#L637-2 assume !(1 == ~M_E~0); 832#L545-1 assume !(1 == ~T1_E~0); 951#L550-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 778#L555-1 assume !(1 == ~T3_E~0); 779#L560-1 assume !(1 == ~T4_E~0); 834#L565-1 assume !(1 == ~E_1~0); 837#L570-1 assume !(1 == ~E_2~0); 1069#L575-1 assume !(1 == ~E_3~0); 1101#L580-1 assume !(1 == ~E_4~0); 960#L766-1 [2019-11-25 08:53:02,345 INFO L796 eck$LassoCheckResult]: Loop: 960#L766-1 assume !false; 1023#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 844#L467 assume !false; 914#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 915#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 855#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 916#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 820#L406 assume !(0 != eval_~tmp~0); 822#L482 start_simulation_~kernel_st~0 := 2; 999#L324-1 start_simulation_~kernel_st~0 := 3; 1000#L492-2 assume !(0 == ~M_E~0); 1110#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1012#L497-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1013#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1059#L507-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 910#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 911#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 978#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 814#L527-3 assume !(0 == ~E_4~0); 815#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 840#L228-15 assume 1 == ~m_pc~0; 860#L229-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 861#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 866#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 867#L605-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 936#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 947#L247-15 assume 1 == ~t1_pc~0; 949#L248-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 943#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 984#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1067#L613-15 assume !(0 != activate_threads_~tmp___0~0); 1095#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1096#L266-15 assume 1 == ~t2_pc~0; 1074#L267-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1075#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1078#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 987#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 988#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 991#L285-15 assume 1 == ~t3_pc~0; 968#L286-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 796#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 797#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 971#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1116#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1018#L304-15 assume 1 == ~t4_pc~0; 1019#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1022#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1051#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 760#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 761#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 770#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 903#L550-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 975#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 807#L560-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 808#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 839#L570-3 assume !(1 == ~E_2~0); 1079#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1103#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1036#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1037#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 864#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 923#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 876#L785 assume !(0 == start_simulation_~tmp~3); 877#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 884#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 872#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 930#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 1060#L740 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 835#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 836#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 959#L798 assume !(0 != start_simulation_~tmp___0~1); 960#L766-1 [2019-11-25 08:53:02,345 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:02,346 INFO L82 PathProgramCache]: Analyzing trace with hash 1244717615, now seen corresponding path program 1 times [2019-11-25 08:53:02,346 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:02,346 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1392300973] [2019-11-25 08:53:02,346 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:02,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:02,381 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:02,381 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1392300973] [2019-11-25 08:53:02,382 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:02,382 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:53:02,382 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2102163864] [2019-11-25 08:53:02,383 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:53:02,383 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:02,383 INFO L82 PathProgramCache]: Analyzing trace with hash 554242591, now seen corresponding path program 1 times [2019-11-25 08:53:02,383 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:02,383 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1827343219] [2019-11-25 08:53:02,384 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:02,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:02,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:02,455 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1827343219] [2019-11-25 08:53:02,455 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:02,456 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:53:02,456 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1269578680] [2019-11-25 08:53:02,456 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:53:02,457 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:53:02,457 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:53:02,457 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:53:02,457 INFO L87 Difference]: Start difference. First operand 368 states and 559 transitions. cyclomatic complexity: 192 Second operand 3 states. [2019-11-25 08:53:02,476 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:53:02,476 INFO L93 Difference]: Finished difference Result 368 states and 558 transitions. [2019-11-25 08:53:02,477 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:53:02,477 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 368 states and 558 transitions. [2019-11-25 08:53:02,481 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2019-11-25 08:53:02,485 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 368 states to 368 states and 558 transitions. [2019-11-25 08:53:02,485 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 368 [2019-11-25 08:53:02,486 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 368 [2019-11-25 08:53:02,486 INFO L73 IsDeterministic]: Start isDeterministic. Operand 368 states and 558 transitions. [2019-11-25 08:53:02,488 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:53:02,488 INFO L688 BuchiCegarLoop]: Abstraction has 368 states and 558 transitions. [2019-11-25 08:53:02,492 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states and 558 transitions. [2019-11-25 08:53:02,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 368. [2019-11-25 08:53:02,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 368 states. [2019-11-25 08:53:02,518 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 558 transitions. [2019-11-25 08:53:02,519 INFO L711 BuchiCegarLoop]: Abstraction has 368 states and 558 transitions. [2019-11-25 08:53:02,519 INFO L591 BuchiCegarLoop]: Abstraction has 368 states and 558 transitions. [2019-11-25 08:53:02,519 INFO L424 BuchiCegarLoop]: ======== Iteration 3============ [2019-11-25 08:53:02,519 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 368 states and 558 transitions. [2019-11-25 08:53:02,523 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2019-11-25 08:53:02,523 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:53:02,523 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:53:02,526 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:02,526 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:02,528 INFO L794 eck$LassoCheckResult]: Stem: 1704#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 1523#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1524#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1737#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 1738#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1675#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1676#L341-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1700#L346-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1527#L351-1 assume !(0 == ~M_E~0); 1528#L492-1 assume !(0 == ~T1_E~0); 1781#L497-1 assume !(0 == ~T2_E~0); 1782#L502-1 assume !(0 == ~T3_E~0); 1807#L507-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1698#L512-1 assume !(0 == ~E_1~0); 1699#L517-1 assume !(0 == ~E_2~0); 1715#L522-1 assume !(0 == ~E_3~0); 1546#L527-1 assume !(0 == ~E_4~0); 1547#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1581#L228 assume !(1 == ~m_pc~0); 1590#L228-2 is_master_triggered_~__retres1~0 := 0; 1589#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1591#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1592#L605 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1733#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1735#L247 assume 1 == ~t1_pc~0; 1667#L248 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1668#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1671#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1672#L613 assume !(0 != activate_threads_~tmp___0~0); 1860#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1767#L266 assume !(1 == ~t2_pc~0); 1768#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 1770#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1771#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1507#L621 assume !(0 != activate_threads_~tmp___1~0); 1508#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1514#L285 assume 1 == ~t3_pc~0; 1515#L286 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1506#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1516#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1695#L629 assume !(0 != activate_threads_~tmp___2~0); 1772#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1773#L304 assume !(1 == ~t4_pc~0); 1788#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 1789#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1804#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1571#L637 assume !(0 != activate_threads_~tmp___3~0); 1572#L637-2 assume !(1 == ~M_E~0); 1575#L545-1 assume !(1 == ~T1_E~0); 1694#L550-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1519#L555-1 assume !(1 == ~T3_E~0); 1520#L560-1 assume !(1 == ~T4_E~0); 1577#L565-1 assume !(1 == ~E_1~0); 1580#L570-1 assume !(1 == ~E_2~0); 1812#L575-1 assume !(1 == ~E_3~0); 1843#L580-1 assume !(1 == ~E_4~0); 1703#L766-1 [2019-11-25 08:53:02,530 INFO L796 eck$LassoCheckResult]: Loop: 1703#L766-1 assume !false; 1765#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 1587#L467 assume !false; 1655#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1656#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1595#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1659#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1563#L406 assume !(0 != eval_~tmp~0); 1565#L482 start_simulation_~kernel_st~0 := 2; 1742#L324-1 start_simulation_~kernel_st~0 := 3; 1743#L492-2 assume !(0 == ~M_E~0); 1853#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1755#L497-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1756#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1802#L507-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1650#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1651#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1723#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1561#L527-3 assume !(0 == ~E_4~0); 1562#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1583#L228-15 assume 1 == ~m_pc~0; 1603#L229-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1604#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1609#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1610#L605-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1679#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1690#L247-15 assume !(1 == ~t1_pc~0); 1687#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 1688#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1729#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1811#L613-15 assume !(0 != activate_threads_~tmp___0~0); 1838#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1839#L266-15 assume 1 == ~t2_pc~0; 1818#L267-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1819#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1821#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1730#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1731#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1734#L285-15 assume !(1 == ~t3_pc~0); 1712#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 1539#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1540#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1714#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1859#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1761#L304-15 assume 1 == ~t4_pc~0; 1762#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1766#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1794#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1503#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1504#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 1513#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1646#L550-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1718#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1550#L560-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1551#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1582#L570-3 assume !(1 == ~E_2~0); 1822#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1846#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1779#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1780#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1607#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1666#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 1622#L785 assume !(0 == start_simulation_~tmp~3); 1623#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1631#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1615#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1673#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 1803#L740 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 1578#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 1579#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 1702#L798 assume !(0 != start_simulation_~tmp___0~1); 1703#L766-1 [2019-11-25 08:53:02,531 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:02,531 INFO L82 PathProgramCache]: Analyzing trace with hash -1021663571, now seen corresponding path program 1 times [2019-11-25 08:53:02,531 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:02,532 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1291172895] [2019-11-25 08:53:02,532 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:02,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:02,585 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:02,585 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1291172895] [2019-11-25 08:53:02,585 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:02,585 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:53:02,586 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [198696200] [2019-11-25 08:53:02,586 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:53:02,586 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:02,587 INFO L82 PathProgramCache]: Analyzing trace with hash -1895792863, now seen corresponding path program 1 times [2019-11-25 08:53:02,587 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:02,587 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1792212775] [2019-11-25 08:53:02,587 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:02,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:02,638 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:02,638 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1792212775] [2019-11-25 08:53:02,639 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:02,639 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:53:02,639 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [492086963] [2019-11-25 08:53:02,640 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:53:02,640 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:53:02,640 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:53:02,640 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:53:02,640 INFO L87 Difference]: Start difference. First operand 368 states and 558 transitions. cyclomatic complexity: 191 Second operand 3 states. [2019-11-25 08:53:02,650 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:53:02,650 INFO L93 Difference]: Finished difference Result 368 states and 557 transitions. [2019-11-25 08:53:02,650 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:53:02,651 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 368 states and 557 transitions. [2019-11-25 08:53:02,654 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2019-11-25 08:53:02,657 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 368 states to 368 states and 557 transitions. [2019-11-25 08:53:02,658 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 368 [2019-11-25 08:53:02,658 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 368 [2019-11-25 08:53:02,658 INFO L73 IsDeterministic]: Start isDeterministic. Operand 368 states and 557 transitions. [2019-11-25 08:53:02,659 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:53:02,659 INFO L688 BuchiCegarLoop]: Abstraction has 368 states and 557 transitions. [2019-11-25 08:53:02,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states and 557 transitions. [2019-11-25 08:53:02,670 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 368. [2019-11-25 08:53:02,671 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 368 states. [2019-11-25 08:53:02,672 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 557 transitions. [2019-11-25 08:53:02,673 INFO L711 BuchiCegarLoop]: Abstraction has 368 states and 557 transitions. [2019-11-25 08:53:02,673 INFO L591 BuchiCegarLoop]: Abstraction has 368 states and 557 transitions. [2019-11-25 08:53:02,673 INFO L424 BuchiCegarLoop]: ======== Iteration 4============ [2019-11-25 08:53:02,673 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 368 states and 557 transitions. [2019-11-25 08:53:02,675 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2019-11-25 08:53:02,676 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:53:02,676 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:53:02,677 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:02,677 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:02,678 INFO L794 eck$LassoCheckResult]: Stem: 2447#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 2268#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2269#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2482#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 2483#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2418#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2419#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2443#L346-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2271#L351-1 assume !(0 == ~M_E~0); 2272#L492-1 assume !(0 == ~T1_E~0); 2525#L497-1 assume !(0 == ~T2_E~0); 2526#L502-1 assume !(0 == ~T3_E~0); 2550#L507-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2441#L512-1 assume !(0 == ~E_1~0); 2442#L517-1 assume !(0 == ~E_2~0); 2458#L522-1 assume !(0 == ~E_3~0); 2289#L527-1 assume !(0 == ~E_4~0); 2290#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2324#L228 assume !(1 == ~m_pc~0); 2333#L228-2 is_master_triggered_~__retres1~0 := 0; 2332#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2334#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2335#L605 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2476#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2479#L247 assume 1 == ~t1_pc~0; 2411#L248 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2412#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2414#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2415#L613 assume !(0 != activate_threads_~tmp___0~0); 2604#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2510#L266 assume !(1 == ~t2_pc~0); 2511#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 2513#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2514#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2252#L621 assume !(0 != activate_threads_~tmp___1~0); 2253#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2257#L285 assume 1 == ~t3_pc~0; 2258#L286 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2249#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2261#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2438#L629 assume !(0 != activate_threads_~tmp___2~0); 2515#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2516#L304 assume !(1 == ~t4_pc~0); 2531#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 2532#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2547#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2316#L637 assume !(0 != activate_threads_~tmp___3~0); 2317#L637-2 assume !(1 == ~M_E~0); 2318#L545-1 assume !(1 == ~T1_E~0); 2437#L550-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2264#L555-1 assume !(1 == ~T3_E~0); 2265#L560-1 assume !(1 == ~T4_E~0); 2320#L565-1 assume !(1 == ~E_1~0); 2323#L570-1 assume !(1 == ~E_2~0); 2555#L575-1 assume !(1 == ~E_3~0); 2587#L580-1 assume !(1 == ~E_4~0); 2446#L766-1 [2019-11-25 08:53:02,678 INFO L796 eck$LassoCheckResult]: Loop: 2446#L766-1 assume !false; 2509#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 2330#L467 assume !false; 2398#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2399#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2341#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2402#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2306#L406 assume !(0 != eval_~tmp~0); 2308#L482 start_simulation_~kernel_st~0 := 2; 2485#L324-1 start_simulation_~kernel_st~0 := 3; 2486#L492-2 assume !(0 == ~M_E~0); 2596#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2498#L497-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2499#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2545#L507-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2393#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2394#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2466#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2304#L527-3 assume !(0 == ~E_4~0); 2305#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2326#L228-15 assume 1 == ~m_pc~0; 2349#L229-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2350#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2352#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2353#L605-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2422#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2433#L247-15 assume 1 == ~t1_pc~0; 2435#L248-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2429#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2470#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2553#L613-15 assume !(0 != activate_threads_~tmp___0~0); 2581#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2582#L266-15 assume 1 == ~t2_pc~0; 2560#L267-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2561#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2564#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2473#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2474#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2477#L285-15 assume 1 == ~t3_pc~0; 2454#L286-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2282#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2283#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2456#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2602#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2504#L304-15 assume 1 == ~t4_pc~0; 2505#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2508#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2537#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2246#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2247#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 2256#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2386#L550-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2461#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2293#L560-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2294#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2325#L570-3 assume !(1 == ~E_2~0); 2565#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2589#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2522#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2523#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2347#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2409#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 2362#L785 assume !(0 == start_simulation_~tmp~3); 2363#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2370#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2355#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2416#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 2546#L740 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 2321#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 2322#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 2445#L798 assume !(0 != start_simulation_~tmp___0~1); 2446#L766-1 [2019-11-25 08:53:02,678 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:02,679 INFO L82 PathProgramCache]: Analyzing trace with hash -540583313, now seen corresponding path program 1 times [2019-11-25 08:53:02,679 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:02,679 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1960397804] [2019-11-25 08:53:02,679 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:02,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:02,719 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:02,719 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1960397804] [2019-11-25 08:53:02,720 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:02,720 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:53:02,720 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2136514463] [2019-11-25 08:53:02,720 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:53:02,721 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:02,721 INFO L82 PathProgramCache]: Analyzing trace with hash 554242591, now seen corresponding path program 2 times [2019-11-25 08:53:02,721 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:02,721 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1298441367] [2019-11-25 08:53:02,722 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:02,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:02,764 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:02,765 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1298441367] [2019-11-25 08:53:02,765 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:02,765 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:53:02,766 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [181941706] [2019-11-25 08:53:02,766 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:53:02,766 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:53:02,767 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:53:02,767 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:53:02,767 INFO L87 Difference]: Start difference. First operand 368 states and 557 transitions. cyclomatic complexity: 190 Second operand 3 states. [2019-11-25 08:53:02,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:53:02,782 INFO L93 Difference]: Finished difference Result 368 states and 556 transitions. [2019-11-25 08:53:02,782 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:53:02,782 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 368 states and 556 transitions. [2019-11-25 08:53:02,786 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2019-11-25 08:53:02,789 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 368 states to 368 states and 556 transitions. [2019-11-25 08:53:02,789 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 368 [2019-11-25 08:53:02,790 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 368 [2019-11-25 08:53:02,790 INFO L73 IsDeterministic]: Start isDeterministic. Operand 368 states and 556 transitions. [2019-11-25 08:53:02,791 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:53:02,791 INFO L688 BuchiCegarLoop]: Abstraction has 368 states and 556 transitions. [2019-11-25 08:53:02,792 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states and 556 transitions. [2019-11-25 08:53:02,798 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 368. [2019-11-25 08:53:02,798 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 368 states. [2019-11-25 08:53:02,800 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 556 transitions. [2019-11-25 08:53:02,800 INFO L711 BuchiCegarLoop]: Abstraction has 368 states and 556 transitions. [2019-11-25 08:53:02,800 INFO L591 BuchiCegarLoop]: Abstraction has 368 states and 556 transitions. [2019-11-25 08:53:02,800 INFO L424 BuchiCegarLoop]: ======== Iteration 5============ [2019-11-25 08:53:02,801 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 368 states and 556 transitions. [2019-11-25 08:53:02,803 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2019-11-25 08:53:02,803 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:53:02,803 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:53:02,805 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:02,805 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:02,805 INFO L794 eck$LassoCheckResult]: Stem: 3190#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 3009#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3010#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3223#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 3224#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3161#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3162#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3186#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3013#L351-1 assume !(0 == ~M_E~0); 3014#L492-1 assume !(0 == ~T1_E~0); 3267#L497-1 assume !(0 == ~T2_E~0); 3268#L502-1 assume !(0 == ~T3_E~0); 3293#L507-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3184#L512-1 assume !(0 == ~E_1~0); 3185#L517-1 assume !(0 == ~E_2~0); 3201#L522-1 assume !(0 == ~E_3~0); 3032#L527-1 assume !(0 == ~E_4~0); 3033#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3067#L228 assume !(1 == ~m_pc~0); 3076#L228-2 is_master_triggered_~__retres1~0 := 0; 3075#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3077#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3078#L605 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3219#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3221#L247 assume 1 == ~t1_pc~0; 3153#L248 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3154#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3157#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3158#L613 assume !(0 != activate_threads_~tmp___0~0); 3346#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3253#L266 assume !(1 == ~t2_pc~0); 3254#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 3256#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3257#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2993#L621 assume !(0 != activate_threads_~tmp___1~0); 2994#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3000#L285 assume 1 == ~t3_pc~0; 3001#L286 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2992#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3002#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3181#L629 assume !(0 != activate_threads_~tmp___2~0); 3258#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3259#L304 assume !(1 == ~t4_pc~0); 3274#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 3275#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3290#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3057#L637 assume !(0 != activate_threads_~tmp___3~0); 3058#L637-2 assume !(1 == ~M_E~0); 3061#L545-1 assume !(1 == ~T1_E~0); 3180#L550-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3005#L555-1 assume !(1 == ~T3_E~0); 3006#L560-1 assume !(1 == ~T4_E~0); 3063#L565-1 assume !(1 == ~E_1~0); 3066#L570-1 assume !(1 == ~E_2~0); 3298#L575-1 assume !(1 == ~E_3~0); 3329#L580-1 assume !(1 == ~E_4~0); 3189#L766-1 [2019-11-25 08:53:02,806 INFO L796 eck$LassoCheckResult]: Loop: 3189#L766-1 assume !false; 3251#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 3073#L467 assume !false; 3141#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3142#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3081#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3145#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 3049#L406 assume !(0 != eval_~tmp~0); 3051#L482 start_simulation_~kernel_st~0 := 2; 3228#L324-1 start_simulation_~kernel_st~0 := 3; 3229#L492-2 assume !(0 == ~M_E~0); 3339#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3241#L497-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3242#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3288#L507-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3136#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3137#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3209#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3047#L527-3 assume !(0 == ~E_4~0); 3048#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3069#L228-15 assume 1 == ~m_pc~0; 3089#L229-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 3090#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3095#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3096#L605-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3165#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3176#L247-15 assume !(1 == ~t1_pc~0); 3173#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 3174#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3215#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3297#L613-15 assume !(0 != activate_threads_~tmp___0~0); 3324#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3325#L266-15 assume 1 == ~t2_pc~0; 3304#L267-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3305#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3307#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3216#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3217#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3220#L285-15 assume 1 == ~t3_pc~0; 3197#L286-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3025#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3026#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3200#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3345#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3247#L304-15 assume 1 == ~t4_pc~0; 3248#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3252#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3280#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2989#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2990#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 2999#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3132#L550-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3204#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3036#L560-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3037#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3068#L570-3 assume !(1 == ~E_2~0); 3308#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3332#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3265#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3266#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3093#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3152#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 3108#L785 assume !(0 == start_simulation_~tmp~3); 3109#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3117#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3101#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3159#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 3289#L740 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 3064#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 3065#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 3188#L798 assume !(0 != start_simulation_~tmp___0~1); 3189#L766-1 [2019-11-25 08:53:02,806 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:02,806 INFO L82 PathProgramCache]: Analyzing trace with hash -525064595, now seen corresponding path program 1 times [2019-11-25 08:53:02,806 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:02,807 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1424551194] [2019-11-25 08:53:02,807 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:02,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:02,835 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:02,836 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1424551194] [2019-11-25 08:53:02,836 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:02,836 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:53:02,837 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [548349933] [2019-11-25 08:53:02,837 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:53:02,837 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:02,837 INFO L82 PathProgramCache]: Analyzing trace with hash -319235104, now seen corresponding path program 1 times [2019-11-25 08:53:02,838 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:02,838 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [302788794] [2019-11-25 08:53:02,838 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:02,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:02,876 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:02,876 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [302788794] [2019-11-25 08:53:02,876 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:02,877 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:53:02,877 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1386897736] [2019-11-25 08:53:02,877 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:53:02,877 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:53:02,878 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:53:02,878 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:53:02,878 INFO L87 Difference]: Start difference. First operand 368 states and 556 transitions. cyclomatic complexity: 189 Second operand 3 states. [2019-11-25 08:53:02,896 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:53:02,897 INFO L93 Difference]: Finished difference Result 368 states and 551 transitions. [2019-11-25 08:53:02,897 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:53:02,897 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 368 states and 551 transitions. [2019-11-25 08:53:02,901 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2019-11-25 08:53:02,904 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 368 states to 368 states and 551 transitions. [2019-11-25 08:53:02,904 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 368 [2019-11-25 08:53:02,905 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 368 [2019-11-25 08:53:02,905 INFO L73 IsDeterministic]: Start isDeterministic. Operand 368 states and 551 transitions. [2019-11-25 08:53:02,905 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:53:02,906 INFO L688 BuchiCegarLoop]: Abstraction has 368 states and 551 transitions. [2019-11-25 08:53:02,906 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states and 551 transitions. [2019-11-25 08:53:02,911 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 368. [2019-11-25 08:53:02,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 368 states. [2019-11-25 08:53:02,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 551 transitions. [2019-11-25 08:53:02,913 INFO L711 BuchiCegarLoop]: Abstraction has 368 states and 551 transitions. [2019-11-25 08:53:02,913 INFO L591 BuchiCegarLoop]: Abstraction has 368 states and 551 transitions. [2019-11-25 08:53:02,913 INFO L424 BuchiCegarLoop]: ======== Iteration 6============ [2019-11-25 08:53:02,913 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 368 states and 551 transitions. [2019-11-25 08:53:02,915 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2019-11-25 08:53:02,915 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:53:02,916 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:53:02,917 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:02,917 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:02,917 INFO L794 eck$LassoCheckResult]: Stem: 3933#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 3754#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3755#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3966#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 3967#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3904#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3905#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3929#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3757#L351-1 assume !(0 == ~M_E~0); 3758#L492-1 assume !(0 == ~T1_E~0); 4011#L497-1 assume !(0 == ~T2_E~0); 4012#L502-1 assume !(0 == ~T3_E~0); 4036#L507-1 assume !(0 == ~T4_E~0); 3927#L512-1 assume !(0 == ~E_1~0); 3928#L517-1 assume !(0 == ~E_2~0); 3944#L522-1 assume !(0 == ~E_3~0); 3775#L527-1 assume !(0 == ~E_4~0); 3776#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3810#L228 assume !(1 == ~m_pc~0); 3819#L228-2 is_master_triggered_~__retres1~0 := 0; 3818#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3820#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3821#L605 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3962#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3965#L247 assume 1 == ~t1_pc~0; 3897#L248 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3898#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3900#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3901#L613 assume !(0 != activate_threads_~tmp___0~0); 4090#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3996#L266 assume !(1 == ~t2_pc~0); 3997#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 3999#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4000#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3738#L621 assume !(0 != activate_threads_~tmp___1~0); 3739#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3743#L285 assume 1 == ~t3_pc~0; 3744#L286 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3735#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3747#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3924#L629 assume !(0 != activate_threads_~tmp___2~0); 4001#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4002#L304 assume !(1 == ~t4_pc~0); 4017#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 4018#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4033#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3802#L637 assume !(0 != activate_threads_~tmp___3~0); 3803#L637-2 assume !(1 == ~M_E~0); 3804#L545-1 assume !(1 == ~T1_E~0); 3923#L550-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3748#L555-1 assume !(1 == ~T3_E~0); 3749#L560-1 assume !(1 == ~T4_E~0); 3806#L565-1 assume !(1 == ~E_1~0); 3809#L570-1 assume !(1 == ~E_2~0); 4041#L575-1 assume !(1 == ~E_3~0); 4072#L580-1 assume !(1 == ~E_4~0); 3932#L766-1 [2019-11-25 08:53:02,917 INFO L796 eck$LassoCheckResult]: Loop: 3932#L766-1 assume !false; 3995#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 3816#L467 assume !false; 3884#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3885#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3827#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3888#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 3792#L406 assume !(0 != eval_~tmp~0); 3794#L482 start_simulation_~kernel_st~0 := 2; 3971#L324-1 start_simulation_~kernel_st~0 := 3; 3972#L492-2 assume !(0 == ~M_E~0); 4082#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3984#L497-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3985#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4031#L507-3 assume !(0 == ~T4_E~0); 3879#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3880#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3952#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3790#L527-3 assume !(0 == ~E_4~0); 3791#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3812#L228-15 assume 1 == ~m_pc~0; 3835#L229-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 3836#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3838#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3839#L605-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3911#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3920#L247-15 assume 1 == ~t1_pc~0; 3922#L248-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3918#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3958#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4040#L613-15 assume !(0 != activate_threads_~tmp___0~0); 4067#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4068#L266-15 assume !(1 == ~t2_pc~0); 4048#L266-17 is_transmit2_triggered_~__retres1~2 := 0; 4047#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4050#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3959#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3960#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3963#L285-15 assume 1 == ~t3_pc~0; 3940#L286-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3768#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3769#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3942#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4088#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3990#L304-15 assume 1 == ~t4_pc~0; 3991#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3994#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4023#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3732#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3733#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 3740#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3872#L550-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3947#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3779#L560-3 assume !(1 == ~T4_E~0); 3780#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3811#L570-3 assume !(1 == ~E_2~0); 4051#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4075#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4008#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4009#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3833#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3895#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 3848#L785 assume !(0 == start_simulation_~tmp~3); 3849#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3856#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3841#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3902#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 4032#L740 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 3807#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 3808#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 3931#L798 assume !(0 != start_simulation_~tmp___0~1); 3932#L766-1 [2019-11-25 08:53:02,918 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:02,918 INFO L82 PathProgramCache]: Analyzing trace with hash 1720514859, now seen corresponding path program 1 times [2019-11-25 08:53:02,918 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:02,918 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1294724900] [2019-11-25 08:53:02,918 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:02,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:02,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:02,944 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1294724900] [2019-11-25 08:53:02,944 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:02,944 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:53:02,944 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [206344675] [2019-11-25 08:53:02,945 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:53:02,945 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:02,945 INFO L82 PathProgramCache]: Analyzing trace with hash -1135913248, now seen corresponding path program 1 times [2019-11-25 08:53:02,945 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:02,945 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [836639322] [2019-11-25 08:53:02,945 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:02,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:02,997 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:02,997 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [836639322] [2019-11-25 08:53:02,998 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:02,998 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:53:02,998 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [254673156] [2019-11-25 08:53:02,999 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:53:02,999 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:53:02,999 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:53:03,000 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:53:03,000 INFO L87 Difference]: Start difference. First operand 368 states and 551 transitions. cyclomatic complexity: 184 Second operand 3 states. [2019-11-25 08:53:03,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:53:03,066 INFO L93 Difference]: Finished difference Result 633 states and 939 transitions. [2019-11-25 08:53:03,067 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:53:03,067 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 633 states and 939 transitions. [2019-11-25 08:53:03,072 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 571 [2019-11-25 08:53:03,078 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 633 states to 633 states and 939 transitions. [2019-11-25 08:53:03,078 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 633 [2019-11-25 08:53:03,079 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 633 [2019-11-25 08:53:03,079 INFO L73 IsDeterministic]: Start isDeterministic. Operand 633 states and 939 transitions. [2019-11-25 08:53:03,080 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:53:03,080 INFO L688 BuchiCegarLoop]: Abstraction has 633 states and 939 transitions. [2019-11-25 08:53:03,081 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 633 states and 939 transitions. [2019-11-25 08:53:03,091 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 633 to 631. [2019-11-25 08:53:03,091 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 631 states. [2019-11-25 08:53:03,094 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 631 states to 631 states and 937 transitions. [2019-11-25 08:53:03,094 INFO L711 BuchiCegarLoop]: Abstraction has 631 states and 937 transitions. [2019-11-25 08:53:03,094 INFO L591 BuchiCegarLoop]: Abstraction has 631 states and 937 transitions. [2019-11-25 08:53:03,095 INFO L424 BuchiCegarLoop]: ======== Iteration 7============ [2019-11-25 08:53:03,095 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 631 states and 937 transitions. [2019-11-25 08:53:03,098 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 569 [2019-11-25 08:53:03,099 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:53:03,099 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:53:03,100 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:03,100 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:03,100 INFO L794 eck$LassoCheckResult]: Stem: 4938#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 4760#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4761#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4972#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 4973#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4910#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4911#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4934#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4764#L351-1 assume !(0 == ~M_E~0); 4765#L492-1 assume !(0 == ~T1_E~0); 5021#L497-1 assume !(0 == ~T2_E~0); 5022#L502-1 assume !(0 == ~T3_E~0); 5050#L507-1 assume !(0 == ~T4_E~0); 4932#L512-1 assume !(0 == ~E_1~0); 4933#L517-1 assume !(0 == ~E_2~0); 4949#L522-1 assume !(0 == ~E_3~0); 4783#L527-1 assume !(0 == ~E_4~0); 4784#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4819#L228 assume !(1 == ~m_pc~0); 4828#L228-2 is_master_triggered_~__retres1~0 := 0; 4827#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4829#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 4830#L605 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4967#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4969#L247 assume !(1 == ~t1_pc~0); 4983#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 4984#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4906#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4907#L613 assume !(0 != activate_threads_~tmp___0~0); 5114#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5007#L266 assume !(1 == ~t2_pc~0); 5008#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 5010#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5011#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4744#L621 assume !(0 != activate_threads_~tmp___1~0); 4745#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4751#L285 assume 1 == ~t3_pc~0; 4752#L286 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4743#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4753#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4929#L629 assume !(0 != activate_threads_~tmp___2~0); 5012#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5013#L304 assume !(1 == ~t4_pc~0); 5030#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 5031#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5047#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4809#L637 assume !(0 != activate_threads_~tmp___3~0); 4810#L637-2 assume !(1 == ~M_E~0); 4813#L545-1 assume !(1 == ~T1_E~0); 4928#L550-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4756#L555-1 assume !(1 == ~T3_E~0); 4757#L560-1 assume !(1 == ~T4_E~0); 4815#L565-1 assume !(1 == ~E_1~0); 4818#L570-1 assume !(1 == ~E_2~0); 5064#L575-1 assume !(1 == ~E_3~0); 5096#L580-1 assume !(1 == ~E_4~0); 5115#L766-1 [2019-11-25 08:53:03,101 INFO L796 eck$LassoCheckResult]: Loop: 5115#L766-1 assume !false; 5005#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 4825#L467 assume !false; 4893#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4894#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 4833#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4897#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 4800#L406 assume !(0 != eval_~tmp~0); 4802#L482 start_simulation_~kernel_st~0 := 2; 4977#L324-1 start_simulation_~kernel_st~0 := 3; 4978#L492-2 assume !(0 == ~M_E~0); 5107#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4995#L497-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4996#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5044#L507-3 assume !(0 == ~T4_E~0); 4888#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4889#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4957#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4798#L527-3 assume !(0 == ~E_4~0); 4799#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4821#L228-15 assume 1 == ~m_pc~0; 4841#L229-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 4842#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4847#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 4848#L605-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4914#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4924#L247-15 assume !(1 == ~t1_pc~0); 4926#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 5308#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5307#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 5306#L613-15 assume !(0 != activate_threads_~tmp___0~0); 5305#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5304#L266-15 assume 1 == ~t2_pc~0; 5302#L267-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5301#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5300#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5299#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5297#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5295#L285-15 assume !(1 == ~t3_pc~0); 5292#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 5290#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5289#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5286#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5284#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5282#L304-15 assume !(1 == ~t4_pc~0); 5280#L304-17 is_transmit4_triggered_~__retres1~4 := 0; 5277#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5275#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5274#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5273#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 5271#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5269#L550-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5267#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5265#L560-3 assume !(1 == ~T4_E~0); 5263#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5260#L570-3 assume !(1 == ~E_2~0); 5258#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5256#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5254#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5245#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5241#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5239#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 5238#L785 assume !(0 == start_simulation_~tmp~3); 5236#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5233#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5230#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5229#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 5228#L740 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 5227#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 5226#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 5225#L798 assume !(0 != start_simulation_~tmp___0~1); 5115#L766-1 [2019-11-25 08:53:03,101 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:03,101 INFO L82 PathProgramCache]: Analyzing trace with hash -1655477814, now seen corresponding path program 1 times [2019-11-25 08:53:03,101 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:03,102 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1326290138] [2019-11-25 08:53:03,102 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:03,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:03,144 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:03,145 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1326290138] [2019-11-25 08:53:03,145 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:03,145 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:53:03,145 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1628926473] [2019-11-25 08:53:03,146 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:53:03,146 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:03,146 INFO L82 PathProgramCache]: Analyzing trace with hash -6570654, now seen corresponding path program 1 times [2019-11-25 08:53:03,146 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:03,147 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2117381848] [2019-11-25 08:53:03,147 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:03,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:03,175 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:03,176 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2117381848] [2019-11-25 08:53:03,176 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:03,176 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:53:03,177 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [33600824] [2019-11-25 08:53:03,177 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:53:03,177 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:53:03,177 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:53:03,178 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:53:03,178 INFO L87 Difference]: Start difference. First operand 631 states and 937 transitions. cyclomatic complexity: 308 Second operand 3 states. [2019-11-25 08:53:03,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:53:03,243 INFO L93 Difference]: Finished difference Result 1121 states and 1653 transitions. [2019-11-25 08:53:03,244 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:53:03,244 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1121 states and 1653 transitions. [2019-11-25 08:53:03,253 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1054 [2019-11-25 08:53:03,262 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1121 states to 1121 states and 1653 transitions. [2019-11-25 08:53:03,262 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1121 [2019-11-25 08:53:03,264 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1121 [2019-11-25 08:53:03,264 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1121 states and 1653 transitions. [2019-11-25 08:53:03,266 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:53:03,266 INFO L688 BuchiCegarLoop]: Abstraction has 1121 states and 1653 transitions. [2019-11-25 08:53:03,267 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1121 states and 1653 transitions. [2019-11-25 08:53:03,285 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1121 to 1117. [2019-11-25 08:53:03,285 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1117 states. [2019-11-25 08:53:03,290 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1117 states to 1117 states and 1649 transitions. [2019-11-25 08:53:03,290 INFO L711 BuchiCegarLoop]: Abstraction has 1117 states and 1649 transitions. [2019-11-25 08:53:03,290 INFO L591 BuchiCegarLoop]: Abstraction has 1117 states and 1649 transitions. [2019-11-25 08:53:03,290 INFO L424 BuchiCegarLoop]: ======== Iteration 8============ [2019-11-25 08:53:03,291 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1117 states and 1649 transitions. [2019-11-25 08:53:03,296 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1050 [2019-11-25 08:53:03,296 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:53:03,297 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:53:03,298 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:03,298 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:03,298 INFO L794 eck$LassoCheckResult]: Stem: 6700#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 6520#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 6521#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6742#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 6743#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6668#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6669#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6696#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6522#L351-1 assume !(0 == ~M_E~0); 6523#L492-1 assume !(0 == ~T1_E~0); 6793#L497-1 assume !(0 == ~T2_E~0); 6794#L502-1 assume !(0 == ~T3_E~0); 6820#L507-1 assume !(0 == ~T4_E~0); 6694#L512-1 assume !(0 == ~E_1~0); 6695#L517-1 assume !(0 == ~E_2~0); 6712#L522-1 assume !(0 == ~E_3~0); 6540#L527-1 assume !(0 == ~E_4~0); 6541#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6576#L228 assume !(1 == ~m_pc~0); 6586#L228-2 is_master_triggered_~__retres1~0 := 0; 6585#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6587#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 6588#L605 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6735#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6741#L247 assume !(1 == ~t1_pc~0); 6756#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 6757#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6664#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 6665#L613 assume !(0 != activate_threads_~tmp___0~0); 6894#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6779#L266 assume !(1 == ~t2_pc~0); 6780#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 6782#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6783#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6503#L621 assume !(0 != activate_threads_~tmp___1~0); 6504#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6510#L285 assume !(1 == ~t3_pc~0); 6501#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 6502#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6513#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 6691#L629 assume !(0 != activate_threads_~tmp___2~0); 6784#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6785#L304 assume !(1 == ~t4_pc~0); 6800#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 6801#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6817#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6568#L637 assume !(0 != activate_threads_~tmp___3~0); 6569#L637-2 assume !(1 == ~M_E~0); 6570#L545-1 assume !(1 == ~T1_E~0); 6690#L550-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6514#L555-1 assume !(1 == ~T3_E~0); 6515#L560-1 assume !(1 == ~T4_E~0); 6572#L565-1 assume !(1 == ~E_1~0); 6575#L570-1 assume !(1 == ~E_2~0); 6836#L575-1 assume !(1 == ~E_3~0); 6869#L580-1 assume !(1 == ~E_4~0); 6895#L766-1 [2019-11-25 08:53:03,298 INFO L796 eck$LassoCheckResult]: Loop: 6895#L766-1 assume !false; 7349#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 7348#L467 assume !false; 7302#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7026#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7016#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 7014#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 7011#L406 assume !(0 != eval_~tmp~0); 7012#L482 start_simulation_~kernel_st~0 := 2; 7608#L324-1 start_simulation_~kernel_st~0 := 3; 7606#L492-2 assume !(0 == ~M_E~0); 7604#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7603#L497-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7602#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7601#L507-3 assume !(0 == ~T4_E~0); 7600#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7599#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7598#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7597#L527-3 assume !(0 == ~E_4~0); 7521#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7520#L228-15 assume !(1 == ~m_pc~0); 7518#L228-17 is_master_triggered_~__retres1~0 := 0; 7517#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7516#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 7515#L605-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7514#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7513#L247-15 assume !(1 == ~t1_pc~0); 7512#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 7511#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7510#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 7509#L613-15 assume !(0 != activate_threads_~tmp___0~0); 7508#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7507#L266-15 assume 1 == ~t2_pc~0; 7475#L267-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7474#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6847#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6733#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6734#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7339#L285-15 assume !(1 == ~t3_pc~0); 7340#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 7450#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7448#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 6902#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6892#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6773#L304-15 assume 1 == ~t4_pc~0; 6774#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6777#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6806#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6497#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 6498#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 6507#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6639#L550-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6715#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6544#L560-3 assume !(1 == ~T4_E~0); 6545#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6577#L570-3 assume !(1 == ~E_2~0); 6848#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6872#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6791#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 6792#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7403#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 7401#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 7398#L785 assume !(0 == start_simulation_~tmp~3); 7395#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7384#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7380#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 7378#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 7376#L740 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 7375#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 7374#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 7372#L798 assume !(0 != start_simulation_~tmp___0~1); 6895#L766-1 [2019-11-25 08:53:03,299 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:03,299 INFO L82 PathProgramCache]: Analyzing trace with hash -994144023, now seen corresponding path program 1 times [2019-11-25 08:53:03,299 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:03,299 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [3996125] [2019-11-25 08:53:03,300 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:03,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:03,371 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:03,371 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [3996125] [2019-11-25 08:53:03,371 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:03,371 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:53:03,371 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [117823630] [2019-11-25 08:53:03,372 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:53:03,372 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:03,372 INFO L82 PathProgramCache]: Analyzing trace with hash -434894238, now seen corresponding path program 1 times [2019-11-25 08:53:03,372 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:03,373 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [974017256] [2019-11-25 08:53:03,373 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:03,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:03,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:03,400 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [974017256] [2019-11-25 08:53:03,400 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:03,400 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:53:03,401 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [152489864] [2019-11-25 08:53:03,401 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:53:03,401 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:53:03,401 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:53:03,402 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:53:03,402 INFO L87 Difference]: Start difference. First operand 1117 states and 1649 transitions. cyclomatic complexity: 536 Second operand 3 states. [2019-11-25 08:53:03,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:53:03,424 INFO L93 Difference]: Finished difference Result 1117 states and 1635 transitions. [2019-11-25 08:53:03,424 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:53:03,424 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1117 states and 1635 transitions. [2019-11-25 08:53:03,431 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1050 [2019-11-25 08:53:03,440 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1117 states to 1117 states and 1635 transitions. [2019-11-25 08:53:03,441 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1117 [2019-11-25 08:53:03,444 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1117 [2019-11-25 08:53:03,444 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1117 states and 1635 transitions. [2019-11-25 08:53:03,445 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:53:03,446 INFO L688 BuchiCegarLoop]: Abstraction has 1117 states and 1635 transitions. [2019-11-25 08:53:03,447 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1117 states and 1635 transitions. [2019-11-25 08:53:03,460 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1117 to 1117. [2019-11-25 08:53:03,460 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1117 states. [2019-11-25 08:53:03,464 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1117 states to 1117 states and 1635 transitions. [2019-11-25 08:53:03,464 INFO L711 BuchiCegarLoop]: Abstraction has 1117 states and 1635 transitions. [2019-11-25 08:53:03,464 INFO L591 BuchiCegarLoop]: Abstraction has 1117 states and 1635 transitions. [2019-11-25 08:53:03,465 INFO L424 BuchiCegarLoop]: ======== Iteration 9============ [2019-11-25 08:53:03,465 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1117 states and 1635 transitions. [2019-11-25 08:53:03,470 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1050 [2019-11-25 08:53:03,470 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:53:03,470 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:53:03,471 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:03,472 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:03,472 INFO L794 eck$LassoCheckResult]: Stem: 8943#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 8760#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 8761#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 8984#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 8985#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8907#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8908#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8939#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8763#L351-1 assume !(0 == ~M_E~0); 8764#L492-1 assume !(0 == ~T1_E~0); 9033#L497-1 assume !(0 == ~T2_E~0); 9034#L502-1 assume !(0 == ~T3_E~0); 9060#L507-1 assume !(0 == ~T4_E~0); 8937#L512-1 assume !(0 == ~E_1~0); 8938#L517-1 assume !(0 == ~E_2~0); 8957#L522-1 assume !(0 == ~E_3~0); 8780#L527-1 assume !(0 == ~E_4~0); 8781#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8815#L228 assume !(1 == ~m_pc~0); 8825#L228-2 is_master_triggered_~__retres1~0 := 0; 8824#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8826#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 8827#L605 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8976#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8981#L247 assume !(1 == ~t1_pc~0); 8994#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 8995#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8903#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 8904#L613 assume !(0 != activate_threads_~tmp___0~0); 9138#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9018#L266 assume !(1 == ~t2_pc~0); 9019#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 9021#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9022#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 8745#L621 assume !(0 != activate_threads_~tmp___1~0); 8746#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8750#L285 assume !(1 == ~t3_pc~0); 8741#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 8742#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8753#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 8934#L629 assume !(0 != activate_threads_~tmp___2~0); 9023#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9024#L304 assume !(1 == ~t4_pc~0); 9040#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 9041#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9057#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8807#L637 assume !(0 != activate_threads_~tmp___3~0); 8808#L637-2 assume !(1 == ~M_E~0); 8809#L545-1 assume !(1 == ~T1_E~0); 8933#L550-1 assume !(1 == ~T2_E~0); 8756#L555-1 assume !(1 == ~T3_E~0); 8757#L560-1 assume !(1 == ~T4_E~0); 8811#L565-1 assume !(1 == ~E_1~0); 8814#L570-1 assume !(1 == ~E_2~0); 9073#L575-1 assume !(1 == ~E_3~0); 9115#L580-1 assume !(1 == ~E_4~0); 9139#L766-1 [2019-11-25 08:53:03,472 INFO L796 eck$LassoCheckResult]: Loop: 9139#L766-1 assume !false; 9696#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 9694#L467 assume !false; 9693#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 9691#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 9683#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 9678#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 9674#L406 assume !(0 != eval_~tmp~0); 9675#L482 start_simulation_~kernel_st~0 := 2; 9719#L324-1 start_simulation_~kernel_st~0 := 3; 9717#L492-2 assume !(0 == ~M_E~0); 9715#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9713#L497-3 assume !(0 == ~T2_E~0); 9711#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9709#L507-3 assume !(0 == ~T4_E~0); 9706#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9704#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9702#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9700#L527-3 assume !(0 == ~E_4~0); 9698#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9685#L228-15 assume !(1 == ~m_pc~0); 9680#L228-17 is_master_triggered_~__retres1~0 := 0; 9677#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8844#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 8845#L605-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8913#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8927#L247-15 assume !(1 == ~t1_pc~0); 8931#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 9795#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9793#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 9791#L613-15 assume !(0 != activate_threads_~tmp___0~0); 9789#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9787#L266-15 assume 1 == ~t2_pc~0; 9784#L267-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9782#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9779#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 9777#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 9775#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9773#L285-15 assume !(1 == ~t3_pc~0); 9771#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 9769#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9767#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 9765#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 9763#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9761#L304-15 assume 1 == ~t4_pc~0; 9758#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9756#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9754#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9753#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 9752#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 9751#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9750#L550-3 assume !(1 == ~T2_E~0); 9744#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9742#L560-3 assume !(1 == ~T4_E~0); 9740#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9738#L570-3 assume !(1 == ~E_2~0); 9736#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9735#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9734#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 9731#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 9728#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 9727#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 9725#L785 assume !(0 == start_simulation_~tmp~3); 9726#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 9747#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 9743#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 9741#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 9739#L740 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 9737#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 9724#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 9723#L798 assume !(0 != start_simulation_~tmp___0~1); 9139#L766-1 [2019-11-25 08:53:03,472 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:03,472 INFO L82 PathProgramCache]: Analyzing trace with hash 780863339, now seen corresponding path program 1 times [2019-11-25 08:53:03,473 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:03,473 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [25024459] [2019-11-25 08:53:03,473 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:03,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:03,542 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:03,542 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [25024459] [2019-11-25 08:53:03,543 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:03,543 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-25 08:53:03,543 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [232794684] [2019-11-25 08:53:03,543 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:53:03,544 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:03,544 INFO L82 PathProgramCache]: Analyzing trace with hash -691842910, now seen corresponding path program 1 times [2019-11-25 08:53:03,544 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:03,544 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [808225152] [2019-11-25 08:53:03,544 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:03,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:03,576 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:03,577 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [808225152] [2019-11-25 08:53:03,577 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:03,577 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:53:03,577 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [696191602] [2019-11-25 08:53:03,578 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:53:03,578 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:53:03,578 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-25 08:53:03,578 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-25 08:53:03,579 INFO L87 Difference]: Start difference. First operand 1117 states and 1635 transitions. cyclomatic complexity: 522 Second operand 5 states. [2019-11-25 08:53:03,757 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:53:03,758 INFO L93 Difference]: Finished difference Result 3126 states and 4538 transitions. [2019-11-25 08:53:03,758 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-25 08:53:03,758 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3126 states and 4538 transitions. [2019-11-25 08:53:03,777 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2970 [2019-11-25 08:53:03,800 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3126 states to 3126 states and 4538 transitions. [2019-11-25 08:53:03,801 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3126 [2019-11-25 08:53:03,805 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3126 [2019-11-25 08:53:03,806 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3126 states and 4538 transitions. [2019-11-25 08:53:03,810 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:53:03,810 INFO L688 BuchiCegarLoop]: Abstraction has 3126 states and 4538 transitions. [2019-11-25 08:53:03,813 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3126 states and 4538 transitions. [2019-11-25 08:53:03,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3126 to 1180. [2019-11-25 08:53:03,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1180 states. [2019-11-25 08:53:03,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1180 states to 1180 states and 1698 transitions. [2019-11-25 08:53:03,841 INFO L711 BuchiCegarLoop]: Abstraction has 1180 states and 1698 transitions. [2019-11-25 08:53:03,841 INFO L591 BuchiCegarLoop]: Abstraction has 1180 states and 1698 transitions. [2019-11-25 08:53:03,842 INFO L424 BuchiCegarLoop]: ======== Iteration 10============ [2019-11-25 08:53:03,842 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1180 states and 1698 transitions. [2019-11-25 08:53:03,847 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1110 [2019-11-25 08:53:03,847 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:53:03,847 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:53:03,848 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:03,848 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:03,849 INFO L794 eck$LassoCheckResult]: Stem: 13201#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 13014#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 13015#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 13245#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 13246#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13165#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13166#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13196#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13018#L351-1 assume !(0 == ~M_E~0); 13019#L492-1 assume !(0 == ~T1_E~0); 13294#L497-1 assume !(0 == ~T2_E~0); 13295#L502-1 assume !(0 == ~T3_E~0); 13322#L507-1 assume !(0 == ~T4_E~0); 13194#L512-1 assume !(0 == ~E_1~0); 13195#L517-1 assume !(0 == ~E_2~0); 13216#L522-1 assume !(0 == ~E_3~0); 13036#L527-1 assume !(0 == ~E_4~0); 13037#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13071#L228 assume !(1 == ~m_pc~0); 13080#L228-2 is_master_triggered_~__retres1~0 := 0; 13392#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13393#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 13238#L605 assume !(0 != activate_threads_~tmp~1); 13239#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13243#L247 assume !(1 == ~t1_pc~0); 13258#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 13259#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13160#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 13161#L613 assume !(0 != activate_threads_~tmp___0~0); 13415#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13280#L266 assume !(1 == ~t2_pc~0); 13281#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 13283#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13284#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 12999#L621 assume !(0 != activate_threads_~tmp___1~0); 13000#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13006#L285 assume !(1 == ~t3_pc~0); 12997#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 12998#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13007#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 13191#L629 assume !(0 != activate_threads_~tmp___2~0); 13285#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 13286#L304 assume !(1 == ~t4_pc~0); 13301#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 13302#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13319#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 13061#L637 assume !(0 != activate_threads_~tmp___3~0); 13062#L637-2 assume !(1 == ~M_E~0); 13065#L545-1 assume !(1 == ~T1_E~0); 13190#L550-1 assume !(1 == ~T2_E~0); 13010#L555-1 assume !(1 == ~T3_E~0); 13011#L560-1 assume !(1 == ~T4_E~0); 13067#L565-1 assume !(1 == ~E_1~0); 13070#L570-1 assume !(1 == ~E_2~0); 13335#L575-1 assume !(1 == ~E_3~0); 13379#L580-1 assume !(1 == ~E_4~0); 13416#L766-1 [2019-11-25 08:53:03,849 INFO L796 eck$LassoCheckResult]: Loop: 13416#L766-1 assume !false; 13278#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 13077#L467 assume !false; 13147#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 13148#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 13086#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 13151#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 13053#L406 assume !(0 != eval_~tmp~0); 13055#L482 start_simulation_~kernel_st~0 := 2; 14135#L324-1 start_simulation_~kernel_st~0 := 3; 14133#L492-2 assume !(0 == ~M_E~0); 14131#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14129#L497-3 assume !(0 == ~T2_E~0); 14126#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13324#L507-3 assume !(0 == ~T4_E~0); 13142#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13143#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13225#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13051#L527-3 assume !(0 == ~E_4~0); 13052#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13073#L228-15 assume 1 == ~m_pc~0; 13094#L229-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 13095#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14142#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 14141#L605-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 13169#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13182#L247-15 assume !(1 == ~t1_pc~0); 13187#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 14140#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14139#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 14138#L613-15 assume !(0 != activate_threads_~tmp___0~0); 14123#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13395#L266-15 assume !(1 == ~t2_pc~0); 13345#L266-17 is_transmit2_triggered_~__retres1~2 := 0; 13344#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13347#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 13236#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 13237#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13242#L285-15 assume !(1 == ~t3_pc~0); 13260#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 13029#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13030#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 13215#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 13414#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 13274#L304-15 assume 1 == ~t4_pc~0; 13275#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 13279#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13307#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 12995#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 12996#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 13005#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13138#L550-3 assume !(1 == ~T2_E~0); 13219#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13040#L560-3 assume !(1 == ~T4_E~0); 13041#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13072#L570-3 assume !(1 == ~E_2~0); 13348#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13386#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13292#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 13293#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 13098#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 13158#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 13113#L785 assume !(0 == start_simulation_~tmp~3); 13114#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 13122#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 13106#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 13995#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 13994#L740 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 13993#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 13992#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 13990#L798 assume !(0 != start_simulation_~tmp___0~1); 13416#L766-1 [2019-11-25 08:53:03,849 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:03,849 INFO L82 PathProgramCache]: Analyzing trace with hash -1463119959, now seen corresponding path program 1 times [2019-11-25 08:53:03,850 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:03,850 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [489894704] [2019-11-25 08:53:03,850 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:03,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:03,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:03,895 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:53:03,896 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:03,897 INFO L82 PathProgramCache]: Analyzing trace with hash 452069922, now seen corresponding path program 1 times [2019-11-25 08:53:03,897 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:03,897 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [969203062] [2019-11-25 08:53:03,897 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:03,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:03,922 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:03,922 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [969203062] [2019-11-25 08:53:03,922 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:03,922 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:53:03,923 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [736952151] [2019-11-25 08:53:03,923 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:53:03,923 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:53:03,923 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:53:03,924 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:53:03,924 INFO L87 Difference]: Start difference. First operand 1180 states and 1698 transitions. cyclomatic complexity: 522 Second operand 3 states. [2019-11-25 08:53:03,985 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:53:03,985 INFO L93 Difference]: Finished difference Result 2078 states and 2956 transitions. [2019-11-25 08:53:03,985 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:53:03,985 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2078 states and 2956 transitions. [2019-11-25 08:53:03,998 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1955 [2019-11-25 08:53:04,011 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2078 states to 2078 states and 2956 transitions. [2019-11-25 08:53:04,011 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2078 [2019-11-25 08:53:04,014 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2078 [2019-11-25 08:53:04,014 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2078 states and 2956 transitions. [2019-11-25 08:53:04,016 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:53:04,017 INFO L688 BuchiCegarLoop]: Abstraction has 2078 states and 2956 transitions. [2019-11-25 08:53:04,018 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2078 states and 2956 transitions. [2019-11-25 08:53:04,043 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2078 to 2076. [2019-11-25 08:53:04,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2076 states. [2019-11-25 08:53:04,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2076 states to 2076 states and 2954 transitions. [2019-11-25 08:53:04,049 INFO L711 BuchiCegarLoop]: Abstraction has 2076 states and 2954 transitions. [2019-11-25 08:53:04,049 INFO L591 BuchiCegarLoop]: Abstraction has 2076 states and 2954 transitions. [2019-11-25 08:53:04,049 INFO L424 BuchiCegarLoop]: ======== Iteration 11============ [2019-11-25 08:53:04,050 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2076 states and 2954 transitions. [2019-11-25 08:53:04,059 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1953 [2019-11-25 08:53:04,059 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:53:04,059 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:53:04,060 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:04,060 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:04,061 INFO L794 eck$LassoCheckResult]: Stem: 16466#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 16280#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 16281#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 16510#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 16511#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16430#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16431#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16462#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16284#L351-1 assume !(0 == ~M_E~0); 16285#L492-1 assume !(0 == ~T1_E~0); 16564#L497-1 assume !(0 == ~T2_E~0); 16565#L502-1 assume !(0 == ~T3_E~0); 16592#L507-1 assume !(0 == ~T4_E~0); 16460#L512-1 assume !(0 == ~E_1~0); 16461#L517-1 assume 0 == ~E_2~0;~E_2~0 := 1; 16478#L522-1 assume !(0 == ~E_3~0); 16303#L527-1 assume !(0 == ~E_4~0); 16304#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16339#L228 assume !(1 == ~m_pc~0); 16740#L228-2 is_master_triggered_~__retres1~0 := 0; 16653#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16349#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 16350#L605 assume !(0 != activate_threads_~tmp~1); 16502#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16737#L247 assume !(1 == ~t1_pc~0); 16523#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 16524#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16426#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 16427#L613 assume !(0 != activate_threads_~tmp___0~0); 16695#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16729#L266 assume !(1 == ~t2_pc~0); 16728#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 16646#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16647#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 16648#L621 assume !(0 != activate_threads_~tmp___1~0); 16271#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16272#L285 assume !(1 == ~t3_pc~0); 16727#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 16726#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16725#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 16724#L629 assume !(0 != activate_threads_~tmp___2~0); 16717#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16589#L304 assume !(1 == ~t4_pc~0); 16571#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 16572#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16588#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 16329#L637 assume !(0 != activate_threads_~tmp___3~0); 16330#L637-2 assume !(1 == ~M_E~0); 16333#L545-1 assume !(1 == ~T1_E~0); 16456#L550-1 assume !(1 == ~T2_E~0); 16276#L555-1 assume !(1 == ~T3_E~0); 16277#L560-1 assume !(1 == ~T4_E~0); 16335#L565-1 assume !(1 == ~E_1~0); 16338#L570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 16608#L575-1 assume !(1 == ~E_3~0); 16642#L580-1 assume !(1 == ~E_4~0); 16465#L766-1 [2019-11-25 08:53:04,061 INFO L796 eck$LassoCheckResult]: Loop: 16465#L766-1 assume !false; 16547#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 16548#L467 assume !false; 17624#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 17517#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 17511#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 17509#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 17506#L406 assume !(0 != eval_~tmp~0); 17507#L482 start_simulation_~kernel_st~0 := 2; 18174#L324-1 start_simulation_~kernel_st~0 := 3; 18172#L492-2 assume !(0 == ~M_E~0); 18170#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18168#L497-3 assume !(0 == ~T2_E~0); 18166#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18164#L507-3 assume !(0 == ~T4_E~0); 18162#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18161#L517-3 assume !(0 == ~E_2~0); 18160#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18158#L527-3 assume !(0 == ~E_4~0); 18157#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 18156#L228-15 assume !(1 == ~m_pc~0); 18153#L228-17 is_master_triggered_~__retres1~0 := 0; 18151#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 18149#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 18147#L605-15 assume !(0 != activate_threads_~tmp~1); 18144#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 18142#L247-15 assume !(1 == ~t1_pc~0); 18140#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 18138#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 18134#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 18132#L613-15 assume !(0 != activate_threads_~tmp___0~0); 18131#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18130#L266-15 assume !(1 == ~t2_pc~0); 18128#L266-17 is_transmit2_triggered_~__retres1~2 := 0; 18126#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 18124#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 18121#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 18116#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 18111#L285-15 assume !(1 == ~t3_pc~0); 18106#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 18101#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 18098#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 18095#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 18093#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 18091#L304-15 assume 1 == ~t4_pc~0; 18087#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 18084#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 18081#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 18078#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 18072#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 18068#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18063#L550-3 assume !(1 == ~T2_E~0); 18058#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18053#L560-3 assume !(1 == ~T4_E~0); 18049#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17984#L570-3 assume !(1 == ~E_2~0); 16619#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16650#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16562#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 16563#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 16365#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 16424#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 16380#L785 assume !(0 == start_simulation_~tmp~3); 16381#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 16389#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 16373#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 16428#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 16587#L740 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 16336#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 16337#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 16464#L798 assume !(0 != start_simulation_~tmp___0~1); 16465#L766-1 [2019-11-25 08:53:04,061 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:04,061 INFO L82 PathProgramCache]: Analyzing trace with hash -1711268375, now seen corresponding path program 1 times [2019-11-25 08:53:04,061 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:04,062 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1500035643] [2019-11-25 08:53:04,062 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:04,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:04,077 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:04,077 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1500035643] [2019-11-25 08:53:04,077 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:04,077 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:53:04,078 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2140112453] [2019-11-25 08:53:04,078 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:53:04,078 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:04,078 INFO L82 PathProgramCache]: Analyzing trace with hash -615074265, now seen corresponding path program 1 times [2019-11-25 08:53:04,078 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:04,079 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [69769773] [2019-11-25 08:53:04,079 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:04,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:04,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:04,150 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [69769773] [2019-11-25 08:53:04,150 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:04,150 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-11-25 08:53:04,150 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [803355939] [2019-11-25 08:53:04,151 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:53:04,151 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:53:04,151 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:53:04,151 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:53:04,151 INFO L87 Difference]: Start difference. First operand 2076 states and 2954 transitions. cyclomatic complexity: 882 Second operand 3 states. [2019-11-25 08:53:04,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:53:04,183 INFO L93 Difference]: Finished difference Result 1180 states and 1663 transitions. [2019-11-25 08:53:04,184 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:53:04,184 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1180 states and 1663 transitions. [2019-11-25 08:53:04,189 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1110 [2019-11-25 08:53:04,197 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1180 states to 1180 states and 1663 transitions. [2019-11-25 08:53:04,197 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2019-11-25 08:53:04,198 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2019-11-25 08:53:04,198 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1663 transitions. [2019-11-25 08:53:04,200 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:53:04,200 INFO L688 BuchiCegarLoop]: Abstraction has 1180 states and 1663 transitions. [2019-11-25 08:53:04,201 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1663 transitions. [2019-11-25 08:53:04,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 1180. [2019-11-25 08:53:04,214 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1180 states. [2019-11-25 08:53:04,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1180 states to 1180 states and 1663 transitions. [2019-11-25 08:53:04,218 INFO L711 BuchiCegarLoop]: Abstraction has 1180 states and 1663 transitions. [2019-11-25 08:53:04,218 INFO L591 BuchiCegarLoop]: Abstraction has 1180 states and 1663 transitions. [2019-11-25 08:53:04,218 INFO L424 BuchiCegarLoop]: ======== Iteration 12============ [2019-11-25 08:53:04,218 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1180 states and 1663 transitions. [2019-11-25 08:53:04,221 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1110 [2019-11-25 08:53:04,222 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:53:04,222 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:53:04,223 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:04,223 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:04,223 INFO L794 eck$LassoCheckResult]: Stem: 19734#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 19551#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 19552#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 19777#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 19778#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19698#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19699#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19731#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19554#L351-1 assume !(0 == ~M_E~0); 19555#L492-1 assume !(0 == ~T1_E~0); 19826#L497-1 assume !(0 == ~T2_E~0); 19827#L502-1 assume !(0 == ~T3_E~0); 19852#L507-1 assume !(0 == ~T4_E~0); 19728#L512-1 assume !(0 == ~E_1~0); 19729#L517-1 assume !(0 == ~E_2~0); 19747#L522-1 assume !(0 == ~E_3~0); 19571#L527-1 assume !(0 == ~E_4~0); 19572#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 19606#L228 assume !(1 == ~m_pc~0); 19615#L228-2 is_master_triggered_~__retres1~0 := 0; 19901#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 19616#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 19617#L605 assume !(0 != activate_threads_~tmp~1); 19768#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 19773#L247 assume !(1 == ~t1_pc~0); 19789#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 19790#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 19694#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 19695#L613 assume !(0 != activate_threads_~tmp___0~0); 19922#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 19811#L266 assume !(1 == ~t2_pc~0); 19812#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 19814#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 19815#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 19536#L621 assume !(0 != activate_threads_~tmp___1~0); 19537#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 19541#L285 assume !(1 == ~t3_pc~0); 19532#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 19533#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 19544#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 19727#L629 assume !(0 != activate_threads_~tmp___2~0); 19816#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 19817#L304 assume !(1 == ~t4_pc~0); 19832#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 19833#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 19849#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 19598#L637 assume !(0 != activate_threads_~tmp___3~0); 19599#L637-2 assume !(1 == ~M_E~0); 19600#L545-1 assume !(1 == ~T1_E~0); 19724#L550-1 assume !(1 == ~T2_E~0); 19547#L555-1 assume !(1 == ~T3_E~0); 19548#L560-1 assume !(1 == ~T4_E~0); 19602#L565-1 assume !(1 == ~E_1~0); 19605#L570-1 assume !(1 == ~E_2~0); 19863#L575-1 assume !(1 == ~E_3~0); 19895#L580-1 assume !(1 == ~E_4~0); 19733#L766-1 [2019-11-25 08:53:04,223 INFO L796 eck$LassoCheckResult]: Loop: 19733#L766-1 assume !false; 19810#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 19612#L467 assume !false; 19681#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 19682#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 19620#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 19685#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 19590#L406 assume !(0 != eval_~tmp~0); 19592#L482 start_simulation_~kernel_st~0 := 2; 20704#L324-1 start_simulation_~kernel_st~0 := 3; 20703#L492-2 assume !(0 == ~M_E~0); 20702#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20701#L497-3 assume !(0 == ~T2_E~0); 20700#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20699#L507-3 assume !(0 == ~T4_E~0); 19676#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19677#L517-3 assume !(0 == ~E_2~0); 20674#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20673#L527-3 assume !(0 == ~E_4~0); 20579#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20578#L228-15 assume !(1 == ~m_pc~0); 20576#L228-17 is_master_triggered_~__retres1~0 := 0; 20574#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20572#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 20571#L605-15 assume !(0 != activate_threads_~tmp~1); 20569#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20548#L247-15 assume !(1 == ~t1_pc~0); 20519#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 20515#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20513#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 20511#L613-15 assume !(0 != activate_threads_~tmp___0~0); 20509#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20506#L266-15 assume !(1 == ~t2_pc~0); 20503#L266-17 is_transmit2_triggered_~__retres1~2 := 0; 20501#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20499#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 20497#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 20495#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20493#L285-15 assume !(1 == ~t3_pc~0); 20491#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 20488#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20486#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 20484#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 20482#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20480#L304-15 assume 1 == ~t4_pc~0; 20477#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 20475#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 20473#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 20471#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 20469#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 20467#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20465#L550-3 assume !(1 == ~T2_E~0); 20463#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20460#L560-3 assume !(1 == ~T4_E~0); 20458#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20456#L570-3 assume !(1 == ~E_2~0); 20454#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20452#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20450#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 20443#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 20439#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 20437#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 20435#L785 assume !(0 == start_simulation_~tmp~3); 19656#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 19657#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 19640#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 19696#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 19848#L740 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 19603#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 19604#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 19732#L798 assume !(0 != start_simulation_~tmp___0~1); 19733#L766-1 [2019-11-25 08:53:04,223 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:04,224 INFO L82 PathProgramCache]: Analyzing trace with hash -1463119959, now seen corresponding path program 2 times [2019-11-25 08:53:04,224 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:04,224 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [364254438] [2019-11-25 08:53:04,224 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:04,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:04,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:04,244 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:53:04,245 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:04,245 INFO L82 PathProgramCache]: Analyzing trace with hash -615074265, now seen corresponding path program 2 times [2019-11-25 08:53:04,245 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:04,245 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1808525377] [2019-11-25 08:53:04,245 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:04,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:04,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:04,331 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1808525377] [2019-11-25 08:53:04,331 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:04,331 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-11-25 08:53:04,331 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [515935226] [2019-11-25 08:53:04,332 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:53:04,332 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:53:04,332 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-11-25 08:53:04,332 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2019-11-25 08:53:04,332 INFO L87 Difference]: Start difference. First operand 1180 states and 1663 transitions. cyclomatic complexity: 487 Second operand 11 states. [2019-11-25 08:53:04,538 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:53:04,538 INFO L93 Difference]: Finished difference Result 2050 states and 2853 transitions. [2019-11-25 08:53:04,538 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-11-25 08:53:04,538 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2050 states and 2853 transitions. [2019-11-25 08:53:04,547 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1972 [2019-11-25 08:53:04,560 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2050 states to 2050 states and 2853 transitions. [2019-11-25 08:53:04,560 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2050 [2019-11-25 08:53:04,562 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2050 [2019-11-25 08:53:04,562 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2050 states and 2853 transitions. [2019-11-25 08:53:04,565 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:53:04,565 INFO L688 BuchiCegarLoop]: Abstraction has 2050 states and 2853 transitions. [2019-11-25 08:53:04,566 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2050 states and 2853 transitions. [2019-11-25 08:53:04,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2050 to 1192. [2019-11-25 08:53:04,583 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1192 states. [2019-11-25 08:53:04,587 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1192 states to 1192 states and 1675 transitions. [2019-11-25 08:53:04,587 INFO L711 BuchiCegarLoop]: Abstraction has 1192 states and 1675 transitions. [2019-11-25 08:53:04,587 INFO L591 BuchiCegarLoop]: Abstraction has 1192 states and 1675 transitions. [2019-11-25 08:53:04,587 INFO L424 BuchiCegarLoop]: ======== Iteration 13============ [2019-11-25 08:53:04,587 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1192 states and 1675 transitions. [2019-11-25 08:53:04,590 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1122 [2019-11-25 08:53:04,591 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:53:04,591 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:53:04,592 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:04,592 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:04,592 INFO L794 eck$LassoCheckResult]: Stem: 22984#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 22802#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 22803#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 23024#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 23025#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22951#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22952#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22979#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22806#L351-1 assume !(0 == ~M_E~0); 22807#L492-1 assume !(0 == ~T1_E~0); 23072#L497-1 assume !(0 == ~T2_E~0); 23073#L502-1 assume !(0 == ~T3_E~0); 23101#L507-1 assume !(0 == ~T4_E~0); 22977#L512-1 assume !(0 == ~E_1~0); 22978#L517-1 assume !(0 == ~E_2~0); 22995#L522-1 assume !(0 == ~E_3~0); 22824#L527-1 assume !(0 == ~E_4~0); 22825#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22858#L228 assume !(1 == ~m_pc~0); 22867#L228-2 is_master_triggered_~__retres1~0 := 0; 23172#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23194#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 23019#L605 assume !(0 != activate_threads_~tmp~1); 23020#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 23022#L247 assume !(1 == ~t1_pc~0); 23035#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 23036#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22947#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 22948#L613 assume !(0 != activate_threads_~tmp___0~0); 23180#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 23058#L266 assume !(1 == ~t2_pc~0); 23059#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 23061#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 23062#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 22787#L621 assume !(0 != activate_threads_~tmp___1~0); 22788#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22794#L285 assume !(1 == ~t3_pc~0); 22785#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 22786#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22795#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 22974#L629 assume !(0 != activate_threads_~tmp___2~0); 23063#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 23064#L304 assume !(1 == ~t4_pc~0); 23081#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 23082#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 23098#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 22848#L637 assume !(0 != activate_threads_~tmp___3~0); 22849#L637-2 assume !(1 == ~M_E~0); 22852#L545-1 assume !(1 == ~T1_E~0); 22973#L550-1 assume !(1 == ~T2_E~0); 22798#L555-1 assume !(1 == ~T3_E~0); 22799#L560-1 assume !(1 == ~T4_E~0); 22854#L565-1 assume !(1 == ~E_1~0); 22857#L570-1 assume !(1 == ~E_2~0); 23114#L575-1 assume !(1 == ~E_3~0); 23147#L580-1 assume !(1 == ~E_4~0); 23181#L766-1 [2019-11-25 08:53:04,592 INFO L796 eck$LassoCheckResult]: Loop: 23181#L766-1 assume !false; 23696#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 23695#L467 assume !false; 23468#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 23414#L364 assume !(0 == ~m_st~0); 23411#L368 assume !(0 == ~t1_st~0); 23412#L372 assume !(0 == ~t2_st~0); 23413#L376 assume !(0 == ~t3_st~0); 23410#L380 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 23393#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 23385#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 23383#L406 assume !(0 != eval_~tmp~0); 23122#L482 start_simulation_~kernel_st~0 := 2; 23029#L324-1 start_simulation_~kernel_st~0 := 3; 23030#L492-2 assume !(0 == ~M_E~0); 23167#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23046#L497-3 assume !(0 == ~T2_E~0); 23047#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 23096#L507-3 assume !(0 == ~T4_E~0); 22927#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22928#L517-3 assume !(0 == ~E_2~0); 23492#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22839#L527-3 assume !(0 == ~E_4~0); 22840#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22860#L228-15 assume 1 == ~m_pc~0; 23489#L229-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 23487#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23485#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 23483#L605-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 23482#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 23481#L247-15 assume !(1 == ~t1_pc~0); 23480#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 23479#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 23478#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 23476#L613-15 assume !(0 != activate_threads_~tmp___0~0); 23474#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 23472#L266-15 assume !(1 == ~t2_pc~0); 23469#L266-17 is_transmit2_triggered_~__retres1~2 := 0; 23260#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 23261#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 23017#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 23018#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 23021#L285-15 assume !(1 == ~t3_pc~0); 23041#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 23857#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 23856#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 23855#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 23177#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 23052#L304-15 assume 1 == ~t4_pc~0; 23053#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 23057#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 23087#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 22783#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 22784#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 22793#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22923#L550-3 assume !(1 == ~T2_E~0); 23843#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23841#L560-3 assume !(1 == ~T4_E~0); 23839#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23837#L570-3 assume !(1 == ~E_2~0); 23834#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23832#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23830#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 23826#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 23820#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 23742#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 23739#L785 assume !(0 == start_simulation_~tmp~3); 23736#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 23722#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 23718#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 23716#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 23714#L740 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 23712#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 23710#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 23708#L798 assume !(0 != start_simulation_~tmp___0~1); 23181#L766-1 [2019-11-25 08:53:04,592 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:04,593 INFO L82 PathProgramCache]: Analyzing trace with hash -1463119959, now seen corresponding path program 3 times [2019-11-25 08:53:04,593 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:04,593 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [335041635] [2019-11-25 08:53:04,593 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:04,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:04,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:04,623 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:53:04,624 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:04,625 INFO L82 PathProgramCache]: Analyzing trace with hash -1470455504, now seen corresponding path program 1 times [2019-11-25 08:53:04,625 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:04,625 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1442086215] [2019-11-25 08:53:04,625 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:04,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:04,689 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:04,689 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1442086215] [2019-11-25 08:53:04,689 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:04,690 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-11-25 08:53:04,690 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [392387884] [2019-11-25 08:53:04,690 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:53:04,690 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:53:04,691 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-11-25 08:53:04,691 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2019-11-25 08:53:04,691 INFO L87 Difference]: Start difference. First operand 1192 states and 1675 transitions. cyclomatic complexity: 487 Second operand 8 states. [2019-11-25 08:53:04,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:53:04,880 INFO L93 Difference]: Finished difference Result 3866 states and 5377 transitions. [2019-11-25 08:53:04,880 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-11-25 08:53:04,880 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3866 states and 5377 transitions. [2019-11-25 08:53:04,897 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3772 [2019-11-25 08:53:04,923 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3866 states to 3866 states and 5377 transitions. [2019-11-25 08:53:04,923 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3866 [2019-11-25 08:53:04,927 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3866 [2019-11-25 08:53:04,927 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3866 states and 5377 transitions. [2019-11-25 08:53:04,933 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:53:04,933 INFO L688 BuchiCegarLoop]: Abstraction has 3866 states and 5377 transitions. [2019-11-25 08:53:04,936 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3866 states and 5377 transitions. [2019-11-25 08:53:04,962 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3866 to 1204. [2019-11-25 08:53:04,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1204 states. [2019-11-25 08:53:04,966 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1204 states to 1204 states and 1687 transitions. [2019-11-25 08:53:04,966 INFO L711 BuchiCegarLoop]: Abstraction has 1204 states and 1687 transitions. [2019-11-25 08:53:04,966 INFO L591 BuchiCegarLoop]: Abstraction has 1204 states and 1687 transitions. [2019-11-25 08:53:04,966 INFO L424 BuchiCegarLoop]: ======== Iteration 14============ [2019-11-25 08:53:04,966 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1204 states and 1687 transitions. [2019-11-25 08:53:04,969 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1134 [2019-11-25 08:53:04,969 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:53:04,969 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:53:04,970 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:04,970 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:04,971 INFO L794 eck$LassoCheckResult]: Stem: 28066#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 27881#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 27882#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 28110#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 28111#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28031#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28032#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28063#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27884#L351-1 assume !(0 == ~M_E~0); 27885#L492-1 assume !(0 == ~T1_E~0); 28159#L497-1 assume !(0 == ~T2_E~0); 28160#L502-1 assume !(0 == ~T3_E~0); 28185#L507-1 assume !(0 == ~T4_E~0); 28059#L512-1 assume !(0 == ~E_1~0); 28060#L517-1 assume !(0 == ~E_2~0); 28080#L522-1 assume !(0 == ~E_3~0); 27902#L527-1 assume !(0 == ~E_4~0); 27903#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27936#L228 assume !(1 == ~m_pc~0); 27945#L228-2 is_master_triggered_~__retres1~0 := 0; 28257#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 28274#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 28103#L605 assume !(0 != activate_threads_~tmp~1); 28104#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 28107#L247 assume !(1 == ~t1_pc~0); 28119#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 28120#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 28026#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 28027#L613 assume !(0 != activate_threads_~tmp___0~0); 28266#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 28144#L266 assume !(1 == ~t2_pc~0); 28145#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 28147#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 28148#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 27866#L621 assume !(0 != activate_threads_~tmp___1~0); 27867#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 27871#L285 assume !(1 == ~t3_pc~0); 27862#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 27863#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 27874#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 28058#L629 assume !(0 != activate_threads_~tmp___2~0); 28149#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 28150#L304 assume !(1 == ~t4_pc~0); 28165#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 28166#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 28182#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 27928#L637 assume !(0 != activate_threads_~tmp___3~0); 27929#L637-2 assume !(1 == ~M_E~0); 27930#L545-1 assume !(1 == ~T1_E~0); 28055#L550-1 assume !(1 == ~T2_E~0); 27877#L555-1 assume !(1 == ~T3_E~0); 27878#L560-1 assume !(1 == ~T4_E~0); 27932#L565-1 assume !(1 == ~E_1~0); 27935#L570-1 assume !(1 == ~E_2~0); 28196#L575-1 assume !(1 == ~E_3~0); 28230#L580-1 assume !(1 == ~E_4~0); 28267#L766-1 [2019-11-25 08:53:04,971 INFO L796 eck$LassoCheckResult]: Loop: 28267#L766-1 assume !false; 28545#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 28523#L467 assume !false; 28442#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 28443#L364 assume !(0 == ~m_st~0); 28435#L368 assume !(0 == ~t1_st~0); 28436#L372 assume !(0 == ~t2_st~0); 28429#L376 assume !(0 == ~t3_st~0); 28430#L380 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 28420#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 28421#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 28391#L406 assume !(0 != eval_~tmp~0); 28392#L482 start_simulation_~kernel_st~0 := 2; 28367#L324-1 start_simulation_~kernel_st~0 := 3; 28368#L492-2 assume !(0 == ~M_E~0); 28359#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28360#L497-3 assume !(0 == ~T2_E~0); 28349#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28350#L507-3 assume !(0 == ~T4_E~0); 28518#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 28087#L517-3 assume !(0 == ~E_2~0); 28088#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28122#L527-3 assume !(0 == ~E_4~0); 28516#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 28515#L228-15 assume 1 == ~m_pc~0; 27958#L229-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 27959#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 27964#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 27965#L605-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 28036#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 28047#L247-15 assume !(1 == ~t1_pc~0); 28053#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 28097#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 28098#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 28193#L613-15 assume !(0 != activate_threads_~tmp___0~0); 28223#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 28224#L266-15 assume !(1 == ~t2_pc~0); 28854#L266-17 is_transmit2_triggered_~__retres1~2 := 0; 28853#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 28204#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 28205#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 28852#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 28851#L285-15 assume !(1 == ~t3_pc~0); 28850#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 28849#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 28848#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 28847#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 28846#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 28845#L304-15 assume 1 == ~t4_pc~0; 28843#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 28842#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 28841#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 28840#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 28839#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 28838#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28837#L550-3 assume !(1 == ~T2_E~0); 28836#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28835#L560-3 assume !(1 == ~T4_E~0); 28834#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28833#L570-3 assume !(1 == ~E_2~0); 28832#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28831#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28830#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 28827#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 28816#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 28812#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 28803#L785 assume !(0 == start_simulation_~tmp~3); 27986#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 27987#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 28577#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 28575#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 28573#L740 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 28571#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 28558#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 28556#L798 assume !(0 != start_simulation_~tmp___0~1); 28267#L766-1 [2019-11-25 08:53:04,971 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:04,971 INFO L82 PathProgramCache]: Analyzing trace with hash -1463119959, now seen corresponding path program 4 times [2019-11-25 08:53:04,971 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:04,972 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [239259398] [2019-11-25 08:53:04,972 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:04,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:04,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:04,997 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:53:04,997 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:04,997 INFO L82 PathProgramCache]: Analyzing trace with hash -1470515086, now seen corresponding path program 1 times [2019-11-25 08:53:04,998 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:05,000 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [316454950] [2019-11-25 08:53:05,000 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:05,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:05,067 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:05,067 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [316454950] [2019-11-25 08:53:05,067 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:05,068 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-25 08:53:05,068 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2044972005] [2019-11-25 08:53:05,068 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:53:05,070 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:53:05,070 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-25 08:53:05,073 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-25 08:53:05,073 INFO L87 Difference]: Start difference. First operand 1204 states and 1687 transitions. cyclomatic complexity: 487 Second operand 5 states. [2019-11-25 08:53:05,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:53:05,207 INFO L93 Difference]: Finished difference Result 1655 states and 2315 transitions. [2019-11-25 08:53:05,209 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-25 08:53:05,209 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1655 states and 2315 transitions. [2019-11-25 08:53:05,216 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1581 [2019-11-25 08:53:05,234 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1655 states to 1655 states and 2315 transitions. [2019-11-25 08:53:05,234 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1655 [2019-11-25 08:53:05,236 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1655 [2019-11-25 08:53:05,236 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1655 states and 2315 transitions. [2019-11-25 08:53:05,239 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:53:05,239 INFO L688 BuchiCegarLoop]: Abstraction has 1655 states and 2315 transitions. [2019-11-25 08:53:05,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1655 states and 2315 transitions. [2019-11-25 08:53:05,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1655 to 1210. [2019-11-25 08:53:05,260 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1210 states. [2019-11-25 08:53:05,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1210 states to 1210 states and 1674 transitions. [2019-11-25 08:53:05,263 INFO L711 BuchiCegarLoop]: Abstraction has 1210 states and 1674 transitions. [2019-11-25 08:53:05,263 INFO L591 BuchiCegarLoop]: Abstraction has 1210 states and 1674 transitions. [2019-11-25 08:53:05,263 INFO L424 BuchiCegarLoop]: ======== Iteration 15============ [2019-11-25 08:53:05,263 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1210 states and 1674 transitions. [2019-11-25 08:53:05,266 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1140 [2019-11-25 08:53:05,267 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:53:05,267 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:53:05,268 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:05,268 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:05,268 INFO L794 eck$LassoCheckResult]: Stem: 30942#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 30752#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 30753#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 30984#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 30985#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30906#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30907#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30937#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30756#L351-1 assume !(0 == ~M_E~0); 30757#L492-1 assume !(0 == ~T1_E~0); 31038#L497-1 assume !(0 == ~T2_E~0); 31039#L502-1 assume !(0 == ~T3_E~0); 31067#L507-1 assume !(0 == ~T4_E~0); 30935#L512-1 assume !(0 == ~E_1~0); 30936#L517-1 assume !(0 == ~E_2~0); 30957#L522-1 assume !(0 == ~E_3~0); 30775#L527-1 assume !(0 == ~E_4~0); 30776#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30809#L228 assume !(1 == ~m_pc~0); 30819#L228-2 is_master_triggered_~__retres1~0 := 0; 31149#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 31178#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 30977#L605 assume !(0 != activate_threads_~tmp~1); 30978#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30980#L247 assume !(1 == ~t1_pc~0); 30998#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 30999#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30901#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 30902#L613 assume !(0 != activate_threads_~tmp___0~0); 31157#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 31024#L266 assume !(1 == ~t2_pc~0); 31025#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 31027#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 31028#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 30737#L621 assume !(0 != activate_threads_~tmp___1~0); 30738#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 30744#L285 assume !(1 == ~t3_pc~0); 30735#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 30736#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 30745#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 30932#L629 assume !(0 != activate_threads_~tmp___2~0); 31029#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 31030#L304 assume !(1 == ~t4_pc~0); 31045#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 31046#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 31064#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 30799#L637 assume !(0 != activate_threads_~tmp___3~0); 30800#L637-2 assume !(1 == ~M_E~0); 30803#L545-1 assume !(1 == ~T1_E~0); 30931#L550-1 assume !(1 == ~T2_E~0); 30748#L555-1 assume !(1 == ~T3_E~0); 30749#L560-1 assume !(1 == ~T4_E~0); 30805#L565-1 assume !(1 == ~E_1~0); 30808#L570-1 assume !(1 == ~E_2~0); 31083#L575-1 assume !(1 == ~E_3~0); 31113#L580-1 assume !(1 == ~E_4~0); 31158#L766-1 [2019-11-25 08:53:05,268 INFO L796 eck$LassoCheckResult]: Loop: 31158#L766-1 assume !false; 31729#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 31722#L467 assume !false; 31676#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 31673#L364 assume !(0 == ~m_st~0); 31670#L368 assume !(0 == ~t1_st~0); 31671#L372 assume !(0 == ~t2_st~0); 31672#L376 assume !(0 == ~t3_st~0); 31668#L380 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 31669#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 31662#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 31663#L406 assume !(0 != eval_~tmp~0); 31091#L482 start_simulation_~kernel_st~0 := 2; 30989#L324-1 start_simulation_~kernel_st~0 := 3; 30990#L492-2 assume !(0 == ~M_E~0); 31141#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31010#L497-3 assume !(0 == ~T2_E~0); 31011#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31059#L507-3 assume !(0 == ~T4_E~0); 30881#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30882#L517-3 assume !(0 == ~E_2~0); 30966#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31001#L527-3 assume !(0 == ~E_4~0); 30811#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30812#L228-15 assume 1 == ~m_pc~0; 30832#L229-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 30833#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 31915#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 31912#L605-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 30911#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30925#L247-15 assume !(1 == ~t1_pc~0); 30919#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 30920#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30971#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 31080#L613-15 assume !(0 != activate_threads_~tmp___0~0); 31109#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 31110#L266-15 assume !(1 == ~t2_pc~0); 31090#L266-17 is_transmit2_triggered_~__retres1~2 := 0; 31153#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 31159#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 31584#L621-15 assume !(0 != activate_threads_~tmp___1~0); 31583#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 31582#L285-15 assume !(1 == ~t3_pc~0); 31581#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 31580#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 31578#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 31177#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 31154#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 31017#L304-15 assume 1 == ~t4_pc~0; 31018#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 31572#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 31571#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 31570#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 31569#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 31568#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31567#L550-3 assume !(1 == ~T2_E~0); 31566#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31564#L560-3 assume !(1 == ~T4_E~0); 31562#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 31560#L570-3 assume !(1 == ~E_2~0); 31557#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31553#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31550#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 31545#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 31540#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 31536#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 30851#L785 assume !(0 == start_simulation_~tmp~3); 30852#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 31758#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 31754#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 31752#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 31749#L740 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 31746#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 31744#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 31742#L798 assume !(0 != start_simulation_~tmp___0~1); 31158#L766-1 [2019-11-25 08:53:05,269 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:05,269 INFO L82 PathProgramCache]: Analyzing trace with hash -1463119959, now seen corresponding path program 5 times [2019-11-25 08:53:05,269 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:05,269 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1180423831] [2019-11-25 08:53:05,269 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:05,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:05,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:05,286 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:53:05,287 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:05,287 INFO L82 PathProgramCache]: Analyzing trace with hash 1980446708, now seen corresponding path program 1 times [2019-11-25 08:53:05,287 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:05,287 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [287626284] [2019-11-25 08:53:05,287 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:05,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:05,362 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:05,364 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [287626284] [2019-11-25 08:53:05,364 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:05,365 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-25 08:53:05,365 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [826737874] [2019-11-25 08:53:05,365 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:53:05,365 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:53:05,366 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-25 08:53:05,366 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-25 08:53:05,366 INFO L87 Difference]: Start difference. First operand 1210 states and 1674 transitions. cyclomatic complexity: 468 Second operand 5 states. [2019-11-25 08:53:05,546 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:53:05,546 INFO L93 Difference]: Finished difference Result 2087 states and 2893 transitions. [2019-11-25 08:53:05,546 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-25 08:53:05,547 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2087 states and 2893 transitions. [2019-11-25 08:53:05,553 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2013 [2019-11-25 08:53:05,561 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2087 states to 2087 states and 2893 transitions. [2019-11-25 08:53:05,562 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2087 [2019-11-25 08:53:05,563 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2087 [2019-11-25 08:53:05,563 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2087 states and 2893 transitions. [2019-11-25 08:53:05,565 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:53:05,565 INFO L688 BuchiCegarLoop]: Abstraction has 2087 states and 2893 transitions. [2019-11-25 08:53:05,567 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2087 states and 2893 transitions. [2019-11-25 08:53:05,585 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2087 to 1243. [2019-11-25 08:53:05,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1243 states. [2019-11-25 08:53:05,587 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1243 states to 1243 states and 1697 transitions. [2019-11-25 08:53:05,588 INFO L711 BuchiCegarLoop]: Abstraction has 1243 states and 1697 transitions. [2019-11-25 08:53:05,588 INFO L591 BuchiCegarLoop]: Abstraction has 1243 states and 1697 transitions. [2019-11-25 08:53:05,588 INFO L424 BuchiCegarLoop]: ======== Iteration 16============ [2019-11-25 08:53:05,588 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1243 states and 1697 transitions. [2019-11-25 08:53:05,591 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1173 [2019-11-25 08:53:05,591 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:53:05,591 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:53:05,592 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:05,592 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:05,592 INFO L794 eck$LassoCheckResult]: Stem: 34254#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 34066#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 34067#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 34299#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 34300#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34218#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34219#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34251#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34068#L351-1 assume !(0 == ~M_E~0); 34069#L492-1 assume !(0 == ~T1_E~0); 34357#L497-1 assume !(0 == ~T2_E~0); 34358#L502-1 assume !(0 == ~T3_E~0); 34385#L507-1 assume !(0 == ~T4_E~0); 34248#L512-1 assume !(0 == ~E_1~0); 34249#L517-1 assume !(0 == ~E_2~0); 34268#L522-1 assume !(0 == ~E_3~0); 34089#L527-1 assume !(0 == ~E_4~0); 34090#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 34123#L228 assume !(1 == ~m_pc~0); 34132#L228-2 is_master_triggered_~__retres1~0 := 0; 34454#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 34479#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 34290#L605 assume !(0 != activate_threads_~tmp~1); 34291#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 34294#L247 assume !(1 == ~t1_pc~0); 34313#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 34314#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 34213#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 34214#L613 assume !(0 != activate_threads_~tmp___0~0); 34463#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 34341#L266 assume !(1 == ~t2_pc~0); 34342#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 34344#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 34345#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 34049#L621 assume !(0 != activate_threads_~tmp___1~0); 34050#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 34056#L285 assume !(1 == ~t3_pc~0); 34047#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 34048#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 34059#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 34247#L629 assume !(0 != activate_threads_~tmp___2~0); 34346#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 34347#L304 assume !(1 == ~t4_pc~0); 34364#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 34365#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 34382#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 34115#L637 assume !(0 != activate_threads_~tmp___3~0); 34116#L637-2 assume !(1 == ~M_E~0); 34117#L545-1 assume !(1 == ~T1_E~0); 34244#L550-1 assume !(1 == ~T2_E~0); 34062#L555-1 assume !(1 == ~T3_E~0); 34063#L560-1 assume !(1 == ~T4_E~0); 34119#L565-1 assume !(1 == ~E_1~0); 34122#L570-1 assume !(1 == ~E_2~0); 34398#L575-1 assume !(1 == ~E_3~0); 34432#L580-1 assume !(1 == ~E_4~0); 34464#L766-1 [2019-11-25 08:53:05,592 INFO L796 eck$LassoCheckResult]: Loop: 34464#L766-1 assume !false; 34904#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 34903#L467 assume !false; 34902#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 34901#L364 assume !(0 == ~m_st~0); 34898#L368 assume !(0 == ~t1_st~0); 34899#L372 assume !(0 == ~t2_st~0); 34900#L376 assume !(0 == ~t3_st~0); 34896#L380 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 34897#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 34816#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 34817#L406 assume !(0 != eval_~tmp~0); 35079#L482 start_simulation_~kernel_st~0 := 2; 35078#L324-1 start_simulation_~kernel_st~0 := 3; 35077#L492-2 assume !(0 == ~M_E~0); 35076#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 35075#L497-3 assume !(0 == ~T2_E~0); 35074#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 35073#L507-3 assume !(0 == ~T4_E~0); 35072#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35071#L517-3 assume !(0 == ~E_2~0); 35070#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35069#L527-3 assume !(0 == ~E_4~0); 35068#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 35067#L228-15 assume 1 == ~m_pc~0; 35065#L229-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 35063#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 35061#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 35059#L605-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 34239#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 34240#L247-15 assume !(1 == ~t1_pc~0); 34235#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 34236#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 34284#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 34395#L613-15 assume !(0 != activate_threads_~tmp___0~0); 34427#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 34428#L266-15 assume !(1 == ~t2_pc~0); 34404#L266-17 is_transmit2_triggered_~__retres1~2 := 0; 34457#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 34407#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 34287#L621-15 assume !(0 != activate_threads_~tmp___1~0); 34288#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 34292#L285-15 assume !(1 == ~t3_pc~0); 34322#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 34992#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 34991#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 34990#L629-15 assume !(0 != activate_threads_~tmp___2~0); 34989#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 34988#L304-15 assume 1 == ~t4_pc~0; 34986#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 34984#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 34982#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 34980#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 34978#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 34976#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34973#L550-3 assume !(1 == ~T2_E~0); 34971#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34969#L560-3 assume !(1 == ~T4_E~0); 34967#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34965#L570-3 assume !(1 == ~E_2~0); 34963#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34961#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34959#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 34954#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 34949#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 34946#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 34942#L785 assume !(0 == start_simulation_~tmp~3); 34939#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 34934#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 34930#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 34927#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 34924#L740 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 34919#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 34917#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 34912#L798 assume !(0 != start_simulation_~tmp___0~1); 34464#L766-1 [2019-11-25 08:53:05,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:05,593 INFO L82 PathProgramCache]: Analyzing trace with hash -1463119959, now seen corresponding path program 6 times [2019-11-25 08:53:05,593 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:05,593 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [418641969] [2019-11-25 08:53:05,593 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:05,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:05,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:05,608 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:53:05,609 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:05,609 INFO L82 PathProgramCache]: Analyzing trace with hash -928317194, now seen corresponding path program 1 times [2019-11-25 08:53:05,609 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:05,609 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1289274546] [2019-11-25 08:53:05,609 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:05,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:05,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:05,633 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:53:05,634 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:05,634 INFO L82 PathProgramCache]: Analyzing trace with hash 1060034638, now seen corresponding path program 1 times [2019-11-25 08:53:05,634 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:05,634 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1441250444] [2019-11-25 08:53:05,634 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:05,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:05,674 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:05,674 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1441250444] [2019-11-25 08:53:05,674 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:05,674 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:53:05,675 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1066159595] [2019-11-25 08:53:06,338 WARN L192 SmtUtils]: Spent 654.00 ms on a formula simplification. DAG size of input: 161 DAG size of output: 144 [2019-11-25 08:53:06,530 WARN L192 SmtUtils]: Spent 182.00 ms on a formula simplification that was a NOOP. DAG size: 124 [2019-11-25 08:53:06,542 INFO L210 LassoAnalysis]: Preferences: [2019-11-25 08:53:06,543 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2019-11-25 08:53:06,543 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-11-25 08:53:06,543 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2019-11-25 08:53:06,543 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2019-11-25 08:53:06,543 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:06,543 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2019-11-25 08:53:06,544 INFO L132 ssoRankerPreferences]: Path of dumped script: [2019-11-25 08:53:06,544 INFO L133 ssoRankerPreferences]: Filename of dumped script: transmitter.04.cil.c_Iteration16_Loop [2019-11-25 08:53:06,544 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2019-11-25 08:53:06,544 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-11-25 08:53:06,566 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,575 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,583 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,586 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,591 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,594 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,599 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,601 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,604 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,606 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,608 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,616 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,622 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,627 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,629 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,631 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,642 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,645 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,651 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,653 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,655 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,657 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,658 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,663 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,667 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,674 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,676 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,679 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,681 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,683 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,688 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,692 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,695 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,699 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,704 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,708 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,710 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,711 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,713 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,714 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,717 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,719 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,723 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,726 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,728 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,729 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,732 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,733 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,738 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:06,743 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,299 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-11-25 08:53:07,300 INFO L404 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-25 08:53:07,310 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-25 08:53:07,311 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:07,317 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-25 08:53:07,317 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_#t~ret11=0} Honda state: {ULTIMATE.start_stop_simulation_#t~ret11=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:07,323 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-25 08:53:07,323 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-11-25 08:53:07,335 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-25 08:53:07,335 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp~1=1, ULTIMATE.start_is_master_triggered_#res=1, ULTIMATE.start_is_master_triggered_~__retres1~0=1} Honda state: {ULTIMATE.start_activate_threads_~tmp~1=1, ULTIMATE.start_is_master_triggered_#res=1, ULTIMATE.start_is_master_triggered_~__retres1~0=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:07,448 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-25 08:53:07,449 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-11-25 08:53:07,458 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-25 08:53:07,458 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~kernel_st~0=3} Honda state: {ULTIMATE.start_start_simulation_~kernel_st~0=3} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:07,473 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-25 08:53:07,473 INFO L160 nArgumentSynthesizer]: Using integer mode. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:07,506 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2019-11-25 08:53:07,506 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-11-25 08:53:07,526 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2019-11-25 08:53:07,528 INFO L210 LassoAnalysis]: Preferences: [2019-11-25 08:53:07,528 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2019-11-25 08:53:07,528 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-11-25 08:53:07,528 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2019-11-25 08:53:07,528 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2019-11-25 08:53:07,528 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:07,528 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2019-11-25 08:53:07,529 INFO L132 ssoRankerPreferences]: Path of dumped script: [2019-11-25 08:53:07,529 INFO L133 ssoRankerPreferences]: Filename of dumped script: transmitter.04.cil.c_Iteration16_Loop [2019-11-25 08:53:07,529 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2019-11-25 08:53:07,529 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-11-25 08:53:07,532 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,542 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,546 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,552 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,556 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,558 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,563 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,564 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,566 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,572 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,574 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,576 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,580 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,582 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,586 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,588 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,593 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,601 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,603 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,614 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,616 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,623 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,625 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,627 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,632 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,637 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,639 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,641 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,643 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,646 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,655 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,660 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,663 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,669 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,675 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,677 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,681 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,683 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,685 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,689 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,695 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,698 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,708 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,711 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,713 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,715 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,718 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,720 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,723 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:07,728 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:08,318 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-11-25 08:53:08,325 INFO L489 LassoAnalysis]: Using template 'affine'. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:08,332 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-25 08:53:08,335 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-25 08:53:08,335 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-25 08:53:08,335 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-25 08:53:08,336 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-25 08:53:08,336 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-25 08:53:08,339 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-25 08:53:08,339 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-25 08:53:08,342 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-25 08:53:08,362 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-25 08:53:08,364 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-25 08:53:08,364 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-25 08:53:08,364 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-25 08:53:08,364 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-25 08:53:08,364 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-25 08:53:08,365 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-25 08:53:08,365 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. Waiting until toolchain timeout for monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:08,367 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-25 08:53:08,384 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-25 08:53:08,386 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-25 08:53:08,386 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-25 08:53:08,386 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-25 08:53:08,386 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-25 08:53:08,387 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-25 08:53:08,388 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-25 08:53:08,388 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. Waiting until toolchain timeout for monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:08,391 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-25 08:53:08,408 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-25 08:53:08,410 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-25 08:53:08,410 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-25 08:53:08,410 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-25 08:53:08,410 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2019-11-25 08:53:08,410 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-25 08:53:08,415 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2019-11-25 08:53:08,415 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. Waiting until toolchain timeout for monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:08,426 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:08,440 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-25 08:53:08,442 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-25 08:53:08,442 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-25 08:53:08,442 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-25 08:53:08,442 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-25 08:53:08,443 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-25 08:53:08,444 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-25 08:53:08,444 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-25 08:53:08,446 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:08,456 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-25 08:53:08,458 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-25 08:53:08,458 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-25 08:53:08,458 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-25 08:53:08,458 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-25 08:53:08,458 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-25 08:53:08,460 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-25 08:53:08,460 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-25 08:53:08,463 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2019-11-25 08:53:08,502 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2019-11-25 08:53:08,502 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-25 08:53:08,571 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2019-11-25 08:53:08,571 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2019-11-25 08:53:08,572 INFO L510 LassoAnalysis]: Proved termination. [2019-11-25 08:53:08,572 INFO L512 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_3~0) = -1*~E_3~0 + 1 Supporting invariants [] [2019-11-25 08:53:08,575 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed Waiting until toolchain timeout for monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:08,642 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:08,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:08,676 INFO L255 TraceCheckSpWp]: Trace formula consists of 150 conjuncts, 2 conjunts are in the unsatisfiable core [2019-11-25 08:53:08,679 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-25 08:53:08,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:08,715 INFO L255 TraceCheckSpWp]: Trace formula consists of 158 conjuncts, 4 conjunts are in the unsatisfiable core [2019-11-25 08:53:08,719 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-25 08:53:08,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:08,779 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2019-11-25 08:53:08,780 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 1243 states and 1697 transitions. cyclomatic complexity: 458 Second operand 5 states. [2019-11-25 08:53:08,987 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 1243 states and 1697 transitions. cyclomatic complexity: 458. Second operand 5 states. Result 4504 states and 6194 transitions. Complement of second has 5 states. [2019-11-25 08:53:08,988 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2019-11-25 08:53:08,988 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2019-11-25 08:53:08,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 920 transitions. [2019-11-25 08:53:08,992 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 920 transitions. Stem has 56 letters. Loop has 75 letters. [2019-11-25 08:53:08,999 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-11-25 08:53:08,999 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 920 transitions. Stem has 131 letters. Loop has 75 letters. [2019-11-25 08:53:09,000 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-11-25 08:53:09,000 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 920 transitions. Stem has 56 letters. Loop has 150 letters. [2019-11-25 08:53:09,002 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-11-25 08:53:09,002 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4504 states and 6194 transitions. [2019-11-25 08:53:09,030 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 3361 [2019-11-25 08:53:09,062 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4504 states to 4500 states and 6190 transitions. [2019-11-25 08:53:09,062 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3452 [2019-11-25 08:53:09,067 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3465 [2019-11-25 08:53:09,067 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4500 states and 6190 transitions. [2019-11-25 08:53:09,067 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-11-25 08:53:09,067 INFO L688 BuchiCegarLoop]: Abstraction has 4500 states and 6190 transitions. [2019-11-25 08:53:09,071 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4500 states and 6190 transitions. [2019-11-25 08:53:09,133 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4500 to 3302. [2019-11-25 08:53:09,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3302 states. [2019-11-25 08:53:09,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3302 states to 3302 states and 4559 transitions. [2019-11-25 08:53:09,141 INFO L711 BuchiCegarLoop]: Abstraction has 3302 states and 4559 transitions. [2019-11-25 08:53:09,141 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:53:09,142 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:53:09,142 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:53:09,142 INFO L87 Difference]: Start difference. First operand 3302 states and 4559 transitions. Second operand 3 states. [2019-11-25 08:53:09,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:53:09,227 INFO L93 Difference]: Finished difference Result 5901 states and 7989 transitions. [2019-11-25 08:53:09,227 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:53:09,227 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5901 states and 7989 transitions. [2019-11-25 08:53:09,259 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3952 [2019-11-25 08:53:09,283 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5901 states to 5901 states and 7989 transitions. [2019-11-25 08:53:09,283 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4047 [2019-11-25 08:53:09,287 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4047 [2019-11-25 08:53:09,287 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5901 states and 7989 transitions. [2019-11-25 08:53:09,288 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-11-25 08:53:09,288 INFO L688 BuchiCegarLoop]: Abstraction has 5901 states and 7989 transitions. [2019-11-25 08:53:09,293 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5901 states and 7989 transitions. [2019-11-25 08:53:09,369 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5901 to 5523. [2019-11-25 08:53:09,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5523 states. [2019-11-25 08:53:09,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5523 states to 5523 states and 7521 transitions. [2019-11-25 08:53:09,382 INFO L711 BuchiCegarLoop]: Abstraction has 5523 states and 7521 transitions. [2019-11-25 08:53:09,382 INFO L591 BuchiCegarLoop]: Abstraction has 5523 states and 7521 transitions. [2019-11-25 08:53:09,382 INFO L424 BuchiCegarLoop]: ======== Iteration 17============ [2019-11-25 08:53:09,383 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5523 states and 7521 transitions. [2019-11-25 08:53:09,400 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3700 [2019-11-25 08:53:09,401 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:53:09,401 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:53:09,402 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:09,402 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:09,402 INFO L794 eck$LassoCheckResult]: Stem: 49781#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 49442#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 49443#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 49859#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 49860#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49722#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49723#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49775#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49446#L351-1 assume !(0 == ~M_E~0); 49447#L492-1 assume !(0 == ~T1_E~0); 49949#L497-1 assume !(0 == ~T2_E~0); 49950#L502-1 assume !(0 == ~T3_E~0); 50004#L507-1 assume !(0 == ~T4_E~0); 49773#L512-1 assume !(0 == ~E_1~0); 49774#L517-1 assume !(0 == ~E_2~0); 49808#L522-1 assume !(0 == ~E_3~0); 49481#L527-1 assume !(0 == ~E_4~0); 49482#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 49544#L228 assume !(1 == ~m_pc~0); 49563#L228-2 is_master_triggered_~__retres1~0 := 0; 50125#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 49564#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 49565#L605 assume !(0 != activate_threads_~tmp~1); 49850#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 49855#L247 assume !(1 == ~t1_pc~0); 49880#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 49881#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 49712#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 49713#L613 assume !(0 != activate_threads_~tmp___0~0); 50169#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 49930#L266 assume !(1 == ~t2_pc~0); 49931#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 49933#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 49934#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 49418#L621 assume !(0 != activate_threads_~tmp___1~0); 49419#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 49430#L285 assume !(1 == ~t3_pc~0); 49416#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 49417#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 49435#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 49768#L629 assume !(0 != activate_threads_~tmp___2~0); 49935#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 49936#L304 assume !(1 == ~t4_pc~0); 49960#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 49961#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 50000#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 49532#L637 assume !(0 != activate_threads_~tmp___3~0); 49533#L637-2 assume !(1 == ~M_E~0); 49534#L545-1 assume !(1 == ~T1_E~0); 49767#L550-1 assume !(1 == ~T2_E~0); 49436#L555-1 assume !(1 == ~T3_E~0); 49437#L560-1 assume !(1 == ~T4_E~0); 49538#L565-1 assume !(1 == ~E_1~0); 49543#L570-1 assume !(1 == ~E_2~0); 50042#L575-1 assume !(1 == ~E_3~0); 50107#L580-1 assume 1 == ~E_4~0;~E_4~0 := 2; 50170#L766-1 [2019-11-25 08:53:09,403 INFO L796 eck$LassoCheckResult]: Loop: 50170#L766-1 assume !false; 54277#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 54092#L467 assume !false; 54093#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 53971#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 53970#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 53969#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 53968#L406 assume 0 != eval_~tmp~0; 53227#L406-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 53224#L414 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1; 53225#L49 assume !(0 == ~m_pc~0); 53957#L52 assume 1 == ~m_pc~0; 53947#L53 assume !false; 50043#L69 ~m_pc~0 := 1;~m_st~0 := 2; 49551#L411 assume !(0 == ~t1_st~0); 49502#L425 assume !(0 == ~t2_st~0); 53023#L439 assume !(0 == ~t3_st~0); 52915#L453 assume !(0 == ~t4_st~0); 54101#L467 assume !false; 53977#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 53978#L364 assume !(0 == ~m_st~0); 49897#L368 assume !(0 == ~t1_st~0); 49568#L372 assume !(0 == ~t2_st~0); 49570#L376 assume !(0 == ~t3_st~0); 49693#L380 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 49694#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 54521#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 54516#L406 assume !(0 != eval_~tmp~0); 54517#L482 start_simulation_~kernel_st~0 := 2; 49866#L324-1 start_simulation_~kernel_st~0 := 3; 49867#L492-2 assume !(0 == ~M_E~0); 50144#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 50145#L497-3 assume !(0 == ~T2_E~0); 54747#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54746#L507-3 assume !(0 == ~T4_E~0); 49671#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 49672#L517-3 assume !(0 == ~E_2~0); 49887#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 49511#L527-3 assume !(0 == ~E_4~0); 49512#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 54744#L228-15 assume !(1 == ~m_pc~0); 50081#L228-17 is_master_triggered_~__retres1~0 := 0; 50082#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 49598#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 49599#L605-15 assume !(0 != activate_threads_~tmp~1); 49729#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 49753#L247-15 assume !(1 == ~t1_pc~0); 49744#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 49745#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 49838#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 50035#L613-15 assume !(0 != activate_threads_~tmp___0~0); 50099#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 50100#L266-15 assume !(1 == ~t2_pc~0); 50058#L266-17 is_transmit2_triggered_~__retres1~2 := 0; 50160#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 50065#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 49844#L621-15 assume !(0 != activate_threads_~tmp___1~0); 49845#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 49853#L285-15 assume !(1 == ~t3_pc~0); 49895#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 49466#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 49467#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 49805#L629-15 assume !(0 != activate_threads_~tmp___2~0); 50163#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 49919#L304-15 assume 1 == ~t4_pc~0; 49920#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 49928#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 49973#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 49412#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 49413#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 49428#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49665#L550-3 assume !(1 == ~T2_E~0); 49813#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49487#L560-3 assume !(1 == ~T4_E~0); 49488#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 49545#L570-3 assume !(1 == ~E_2~0); 50067#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50117#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49945#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 49946#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 50024#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 54634#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 54587#L785 assume !(0 == start_simulation_~tmp~3); 54583#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 50037#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 49714#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 49715#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 54295#L740 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 54291#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 54288#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 54287#L798 assume !(0 != start_simulation_~tmp___0~1); 50170#L766-1 [2019-11-25 08:53:09,403 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:09,403 INFO L82 PathProgramCache]: Analyzing trace with hash -1463119961, now seen corresponding path program 1 times [2019-11-25 08:53:09,403 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:09,404 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [424641688] [2019-11-25 08:53:09,404 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:09,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:09,432 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:09,432 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [424641688] [2019-11-25 08:53:09,433 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:09,433 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-11-25 08:53:09,433 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1733080539] [2019-11-25 08:53:09,433 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:53:09,433 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:09,433 INFO L82 PathProgramCache]: Analyzing trace with hash 64244943, now seen corresponding path program 1 times [2019-11-25 08:53:09,433 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:09,434 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1447944845] [2019-11-25 08:53:09,434 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:09,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:09,458 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:09,459 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1447944845] [2019-11-25 08:53:09,459 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:09,459 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:53:09,459 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1375599383] [2019-11-25 08:53:09,460 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:53:09,460 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:53:09,460 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:53:09,460 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:53:09,460 INFO L87 Difference]: Start difference. First operand 5523 states and 7521 transitions. cyclomatic complexity: 2010 Second operand 3 states. [2019-11-25 08:53:09,512 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:53:09,512 INFO L93 Difference]: Finished difference Result 5523 states and 7338 transitions. [2019-11-25 08:53:09,512 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:53:09,513 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5523 states and 7338 transitions. [2019-11-25 08:53:09,537 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3700 [2019-11-25 08:53:09,554 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5523 states to 5523 states and 7338 transitions. [2019-11-25 08:53:09,554 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3795 [2019-11-25 08:53:09,558 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3795 [2019-11-25 08:53:09,558 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5523 states and 7338 transitions. [2019-11-25 08:53:09,559 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-11-25 08:53:09,559 INFO L688 BuchiCegarLoop]: Abstraction has 5523 states and 7338 transitions. [2019-11-25 08:53:09,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5523 states and 7338 transitions. [2019-11-25 08:53:09,618 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5523 to 5523. [2019-11-25 08:53:09,619 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5523 states. [2019-11-25 08:53:09,631 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5523 states to 5523 states and 7338 transitions. [2019-11-25 08:53:09,631 INFO L711 BuchiCegarLoop]: Abstraction has 5523 states and 7338 transitions. [2019-11-25 08:53:09,631 INFO L591 BuchiCegarLoop]: Abstraction has 5523 states and 7338 transitions. [2019-11-25 08:53:09,631 INFO L424 BuchiCegarLoop]: ======== Iteration 18============ [2019-11-25 08:53:09,632 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5523 states and 7338 transitions. [2019-11-25 08:53:09,649 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3700 [2019-11-25 08:53:09,650 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:53:09,650 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:53:09,651 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:09,651 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:09,651 INFO L794 eck$LassoCheckResult]: Stem: 60843#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 60498#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 60499#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 60924#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 60925#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 60782#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 60783#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60837#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60502#L351-1 assume !(0 == ~M_E~0); 60503#L492-1 assume !(0 == ~T1_E~0); 61024#L497-1 assume !(0 == ~T2_E~0); 61025#L502-1 assume !(0 == ~T3_E~0); 61078#L507-1 assume !(0 == ~T4_E~0); 60835#L512-1 assume !(0 == ~E_1~0); 60836#L517-1 assume !(0 == ~E_2~0); 60871#L522-1 assume !(0 == ~E_3~0); 60541#L527-1 assume !(0 == ~E_4~0); 60542#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 60603#L228 assume !(1 == ~m_pc~0); 60622#L228-2 is_master_triggered_~__retres1~0 := 0; 61203#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 60623#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 60624#L605 assume !(0 != activate_threads_~tmp~1); 60911#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 60919#L247 assume !(1 == ~t1_pc~0); 60947#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 60948#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 60772#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 60773#L613 assume !(0 != activate_threads_~tmp___0~0); 61271#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 61001#L266 assume !(1 == ~t2_pc~0); 61002#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 61004#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 61005#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 60475#L621 assume !(0 != activate_threads_~tmp___1~0); 60476#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 60484#L285 assume !(1 == ~t3_pc~0); 60469#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 60470#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 60489#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 60834#L629 assume !(0 != activate_threads_~tmp___2~0); 61006#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 61007#L304 assume !(1 == ~t4_pc~0); 61036#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 61037#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 61074#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 60591#L637 assume !(0 != activate_threads_~tmp___3~0); 60592#L637-2 assume !(1 == ~M_E~0); 60593#L545-1 assume !(1 == ~T1_E~0); 60829#L550-1 assume !(1 == ~T2_E~0); 60494#L555-1 assume !(1 == ~T3_E~0); 60495#L560-1 assume !(1 == ~T4_E~0); 60597#L565-1 assume !(1 == ~E_1~0); 60602#L570-1 assume !(1 == ~E_2~0); 61112#L575-1 assume !(1 == ~E_3~0); 61187#L580-1 assume !(1 == ~E_4~0); 61272#L766-1 assume !false; 61806#L767 [2019-11-25 08:53:09,652 INFO L796 eck$LassoCheckResult]: Loop: 61806#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 65427#L467 assume !false; 65425#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 62924#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 62925#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 63805#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 63804#L406 assume 0 != eval_~tmp~0; 62906#L406-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 62907#L414 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1; 62900#L49 assume !(0 == ~m_pc~0); 62902#L52 assume 1 == ~m_pc~0; 62903#L53 assume !false; 62911#L69 ~m_pc~0 := 1;~m_st~0 := 2; 62910#L411 assume !(0 == ~t1_st~0); 64275#L425 assume !(0 == ~t2_st~0); 64801#L439 assume !(0 == ~t3_st~0); 61027#L453 assume !(0 == ~t4_st~0); 60617#L467 assume !false; 60949#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 65252#L364 assume !(0 == ~m_st~0); 60961#L368 assume !(0 == ~t1_st~0); 60627#L372 assume !(0 == ~t2_st~0); 60629#L376 assume !(0 == ~t3_st~0); 60752#L380 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 60753#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 65975#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 65974#L406 assume !(0 != eval_~tmp~0); 61136#L482 start_simulation_~kernel_st~0 := 2; 60930#L324-1 start_simulation_~kernel_st~0 := 3; 60931#L492-2 assume !(0 == ~M_E~0); 61236#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 60974#L497-3 assume !(0 == ~T2_E~0); 60975#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 61066#L507-3 assume !(0 == ~T4_E~0); 60731#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 60732#L517-3 assume !(0 == ~E_2~0); 60886#L522-3 assume !(0 == ~E_3~0); 60570#L527-3 assume !(0 == ~E_4~0); 60571#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 60606#L228-15 assume 1 == ~m_pc~0; 61186#L229-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 65765#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 65763#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 65761#L605-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 65760#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 65758#L247-15 assume !(1 == ~t1_pc~0); 65757#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 65756#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 65754#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 65752#L613-15 assume !(0 != activate_threads_~tmp___0~0); 65750#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 65695#L266-15 assume !(1 == ~t2_pc~0); 65692#L266-17 is_transmit2_triggered_~__retres1~2 := 0; 65690#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 65687#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 65686#L621-15 assume !(0 != activate_threads_~tmp___1~0); 65685#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 65682#L285-15 assume !(1 == ~t3_pc~0); 65678#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 65675#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 65672#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 65669#L629-15 assume !(0 != activate_threads_~tmp___2~0); 65666#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 65664#L304-15 assume !(1 == ~t4_pc~0); 65661#L304-17 is_transmit4_triggered_~__retres1~4 := 0; 65659#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 65657#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 65654#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 65650#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 65647#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 65644#L550-3 assume !(1 == ~T2_E~0); 65636#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 65603#L560-3 assume !(1 == ~T4_E~0); 65599#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 65595#L570-3 assume !(1 == ~E_2~0); 65592#L575-3 assume !(1 == ~E_3~0); 65575#L580-3 assume !(1 == ~E_4~0); 65547#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 65478#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 65473#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 65471#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 65468#L785 assume !(0 == start_simulation_~tmp~3); 65463#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 65461#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 65420#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 65452#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 65449#L740 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 65446#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 65444#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 65442#L798 assume !(0 != start_simulation_~tmp___0~1); 65439#L766-1 assume !false; 61806#L767 [2019-11-25 08:53:09,652 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:09,652 INFO L82 PathProgramCache]: Analyzing trace with hash 1887921798, now seen corresponding path program 1 times [2019-11-25 08:53:09,652 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:09,653 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1121070866] [2019-11-25 08:53:09,653 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:09,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:09,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:09,669 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:53:09,669 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:09,669 INFO L82 PathProgramCache]: Analyzing trace with hash -474259599, now seen corresponding path program 1 times [2019-11-25 08:53:09,670 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:09,670 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [941825229] [2019-11-25 08:53:09,670 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:09,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:09,718 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-11-25 08:53:09,718 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [941825229] [2019-11-25 08:53:09,718 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:09,718 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-25 08:53:09,718 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2083615300] [2019-11-25 08:53:09,719 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:53:09,719 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:53:09,719 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-25 08:53:09,719 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-25 08:53:09,719 INFO L87 Difference]: Start difference. First operand 5523 states and 7338 transitions. cyclomatic complexity: 1827 Second operand 5 states. [2019-11-25 08:53:09,839 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:53:09,840 INFO L93 Difference]: Finished difference Result 7970 states and 10578 transitions. [2019-11-25 08:53:09,840 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-25 08:53:09,840 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7970 states and 10578 transitions. [2019-11-25 08:53:09,873 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5360 [2019-11-25 08:53:09,895 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7970 states to 7970 states and 10578 transitions. [2019-11-25 08:53:09,896 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5471 [2019-11-25 08:53:09,901 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5471 [2019-11-25 08:53:09,901 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7970 states and 10578 transitions. [2019-11-25 08:53:09,901 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-11-25 08:53:09,901 INFO L688 BuchiCegarLoop]: Abstraction has 7970 states and 10578 transitions. [2019-11-25 08:53:09,908 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7970 states and 10578 transitions. [2019-11-25 08:53:09,971 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7970 to 5559. [2019-11-25 08:53:09,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5559 states. [2019-11-25 08:53:09,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5559 states to 5559 states and 7293 transitions. [2019-11-25 08:53:09,983 INFO L711 BuchiCegarLoop]: Abstraction has 5559 states and 7293 transitions. [2019-11-25 08:53:09,983 INFO L591 BuchiCegarLoop]: Abstraction has 5559 states and 7293 transitions. [2019-11-25 08:53:09,983 INFO L424 BuchiCegarLoop]: ======== Iteration 19============ [2019-11-25 08:53:09,983 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5559 states and 7293 transitions. [2019-11-25 08:53:09,999 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3724 [2019-11-25 08:53:10,000 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:53:10,000 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:53:10,001 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:10,001 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:10,001 INFO L794 eck$LassoCheckResult]: Stem: 74352#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 74004#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 74005#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 74439#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 74440#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 74296#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 74297#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 74346#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 74008#L351-1 assume !(0 == ~M_E~0); 74009#L492-1 assume !(0 == ~T1_E~0); 74539#L497-1 assume !(0 == ~T2_E~0); 74540#L502-1 assume !(0 == ~T3_E~0); 74610#L507-1 assume !(0 == ~T4_E~0); 74344#L512-1 assume !(0 == ~E_1~0); 74345#L517-1 assume !(0 == ~E_2~0); 74382#L522-1 assume !(0 == ~E_3~0); 74048#L527-1 assume !(0 == ~E_4~0); 74049#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 74115#L228 assume !(1 == ~m_pc~0); 74133#L228-2 is_master_triggered_~__retres1~0 := 0; 74744#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 74134#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 74135#L605 assume !(0 != activate_threads_~tmp~1); 74428#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 74433#L247 assume !(1 == ~t1_pc~0); 74464#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 74465#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 74286#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 74287#L613 assume !(0 != activate_threads_~tmp___0~0); 74818#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 74519#L266 assume !(1 == ~t2_pc~0); 74520#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 74522#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 74523#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 73979#L621 assume !(0 != activate_threads_~tmp___1~0); 73980#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 73992#L285 assume !(1 == ~t3_pc~0); 73977#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 73978#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 73993#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 74339#L629 assume !(0 != activate_threads_~tmp___2~0); 74524#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 74525#L304 assume !(1 == ~t4_pc~0); 74559#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 74560#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 74605#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 74098#L637 assume !(0 != activate_threads_~tmp___3~0); 74099#L637-2 assume !(1 == ~M_E~0); 74104#L545-1 assume !(1 == ~T1_E~0); 74338#L550-1 assume !(1 == ~T2_E~0); 73998#L555-1 assume !(1 == ~T3_E~0); 73999#L560-1 assume !(1 == ~T4_E~0); 74109#L565-1 assume !(1 == ~E_1~0); 74114#L570-1 assume !(1 == ~E_2~0); 74650#L575-1 assume !(1 == ~E_3~0); 74722#L580-1 assume !(1 == ~E_4~0); 74819#L766-1 assume !false; 74992#L767 [2019-11-25 08:53:10,002 INFO L796 eck$LassoCheckResult]: Loop: 74992#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 77778#L467 assume !false; 77776#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 77774#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 77516#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 77764#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 77760#L406 assume 0 != eval_~tmp~0; 77212#L406-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 77210#L414 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1; 77211#L49 assume !(0 == ~m_pc~0); 77276#L52 assume 1 == ~m_pc~0; 77272#L53 assume !false; 77270#L69 ~m_pc~0 := 1;~m_st~0 := 2; 77266#L411 assume !(0 == ~t1_st~0); 77263#L425 assume !(0 == ~t2_st~0); 77262#L439 assume !(0 == ~t3_st~0); 77533#L453 assume !(0 == ~t4_st~0); 77526#L467 assume !false; 77520#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 77515#L364 assume !(0 == ~m_st~0); 77507#L368 assume !(0 == ~t1_st~0); 77508#L372 assume !(0 == ~t2_st~0); 77509#L376 assume !(0 == ~t3_st~0); 77506#L380 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 77501#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 77496#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 77491#L406 assume !(0 != eval_~tmp~0); 77492#L482 start_simulation_~kernel_st~0 := 2; 78018#L324-1 start_simulation_~kernel_st~0 := 3; 78017#L492-2 assume !(0 == ~M_E~0); 78016#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 78015#L497-3 assume !(0 == ~T2_E~0); 78014#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 78013#L507-3 assume !(0 == ~T4_E~0); 78012#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 78011#L517-3 assume !(0 == ~E_2~0); 78010#L522-3 assume !(0 == ~E_3~0); 78009#L527-3 assume !(0 == ~E_4~0); 76368#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 78008#L228-15 assume !(1 == ~m_pc~0); 78007#L228-17 is_master_triggered_~__retres1~0 := 0; 78102#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 78097#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 78092#L605-15 assume !(0 != activate_threads_~tmp~1); 78003#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 78084#L247-15 assume !(1 == ~t1_pc~0); 78081#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 78077#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 78072#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 78063#L613-15 assume !(0 != activate_threads_~tmp___0~0); 78058#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 78053#L266-15 assume !(1 == ~t2_pc~0); 78047#L266-17 is_transmit2_triggered_~__retres1~2 := 0; 78044#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 78041#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 78038#L621-15 assume !(0 != activate_threads_~tmp___1~0); 78035#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 76306#L285-15 assume !(1 == ~t3_pc~0); 76307#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 77750#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 77748#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 77745#L629-15 assume !(0 != activate_threads_~tmp___2~0); 77743#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 77740#L304-15 assume !(1 == ~t4_pc~0); 77737#L304-17 is_transmit4_triggered_~__retres1~4 := 0; 77734#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 77730#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 77725#L637-15 assume !(0 != activate_threads_~tmp___3~0); 77721#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 77717#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 77713#L550-3 assume !(1 == ~T2_E~0); 77708#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77702#L560-3 assume !(1 == ~T4_E~0); 77697#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 77693#L570-3 assume !(1 == ~E_2~0); 77687#L575-3 assume !(1 == ~E_3~0); 77668#L580-3 assume !(1 == ~E_4~0); 76234#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 77657#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 77658#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 77888#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 77884#L785 assume !(0 == start_simulation_~tmp~3); 77881#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 77878#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 77627#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 77873#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 77870#L740 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 77867#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 77865#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 77863#L798 assume !(0 != start_simulation_~tmp___0~1); 77861#L766-1 assume !false; 74992#L767 [2019-11-25 08:53:10,002 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:10,003 INFO L82 PathProgramCache]: Analyzing trace with hash 1887921798, now seen corresponding path program 2 times [2019-11-25 08:53:10,003 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:10,003 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [643742107] [2019-11-25 08:53:10,003 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:10,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:10,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:10,030 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:53:10,030 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:10,030 INFO L82 PathProgramCache]: Analyzing trace with hash 629320716, now seen corresponding path program 1 times [2019-11-25 08:53:10,030 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:10,031 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1902315718] [2019-11-25 08:53:10,031 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:10,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:10,052 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:10,052 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1902315718] [2019-11-25 08:53:10,052 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:10,053 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:53:10,053 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1249257654] [2019-11-25 08:53:10,053 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:53:10,053 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:53:10,053 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:53:10,054 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:53:10,054 INFO L87 Difference]: Start difference. First operand 5559 states and 7293 transitions. cyclomatic complexity: 1746 Second operand 3 states. [2019-11-25 08:53:10,147 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:53:10,148 INFO L93 Difference]: Finished difference Result 7030 states and 9084 transitions. [2019-11-25 08:53:10,148 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:53:10,148 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7030 states and 9084 transitions. [2019-11-25 08:53:10,173 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4084 [2019-11-25 08:53:10,192 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7030 states to 7030 states and 9084 transitions. [2019-11-25 08:53:10,193 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4860 [2019-11-25 08:53:10,197 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4860 [2019-11-25 08:53:10,197 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7030 states and 9084 transitions. [2019-11-25 08:53:10,200 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-11-25 08:53:10,200 INFO L688 BuchiCegarLoop]: Abstraction has 7030 states and 9084 transitions. [2019-11-25 08:53:10,207 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7030 states and 9084 transitions. [2019-11-25 08:53:10,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7030 to 6604. [2019-11-25 08:53:10,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6604 states. [2019-11-25 08:53:10,279 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6604 states to 6604 states and 8592 transitions. [2019-11-25 08:53:10,280 INFO L711 BuchiCegarLoop]: Abstraction has 6604 states and 8592 transitions. [2019-11-25 08:53:10,280 INFO L591 BuchiCegarLoop]: Abstraction has 6604 states and 8592 transitions. [2019-11-25 08:53:10,280 INFO L424 BuchiCegarLoop]: ======== Iteration 20============ [2019-11-25 08:53:10,280 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6604 states and 8592 transitions. [2019-11-25 08:53:10,297 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4084 [2019-11-25 08:53:10,298 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:53:10,298 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:53:10,299 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:10,299 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:10,299 INFO L794 eck$LassoCheckResult]: Stem: 86951#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 86604#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 86605#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 87038#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 87039#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 86888#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 86889#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 86945#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 86610#L351-1 assume !(0 == ~M_E~0); 86611#L492-1 assume !(0 == ~T1_E~0); 87133#L497-1 assume !(0 == ~T2_E~0); 87134#L502-1 assume !(0 == ~T3_E~0); 87192#L507-1 assume !(0 == ~T4_E~0); 86943#L512-1 assume !(0 == ~E_1~0); 86944#L517-1 assume !(0 == ~E_2~0); 86978#L522-1 assume !(0 == ~E_3~0); 86643#L527-1 assume !(0 == ~E_4~0); 86644#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 86709#L228 assume 1 == ~m_pc~0; 86724#L229 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 86725#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 87414#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 87413#L605 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 87030#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 87031#L247 assume !(1 == ~t1_pc~0); 87062#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 87063#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 86878#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 86879#L613 assume !(0 != activate_threads_~tmp___0~0); 87380#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 87381#L266 assume !(1 == ~t2_pc~0); 87393#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 87394#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 87304#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 87305#L621 assume !(0 != activate_threads_~tmp___1~0); 86592#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 86593#L285 assume !(1 == ~t3_pc~0); 86572#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 86573#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 86941#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 86942#L629 assume !(0 != activate_threads_~tmp___2~0); 87117#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 87118#L304 assume !(1 == ~t4_pc~0); 87144#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 87145#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 87357#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 87358#L637 assume !(0 != activate_threads_~tmp___3~0); 86697#L637-2 assume !(1 == ~M_E~0); 86698#L545-1 assume !(1 == ~T1_E~0); 87032#L550-1 assume !(1 == ~T2_E~0); 87033#L555-1 assume !(1 == ~T3_E~0); 86701#L560-1 assume !(1 == ~T4_E~0); 86702#L565-1 assume !(1 == ~E_1~0); 87228#L570-1 assume !(1 == ~E_2~0); 87229#L575-1 assume !(1 == ~E_3~0); 87382#L580-1 assume !(1 == ~E_4~0); 87383#L766-1 assume !false; 88723#L767 [2019-11-25 08:53:10,300 INFO L796 eck$LassoCheckResult]: Loop: 88723#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 92787#L467 assume !false; 92786#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 87197#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 87198#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 92745#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 86677#L406 assume 0 != eval_~tmp~0; 86678#L406-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 91408#L414 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1; 91409#L49 assume !(0 == ~m_pc~0); 91807#L52 assume 1 == ~m_pc~0; 91805#L53 assume !false; 91507#L69 ~m_pc~0 := 1;~m_st~0 := 2; 91504#L411 assume !(0 == ~t1_st~0); 91491#L425 assume !(0 == ~t2_st~0); 91486#L439 assume !(0 == ~t3_st~0); 91484#L453 assume !(0 == ~t4_st~0); 91529#L467 assume !false; 91525#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 91524#L364 assume !(0 == ~m_st~0); 91521#L368 assume !(0 == ~t1_st~0); 91522#L372 assume !(0 == ~t2_st~0); 91523#L376 assume !(0 == ~t3_st~0); 91519#L380 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 91520#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 91513#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 91514#L406 assume !(0 != eval_~tmp~0); 87251#L482 start_simulation_~kernel_st~0 := 2; 87042#L324-1 start_simulation_~kernel_st~0 := 3; 87043#L492-2 assume !(0 == ~M_E~0); 87343#L492-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 87089#L497-3 assume !(0 == ~T2_E~0); 87090#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 87175#L507-3 assume !(0 == ~T4_E~0); 86838#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 86839#L517-3 assume !(0 == ~E_2~0); 86993#L522-3 assume !(0 == ~E_3~0); 86673#L527-3 assume !(0 == ~E_4~0); 86674#L532-3 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 86712#L228-15 assume 1 == ~m_pc~0; 86751#L229-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 86752#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 92887#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 92885#L605-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 92883#L605-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 92881#L247-15 assume !(1 == ~t1_pc~0); 92879#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 92877#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 92875#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 92872#L613-15 assume !(0 != activate_threads_~tmp___0~0); 92870#L613-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 92868#L266-15 assume !(1 == ~t2_pc~0); 92865#L266-17 is_transmit2_triggered_~__retres1~2 := 0; 92863#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 92861#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 92859#L621-15 assume !(0 != activate_threads_~tmp___1~0); 92857#L621-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 92855#L285-15 assume !(1 == ~t3_pc~0); 92853#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 92851#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 92849#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 92846#L629-15 assume !(0 != activate_threads_~tmp___2~0); 92844#L629-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 92842#L304-15 assume !(1 == ~t4_pc~0); 92839#L304-17 is_transmit4_triggered_~__retres1~4 := 0; 92837#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 92835#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 92833#L637-15 assume !(0 != activate_threads_~tmp___3~0); 92831#L637-17 assume 1 == ~M_E~0;~M_E~0 := 2; 92829#L545-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 92827#L550-3 assume !(1 == ~T2_E~0); 92825#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 92823#L560-3 assume !(1 == ~T4_E~0); 92821#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 92820#L570-3 assume !(1 == ~E_2~0); 92819#L575-3 assume !(1 == ~E_3~0); 92818#L580-3 assume !(1 == ~E_4~0); 92817#L585-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 92816#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 91633#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 92814#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 92811#L785 assume !(0 == start_simulation_~tmp~3); 92808#L785-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 92806#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 91604#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 92803#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 92801#L740 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 92799#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 92797#L748 start_simulation_#t~ret13 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 92795#L798 assume !(0 != start_simulation_~tmp___0~1); 92793#L766-1 assume !false; 88723#L767 [2019-11-25 08:53:10,300 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:10,300 INFO L82 PathProgramCache]: Analyzing trace with hash -606111613, now seen corresponding path program 1 times [2019-11-25 08:53:10,300 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:10,301 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [857217495] [2019-11-25 08:53:10,301 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:10,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:10,328 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:10,329 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [857217495] [2019-11-25 08:53:10,329 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:10,329 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:53:10,329 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [229059040] [2019-11-25 08:53:10,329 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:53:10,330 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:10,330 INFO L82 PathProgramCache]: Analyzing trace with hash -608273105, now seen corresponding path program 1 times [2019-11-25 08:53:10,330 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:10,330 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1839217083] [2019-11-25 08:53:10,330 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:10,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:10,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:10,365 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:53:11,100 WARN L192 SmtUtils]: Spent 721.00 ms on a formula simplification. DAG size of input: 179 DAG size of output: 159 [2019-11-25 08:53:11,310 WARN L192 SmtUtils]: Spent 205.00 ms on a formula simplification that was a NOOP. DAG size: 129 [2019-11-25 08:53:11,312 INFO L210 LassoAnalysis]: Preferences: [2019-11-25 08:53:11,312 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2019-11-25 08:53:11,312 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-11-25 08:53:11,312 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2019-11-25 08:53:11,313 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2019-11-25 08:53:11,313 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:11,313 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2019-11-25 08:53:11,313 INFO L132 ssoRankerPreferences]: Path of dumped script: [2019-11-25 08:53:11,313 INFO L133 ssoRankerPreferences]: Filename of dumped script: transmitter.04.cil.c_Iteration20_Loop [2019-11-25 08:53:11,313 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2019-11-25 08:53:11,313 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-11-25 08:53:11,316 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,322 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,334 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,340 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,342 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,345 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,350 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,353 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,355 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,357 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,365 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,370 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,372 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,374 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,377 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,382 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,389 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,394 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,396 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,398 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,400 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,403 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,410 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,413 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,415 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,417 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,419 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,424 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,434 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,443 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,445 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,454 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,461 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,468 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,473 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,475 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,480 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,482 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,484 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,486 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,488 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,490 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,492 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,495 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,497 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,502 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,503 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,506 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,510 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,514 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:11,517 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,028 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-11-25 08:53:12,028 INFO L404 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-25 08:53:12,043 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-25 08:53:12,043 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:12,047 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-25 08:53:12,047 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret12=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret12=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:12,070 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-25 08:53:12,070 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-11-25 08:53:12,074 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-25 08:53:12,074 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit2_triggered_#res=0, ULTIMATE.start_activate_threads_~tmp___1~0=0} Honda state: {ULTIMATE.start_is_transmit2_triggered_#res=0, ULTIMATE.start_activate_threads_~tmp___1~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:12,082 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-25 08:53:12,082 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-11-25 08:53:12,090 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-25 08:53:12,090 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___0~0=0, ULTIMATE.start_is_transmit1_triggered_#res=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___0~0=0, ULTIMATE.start_is_transmit1_triggered_#res=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 17 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:12,105 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-25 08:53:12,105 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-11-25 08:53:12,109 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-25 08:53:12,110 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-5} Honda state: {~t4_st~0=-5} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 18 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-25 08:53:12,126 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-25 08:53:12,126 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 18 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:12,130 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-25 08:53:12,130 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t3_pc~0=-8} Honda state: {~t3_pc~0=-8} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 19 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-25 08:53:12,147 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-25 08:53:12,147 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 19 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:12,152 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-25 08:53:12,152 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_4~0=3} Honda state: {~E_4~0=3} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 20 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:12,158 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-25 08:53:12,158 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-11-25 08:53:12,160 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-25 08:53:12,161 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=0} Honda state: {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 21 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:12,166 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-25 08:53:12,166 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-11-25 08:53:12,169 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-25 08:53:12,169 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret8=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret8=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 22 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:12,173 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-25 08:53:12,173 INFO L160 nArgumentSynthesizer]: Using integer mode. [2019-11-25 08:53:12,176 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2019-11-25 08:53:12,176 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_3~0=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_3~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 23 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:12,182 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2019-11-25 08:53:12,182 INFO L160 nArgumentSynthesizer]: Using integer mode. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 24 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-25 08:53:12,198 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2019-11-25 08:53:12,198 INFO L160 nArgumentSynthesizer]: Using integer mode. Waiting until toolchain timeout for monitored process 24 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:12,203 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2019-11-25 08:53:12,205 INFO L210 LassoAnalysis]: Preferences: [2019-11-25 08:53:12,205 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2019-11-25 08:53:12,205 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2019-11-25 08:53:12,205 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2019-11-25 08:53:12,205 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2019-11-25 08:53:12,205 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:12,205 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2019-11-25 08:53:12,205 INFO L132 ssoRankerPreferences]: Path of dumped script: [2019-11-25 08:53:12,206 INFO L133 ssoRankerPreferences]: Filename of dumped script: transmitter.04.cil.c_Iteration20_Loop [2019-11-25 08:53:12,206 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2019-11-25 08:53:12,206 INFO L274 LassoAnalysis]: Starting lasso preprocessing... [2019-11-25 08:53:12,208 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,212 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,213 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,218 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,221 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,223 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,228 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,230 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,232 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,234 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,238 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,240 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,247 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,252 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,258 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,261 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,266 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,269 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,271 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,273 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,276 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,279 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,281 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,283 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,284 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,289 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,290 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,295 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,297 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,301 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,307 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,309 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,315 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,319 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,322 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,327 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,329 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,331 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,333 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,341 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,343 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,362 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,364 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,367 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,370 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,377 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,380 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,384 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,386 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,390 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,394 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2019-11-25 08:53:12,848 INFO L292 LassoAnalysis]: Preprocessing complete. [2019-11-25 08:53:12,848 INFO L489 LassoAnalysis]: Using template 'affine'. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 25 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:12,851 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-25 08:53:12,852 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-25 08:53:12,852 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-25 08:53:12,852 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-25 08:53:12,853 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-25 08:53:12,853 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-25 08:53:12,853 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-25 08:53:12,853 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-25 08:53:12,854 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 26 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:12,858 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-25 08:53:12,859 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-25 08:53:12,859 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-25 08:53:12,859 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-25 08:53:12,859 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-25 08:53:12,859 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-25 08:53:12,859 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-25 08:53:12,860 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-25 08:53:12,860 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 27 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:12,864 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-25 08:53:12,871 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-25 08:53:12,871 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-25 08:53:12,871 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-25 08:53:12,871 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-25 08:53:12,871 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-25 08:53:12,872 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-25 08:53:12,872 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-25 08:53:12,874 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 28 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-25 08:53:12,886 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-25 08:53:12,888 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-25 08:53:12,888 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-25 08:53:12,888 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-25 08:53:12,888 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2019-11-25 08:53:12,888 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-25 08:53:12,889 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2019-11-25 08:53:12,889 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. Waiting until toolchain timeout for monitored process 28 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:12,891 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 29 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-25 08:53:12,897 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-25 08:53:12,898 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-25 08:53:12,898 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-25 08:53:12,898 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-25 08:53:12,899 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2019-11-25 08:53:12,899 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-25 08:53:12,899 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2019-11-25 08:53:12,900 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. Waiting until toolchain timeout for monitored process 29 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:12,901 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 30 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:12,905 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-25 08:53:12,906 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-25 08:53:12,906 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-25 08:53:12,907 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-25 08:53:12,907 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2019-11-25 08:53:12,907 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-25 08:53:12,907 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2019-11-25 08:53:12,907 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-25 08:53:12,909 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 31 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:12,913 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-25 08:53:12,914 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-25 08:53:12,914 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-25 08:53:12,914 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-25 08:53:12,914 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-25 08:53:12,914 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-25 08:53:12,914 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-25 08:53:12,914 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-25 08:53:12,915 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 32 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:12,922 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-25 08:53:12,923 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-25 08:53:12,924 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-25 08:53:12,924 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-25 08:53:12,924 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-25 08:53:12,924 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-25 08:53:12,924 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-25 08:53:12,924 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-25 08:53:12,926 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 33 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-25 08:53:12,934 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-25 08:53:12,935 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-25 08:53:12,935 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-25 08:53:12,936 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-25 08:53:12,936 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-25 08:53:12,936 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-25 08:53:12,936 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-25 08:53:12,936 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. Waiting until toolchain timeout for monitored process 33 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:12,938 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 34 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:12,946 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-25 08:53:12,948 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-25 08:53:12,948 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-25 08:53:12,948 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-25 08:53:12,948 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-25 08:53:12,948 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-25 08:53:12,949 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-25 08:53:12,949 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-25 08:53:12,951 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 35 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-25 08:53:12,955 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false Waiting until toolchain timeout for monitored process 35 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:12,956 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-25 08:53:12,956 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-25 08:53:12,956 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-25 08:53:12,956 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-25 08:53:12,956 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-25 08:53:12,957 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-25 08:53:12,957 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-25 08:53:12,958 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 36 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2019-11-25 08:53:12,970 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-25 08:53:12,972 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-25 08:53:12,972 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-25 08:53:12,972 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-25 08:53:12,972 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-25 08:53:12,973 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-25 08:53:12,974 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-25 08:53:12,974 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. Waiting until toolchain timeout for monitored process 36 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:12,977 INFO L522 LassoAnalysis]: Proving termination failed for this template and these settings. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 37 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:12,985 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2019-11-25 08:53:12,987 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2019-11-25 08:53:12,987 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2019-11-25 08:53:12,987 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2019-11-25 08:53:12,987 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2019-11-25 08:53:12,987 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2019-11-25 08:53:12,988 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2019-11-25 08:53:12,988 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2019-11-25 08:53:12,989 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2019-11-25 08:53:12,991 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2019-11-25 08:53:12,991 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/z3 Starting monitored process 38 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:53:12,994 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2019-11-25 08:53:12,994 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2019-11-25 08:53:12,994 INFO L510 LassoAnalysis]: Proved termination. [2019-11-25 08:53:12,994 INFO L512 LassoAnalysis]: Termination argument consisting of: Ranking function f(~T1_E~0) = -1*~T1_E~0 + 1 Supporting invariants [] [2019-11-25 08:53:12,995 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2019-11-25 08:53:13,005 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:13,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:13,035 INFO L255 TraceCheckSpWp]: Trace formula consists of 155 conjuncts, 2 conjunts are in the unsatisfiable core [2019-11-25 08:53:13,036 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-25 08:53:13,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:13,078 INFO L255 TraceCheckSpWp]: Trace formula consists of 175 conjuncts, 4 conjunts are in the unsatisfiable core [2019-11-25 08:53:13,086 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-25 08:53:13,120 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-11-25 08:53:13,120 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2019-11-25 08:53:13,121 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 6604 states and 8592 transitions. cyclomatic complexity: 2012 Second operand 5 states. [2019-11-25 08:53:13,209 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 6604 states and 8592 transitions. cyclomatic complexity: 2012. Second operand 5 states. Result 13227 states and 17220 transitions. Complement of second has 4 states. [2019-11-25 08:53:13,210 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2019-11-25 08:53:13,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2019-11-25 08:53:13,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 507 transitions. [2019-11-25 08:53:13,212 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 507 transitions. Stem has 57 letters. Loop has 91 letters. [2019-11-25 08:53:13,213 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-11-25 08:53:13,213 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 507 transitions. Stem has 148 letters. Loop has 91 letters. [2019-11-25 08:53:13,214 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-11-25 08:53:13,214 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 507 transitions. Stem has 57 letters. Loop has 182 letters. [2019-11-25 08:53:13,215 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2019-11-25 08:53:13,215 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13227 states and 17220 transitions. [2019-11-25 08:53:13,261 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4084 [2019-11-25 08:53:13,300 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13227 states to 13227 states and 17220 transitions. [2019-11-25 08:53:13,300 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4597 [2019-11-25 08:53:13,303 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4639 [2019-11-25 08:53:13,303 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13227 states and 17220 transitions. [2019-11-25 08:53:13,308 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-11-25 08:53:13,308 INFO L688 BuchiCegarLoop]: Abstraction has 13227 states and 17220 transitions. [2019-11-25 08:53:13,318 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13227 states and 17220 transitions. [2019-11-25 08:53:13,421 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13227 to 13185. [2019-11-25 08:53:13,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13185 states. [2019-11-25 08:53:13,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13185 states to 13185 states and 17138 transitions. [2019-11-25 08:53:13,450 INFO L711 BuchiCegarLoop]: Abstraction has 13185 states and 17138 transitions. [2019-11-25 08:53:13,450 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:53:13,450 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:53:13,450 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:53:13,450 INFO L87 Difference]: Start difference. First operand 13185 states and 17138 transitions. Second operand 3 states. [2019-11-25 08:53:13,514 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:53:13,514 INFO L93 Difference]: Finished difference Result 13091 states and 16902 transitions. [2019-11-25 08:53:13,514 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:53:13,514 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13091 states and 16902 transitions. [2019-11-25 08:53:13,559 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4084 [2019-11-25 08:53:13,595 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13091 states to 13091 states and 16902 transitions. [2019-11-25 08:53:13,595 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4536 [2019-11-25 08:53:13,599 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4536 [2019-11-25 08:53:13,599 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13091 states and 16902 transitions. [2019-11-25 08:53:13,599 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-11-25 08:53:13,600 INFO L688 BuchiCegarLoop]: Abstraction has 13091 states and 16902 transitions. [2019-11-25 08:53:13,607 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13091 states and 16902 transitions. [2019-11-25 08:53:13,699 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13091 to 13043. [2019-11-25 08:53:13,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13043 states. [2019-11-25 08:53:13,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13043 states to 13043 states and 16854 transitions. [2019-11-25 08:53:13,722 INFO L711 BuchiCegarLoop]: Abstraction has 13043 states and 16854 transitions. [2019-11-25 08:53:13,722 INFO L591 BuchiCegarLoop]: Abstraction has 13043 states and 16854 transitions. [2019-11-25 08:53:13,722 INFO L424 BuchiCegarLoop]: ======== Iteration 21============ [2019-11-25 08:53:13,722 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13043 states and 16854 transitions. [2019-11-25 08:53:13,750 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4084 [2019-11-25 08:53:13,750 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:53:13,750 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:53:13,751 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:13,751 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:13,752 INFO L794 eck$LassoCheckResult]: Stem: 133517#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 133170#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 133171#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 133594#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 133595#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 133451#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 133452#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 133509#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 133176#L351-1 assume !(0 == ~M_E~0); 133177#L492-1 assume !(0 == ~T1_E~0); 133691#L497-1 assume !(0 == ~T2_E~0); 133692#L502-1 assume !(0 == ~T3_E~0); 133747#L507-1 assume !(0 == ~T4_E~0); 133507#L512-1 assume !(0 == ~E_1~0); 133508#L517-1 assume !(0 == ~E_2~0); 133545#L522-1 assume !(0 == ~E_3~0); 133212#L527-1 assume !(0 == ~E_4~0); 133213#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 133274#L228 assume !(1 == ~m_pc~0); 133893#L228-2 is_master_triggered_~__retres1~0 := 0; 133854#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 133289#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 133290#L605 assume !(0 != activate_threads_~tmp~1); 133583#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 133593#L247 assume !(1 == ~t1_pc~0); 133618#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 133619#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 133441#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 133442#L613 assume !(0 != activate_threads_~tmp___0~0); 133914#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 133669#L266 assume !(1 == ~t2_pc~0); 133670#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 133672#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 133673#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 133146#L621 assume !(0 != activate_threads_~tmp___1~0); 133147#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 133158#L285 assume !(1 == ~t3_pc~0); 133144#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 133145#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 133163#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 133502#L629 assume !(0 != activate_threads_~tmp___2~0); 133674#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 133675#L304 assume !(1 == ~t4_pc~0); 133705#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 133706#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 133743#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 133263#L637 assume !(0 != activate_threads_~tmp___3~0); 133264#L637-2 assume !(1 == ~M_E~0); 133265#L545-1 assume !(1 == ~T1_E~0); 133501#L550-1 assume !(1 == ~T2_E~0); 133164#L555-1 assume !(1 == ~T3_E~0); 133165#L560-1 assume !(1 == ~T4_E~0); 133268#L565-1 assume !(1 == ~E_1~0); 133273#L570-1 assume !(1 == ~E_2~0); 133773#L575-1 assume !(1 == ~E_3~0); 133839#L580-1 assume !(1 == ~E_4~0); 133915#L766-1 assume !false; 134395#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 134388#L467 [2019-11-25 08:53:13,752 INFO L796 eck$LassoCheckResult]: Loop: 134388#L467 assume !false; 134389#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 134377#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 134378#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 134369#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 134365#L406 assume 0 != eval_~tmp~0; 134361#L406-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 134356#L414 assume !(0 != eval_~tmp_ndt_1~0); 134352#L411 assume !(0 == ~t1_st~0); 134346#L425 assume !(0 == ~t2_st~0); 134411#L439 assume !(0 == ~t3_st~0); 134410#L453 assume !(0 == ~t4_st~0); 134388#L467 [2019-11-25 08:53:13,752 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:13,752 INFO L82 PathProgramCache]: Analyzing trace with hash -1603966133, now seen corresponding path program 1 times [2019-11-25 08:53:13,753 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:13,753 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2075104693] [2019-11-25 08:53:13,753 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:13,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:13,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:13,770 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:53:13,770 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:13,771 INFO L82 PathProgramCache]: Analyzing trace with hash 590384517, now seen corresponding path program 1 times [2019-11-25 08:53:13,771 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:13,771 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [527840382] [2019-11-25 08:53:13,771 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:13,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:13,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:13,777 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:53:13,778 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:13,778 INFO L82 PathProgramCache]: Analyzing trace with hash 162355663, now seen corresponding path program 1 times [2019-11-25 08:53:13,778 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:13,778 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [795141688] [2019-11-25 08:53:13,779 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:13,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:13,801 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:13,801 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [795141688] [2019-11-25 08:53:13,802 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:13,802 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:53:13,802 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1801934563] [2019-11-25 08:53:13,862 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:53:13,863 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:53:13,863 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:53:13,863 INFO L87 Difference]: Start difference. First operand 13043 states and 16854 transitions. cyclomatic complexity: 3859 Second operand 3 states. [2019-11-25 08:53:13,950 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:53:13,951 INFO L93 Difference]: Finished difference Result 24101 states and 30714 transitions. [2019-11-25 08:53:13,951 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:53:13,951 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24101 states and 30714 transitions. [2019-11-25 08:53:14,021 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 6788 [2019-11-25 08:53:14,086 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24101 states to 24101 states and 30714 transitions. [2019-11-25 08:53:14,087 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8379 [2019-11-25 08:53:14,093 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8379 [2019-11-25 08:53:14,093 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24101 states and 30714 transitions. [2019-11-25 08:53:14,097 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-11-25 08:53:14,097 INFO L688 BuchiCegarLoop]: Abstraction has 24101 states and 30714 transitions. [2019-11-25 08:53:14,111 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24101 states and 30714 transitions. [MP z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Exception during sending of exit command (exit): Broken pipe [2019-11-25 08:53:14,426 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24101 to 23093. [2019-11-25 08:53:14,427 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23093 states. [2019-11-25 08:53:14,462 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23093 states to 23093 states and 29544 transitions. [2019-11-25 08:53:14,462 INFO L711 BuchiCegarLoop]: Abstraction has 23093 states and 29544 transitions. [2019-11-25 08:53:14,462 INFO L591 BuchiCegarLoop]: Abstraction has 23093 states and 29544 transitions. [2019-11-25 08:53:14,462 INFO L424 BuchiCegarLoop]: ======== Iteration 22============ [2019-11-25 08:53:14,462 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23093 states and 29544 transitions. [2019-11-25 08:53:14,507 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 6452 [2019-11-25 08:53:14,507 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:53:14,507 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:53:14,508 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:14,508 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:14,508 INFO L794 eck$LassoCheckResult]: Stem: 170677#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 170323#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 170324#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 170758#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 170759#L331-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 170948#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 172632#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 172631#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 172630#L351-1 assume !(0 == ~M_E~0); 172629#L492-1 assume !(0 == ~T1_E~0); 172628#L497-1 assume !(0 == ~T2_E~0); 172627#L502-1 assume !(0 == ~T3_E~0); 172626#L507-1 assume !(0 == ~T4_E~0); 172625#L512-1 assume !(0 == ~E_1~0); 172624#L517-1 assume !(0 == ~E_2~0); 172623#L522-1 assume !(0 == ~E_3~0); 172622#L527-1 assume !(0 == ~E_4~0); 172621#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 172620#L228 assume !(1 == ~m_pc~0); 172619#L228-2 is_master_triggered_~__retres1~0 := 0; 172618#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 172617#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 172616#L605 assume !(0 != activate_threads_~tmp~1); 172615#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 172614#L247 assume !(1 == ~t1_pc~0); 172613#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 172612#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 172611#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 172610#L613 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 171108#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 170837#L266 assume !(1 == ~t2_pc~0); 170838#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 172603#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 172601#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 170303#L621 assume !(0 != activate_threads_~tmp___1~0); 170304#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 170311#L285 assume !(1 == ~t3_pc~0); 170297#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 170298#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 170316#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 170662#L629 assume !(0 != activate_threads_~tmp___2~0); 170842#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 170843#L304 assume !(1 == ~t4_pc~0); 170871#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 170872#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 170909#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 170415#L637 assume !(0 != activate_threads_~tmp___3~0); 170416#L637-2 assume !(1 == ~M_E~0); 170417#L545-1 assume !(1 == ~T1_E~0); 170661#L550-1 assume !(1 == ~T2_E~0); 170317#L555-1 assume !(1 == ~T3_E~0); 170318#L560-1 assume !(1 == ~T4_E~0); 170421#L565-1 assume !(1 == ~E_1~0); 170426#L570-1 assume !(1 == ~E_2~0); 170952#L575-1 assume !(1 == ~E_3~0); 171022#L580-1 assume !(1 == ~E_4~0); 171109#L766-1 assume !false; 173568#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 190994#L467 [2019-11-25 08:53:14,509 INFO L796 eck$LassoCheckResult]: Loop: 190994#L467 assume !false; 192348#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 192345#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 192343#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 192341#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 192339#L406 assume 0 != eval_~tmp~0; 192337#L406-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 192334#L414 assume !(0 != eval_~tmp_ndt_1~0); 170433#L411 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 170384#L428 assume !(0 != eval_~tmp_ndt_2~0); 170385#L425 assume !(0 == ~t2_st~0); 190822#L439 assume !(0 == ~t3_st~0); 190820#L453 assume !(0 == ~t4_st~0); 190994#L467 [2019-11-25 08:53:14,509 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:14,509 INFO L82 PathProgramCache]: Analyzing trace with hash -750579381, now seen corresponding path program 1 times [2019-11-25 08:53:14,509 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:14,509 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1916832997] [2019-11-25 08:53:14,510 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:14,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:14,525 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:14,525 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1916832997] [2019-11-25 08:53:14,525 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:14,525 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:53:14,525 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1067106302] [2019-11-25 08:53:14,526 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:53:14,526 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:14,526 INFO L82 PathProgramCache]: Analyzing trace with hash 976788691, now seen corresponding path program 1 times [2019-11-25 08:53:14,526 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:14,526 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [618562231] [2019-11-25 08:53:14,526 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:14,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:14,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:14,530 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:53:14,600 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:53:14,601 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:53:14,601 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:53:14,601 INFO L87 Difference]: Start difference. First operand 23093 states and 29544 transitions. cyclomatic complexity: 6523 Second operand 3 states. [2019-11-25 08:53:14,641 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:53:14,641 INFO L93 Difference]: Finished difference Result 15181 states and 19529 transitions. [2019-11-25 08:53:14,641 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:53:14,642 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15181 states and 19529 transitions. [2019-11-25 08:53:14,685 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4710 [2019-11-25 08:53:14,725 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15181 states to 15181 states and 19529 transitions. [2019-11-25 08:53:14,725 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5312 [2019-11-25 08:53:14,729 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5312 [2019-11-25 08:53:14,729 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15181 states and 19529 transitions. [2019-11-25 08:53:14,731 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-11-25 08:53:14,731 INFO L688 BuchiCegarLoop]: Abstraction has 15181 states and 19529 transitions. [2019-11-25 08:53:14,740 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15181 states and 19529 transitions. [2019-11-25 08:53:14,828 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15181 to 15181. [2019-11-25 08:53:14,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15181 states. [2019-11-25 08:53:14,851 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15181 states to 15181 states and 19529 transitions. [2019-11-25 08:53:14,852 INFO L711 BuchiCegarLoop]: Abstraction has 15181 states and 19529 transitions. [2019-11-25 08:53:14,852 INFO L591 BuchiCegarLoop]: Abstraction has 15181 states and 19529 transitions. [2019-11-25 08:53:14,852 INFO L424 BuchiCegarLoop]: ======== Iteration 23============ [2019-11-25 08:53:14,852 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15181 states and 19529 transitions. [2019-11-25 08:53:14,882 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4710 [2019-11-25 08:53:14,882 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:53:14,882 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:53:14,883 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:14,883 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:14,883 INFO L794 eck$LassoCheckResult]: Stem: 208960#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 208607#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 208608#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 209040#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 209041#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 208890#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 208891#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 208955#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 208611#L351-1 assume !(0 == ~M_E~0); 208612#L492-1 assume !(0 == ~T1_E~0); 209142#L497-1 assume !(0 == ~T2_E~0); 209143#L502-1 assume !(0 == ~T3_E~0); 209200#L507-1 assume !(0 == ~T4_E~0); 208950#L512-1 assume !(0 == ~E_1~0); 208951#L517-1 assume !(0 == ~E_2~0); 208986#L522-1 assume !(0 == ~E_3~0); 208645#L527-1 assume !(0 == ~E_4~0); 208646#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 208709#L228 assume !(1 == ~m_pc~0); 209355#L228-2 is_master_triggered_~__retres1~0 := 0; 209315#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 208724#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 208725#L605 assume !(0 != activate_threads_~tmp~1); 209027#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 209034#L247 assume !(1 == ~t1_pc~0); 209063#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 209064#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 208881#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 208882#L613 assume !(0 != activate_threads_~tmp___0~0); 209376#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 209119#L266 assume !(1 == ~t2_pc~0); 209120#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 209122#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 209123#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 208582#L621 assume !(0 != activate_threads_~tmp___1~0); 208583#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 208591#L285 assume !(1 == ~t3_pc~0); 208576#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 208577#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 208596#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 208949#L629 assume !(0 != activate_threads_~tmp___2~0); 209124#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 209125#L304 assume !(1 == ~t4_pc~0); 209155#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 209156#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 209196#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 208698#L637 assume !(0 != activate_threads_~tmp___3~0); 208699#L637-2 assume !(1 == ~M_E~0); 208700#L545-1 assume !(1 == ~T1_E~0); 208944#L550-1 assume !(1 == ~T2_E~0); 208601#L555-1 assume !(1 == ~T3_E~0); 208602#L560-1 assume !(1 == ~T4_E~0); 208703#L565-1 assume !(1 == ~E_1~0); 208708#L570-1 assume !(1 == ~E_2~0); 209227#L575-1 assume !(1 == ~E_3~0); 209297#L580-1 assume !(1 == ~E_4~0); 209377#L766-1 assume !false; 210642#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 210641#L467 [2019-11-25 08:53:14,884 INFO L796 eck$LassoCheckResult]: Loop: 210641#L467 assume !false; 210640#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 210639#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 210638#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 210636#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 210634#L406 assume 0 != eval_~tmp~0; 210633#L406-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 210631#L414 assume !(0 != eval_~tmp_ndt_1~0); 210630#L411 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 210628#L428 assume !(0 != eval_~tmp_ndt_2~0); 210629#L425 assume !(0 == ~t2_st~0); 210651#L439 assume !(0 == ~t3_st~0); 210646#L453 assume !(0 == ~t4_st~0); 210641#L467 [2019-11-25 08:53:14,884 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:14,884 INFO L82 PathProgramCache]: Analyzing trace with hash -1603966133, now seen corresponding path program 2 times [2019-11-25 08:53:14,884 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:14,884 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1988012174] [2019-11-25 08:53:14,884 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:14,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:14,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:14,900 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:53:14,900 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:14,900 INFO L82 PathProgramCache]: Analyzing trace with hash 976788691, now seen corresponding path program 2 times [2019-11-25 08:53:14,901 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:14,901 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1395223630] [2019-11-25 08:53:14,901 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:14,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:14,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:14,905 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:53:14,906 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:14,906 INFO L82 PathProgramCache]: Analyzing trace with hash 592796105, now seen corresponding path program 1 times [2019-11-25 08:53:14,906 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:14,906 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1921179302] [2019-11-25 08:53:14,907 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:14,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:14,931 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:14,932 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1921179302] [2019-11-25 08:53:14,932 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:14,932 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:53:14,932 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1660205663] [2019-11-25 08:53:15,010 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:53:15,011 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:53:15,011 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:53:15,011 INFO L87 Difference]: Start difference. First operand 15181 states and 19529 transitions. cyclomatic complexity: 4396 Second operand 3 states. [2019-11-25 08:53:15,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:53:15,096 INFO L93 Difference]: Finished difference Result 25501 states and 32615 transitions. [2019-11-25 08:53:15,097 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:53:15,097 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25501 states and 32615 transitions. [2019-11-25 08:53:15,177 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7610 [2019-11-25 08:53:15,240 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25501 states to 25501 states and 32615 transitions. [2019-11-25 08:53:15,240 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8744 [2019-11-25 08:53:15,245 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8744 [2019-11-25 08:53:15,246 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25501 states and 32615 transitions. [2019-11-25 08:53:15,246 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-11-25 08:53:15,246 INFO L688 BuchiCegarLoop]: Abstraction has 25501 states and 32615 transitions. [2019-11-25 08:53:15,261 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25501 states and 32615 transitions. [2019-11-25 08:53:15,419 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25501 to 25501. [2019-11-25 08:53:15,419 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25501 states. [2019-11-25 08:53:15,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25501 states to 25501 states and 32615 transitions. [2019-11-25 08:53:15,459 INFO L711 BuchiCegarLoop]: Abstraction has 25501 states and 32615 transitions. [2019-11-25 08:53:15,459 INFO L591 BuchiCegarLoop]: Abstraction has 25501 states and 32615 transitions. [2019-11-25 08:53:15,459 INFO L424 BuchiCegarLoop]: ======== Iteration 24============ [2019-11-25 08:53:15,460 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25501 states and 32615 transitions. [2019-11-25 08:53:15,512 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7610 [2019-11-25 08:53:15,512 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:53:15,512 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:53:15,513 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:15,513 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:15,515 INFO L794 eck$LassoCheckResult]: Stem: 249653#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 249292#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 249293#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 249728#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 249729#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 249582#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 249583#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 249646#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 249298#L351-1 assume !(0 == ~M_E~0); 249299#L492-1 assume !(0 == ~T1_E~0); 249836#L497-1 assume !(0 == ~T2_E~0); 249837#L502-1 assume !(0 == ~T3_E~0); 249900#L507-1 assume !(0 == ~T4_E~0); 249644#L512-1 assume !(0 == ~E_1~0); 249645#L517-1 assume !(0 == ~E_2~0); 249681#L522-1 assume !(0 == ~E_3~0); 249336#L527-1 assume !(0 == ~E_4~0); 249337#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 249398#L228 assume !(1 == ~m_pc~0); 250054#L228-2 is_master_triggered_~__retres1~0 := 0; 250008#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 249414#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 249415#L605 assume !(0 != activate_threads_~tmp~1); 249719#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 249724#L247 assume !(1 == ~t1_pc~0); 249754#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 249755#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 249570#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 249571#L613 assume !(0 != activate_threads_~tmp___0~0); 250073#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 249814#L266 assume !(1 == ~t2_pc~0); 249815#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 249817#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 249818#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 249268#L621 assume !(0 != activate_threads_~tmp___1~0); 249269#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 249280#L285 assume !(1 == ~t3_pc~0); 249266#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 249267#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 249281#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 249639#L629 assume !(0 != activate_threads_~tmp___2~0); 249819#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 249820#L304 assume !(1 == ~t4_pc~0); 249856#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 249857#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 249896#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 249382#L637 assume !(0 != activate_threads_~tmp___3~0); 249383#L637-2 assume !(1 == ~M_E~0); 249389#L545-1 assume !(1 == ~T1_E~0); 249638#L550-1 assume !(1 == ~T2_E~0); 249286#L555-1 assume !(1 == ~T3_E~0); 249287#L560-1 assume !(1 == ~T4_E~0); 249392#L565-1 assume !(1 == ~E_1~0); 249397#L570-1 assume !(1 == ~E_2~0); 249923#L575-1 assume !(1 == ~E_3~0); 249989#L580-1 assume !(1 == ~E_4~0); 250074#L766-1 assume !false; 252245#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 262696#L467 [2019-11-25 08:53:15,515 INFO L796 eck$LassoCheckResult]: Loop: 262696#L467 assume !false; 267634#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 267632#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 267630#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 267628#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 267626#L406 assume 0 != eval_~tmp~0; 267624#L406-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 267621#L414 assume !(0 != eval_~tmp_ndt_1~0); 267619#L411 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 267615#L428 assume !(0 != eval_~tmp_ndt_2~0); 267616#L425 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 267649#L442 assume !(0 != eval_~tmp_ndt_3~0); 267648#L439 assume !(0 == ~t3_st~0); 267641#L453 assume !(0 == ~t4_st~0); 262696#L467 [2019-11-25 08:53:15,516 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:15,516 INFO L82 PathProgramCache]: Analyzing trace with hash -1603966133, now seen corresponding path program 3 times [2019-11-25 08:53:15,516 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:15,516 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1324378425] [2019-11-25 08:53:15,516 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:15,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:15,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:15,534 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:53:15,535 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:15,535 INFO L82 PathProgramCache]: Analyzing trace with hash 210997043, now seen corresponding path program 1 times [2019-11-25 08:53:15,535 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:15,535 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1247666701] [2019-11-25 08:53:15,535 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:15,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:15,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:15,540 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:53:15,540 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:15,541 INFO L82 PathProgramCache]: Analyzing trace with hash 1192128765, now seen corresponding path program 1 times [2019-11-25 08:53:15,541 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:15,541 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1417686870] [2019-11-25 08:53:15,541 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:15,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:15,566 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:15,566 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1417686870] [2019-11-25 08:53:15,566 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:15,566 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:53:15,566 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [703116959] [2019-11-25 08:53:15,654 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:53:15,655 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:53:15,655 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:53:15,655 INFO L87 Difference]: Start difference. First operand 25501 states and 32615 transitions. cyclomatic complexity: 7162 Second operand 3 states. [2019-11-25 08:53:15,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:53:15,775 INFO L93 Difference]: Finished difference Result 32833 states and 41885 transitions. [2019-11-25 08:53:15,776 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:53:15,776 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32833 states and 41885 transitions. [2019-11-25 08:53:15,871 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9665 [2019-11-25 08:53:15,937 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32833 states to 32833 states and 41885 transitions. [2019-11-25 08:53:15,937 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11310 [2019-11-25 08:53:15,942 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11310 [2019-11-25 08:53:15,942 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32833 states and 41885 transitions. [2019-11-25 08:53:15,943 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-11-25 08:53:15,943 INFO L688 BuchiCegarLoop]: Abstraction has 32833 states and 41885 transitions. [2019-11-25 08:53:15,962 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32833 states and 41885 transitions. [2019-11-25 08:53:16,413 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32833 to 31429. [2019-11-25 08:53:16,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31429 states. [2019-11-25 08:53:16,451 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31429 states to 31429 states and 40157 transitions. [2019-11-25 08:53:16,451 INFO L711 BuchiCegarLoop]: Abstraction has 31429 states and 40157 transitions. [2019-11-25 08:53:16,451 INFO L591 BuchiCegarLoop]: Abstraction has 31429 states and 40157 transitions. [2019-11-25 08:53:16,451 INFO L424 BuchiCegarLoop]: ======== Iteration 25============ [2019-11-25 08:53:16,451 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31429 states and 40157 transitions. [2019-11-25 08:53:16,501 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9197 [2019-11-25 08:53:16,501 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:53:16,501 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:53:16,502 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:16,502 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:16,502 INFO L794 eck$LassoCheckResult]: Stem: 308005#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 307635#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 307636#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 308080#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 308081#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 307931#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 307932#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 307996#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 307641#L351-1 assume !(0 == ~M_E~0); 307642#L492-1 assume !(0 == ~T1_E~0); 308200#L497-1 assume !(0 == ~T2_E~0); 308201#L502-1 assume !(0 == ~T3_E~0); 308263#L507-1 assume !(0 == ~T4_E~0); 307994#L512-1 assume !(0 == ~E_1~0); 307995#L517-1 assume !(0 == ~E_2~0); 308031#L522-1 assume !(0 == ~E_3~0); 307683#L527-1 assume !(0 == ~E_4~0); 307684#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 307747#L228 assume !(1 == ~m_pc~0); 308430#L228-2 is_master_triggered_~__retres1~0 := 0; 308386#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 307764#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 307765#L605 assume !(0 != activate_threads_~tmp~1); 308071#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 308076#L247 assume !(1 == ~t1_pc~0); 308110#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 308111#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 307919#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 307920#L613 assume !(0 != activate_threads_~tmp___0~0); 308449#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 308178#L266 assume !(1 == ~t2_pc~0); 308179#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 308181#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 308182#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 307611#L621 assume !(0 != activate_threads_~tmp___1~0); 307612#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 307623#L285 assume !(1 == ~t3_pc~0); 307609#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 307610#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 307624#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 307989#L629 assume !(0 != activate_threads_~tmp___2~0); 308183#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 308184#L304 assume !(1 == ~t4_pc~0); 308218#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 308219#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 308258#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 307731#L637 assume !(0 != activate_threads_~tmp___3~0); 307732#L637-2 assume !(1 == ~M_E~0); 307737#L545-1 assume !(1 == ~T1_E~0); 307988#L550-1 assume !(1 == ~T2_E~0); 307629#L555-1 assume !(1 == ~T3_E~0); 307630#L560-1 assume !(1 == ~T4_E~0); 307741#L565-1 assume !(1 == ~E_1~0); 307746#L570-1 assume !(1 == ~E_2~0); 308295#L575-1 assume !(1 == ~E_3~0); 308367#L580-1 assume !(1 == ~E_4~0); 308450#L766-1 assume !false; 311550#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 322687#L467 [2019-11-25 08:53:16,502 INFO L796 eck$LassoCheckResult]: Loop: 322687#L467 assume !false; 322686#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 322685#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 322683#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 322681#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 322679#L406 assume 0 != eval_~tmp~0; 322677#L406-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 322674#L414 assume !(0 != eval_~tmp_ndt_1~0); 322672#L411 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 322669#L428 assume !(0 != eval_~tmp_ndt_2~0); 322670#L425 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 322705#L442 assume !(0 != eval_~tmp_ndt_3~0); 322703#L439 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 322700#L456 assume !(0 != eval_~tmp_ndt_4~0); 322691#L453 assume !(0 == ~t4_st~0); 322687#L467 [2019-11-25 08:53:16,503 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:16,503 INFO L82 PathProgramCache]: Analyzing trace with hash -1603966133, now seen corresponding path program 4 times [2019-11-25 08:53:16,503 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:16,503 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [577135140] [2019-11-25 08:53:16,503 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:16,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:16,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:16,519 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:53:16,519 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:16,519 INFO L82 PathProgramCache]: Analyzing trace with hash -2049172699, now seen corresponding path program 1 times [2019-11-25 08:53:16,519 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:16,519 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1147112118] [2019-11-25 08:53:16,520 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:16,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:16,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:16,525 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:53:16,525 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:16,525 INFO L82 PathProgramCache]: Analyzing trace with hash -1698860389, now seen corresponding path program 1 times [2019-11-25 08:53:16,525 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:16,525 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [553621865] [2019-11-25 08:53:16,526 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:16,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:53:16,547 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:53:16,548 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [553621865] [2019-11-25 08:53:16,548 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:53:16,548 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:53:16,548 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [984550164] [2019-11-25 08:53:16,666 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:53:16,666 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:53:16,667 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:53:16,667 INFO L87 Difference]: Start difference. First operand 31429 states and 40157 transitions. cyclomatic complexity: 8776 Second operand 3 states. [2019-11-25 08:53:16,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:53:16,806 INFO L93 Difference]: Finished difference Result 55933 states and 70901 transitions. [2019-11-25 08:53:16,807 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:53:16,807 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55933 states and 70901 transitions. [2019-11-25 08:53:16,979 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16140 [2019-11-25 08:53:17,099 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55933 states to 55933 states and 70901 transitions. [2019-11-25 08:53:17,100 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19353 [2019-11-25 08:53:17,111 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19353 [2019-11-25 08:53:17,111 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55933 states and 70901 transitions. [2019-11-25 08:53:17,113 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2019-11-25 08:53:17,113 INFO L688 BuchiCegarLoop]: Abstraction has 55933 states and 70901 transitions. [2019-11-25 08:53:17,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55933 states and 70901 transitions. [2019-11-25 08:53:17,454 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55933 to 55933. [2019-11-25 08:53:17,454 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 55933 states. [2019-11-25 08:53:17,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55933 states to 55933 states and 70901 transitions. [2019-11-25 08:53:17,550 INFO L711 BuchiCegarLoop]: Abstraction has 55933 states and 70901 transitions. [2019-11-25 08:53:17,551 INFO L591 BuchiCegarLoop]: Abstraction has 55933 states and 70901 transitions. [2019-11-25 08:53:17,551 INFO L424 BuchiCegarLoop]: ======== Iteration 26============ [2019-11-25 08:53:17,552 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55933 states and 70901 transitions. [2019-11-25 08:53:17,639 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16140 [2019-11-25 08:53:17,639 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:53:17,639 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:53:17,640 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:17,640 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:53:17,640 INFO L794 eck$LassoCheckResult]: Stem: 395374#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 395006#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 395007#L729 havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 395463#L324 assume 1 == ~m_i~0;~m_st~0 := 0; 395464#L331-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 395304#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 395305#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 395366#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 395012#L351-1 assume !(0 == ~M_E~0); 395013#L492-1 assume !(0 == ~T1_E~0); 395584#L497-1 assume !(0 == ~T2_E~0); 395585#L502-1 assume !(0 == ~T3_E~0); 395654#L507-1 assume !(0 == ~T4_E~0); 395364#L512-1 assume !(0 == ~E_1~0); 395365#L517-1 assume !(0 == ~E_2~0); 395403#L522-1 assume !(0 == ~E_3~0); 395052#L527-1 assume !(0 == ~E_4~0); 395053#L532-1 havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 395117#L228 assume !(1 == ~m_pc~0); 395810#L228-2 is_master_triggered_~__retres1~0 := 0; 395761#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 395134#L240 activate_threads_#t~ret6 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 395135#L605 assume !(0 != activate_threads_~tmp~1); 395452#L605-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 395461#L247 assume !(1 == ~t1_pc~0); 395493#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 395494#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 395294#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 395295#L613 assume !(0 != activate_threads_~tmp___0~0); 395834#L613-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 395562#L266 assume !(1 == ~t2_pc~0); 395563#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 395565#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 395566#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 394982#L621 assume !(0 != activate_threads_~tmp___1~0); 394983#L621-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 394994#L285 assume !(1 == ~t3_pc~0); 394980#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 394981#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 394999#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 395359#L629 assume !(0 != activate_threads_~tmp___2~0); 395567#L629-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 395568#L304 assume !(1 == ~t4_pc~0); 395605#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 395606#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 395650#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 395105#L637 assume !(0 != activate_threads_~tmp___3~0); 395106#L637-2 assume !(1 == ~M_E~0); 395107#L545-1 assume !(1 == ~T1_E~0); 395358#L550-1 assume !(1 == ~T2_E~0); 395000#L555-1 assume !(1 == ~T3_E~0); 395001#L560-1 assume !(1 == ~T4_E~0); 395111#L565-1 assume !(1 == ~E_1~0); 395116#L570-1 assume !(1 == ~E_2~0); 395671#L575-1 assume !(1 == ~E_3~0); 395741#L580-1 assume !(1 == ~E_4~0); 395835#L766-1 assume !false; 404144#L767 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 422224#L467 [2019-11-25 08:53:17,640 INFO L796 eck$LassoCheckResult]: Loop: 422224#L467 assume !false; 423168#L402 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 423166#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 423164#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 423162#L392 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 423160#L406 assume 0 != eval_~tmp~0; 423157#L406-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 423154#L414 assume !(0 != eval_~tmp_ndt_1~0); 423151#L411 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 423149#L428 assume !(0 != eval_~tmp_ndt_2~0); 423146#L425 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 423143#L442 assume !(0 != eval_~tmp_ndt_3~0); 423140#L439 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 423138#L456 assume !(0 != eval_~tmp_ndt_4~0); 423137#L453 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 423119#L470 assume !(0 != eval_~tmp_ndt_5~0); 422224#L467 [2019-11-25 08:53:17,641 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:17,641 INFO L82 PathProgramCache]: Analyzing trace with hash -1603966133, now seen corresponding path program 5 times [2019-11-25 08:53:17,641 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:17,641 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1252078863] [2019-11-25 08:53:17,641 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:17,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:17,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:17,657 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:53:17,657 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:17,657 INFO L82 PathProgramCache]: Analyzing trace with hash 900155617, now seen corresponding path program 1 times [2019-11-25 08:53:17,657 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:17,658 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2035139865] [2019-11-25 08:53:17,658 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:17,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:17,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:17,663 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:53:18,008 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:53:18,008 INFO L82 PathProgramCache]: Analyzing trace with hash -1125064661, now seen corresponding path program 1 times [2019-11-25 08:53:18,008 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:53:18,008 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1690316338] [2019-11-25 08:53:18,009 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:53:18,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:18,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:53:18,029 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:53:18,573 WARN L192 SmtUtils]: Spent 433.00 ms on a formula simplification. DAG size of input: 157 DAG size of output: 106 [2019-11-25 08:53:18,697 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 25.11 08:53:18 BoogieIcfgContainer [2019-11-25 08:53:18,698 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2019-11-25 08:53:18,698 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-25 08:53:18,698 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-25 08:53:18,698 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-25 08:53:18,699 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 08:53:01" (3/4) ... [2019-11-25 08:53:18,701 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2019-11-25 08:53:18,752 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_db6b70a3-2220-41b3-9cd0-fefc78c8771a/bin/uautomizer/witness.graphml [2019-11-25 08:53:18,752 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-25 08:53:18,753 INFO L168 Benchmark]: Toolchain (without parser) took 18637.53 ms. Allocated memory was 1.0 GB in the beginning and 1.9 GB in the end (delta: 860.4 MB). Free memory was 951.4 MB in the beginning and 1.3 GB in the end (delta: -367.6 MB). Peak memory consumption was 492.8 MB. Max. memory is 11.5 GB. [2019-11-25 08:53:18,754 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-25 08:53:18,754 INFO L168 Benchmark]: CACSL2BoogieTranslator took 400.95 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 140.0 MB). Free memory was 951.4 MB in the beginning and 1.1 GB in the end (delta: -179.1 MB). Peak memory consumption was 23.2 MB. Max. memory is 11.5 GB. [2019-11-25 08:53:18,754 INFO L168 Benchmark]: Boogie Procedure Inliner took 55.53 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 7.1 MB). Peak memory consumption was 7.1 MB. Max. memory is 11.5 GB. [2019-11-25 08:53:18,755 INFO L168 Benchmark]: Boogie Preprocessor took 55.37 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 7.1 MB). Peak memory consumption was 7.1 MB. Max. memory is 11.5 GB. [2019-11-25 08:53:18,755 INFO L168 Benchmark]: RCFGBuilder took 1195.10 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 96.6 MB). Peak memory consumption was 96.6 MB. Max. memory is 11.5 GB. [2019-11-25 08:53:18,755 INFO L168 Benchmark]: BuchiAutomizer took 16872.89 ms. Allocated memory was 1.2 GB in the beginning and 1.9 GB in the end (delta: 720.4 MB). Free memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: -306.2 MB). Peak memory consumption was 414.2 MB. Max. memory is 11.5 GB. [2019-11-25 08:53:18,756 INFO L168 Benchmark]: Witness Printer took 54.18 ms. Allocated memory is still 1.9 GB. Free memory was 1.3 GB in the beginning and 1.3 GB in the end (delta: 6.9 MB). Peak memory consumption was 6.9 MB. Max. memory is 11.5 GB. [2019-11-25 08:53:18,757 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 400.95 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 140.0 MB). Free memory was 951.4 MB in the beginning and 1.1 GB in the end (delta: -179.1 MB). Peak memory consumption was 23.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 55.53 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 7.1 MB). Peak memory consumption was 7.1 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 55.37 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 7.1 MB). Peak memory consumption was 7.1 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1195.10 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 96.6 MB). Peak memory consumption was 96.6 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 16872.89 ms. Allocated memory was 1.2 GB in the beginning and 1.9 GB in the end (delta: 720.4 MB). Free memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: -306.2 MB). Peak memory consumption was 414.2 MB. Max. memory is 11.5 GB. * Witness Printer took 54.18 ms. Allocated memory is still 1.9 GB. Free memory was 1.3 GB in the beginning and 1.3 GB in the end (delta: 6.9 MB). Peak memory consumption was 6.9 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 27 terminating modules (25 trivial, 2 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function -1 * E_3 + 1 and consists of 3 locations. One deterministic module has affine ranking function -1 * T1_E + 1 and consists of 3 locations. 25 modules have a trivial ranking function, the largest among these consists of 11 locations. The remainder module has 55933 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 16.8s and 26 iterations. TraceHistogramMax:2. Analysis of lassos took 9.0s. Construction of modules took 1.0s. Büchi inclusion checks took 1.7s. Highest rank in rank-based complementation 3. Minimization of det autom 15. Minimization of nondet autom 12. Automata minimization 2.6s AutomataMinimizationTime, 27 MinimizatonAttempts, 13678 StatesRemovedByMinimization, 16 NontrivialMinimizations. Non-live state removal took 1.5s Buchi closure took 0.0s. Biggest automaton had 55933 states and ocurred in iteration 25. Nontrivial modules had stage [2, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 6/6 HoareTripleCheckerStatistics: 16259 SDtfs, 17184 SDslu, 21688 SDs, 0 SdLazy, 785 SolverSat, 295 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.0s Time LassoAnalysisResults: nont1 unkn0 SFLI7 SFLT0 conc4 concLT1 SILN1 SILU0 SILI11 SILT1 lasso0 LassoPreprocessingBenchmarks: Lassos: inital182 mio100 ax100 hnf100 lsp6 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq209 hnf86 smp100 dnf189 smp57 tf109 neg96 sie108 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 31ms VariablesStem: 0 VariablesLoop: 2 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 12 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 2 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.3s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 401]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {__retres1=0, t3_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2a836caf=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7ab444ac=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@42919538=0, tmp=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@70576711=0, __retres1=0, kernel_st=1, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@32b7e2ff=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5adf32b3=0, t4_i=1, E_3=2, t4_pc=0, \result=0, E_1=2, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, m_st=0, tmp___2=0, tmp___0=0, t3_pc=0, tmp=0, \result=0, __retres1=0, m_pc=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4aba6942=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, E_2=2, E_4=2, __retres1=1, T1_E=2, tmp_ndt_1=0, M_E=2, tmp=0, tmp_ndt_3=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@340e0f1b=0, __retres1=0, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@19a01389=0, T4_E=2, t3_i=1, t4_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5d92a9f7=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4b9900ef=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@41725cdd=0, t1_st=0, tmp_ndt_5=0, t2_pc=0, tmp___3=0, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5ee83914=0, t1_i=1, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 401]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int m_i ; [L26] int t1_i ; [L27] int t2_i ; [L28] int t3_i ; [L29] int t4_i ; [L30] int M_E = 2; [L31] int T1_E = 2; [L32] int T2_E = 2; [L33] int T3_E = 2; [L34] int T4_E = 2; [L35] int E_1 = 2; [L36] int E_2 = 2; [L37] int E_3 = 2; [L38] int E_4 = 2; [L811] int __retres1 ; [L723] m_i = 1 [L724] t1_i = 1 [L725] t2_i = 1 [L726] t3_i = 1 [L727] t4_i = 1 [L752] int kernel_st ; [L753] int tmp ; [L754] int tmp___0 ; [L758] kernel_st = 0 [L331] COND TRUE m_i == 1 [L332] m_st = 0 [L336] COND TRUE t1_i == 1 [L337] t1_st = 0 [L341] COND TRUE t2_i == 1 [L342] t2_st = 0 [L346] COND TRUE t3_i == 1 [L347] t3_st = 0 [L351] COND TRUE t4_i == 1 [L352] t4_st = 0 [L492] COND FALSE !(M_E == 0) [L497] COND FALSE !(T1_E == 0) [L502] COND FALSE !(T2_E == 0) [L507] COND FALSE !(T3_E == 0) [L512] COND FALSE !(T4_E == 0) [L517] COND FALSE !(E_1 == 0) [L522] COND FALSE !(E_2 == 0) [L527] COND FALSE !(E_3 == 0) [L532] COND FALSE !(E_4 == 0) [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L225] int __retres1 ; [L228] COND FALSE !(m_pc == 1) [L238] __retres1 = 0 [L240] return (__retres1); [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) [L244] int __retres1 ; [L247] COND FALSE !(t1_pc == 1) [L257] __retres1 = 0 [L259] return (__retres1); [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) [L263] int __retres1 ; [L266] COND FALSE !(t2_pc == 1) [L276] __retres1 = 0 [L278] return (__retres1); [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) [L282] int __retres1 ; [L285] COND FALSE !(t3_pc == 1) [L295] __retres1 = 0 [L297] return (__retres1); [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) [L301] int __retres1 ; [L304] COND FALSE !(t4_pc == 1) [L314] __retres1 = 0 [L316] return (__retres1); [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE !(\read(tmp___3)) [L545] COND FALSE !(M_E == 1) [L550] COND FALSE !(T1_E == 1) [L555] COND FALSE !(T2_E == 1) [L560] COND FALSE !(T3_E == 1) [L565] COND FALSE !(T4_E == 1) [L570] COND FALSE !(E_1 == 1) [L575] COND FALSE !(E_2 == 1) [L580] COND FALSE !(E_3 == 1) [L585] COND FALSE !(E_4 == 1) [L766] COND TRUE 1 [L769] kernel_st = 1 [L397] int tmp ; Loop: [L401] COND TRUE 1 [L361] int __retres1 ; [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 [L392] return (__retres1); [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND FALSE !(\read(tmp_ndt_1)) [L425] COND TRUE t1_st == 0 [L426] int tmp_ndt_2; [L427] tmp_ndt_2 = __VERIFIER_nondet_int() [L428] COND FALSE !(\read(tmp_ndt_2)) [L439] COND TRUE t2_st == 0 [L440] int tmp_ndt_3; [L441] tmp_ndt_3 = __VERIFIER_nondet_int() [L442] COND FALSE !(\read(tmp_ndt_3)) [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND FALSE !(\read(tmp_ndt_4)) [L467] COND TRUE t4_st == 0 [L468] int tmp_ndt_5; [L469] tmp_ndt_5 = __VERIFIER_nondet_int() [L470] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...