./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.05.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 6b5699aa Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_c943f5b4-42aa-45ad-a775-4c520edda3ad/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_c943f5b4-42aa-45ad-a775-4c520edda3ad/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_c943f5b4-42aa-45ad-a775-4c520edda3ad/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_c943f5b4-42aa-45ad-a775-4c520edda3ad/bin/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.05.cil.c -s /tmp/vcloud-vcloud-master/worker/run_dir_c943f5b4-42aa-45ad-a775-4c520edda3ad/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_c943f5b4-42aa-45ad-a775-4c520edda3ad/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 8ef5d3a30c95e1a42cc229ca801f47c5cf92951a ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.24-6b5699a [2019-11-25 08:58:08,012 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-25 08:58:08,014 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-25 08:58:08,024 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-25 08:58:08,024 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-25 08:58:08,025 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-25 08:58:08,027 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-25 08:58:08,028 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-25 08:58:08,030 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-25 08:58:08,031 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-25 08:58:08,032 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-25 08:58:08,033 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-25 08:58:08,033 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-25 08:58:08,034 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-25 08:58:08,035 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-25 08:58:08,036 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-25 08:58:08,037 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-25 08:58:08,037 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-25 08:58:08,039 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-25 08:58:08,041 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-25 08:58:08,042 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-25 08:58:08,043 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-25 08:58:08,044 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-25 08:58:08,045 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-25 08:58:08,047 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-25 08:58:08,048 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-25 08:58:08,048 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-25 08:58:08,049 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-25 08:58:08,049 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-25 08:58:08,050 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-25 08:58:08,050 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-25 08:58:08,051 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-25 08:58:08,051 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-25 08:58:08,052 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-25 08:58:08,053 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-25 08:58:08,053 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-25 08:58:08,053 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-25 08:58:08,054 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-25 08:58:08,054 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-25 08:58:08,055 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-25 08:58:08,055 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-25 08:58:08,056 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_c943f5b4-42aa-45ad-a775-4c520edda3ad/bin/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2019-11-25 08:58:08,070 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-25 08:58:08,070 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-25 08:58:08,071 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-25 08:58:08,072 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-25 08:58:08,072 INFO L138 SettingsManager]: * Use SBE=true [2019-11-25 08:58:08,072 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2019-11-25 08:58:08,072 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2019-11-25 08:58:08,072 INFO L138 SettingsManager]: * Use old map elimination=false [2019-11-25 08:58:08,073 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2019-11-25 08:58:08,073 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2019-11-25 08:58:08,073 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2019-11-25 08:58:08,073 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-25 08:58:08,073 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-25 08:58:08,073 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2019-11-25 08:58:08,074 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-25 08:58:08,074 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-25 08:58:08,074 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-25 08:58:08,074 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2019-11-25 08:58:08,074 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2019-11-25 08:58:08,075 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2019-11-25 08:58:08,075 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-25 08:58:08,075 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-25 08:58:08,075 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2019-11-25 08:58:08,075 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-25 08:58:08,075 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2019-11-25 08:58:08,076 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-25 08:58:08,076 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-25 08:58:08,076 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2019-11-25 08:58:08,076 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-25 08:58:08,076 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-25 08:58:08,077 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2019-11-25 08:58:08,077 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2019-11-25 08:58:08,077 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_c943f5b4-42aa-45ad-a775-4c520edda3ad/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 8ef5d3a30c95e1a42cc229ca801f47c5cf92951a [2019-11-25 08:58:08,223 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-25 08:58:08,233 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-25 08:58:08,237 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-25 08:58:08,238 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-25 08:58:08,239 INFO L275 PluginConnector]: CDTParser initialized [2019-11-25 08:58:08,239 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_c943f5b4-42aa-45ad-a775-4c520edda3ad/bin/uautomizer/../../sv-benchmarks/c/systemc/transmitter.05.cil.c [2019-11-25 08:58:08,294 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_c943f5b4-42aa-45ad-a775-4c520edda3ad/bin/uautomizer/data/61a23aa8c/1a140d32b12f41daa2b5c934797fe314/FLAGf57622012 [2019-11-25 08:58:08,670 INFO L306 CDTParser]: Found 1 translation units. [2019-11-25 08:58:08,671 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_c943f5b4-42aa-45ad-a775-4c520edda3ad/sv-benchmarks/c/systemc/transmitter.05.cil.c [2019-11-25 08:58:08,681 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_c943f5b4-42aa-45ad-a775-4c520edda3ad/bin/uautomizer/data/61a23aa8c/1a140d32b12f41daa2b5c934797fe314/FLAGf57622012 [2019-11-25 08:58:08,692 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_c943f5b4-42aa-45ad-a775-4c520edda3ad/bin/uautomizer/data/61a23aa8c/1a140d32b12f41daa2b5c934797fe314 [2019-11-25 08:58:08,695 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-25 08:58:08,696 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-25 08:58:08,697 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-25 08:58:08,697 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-25 08:58:08,700 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-25 08:58:08,701 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 25.11 08:58:08" (1/1) ... [2019-11-25 08:58:08,703 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@23ce90a7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:58:08, skipping insertion in model container [2019-11-25 08:58:08,703 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 25.11 08:58:08" (1/1) ... [2019-11-25 08:58:08,709 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-11-25 08:58:08,741 INFO L179 MainTranslator]: Built tables and reachable declarations [2019-11-25 08:58:09,013 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-25 08:58:09,018 INFO L201 MainTranslator]: Completed pre-run [2019-11-25 08:58:09,079 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-25 08:58:09,096 INFO L205 MainTranslator]: Completed translation [2019-11-25 08:58:09,097 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:58:09 WrapperNode [2019-11-25 08:58:09,097 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-25 08:58:09,097 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-25 08:58:09,097 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-25 08:58:09,098 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-25 08:58:09,105 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:58:09" (1/1) ... [2019-11-25 08:58:09,114 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:58:09" (1/1) ... [2019-11-25 08:58:09,160 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-25 08:58:09,161 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-25 08:58:09,161 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-25 08:58:09,161 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-25 08:58:09,170 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:58:09" (1/1) ... [2019-11-25 08:58:09,170 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:58:09" (1/1) ... [2019-11-25 08:58:09,176 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:58:09" (1/1) ... [2019-11-25 08:58:09,176 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:58:09" (1/1) ... [2019-11-25 08:58:09,192 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:58:09" (1/1) ... [2019-11-25 08:58:09,209 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:58:09" (1/1) ... [2019-11-25 08:58:09,214 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:58:09" (1/1) ... [2019-11-25 08:58:09,221 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-25 08:58:09,221 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-25 08:58:09,221 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-25 08:58:09,221 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-25 08:58:09,222 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:58:09" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_c943f5b4-42aa-45ad-a775-4c520edda3ad/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2019-11-25 08:58:09,296 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-25 08:58:09,296 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-25 08:58:10,728 INFO L279 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-25 08:58:10,729 INFO L284 CfgBuilder]: Removed 181 assume(true) statements. [2019-11-25 08:58:10,730 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 08:58:10 BoogieIcfgContainer [2019-11-25 08:58:10,730 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-25 08:58:10,731 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2019-11-25 08:58:10,731 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2019-11-25 08:58:10,735 INFO L275 PluginConnector]: BuchiAutomizer initialized [2019-11-25 08:58:10,736 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-11-25 08:58:10,736 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 25.11 08:58:08" (1/3) ... [2019-11-25 08:58:10,737 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4020367 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 25.11 08:58:10, skipping insertion in model container [2019-11-25 08:58:10,737 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-11-25 08:58:10,737 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 08:58:09" (2/3) ... [2019-11-25 08:58:10,738 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4020367 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 25.11 08:58:10, skipping insertion in model container [2019-11-25 08:58:10,738 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2019-11-25 08:58:10,738 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 08:58:10" (3/3) ... [2019-11-25 08:58:10,740 INFO L371 chiAutomizerObserver]: Analyzing ICFG transmitter.05.cil.c [2019-11-25 08:58:10,781 INFO L356 BuchiCegarLoop]: Interprodecural is true [2019-11-25 08:58:10,781 INFO L357 BuchiCegarLoop]: Hoare is false [2019-11-25 08:58:10,781 INFO L358 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2019-11-25 08:58:10,781 INFO L359 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-25 08:58:10,781 INFO L360 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-25 08:58:10,782 INFO L361 BuchiCegarLoop]: Difference is false [2019-11-25 08:58:10,782 INFO L362 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-25 08:58:10,782 INFO L365 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2019-11-25 08:58:10,808 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 485 states. [2019-11-25 08:58:10,853 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 408 [2019-11-25 08:58:10,853 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:58:10,853 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:58:10,865 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:10,866 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:10,866 INFO L424 BuchiCegarLoop]: ======== Iteration 1============ [2019-11-25 08:58:10,866 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 485 states. [2019-11-25 08:58:10,880 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 408 [2019-11-25 08:58:10,880 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:58:10,880 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:58:10,885 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:10,886 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:10,894 INFO L794 eck$LassoCheckResult]: Stem: 340#ULTIMATE.startENTRYtrue ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 301#L-1true havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 99#L853true havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 316#L384true assume !(1 == ~m_i~0);~m_st~0 := 2; 64#L391-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 363#L396-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 141#L401-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 317#L406-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 45#L411-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 433#L416-1true assume !(0 == ~M_E~0); 50#L576-1true assume !(0 == ~T1_E~0); 427#L581-1true assume !(0 == ~T2_E~0); 237#L586-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 473#L591-1true assume !(0 == ~T4_E~0); 160#L596-1true assume !(0 == ~T5_E~0); 412#L601-1true assume !(0 == ~E_1~0); 206#L606-1true assume !(0 == ~E_2~0); 76#L611-1true assume !(0 == ~E_3~0); 372#L616-1true assume !(0 == ~E_4~0); 8#L621-1true assume !(0 == ~E_5~0); 320#L626-1true havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 137#L269true assume 1 == ~m_pc~0; 69#L270true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 138#L280true is_master_triggered_#res := is_master_triggered_~__retres1~0; 70#L281true activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 88#L710true assume !(0 != activate_threads_~tmp~1); 72#L710-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 161#L288true assume 1 == ~t1_pc~0; 244#L289true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 162#L299true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 246#L300true activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 253#L718true assume !(0 != activate_threads_~tmp___0~0); 255#L718-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 303#L307true assume !(1 == ~t2_pc~0); 306#L307-2true is_transmit2_triggered_~__retres1~2 := 0; 302#L318true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 367#L319true activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 383#L726true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 368#L726-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 407#L326true assume 1 == ~t3_pc~0; 463#L327true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 406#L337true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 461#L338true activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 481#L734true assume !(0 != activate_threads_~tmp___2~0); 483#L734-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 32#L345true assume !(1 == ~t4_pc~0); 35#L345-2true is_transmit4_triggered_~__retres1~4 := 0; 31#L356true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 142#L357true activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 17#L742true assume !(0 != activate_threads_~tmp___3~0); 3#L742-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 201#L364true assume 1 == ~t5_pc~0; 147#L365true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 199#L375true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 146#L376true activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 167#L750true assume !(0 != activate_threads_~tmp___4~0); 171#L750-2true assume !(1 == ~M_E~0); 205#L639-1true assume !(1 == ~T1_E~0); 73#L644-1true assume !(1 == ~T2_E~0); 371#L649-1true assume !(1 == ~T3_E~0); 6#L654-1true assume !(1 == ~T4_E~0); 319#L659-1true assume !(1 == ~T5_E~0); 47#L664-1true assume 1 == ~E_1~0;~E_1~0 := 2; 435#L669-1true assume !(1 == ~E_2~0); 256#L674-1true assume !(1 == ~E_3~0); 485#L679-1true assume !(1 == ~E_4~0); 172#L684-1true assume !(1 == ~E_5~0); 323#L890-1true [2019-11-25 08:58:10,895 INFO L796 eck$LassoCheckResult]: Loop: 323#L890-1true assume !false; 387#L891true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 207#L551true assume !true; 10#L566true start_simulation_~kernel_st~0 := 2; 318#L384-1true start_simulation_~kernel_st~0 := 3; 40#L576-2true assume 0 == ~M_E~0;~M_E~0 := 1; 42#L576-4true assume !(0 == ~T1_E~0); 430#L581-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 247#L586-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 475#L591-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 164#L596-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 413#L601-3true assume 0 == ~E_1~0;~E_1~0 := 1; 210#L606-3true assume 0 == ~E_2~0;~E_2~0 := 1; 82#L611-3true assume 0 == ~E_3~0;~E_3~0 := 1; 377#L616-3true assume !(0 == ~E_4~0); 13#L621-3true assume 0 == ~E_5~0;~E_5~0 := 1; 322#L626-3true havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 75#L269-18true assume 1 == ~m_pc~0; 419#L270-6true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 95#L280-6true is_master_triggered_#res := is_master_triggered_~__retres1~0; 420#L281-6true activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 423#L710-18true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 424#L710-20true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 265#L288-18true assume 1 == ~t1_pc~0; 215#L289-6true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 268#L299-6true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 216#L300-6true activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 229#L718-18true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 230#L718-20true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 382#L307-18true assume !(1 == ~t2_pc~0); 384#L307-20true is_transmit2_triggered_~__retres1~2 := 0; 296#L318-6true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 331#L319-6true activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 330#L726-18true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 335#L726-20true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 480#L326-18true assume !(1 == ~t3_pc~0); 482#L326-20true is_transmit3_triggered_~__retres1~3 := 0; 403#L337-6true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 450#L338-6true activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 451#L734-18true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 455#L734-20true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15#L345-18true assume !(1 == ~t4_pc~0); 18#L345-20true is_transmit4_triggered_~__retres1~4 := 0; 26#L356-6true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 125#L357-6true activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 103#L742-18true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 107#L742-20true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 179#L364-18true assume !(1 == ~t5_pc~0); 169#L364-20true is_transmit5_triggered_~__retres1~5 := 0; 192#L375-6true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 285#L376-6true activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 288#L750-18true assume !(0 != activate_threads_~tmp___4~0); 292#L750-20true assume 1 == ~M_E~0;~M_E~0 := 2; 209#L639-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 79#L644-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 375#L649-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 11#L654-3true assume !(1 == ~T4_E~0); 321#L659-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 48#L664-3true assume 1 == ~E_1~0;~E_1~0 := 2; 438#L669-3true assume 1 == ~E_2~0;~E_2~0 := 2; 260#L674-3true assume 1 == ~E_3~0;~E_3~0 := 2; 471#L679-3true assume 1 == ~E_4~0;~E_4~0 := 2; 159#L684-3true assume 1 == ~E_5~0;~E_5~0 := 2; 411#L689-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 361#L429-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 314#L461-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 360#L462-1true start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 415#L909true assume !(0 == start_simulation_~tmp~3); 416#L909-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 365#L429-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 315#L461-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 362#L462-2true stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 98#L864true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 177#L871true stop_simulation_#res := stop_simulation_~__retres2~0; 261#L872true start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 442#L922true assume !(0 != start_simulation_~tmp___0~1); 323#L890-1true [2019-11-25 08:58:10,905 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:10,906 INFO L82 PathProgramCache]: Analyzing trace with hash -1450413925, now seen corresponding path program 1 times [2019-11-25 08:58:10,915 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:10,915 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [910202279] [2019-11-25 08:58:10,915 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:11,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:11,124 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:11,125 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [910202279] [2019-11-25 08:58:11,125 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:11,126 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:58:11,127 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1530057013] [2019-11-25 08:58:11,132 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:58:11,132 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:11,132 INFO L82 PathProgramCache]: Analyzing trace with hash -969169923, now seen corresponding path program 1 times [2019-11-25 08:58:11,133 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:11,133 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1731433538] [2019-11-25 08:58:11,133 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:11,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:11,172 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:11,172 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1731433538] [2019-11-25 08:58:11,173 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:11,173 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:58:11,174 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [349259384] [2019-11-25 08:58:11,176 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:58:11,177 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:58:11,191 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:58:11,193 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:58:11,194 INFO L87 Difference]: Start difference. First operand 485 states. Second operand 3 states. [2019-11-25 08:58:11,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:58:11,253 INFO L93 Difference]: Finished difference Result 485 states and 733 transitions. [2019-11-25 08:58:11,254 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:58:11,256 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 485 states and 733 transitions. [2019-11-25 08:58:11,264 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2019-11-25 08:58:11,275 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 485 states to 480 states and 728 transitions. [2019-11-25 08:58:11,276 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 480 [2019-11-25 08:58:11,278 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 480 [2019-11-25 08:58:11,278 INFO L73 IsDeterministic]: Start isDeterministic. Operand 480 states and 728 transitions. [2019-11-25 08:58:11,282 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:58:11,283 INFO L688 BuchiCegarLoop]: Abstraction has 480 states and 728 transitions. [2019-11-25 08:58:11,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 480 states and 728 transitions. [2019-11-25 08:58:11,332 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 480 to 480. [2019-11-25 08:58:11,333 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 480 states. [2019-11-25 08:58:11,335 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 480 states to 480 states and 728 transitions. [2019-11-25 08:58:11,337 INFO L711 BuchiCegarLoop]: Abstraction has 480 states and 728 transitions. [2019-11-25 08:58:11,337 INFO L591 BuchiCegarLoop]: Abstraction has 480 states and 728 transitions. [2019-11-25 08:58:11,337 INFO L424 BuchiCegarLoop]: ======== Iteration 2============ [2019-11-25 08:58:11,337 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 480 states and 728 transitions. [2019-11-25 08:58:11,341 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2019-11-25 08:58:11,341 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:58:11,341 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:58:11,345 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:11,345 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:11,346 INFO L794 eck$LassoCheckResult]: Stem: 1380#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 1349#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1151#L853 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1152#L384 assume 1 == ~m_i~0;~m_st~0 := 0; 1097#L391-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1098#L396-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1181#L401-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1182#L406-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1055#L411-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1056#L416-1 assume !(0 == ~M_E~0); 1067#L576-1 assume !(0 == ~T1_E~0); 1068#L581-1 assume !(0 == ~T2_E~0); 1298#L586-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1299#L591-1 assume !(0 == ~T4_E~0); 1214#L596-1 assume !(0 == ~T5_E~0); 1215#L601-1 assume !(0 == ~E_1~0); 1253#L606-1 assume !(0 == ~E_2~0); 1119#L611-1 assume !(0 == ~E_3~0); 1120#L616-1 assume !(0 == ~E_4~0); 989#L621-1 assume !(0 == ~E_5~0); 990#L626-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1177#L269 assume 1 == ~m_pc~0; 1106#L270 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1107#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1109#L281 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1110#L710 assume !(0 != activate_threads_~tmp~1); 1111#L710-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1112#L288 assume 1 == ~t1_pc~0; 1216#L289 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1218#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1219#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1312#L718 assume !(0 != activate_threads_~tmp___0~0); 1320#L718-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1321#L307 assume !(1 == ~t2_pc~0); 1352#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 1350#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1351#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1402#L726 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1403#L726-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1404#L326 assume 1 == ~t3_pc~0; 1432#L327 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1419#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1431#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1451#L734 assume !(0 != activate_threads_~tmp___2~0); 1458#L734-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1034#L345 assume !(1 == ~t4_pc~0); 1035#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 1032#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1033#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1007#L742 assume !(0 != activate_threads_~tmp___3~0); 979#L742-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 980#L364 assume 1 == ~t5_pc~0; 1187#L365 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1188#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1185#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1186#L750 assume !(0 != activate_threads_~tmp___4~0); 1224#L750-2 assume !(1 == ~M_E~0); 1231#L639-1 assume !(1 == ~T1_E~0); 1113#L644-1 assume !(1 == ~T2_E~0); 1114#L649-1 assume !(1 == ~T3_E~0); 986#L654-1 assume !(1 == ~T4_E~0); 987#L659-1 assume !(1 == ~T5_E~0); 1060#L664-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1061#L669-1 assume !(1 == ~E_2~0); 1322#L674-1 assume !(1 == ~E_3~0); 1323#L679-1 assume !(1 == ~E_4~0); 1232#L684-1 assume !(1 == ~E_5~0); 1233#L890-1 [2019-11-25 08:58:11,347 INFO L796 eck$LassoCheckResult]: Loop: 1233#L890-1 assume !false; 1366#L891 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 1065#L551 assume !false; 1254#L472 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1362#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1050#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1363#L462 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1315#L476 assume !(0 != eval_~tmp~0); 992#L566 start_simulation_~kernel_st~0 := 2; 993#L384-1 start_simulation_~kernel_st~0 := 3; 1044#L576-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1045#L576-4 assume !(0 == ~T1_E~0); 1048#L581-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1313#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1314#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1221#L596-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1222#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1257#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1131#L611-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1132#L616-3 assume !(0 == ~E_4~0); 998#L621-3 assume 0 == ~E_5~0;~E_5~0 := 1; 999#L626-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1116#L269-18 assume !(1 == ~m_pc~0); 1117#L269-20 is_master_triggered_~__retres1~0 := 0; 1142#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1147#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1436#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1437#L710-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1330#L288-18 assume 1 == ~t1_pc~0; 1265#L289-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1266#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1268#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1269#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1289#L718-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1290#L307-18 assume 1 == ~t2_pc~0; 1371#L308-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1340#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1341#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1369#L726-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1370#L726-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1376#L326-18 assume 1 == ~t3_pc~0; 1446#L327-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1426#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1427#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1444#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1445#L734-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1002#L345-18 assume 1 == ~t4_pc~0; 1003#L346-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1008#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1024#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1153#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1154#L742-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1157#L364-18 assume 1 == ~t5_pc~0; 1241#L365-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1228#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1247#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1334#L750-18 assume !(0 != activate_threads_~tmp___4~0); 1335#L750-20 assume 1 == ~M_E~0;~M_E~0 := 2; 1256#L639-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1124#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1125#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 994#L654-3 assume !(1 == ~T4_E~0); 995#L659-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1062#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1063#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1324#L674-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1325#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1212#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1213#L689-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1399#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1054#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1364#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 1398#L909 assume !(0 == start_simulation_~tmp~3); 1329#L909-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1401#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1058#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1365#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 1149#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1150#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 1239#L872 start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 1326#L922 assume !(0 != start_simulation_~tmp___0~1); 1233#L890-1 [2019-11-25 08:58:11,347 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:11,347 INFO L82 PathProgramCache]: Analyzing trace with hash -1396021027, now seen corresponding path program 1 times [2019-11-25 08:58:11,347 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:11,348 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [310150764] [2019-11-25 08:58:11,348 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:11,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:11,388 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:11,388 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [310150764] [2019-11-25 08:58:11,389 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:11,389 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:58:11,389 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1523891311] [2019-11-25 08:58:11,389 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:58:11,390 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:11,390 INFO L82 PathProgramCache]: Analyzing trace with hash -1203867808, now seen corresponding path program 1 times [2019-11-25 08:58:11,390 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:11,390 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1975273801] [2019-11-25 08:58:11,391 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:11,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:11,486 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:11,489 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1975273801] [2019-11-25 08:58:11,489 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:11,489 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:58:11,490 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [84290199] [2019-11-25 08:58:11,490 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:58:11,491 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:58:11,491 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:58:11,491 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:58:11,491 INFO L87 Difference]: Start difference. First operand 480 states and 728 transitions. cyclomatic complexity: 249 Second operand 3 states. [2019-11-25 08:58:11,514 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:58:11,515 INFO L93 Difference]: Finished difference Result 480 states and 727 transitions. [2019-11-25 08:58:11,515 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:58:11,516 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 480 states and 727 transitions. [2019-11-25 08:58:11,521 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2019-11-25 08:58:11,527 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 480 states to 480 states and 727 transitions. [2019-11-25 08:58:11,527 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 480 [2019-11-25 08:58:11,528 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 480 [2019-11-25 08:58:11,528 INFO L73 IsDeterministic]: Start isDeterministic. Operand 480 states and 727 transitions. [2019-11-25 08:58:11,531 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:58:11,531 INFO L688 BuchiCegarLoop]: Abstraction has 480 states and 727 transitions. [2019-11-25 08:58:11,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 480 states and 727 transitions. [2019-11-25 08:58:11,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 480 to 480. [2019-11-25 08:58:11,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 480 states. [2019-11-25 08:58:11,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 480 states to 480 states and 727 transitions. [2019-11-25 08:58:11,554 INFO L711 BuchiCegarLoop]: Abstraction has 480 states and 727 transitions. [2019-11-25 08:58:11,554 INFO L591 BuchiCegarLoop]: Abstraction has 480 states and 727 transitions. [2019-11-25 08:58:11,555 INFO L424 BuchiCegarLoop]: ======== Iteration 3============ [2019-11-25 08:58:11,555 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 480 states and 727 transitions. [2019-11-25 08:58:11,558 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2019-11-25 08:58:11,558 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:58:11,558 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:58:11,564 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:11,565 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:11,565 INFO L794 eck$LassoCheckResult]: Stem: 2347#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 2316#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2118#L853 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2119#L384 assume 1 == ~m_i~0;~m_st~0 := 0; 2064#L391-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2065#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2148#L401-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2149#L406-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2022#L411-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2023#L416-1 assume !(0 == ~M_E~0); 2034#L576-1 assume !(0 == ~T1_E~0); 2035#L581-1 assume !(0 == ~T2_E~0); 2265#L586-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2266#L591-1 assume !(0 == ~T4_E~0); 2181#L596-1 assume !(0 == ~T5_E~0); 2182#L601-1 assume !(0 == ~E_1~0); 2220#L606-1 assume !(0 == ~E_2~0); 2086#L611-1 assume !(0 == ~E_3~0); 2087#L616-1 assume !(0 == ~E_4~0); 1956#L621-1 assume !(0 == ~E_5~0); 1957#L626-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2144#L269 assume 1 == ~m_pc~0; 2073#L270 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2074#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2076#L281 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2077#L710 assume !(0 != activate_threads_~tmp~1); 2078#L710-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2079#L288 assume 1 == ~t1_pc~0; 2183#L289 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2185#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2186#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2279#L718 assume !(0 != activate_threads_~tmp___0~0); 2287#L718-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2288#L307 assume !(1 == ~t2_pc~0); 2319#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 2317#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2318#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2369#L726 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2370#L726-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2371#L326 assume 1 == ~t3_pc~0; 2399#L327 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2386#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2398#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2418#L734 assume !(0 != activate_threads_~tmp___2~0); 2425#L734-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2001#L345 assume !(1 == ~t4_pc~0); 2002#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 1999#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2000#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1974#L742 assume !(0 != activate_threads_~tmp___3~0); 1946#L742-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1947#L364 assume 1 == ~t5_pc~0; 2154#L365 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2155#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2152#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2153#L750 assume !(0 != activate_threads_~tmp___4~0); 2191#L750-2 assume !(1 == ~M_E~0); 2198#L639-1 assume !(1 == ~T1_E~0); 2080#L644-1 assume !(1 == ~T2_E~0); 2081#L649-1 assume !(1 == ~T3_E~0); 1953#L654-1 assume !(1 == ~T4_E~0); 1954#L659-1 assume !(1 == ~T5_E~0); 2027#L664-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2028#L669-1 assume !(1 == ~E_2~0); 2289#L674-1 assume !(1 == ~E_3~0); 2290#L679-1 assume !(1 == ~E_4~0); 2199#L684-1 assume !(1 == ~E_5~0); 2200#L890-1 [2019-11-25 08:58:11,566 INFO L796 eck$LassoCheckResult]: Loop: 2200#L890-1 assume !false; 2333#L891 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 2032#L551 assume !false; 2221#L472 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2329#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2017#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2330#L462 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2282#L476 assume !(0 != eval_~tmp~0); 1959#L566 start_simulation_~kernel_st~0 := 2; 1960#L384-1 start_simulation_~kernel_st~0 := 3; 2011#L576-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2012#L576-4 assume !(0 == ~T1_E~0); 2015#L581-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2280#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2281#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2188#L596-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2189#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2224#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2098#L611-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2099#L616-3 assume !(0 == ~E_4~0); 1965#L621-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1966#L626-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2083#L269-18 assume !(1 == ~m_pc~0); 2084#L269-20 is_master_triggered_~__retres1~0 := 0; 2109#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2114#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2403#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2404#L710-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2297#L288-18 assume 1 == ~t1_pc~0; 2232#L289-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2233#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2235#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2236#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2256#L718-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2257#L307-18 assume 1 == ~t2_pc~0; 2338#L308-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2307#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2308#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2336#L726-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2337#L726-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2343#L326-18 assume 1 == ~t3_pc~0; 2413#L327-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2393#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2394#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2411#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2412#L734-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1969#L345-18 assume 1 == ~t4_pc~0; 1970#L346-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1975#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1991#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2120#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2121#L742-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2124#L364-18 assume 1 == ~t5_pc~0; 2208#L365-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2195#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2214#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2301#L750-18 assume !(0 != activate_threads_~tmp___4~0); 2302#L750-20 assume 1 == ~M_E~0;~M_E~0 := 2; 2223#L639-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2091#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2092#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1961#L654-3 assume !(1 == ~T4_E~0); 1962#L659-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2029#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2030#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2291#L674-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2292#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2179#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2180#L689-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2366#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2021#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2331#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 2365#L909 assume !(0 == start_simulation_~tmp~3); 2296#L909-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2368#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2025#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2332#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 2116#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2117#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 2206#L872 start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 2293#L922 assume !(0 != start_simulation_~tmp___0~1); 2200#L890-1 [2019-11-25 08:58:11,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:11,566 INFO L82 PathProgramCache]: Analyzing trace with hash -2075293281, now seen corresponding path program 1 times [2019-11-25 08:58:11,566 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:11,566 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1154259373] [2019-11-25 08:58:11,566 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:11,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:11,629 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:11,630 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1154259373] [2019-11-25 08:58:11,631 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:11,631 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:58:11,632 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [263236116] [2019-11-25 08:58:11,633 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:58:11,633 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:11,633 INFO L82 PathProgramCache]: Analyzing trace with hash -1203867808, now seen corresponding path program 2 times [2019-11-25 08:58:11,633 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:11,634 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [685058787] [2019-11-25 08:58:11,634 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:11,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:11,717 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:11,717 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [685058787] [2019-11-25 08:58:11,718 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:11,718 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:58:11,718 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [176394101] [2019-11-25 08:58:11,719 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:58:11,719 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:58:11,719 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:58:11,720 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:58:11,720 INFO L87 Difference]: Start difference. First operand 480 states and 727 transitions. cyclomatic complexity: 248 Second operand 3 states. [2019-11-25 08:58:11,733 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:58:11,733 INFO L93 Difference]: Finished difference Result 480 states and 726 transitions. [2019-11-25 08:58:11,733 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:58:11,734 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 480 states and 726 transitions. [2019-11-25 08:58:11,739 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2019-11-25 08:58:11,743 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 480 states to 480 states and 726 transitions. [2019-11-25 08:58:11,744 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 480 [2019-11-25 08:58:11,744 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 480 [2019-11-25 08:58:11,745 INFO L73 IsDeterministic]: Start isDeterministic. Operand 480 states and 726 transitions. [2019-11-25 08:58:11,746 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:58:11,746 INFO L688 BuchiCegarLoop]: Abstraction has 480 states and 726 transitions. [2019-11-25 08:58:11,747 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 480 states and 726 transitions. [2019-11-25 08:58:11,755 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 480 to 480. [2019-11-25 08:58:11,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 480 states. [2019-11-25 08:58:11,757 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 480 states to 480 states and 726 transitions. [2019-11-25 08:58:11,758 INFO L711 BuchiCegarLoop]: Abstraction has 480 states and 726 transitions. [2019-11-25 08:58:11,758 INFO L591 BuchiCegarLoop]: Abstraction has 480 states and 726 transitions. [2019-11-25 08:58:11,758 INFO L424 BuchiCegarLoop]: ======== Iteration 4============ [2019-11-25 08:58:11,758 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 480 states and 726 transitions. [2019-11-25 08:58:11,761 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2019-11-25 08:58:11,762 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:58:11,765 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:58:11,769 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:11,769 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:11,769 INFO L794 eck$LassoCheckResult]: Stem: 3314#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 3283#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3085#L853 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3086#L384 assume 1 == ~m_i~0;~m_st~0 := 0; 3031#L391-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3032#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3115#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3116#L406-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2989#L411-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2990#L416-1 assume !(0 == ~M_E~0); 3001#L576-1 assume !(0 == ~T1_E~0); 3002#L581-1 assume !(0 == ~T2_E~0); 3232#L586-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3233#L591-1 assume !(0 == ~T4_E~0); 3148#L596-1 assume !(0 == ~T5_E~0); 3149#L601-1 assume !(0 == ~E_1~0); 3187#L606-1 assume !(0 == ~E_2~0); 3053#L611-1 assume !(0 == ~E_3~0); 3054#L616-1 assume !(0 == ~E_4~0); 2923#L621-1 assume !(0 == ~E_5~0); 2924#L626-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3111#L269 assume 1 == ~m_pc~0; 3040#L270 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 3041#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3043#L281 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3044#L710 assume !(0 != activate_threads_~tmp~1); 3045#L710-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3046#L288 assume 1 == ~t1_pc~0; 3150#L289 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3152#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3153#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3246#L718 assume !(0 != activate_threads_~tmp___0~0); 3254#L718-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3255#L307 assume !(1 == ~t2_pc~0); 3286#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 3284#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3285#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3336#L726 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3337#L726-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3338#L326 assume 1 == ~t3_pc~0; 3366#L327 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3353#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3365#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3385#L734 assume !(0 != activate_threads_~tmp___2~0); 3392#L734-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2968#L345 assume !(1 == ~t4_pc~0); 2969#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 2966#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2967#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2941#L742 assume !(0 != activate_threads_~tmp___3~0); 2913#L742-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2914#L364 assume 1 == ~t5_pc~0; 3121#L365 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3122#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3119#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3120#L750 assume !(0 != activate_threads_~tmp___4~0); 3158#L750-2 assume !(1 == ~M_E~0); 3165#L639-1 assume !(1 == ~T1_E~0); 3047#L644-1 assume !(1 == ~T2_E~0); 3048#L649-1 assume !(1 == ~T3_E~0); 2920#L654-1 assume !(1 == ~T4_E~0); 2921#L659-1 assume !(1 == ~T5_E~0); 2994#L664-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2995#L669-1 assume !(1 == ~E_2~0); 3256#L674-1 assume !(1 == ~E_3~0); 3257#L679-1 assume !(1 == ~E_4~0); 3166#L684-1 assume !(1 == ~E_5~0); 3167#L890-1 [2019-11-25 08:58:11,771 INFO L796 eck$LassoCheckResult]: Loop: 3167#L890-1 assume !false; 3300#L891 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 2999#L551 assume !false; 3188#L472 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3296#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2984#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3297#L462 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 3249#L476 assume !(0 != eval_~tmp~0); 2926#L566 start_simulation_~kernel_st~0 := 2; 2927#L384-1 start_simulation_~kernel_st~0 := 3; 2978#L576-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2979#L576-4 assume !(0 == ~T1_E~0); 2982#L581-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3247#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3248#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3155#L596-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3156#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3191#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3065#L611-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3066#L616-3 assume !(0 == ~E_4~0); 2932#L621-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2933#L626-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3050#L269-18 assume !(1 == ~m_pc~0); 3051#L269-20 is_master_triggered_~__retres1~0 := 0; 3076#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3081#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3370#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3371#L710-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3264#L288-18 assume !(1 == ~t1_pc~0); 3201#L288-20 is_transmit1_triggered_~__retres1~1 := 0; 3200#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3202#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3203#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3223#L718-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3224#L307-18 assume 1 == ~t2_pc~0; 3305#L308-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3274#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3275#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3303#L726-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3304#L726-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3310#L326-18 assume 1 == ~t3_pc~0; 3380#L327-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3360#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3361#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3378#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3379#L734-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2936#L345-18 assume 1 == ~t4_pc~0; 2937#L346-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2942#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2958#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3087#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3088#L742-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3091#L364-18 assume 1 == ~t5_pc~0; 3175#L365-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3162#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3181#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3268#L750-18 assume !(0 != activate_threads_~tmp___4~0); 3269#L750-20 assume 1 == ~M_E~0;~M_E~0 := 2; 3190#L639-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3058#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3059#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2928#L654-3 assume !(1 == ~T4_E~0); 2929#L659-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2996#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2997#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3258#L674-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3259#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3146#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3147#L689-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3333#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2988#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3298#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 3332#L909 assume !(0 == start_simulation_~tmp~3); 3263#L909-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3335#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2992#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3299#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 3083#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3084#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 3173#L872 start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 3260#L922 assume !(0 != start_simulation_~tmp___0~1); 3167#L890-1 [2019-11-25 08:58:11,771 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:11,772 INFO L82 PathProgramCache]: Analyzing trace with hash 258099357, now seen corresponding path program 1 times [2019-11-25 08:58:11,772 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:11,772 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1932821264] [2019-11-25 08:58:11,773 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:11,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:11,826 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:11,827 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1932821264] [2019-11-25 08:58:11,827 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:11,827 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:58:11,827 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [548705379] [2019-11-25 08:58:11,827 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:58:11,827 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:11,828 INFO L82 PathProgramCache]: Analyzing trace with hash -1477646303, now seen corresponding path program 1 times [2019-11-25 08:58:11,828 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:11,828 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [996114067] [2019-11-25 08:58:11,828 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:11,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:11,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:11,866 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [996114067] [2019-11-25 08:58:11,867 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:11,867 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:58:11,867 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1225404926] [2019-11-25 08:58:11,868 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:58:11,868 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:58:11,868 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:58:11,868 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:58:11,868 INFO L87 Difference]: Start difference. First operand 480 states and 726 transitions. cyclomatic complexity: 247 Second operand 3 states. [2019-11-25 08:58:11,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:58:11,880 INFO L93 Difference]: Finished difference Result 480 states and 725 transitions. [2019-11-25 08:58:11,880 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:58:11,881 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 480 states and 725 transitions. [2019-11-25 08:58:11,885 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2019-11-25 08:58:11,889 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 480 states to 480 states and 725 transitions. [2019-11-25 08:58:11,889 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 480 [2019-11-25 08:58:11,890 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 480 [2019-11-25 08:58:11,890 INFO L73 IsDeterministic]: Start isDeterministic. Operand 480 states and 725 transitions. [2019-11-25 08:58:11,891 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:58:11,891 INFO L688 BuchiCegarLoop]: Abstraction has 480 states and 725 transitions. [2019-11-25 08:58:11,892 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 480 states and 725 transitions. [2019-11-25 08:58:11,899 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 480 to 480. [2019-11-25 08:58:11,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 480 states. [2019-11-25 08:58:11,902 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 480 states to 480 states and 725 transitions. [2019-11-25 08:58:11,902 INFO L711 BuchiCegarLoop]: Abstraction has 480 states and 725 transitions. [2019-11-25 08:58:11,902 INFO L591 BuchiCegarLoop]: Abstraction has 480 states and 725 transitions. [2019-11-25 08:58:11,902 INFO L424 BuchiCegarLoop]: ======== Iteration 5============ [2019-11-25 08:58:11,903 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 480 states and 725 transitions. [2019-11-25 08:58:11,906 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2019-11-25 08:58:11,906 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:58:11,906 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:58:11,908 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:11,908 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:11,909 INFO L794 eck$LassoCheckResult]: Stem: 4281#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 4250#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4052#L853 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4053#L384 assume 1 == ~m_i~0;~m_st~0 := 0; 3998#L391-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3999#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4082#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4083#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3956#L411-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3957#L416-1 assume !(0 == ~M_E~0); 3968#L576-1 assume !(0 == ~T1_E~0); 3969#L581-1 assume !(0 == ~T2_E~0); 4199#L586-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4200#L591-1 assume !(0 == ~T4_E~0); 4115#L596-1 assume !(0 == ~T5_E~0); 4116#L601-1 assume !(0 == ~E_1~0); 4154#L606-1 assume !(0 == ~E_2~0); 4020#L611-1 assume !(0 == ~E_3~0); 4021#L616-1 assume !(0 == ~E_4~0); 3890#L621-1 assume !(0 == ~E_5~0); 3891#L626-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4078#L269 assume 1 == ~m_pc~0; 4007#L270 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 4008#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4010#L281 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4011#L710 assume !(0 != activate_threads_~tmp~1); 4012#L710-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4013#L288 assume 1 == ~t1_pc~0; 4117#L289 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4119#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4120#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4213#L718 assume !(0 != activate_threads_~tmp___0~0); 4221#L718-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4222#L307 assume !(1 == ~t2_pc~0); 4253#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 4251#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4252#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4303#L726 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4304#L726-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4305#L326 assume 1 == ~t3_pc~0; 4333#L327 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4320#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4332#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4352#L734 assume !(0 != activate_threads_~tmp___2~0); 4359#L734-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3935#L345 assume !(1 == ~t4_pc~0); 3936#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 3933#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3934#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3908#L742 assume !(0 != activate_threads_~tmp___3~0); 3880#L742-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3881#L364 assume 1 == ~t5_pc~0; 4088#L365 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4089#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4086#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4087#L750 assume !(0 != activate_threads_~tmp___4~0); 4125#L750-2 assume !(1 == ~M_E~0); 4132#L639-1 assume !(1 == ~T1_E~0); 4014#L644-1 assume !(1 == ~T2_E~0); 4015#L649-1 assume !(1 == ~T3_E~0); 3887#L654-1 assume !(1 == ~T4_E~0); 3888#L659-1 assume !(1 == ~T5_E~0); 3961#L664-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3962#L669-1 assume !(1 == ~E_2~0); 4223#L674-1 assume !(1 == ~E_3~0); 4224#L679-1 assume !(1 == ~E_4~0); 4133#L684-1 assume !(1 == ~E_5~0); 4134#L890-1 [2019-11-25 08:58:11,909 INFO L796 eck$LassoCheckResult]: Loop: 4134#L890-1 assume !false; 4267#L891 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 3966#L551 assume !false; 4155#L472 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4263#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3951#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4264#L462 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 4216#L476 assume !(0 != eval_~tmp~0); 3893#L566 start_simulation_~kernel_st~0 := 2; 3894#L384-1 start_simulation_~kernel_st~0 := 3; 3945#L576-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3946#L576-4 assume !(0 == ~T1_E~0); 3949#L581-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4214#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4215#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4122#L596-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4123#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4158#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4032#L611-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4033#L616-3 assume !(0 == ~E_4~0); 3899#L621-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3900#L626-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4017#L269-18 assume !(1 == ~m_pc~0); 4018#L269-20 is_master_triggered_~__retres1~0 := 0; 4043#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4048#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4337#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4338#L710-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4231#L288-18 assume 1 == ~t1_pc~0; 4166#L289-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4167#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4169#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4170#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4190#L718-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4191#L307-18 assume 1 == ~t2_pc~0; 4272#L308-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4241#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4242#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4270#L726-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4271#L726-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4277#L326-18 assume 1 == ~t3_pc~0; 4347#L327-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4327#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4328#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4345#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4346#L734-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3903#L345-18 assume 1 == ~t4_pc~0; 3904#L346-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3909#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3925#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4054#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4055#L742-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4058#L364-18 assume !(1 == ~t5_pc~0); 4128#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 4129#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4148#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4235#L750-18 assume !(0 != activate_threads_~tmp___4~0); 4236#L750-20 assume 1 == ~M_E~0;~M_E~0 := 2; 4157#L639-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4025#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4026#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3895#L654-3 assume !(1 == ~T4_E~0); 3896#L659-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3963#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3964#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4225#L674-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4226#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4113#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4114#L689-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4300#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3955#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4265#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 4299#L909 assume !(0 == start_simulation_~tmp~3); 4230#L909-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4302#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3959#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4266#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 4050#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4051#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 4140#L872 start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 4227#L922 assume !(0 != start_simulation_~tmp___0~1); 4134#L890-1 [2019-11-25 08:58:11,909 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:11,910 INFO L82 PathProgramCache]: Analyzing trace with hash 56275423, now seen corresponding path program 1 times [2019-11-25 08:58:11,910 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:11,910 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [926588296] [2019-11-25 08:58:11,910 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:11,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:11,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:11,936 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [926588296] [2019-11-25 08:58:11,937 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:11,937 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:58:11,937 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1595739917] [2019-11-25 08:58:11,938 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:58:11,938 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:11,938 INFO L82 PathProgramCache]: Analyzing trace with hash 2119424801, now seen corresponding path program 1 times [2019-11-25 08:58:11,938 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:11,939 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [620318203] [2019-11-25 08:58:11,939 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:11,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:11,986 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:11,986 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [620318203] [2019-11-25 08:58:11,987 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:11,987 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:58:11,987 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [778200275] [2019-11-25 08:58:11,988 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:58:11,988 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:58:11,988 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:58:11,988 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:58:11,989 INFO L87 Difference]: Start difference. First operand 480 states and 725 transitions. cyclomatic complexity: 246 Second operand 3 states. [2019-11-25 08:58:12,001 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:58:12,002 INFO L93 Difference]: Finished difference Result 480 states and 724 transitions. [2019-11-25 08:58:12,002 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:58:12,002 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 480 states and 724 transitions. [2019-11-25 08:58:12,007 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2019-11-25 08:58:12,011 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 480 states to 480 states and 724 transitions. [2019-11-25 08:58:12,012 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 480 [2019-11-25 08:58:12,012 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 480 [2019-11-25 08:58:12,012 INFO L73 IsDeterministic]: Start isDeterministic. Operand 480 states and 724 transitions. [2019-11-25 08:58:12,013 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:58:12,014 INFO L688 BuchiCegarLoop]: Abstraction has 480 states and 724 transitions. [2019-11-25 08:58:12,015 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 480 states and 724 transitions. [2019-11-25 08:58:12,022 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 480 to 480. [2019-11-25 08:58:12,022 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 480 states. [2019-11-25 08:58:12,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 480 states to 480 states and 724 transitions. [2019-11-25 08:58:12,025 INFO L711 BuchiCegarLoop]: Abstraction has 480 states and 724 transitions. [2019-11-25 08:58:12,025 INFO L591 BuchiCegarLoop]: Abstraction has 480 states and 724 transitions. [2019-11-25 08:58:12,025 INFO L424 BuchiCegarLoop]: ======== Iteration 6============ [2019-11-25 08:58:12,025 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 480 states and 724 transitions. [2019-11-25 08:58:12,028 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2019-11-25 08:58:12,029 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:58:12,029 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:58:12,030 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:12,031 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:12,031 INFO L794 eck$LassoCheckResult]: Stem: 5248#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 5217#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5019#L853 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5020#L384 assume 1 == ~m_i~0;~m_st~0 := 0; 4965#L391-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4966#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5049#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5050#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4923#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4924#L416-1 assume !(0 == ~M_E~0); 4935#L576-1 assume !(0 == ~T1_E~0); 4936#L581-1 assume !(0 == ~T2_E~0); 5166#L586-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5167#L591-1 assume !(0 == ~T4_E~0); 5082#L596-1 assume !(0 == ~T5_E~0); 5083#L601-1 assume !(0 == ~E_1~0); 5121#L606-1 assume !(0 == ~E_2~0); 4987#L611-1 assume !(0 == ~E_3~0); 4988#L616-1 assume !(0 == ~E_4~0); 4857#L621-1 assume !(0 == ~E_5~0); 4858#L626-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5045#L269 assume 1 == ~m_pc~0; 4974#L270 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 4975#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4977#L281 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4978#L710 assume !(0 != activate_threads_~tmp~1); 4979#L710-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4980#L288 assume 1 == ~t1_pc~0; 5084#L289 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5086#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5087#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5180#L718 assume !(0 != activate_threads_~tmp___0~0); 5188#L718-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5189#L307 assume !(1 == ~t2_pc~0); 5220#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 5218#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5219#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5270#L726 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5271#L726-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5272#L326 assume 1 == ~t3_pc~0; 5300#L327 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5287#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5299#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5319#L734 assume !(0 != activate_threads_~tmp___2~0); 5326#L734-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4902#L345 assume !(1 == ~t4_pc~0); 4903#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 4900#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4901#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4875#L742 assume !(0 != activate_threads_~tmp___3~0); 4847#L742-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4848#L364 assume 1 == ~t5_pc~0; 5055#L365 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5056#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5053#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5054#L750 assume !(0 != activate_threads_~tmp___4~0); 5092#L750-2 assume !(1 == ~M_E~0); 5099#L639-1 assume !(1 == ~T1_E~0); 4981#L644-1 assume !(1 == ~T2_E~0); 4982#L649-1 assume !(1 == ~T3_E~0); 4854#L654-1 assume !(1 == ~T4_E~0); 4855#L659-1 assume !(1 == ~T5_E~0); 4928#L664-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4929#L669-1 assume !(1 == ~E_2~0); 5190#L674-1 assume !(1 == ~E_3~0); 5191#L679-1 assume !(1 == ~E_4~0); 5100#L684-1 assume !(1 == ~E_5~0); 5101#L890-1 [2019-11-25 08:58:12,031 INFO L796 eck$LassoCheckResult]: Loop: 5101#L890-1 assume !false; 5234#L891 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 4933#L551 assume !false; 5122#L472 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5230#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4918#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5231#L462 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 5183#L476 assume !(0 != eval_~tmp~0); 4860#L566 start_simulation_~kernel_st~0 := 2; 4861#L384-1 start_simulation_~kernel_st~0 := 3; 4912#L576-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4913#L576-4 assume !(0 == ~T1_E~0); 4916#L581-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5181#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5182#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5089#L596-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5090#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5125#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4999#L611-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5000#L616-3 assume !(0 == ~E_4~0); 4866#L621-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4867#L626-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4984#L269-18 assume !(1 == ~m_pc~0); 4985#L269-20 is_master_triggered_~__retres1~0 := 0; 5010#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5015#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 5304#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5305#L710-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5198#L288-18 assume 1 == ~t1_pc~0; 5133#L289-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5134#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5136#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5137#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5157#L718-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5158#L307-18 assume 1 == ~t2_pc~0; 5239#L308-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5208#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5209#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5237#L726-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5238#L726-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5244#L326-18 assume 1 == ~t3_pc~0; 5314#L327-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5294#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5295#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5312#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5313#L734-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4870#L345-18 assume 1 == ~t4_pc~0; 4871#L346-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4876#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4892#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5021#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5022#L742-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5025#L364-18 assume 1 == ~t5_pc~0; 5109#L365-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5096#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5115#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5202#L750-18 assume !(0 != activate_threads_~tmp___4~0); 5203#L750-20 assume 1 == ~M_E~0;~M_E~0 := 2; 5124#L639-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4992#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4993#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4862#L654-3 assume !(1 == ~T4_E~0); 4863#L659-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4930#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4931#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5192#L674-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5193#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5080#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5081#L689-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5267#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4922#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5232#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 5266#L909 assume !(0 == start_simulation_~tmp~3); 5197#L909-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5269#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4926#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5233#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 5017#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5018#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 5107#L872 start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 5194#L922 assume !(0 != start_simulation_~tmp___0~1); 5101#L890-1 [2019-11-25 08:58:12,032 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:12,032 INFO L82 PathProgramCache]: Analyzing trace with hash -504424355, now seen corresponding path program 1 times [2019-11-25 08:58:12,032 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:12,032 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [173314451] [2019-11-25 08:58:12,033 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:12,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:12,073 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:12,073 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [173314451] [2019-11-25 08:58:12,074 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:12,074 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:58:12,074 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1730778704] [2019-11-25 08:58:12,075 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:58:12,075 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:12,075 INFO L82 PathProgramCache]: Analyzing trace with hash -1203867808, now seen corresponding path program 3 times [2019-11-25 08:58:12,076 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:12,077 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1359151956] [2019-11-25 08:58:12,077 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:12,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:12,156 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:12,157 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1359151956] [2019-11-25 08:58:12,157 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:12,157 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:58:12,157 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2041623003] [2019-11-25 08:58:12,158 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:58:12,158 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:58:12,158 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:58:12,158 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:58:12,158 INFO L87 Difference]: Start difference. First operand 480 states and 724 transitions. cyclomatic complexity: 245 Second operand 3 states. [2019-11-25 08:58:12,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:58:12,184 INFO L93 Difference]: Finished difference Result 480 states and 719 transitions. [2019-11-25 08:58:12,185 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:58:12,185 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 480 states and 719 transitions. [2019-11-25 08:58:12,189 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2019-11-25 08:58:12,193 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 480 states to 480 states and 719 transitions. [2019-11-25 08:58:12,193 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 480 [2019-11-25 08:58:12,194 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 480 [2019-11-25 08:58:12,194 INFO L73 IsDeterministic]: Start isDeterministic. Operand 480 states and 719 transitions. [2019-11-25 08:58:12,195 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:58:12,195 INFO L688 BuchiCegarLoop]: Abstraction has 480 states and 719 transitions. [2019-11-25 08:58:12,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 480 states and 719 transitions. [2019-11-25 08:58:12,202 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 480 to 480. [2019-11-25 08:58:12,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 480 states. [2019-11-25 08:58:12,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 480 states to 480 states and 719 transitions. [2019-11-25 08:58:12,205 INFO L711 BuchiCegarLoop]: Abstraction has 480 states and 719 transitions. [2019-11-25 08:58:12,205 INFO L591 BuchiCegarLoop]: Abstraction has 480 states and 719 transitions. [2019-11-25 08:58:12,205 INFO L424 BuchiCegarLoop]: ======== Iteration 7============ [2019-11-25 08:58:12,205 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 480 states and 719 transitions. [2019-11-25 08:58:12,208 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2019-11-25 08:58:12,208 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:58:12,208 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:58:12,210 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:12,210 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:12,210 INFO L794 eck$LassoCheckResult]: Stem: 6215#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 6184#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5986#L853 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5987#L384 assume 1 == ~m_i~0;~m_st~0 := 0; 5932#L391-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5933#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6016#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6017#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5890#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5891#L416-1 assume !(0 == ~M_E~0); 5902#L576-1 assume !(0 == ~T1_E~0); 5903#L581-1 assume !(0 == ~T2_E~0); 6133#L586-1 assume !(0 == ~T3_E~0); 6134#L591-1 assume !(0 == ~T4_E~0); 6049#L596-1 assume !(0 == ~T5_E~0); 6050#L601-1 assume !(0 == ~E_1~0); 6088#L606-1 assume !(0 == ~E_2~0); 5954#L611-1 assume !(0 == ~E_3~0); 5955#L616-1 assume !(0 == ~E_4~0); 5824#L621-1 assume !(0 == ~E_5~0); 5825#L626-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6012#L269 assume 1 == ~m_pc~0; 5941#L270 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 5942#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5944#L281 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 5945#L710 assume !(0 != activate_threads_~tmp~1); 5946#L710-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5947#L288 assume 1 == ~t1_pc~0; 6051#L289 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 6053#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6054#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6147#L718 assume !(0 != activate_threads_~tmp___0~0); 6155#L718-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6156#L307 assume !(1 == ~t2_pc~0); 6187#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 6185#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6186#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 6237#L726 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6238#L726-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6239#L326 assume 1 == ~t3_pc~0; 6267#L327 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6254#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6266#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6286#L734 assume !(0 != activate_threads_~tmp___2~0); 6293#L734-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5869#L345 assume !(1 == ~t4_pc~0); 5870#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 5867#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5868#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5842#L742 assume !(0 != activate_threads_~tmp___3~0); 5814#L742-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5815#L364 assume 1 == ~t5_pc~0; 6022#L365 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 6023#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6020#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6021#L750 assume !(0 != activate_threads_~tmp___4~0); 6059#L750-2 assume !(1 == ~M_E~0); 6066#L639-1 assume !(1 == ~T1_E~0); 5948#L644-1 assume !(1 == ~T2_E~0); 5949#L649-1 assume !(1 == ~T3_E~0); 5821#L654-1 assume !(1 == ~T4_E~0); 5822#L659-1 assume !(1 == ~T5_E~0); 5895#L664-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5896#L669-1 assume !(1 == ~E_2~0); 6157#L674-1 assume !(1 == ~E_3~0); 6158#L679-1 assume !(1 == ~E_4~0); 6067#L684-1 assume !(1 == ~E_5~0); 6068#L890-1 [2019-11-25 08:58:12,210 INFO L796 eck$LassoCheckResult]: Loop: 6068#L890-1 assume !false; 6201#L891 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 5900#L551 assume !false; 6089#L472 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6197#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5885#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6198#L462 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 6150#L476 assume !(0 != eval_~tmp~0); 5827#L566 start_simulation_~kernel_st~0 := 2; 5828#L384-1 start_simulation_~kernel_st~0 := 3; 5879#L576-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5880#L576-4 assume !(0 == ~T1_E~0); 5883#L581-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6148#L586-3 assume !(0 == ~T3_E~0); 6149#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6056#L596-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6057#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6092#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5966#L611-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5967#L616-3 assume !(0 == ~E_4~0); 5833#L621-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5834#L626-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5951#L269-18 assume !(1 == ~m_pc~0); 5952#L269-20 is_master_triggered_~__retres1~0 := 0; 5977#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5982#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 6271#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6272#L710-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6165#L288-18 assume 1 == ~t1_pc~0; 6100#L289-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 6101#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6103#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6104#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6124#L718-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6125#L307-18 assume 1 == ~t2_pc~0; 6206#L308-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6175#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6176#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 6204#L726-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6205#L726-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6211#L326-18 assume 1 == ~t3_pc~0; 6281#L327-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6261#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6262#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6279#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6280#L734-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5837#L345-18 assume 1 == ~t4_pc~0; 5838#L346-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5843#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5859#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5988#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5989#L742-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5992#L364-18 assume 1 == ~t5_pc~0; 6076#L365-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 6063#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6082#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6169#L750-18 assume !(0 != activate_threads_~tmp___4~0); 6170#L750-20 assume 1 == ~M_E~0;~M_E~0 := 2; 6091#L639-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5959#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5960#L649-3 assume !(1 == ~T3_E~0); 5829#L654-3 assume !(1 == ~T4_E~0); 5830#L659-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5897#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5898#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6159#L674-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6160#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6047#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6048#L689-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6234#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5889#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6199#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 6233#L909 assume !(0 == start_simulation_~tmp~3); 6164#L909-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6236#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5893#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6200#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 5984#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5985#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 6074#L872 start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 6161#L922 assume !(0 != start_simulation_~tmp___0~1); 6068#L890-1 [2019-11-25 08:58:12,211 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:12,211 INFO L82 PathProgramCache]: Analyzing trace with hash 882361055, now seen corresponding path program 1 times [2019-11-25 08:58:12,211 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:12,211 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1073279771] [2019-11-25 08:58:12,212 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:12,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:12,233 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:12,233 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1073279771] [2019-11-25 08:58:12,234 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:12,234 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:58:12,234 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [640456924] [2019-11-25 08:58:12,234 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:58:12,234 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:12,235 INFO L82 PathProgramCache]: Analyzing trace with hash 172774176, now seen corresponding path program 1 times [2019-11-25 08:58:12,235 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:12,235 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1472282196] [2019-11-25 08:58:12,235 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:12,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:12,270 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:12,270 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1472282196] [2019-11-25 08:58:12,270 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:12,271 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:58:12,271 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [98201642] [2019-11-25 08:58:12,271 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:58:12,271 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:58:12,272 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:58:12,272 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:58:12,272 INFO L87 Difference]: Start difference. First operand 480 states and 719 transitions. cyclomatic complexity: 240 Second operand 3 states. [2019-11-25 08:58:12,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:58:12,344 INFO L93 Difference]: Finished difference Result 879 states and 1301 transitions. [2019-11-25 08:58:12,344 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:58:12,345 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 879 states and 1301 transitions. [2019-11-25 08:58:12,351 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 805 [2019-11-25 08:58:12,359 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 879 states to 879 states and 1301 transitions. [2019-11-25 08:58:12,359 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 879 [2019-11-25 08:58:12,360 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 879 [2019-11-25 08:58:12,360 INFO L73 IsDeterministic]: Start isDeterministic. Operand 879 states and 1301 transitions. [2019-11-25 08:58:12,362 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:58:12,362 INFO L688 BuchiCegarLoop]: Abstraction has 879 states and 1301 transitions. [2019-11-25 08:58:12,363 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 879 states and 1301 transitions. [2019-11-25 08:58:12,377 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 879 to 837. [2019-11-25 08:58:12,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 837 states. [2019-11-25 08:58:12,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 837 states to 837 states and 1243 transitions. [2019-11-25 08:58:12,381 INFO L711 BuchiCegarLoop]: Abstraction has 837 states and 1243 transitions. [2019-11-25 08:58:12,381 INFO L591 BuchiCegarLoop]: Abstraction has 837 states and 1243 transitions. [2019-11-25 08:58:12,381 INFO L424 BuchiCegarLoop]: ======== Iteration 8============ [2019-11-25 08:58:12,382 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 837 states and 1243 transitions. [2019-11-25 08:58:12,386 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 763 [2019-11-25 08:58:12,386 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:58:12,386 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:58:12,387 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:12,387 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:12,388 INFO L794 eck$LassoCheckResult]: Stem: 7596#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 7562#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7350#L853 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7351#L384 assume 1 == ~m_i~0;~m_st~0 := 0; 7299#L391-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7300#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7389#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7390#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7257#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7258#L416-1 assume !(0 == ~M_E~0); 7269#L576-1 assume !(0 == ~T1_E~0); 7270#L581-1 assume !(0 == ~T2_E~0); 7509#L586-1 assume !(0 == ~T3_E~0); 7510#L591-1 assume !(0 == ~T4_E~0); 7422#L596-1 assume !(0 == ~T5_E~0); 7423#L601-1 assume !(0 == ~E_1~0); 7463#L606-1 assume !(0 == ~E_2~0); 7317#L611-1 assume !(0 == ~E_3~0); 7318#L616-1 assume !(0 == ~E_4~0); 7190#L621-1 assume !(0 == ~E_5~0); 7191#L626-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7385#L269 assume !(1 == ~m_pc~0); 7375#L269-2 is_master_triggered_~__retres1~0 := 0; 7376#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7308#L281 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 7309#L710 assume !(0 != activate_threads_~tmp~1); 7310#L710-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7311#L288 assume 1 == ~t1_pc~0; 7424#L289 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7426#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7427#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 7523#L718 assume !(0 != activate_threads_~tmp___0~0); 7531#L718-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7532#L307 assume !(1 == ~t2_pc~0); 7565#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 7563#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7564#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7622#L726 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7623#L726-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7624#L326 assume 1 == ~t3_pc~0; 7655#L327 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7642#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7654#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7682#L734 assume !(0 != activate_threads_~tmp___2~0); 7690#L734-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7235#L345 assume !(1 == ~t4_pc~0); 7236#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 7233#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7234#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7208#L742 assume !(0 != activate_threads_~tmp___3~0); 7180#L742-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7181#L364 assume 1 == ~t5_pc~0; 7395#L365 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 7396#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7393#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7394#L750 assume !(0 != activate_threads_~tmp___4~0); 7432#L750-2 assume !(1 == ~M_E~0); 7439#L639-1 assume !(1 == ~T1_E~0); 7312#L644-1 assume !(1 == ~T2_E~0); 7313#L649-1 assume !(1 == ~T3_E~0); 7187#L654-1 assume !(1 == ~T4_E~0); 7188#L659-1 assume !(1 == ~T5_E~0); 7262#L664-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7263#L669-1 assume !(1 == ~E_2~0); 7533#L674-1 assume !(1 == ~E_3~0); 7534#L679-1 assume !(1 == ~E_4~0); 7440#L684-1 assume !(1 == ~E_5~0); 7441#L890-1 [2019-11-25 08:58:12,388 INFO L796 eck$LassoCheckResult]: Loop: 7441#L890-1 assume !false; 7629#L891 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 7267#L551 assume !false; 7464#L472 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7575#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7252#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7576#L462 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 7526#L476 assume !(0 != eval_~tmp~0); 7193#L566 start_simulation_~kernel_st~0 := 2; 7194#L384-1 start_simulation_~kernel_st~0 := 3; 7246#L576-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7247#L576-4 assume !(0 == ~T1_E~0); 7250#L581-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7524#L586-3 assume !(0 == ~T3_E~0); 7525#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7429#L596-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7430#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7467#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7329#L611-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7330#L616-3 assume !(0 == ~E_4~0); 7199#L621-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7200#L626-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7315#L269-18 assume !(1 == ~m_pc~0); 7316#L269-20 is_master_triggered_~__retres1~0 := 0; 7339#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7346#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 7664#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7668#L710-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7542#L288-18 assume 1 == ~t1_pc~0; 7475#L289-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7476#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7478#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 7479#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7500#L718-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7501#L307-18 assume 1 == ~t2_pc~0; 7587#L308-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7553#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7554#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7585#L726-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7586#L726-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7592#L326-18 assume 1 == ~t3_pc~0; 7677#L327-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7649#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7650#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7675#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7676#L734-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7203#L345-18 assume 1 == ~t4_pc~0; 7204#L346-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7209#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7225#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7354#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 7355#L742-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7358#L364-18 assume 1 == ~t5_pc~0; 7449#L365-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 7436#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7456#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7547#L750-18 assume !(0 != activate_threads_~tmp___4~0); 7548#L750-20 assume 1 == ~M_E~0;~M_E~0 := 2; 7466#L639-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7322#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7323#L649-3 assume !(1 == ~T3_E~0); 7195#L654-3 assume !(1 == ~T4_E~0); 7196#L659-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7264#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7265#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7535#L674-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7536#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7420#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7421#L689-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7618#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7256#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7577#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 7617#L909 assume !(0 == start_simulation_~tmp~3); 7658#L909-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7621#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7260#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7619#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 7348#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7349#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 7447#L872 start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 7930#L922 assume !(0 != start_simulation_~tmp___0~1); 7441#L890-1 [2019-11-25 08:58:12,388 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:12,389 INFO L82 PathProgramCache]: Analyzing trace with hash -425643714, now seen corresponding path program 1 times [2019-11-25 08:58:12,389 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:12,389 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1733355580] [2019-11-25 08:58:12,389 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:12,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:12,415 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:12,415 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1733355580] [2019-11-25 08:58:12,415 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:12,415 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:58:12,416 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1887160404] [2019-11-25 08:58:12,416 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:58:12,416 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:12,416 INFO L82 PathProgramCache]: Analyzing trace with hash 172774176, now seen corresponding path program 2 times [2019-11-25 08:58:12,417 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:12,417 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [15280675] [2019-11-25 08:58:12,417 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:12,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:12,449 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:12,449 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [15280675] [2019-11-25 08:58:12,451 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:12,452 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:58:12,452 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [775820618] [2019-11-25 08:58:12,452 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:58:12,452 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:58:12,453 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:58:12,453 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:58:12,453 INFO L87 Difference]: Start difference. First operand 837 states and 1243 transitions. cyclomatic complexity: 408 Second operand 3 states. [2019-11-25 08:58:12,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:58:12,527 INFO L93 Difference]: Finished difference Result 1505 states and 2220 transitions. [2019-11-25 08:58:12,527 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:58:12,528 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1505 states and 2220 transitions. [2019-11-25 08:58:12,540 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1426 [2019-11-25 08:58:12,552 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1505 states to 1505 states and 2220 transitions. [2019-11-25 08:58:12,553 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1505 [2019-11-25 08:58:12,554 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1505 [2019-11-25 08:58:12,555 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1505 states and 2220 transitions. [2019-11-25 08:58:12,557 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:58:12,557 INFO L688 BuchiCegarLoop]: Abstraction has 1505 states and 2220 transitions. [2019-11-25 08:58:12,559 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1505 states and 2220 transitions. [2019-11-25 08:58:12,584 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1505 to 1501. [2019-11-25 08:58:12,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1501 states. [2019-11-25 08:58:12,591 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1501 states to 1501 states and 2216 transitions. [2019-11-25 08:58:12,591 INFO L711 BuchiCegarLoop]: Abstraction has 1501 states and 2216 transitions. [2019-11-25 08:58:12,592 INFO L591 BuchiCegarLoop]: Abstraction has 1501 states and 2216 transitions. [2019-11-25 08:58:12,592 INFO L424 BuchiCegarLoop]: ======== Iteration 9============ [2019-11-25 08:58:12,592 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1501 states and 2216 transitions. [2019-11-25 08:58:12,601 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1422 [2019-11-25 08:58:12,601 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:58:12,602 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:58:12,603 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:12,603 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:12,604 INFO L794 eck$LassoCheckResult]: Stem: 9970#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 9931#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9699#L853 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9700#L384 assume 1 == ~m_i~0;~m_st~0 := 0; 9650#L391-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9651#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9737#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9738#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9605#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9606#L416-1 assume !(0 == ~M_E~0); 9617#L576-1 assume !(0 == ~T1_E~0); 9618#L581-1 assume !(0 == ~T2_E~0); 9869#L586-1 assume !(0 == ~T3_E~0); 9870#L591-1 assume !(0 == ~T4_E~0); 9770#L596-1 assume !(0 == ~T5_E~0); 9771#L601-1 assume !(0 == ~E_1~0); 9815#L606-1 assume !(0 == ~E_2~0); 9665#L611-1 assume !(0 == ~E_3~0); 9666#L616-1 assume !(0 == ~E_4~0); 9539#L621-1 assume !(0 == ~E_5~0); 9540#L626-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9733#L269 assume !(1 == ~m_pc~0); 9724#L269-2 is_master_triggered_~__retres1~0 := 0; 9725#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9656#L281 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 9657#L710 assume !(0 != activate_threads_~tmp~1); 9658#L710-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9659#L288 assume !(1 == ~t1_pc~0); 9772#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 9775#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9776#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 9883#L718 assume !(0 != activate_threads_~tmp___0~0); 9892#L718-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9893#L307 assume !(1 == ~t2_pc~0); 9934#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 9932#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9933#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 10002#L726 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 10003#L726-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10004#L326 assume 1 == ~t3_pc~0; 10037#L327 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 10022#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10035#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 10069#L734 assume !(0 != activate_threads_~tmp___2~0); 10078#L734-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9584#L345 assume !(1 == ~t4_pc~0); 9585#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 9582#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9583#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9557#L742 assume !(0 != activate_threads_~tmp___3~0); 9532#L742-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9533#L364 assume 1 == ~t5_pc~0; 9743#L365 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 9744#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9741#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9742#L750 assume !(0 != activate_threads_~tmp___4~0); 9783#L750-2 assume !(1 == ~M_E~0); 9788#L639-1 assume !(1 == ~T1_E~0); 9661#L644-1 assume !(1 == ~T2_E~0); 9662#L649-1 assume !(1 == ~T3_E~0); 9536#L654-1 assume !(1 == ~T4_E~0); 9537#L659-1 assume !(1 == ~T5_E~0); 9610#L664-1 assume 1 == ~E_1~0;~E_1~0 := 2; 9611#L669-1 assume !(1 == ~E_2~0); 9896#L674-1 assume !(1 == ~E_3~0); 9897#L679-1 assume !(1 == ~E_4~0); 9789#L684-1 assume !(1 == ~E_5~0); 9790#L890-1 [2019-11-25 08:58:12,604 INFO L796 eck$LassoCheckResult]: Loop: 9790#L890-1 assume !false; 10009#L891 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 9615#L551 assume !false; 9816#L472 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9945#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 9946#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9947#L462 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 10667#L476 assume !(0 != eval_~tmp~0); 10666#L566 start_simulation_~kernel_st~0 := 2; 10665#L384-1 start_simulation_~kernel_st~0 := 3; 10664#L576-2 assume 0 == ~M_E~0;~M_E~0 := 1; 10663#L576-4 assume !(0 == ~T1_E~0); 10662#L581-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10660#L586-3 assume !(0 == ~T3_E~0); 10077#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9777#L596-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9778#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9819#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9674#L611-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9675#L616-3 assume !(0 == ~E_4~0); 10647#L621-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10645#L626-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9663#L269-18 assume !(1 == ~m_pc~0); 9664#L269-20 is_master_triggered_~__retres1~0 := 0; 10903#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10902#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 10901#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 10900#L710-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10899#L288-18 assume !(1 == ~t1_pc~0); 10898#L288-20 is_transmit1_triggered_~__retres1~1 := 0; 10897#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10896#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 10895#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10894#L718-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10893#L307-18 assume !(1 == ~t2_pc~0); 10891#L307-20 is_transmit2_triggered_~__retres1~2 := 0; 10890#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10889#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 10888#L726-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 9965#L726-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9966#L326-18 assume 1 == ~t3_pc~0; 10059#L327-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 10030#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10031#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 10057#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 10058#L734-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9552#L345-18 assume 1 == ~t4_pc~0; 9553#L346-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9558#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9574#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9703#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 9704#L742-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9707#L364-18 assume 1 == ~t5_pc~0; 9798#L365-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 9785#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9807#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 10827#L750-18 assume !(0 != activate_threads_~tmp___4~0); 10825#L750-20 assume 1 == ~M_E~0;~M_E~0 := 2; 10823#L639-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10821#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10819#L649-3 assume !(1 == ~T3_E~0); 10818#L654-3 assume !(1 == ~T4_E~0); 10817#L659-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10816#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10815#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10814#L674-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10813#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10812#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10811#L689-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 10809#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 10804#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 10803#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 10802#L909 assume !(0 == start_simulation_~tmp~3); 10800#L909-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 10796#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 10793#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 10792#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 10704#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 10703#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 9900#L872 start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 9901#L922 assume !(0 != start_simulation_~tmp___0~1); 9790#L890-1 [2019-11-25 08:58:12,604 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:12,604 INFO L82 PathProgramCache]: Analyzing trace with hash -25652515, now seen corresponding path program 1 times [2019-11-25 08:58:12,605 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:12,605 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1788399484] [2019-11-25 08:58:12,605 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:12,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:12,640 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:12,640 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1788399484] [2019-11-25 08:58:12,641 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:12,641 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:58:12,641 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1285355076] [2019-11-25 08:58:12,642 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:58:12,642 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:12,642 INFO L82 PathProgramCache]: Analyzing trace with hash -1994446494, now seen corresponding path program 1 times [2019-11-25 08:58:12,642 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:12,642 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1542292698] [2019-11-25 08:58:12,643 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:12,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:12,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:12,670 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1542292698] [2019-11-25 08:58:12,671 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:12,671 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:58:12,671 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [817049512] [2019-11-25 08:58:12,672 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:58:12,672 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:58:12,672 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:58:12,672 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:58:12,672 INFO L87 Difference]: Start difference. First operand 1501 states and 2216 transitions. cyclomatic complexity: 719 Second operand 3 states. [2019-11-25 08:58:12,752 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:58:12,752 INFO L93 Difference]: Finished difference Result 2742 states and 4027 transitions. [2019-11-25 08:58:12,752 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:58:12,753 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2742 states and 4027 transitions. [2019-11-25 08:58:12,775 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2648 [2019-11-25 08:58:12,798 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2742 states to 2742 states and 4027 transitions. [2019-11-25 08:58:12,798 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2742 [2019-11-25 08:58:12,801 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2742 [2019-11-25 08:58:12,801 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2742 states and 4027 transitions. [2019-11-25 08:58:12,806 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:58:12,806 INFO L688 BuchiCegarLoop]: Abstraction has 2742 states and 4027 transitions. [2019-11-25 08:58:12,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2742 states and 4027 transitions. [2019-11-25 08:58:12,844 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2742 to 2734. [2019-11-25 08:58:12,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2734 states. [2019-11-25 08:58:12,855 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2734 states to 2734 states and 4019 transitions. [2019-11-25 08:58:12,856 INFO L711 BuchiCegarLoop]: Abstraction has 2734 states and 4019 transitions. [2019-11-25 08:58:12,856 INFO L591 BuchiCegarLoop]: Abstraction has 2734 states and 4019 transitions. [2019-11-25 08:58:12,858 INFO L424 BuchiCegarLoop]: ======== Iteration 10============ [2019-11-25 08:58:12,858 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2734 states and 4019 transitions. [2019-11-25 08:58:12,872 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2640 [2019-11-25 08:58:12,872 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:58:12,873 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:58:12,874 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:12,874 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:12,874 INFO L794 eck$LassoCheckResult]: Stem: 14204#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 14170#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 13949#L853 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 13950#L384 assume 1 == ~m_i~0;~m_st~0 := 0; 13899#L391-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13900#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13988#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13989#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13854#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13855#L416-1 assume !(0 == ~M_E~0); 13866#L576-1 assume !(0 == ~T1_E~0); 13867#L581-1 assume !(0 == ~T2_E~0); 14110#L586-1 assume !(0 == ~T3_E~0); 14111#L591-1 assume !(0 == ~T4_E~0); 14022#L596-1 assume !(0 == ~T5_E~0); 14023#L601-1 assume !(0 == ~E_1~0); 14060#L606-1 assume !(0 == ~E_2~0); 13916#L611-1 assume !(0 == ~E_3~0); 13917#L616-1 assume !(0 == ~E_4~0); 13789#L621-1 assume !(0 == ~E_5~0); 13790#L626-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13984#L269 assume !(1 == ~m_pc~0); 13975#L269-2 is_master_triggered_~__retres1~0 := 0; 13976#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13907#L281 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 13908#L710 assume !(0 != activate_threads_~tmp~1); 13909#L710-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13910#L288 assume !(1 == ~t1_pc~0); 14024#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 14026#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14027#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 14124#L718 assume !(0 != activate_threads_~tmp___0~0); 14130#L718-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14132#L307 assume !(1 == ~t2_pc~0); 14173#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 14171#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14172#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 14228#L726 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 14229#L726-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14230#L326 assume !(1 == ~t3_pc~0); 14245#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 14246#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14258#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 14289#L734 assume !(0 != activate_threads_~tmp___2~0); 14297#L734-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 13833#L345 assume !(1 == ~t4_pc~0); 13834#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 13831#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13832#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 13807#L742 assume !(0 != activate_threads_~tmp___3~0); 13782#L742-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 13783#L364 assume 1 == ~t5_pc~0; 13994#L365 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 13995#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 13992#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 13993#L750 assume !(0 != activate_threads_~tmp___4~0); 14033#L750-2 assume !(1 == ~M_E~0); 14038#L639-1 assume !(1 == ~T1_E~0); 13911#L644-1 assume !(1 == ~T2_E~0); 13912#L649-1 assume !(1 == ~T3_E~0); 13786#L654-1 assume !(1 == ~T4_E~0); 13787#L659-1 assume !(1 == ~T5_E~0); 13859#L664-1 assume 1 == ~E_1~0;~E_1~0 := 2; 13860#L669-1 assume !(1 == ~E_2~0); 14135#L674-1 assume !(1 == ~E_3~0); 14136#L679-1 assume !(1 == ~E_4~0); 14039#L684-1 assume !(1 == ~E_5~0); 14040#L890-1 [2019-11-25 08:58:12,875 INFO L796 eck$LassoCheckResult]: Loop: 14040#L890-1 assume !false; 14894#L891 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 14891#L551 assume !false; 14881#L472 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 14875#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 14857#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 14850#L462 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 14842#L476 assume !(0 != eval_~tmp~0); 14843#L566 start_simulation_~kernel_st~0 := 2; 15291#L384-1 start_simulation_~kernel_st~0 := 3; 15290#L576-2 assume 0 == ~M_E~0;~M_E~0 := 1; 15289#L576-4 assume !(0 == ~T1_E~0); 15288#L581-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15287#L586-3 assume !(0 == ~T3_E~0); 15286#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15285#L596-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15284#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15283#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15282#L611-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15281#L616-3 assume !(0 == ~E_4~0); 15280#L621-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15279#L626-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15278#L269-18 assume !(1 == ~m_pc~0); 15277#L269-20 is_master_triggered_~__retres1~0 := 0; 15276#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15275#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 15274#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 15273#L710-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15272#L288-18 assume !(1 == ~t1_pc~0); 15271#L288-20 is_transmit1_triggered_~__retres1~1 := 0; 15270#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15269#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 15268#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 15267#L718-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15266#L307-18 assume !(1 == ~t2_pc~0); 15264#L307-20 is_transmit2_triggered_~__retres1~2 := 0; 15263#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15262#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 15261#L726-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 15260#L726-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15258#L326-18 assume !(1 == ~t3_pc~0); 15255#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 15253#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15251#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 15249#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 15247#L734-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15245#L345-18 assume !(1 == ~t4_pc~0); 15242#L345-20 is_transmit4_triggered_~__retres1~4 := 0; 15240#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15238#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 15236#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 15234#L742-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15232#L364-18 assume 1 == ~t5_pc~0; 15228#L365-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 15226#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15224#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 15222#L750-18 assume !(0 != activate_threads_~tmp___4~0); 15220#L750-20 assume 1 == ~M_E~0;~M_E~0 := 2; 15218#L639-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15215#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15213#L649-3 assume !(1 == ~T3_E~0); 15210#L654-3 assume !(1 == ~T4_E~0); 15207#L659-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15204#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15201#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15197#L674-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15194#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15191#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15189#L689-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 15058#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 15048#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 15043#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 15037#L909 assume !(0 == start_simulation_~tmp~3); 15032#L909-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 15024#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 15015#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 15010#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 15006#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 14968#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 14958#L872 start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 14951#L922 assume !(0 != start_simulation_~tmp___0~1); 14040#L890-1 [2019-11-25 08:58:12,875 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:12,875 INFO L82 PathProgramCache]: Analyzing trace with hash -334091524, now seen corresponding path program 1 times [2019-11-25 08:58:12,875 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:12,876 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2000221663] [2019-11-25 08:58:12,876 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:12,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:12,905 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:12,905 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2000221663] [2019-11-25 08:58:12,906 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:12,906 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:58:12,907 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2057675175] [2019-11-25 08:58:12,910 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:58:12,911 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:12,911 INFO L82 PathProgramCache]: Analyzing trace with hash -1428172124, now seen corresponding path program 1 times [2019-11-25 08:58:12,911 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:12,912 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [470400942] [2019-11-25 08:58:12,912 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:12,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:12,940 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:12,940 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [470400942] [2019-11-25 08:58:12,941 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:12,941 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:58:12,941 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1454221978] [2019-11-25 08:58:12,942 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:58:12,942 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:58:12,943 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:58:12,943 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:58:12,943 INFO L87 Difference]: Start difference. First operand 2734 states and 4019 transitions. cyclomatic complexity: 1293 Second operand 3 states. [2019-11-25 08:58:13,032 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:58:13,033 INFO L93 Difference]: Finished difference Result 5353 states and 7800 transitions. [2019-11-25 08:58:13,033 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:58:13,033 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5353 states and 7800 transitions. [2019-11-25 08:58:13,070 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 5220 [2019-11-25 08:58:13,116 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5353 states to 5353 states and 7800 transitions. [2019-11-25 08:58:13,116 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5353 [2019-11-25 08:58:13,122 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5353 [2019-11-25 08:58:13,122 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5353 states and 7800 transitions. [2019-11-25 08:58:13,131 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:58:13,131 INFO L688 BuchiCegarLoop]: Abstraction has 5353 states and 7800 transitions. [2019-11-25 08:58:13,136 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5353 states and 7800 transitions. [2019-11-25 08:58:13,213 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5353 to 5321. [2019-11-25 08:58:13,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5321 states. [2019-11-25 08:58:13,234 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5321 states to 5321 states and 7760 transitions. [2019-11-25 08:58:13,235 INFO L711 BuchiCegarLoop]: Abstraction has 5321 states and 7760 transitions. [2019-11-25 08:58:13,235 INFO L591 BuchiCegarLoop]: Abstraction has 5321 states and 7760 transitions. [2019-11-25 08:58:13,235 INFO L424 BuchiCegarLoop]: ======== Iteration 11============ [2019-11-25 08:58:13,235 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5321 states and 7760 transitions. [2019-11-25 08:58:13,255 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 5204 [2019-11-25 08:58:13,255 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:58:13,255 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:58:13,256 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:13,257 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:13,257 INFO L794 eck$LassoCheckResult]: Stem: 22328#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 22290#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 22046#L853 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 22047#L384 assume 1 == ~m_i~0;~m_st~0 := 0; 21992#L391-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21993#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22088#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22089#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21950#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21951#L416-1 assume !(0 == ~M_E~0); 21962#L576-1 assume !(0 == ~T1_E~0); 21963#L581-1 assume !(0 == ~T2_E~0); 22216#L586-1 assume !(0 == ~T3_E~0); 22217#L591-1 assume !(0 == ~T4_E~0); 22119#L596-1 assume !(0 == ~T5_E~0); 22120#L601-1 assume !(0 == ~E_1~0); 22168#L606-1 assume !(0 == ~E_2~0); 22012#L611-1 assume !(0 == ~E_3~0); 22013#L616-1 assume !(0 == ~E_4~0); 21883#L621-1 assume !(0 == ~E_5~0); 21884#L626-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22084#L269 assume !(1 == ~m_pc~0); 22072#L269-2 is_master_triggered_~__retres1~0 := 0; 22073#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22002#L281 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 22003#L710 assume !(0 != activate_threads_~tmp~1); 22004#L710-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22005#L288 assume !(1 == ~t1_pc~0); 22121#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 22122#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22123#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 22232#L718 assume !(0 != activate_threads_~tmp___0~0); 22241#L718-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22242#L307 assume !(1 == ~t2_pc~0); 22293#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 22291#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22292#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 22354#L726 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 22355#L726-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22356#L326 assume !(1 == ~t3_pc~0); 22370#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 22371#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22382#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 22415#L734 assume !(0 != activate_threads_~tmp___2~0); 22431#L734-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 21927#L345 assume !(1 == ~t4_pc~0); 21928#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 21925#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21926#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 21901#L742 assume !(0 != activate_threads_~tmp___3~0); 21873#L742-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 21874#L364 assume !(1 == ~t5_pc~0); 22166#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 22164#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 22092#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 22093#L750 assume !(0 != activate_threads_~tmp___4~0); 22129#L750-2 assume !(1 == ~M_E~0); 22135#L639-1 assume !(1 == ~T1_E~0); 22006#L644-1 assume !(1 == ~T2_E~0); 22007#L649-1 assume !(1 == ~T3_E~0); 21880#L654-1 assume !(1 == ~T4_E~0); 21881#L659-1 assume !(1 == ~T5_E~0); 21955#L664-1 assume 1 == ~E_1~0;~E_1~0 := 2; 21956#L669-1 assume !(1 == ~E_2~0); 22243#L674-1 assume !(1 == ~E_3~0); 22244#L679-1 assume !(1 == ~E_4~0); 22136#L684-1 assume !(1 == ~E_5~0); 22137#L890-1 [2019-11-25 08:58:13,257 INFO L796 eck$LassoCheckResult]: Loop: 22137#L890-1 assume !false; 25135#L891 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 25134#L551 assume !false; 25133#L472 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 25126#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 25122#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 25119#L462 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 25116#L476 assume !(0 != eval_~tmp~0); 25117#L566 start_simulation_~kernel_st~0 := 2; 25365#L384-1 start_simulation_~kernel_st~0 := 3; 25364#L576-2 assume 0 == ~M_E~0;~M_E~0 := 1; 25363#L576-4 assume !(0 == ~T1_E~0); 25362#L581-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25361#L586-3 assume !(0 == ~T3_E~0); 25360#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25359#L596-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25358#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25357#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25356#L611-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25355#L616-3 assume !(0 == ~E_4~0); 25354#L621-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25353#L626-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25352#L269-18 assume !(1 == ~m_pc~0); 25351#L269-20 is_master_triggered_~__retres1~0 := 0; 25350#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25349#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 25348#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 25347#L710-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 25346#L288-18 assume !(1 == ~t1_pc~0); 25344#L288-20 is_transmit1_triggered_~__retres1~1 := 0; 25342#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 25340#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 25338#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 25336#L718-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 25334#L307-18 assume !(1 == ~t2_pc~0); 25331#L307-20 is_transmit2_triggered_~__retres1~2 := 0; 25329#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25327#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 25325#L726-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 25323#L726-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 25321#L326-18 assume !(1 == ~t3_pc~0); 25319#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 25316#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25314#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 25312#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 25310#L734-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 25308#L345-18 assume !(1 == ~t4_pc~0); 25305#L345-20 is_transmit4_triggered_~__retres1~4 := 0; 25303#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 25301#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 25299#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 25297#L742-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 25295#L364-18 assume !(1 == ~t5_pc~0); 25293#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 25290#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 25288#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 25286#L750-18 assume !(0 != activate_threads_~tmp___4~0); 25284#L750-20 assume 1 == ~M_E~0;~M_E~0 := 2; 25282#L639-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25280#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25278#L649-3 assume !(1 == ~T3_E~0); 25276#L654-3 assume !(1 == ~T4_E~0); 25274#L659-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25272#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25270#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25268#L674-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25266#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25264#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25262#L689-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 25257#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 25251#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 25249#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 25247#L909 assume !(0 == start_simulation_~tmp~3); 25245#L909-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 25241#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 25238#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 25237#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 25236#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 25234#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 25232#L872 start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 25230#L922 assume !(0 != start_simulation_~tmp___0~1); 22137#L890-1 [2019-11-25 08:58:13,258 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:13,258 INFO L82 PathProgramCache]: Analyzing trace with hash 842512795, now seen corresponding path program 1 times [2019-11-25 08:58:13,258 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:13,258 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [48340999] [2019-11-25 08:58:13,258 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:13,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:13,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:13,289 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [48340999] [2019-11-25 08:58:13,289 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:13,290 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:58:13,290 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1660672357] [2019-11-25 08:58:13,290 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:58:13,291 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:13,291 INFO L82 PathProgramCache]: Analyzing trace with hash 1895120485, now seen corresponding path program 1 times [2019-11-25 08:58:13,291 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:13,291 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [197110108] [2019-11-25 08:58:13,292 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:13,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:13,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:13,322 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [197110108] [2019-11-25 08:58:13,322 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:13,322 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:58:13,323 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [337101871] [2019-11-25 08:58:13,323 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:58:13,323 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:58:13,323 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:58:13,324 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:58:13,324 INFO L87 Difference]: Start difference. First operand 5321 states and 7760 transitions. cyclomatic complexity: 2455 Second operand 3 states. [2019-11-25 08:58:13,382 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:58:13,382 INFO L93 Difference]: Finished difference Result 5321 states and 7666 transitions. [2019-11-25 08:58:13,382 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:58:13,382 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5321 states and 7666 transitions. [2019-11-25 08:58:13,411 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 5204 [2019-11-25 08:58:13,448 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5321 states to 5321 states and 7666 transitions. [2019-11-25 08:58:13,448 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5321 [2019-11-25 08:58:13,454 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5321 [2019-11-25 08:58:13,454 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5321 states and 7666 transitions. [2019-11-25 08:58:13,462 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:58:13,462 INFO L688 BuchiCegarLoop]: Abstraction has 5321 states and 7666 transitions. [2019-11-25 08:58:13,468 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5321 states and 7666 transitions. [2019-11-25 08:58:13,540 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5321 to 5321. [2019-11-25 08:58:13,540 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5321 states. [2019-11-25 08:58:13,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5321 states to 5321 states and 7666 transitions. [2019-11-25 08:58:13,557 INFO L711 BuchiCegarLoop]: Abstraction has 5321 states and 7666 transitions. [2019-11-25 08:58:13,557 INFO L591 BuchiCegarLoop]: Abstraction has 5321 states and 7666 transitions. [2019-11-25 08:58:13,557 INFO L424 BuchiCegarLoop]: ======== Iteration 12============ [2019-11-25 08:58:13,557 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5321 states and 7666 transitions. [2019-11-25 08:58:13,579 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 5204 [2019-11-25 08:58:13,579 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:58:13,579 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:58:13,580 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:13,581 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:13,581 INFO L794 eck$LassoCheckResult]: Stem: 32966#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 32930#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 32694#L853 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 32695#L384 assume 1 == ~m_i~0;~m_st~0 := 0; 32639#L391-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32640#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32733#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32734#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32597#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 32598#L416-1 assume !(0 == ~M_E~0); 32609#L576-1 assume !(0 == ~T1_E~0); 32610#L581-1 assume !(0 == ~T2_E~0); 32857#L586-1 assume !(0 == ~T3_E~0); 32858#L591-1 assume !(0 == ~T4_E~0); 32763#L596-1 assume !(0 == ~T5_E~0); 32764#L601-1 assume !(0 == ~E_1~0); 32813#L606-1 assume !(0 == ~E_2~0); 32659#L611-1 assume !(0 == ~E_3~0); 32660#L616-1 assume !(0 == ~E_4~0); 32532#L621-1 assume !(0 == ~E_5~0); 32533#L626-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 32729#L269 assume !(1 == ~m_pc~0); 32720#L269-2 is_master_triggered_~__retres1~0 := 0; 32721#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 32649#L281 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 32650#L710 assume !(0 != activate_threads_~tmp~1); 32651#L710-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 32652#L288 assume !(1 == ~t1_pc~0); 32765#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 32766#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 32767#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 32873#L718 assume !(0 != activate_threads_~tmp___0~0); 32884#L718-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 32885#L307 assume !(1 == ~t2_pc~0); 32933#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 32931#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 32932#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 32992#L726 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 32993#L726-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 32994#L326 assume !(1 == ~t3_pc~0); 33009#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 33010#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 33022#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 33054#L734 assume !(0 != activate_threads_~tmp___2~0); 33071#L734-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 32576#L345 assume !(1 == ~t4_pc~0); 32577#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 32574#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 32575#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 32550#L742 assume !(0 != activate_threads_~tmp___3~0); 32522#L742-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 32523#L364 assume !(1 == ~t5_pc~0); 32810#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 32808#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 32737#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 32738#L750 assume !(0 != activate_threads_~tmp___4~0); 32774#L750-2 assume !(1 == ~M_E~0); 32782#L639-1 assume !(1 == ~T1_E~0); 32653#L644-1 assume !(1 == ~T2_E~0); 32654#L649-1 assume !(1 == ~T3_E~0); 32529#L654-1 assume !(1 == ~T4_E~0); 32530#L659-1 assume !(1 == ~T5_E~0); 32602#L664-1 assume !(1 == ~E_1~0); 32603#L669-1 assume !(1 == ~E_2~0); 32886#L674-1 assume !(1 == ~E_3~0); 32887#L679-1 assume !(1 == ~E_4~0); 32783#L684-1 assume !(1 == ~E_5~0); 32784#L890-1 [2019-11-25 08:58:13,581 INFO L796 eck$LassoCheckResult]: Loop: 32784#L890-1 assume !false; 34328#L891 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 34233#L551 assume !false; 34327#L472 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 34323#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 34320#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 34318#L462 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 34315#L476 assume !(0 != eval_~tmp~0); 34316#L566 start_simulation_~kernel_st~0 := 2; 34480#L384-1 start_simulation_~kernel_st~0 := 3; 34478#L576-2 assume 0 == ~M_E~0;~M_E~0 := 1; 34476#L576-4 assume !(0 == ~T1_E~0); 34474#L581-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34472#L586-3 assume !(0 == ~T3_E~0); 34470#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 34468#L596-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 34466#L601-3 assume !(0 == ~E_1~0); 34465#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 34461#L611-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34459#L616-3 assume !(0 == ~E_4~0); 34458#L621-3 assume 0 == ~E_5~0;~E_5~0 := 1; 34457#L626-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 34456#L269-18 assume !(1 == ~m_pc~0); 34455#L269-20 is_master_triggered_~__retres1~0 := 0; 34454#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 34453#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 34452#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 34451#L710-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 34450#L288-18 assume !(1 == ~t1_pc~0); 34448#L288-20 is_transmit1_triggered_~__retres1~1 := 0; 34446#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 34444#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 34442#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 34440#L718-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 34438#L307-18 assume !(1 == ~t2_pc~0); 34435#L307-20 is_transmit2_triggered_~__retres1~2 := 0; 34433#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 34431#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 34429#L726-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 34427#L726-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 34425#L326-18 assume !(1 == ~t3_pc~0); 34423#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 34420#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 34418#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 34416#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 34414#L734-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 34412#L345-18 assume !(1 == ~t4_pc~0); 34409#L345-20 is_transmit4_triggered_~__retres1~4 := 0; 34407#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 34405#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 34403#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 34401#L742-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 34399#L364-18 assume !(1 == ~t5_pc~0); 34397#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 34394#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 34392#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 34390#L750-18 assume !(0 != activate_threads_~tmp___4~0); 34388#L750-20 assume 1 == ~M_E~0;~M_E~0 := 2; 34386#L639-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34384#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34382#L649-3 assume !(1 == ~T3_E~0); 34380#L654-3 assume !(1 == ~T4_E~0); 34378#L659-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 34376#L664-3 assume !(1 == ~E_1~0); 34374#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34372#L674-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34370#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34368#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 34366#L689-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 34361#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 34355#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 34353#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 34351#L909 assume !(0 == start_simulation_~tmp~3); 34349#L909-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 34345#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 34342#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 34339#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 34334#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 34333#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 34330#L872 start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 34329#L922 assume !(0 != start_simulation_~tmp___0~1); 32784#L890-1 [2019-11-25 08:58:13,582 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:13,582 INFO L82 PathProgramCache]: Analyzing trace with hash 844359837, now seen corresponding path program 1 times [2019-11-25 08:58:13,582 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:13,582 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [309250530] [2019-11-25 08:58:13,583 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:13,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:13,650 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:13,650 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [309250530] [2019-11-25 08:58:13,650 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:13,650 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-25 08:58:13,651 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1639151235] [2019-11-25 08:58:13,651 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:58:13,651 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:13,652 INFO L82 PathProgramCache]: Analyzing trace with hash -1785204059, now seen corresponding path program 1 times [2019-11-25 08:58:13,652 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:13,652 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1220951843] [2019-11-25 08:58:13,652 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:13,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:13,681 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:13,681 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1220951843] [2019-11-25 08:58:13,682 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:13,682 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:58:13,682 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [458464723] [2019-11-25 08:58:13,682 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:58:13,683 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:58:13,683 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-25 08:58:13,683 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-25 08:58:13,683 INFO L87 Difference]: Start difference. First operand 5321 states and 7666 transitions. cyclomatic complexity: 2361 Second operand 5 states. [2019-11-25 08:58:13,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:58:13,988 INFO L93 Difference]: Finished difference Result 13936 states and 20089 transitions. [2019-11-25 08:58:13,988 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-25 08:58:13,989 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13936 states and 20089 transitions. [2019-11-25 08:58:14,062 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13660 [2019-11-25 08:58:14,142 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13936 states to 13936 states and 20089 transitions. [2019-11-25 08:58:14,143 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13936 [2019-11-25 08:58:14,158 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13936 [2019-11-25 08:58:14,158 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13936 states and 20089 transitions. [2019-11-25 08:58:14,179 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:58:14,179 INFO L688 BuchiCegarLoop]: Abstraction has 13936 states and 20089 transitions. [2019-11-25 08:58:14,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13936 states and 20089 transitions. [2019-11-25 08:58:14,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13936 to 5588. [2019-11-25 08:58:14,309 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5588 states. [2019-11-25 08:58:14,324 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5588 states to 5588 states and 7933 transitions. [2019-11-25 08:58:14,324 INFO L711 BuchiCegarLoop]: Abstraction has 5588 states and 7933 transitions. [2019-11-25 08:58:14,324 INFO L591 BuchiCegarLoop]: Abstraction has 5588 states and 7933 transitions. [2019-11-25 08:58:14,324 INFO L424 BuchiCegarLoop]: ======== Iteration 13============ [2019-11-25 08:58:14,324 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5588 states and 7933 transitions. [2019-11-25 08:58:14,345 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 5468 [2019-11-25 08:58:14,345 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:58:14,345 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:58:14,346 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:14,346 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:14,347 INFO L794 eck$LassoCheckResult]: Stem: 52243#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 52197#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 51964#L853 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 51965#L384 assume 1 == ~m_i~0;~m_st~0 := 0; 51910#L391-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51911#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 52002#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 52003#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 51868#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 51869#L416-1 assume !(0 == ~M_E~0); 51880#L576-1 assume !(0 == ~T1_E~0); 51881#L581-1 assume !(0 == ~T2_E~0); 52116#L586-1 assume !(0 == ~T3_E~0); 52117#L591-1 assume !(0 == ~T4_E~0); 52032#L596-1 assume !(0 == ~T5_E~0); 52033#L601-1 assume !(0 == ~E_1~0); 52073#L606-1 assume !(0 == ~E_2~0); 51929#L611-1 assume !(0 == ~E_3~0); 51930#L616-1 assume !(0 == ~E_4~0); 51802#L621-1 assume !(0 == ~E_5~0); 51803#L626-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 51998#L269 assume !(1 == ~m_pc~0); 51988#L269-2 is_master_triggered_~__retres1~0 := 0; 51989#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 51919#L281 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 51920#L710 assume !(0 != activate_threads_~tmp~1); 51921#L710-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 51922#L288 assume !(1 == ~t1_pc~0); 52034#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 52035#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 52036#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 52132#L718 assume !(0 != activate_threads_~tmp___0~0); 52143#L718-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 52144#L307 assume !(1 == ~t2_pc~0); 52200#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 52198#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 52199#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 52294#L726 assume !(0 != activate_threads_~tmp___1~0); 52281#L726-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 52282#L326 assume !(1 == ~t3_pc~0); 52308#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 52309#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 52320#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 52358#L734 assume !(0 != activate_threads_~tmp___2~0); 52374#L734-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 51846#L345 assume !(1 == ~t4_pc~0); 51847#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 51844#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 51845#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 51820#L742 assume !(0 != activate_threads_~tmp___3~0); 51792#L742-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 51793#L364 assume !(1 == ~t5_pc~0); 52072#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 52070#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 52006#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 52007#L750 assume !(0 != activate_threads_~tmp___4~0); 52041#L750-2 assume !(1 == ~M_E~0); 52047#L639-1 assume !(1 == ~T1_E~0); 51923#L644-1 assume !(1 == ~T2_E~0); 51924#L649-1 assume !(1 == ~T3_E~0); 51799#L654-1 assume !(1 == ~T4_E~0); 51800#L659-1 assume !(1 == ~T5_E~0); 51873#L664-1 assume !(1 == ~E_1~0); 51874#L669-1 assume !(1 == ~E_2~0); 52145#L674-1 assume !(1 == ~E_3~0); 52146#L679-1 assume !(1 == ~E_4~0); 52048#L684-1 assume !(1 == ~E_5~0); 52049#L890-1 [2019-11-25 08:58:14,347 INFO L796 eck$LassoCheckResult]: Loop: 52049#L890-1 assume !false; 55001#L891 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 54999#L551 assume !false; 54998#L472 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 54994#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 54988#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 54986#L462 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 54984#L476 assume !(0 != eval_~tmp~0); 54985#L566 start_simulation_~kernel_st~0 := 2; 57310#L384-1 start_simulation_~kernel_st~0 := 3; 57308#L576-2 assume 0 == ~M_E~0;~M_E~0 := 1; 57306#L576-4 assume !(0 == ~T1_E~0); 57304#L581-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 57302#L586-3 assume !(0 == ~T3_E~0); 57300#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 57298#L596-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 57296#L601-3 assume !(0 == ~E_1~0); 57289#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 57288#L611-3 assume 0 == ~E_3~0;~E_3~0 := 1; 57287#L616-3 assume !(0 == ~E_4~0); 57286#L621-3 assume 0 == ~E_5~0;~E_5~0 := 1; 57285#L626-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 57284#L269-18 assume !(1 == ~m_pc~0); 57283#L269-20 is_master_triggered_~__retres1~0 := 0; 57282#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 57281#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 57280#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 57279#L710-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 57278#L288-18 assume !(1 == ~t1_pc~0); 57277#L288-20 is_transmit1_triggered_~__retres1~1 := 0; 57276#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 57275#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 57274#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 57273#L718-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 57272#L307-18 assume 1 == ~t2_pc~0; 57270#L308-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 57268#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 57266#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 57264#L726-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 57263#L726-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 57261#L326-18 assume !(1 == ~t3_pc~0); 57259#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 57257#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 57255#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 57253#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 57250#L734-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 57248#L345-18 assume !(1 == ~t4_pc~0); 57245#L345-20 is_transmit4_triggered_~__retres1~4 := 0; 57243#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 57241#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 57239#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 57237#L742-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 57235#L364-18 assume !(1 == ~t5_pc~0); 57233#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 57231#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 57229#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 57227#L750-18 assume !(0 != activate_threads_~tmp___4~0); 57225#L750-20 assume 1 == ~M_E~0;~M_E~0 := 2; 57223#L639-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 57221#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 57154#L649-3 assume !(1 == ~T3_E~0); 57153#L654-3 assume !(1 == ~T4_E~0); 57142#L659-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 57140#L664-3 assume !(1 == ~E_1~0); 57117#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 57115#L674-3 assume 1 == ~E_3~0;~E_3~0 := 2; 57112#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 52030#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 52031#L689-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 56939#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 56934#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 52274#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 52275#L909 assume !(0 == start_simulation_~tmp~3); 52325#L909-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 57039#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 57036#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 57034#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 57010#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 57008#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 57006#L872 start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 57001#L922 assume !(0 != start_simulation_~tmp___0~1); 52049#L890-1 [2019-11-25 08:58:14,347 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:14,347 INFO L82 PathProgramCache]: Analyzing trace with hash 866992091, now seen corresponding path program 1 times [2019-11-25 08:58:14,348 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:14,348 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [732594729] [2019-11-25 08:58:14,348 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:14,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:14,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:14,401 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:58:14,403 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:14,403 INFO L82 PathProgramCache]: Analyzing trace with hash 108238116, now seen corresponding path program 1 times [2019-11-25 08:58:14,404 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:14,404 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1706905966] [2019-11-25 08:58:14,404 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:14,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:14,429 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:14,430 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1706905966] [2019-11-25 08:58:14,430 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:14,430 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:58:14,430 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1372003914] [2019-11-25 08:58:14,431 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:58:14,433 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:58:14,434 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:58:14,435 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:58:14,435 INFO L87 Difference]: Start difference. First operand 5588 states and 7933 transitions. cyclomatic complexity: 2361 Second operand 3 states. [2019-11-25 08:58:14,490 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:58:14,491 INFO L93 Difference]: Finished difference Result 6504 states and 9211 transitions. [2019-11-25 08:58:14,491 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:58:14,491 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6504 states and 9211 transitions. [2019-11-25 08:58:14,529 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6332 [2019-11-25 08:58:14,555 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6504 states to 6504 states and 9211 transitions. [2019-11-25 08:58:14,556 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6504 [2019-11-25 08:58:14,563 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6504 [2019-11-25 08:58:14,563 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6504 states and 9211 transitions. [2019-11-25 08:58:14,571 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:58:14,571 INFO L688 BuchiCegarLoop]: Abstraction has 6504 states and 9211 transitions. [2019-11-25 08:58:14,577 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6504 states and 9211 transitions. [2019-11-25 08:58:14,644 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6504 to 6504. [2019-11-25 08:58:14,644 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6504 states. [2019-11-25 08:58:14,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6504 states to 6504 states and 9211 transitions. [2019-11-25 08:58:14,662 INFO L711 BuchiCegarLoop]: Abstraction has 6504 states and 9211 transitions. [2019-11-25 08:58:14,662 INFO L591 BuchiCegarLoop]: Abstraction has 6504 states and 9211 transitions. [2019-11-25 08:58:14,662 INFO L424 BuchiCegarLoop]: ======== Iteration 14============ [2019-11-25 08:58:14,662 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6504 states and 9211 transitions. [2019-11-25 08:58:14,684 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6332 [2019-11-25 08:58:14,685 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:58:14,685 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:58:14,686 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:14,686 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:14,687 INFO L794 eck$LassoCheckResult]: Stem: 64343#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 64300#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 64064#L853 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 64065#L384 assume 1 == ~m_i~0;~m_st~0 := 0; 64009#L391-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 64010#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 64101#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 64102#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 63967#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 63968#L416-1 assume !(0 == ~M_E~0); 63979#L576-1 assume !(0 == ~T1_E~0); 63980#L581-1 assume !(0 == ~T2_E~0); 64221#L586-1 assume !(0 == ~T3_E~0); 64222#L591-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 64452#L596-1 assume !(0 == ~T5_E~0); 64411#L601-1 assume !(0 == ~E_1~0); 64412#L606-1 assume !(0 == ~E_2~0); 64029#L611-1 assume !(0 == ~E_3~0); 64030#L616-1 assume !(0 == ~E_4~0); 63900#L621-1 assume !(0 == ~E_5~0); 63901#L626-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 64094#L269 assume !(1 == ~m_pc~0); 64095#L269-2 is_master_triggered_~__retres1~0 := 0; 64096#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 64097#L281 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 64052#L710 assume !(0 != activate_threads_~tmp~1); 64053#L710-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 64135#L288 assume !(1 == ~t1_pc~0); 64136#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 64137#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 64138#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 64479#L718 assume !(0 != activate_threads_~tmp___0~0); 64478#L718-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 64303#L307 assume !(1 == ~t2_pc~0); 64304#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 64476#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 64475#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 64474#L726 assume !(0 != activate_threads_~tmp___1~0); 64372#L726-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 64373#L326 assume !(1 == ~t3_pc~0); 64393#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 64394#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 64441#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 64442#L734 assume !(0 != activate_threads_~tmp___2~0); 64473#L734-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 64472#L345 assume !(1 == ~t4_pc~0); 63950#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 63943#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 63944#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 64470#L742 assume !(0 != activate_threads_~tmp___3~0); 63890#L742-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 63891#L364 assume !(1 == ~t5_pc~0); 64178#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 64179#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 64464#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 64463#L750 assume !(0 != activate_threads_~tmp___4~0); 64462#L750-2 assume !(1 == ~M_E~0); 64461#L639-1 assume !(1 == ~T1_E~0); 64460#L644-1 assume !(1 == ~T2_E~0); 64459#L649-1 assume !(1 == ~T3_E~0); 63897#L654-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 63898#L659-1 assume !(1 == ~T5_E~0); 63972#L664-1 assume !(1 == ~E_1~0); 63973#L669-1 assume !(1 == ~E_2~0); 64249#L674-1 assume !(1 == ~E_3~0); 64250#L679-1 assume !(1 == ~E_4~0); 64150#L684-1 assume !(1 == ~E_5~0); 64151#L890-1 [2019-11-25 08:58:14,687 INFO L796 eck$LassoCheckResult]: Loop: 64151#L890-1 assume !false; 67238#L891 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 67117#L551 assume !false; 67236#L472 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 67232#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 67226#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 67224#L462 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 67222#L476 assume !(0 != eval_~tmp~0); 67223#L566 start_simulation_~kernel_st~0 := 2; 67413#L384-1 start_simulation_~kernel_st~0 := 3; 67411#L576-2 assume 0 == ~M_E~0;~M_E~0 := 1; 67409#L576-4 assume !(0 == ~T1_E~0); 67407#L581-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 67405#L586-3 assume !(0 == ~T3_E~0); 67402#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 67400#L596-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 67398#L601-3 assume !(0 == ~E_1~0); 67396#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 67394#L611-3 assume 0 == ~E_3~0;~E_3~0 := 1; 67392#L616-3 assume !(0 == ~E_4~0); 67390#L621-3 assume 0 == ~E_5~0;~E_5~0 := 1; 67388#L626-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 67386#L269-18 assume !(1 == ~m_pc~0); 67384#L269-20 is_master_triggered_~__retres1~0 := 0; 67382#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 67380#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 67379#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 67375#L710-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 67373#L288-18 assume !(1 == ~t1_pc~0); 67371#L288-20 is_transmit1_triggered_~__retres1~1 := 0; 67369#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 67366#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 67364#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 67362#L718-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 67357#L307-18 assume !(1 == ~t2_pc~0); 67355#L307-20 is_transmit2_triggered_~__retres1~2 := 0; 67353#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 67351#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 67349#L726-18 assume !(0 != activate_threads_~tmp___1~0); 67345#L726-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 67343#L326-18 assume !(1 == ~t3_pc~0); 67341#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 67339#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 67337#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 67335#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 67333#L734-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 67331#L345-18 assume 1 == ~t4_pc~0; 67329#L346-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 67326#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 67324#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 67322#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 67320#L742-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 67318#L364-18 assume !(1 == ~t5_pc~0); 67317#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 67316#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 67314#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 67312#L750-18 assume !(0 != activate_threads_~tmp___4~0); 67310#L750-20 assume 1 == ~M_E~0;~M_E~0 := 2; 67308#L639-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 67306#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 67304#L649-3 assume !(1 == ~T3_E~0); 67302#L654-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 67299#L659-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 67297#L664-3 assume !(1 == ~E_1~0); 67295#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 67293#L674-3 assume 1 == ~E_3~0;~E_3~0 := 2; 67291#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 67290#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 67286#L689-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 67281#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 67274#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 67272#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 67269#L909 assume !(0 == start_simulation_~tmp~3); 67266#L909-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 67255#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 67251#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 67249#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 67247#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 67245#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 67243#L872 start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 67241#L922 assume !(0 != start_simulation_~tmp___0~1); 64151#L890-1 [2019-11-25 08:58:14,687 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:14,688 INFO L82 PathProgramCache]: Analyzing trace with hash -1784034277, now seen corresponding path program 1 times [2019-11-25 08:58:14,688 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:14,688 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1137552080] [2019-11-25 08:58:14,688 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:14,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:14,705 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:14,706 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1137552080] [2019-11-25 08:58:14,706 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:14,706 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:58:14,706 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [226507271] [2019-11-25 08:58:14,706 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:58:14,707 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:14,707 INFO L82 PathProgramCache]: Analyzing trace with hash 1378569320, now seen corresponding path program 1 times [2019-11-25 08:58:14,707 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:14,707 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2143050293] [2019-11-25 08:58:14,707 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:14,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:14,744 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:14,745 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2143050293] [2019-11-25 08:58:14,745 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:14,745 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-25 08:58:14,745 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1641829742] [2019-11-25 08:58:14,745 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:58:14,746 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:58:14,746 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:58:14,746 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:58:14,746 INFO L87 Difference]: Start difference. First operand 6504 states and 9211 transitions. cyclomatic complexity: 2723 Second operand 3 states. [2019-11-25 08:58:14,782 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:58:14,783 INFO L93 Difference]: Finished difference Result 5588 states and 7883 transitions. [2019-11-25 08:58:14,783 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:58:14,783 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5588 states and 7883 transitions. [2019-11-25 08:58:14,808 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 5468 [2019-11-25 08:58:14,827 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5588 states to 5588 states and 7883 transitions. [2019-11-25 08:58:14,827 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5588 [2019-11-25 08:58:14,833 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5588 [2019-11-25 08:58:14,833 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5588 states and 7883 transitions. [2019-11-25 08:58:14,839 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:58:14,839 INFO L688 BuchiCegarLoop]: Abstraction has 5588 states and 7883 transitions. [2019-11-25 08:58:14,845 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5588 states and 7883 transitions. [2019-11-25 08:58:14,899 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5588 to 5588. [2019-11-25 08:58:14,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5588 states. [2019-11-25 08:58:14,914 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5588 states to 5588 states and 7883 transitions. [2019-11-25 08:58:14,914 INFO L711 BuchiCegarLoop]: Abstraction has 5588 states and 7883 transitions. [2019-11-25 08:58:14,914 INFO L591 BuchiCegarLoop]: Abstraction has 5588 states and 7883 transitions. [2019-11-25 08:58:14,914 INFO L424 BuchiCegarLoop]: ======== Iteration 15============ [2019-11-25 08:58:14,914 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5588 states and 7883 transitions. [2019-11-25 08:58:14,932 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 5468 [2019-11-25 08:58:14,932 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:58:14,932 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:58:14,934 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:14,934 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:14,934 INFO L794 eck$LassoCheckResult]: Stem: 76436#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 76398#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 76164#L853 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 76165#L384 assume 1 == ~m_i~0;~m_st~0 := 0; 76109#L391-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76110#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76199#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76200#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 76066#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76067#L416-1 assume !(0 == ~M_E~0); 76078#L576-1 assume !(0 == ~T1_E~0); 76079#L581-1 assume !(0 == ~T2_E~0); 76322#L586-1 assume !(0 == ~T3_E~0); 76323#L591-1 assume !(0 == ~T4_E~0); 76229#L596-1 assume !(0 == ~T5_E~0); 76230#L601-1 assume !(0 == ~E_1~0); 76276#L606-1 assume !(0 == ~E_2~0); 76128#L611-1 assume !(0 == ~E_3~0); 76129#L616-1 assume !(0 == ~E_4~0); 76001#L621-1 assume !(0 == ~E_5~0); 76002#L626-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 76195#L269 assume !(1 == ~m_pc~0); 76186#L269-2 is_master_triggered_~__retres1~0 := 0; 76187#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 76118#L281 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 76119#L710 assume !(0 != activate_threads_~tmp~1); 76121#L710-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 76122#L288 assume !(1 == ~t1_pc~0); 76231#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 76233#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 76234#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 76337#L718 assume !(0 != activate_threads_~tmp___0~0); 76348#L718-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 76350#L307 assume !(1 == ~t2_pc~0); 76401#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 76399#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 76400#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 76463#L726 assume !(0 != activate_threads_~tmp___1~0); 76464#L726-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 76465#L326 assume !(1 == ~t3_pc~0); 76481#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 76482#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 76493#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 76525#L734 assume !(0 != activate_threads_~tmp___2~0); 76538#L734-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 76045#L345 assume !(1 == ~t4_pc~0); 76046#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 76043#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 76044#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 76019#L742 assume !(0 != activate_threads_~tmp___3~0); 75994#L742-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 75995#L364 assume !(1 == ~t5_pc~0); 76275#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 76274#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 76203#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 76204#L750 assume !(0 != activate_threads_~tmp___4~0); 76240#L750-2 assume !(1 == ~M_E~0); 76244#L639-1 assume !(1 == ~T1_E~0); 76123#L644-1 assume !(1 == ~T2_E~0); 76124#L649-1 assume !(1 == ~T3_E~0); 75998#L654-1 assume !(1 == ~T4_E~0); 75999#L659-1 assume !(1 == ~T5_E~0); 76071#L664-1 assume !(1 == ~E_1~0); 76072#L669-1 assume !(1 == ~E_2~0); 76352#L674-1 assume !(1 == ~E_3~0); 76353#L679-1 assume !(1 == ~E_4~0); 76245#L684-1 assume !(1 == ~E_5~0); 76246#L890-1 [2019-11-25 08:58:14,934 INFO L796 eck$LassoCheckResult]: Loop: 76246#L890-1 assume !false; 78759#L891 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 78758#L551 assume !false; 78757#L472 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 78753#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 78750#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 78749#L462 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 78746#L476 assume !(0 != eval_~tmp~0); 78747#L566 start_simulation_~kernel_st~0 := 2; 79006#L384-1 start_simulation_~kernel_st~0 := 3; 79004#L576-2 assume 0 == ~M_E~0;~M_E~0 := 1; 79002#L576-4 assume !(0 == ~T1_E~0); 79000#L581-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 78998#L586-3 assume !(0 == ~T3_E~0); 78996#L591-3 assume !(0 == ~T4_E~0); 78995#L596-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 78994#L601-3 assume !(0 == ~E_1~0); 78993#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 78992#L611-3 assume 0 == ~E_3~0;~E_3~0 := 1; 78991#L616-3 assume !(0 == ~E_4~0); 78990#L621-3 assume 0 == ~E_5~0;~E_5~0 := 1; 78989#L626-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 78988#L269-18 assume !(1 == ~m_pc~0); 78986#L269-20 is_master_triggered_~__retres1~0 := 0; 78984#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 78983#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 78982#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 78980#L710-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 78979#L288-18 assume !(1 == ~t1_pc~0); 78978#L288-20 is_transmit1_triggered_~__retres1~1 := 0; 78976#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 78974#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 78972#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 78970#L718-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 78965#L307-18 assume !(1 == ~t2_pc~0); 78963#L307-20 is_transmit2_triggered_~__retres1~2 := 0; 78961#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 78959#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 78957#L726-18 assume !(0 != activate_threads_~tmp___1~0); 78954#L726-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 78952#L326-18 assume !(1 == ~t3_pc~0); 78950#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 78947#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 78945#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 78943#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 78940#L734-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 78938#L345-18 assume !(1 == ~t4_pc~0); 78935#L345-20 is_transmit4_triggered_~__retres1~4 := 0; 78933#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 78931#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 78929#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 78927#L742-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 78925#L364-18 assume !(1 == ~t5_pc~0); 78923#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 78920#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 78918#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 78916#L750-18 assume !(0 != activate_threads_~tmp___4~0); 78914#L750-20 assume 1 == ~M_E~0;~M_E~0 := 2; 78912#L639-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 78910#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 78908#L649-3 assume !(1 == ~T3_E~0); 78906#L654-3 assume !(1 == ~T4_E~0); 78904#L659-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 78902#L664-3 assume !(1 == ~E_1~0); 78900#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 78898#L674-3 assume 1 == ~E_3~0;~E_3~0 := 2; 78896#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 78894#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 78892#L689-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 78887#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 78881#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 78879#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 78877#L909 assume !(0 == start_simulation_~tmp~3); 78875#L909-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 78871#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 78868#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 78867#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 78866#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 78865#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 78863#L872 start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 78862#L922 assume !(0 != start_simulation_~tmp___0~1); 76246#L890-1 [2019-11-25 08:58:14,935 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:14,935 INFO L82 PathProgramCache]: Analyzing trace with hash 866992091, now seen corresponding path program 2 times [2019-11-25 08:58:14,935 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:14,940 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1819430543] [2019-11-25 08:58:14,940 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:14,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:14,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:14,970 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:58:14,970 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:14,971 INFO L82 PathProgramCache]: Analyzing trace with hash 396216233, now seen corresponding path program 1 times [2019-11-25 08:58:14,971 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:14,971 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [310284083] [2019-11-25 08:58:14,971 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:14,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:15,001 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:15,001 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [310284083] [2019-11-25 08:58:15,002 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:15,002 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-25 08:58:15,002 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1434286444] [2019-11-25 08:58:15,002 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:58:15,002 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:58:15,003 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-25 08:58:15,003 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-25 08:58:15,003 INFO L87 Difference]: Start difference. First operand 5588 states and 7883 transitions. cyclomatic complexity: 2311 Second operand 5 states. [2019-11-25 08:58:15,142 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:58:15,143 INFO L93 Difference]: Finished difference Result 9920 states and 13803 transitions. [2019-11-25 08:58:15,143 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-11-25 08:58:15,143 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9920 states and 13803 transitions. [2019-11-25 08:58:15,186 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9752 [2019-11-25 08:58:15,220 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9920 states to 9920 states and 13803 transitions. [2019-11-25 08:58:15,220 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9920 [2019-11-25 08:58:15,231 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9920 [2019-11-25 08:58:15,231 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9920 states and 13803 transitions. [2019-11-25 08:58:15,238 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:58:15,238 INFO L688 BuchiCegarLoop]: Abstraction has 9920 states and 13803 transitions. [2019-11-25 08:58:15,248 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9920 states and 13803 transitions. [2019-11-25 08:58:15,325 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9920 to 5636. [2019-11-25 08:58:15,326 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5636 states. [2019-11-25 08:58:15,341 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5636 states to 5636 states and 7931 transitions. [2019-11-25 08:58:15,341 INFO L711 BuchiCegarLoop]: Abstraction has 5636 states and 7931 transitions. [2019-11-25 08:58:15,341 INFO L591 BuchiCegarLoop]: Abstraction has 5636 states and 7931 transitions. [2019-11-25 08:58:15,341 INFO L424 BuchiCegarLoop]: ======== Iteration 16============ [2019-11-25 08:58:15,341 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5636 states and 7931 transitions. [2019-11-25 08:58:15,357 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 5516 [2019-11-25 08:58:15,357 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:58:15,357 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:58:15,358 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:15,359 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:15,359 INFO L794 eck$LassoCheckResult]: Stem: 91968#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 91925#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 91686#L853 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 91687#L384 assume 1 == ~m_i~0;~m_st~0 := 0; 91638#L391-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 91639#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 91725#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 91726#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 91593#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 91594#L416-1 assume !(0 == ~M_E~0); 91605#L576-1 assume !(0 == ~T1_E~0); 91606#L581-1 assume !(0 == ~T2_E~0); 91845#L586-1 assume !(0 == ~T3_E~0); 91846#L591-1 assume !(0 == ~T4_E~0); 91755#L596-1 assume !(0 == ~T5_E~0); 91756#L601-1 assume !(0 == ~E_1~0); 91799#L606-1 assume !(0 == ~E_2~0); 91654#L611-1 assume !(0 == ~E_3~0); 91655#L616-1 assume !(0 == ~E_4~0); 91525#L621-1 assume !(0 == ~E_5~0); 91526#L626-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 91721#L269 assume !(1 == ~m_pc~0); 91711#L269-2 is_master_triggered_~__retres1~0 := 0; 91712#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 91645#L281 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 91646#L710 assume !(0 != activate_threads_~tmp~1); 91647#L710-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 91648#L288 assume !(1 == ~t1_pc~0); 91757#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 91759#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 91760#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 91860#L718 assume !(0 != activate_threads_~tmp___0~0); 91868#L718-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 91869#L307 assume !(1 == ~t2_pc~0); 91928#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 91926#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 91927#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 91997#L726 assume !(0 != activate_threads_~tmp___1~0); 91998#L726-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 91999#L326 assume !(1 == ~t3_pc~0); 92019#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 92020#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 92030#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 92073#L734 assume !(0 != activate_threads_~tmp___2~0); 92088#L734-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 91570#L345 assume !(1 == ~t4_pc~0); 91571#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 91568#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 91569#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 91543#L742 assume !(0 != activate_threads_~tmp___3~0); 91518#L742-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 91519#L364 assume !(1 == ~t5_pc~0); 91798#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 91797#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 91729#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 91730#L750 assume !(0 != activate_threads_~tmp___4~0); 91766#L750-2 assume !(1 == ~M_E~0); 91770#L639-1 assume !(1 == ~T1_E~0); 91650#L644-1 assume !(1 == ~T2_E~0); 91651#L649-1 assume !(1 == ~T3_E~0); 91522#L654-1 assume !(1 == ~T4_E~0); 91523#L659-1 assume !(1 == ~T5_E~0); 91598#L664-1 assume !(1 == ~E_1~0); 91599#L669-1 assume !(1 == ~E_2~0); 91871#L674-1 assume !(1 == ~E_3~0); 91872#L679-1 assume !(1 == ~E_4~0); 91771#L684-1 assume !(1 == ~E_5~0); 91772#L890-1 [2019-11-25 08:58:15,359 INFO L796 eck$LassoCheckResult]: Loop: 91772#L890-1 assume !false; 96762#L891 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 91603#L551 assume !false; 96471#L472 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 96366#L429 assume !(0 == ~m_st~0); 96367#L433 assume !(0 == ~t1_st~0); 96369#L437 assume !(0 == ~t2_st~0); 96364#L441 assume !(0 == ~t3_st~0); 96365#L445 assume !(0 == ~t4_st~0); 96368#L449 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 96370#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 94118#L462 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 94119#L476 assume !(0 != eval_~tmp~0); 96330#L566 start_simulation_~kernel_st~0 := 2; 96327#L384-1 start_simulation_~kernel_st~0 := 3; 96326#L576-2 assume 0 == ~M_E~0;~M_E~0 := 1; 91585#L576-4 assume !(0 == ~T1_E~0); 91586#L581-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 91858#L586-3 assume !(0 == ~T3_E~0); 91859#L591-3 assume !(0 == ~T4_E~0); 92086#L596-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 96286#L601-3 assume !(0 == ~E_1~0); 96285#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 96284#L611-3 assume 0 == ~E_3~0;~E_3~0 := 1; 96283#L616-3 assume !(0 == ~E_4~0); 96282#L621-3 assume 0 == ~E_5~0;~E_5~0 := 1; 96281#L626-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 96280#L269-18 assume !(1 == ~m_pc~0); 96279#L269-20 is_master_triggered_~__retres1~0 := 0; 91681#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 91682#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 92045#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 92046#L710-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 91881#L288-18 assume !(1 == ~t1_pc~0); 91882#L288-20 is_transmit1_triggered_~__retres1~1 := 0; 91885#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 91886#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 96853#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 91832#L718-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 91833#L307-18 assume !(1 == ~t2_pc~0); 92005#L307-20 is_transmit2_triggered_~__retres1~2 := 0; 96328#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 96329#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 91951#L726-18 assume !(0 != activate_threads_~tmp___1~0); 91952#L726-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 96851#L326-18 assume !(1 == ~t3_pc~0); 96850#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 96849#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 96848#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 96847#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 96846#L734-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 96845#L345-18 assume !(1 == ~t4_pc~0); 96843#L345-20 is_transmit4_triggered_~__retres1~4 := 0; 96842#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 96841#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 96840#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 96839#L742-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 96838#L364-18 assume !(1 == ~t5_pc~0); 96837#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 96836#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 96835#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 96834#L750-18 assume !(0 != activate_threads_~tmp___4~0); 96833#L750-20 assume 1 == ~M_E~0;~M_E~0 := 2; 96832#L639-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 96831#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 96830#L649-3 assume !(1 == ~T3_E~0); 96829#L654-3 assume !(1 == ~T4_E~0); 96828#L659-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 96827#L664-3 assume !(1 == ~E_1~0); 96826#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 96825#L674-3 assume 1 == ~E_3~0;~E_3~0 := 2; 96824#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 96823#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 96822#L689-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 96820#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 96813#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 96807#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 96800#L909 assume !(0 == start_simulation_~tmp~3); 96781#L909-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 96777#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 96774#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 96773#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 96771#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 96769#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 96767#L872 start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 96765#L922 assume !(0 != start_simulation_~tmp___0~1); 91772#L890-1 [2019-11-25 08:58:15,360 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:15,360 INFO L82 PathProgramCache]: Analyzing trace with hash 866992091, now seen corresponding path program 3 times [2019-11-25 08:58:15,360 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:15,360 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2052941345] [2019-11-25 08:58:15,360 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:15,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:15,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:15,393 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:58:15,393 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:15,393 INFO L82 PathProgramCache]: Analyzing trace with hash -1696337522, now seen corresponding path program 1 times [2019-11-25 08:58:15,394 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:15,394 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [817169889] [2019-11-25 08:58:15,394 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:15,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:15,446 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:15,446 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [817169889] [2019-11-25 08:58:15,446 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:15,446 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-25 08:58:15,447 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1111328883] [2019-11-25 08:58:15,447 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:58:15,447 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:58:15,447 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-25 08:58:15,448 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-25 08:58:15,448 INFO L87 Difference]: Start difference. First operand 5636 states and 7931 transitions. cyclomatic complexity: 2311 Second operand 5 states. [2019-11-25 08:58:15,689 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:58:15,689 INFO L93 Difference]: Finished difference Result 11196 states and 15638 transitions. [2019-11-25 08:58:15,689 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-25 08:58:15,690 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11196 states and 15638 transitions. [2019-11-25 08:58:15,738 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 11044 [2019-11-25 08:58:15,837 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11196 states to 11196 states and 15638 transitions. [2019-11-25 08:58:15,837 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11196 [2019-11-25 08:58:15,843 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11196 [2019-11-25 08:58:15,843 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11196 states and 15638 transitions. [2019-11-25 08:58:15,849 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:58:15,849 INFO L688 BuchiCegarLoop]: Abstraction has 11196 states and 15638 transitions. [2019-11-25 08:58:15,856 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11196 states and 15638 transitions. [2019-11-25 08:58:15,926 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11196 to 5780. [2019-11-25 08:58:15,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5780 states. [2019-11-25 08:58:15,941 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5780 states to 5780 states and 8034 transitions. [2019-11-25 08:58:15,941 INFO L711 BuchiCegarLoop]: Abstraction has 5780 states and 8034 transitions. [2019-11-25 08:58:15,941 INFO L591 BuchiCegarLoop]: Abstraction has 5780 states and 8034 transitions. [2019-11-25 08:58:15,941 INFO L424 BuchiCegarLoop]: ======== Iteration 17============ [2019-11-25 08:58:15,941 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5780 states and 8034 transitions. [2019-11-25 08:58:15,955 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 5660 [2019-11-25 08:58:15,956 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:58:15,956 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:58:15,957 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:15,957 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:15,957 INFO L794 eck$LassoCheckResult]: Stem: 108843#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 108798#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 108542#L853 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 108543#L384 assume 1 == ~m_i~0;~m_st~0 := 0; 108484#L391-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 108485#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 108590#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 108591#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 108438#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 108439#L416-1 assume !(0 == ~M_E~0); 108450#L576-1 assume !(0 == ~T1_E~0); 108451#L581-1 assume !(0 == ~T2_E~0); 108724#L586-1 assume !(0 == ~T3_E~0); 108725#L591-1 assume !(0 == ~T4_E~0); 108620#L596-1 assume !(0 == ~T5_E~0); 108621#L601-1 assume !(0 == ~E_1~0); 108674#L606-1 assume !(0 == ~E_2~0); 108501#L611-1 assume !(0 == ~E_3~0); 108502#L616-1 assume !(0 == ~E_4~0); 108370#L621-1 assume !(0 == ~E_5~0); 108371#L626-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 108586#L269 assume !(1 == ~m_pc~0); 108575#L269-2 is_master_triggered_~__retres1~0 := 0; 108576#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 108492#L281 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 108493#L710 assume !(0 != activate_threads_~tmp~1); 108494#L710-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 108495#L288 assume !(1 == ~t1_pc~0); 108622#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 108624#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 108625#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 108737#L718 assume !(0 != activate_threads_~tmp___0~0); 108745#L718-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 108747#L307 assume !(1 == ~t2_pc~0); 108801#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 108799#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 108800#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 108872#L726 assume !(0 != activate_threads_~tmp___1~0); 108873#L726-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 108874#L326 assume !(1 == ~t3_pc~0); 108898#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 108899#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 108910#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 108946#L734 assume !(0 != activate_threads_~tmp___2~0); 108963#L734-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 108416#L345 assume !(1 == ~t4_pc~0); 108417#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 108414#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 108415#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 108388#L742 assume !(0 != activate_threads_~tmp___3~0); 108363#L742-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 108364#L364 assume !(1 == ~t5_pc~0); 108673#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 108672#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 108594#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 108595#L750 assume !(0 != activate_threads_~tmp___4~0); 108633#L750-2 assume !(1 == ~M_E~0); 108637#L639-1 assume !(1 == ~T1_E~0); 108497#L644-1 assume !(1 == ~T2_E~0); 108498#L649-1 assume !(1 == ~T3_E~0); 108367#L654-1 assume !(1 == ~T4_E~0); 108368#L659-1 assume !(1 == ~T5_E~0); 108443#L664-1 assume !(1 == ~E_1~0); 108444#L669-1 assume !(1 == ~E_2~0); 108750#L674-1 assume !(1 == ~E_3~0); 108751#L679-1 assume !(1 == ~E_4~0); 108638#L684-1 assume !(1 == ~E_5~0); 108639#L890-1 [2019-11-25 08:58:15,958 INFO L796 eck$LassoCheckResult]: Loop: 108639#L890-1 assume !false; 110743#L891 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 110740#L551 assume !false; 110738#L472 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 110732#L429 assume !(0 == ~m_st~0); 110733#L433 assume !(0 == ~t1_st~0); 110735#L437 assume !(0 == ~t2_st~0); 110730#L441 assume !(0 == ~t3_st~0); 110731#L445 assume !(0 == ~t4_st~0); 110734#L449 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 110736#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 110328#L462 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 110329#L476 assume !(0 != eval_~tmp~0); 111044#L566 start_simulation_~kernel_st~0 := 2; 111043#L384-1 start_simulation_~kernel_st~0 := 3; 111042#L576-2 assume 0 == ~M_E~0;~M_E~0 := 1; 111041#L576-4 assume !(0 == ~T1_E~0); 111040#L581-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 111039#L586-3 assume !(0 == ~T3_E~0); 111038#L591-3 assume !(0 == ~T4_E~0); 111037#L596-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 111036#L601-3 assume !(0 == ~E_1~0); 111035#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 111034#L611-3 assume 0 == ~E_3~0;~E_3~0 := 1; 111033#L616-3 assume !(0 == ~E_4~0); 111030#L621-3 assume 0 == ~E_5~0;~E_5~0 := 1; 111029#L626-3 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 111028#L269-18 assume !(1 == ~m_pc~0); 111027#L269-20 is_master_triggered_~__retres1~0 := 0; 111025#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 111022#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 111019#L710-18 assume !(0 != activate_threads_~tmp~1); 111016#L710-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 111013#L288-18 assume !(1 == ~t1_pc~0); 111010#L288-20 is_transmit1_triggered_~__retres1~1 := 0; 111006#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 111002#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 110998#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 110994#L718-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 110990#L307-18 assume 1 == ~t2_pc~0; 110985#L308-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 110980#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 110974#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 110968#L726-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 110963#L726-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 110958#L326-18 assume !(1 == ~t3_pc~0); 110953#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 110935#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 110928#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 110924#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 110920#L734-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 110916#L345-18 assume 1 == ~t4_pc~0; 110912#L346-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 110907#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 110903#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 110898#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 110893#L742-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 110888#L364-18 assume !(1 == ~t5_pc~0); 110882#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 110878#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 110874#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 110870#L750-18 assume !(0 != activate_threads_~tmp___4~0); 110866#L750-20 assume 1 == ~M_E~0;~M_E~0 := 2; 110861#L639-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 110856#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 110851#L649-3 assume !(1 == ~T3_E~0); 110846#L654-3 assume !(1 == ~T4_E~0); 110841#L659-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 110837#L664-3 assume !(1 == ~E_1~0); 110833#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 110829#L674-3 assume 1 == ~E_3~0;~E_3~0 := 2; 110825#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 110821#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 110817#L689-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 110812#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 110803#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 110799#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 110794#L909 assume !(0 == start_simulation_~tmp~3); 110790#L909-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 110782#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 110776#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 110772#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 110768#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 110764#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 110758#L872 start_simulation_#t~ret15 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 110754#L922 assume !(0 != start_simulation_~tmp___0~1); 108639#L890-1 [2019-11-25 08:58:15,958 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:15,958 INFO L82 PathProgramCache]: Analyzing trace with hash 866992091, now seen corresponding path program 4 times [2019-11-25 08:58:15,958 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:15,959 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [87343035] [2019-11-25 08:58:15,959 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:15,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:15,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:15,979 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:58:15,980 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:15,980 INFO L82 PathProgramCache]: Analyzing trace with hash 1429834252, now seen corresponding path program 1 times [2019-11-25 08:58:15,980 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:15,980 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [675709923] [2019-11-25 08:58:15,980 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:15,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:16,009 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:16,010 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [675709923] [2019-11-25 08:58:16,010 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:16,010 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:58:16,010 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [669338126] [2019-11-25 08:58:16,011 INFO L811 eck$LassoCheckResult]: loop already infeasible [2019-11-25 08:58:16,011 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:58:16,011 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:58:16,011 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:58:16,011 INFO L87 Difference]: Start difference. First operand 5780 states and 8034 transitions. cyclomatic complexity: 2270 Second operand 3 states. [2019-11-25 08:58:16,084 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:58:16,084 INFO L93 Difference]: Finished difference Result 9778 states and 13380 transitions. [2019-11-25 08:58:16,084 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:58:16,085 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9778 states and 13380 transitions. [2019-11-25 08:58:16,120 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 9624 [2019-11-25 08:58:16,152 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9778 states to 9778 states and 13380 transitions. [2019-11-25 08:58:16,152 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9778 [2019-11-25 08:58:16,158 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9778 [2019-11-25 08:58:16,158 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9778 states and 13380 transitions. [2019-11-25 08:58:16,165 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:58:16,165 INFO L688 BuchiCegarLoop]: Abstraction has 9778 states and 13380 transitions. [2019-11-25 08:58:16,172 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9778 states and 13380 transitions. [2019-11-25 08:58:16,260 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9778 to 9462. [2019-11-25 08:58:16,260 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9462 states. [2019-11-25 08:58:16,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9462 states to 9462 states and 12968 transitions. [2019-11-25 08:58:16,284 INFO L711 BuchiCegarLoop]: Abstraction has 9462 states and 12968 transitions. [2019-11-25 08:58:16,284 INFO L591 BuchiCegarLoop]: Abstraction has 9462 states and 12968 transitions. [2019-11-25 08:58:16,284 INFO L424 BuchiCegarLoop]: ======== Iteration 18============ [2019-11-25 08:58:16,284 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9462 states and 12968 transitions. [2019-11-25 08:58:16,307 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 9308 [2019-11-25 08:58:16,307 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:58:16,307 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:58:16,308 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:16,308 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:16,308 INFO L794 eck$LassoCheckResult]: Stem: 124363#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 124323#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 124099#L853 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 124100#L384 assume 1 == ~m_i~0;~m_st~0 := 0; 124046#L391-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 124047#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 124143#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 124144#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 124001#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 124002#L416-1 assume !(0 == ~M_E~0); 124013#L576-1 assume !(0 == ~T1_E~0); 124014#L581-1 assume !(0 == ~T2_E~0); 124262#L586-1 assume !(0 == ~T3_E~0); 124263#L591-1 assume !(0 == ~T4_E~0); 124173#L596-1 assume !(0 == ~T5_E~0); 124174#L601-1 assume !(0 == ~E_1~0); 124217#L606-1 assume !(0 == ~E_2~0); 124064#L611-1 assume !(0 == ~E_3~0); 124065#L616-1 assume !(0 == ~E_4~0); 123934#L621-1 assume !(0 == ~E_5~0); 123935#L626-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 124139#L269 assume !(1 == ~m_pc~0); 124128#L269-2 is_master_triggered_~__retres1~0 := 0; 124129#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 124054#L281 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 124055#L710 assume !(0 != activate_threads_~tmp~1); 124056#L710-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 124057#L288 assume !(1 == ~t1_pc~0); 124175#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 124177#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 124178#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 124276#L718 assume !(0 != activate_threads_~tmp___0~0); 124282#L718-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 124283#L307 assume !(1 == ~t2_pc~0); 124326#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 124324#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 124325#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 124398#L726 assume !(0 != activate_threads_~tmp___1~0); 124399#L726-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 124400#L326 assume !(1 == ~t3_pc~0); 124416#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 124417#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 124429#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 124473#L734 assume !(0 != activate_threads_~tmp___2~0); 124487#L734-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 123979#L345 assume !(1 == ~t4_pc~0); 123980#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 123977#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 123978#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 123952#L742 assume !(0 != activate_threads_~tmp___3~0); 123927#L742-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 123928#L364 assume !(1 == ~t5_pc~0); 124216#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 124215#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 124147#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 124148#L750 assume !(0 != activate_threads_~tmp___4~0); 124184#L750-2 assume !(1 == ~M_E~0); 124189#L639-1 assume !(1 == ~T1_E~0); 124060#L644-1 assume !(1 == ~T2_E~0); 124061#L649-1 assume !(1 == ~T3_E~0); 123931#L654-1 assume !(1 == ~T4_E~0); 123932#L659-1 assume !(1 == ~T5_E~0); 124006#L664-1 assume !(1 == ~E_1~0); 124007#L669-1 assume !(1 == ~E_2~0); 124285#L674-1 assume !(1 == ~E_3~0); 124286#L679-1 assume !(1 == ~E_4~0); 124190#L684-1 assume !(1 == ~E_5~0); 124191#L890-1 assume !false; 129280#L891 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 129191#L551 [2019-11-25 08:58:16,309 INFO L796 eck$LassoCheckResult]: Loop: 129191#L551 assume !false; 129270#L472 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 129264#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 129258#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 129253#L462 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 129248#L476 assume 0 != eval_~tmp~0; 129242#L476-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 129235#L484 assume !(0 != eval_~tmp_ndt_1~0); 129228#L481 assume !(0 == ~t1_st~0); 129218#L495 assume !(0 == ~t2_st~0); 129209#L509 assume !(0 == ~t3_st~0); 129203#L523 assume !(0 == ~t4_st~0); 129198#L537 assume !(0 == ~t5_st~0); 129191#L551 [2019-11-25 08:58:16,309 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:16,309 INFO L82 PathProgramCache]: Analyzing trace with hash -44245603, now seen corresponding path program 1 times [2019-11-25 08:58:16,309 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:16,310 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1453528469] [2019-11-25 08:58:16,310 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:16,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:16,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:16,332 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:58:16,332 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:16,332 INFO L82 PathProgramCache]: Analyzing trace with hash 346179051, now seen corresponding path program 1 times [2019-11-25 08:58:16,332 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:16,333 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [896918540] [2019-11-25 08:58:16,333 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:16,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:16,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:16,338 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:58:16,339 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:16,339 INFO L82 PathProgramCache]: Analyzing trace with hash -956602929, now seen corresponding path program 1 times [2019-11-25 08:58:16,339 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:16,339 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1490575016] [2019-11-25 08:58:16,339 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:16,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:16,367 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:16,368 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1490575016] [2019-11-25 08:58:16,368 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:16,368 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:58:16,368 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [11812650] [2019-11-25 08:58:16,453 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:58:16,453 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:58:16,453 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:58:16,453 INFO L87 Difference]: Start difference. First operand 9462 states and 12968 transitions. cyclomatic complexity: 3530 Second operand 3 states. [2019-11-25 08:58:16,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:58:16,568 INFO L93 Difference]: Finished difference Result 17851 states and 24250 transitions. [2019-11-25 08:58:16,568 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:58:16,568 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17851 states and 24250 transitions. [2019-11-25 08:58:16,638 INFO L131 ngComponentsAnalysis]: Automaton has 36 accepting balls. 16224 [2019-11-25 08:58:16,705 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17851 states to 17851 states and 24250 transitions. [2019-11-25 08:58:16,705 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17851 [2019-11-25 08:58:16,716 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17851 [2019-11-25 08:58:16,716 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17851 states and 24250 transitions. [2019-11-25 08:58:16,729 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:58:16,730 INFO L688 BuchiCegarLoop]: Abstraction has 17851 states and 24250 transitions. [2019-11-25 08:58:16,742 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17851 states and 24250 transitions. [2019-11-25 08:58:16,884 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17851 to 17323. [2019-11-25 08:58:16,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17323 states. [2019-11-25 08:58:16,929 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17323 states to 17323 states and 23562 transitions. [2019-11-25 08:58:16,929 INFO L711 BuchiCegarLoop]: Abstraction has 17323 states and 23562 transitions. [2019-11-25 08:58:16,929 INFO L591 BuchiCegarLoop]: Abstraction has 17323 states and 23562 transitions. [2019-11-25 08:58:16,929 INFO L424 BuchiCegarLoop]: ======== Iteration 19============ [2019-11-25 08:58:16,930 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17323 states and 23562 transitions. [2019-11-25 08:58:16,973 INFO L131 ngComponentsAnalysis]: Automaton has 36 accepting balls. 15696 [2019-11-25 08:58:16,973 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:58:16,973 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:58:16,974 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:16,974 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:16,975 INFO L794 eck$LassoCheckResult]: Stem: 151761#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 151707#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 151425#L853 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 151426#L384 assume 1 == ~m_i~0;~m_st~0 := 0; 151365#L391-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 151366#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 151474#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 151475#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 151324#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 151325#L416-1 assume !(0 == ~M_E~0); 151335#L576-1 assume !(0 == ~T1_E~0); 151336#L581-1 assume !(0 == ~T2_E~0); 151608#L586-1 assume !(0 == ~T3_E~0); 151609#L591-1 assume !(0 == ~T4_E~0); 151507#L596-1 assume !(0 == ~T5_E~0); 151508#L601-1 assume !(0 == ~E_1~0); 151562#L606-1 assume !(0 == ~E_2~0); 151563#L611-1 assume !(0 == ~E_3~0); 151806#L616-1 assume !(0 == ~E_4~0); 151807#L621-1 assume !(0 == ~E_5~0); 151734#L626-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 151735#L269 assume !(1 == ~m_pc~0); 151454#L269-2 is_master_triggered_~__retres1~0 := 0; 151455#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 151375#L281 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 151376#L710 assume !(0 != activate_threads_~tmp~1); 151377#L710-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 151378#L288 assume !(1 == ~t1_pc~0); 151667#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 151668#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 151626#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 151627#L718 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 151637#L718-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 151710#L307 assume !(1 == ~t2_pc~0); 151711#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 151708#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 151709#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 151813#L726 assume !(0 != activate_threads_~tmp___1~0); 151814#L726-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 151845#L326 assume !(1 == ~t3_pc~0); 151846#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 151843#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 151844#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 151923#L734 assume !(0 != activate_threads_~tmp___2~0); 151924#L734-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 151301#L345 assume !(1 == ~t4_pc~0); 151302#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 151299#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 151300#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 151273#L742 assume !(0 != activate_threads_~tmp___3~0); 151274#L742-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 151556#L364 assume !(1 == ~t5_pc~0); 151557#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 151553#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 151554#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 151517#L750 assume !(0 != activate_threads_~tmp___4~0); 151518#L750-2 assume !(1 == ~M_E~0); 151560#L639-1 assume !(1 == ~T1_E~0); 151561#L644-1 assume !(1 == ~T2_E~0); 151804#L649-1 assume !(1 == ~T3_E~0); 151805#L654-1 assume !(1 == ~T4_E~0); 151732#L659-1 assume !(1 == ~T5_E~0); 151733#L664-1 assume !(1 == ~E_1~0); 156214#L669-1 assume !(1 == ~E_2~0); 156212#L674-1 assume !(1 == ~E_3~0); 156210#L679-1 assume !(1 == ~E_4~0); 151526#L684-1 assume !(1 == ~E_5~0); 151527#L890-1 assume !false; 156116#L891 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 156114#L551 [2019-11-25 08:58:16,975 INFO L796 eck$LassoCheckResult]: Loop: 156114#L551 assume !false; 156112#L472 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 156109#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 156107#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 156105#L462 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 156103#L476 assume 0 != eval_~tmp~0; 156100#L476-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 156098#L484 assume !(0 != eval_~tmp_ndt_1~0); 156096#L481 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 156050#L498 assume !(0 != eval_~tmp_ndt_2~0); 156093#L495 assume !(0 == ~t2_st~0); 156306#L509 assume !(0 == ~t3_st~0); 156123#L523 assume !(0 == ~t4_st~0); 156119#L537 assume !(0 == ~t5_st~0); 156114#L551 [2019-11-25 08:58:16,975 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:16,975 INFO L82 PathProgramCache]: Analyzing trace with hash -701066143, now seen corresponding path program 1 times [2019-11-25 08:58:16,976 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:16,976 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1466127037] [2019-11-25 08:58:16,976 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:16,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:16,992 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:16,992 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1466127037] [2019-11-25 08:58:16,992 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:16,992 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:58:16,993 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1254560526] [2019-11-25 08:58:16,993 INFO L799 eck$LassoCheckResult]: stem already infeasible [2019-11-25 08:58:16,993 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:16,993 INFO L82 PathProgramCache]: Analyzing trace with hash 1252896484, now seen corresponding path program 1 times [2019-11-25 08:58:16,993 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:16,993 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [367338276] [2019-11-25 08:58:16,993 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:16,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:16,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:17,001 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:58:17,090 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:58:17,090 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:58:17,090 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:58:17,090 INFO L87 Difference]: Start difference. First operand 17323 states and 23562 transitions. cyclomatic complexity: 6275 Second operand 3 states. [2019-11-25 08:58:17,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:58:17,137 INFO L93 Difference]: Finished difference Result 11670 states and 15827 transitions. [2019-11-25 08:58:17,137 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:58:17,138 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11670 states and 15827 transitions. [2019-11-25 08:58:17,178 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 11492 [2019-11-25 08:58:17,216 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11670 states to 11670 states and 15827 transitions. [2019-11-25 08:58:17,217 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11670 [2019-11-25 08:58:17,223 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11670 [2019-11-25 08:58:17,223 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11670 states and 15827 transitions. [2019-11-25 08:58:17,232 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:58:17,232 INFO L688 BuchiCegarLoop]: Abstraction has 11670 states and 15827 transitions. [2019-11-25 08:58:17,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11670 states and 15827 transitions. [2019-11-25 08:58:17,473 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11670 to 11670. [2019-11-25 08:58:17,474 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11670 states. [2019-11-25 08:58:17,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11670 states to 11670 states and 15827 transitions. [2019-11-25 08:58:17,502 INFO L711 BuchiCegarLoop]: Abstraction has 11670 states and 15827 transitions. [2019-11-25 08:58:17,502 INFO L591 BuchiCegarLoop]: Abstraction has 11670 states and 15827 transitions. [2019-11-25 08:58:17,503 INFO L424 BuchiCegarLoop]: ======== Iteration 20============ [2019-11-25 08:58:17,503 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11670 states and 15827 transitions. [2019-11-25 08:58:17,530 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 11492 [2019-11-25 08:58:17,530 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:58:17,530 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:58:17,531 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:17,531 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:17,531 INFO L794 eck$LassoCheckResult]: Stem: 180698#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 180656#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 180410#L853 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 180411#L384 assume 1 == ~m_i~0;~m_st~0 := 0; 180359#L391-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 180360#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 180457#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 180458#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 180318#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 180319#L416-1 assume !(0 == ~M_E~0); 180329#L576-1 assume !(0 == ~T1_E~0); 180330#L581-1 assume !(0 == ~T2_E~0); 180579#L586-1 assume !(0 == ~T3_E~0); 180580#L591-1 assume !(0 == ~T4_E~0); 180488#L596-1 assume !(0 == ~T5_E~0); 180489#L601-1 assume !(0 == ~E_1~0); 180536#L606-1 assume !(0 == ~E_2~0); 180377#L611-1 assume !(0 == ~E_3~0); 180378#L616-1 assume !(0 == ~E_4~0); 180254#L621-1 assume !(0 == ~E_5~0); 180255#L626-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 180452#L269 assume !(1 == ~m_pc~0); 180440#L269-2 is_master_triggered_~__retres1~0 := 0; 180441#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 180368#L281 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 180369#L710 assume !(0 != activate_threads_~tmp~1); 180370#L710-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 180371#L288 assume !(1 == ~t1_pc~0); 180490#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 180491#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 180492#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 180595#L718 assume !(0 != activate_threads_~tmp___0~0); 180606#L718-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 180607#L307 assume !(1 == ~t2_pc~0); 180659#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 180657#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 180658#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 180731#L726 assume !(0 != activate_threads_~tmp___1~0); 180732#L726-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 180733#L326 assume !(1 == ~t3_pc~0); 180750#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 180751#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 180763#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 180806#L734 assume !(0 != activate_threads_~tmp___2~0); 180823#L734-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 180298#L345 assume !(1 == ~t4_pc~0); 180299#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 180296#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 180297#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 180272#L742 assume !(0 != activate_threads_~tmp___3~0); 180244#L742-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 180245#L364 assume !(1 == ~t5_pc~0); 180535#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 180533#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 180461#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 180462#L750 assume !(0 != activate_threads_~tmp___4~0); 180500#L750-2 assume !(1 == ~M_E~0); 180506#L639-1 assume !(1 == ~T1_E~0); 180372#L644-1 assume !(1 == ~T2_E~0); 180373#L649-1 assume !(1 == ~T3_E~0); 180251#L654-1 assume !(1 == ~T4_E~0); 180252#L659-1 assume !(1 == ~T5_E~0); 180322#L664-1 assume !(1 == ~E_1~0); 180323#L669-1 assume !(1 == ~E_2~0); 180608#L674-1 assume !(1 == ~E_3~0); 180609#L679-1 assume !(1 == ~E_4~0); 180507#L684-1 assume !(1 == ~E_5~0); 180508#L890-1 assume !false; 181514#L891 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 181428#L551 [2019-11-25 08:58:17,532 INFO L796 eck$LassoCheckResult]: Loop: 181428#L551 assume !false; 181506#L472 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 181501#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 181497#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 181493#L462 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 181488#L476 assume 0 != eval_~tmp~0; 181483#L476-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 181478#L484 assume !(0 != eval_~tmp_ndt_1~0); 181474#L481 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 181467#L498 assume !(0 != eval_~tmp_ndt_2~0); 181461#L495 assume !(0 == ~t2_st~0); 181453#L509 assume !(0 == ~t3_st~0); 181450#L523 assume !(0 == ~t4_st~0); 181446#L537 assume !(0 == ~t5_st~0); 181428#L551 [2019-11-25 08:58:17,532 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:17,532 INFO L82 PathProgramCache]: Analyzing trace with hash -44245603, now seen corresponding path program 2 times [2019-11-25 08:58:17,532 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:17,532 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1566122259] [2019-11-25 08:58:17,533 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:17,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:17,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:17,554 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:58:17,555 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:17,555 INFO L82 PathProgramCache]: Analyzing trace with hash 1252896484, now seen corresponding path program 2 times [2019-11-25 08:58:17,555 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:17,555 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [786304507] [2019-11-25 08:58:17,555 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:17,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:17,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:17,561 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:58:17,561 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:17,561 INFO L82 PathProgramCache]: Analyzing trace with hash -478639232, now seen corresponding path program 1 times [2019-11-25 08:58:17,562 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:17,562 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [887861345] [2019-11-25 08:58:17,562 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:17,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:17,593 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:17,593 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [887861345] [2019-11-25 08:58:17,594 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:17,594 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:58:17,594 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2059215188] [2019-11-25 08:58:17,674 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:58:17,675 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:58:17,675 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:58:17,675 INFO L87 Difference]: Start difference. First operand 11670 states and 15827 transitions. cyclomatic complexity: 4181 Second operand 3 states. [2019-11-25 08:58:17,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:58:17,789 INFO L93 Difference]: Finished difference Result 21350 states and 28875 transitions. [2019-11-25 08:58:17,789 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:58:17,789 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21350 states and 28875 transitions. [2019-11-25 08:58:17,866 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 21068 [2019-11-25 08:58:17,936 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21350 states to 21350 states and 28875 transitions. [2019-11-25 08:58:17,936 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21350 [2019-11-25 08:58:17,949 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21350 [2019-11-25 08:58:17,949 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21350 states and 28875 transitions. [2019-11-25 08:58:17,964 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:58:17,964 INFO L688 BuchiCegarLoop]: Abstraction has 21350 states and 28875 transitions. [2019-11-25 08:58:17,979 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21350 states and 28875 transitions. [2019-11-25 08:58:18,132 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21350 to 20246. [2019-11-25 08:58:18,132 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20246 states. [2019-11-25 08:58:18,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20246 states to 20246 states and 27435 transitions. [2019-11-25 08:58:18,182 INFO L711 BuchiCegarLoop]: Abstraction has 20246 states and 27435 transitions. [2019-11-25 08:58:18,182 INFO L591 BuchiCegarLoop]: Abstraction has 20246 states and 27435 transitions. [2019-11-25 08:58:18,183 INFO L424 BuchiCegarLoop]: ======== Iteration 21============ [2019-11-25 08:58:18,183 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20246 states and 27435 transitions. [2019-11-25 08:58:18,233 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 19964 [2019-11-25 08:58:18,234 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:58:18,234 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:58:18,235 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:18,235 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:18,235 INFO L794 eck$LassoCheckResult]: Stem: 213733#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 213685#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 213442#L853 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 213443#L384 assume 1 == ~m_i~0;~m_st~0 := 0; 213391#L391-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 213392#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 213485#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 213486#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 213346#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 213347#L416-1 assume !(0 == ~M_E~0); 213357#L576-1 assume !(0 == ~T1_E~0); 213358#L581-1 assume !(0 == ~T2_E~0); 213615#L586-1 assume !(0 == ~T3_E~0); 213616#L591-1 assume !(0 == ~T4_E~0); 213515#L596-1 assume !(0 == ~T5_E~0); 213516#L601-1 assume !(0 == ~E_1~0); 213564#L606-1 assume !(0 == ~E_2~0); 213408#L611-1 assume !(0 == ~E_3~0); 213409#L616-1 assume !(0 == ~E_4~0); 213282#L621-1 assume !(0 == ~E_5~0); 213283#L626-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 213480#L269 assume !(1 == ~m_pc~0); 213467#L269-2 is_master_triggered_~__retres1~0 := 0; 213468#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 213398#L281 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 213399#L710 assume !(0 != activate_threads_~tmp~1); 213400#L710-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 213401#L288 assume !(1 == ~t1_pc~0); 213517#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 213519#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 213520#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 213628#L718 assume !(0 != activate_threads_~tmp___0~0); 213634#L718-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 213636#L307 assume !(1 == ~t2_pc~0); 213688#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 213686#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 213687#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 213770#L726 assume !(0 != activate_threads_~tmp___1~0); 213771#L726-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 213772#L326 assume !(1 == ~t3_pc~0); 213792#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 213793#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 213804#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 213850#L734 assume !(0 != activate_threads_~tmp___2~0); 213863#L734-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 213326#L345 assume !(1 == ~t4_pc~0); 213327#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 213324#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 213325#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 213300#L742 assume !(0 != activate_threads_~tmp___3~0); 213275#L742-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 213276#L364 assume !(1 == ~t5_pc~0); 213563#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 213562#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 213489#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 213490#L750 assume !(0 != activate_threads_~tmp___4~0); 213526#L750-2 assume !(1 == ~M_E~0); 213530#L639-1 assume !(1 == ~T1_E~0); 213404#L644-1 assume !(1 == ~T2_E~0); 213405#L649-1 assume !(1 == ~T3_E~0); 213279#L654-1 assume !(1 == ~T4_E~0); 213280#L659-1 assume !(1 == ~T5_E~0); 213350#L664-1 assume !(1 == ~E_1~0); 213351#L669-1 assume !(1 == ~E_2~0); 213638#L674-1 assume !(1 == ~E_3~0); 213639#L679-1 assume !(1 == ~E_4~0); 213532#L684-1 assume !(1 == ~E_5~0); 213533#L890-1 assume !false; 218021#L891 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 218015#L551 [2019-11-25 08:58:18,235 INFO L796 eck$LassoCheckResult]: Loop: 218015#L551 assume !false; 218008#L472 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 218003#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 217999#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 217994#L462 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 217989#L476 assume 0 != eval_~tmp~0; 217980#L476-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 217974#L484 assume !(0 != eval_~tmp_ndt_1~0); 217968#L481 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 217960#L498 assume !(0 != eval_~tmp_ndt_2~0); 217622#L495 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 217616#L512 assume !(0 != eval_~tmp_ndt_3~0); 217608#L509 assume !(0 == ~t3_st~0); 217602#L523 assume !(0 == ~t4_st~0); 218024#L537 assume !(0 == ~t5_st~0); 218015#L551 [2019-11-25 08:58:18,236 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:18,236 INFO L82 PathProgramCache]: Analyzing trace with hash -44245603, now seen corresponding path program 3 times [2019-11-25 08:58:18,236 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:18,236 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1519437565] [2019-11-25 08:58:18,236 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:18,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:18,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:18,265 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:58:18,266 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:18,266 INFO L82 PathProgramCache]: Analyzing trace with hash 17875238, now seen corresponding path program 1 times [2019-11-25 08:58:18,266 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:18,266 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2876824] [2019-11-25 08:58:18,267 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:18,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:18,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:18,275 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:58:18,276 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:18,276 INFO L82 PathProgramCache]: Analyzing trace with hash -2120124406, now seen corresponding path program 1 times [2019-11-25 08:58:18,276 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:18,277 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [651841408] [2019-11-25 08:58:18,277 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:18,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:18,310 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:18,310 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [651841408] [2019-11-25 08:58:18,310 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:18,310 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:58:18,311 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [708324428] [2019-11-25 08:58:18,432 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:58:18,433 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:58:18,433 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:58:18,433 INFO L87 Difference]: Start difference. First operand 20246 states and 27435 transitions. cyclomatic complexity: 7213 Second operand 3 states. [2019-11-25 08:58:18,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:58:18,557 INFO L93 Difference]: Finished difference Result 26670 states and 36021 transitions. [2019-11-25 08:58:18,558 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:58:18,558 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26670 states and 36021 transitions. [2019-11-25 08:58:18,659 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 26332 [2019-11-25 08:58:18,752 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26670 states to 26670 states and 36021 transitions. [2019-11-25 08:58:18,752 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26670 [2019-11-25 08:58:18,768 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26670 [2019-11-25 08:58:18,768 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26670 states and 36021 transitions. [2019-11-25 08:58:18,783 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:58:18,783 INFO L688 BuchiCegarLoop]: Abstraction has 26670 states and 36021 transitions. [2019-11-25 08:58:18,801 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26670 states and 36021 transitions. [2019-11-25 08:58:19,002 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26670 to 25878. [2019-11-25 08:58:19,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25878 states. [2019-11-25 08:58:19,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25878 states to 25878 states and 34989 transitions. [2019-11-25 08:58:19,078 INFO L711 BuchiCegarLoop]: Abstraction has 25878 states and 34989 transitions. [2019-11-25 08:58:19,078 INFO L591 BuchiCegarLoop]: Abstraction has 25878 states and 34989 transitions. [2019-11-25 08:58:19,078 INFO L424 BuchiCegarLoop]: ======== Iteration 22============ [2019-11-25 08:58:19,078 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25878 states and 34989 transitions. [2019-11-25 08:58:19,157 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 25540 [2019-11-25 08:58:19,158 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:58:19,158 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:58:19,159 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:19,159 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:19,159 INFO L794 eck$LassoCheckResult]: Stem: 260661#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 260617#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 260371#L853 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 260372#L384 assume 1 == ~m_i~0;~m_st~0 := 0; 260314#L391-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 260315#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 260418#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 260419#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 260271#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 260272#L416-1 assume !(0 == ~M_E~0); 260282#L576-1 assume !(0 == ~T1_E~0); 260283#L581-1 assume !(0 == ~T2_E~0); 260544#L586-1 assume !(0 == ~T3_E~0); 260545#L591-1 assume !(0 == ~T4_E~0); 260450#L596-1 assume !(0 == ~T5_E~0); 260451#L601-1 assume !(0 == ~E_1~0); 260498#L606-1 assume !(0 == ~E_2~0); 260333#L611-1 assume !(0 == ~E_3~0); 260334#L616-1 assume !(0 == ~E_4~0); 260206#L621-1 assume !(0 == ~E_5~0); 260207#L626-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 260413#L269 assume !(1 == ~m_pc~0); 260401#L269-2 is_master_triggered_~__retres1~0 := 0; 260402#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 260323#L281 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 260324#L710 assume !(0 != activate_threads_~tmp~1); 260326#L710-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 260327#L288 assume !(1 == ~t1_pc~0); 260452#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 260453#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 260454#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 260559#L718 assume !(0 != activate_threads_~tmp___0~0); 260567#L718-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 260568#L307 assume !(1 == ~t2_pc~0); 260620#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 260618#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 260619#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 260693#L726 assume !(0 != activate_threads_~tmp___1~0); 260694#L726-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 260695#L326 assume !(1 == ~t3_pc~0); 260718#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 260719#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 260733#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 260786#L734 assume !(0 != activate_threads_~tmp___2~0); 260799#L734-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 260251#L345 assume !(1 == ~t4_pc~0); 260252#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 260249#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 260250#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 260224#L742 assume !(0 != activate_threads_~tmp___3~0); 260196#L742-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 260197#L364 assume !(1 == ~t5_pc~0); 260497#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 260494#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 260423#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 260424#L750 assume !(0 != activate_threads_~tmp___4~0); 260459#L750-2 assume !(1 == ~M_E~0); 260466#L639-1 assume !(1 == ~T1_E~0); 260328#L644-1 assume !(1 == ~T2_E~0); 260329#L649-1 assume !(1 == ~T3_E~0); 260203#L654-1 assume !(1 == ~T4_E~0); 260204#L659-1 assume !(1 == ~T5_E~0); 260275#L664-1 assume !(1 == ~E_1~0); 260276#L669-1 assume !(1 == ~E_2~0); 260569#L674-1 assume !(1 == ~E_3~0); 260570#L679-1 assume !(1 == ~E_4~0); 260467#L684-1 assume !(1 == ~E_5~0); 260468#L890-1 assume !false; 263639#L891 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 263637#L551 [2019-11-25 08:58:19,160 INFO L796 eck$LassoCheckResult]: Loop: 263637#L551 assume !false; 263635#L472 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 263632#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 263629#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 263626#L462 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 263624#L476 assume 0 != eval_~tmp~0; 263597#L476-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 263222#L484 assume !(0 != eval_~tmp_ndt_1~0); 262983#L481 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 262981#L498 assume !(0 != eval_~tmp_ndt_2~0); 262980#L495 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 262938#L512 assume !(0 != eval_~tmp_ndt_3~0); 262940#L509 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 262932#L526 assume !(0 != eval_~tmp_ndt_4~0); 262934#L523 assume !(0 == ~t4_st~0); 263642#L537 assume !(0 == ~t5_st~0); 263637#L551 [2019-11-25 08:58:19,160 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:19,160 INFO L82 PathProgramCache]: Analyzing trace with hash -44245603, now seen corresponding path program 4 times [2019-11-25 08:58:19,160 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:19,161 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1548394233] [2019-11-25 08:58:19,161 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:19,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:19,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:19,186 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:58:19,187 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:19,187 INFO L82 PathProgramCache]: Analyzing trace with hash 548744105, now seen corresponding path program 1 times [2019-11-25 08:58:19,187 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:19,187 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1850809388] [2019-11-25 08:58:19,188 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:19,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:19,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:19,195 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:58:19,196 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:19,196 INFO L82 PathProgramCache]: Analyzing trace with hash -1304735419, now seen corresponding path program 1 times [2019-11-25 08:58:19,196 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:19,196 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1985211049] [2019-11-25 08:58:19,197 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:19,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:19,363 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:19,363 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1985211049] [2019-11-25 08:58:19,364 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:19,364 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-25 08:58:19,364 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1881660598] [2019-11-25 08:58:19,473 WARN L192 SmtUtils]: Spent 107.00 ms on a formula simplification. DAG size of input: 41 DAG size of output: 39 [2019-11-25 08:58:19,512 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:58:19,513 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:58:19,513 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:58:19,513 INFO L87 Difference]: Start difference. First operand 25878 states and 34989 transitions. cyclomatic complexity: 9135 Second operand 3 states. [2019-11-25 08:58:19,655 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:58:19,655 INFO L93 Difference]: Finished difference Result 44956 states and 60591 transitions. [2019-11-25 08:58:19,656 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:58:19,656 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44956 states and 60591 transitions. [2019-11-25 08:58:19,818 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 44354 [2019-11-25 08:58:19,964 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44956 states to 44956 states and 60591 transitions. [2019-11-25 08:58:19,964 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44956 [2019-11-25 08:58:19,989 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44956 [2019-11-25 08:58:19,989 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44956 states and 60591 transitions. [2019-11-25 08:58:20,012 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:58:20,012 INFO L688 BuchiCegarLoop]: Abstraction has 44956 states and 60591 transitions. [2019-11-25 08:58:20,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44956 states and 60591 transitions. [2019-11-25 08:58:20,306 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44956 to 43588. [2019-11-25 08:58:20,306 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 43588 states. [2019-11-25 08:58:20,389 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43588 states to 43588 states and 58935 transitions. [2019-11-25 08:58:20,389 INFO L711 BuchiCegarLoop]: Abstraction has 43588 states and 58935 transitions. [2019-11-25 08:58:20,390 INFO L591 BuchiCegarLoop]: Abstraction has 43588 states and 58935 transitions. [2019-11-25 08:58:20,390 INFO L424 BuchiCegarLoop]: ======== Iteration 23============ [2019-11-25 08:58:20,390 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43588 states and 58935 transitions. [2019-11-25 08:58:20,498 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 42986 [2019-11-25 08:58:20,498 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:58:20,498 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:58:20,499 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:20,499 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:20,499 INFO L794 eck$LassoCheckResult]: Stem: 331529#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 331477#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 331211#L853 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 331212#L384 assume 1 == ~m_i~0;~m_st~0 := 0; 331156#L391-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 331157#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 331256#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 331257#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 331115#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 331116#L416-1 assume !(0 == ~M_E~0); 331126#L576-1 assume !(0 == ~T1_E~0); 331127#L581-1 assume !(0 == ~T2_E~0); 331394#L586-1 assume !(0 == ~T3_E~0); 331395#L591-1 assume !(0 == ~T4_E~0); 331288#L596-1 assume !(0 == ~T5_E~0); 331289#L601-1 assume !(0 == ~E_1~0); 331344#L606-1 assume !(0 == ~E_2~0); 331176#L611-1 assume !(0 == ~E_3~0); 331177#L616-1 assume !(0 == ~E_4~0); 331048#L621-1 assume !(0 == ~E_5~0); 331049#L626-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 331252#L269 assume !(1 == ~m_pc~0); 331240#L269-2 is_master_triggered_~__retres1~0 := 0; 331241#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 331165#L281 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 331166#L710 assume !(0 != activate_threads_~tmp~1); 331168#L710-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 331169#L288 assume !(1 == ~t1_pc~0); 331290#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 331291#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 331292#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 331410#L718 assume !(0 != activate_threads_~tmp___0~0); 331420#L718-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 331422#L307 assume !(1 == ~t2_pc~0); 331480#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 331478#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 331479#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 331567#L726 assume !(0 != activate_threads_~tmp___1~0); 331568#L726-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 331569#L326 assume !(1 == ~t3_pc~0); 331595#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 331596#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 331607#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 331660#L734 assume !(0 != activate_threads_~tmp___2~0); 331679#L734-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 331092#L345 assume !(1 == ~t4_pc~0); 331093#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 331090#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 331091#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 331066#L742 assume !(0 != activate_threads_~tmp___3~0); 331041#L742-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 331042#L364 assume !(1 == ~t5_pc~0); 331342#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 331339#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 331260#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 331261#L750 assume !(0 != activate_threads_~tmp___4~0); 331300#L750-2 assume !(1 == ~M_E~0); 331305#L639-1 assume !(1 == ~T1_E~0); 331170#L644-1 assume !(1 == ~T2_E~0); 331171#L649-1 assume !(1 == ~T3_E~0); 331045#L654-1 assume !(1 == ~T4_E~0); 331046#L659-1 assume !(1 == ~T5_E~0); 331119#L664-1 assume !(1 == ~E_1~0); 331120#L669-1 assume !(1 == ~E_2~0); 331423#L674-1 assume !(1 == ~E_3~0); 331424#L679-1 assume !(1 == ~E_4~0); 331306#L684-1 assume !(1 == ~E_5~0); 331307#L890-1 assume !false; 336652#L891 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 336651#L551 [2019-11-25 08:58:20,500 INFO L796 eck$LassoCheckResult]: Loop: 336651#L551 assume !false; 336650#L472 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 336647#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 336643#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 336641#L462 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 336639#L476 assume 0 != eval_~tmp~0; 336635#L476-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 336632#L484 assume !(0 != eval_~tmp_ndt_1~0); 336630#L481 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 336627#L498 assume !(0 != eval_~tmp_ndt_2~0); 336628#L495 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 337080#L512 assume !(0 != eval_~tmp_ndt_3~0); 337106#L509 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 337549#L526 assume !(0 != eval_~tmp_ndt_4~0); 336658#L523 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 336656#L540 assume !(0 != eval_~tmp_ndt_5~0); 336655#L537 assume !(0 == ~t5_st~0); 336651#L551 [2019-11-25 08:58:20,500 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:20,500 INFO L82 PathProgramCache]: Analyzing trace with hash -44245603, now seen corresponding path program 5 times [2019-11-25 08:58:20,501 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:20,501 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [477962793] [2019-11-25 08:58:20,501 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:20,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:20,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:20,524 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:58:20,525 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:20,525 INFO L82 PathProgramCache]: Analyzing trace with hash -168970143, now seen corresponding path program 1 times [2019-11-25 08:58:20,525 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:20,525 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1704325831] [2019-11-25 08:58:20,525 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:20,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:20,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:20,533 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:58:20,535 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:20,535 INFO L82 PathProgramCache]: Analyzing trace with hash -1792260539, now seen corresponding path program 1 times [2019-11-25 08:58:20,536 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:20,536 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1323370596] [2019-11-25 08:58:20,536 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:20,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-25 08:58:20,568 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-25 08:58:20,569 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1323370596] [2019-11-25 08:58:20,569 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-25 08:58:20,569 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-25 08:58:20,569 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1420702382] [2019-11-25 08:58:20,699 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-25 08:58:20,699 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-25 08:58:20,699 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-25 08:58:20,699 INFO L87 Difference]: Start difference. First operand 43588 states and 58935 transitions. cyclomatic complexity: 15371 Second operand 3 states. [2019-11-25 08:58:20,873 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-25 08:58:20,873 INFO L93 Difference]: Finished difference Result 59615 states and 80353 transitions. [2019-11-25 08:58:20,874 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-25 08:58:20,874 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 59615 states and 80353 transitions. [2019-11-25 08:58:21,407 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 58749 [2019-11-25 08:58:21,548 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 59615 states to 59615 states and 80353 transitions. [2019-11-25 08:58:21,549 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 59615 [2019-11-25 08:58:21,582 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 59615 [2019-11-25 08:58:21,582 INFO L73 IsDeterministic]: Start isDeterministic. Operand 59615 states and 80353 transitions. [2019-11-25 08:58:21,610 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2019-11-25 08:58:21,610 INFO L688 BuchiCegarLoop]: Abstraction has 59615 states and 80353 transitions. [2019-11-25 08:58:21,642 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59615 states and 80353 transitions. [2019-11-25 08:58:21,997 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59615 to 59615. [2019-11-25 08:58:21,997 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 59615 states. [2019-11-25 08:58:22,102 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59615 states to 59615 states and 80353 transitions. [2019-11-25 08:58:22,102 INFO L711 BuchiCegarLoop]: Abstraction has 59615 states and 80353 transitions. [2019-11-25 08:58:22,102 INFO L591 BuchiCegarLoop]: Abstraction has 59615 states and 80353 transitions. [2019-11-25 08:58:22,102 INFO L424 BuchiCegarLoop]: ======== Iteration 24============ [2019-11-25 08:58:22,103 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59615 states and 80353 transitions. [2019-11-25 08:58:22,234 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 58749 [2019-11-25 08:58:22,234 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2019-11-25 08:58:22,235 INFO L119 BuchiIsEmpty]: Starting construction of run [2019-11-25 08:58:22,236 INFO L849 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:22,236 INFO L850 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-25 08:58:22,236 INFO L794 eck$LassoCheckResult]: Stem: 434730#ULTIMATE.startENTRY ~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 434681#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 434427#L853 havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 434428#L384 assume 1 == ~m_i~0;~m_st~0 := 0; 434370#L391-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 434371#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 434474#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 434475#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 434326#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 434327#L416-1 assume !(0 == ~M_E~0); 434337#L576-1 assume !(0 == ~T1_E~0); 434338#L581-1 assume !(0 == ~T2_E~0); 434609#L586-1 assume !(0 == ~T3_E~0); 434610#L591-1 assume !(0 == ~T4_E~0); 434505#L596-1 assume !(0 == ~T5_E~0); 434506#L601-1 assume !(0 == ~E_1~0); 434557#L606-1 assume !(0 == ~E_2~0); 434388#L611-1 assume !(0 == ~E_3~0); 434389#L616-1 assume !(0 == ~E_4~0); 434260#L621-1 assume !(0 == ~E_5~0); 434261#L626-1 havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 434470#L269 assume !(1 == ~m_pc~0); 434459#L269-2 is_master_triggered_~__retres1~0 := 0; 434460#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 434378#L281 activate_threads_#t~ret7 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 434379#L710 assume !(0 != activate_threads_~tmp~1); 434380#L710-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 434381#L288 assume !(1 == ~t1_pc~0); 434507#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 434509#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 434510#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 434622#L718 assume !(0 != activate_threads_~tmp___0~0); 434631#L718-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 434632#L307 assume !(1 == ~t2_pc~0); 434684#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 434682#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 434683#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 434769#L726 assume !(0 != activate_threads_~tmp___1~0); 434770#L726-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 434771#L326 assume !(1 == ~t3_pc~0); 434797#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 434798#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 434813#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 434874#L734 assume !(0 != activate_threads_~tmp___2~0); 434889#L734-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 434306#L345 assume !(1 == ~t4_pc~0); 434307#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 434304#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 434305#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 434279#L742 assume !(0 != activate_threads_~tmp___3~0); 434252#L742-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 434253#L364 assume !(1 == ~t5_pc~0); 434553#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 434552#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 434478#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 434479#L750 assume !(0 != activate_threads_~tmp___4~0); 434516#L750-2 assume !(1 == ~M_E~0); 434521#L639-1 assume !(1 == ~T1_E~0); 434384#L644-1 assume !(1 == ~T2_E~0); 434385#L649-1 assume !(1 == ~T3_E~0); 434256#L654-1 assume !(1 == ~T4_E~0); 434257#L659-1 assume !(1 == ~T5_E~0); 434330#L664-1 assume !(1 == ~E_1~0); 434331#L669-1 assume !(1 == ~E_2~0); 434634#L674-1 assume !(1 == ~E_3~0); 434635#L679-1 assume !(1 == ~E_4~0); 434523#L684-1 assume !(1 == ~E_5~0); 434524#L890-1 assume !false; 455490#L891 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 455488#L551 [2019-11-25 08:58:22,236 INFO L796 eck$LassoCheckResult]: Loop: 455488#L551 assume !false; 455486#L472 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 455483#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 455481#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 455479#L462 eval_#t~ret0 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 455477#L476 assume 0 != eval_~tmp~0; 455474#L476-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 455470#L484 assume !(0 != eval_~tmp_ndt_1~0); 455468#L481 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 455466#L498 assume !(0 != eval_~tmp_ndt_2~0); 455462#L495 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 455425#L512 assume !(0 != eval_~tmp_ndt_3~0); 455460#L509 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 455377#L526 assume !(0 != eval_~tmp_ndt_4~0); 455378#L523 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 455496#L540 assume !(0 != eval_~tmp_ndt_5~0); 455493#L537 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 455491#L554 assume !(0 != eval_~tmp_ndt_6~0); 455488#L551 [2019-11-25 08:58:22,237 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:22,237 INFO L82 PathProgramCache]: Analyzing trace with hash -44245603, now seen corresponding path program 6 times [2019-11-25 08:58:22,237 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:22,237 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [454338894] [2019-11-25 08:58:22,238 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:22,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:22,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:22,262 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:58:22,262 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:22,262 INFO L82 PathProgramCache]: Analyzing trace with hash -943106962, now seen corresponding path program 1 times [2019-11-25 08:58:22,262 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:22,263 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1119672920] [2019-11-25 08:58:22,263 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:22,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:22,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:22,269 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:58:22,269 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-25 08:58:22,269 INFO L82 PathProgramCache]: Analyzing trace with hash 274498314, now seen corresponding path program 1 times [2019-11-25 08:58:22,269 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-25 08:58:22,270 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [757724031] [2019-11-25 08:58:22,270 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-25 08:58:22,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:22,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-25 08:58:22,304 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-25 08:58:22,414 WARN L192 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 45 [2019-11-25 08:58:23,231 WARN L192 SmtUtils]: Spent 743.00 ms on a formula simplification. DAG size of input: 188 DAG size of output: 126 [2019-11-25 08:58:23,433 WARN L192 SmtUtils]: Spent 191.00 ms on a formula simplification that was a NOOP. DAG size: 100 [2019-11-25 08:58:23,494 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 25.11 08:58:23 BoogieIcfgContainer [2019-11-25 08:58:23,494 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2019-11-25 08:58:23,495 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-25 08:58:23,495 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-25 08:58:23,495 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-25 08:58:23,496 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 08:58:10" (3/4) ... [2019-11-25 08:58:23,499 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2019-11-25 08:58:23,562 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_c943f5b4-42aa-45ad-a775-4c520edda3ad/bin/uautomizer/witness.graphml [2019-11-25 08:58:23,563 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-25 08:58:23,564 INFO L168 Benchmark]: Toolchain (without parser) took 14868.07 ms. Allocated memory was 1.0 GB in the beginning and 1.8 GB in the end (delta: 790.1 MB). Free memory was 952.8 MB in the beginning and 823.9 MB in the end (delta: 128.9 MB). Peak memory consumption was 919.0 MB. Max. memory is 11.5 GB. [2019-11-25 08:58:23,564 INFO L168 Benchmark]: CDTParser took 0.21 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-25 08:58:23,564 INFO L168 Benchmark]: CACSL2BoogieTranslator took 400.14 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 140.0 MB). Free memory was 952.8 MB in the beginning and 1.1 GB in the end (delta: -171.3 MB). Peak memory consumption was 24.6 MB. Max. memory is 11.5 GB. [2019-11-25 08:58:23,565 INFO L168 Benchmark]: Boogie Procedure Inliner took 63.20 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-25 08:58:23,565 INFO L168 Benchmark]: Boogie Preprocessor took 60.07 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.9 MB). Peak memory consumption was 6.9 MB. Max. memory is 11.5 GB. [2019-11-25 08:58:23,565 INFO L168 Benchmark]: RCFGBuilder took 1509.15 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 995.8 MB in the end (delta: 121.4 MB). Peak memory consumption was 121.4 MB. Max. memory is 11.5 GB. [2019-11-25 08:58:23,566 INFO L168 Benchmark]: BuchiAutomizer took 12763.70 ms. Allocated memory was 1.2 GB in the beginning and 1.8 GB in the end (delta: 650.1 MB). Free memory was 995.8 MB in the beginning and 829.9 MB in the end (delta: 166.0 MB). Peak memory consumption was 816.1 MB. Max. memory is 11.5 GB. [2019-11-25 08:58:23,566 INFO L168 Benchmark]: Witness Printer took 67.64 ms. Allocated memory is still 1.8 GB. Free memory was 829.9 MB in the beginning and 823.9 MB in the end (delta: 6.0 MB). Peak memory consumption was 6.0 MB. Max. memory is 11.5 GB. [2019-11-25 08:58:23,568 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.21 ms. Allocated memory is still 1.0 GB. Free memory is still 967.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 400.14 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 140.0 MB). Free memory was 952.8 MB in the beginning and 1.1 GB in the end (delta: -171.3 MB). Peak memory consumption was 24.6 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 63.20 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 60.07 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.9 MB). Peak memory consumption was 6.9 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1509.15 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 995.8 MB in the end (delta: 121.4 MB). Peak memory consumption was 121.4 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 12763.70 ms. Allocated memory was 1.2 GB in the beginning and 1.8 GB in the end (delta: 650.1 MB). Free memory was 995.8 MB in the beginning and 829.9 MB in the end (delta: 166.0 MB). Peak memory consumption was 816.1 MB. Max. memory is 11.5 GB. * Witness Printer took 67.64 ms. Allocated memory is still 1.8 GB. Free memory was 829.9 MB in the beginning and 823.9 MB in the end (delta: 6.0 MB). Peak memory consumption was 6.0 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 23 terminating modules (23 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.23 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 59615 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 12.6s and 24 iterations. TraceHistogramMax:1. Analysis of lassos took 4.0s. Construction of modules took 0.6s. Büchi inclusion checks took 1.4s. Highest rank in rank-based complementation 0. Minimization of det autom 23. Minimization of nondet autom 0. Automata minimization 2.8s AutomataMinimizationTime, 23 MinimizatonAttempts, 22242 StatesRemovedByMinimization, 12 NontrivialMinimizations. Non-live state removal took 2.3s Buchi closure took 0.1s. Biggest automaton had 59615 states and ocurred in iteration 23. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 16765 SDtfs, 17424 SDslu, 13961 SDs, 0 SdLazy, 479 SolverSat, 254 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.6s Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc5 concLT0 SILN1 SILU0 SILI13 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 471]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {__retres1=0, t3_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5fd06baf=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@28076b7b=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1de0b231=0, tmp=1, t5_i=1, __retres1=0, kernel_st=1, t2_st=0, t4_i=1, E_3=2, t4_pc=0, E_5=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@131aa4d6=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7dd91baf=0, \result=0, E_1=2, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, tmp_ndt_6=0, m_st=0, tmp___2=0, tmp___0=0, t3_pc=0, tmp=0, \result=0, __retres1=0, m_pc=0, tmp___4=0, \result=0, __retres1=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@11cf61bd=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, t5_st=0, __retres1=1, E_2=2, E_4=2, T1_E=2, tmp_ndt_1=0, M_E=2, tmp=0, tmp_ndt_3=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@73d5756b=0, __retres1=0, T5_E=2, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3d242056=0, T4_E=2, t3_i=1, t4_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@65026fb0=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@627172c1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@78865148=0, t1_st=0, tmp_ndt_5=0, t5_pc=0, t2_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@77e22aab=0, tmp___3=0, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4bb6fae3=0, t1_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1b3b219b=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2c615ac=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 471]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int t5_pc = 0; [L21] int m_st ; [L22] int t1_st ; [L23] int t2_st ; [L24] int t3_st ; [L25] int t4_st ; [L26] int t5_st ; [L27] int m_i ; [L28] int t1_i ; [L29] int t2_i ; [L30] int t3_i ; [L31] int t4_i ; [L32] int t5_i ; [L33] int M_E = 2; [L34] int T1_E = 2; [L35] int T2_E = 2; [L36] int T3_E = 2; [L37] int T4_E = 2; [L38] int T5_E = 2; [L39] int E_1 = 2; [L40] int E_2 = 2; [L41] int E_3 = 2; [L42] int E_4 = 2; [L43] int E_5 = 2; [L935] int __retres1 ; [L846] m_i = 1 [L847] t1_i = 1 [L848] t2_i = 1 [L849] t3_i = 1 [L850] t4_i = 1 [L851] t5_i = 1 [L876] int kernel_st ; [L877] int tmp ; [L878] int tmp___0 ; [L882] kernel_st = 0 [L391] COND TRUE m_i == 1 [L392] m_st = 0 [L396] COND TRUE t1_i == 1 [L397] t1_st = 0 [L401] COND TRUE t2_i == 1 [L402] t2_st = 0 [L406] COND TRUE t3_i == 1 [L407] t3_st = 0 [L411] COND TRUE t4_i == 1 [L412] t4_st = 0 [L416] COND TRUE t5_i == 1 [L417] t5_st = 0 [L576] COND FALSE !(M_E == 0) [L581] COND FALSE !(T1_E == 0) [L586] COND FALSE !(T2_E == 0) [L591] COND FALSE !(T3_E == 0) [L596] COND FALSE !(T4_E == 0) [L601] COND FALSE !(T5_E == 0) [L606] COND FALSE !(E_1 == 0) [L611] COND FALSE !(E_2 == 0) [L616] COND FALSE !(E_3 == 0) [L621] COND FALSE !(E_4 == 0) [L626] COND FALSE !(E_5 == 0) [L699] int tmp ; [L700] int tmp___0 ; [L701] int tmp___1 ; [L702] int tmp___2 ; [L703] int tmp___3 ; [L704] int tmp___4 ; [L266] int __retres1 ; [L269] COND FALSE !(m_pc == 1) [L279] __retres1 = 0 [L281] return (__retres1); [L708] tmp = is_master_triggered() [L710] COND FALSE !(\read(tmp)) [L285] int __retres1 ; [L288] COND FALSE !(t1_pc == 1) [L298] __retres1 = 0 [L300] return (__retres1); [L716] tmp___0 = is_transmit1_triggered() [L718] COND FALSE !(\read(tmp___0)) [L304] int __retres1 ; [L307] COND FALSE !(t2_pc == 1) [L317] __retres1 = 0 [L319] return (__retres1); [L724] tmp___1 = is_transmit2_triggered() [L726] COND FALSE !(\read(tmp___1)) [L323] int __retres1 ; [L326] COND FALSE !(t3_pc == 1) [L336] __retres1 = 0 [L338] return (__retres1); [L732] tmp___2 = is_transmit3_triggered() [L734] COND FALSE !(\read(tmp___2)) [L342] int __retres1 ; [L345] COND FALSE !(t4_pc == 1) [L355] __retres1 = 0 [L357] return (__retres1); [L740] tmp___3 = is_transmit4_triggered() [L742] COND FALSE !(\read(tmp___3)) [L361] int __retres1 ; [L364] COND FALSE !(t5_pc == 1) [L374] __retres1 = 0 [L376] return (__retres1); [L748] tmp___4 = is_transmit5_triggered() [L750] COND FALSE !(\read(tmp___4)) [L639] COND FALSE !(M_E == 1) [L644] COND FALSE !(T1_E == 1) [L649] COND FALSE !(T2_E == 1) [L654] COND FALSE !(T3_E == 1) [L659] COND FALSE !(T4_E == 1) [L664] COND FALSE !(T5_E == 1) [L669] COND FALSE !(E_1 == 1) [L674] COND FALSE !(E_2 == 1) [L679] COND FALSE !(E_3 == 1) [L684] COND FALSE !(E_4 == 1) [L689] COND FALSE !(E_5 == 1) [L890] COND TRUE 1 [L893] kernel_st = 1 [L467] int tmp ; Loop: [L471] COND TRUE 1 [L426] int __retres1 ; [L429] COND TRUE m_st == 0 [L430] __retres1 = 1 [L462] return (__retres1); [L474] tmp = exists_runnable_thread() [L476] COND TRUE \read(tmp) [L481] COND TRUE m_st == 0 [L482] int tmp_ndt_1; [L483] tmp_ndt_1 = __VERIFIER_nondet_int() [L484] COND FALSE !(\read(tmp_ndt_1)) [L495] COND TRUE t1_st == 0 [L496] int tmp_ndt_2; [L497] tmp_ndt_2 = __VERIFIER_nondet_int() [L498] COND FALSE !(\read(tmp_ndt_2)) [L509] COND TRUE t2_st == 0 [L510] int tmp_ndt_3; [L511] tmp_ndt_3 = __VERIFIER_nondet_int() [L512] COND FALSE !(\read(tmp_ndt_3)) [L523] COND TRUE t3_st == 0 [L524] int tmp_ndt_4; [L525] tmp_ndt_4 = __VERIFIER_nondet_int() [L526] COND FALSE !(\read(tmp_ndt_4)) [L537] COND TRUE t4_st == 0 [L538] int tmp_ndt_5; [L539] tmp_ndt_5 = __VERIFIER_nondet_int() [L540] COND FALSE !(\read(tmp_ndt_5)) [L551] COND TRUE t5_st == 0 [L552] int tmp_ndt_6; [L553] tmp_ndt_6 = __VERIFIER_nondet_int() [L554] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...