./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/systemc/kundu1.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 30f4e4ab Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx12G -Xms1G -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/systemc/kundu1.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 532163d21d7e473fbfa4a073427e9fd2a45c7337 ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.24-30f4e4a [2019-11-28 00:26:35,958 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-28 00:26:35,960 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-28 00:26:35,972 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-28 00:26:35,973 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-28 00:26:35,974 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-28 00:26:35,975 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-28 00:26:35,977 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-28 00:26:35,979 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-28 00:26:35,980 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-28 00:26:35,981 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-28 00:26:35,982 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-28 00:26:35,988 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-28 00:26:35,989 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-28 00:26:35,990 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-28 00:26:35,994 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-28 00:26:35,995 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-28 00:26:35,997 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-28 00:26:35,999 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-28 00:26:36,003 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-28 00:26:36,009 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-28 00:26:36,011 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-28 00:26:36,013 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-28 00:26:36,014 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-28 00:26:36,020 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-28 00:26:36,020 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-28 00:26:36,020 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-28 00:26:36,022 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-28 00:26:36,023 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-28 00:26:36,024 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-28 00:26:36,025 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-28 00:26:36,026 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-28 00:26:36,027 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-28 00:26:36,028 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-28 00:26:36,029 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-28 00:26:36,030 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-28 00:26:36,031 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-28 00:26:36,032 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-28 00:26:36,032 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-28 00:26:36,033 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-28 00:26:36,034 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-28 00:26:36,035 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-28 00:26:36,070 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-28 00:26:36,072 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-28 00:26:36,073 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-28 00:26:36,075 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-28 00:26:36,075 INFO L138 SettingsManager]: * Use SBE=true [2019-11-28 00:26:36,075 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-28 00:26:36,076 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-28 00:26:36,077 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-28 00:26:36,077 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-28 00:26:36,077 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-28 00:26:36,079 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-28 00:26:36,079 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-28 00:26:36,079 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-28 00:26:36,079 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-28 00:26:36,080 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-28 00:26:36,080 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-28 00:26:36,083 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-28 00:26:36,083 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-28 00:26:36,083 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-28 00:26:36,084 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-28 00:26:36,084 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-28 00:26:36,084 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 00:26:36,085 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-28 00:26:36,085 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-28 00:26:36,085 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-28 00:26:36,085 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-28 00:26:36,087 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-28 00:26:36,087 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-28 00:26:36,087 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 532163d21d7e473fbfa4a073427e9fd2a45c7337 [2019-11-28 00:26:36,432 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-28 00:26:36,445 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-28 00:26:36,448 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-28 00:26:36,449 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-28 00:26:36,450 INFO L275 PluginConnector]: CDTParser initialized [2019-11-28 00:26:36,451 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/kundu1.cil.c [2019-11-28 00:26:36,519 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4818e6a43/39d60d6be36e4066a37caaeb5b9b8dc8/FLAG6e255d448 [2019-11-28 00:26:36,963 INFO L306 CDTParser]: Found 1 translation units. [2019-11-28 00:26:36,964 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/kundu1.cil.c [2019-11-28 00:26:36,973 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4818e6a43/39d60d6be36e4066a37caaeb5b9b8dc8/FLAG6e255d448 [2019-11-28 00:26:37,390 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4818e6a43/39d60d6be36e4066a37caaeb5b9b8dc8 [2019-11-28 00:26:37,393 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-28 00:26:37,394 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-28 00:26:37,395 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-28 00:26:37,395 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-28 00:26:37,399 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-28 00:26:37,401 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 12:26:37" (1/1) ... [2019-11-28 00:26:37,403 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@427f16d6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:26:37, skipping insertion in model container [2019-11-28 00:26:37,403 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 12:26:37" (1/1) ... [2019-11-28 00:26:37,410 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-11-28 00:26:37,460 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-11-28 00:26:37,693 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 00:26:37,698 INFO L203 MainTranslator]: Completed pre-run [2019-11-28 00:26:37,793 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 00:26:37,813 INFO L208 MainTranslator]: Completed translation [2019-11-28 00:26:37,814 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:26:37 WrapperNode [2019-11-28 00:26:37,814 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-28 00:26:37,814 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-28 00:26:37,815 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-28 00:26:37,815 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-28 00:26:37,823 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:26:37" (1/1) ... [2019-11-28 00:26:37,830 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:26:37" (1/1) ... [2019-11-28 00:26:37,864 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-28 00:26:37,864 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-28 00:26:37,864 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-28 00:26:37,865 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-28 00:26:37,876 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:26:37" (1/1) ... [2019-11-28 00:26:37,877 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:26:37" (1/1) ... [2019-11-28 00:26:37,885 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:26:37" (1/1) ... [2019-11-28 00:26:37,887 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:26:37" (1/1) ... [2019-11-28 00:26:37,893 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:26:37" (1/1) ... [2019-11-28 00:26:37,901 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:26:37" (1/1) ... [2019-11-28 00:26:37,904 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:26:37" (1/1) ... [2019-11-28 00:26:37,907 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-28 00:26:37,908 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-28 00:26:37,908 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-28 00:26:37,908 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-28 00:26:37,909 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:26:37" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 00:26:37,974 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-28 00:26:37,975 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-28 00:26:38,487 INFO L292 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-28 00:26:38,488 INFO L297 CfgBuilder]: Removed 72 assume(true) statements. [2019-11-28 00:26:38,489 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 12:26:38 BoogieIcfgContainer [2019-11-28 00:26:38,489 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-28 00:26:38,490 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-28 00:26:38,490 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-28 00:26:38,493 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-28 00:26:38,493 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 12:26:37" (1/3) ... [2019-11-28 00:26:38,494 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7117b94a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 12:26:38, skipping insertion in model container [2019-11-28 00:26:38,494 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:26:37" (2/3) ... [2019-11-28 00:26:38,495 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7117b94a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 12:26:38, skipping insertion in model container [2019-11-28 00:26:38,495 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 12:26:38" (3/3) ... [2019-11-28 00:26:38,498 INFO L109 eAbstractionObserver]: Analyzing ICFG kundu1.cil.c [2019-11-28 00:26:38,507 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-28 00:26:38,517 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 3 error locations. [2019-11-28 00:26:38,529 INFO L249 AbstractCegarLoop]: Starting to check reachability of 3 error locations. [2019-11-28 00:26:38,551 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-28 00:26:38,551 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-28 00:26:38,551 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-28 00:26:38,552 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-28 00:26:38,552 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-28 00:26:38,552 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-28 00:26:38,552 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-28 00:26:38,552 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-28 00:26:38,569 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states. [2019-11-28 00:26:38,576 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-11-28 00:26:38,576 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:26:38,577 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:26:38,577 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:26:38,581 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:26:38,582 INFO L82 PathProgramCache]: Analyzing trace with hash 1913091172, now seen corresponding path program 1 times [2019-11-28 00:26:38,590 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:26:38,590 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [447269056] [2019-11-28 00:26:38,590 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:26:38,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:26:38,725 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:26:38,726 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [447269056] [2019-11-28 00:26:38,726 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:26:38,727 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:26:38,728 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [8552519] [2019-11-28 00:26:38,733 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:26:38,733 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:26:38,747 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:26:38,748 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:26:38,750 INFO L87 Difference]: Start difference. First operand 117 states. Second operand 3 states. [2019-11-28 00:26:38,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:26:38,799 INFO L93 Difference]: Finished difference Result 228 states and 346 transitions. [2019-11-28 00:26:38,799 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:26:38,801 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 33 [2019-11-28 00:26:38,801 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:26:38,813 INFO L225 Difference]: With dead ends: 228 [2019-11-28 00:26:38,813 INFO L226 Difference]: Without dead ends: 112 [2019-11-28 00:26:38,817 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:26:38,835 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2019-11-28 00:26:38,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 112. [2019-11-28 00:26:38,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112 states. [2019-11-28 00:26:38,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 162 transitions. [2019-11-28 00:26:38,867 INFO L78 Accepts]: Start accepts. Automaton has 112 states and 162 transitions. Word has length 33 [2019-11-28 00:26:38,867 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:26:38,867 INFO L462 AbstractCegarLoop]: Abstraction has 112 states and 162 transitions. [2019-11-28 00:26:38,868 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:26:38,868 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 162 transitions. [2019-11-28 00:26:38,869 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-11-28 00:26:38,869 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:26:38,869 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:26:38,870 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:26:38,870 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:26:38,870 INFO L82 PathProgramCache]: Analyzing trace with hash 526887778, now seen corresponding path program 1 times [2019-11-28 00:26:38,871 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:26:38,871 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1051820560] [2019-11-28 00:26:38,871 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:26:38,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:26:38,930 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:26:38,930 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1051820560] [2019-11-28 00:26:38,931 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:26:38,931 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:26:38,931 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1874018504] [2019-11-28 00:26:38,933 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:26:38,933 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:26:38,934 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:26:38,934 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:26:38,934 INFO L87 Difference]: Start difference. First operand 112 states and 162 transitions. Second operand 3 states. [2019-11-28 00:26:39,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:26:39,044 INFO L93 Difference]: Finished difference Result 305 states and 441 transitions. [2019-11-28 00:26:39,046 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:26:39,046 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 33 [2019-11-28 00:26:39,046 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:26:39,051 INFO L225 Difference]: With dead ends: 305 [2019-11-28 00:26:39,051 INFO L226 Difference]: Without dead ends: 200 [2019-11-28 00:26:39,053 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:26:39,054 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 200 states. [2019-11-28 00:26:39,097 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 200 to 190. [2019-11-28 00:26:39,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 190 states. [2019-11-28 00:26:39,102 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190 states to 190 states and 275 transitions. [2019-11-28 00:26:39,102 INFO L78 Accepts]: Start accepts. Automaton has 190 states and 275 transitions. Word has length 33 [2019-11-28 00:26:39,105 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:26:39,105 INFO L462 AbstractCegarLoop]: Abstraction has 190 states and 275 transitions. [2019-11-28 00:26:39,105 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:26:39,105 INFO L276 IsEmpty]: Start isEmpty. Operand 190 states and 275 transitions. [2019-11-28 00:26:39,106 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-11-28 00:26:39,107 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:26:39,107 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:26:39,110 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:26:39,110 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:26:39,111 INFO L82 PathProgramCache]: Analyzing trace with hash -1145629853, now seen corresponding path program 1 times [2019-11-28 00:26:39,111 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:26:39,111 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1182956248] [2019-11-28 00:26:39,112 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:26:39,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:26:39,189 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:26:39,189 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1182956248] [2019-11-28 00:26:39,189 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:26:39,190 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:26:39,190 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1419970478] [2019-11-28 00:26:39,190 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:26:39,191 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:26:39,191 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:26:39,192 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:26:39,192 INFO L87 Difference]: Start difference. First operand 190 states and 275 transitions. Second operand 3 states. [2019-11-28 00:26:39,284 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:26:39,284 INFO L93 Difference]: Finished difference Result 527 states and 762 transitions. [2019-11-28 00:26:39,284 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:26:39,285 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 33 [2019-11-28 00:26:39,285 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:26:39,289 INFO L225 Difference]: With dead ends: 527 [2019-11-28 00:26:39,290 INFO L226 Difference]: Without dead ends: 350 [2019-11-28 00:26:39,291 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:26:39,293 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 350 states. [2019-11-28 00:26:39,334 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 350 to 328. [2019-11-28 00:26:39,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 328 states. [2019-11-28 00:26:39,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 328 states to 328 states and 462 transitions. [2019-11-28 00:26:39,341 INFO L78 Accepts]: Start accepts. Automaton has 328 states and 462 transitions. Word has length 33 [2019-11-28 00:26:39,342 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:26:39,342 INFO L462 AbstractCegarLoop]: Abstraction has 328 states and 462 transitions. [2019-11-28 00:26:39,342 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:26:39,342 INFO L276 IsEmpty]: Start isEmpty. Operand 328 states and 462 transitions. [2019-11-28 00:26:39,343 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-11-28 00:26:39,345 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:26:39,346 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:26:39,346 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:26:39,347 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:26:39,347 INFO L82 PathProgramCache]: Analyzing trace with hash -1045714737, now seen corresponding path program 1 times [2019-11-28 00:26:39,348 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:26:39,348 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1536746704] [2019-11-28 00:26:39,348 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:26:39,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:26:39,500 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:26:39,500 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1536746704] [2019-11-28 00:26:39,500 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:26:39,501 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 00:26:39,501 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [334718406] [2019-11-28 00:26:39,501 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 00:26:39,502 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:26:39,502 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 00:26:39,502 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 00:26:39,502 INFO L87 Difference]: Start difference. First operand 328 states and 462 transitions. Second operand 5 states. [2019-11-28 00:26:39,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:26:39,642 INFO L93 Difference]: Finished difference Result 1045 states and 1489 transitions. [2019-11-28 00:26:39,643 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 00:26:39,643 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 34 [2019-11-28 00:26:39,643 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:26:39,647 INFO L225 Difference]: With dead ends: 1045 [2019-11-28 00:26:39,648 INFO L226 Difference]: Without dead ends: 728 [2019-11-28 00:26:39,649 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-28 00:26:39,651 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 728 states. [2019-11-28 00:26:39,685 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 728 to 340. [2019-11-28 00:26:39,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 340 states. [2019-11-28 00:26:39,687 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 340 states to 340 states and 469 transitions. [2019-11-28 00:26:39,688 INFO L78 Accepts]: Start accepts. Automaton has 340 states and 469 transitions. Word has length 34 [2019-11-28 00:26:39,688 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:26:39,688 INFO L462 AbstractCegarLoop]: Abstraction has 340 states and 469 transitions. [2019-11-28 00:26:39,688 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 00:26:39,688 INFO L276 IsEmpty]: Start isEmpty. Operand 340 states and 469 transitions. [2019-11-28 00:26:39,689 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-11-28 00:26:39,690 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:26:39,690 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:26:39,690 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:26:39,690 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:26:39,691 INFO L82 PathProgramCache]: Analyzing trace with hash -1179728243, now seen corresponding path program 1 times [2019-11-28 00:26:39,691 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:26:39,691 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1661267164] [2019-11-28 00:26:39,691 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:26:39,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:26:39,770 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:26:39,770 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1661267164] [2019-11-28 00:26:39,771 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:26:39,771 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 00:26:39,771 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [333819541] [2019-11-28 00:26:39,772 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 00:26:39,772 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:26:39,772 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 00:26:39,772 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 00:26:39,773 INFO L87 Difference]: Start difference. First operand 340 states and 469 transitions. Second operand 5 states. [2019-11-28 00:26:39,919 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:26:39,919 INFO L93 Difference]: Finished difference Result 1046 states and 1465 transitions. [2019-11-28 00:26:39,920 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 00:26:39,920 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 34 [2019-11-28 00:26:39,920 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:26:39,924 INFO L225 Difference]: With dead ends: 1046 [2019-11-28 00:26:39,924 INFO L226 Difference]: Without dead ends: 724 [2019-11-28 00:26:39,925 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-28 00:26:39,927 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 724 states. [2019-11-28 00:26:39,963 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 724 to 352. [2019-11-28 00:26:39,964 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 352 states. [2019-11-28 00:26:39,965 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 352 states to 352 states and 476 transitions. [2019-11-28 00:26:39,965 INFO L78 Accepts]: Start accepts. Automaton has 352 states and 476 transitions. Word has length 34 [2019-11-28 00:26:39,966 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:26:39,966 INFO L462 AbstractCegarLoop]: Abstraction has 352 states and 476 transitions. [2019-11-28 00:26:39,966 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 00:26:39,966 INFO L276 IsEmpty]: Start isEmpty. Operand 352 states and 476 transitions. [2019-11-28 00:26:39,967 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-11-28 00:26:39,967 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:26:39,968 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:26:39,968 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:26:39,968 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:26:39,968 INFO L82 PathProgramCache]: Analyzing trace with hash 1526891151, now seen corresponding path program 1 times [2019-11-28 00:26:39,969 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:26:39,969 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1830008254] [2019-11-28 00:26:39,969 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:26:39,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:26:40,047 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:26:40,047 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1830008254] [2019-11-28 00:26:40,048 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:26:40,049 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 00:26:40,049 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1707565574] [2019-11-28 00:26:40,049 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 00:26:40,050 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:26:40,050 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 00:26:40,050 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 00:26:40,050 INFO L87 Difference]: Start difference. First operand 352 states and 476 transitions. Second operand 4 states. [2019-11-28 00:26:40,252 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:26:40,252 INFO L93 Difference]: Finished difference Result 1638 states and 2239 transitions. [2019-11-28 00:26:40,253 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 00:26:40,253 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 34 [2019-11-28 00:26:40,254 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:26:40,262 INFO L225 Difference]: With dead ends: 1638 [2019-11-28 00:26:40,262 INFO L226 Difference]: Without dead ends: 1304 [2019-11-28 00:26:40,264 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 00:26:40,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1304 states. [2019-11-28 00:26:40,335 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1304 to 662. [2019-11-28 00:26:40,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 662 states. [2019-11-28 00:26:40,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 662 states to 662 states and 900 transitions. [2019-11-28 00:26:40,338 INFO L78 Accepts]: Start accepts. Automaton has 662 states and 900 transitions. Word has length 34 [2019-11-28 00:26:40,340 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:26:40,341 INFO L462 AbstractCegarLoop]: Abstraction has 662 states and 900 transitions. [2019-11-28 00:26:40,341 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 00:26:40,341 INFO L276 IsEmpty]: Start isEmpty. Operand 662 states and 900 transitions. [2019-11-28 00:26:40,343 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2019-11-28 00:26:40,343 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:26:40,343 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:26:40,344 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:26:40,344 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:26:40,348 INFO L82 PathProgramCache]: Analyzing trace with hash -1026068075, now seen corresponding path program 1 times [2019-11-28 00:26:40,348 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:26:40,349 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [372144238] [2019-11-28 00:26:40,349 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:26:40,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:26:40,425 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:26:40,426 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [372144238] [2019-11-28 00:26:40,426 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:26:40,426 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 00:26:40,426 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2042560992] [2019-11-28 00:26:40,427 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 00:26:40,428 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:26:40,428 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 00:26:40,428 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-28 00:26:40,428 INFO L87 Difference]: Start difference. First operand 662 states and 900 transitions. Second operand 4 states. [2019-11-28 00:26:40,567 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:26:40,567 INFO L93 Difference]: Finished difference Result 1626 states and 2222 transitions. [2019-11-28 00:26:40,568 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-28 00:26:40,568 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 41 [2019-11-28 00:26:40,569 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:26:40,574 INFO L225 Difference]: With dead ends: 1626 [2019-11-28 00:26:40,574 INFO L226 Difference]: Without dead ends: 982 [2019-11-28 00:26:40,580 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-28 00:26:40,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 982 states. [2019-11-28 00:26:40,707 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 982 to 972. [2019-11-28 00:26:40,707 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 972 states. [2019-11-28 00:26:40,711 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 972 states to 972 states and 1324 transitions. [2019-11-28 00:26:40,711 INFO L78 Accepts]: Start accepts. Automaton has 972 states and 1324 transitions. Word has length 41 [2019-11-28 00:26:40,711 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:26:40,711 INFO L462 AbstractCegarLoop]: Abstraction has 972 states and 1324 transitions. [2019-11-28 00:26:40,712 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 00:26:40,712 INFO L276 IsEmpty]: Start isEmpty. Operand 972 states and 1324 transitions. [2019-11-28 00:26:40,713 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2019-11-28 00:26:40,713 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:26:40,713 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:26:40,714 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:26:40,714 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:26:40,714 INFO L82 PathProgramCache]: Analyzing trace with hash -305826283, now seen corresponding path program 1 times [2019-11-28 00:26:40,715 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:26:40,715 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [242967032] [2019-11-28 00:26:40,715 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:26:40,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:26:40,768 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:26:40,768 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [242967032] [2019-11-28 00:26:40,768 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:26:40,768 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-28 00:26:40,769 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [238918252] [2019-11-28 00:26:40,769 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-28 00:26:40,769 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:26:40,769 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-28 00:26:40,770 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2019-11-28 00:26:40,770 INFO L87 Difference]: Start difference. First operand 972 states and 1324 transitions. Second operand 6 states. [2019-11-28 00:26:41,153 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:26:41,153 INFO L93 Difference]: Finished difference Result 3850 states and 5260 transitions. [2019-11-28 00:26:41,153 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-11-28 00:26:41,153 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 44 [2019-11-28 00:26:41,154 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:26:41,168 INFO L225 Difference]: With dead ends: 3850 [2019-11-28 00:26:41,168 INFO L226 Difference]: Without dead ends: 2896 [2019-11-28 00:26:41,171 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2019-11-28 00:26:41,174 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2896 states. [2019-11-28 00:26:41,321 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2896 to 1606. [2019-11-28 00:26:41,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1606 states. [2019-11-28 00:26:41,327 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1606 states to 1606 states and 2192 transitions. [2019-11-28 00:26:41,327 INFO L78 Accepts]: Start accepts. Automaton has 1606 states and 2192 transitions. Word has length 44 [2019-11-28 00:26:41,328 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:26:41,328 INFO L462 AbstractCegarLoop]: Abstraction has 1606 states and 2192 transitions. [2019-11-28 00:26:41,328 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-28 00:26:41,328 INFO L276 IsEmpty]: Start isEmpty. Operand 1606 states and 2192 transitions. [2019-11-28 00:26:41,329 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2019-11-28 00:26:41,329 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:26:41,329 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:26:41,330 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:26:41,330 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:26:41,330 INFO L82 PathProgramCache]: Analyzing trace with hash -1702134670, now seen corresponding path program 1 times [2019-11-28 00:26:41,330 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:26:41,330 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2117778230] [2019-11-28 00:26:41,331 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:26:41,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:26:41,353 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2019-11-28 00:26:41,353 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2117778230] [2019-11-28 00:26:41,353 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:26:41,353 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:26:41,354 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1579365723] [2019-11-28 00:26:41,354 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:26:41,354 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:26:41,354 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:26:41,355 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:26:41,355 INFO L87 Difference]: Start difference. First operand 1606 states and 2192 transitions. Second operand 3 states. [2019-11-28 00:26:41,622 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:26:41,623 INFO L93 Difference]: Finished difference Result 4614 states and 6233 transitions. [2019-11-28 00:26:41,623 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:26:41,623 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 46 [2019-11-28 00:26:41,624 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:26:41,644 INFO L225 Difference]: With dead ends: 4614 [2019-11-28 00:26:41,644 INFO L226 Difference]: Without dead ends: 3026 [2019-11-28 00:26:41,649 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:26:41,653 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3026 states. [2019-11-28 00:26:42,100 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3026 to 3022. [2019-11-28 00:26:42,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3022 states. [2019-11-28 00:26:42,111 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3022 states to 3022 states and 3978 transitions. [2019-11-28 00:26:42,112 INFO L78 Accepts]: Start accepts. Automaton has 3022 states and 3978 transitions. Word has length 46 [2019-11-28 00:26:42,112 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:26:42,112 INFO L462 AbstractCegarLoop]: Abstraction has 3022 states and 3978 transitions. [2019-11-28 00:26:42,112 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:26:42,112 INFO L276 IsEmpty]: Start isEmpty. Operand 3022 states and 3978 transitions. [2019-11-28 00:26:42,113 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2019-11-28 00:26:42,113 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:26:42,114 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:26:42,114 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:26:42,115 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:26:42,115 INFO L82 PathProgramCache]: Analyzing trace with hash 1664931104, now seen corresponding path program 1 times [2019-11-28 00:26:42,115 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:26:42,115 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1539762993] [2019-11-28 00:26:42,116 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:26:42,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:26:42,167 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:26:42,167 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1539762993] [2019-11-28 00:26:42,167 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:26:42,167 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:26:42,168 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [945547812] [2019-11-28 00:26:42,168 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:26:42,168 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:26:42,169 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:26:42,169 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:26:42,169 INFO L87 Difference]: Start difference. First operand 3022 states and 3978 transitions. Second operand 3 states. [2019-11-28 00:26:42,553 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:26:42,555 INFO L93 Difference]: Finished difference Result 8013 states and 10530 transitions. [2019-11-28 00:26:42,556 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:26:42,556 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2019-11-28 00:26:42,556 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:26:42,580 INFO L225 Difference]: With dead ends: 8013 [2019-11-28 00:26:42,581 INFO L226 Difference]: Without dead ends: 5023 [2019-11-28 00:26:42,586 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:26:42,592 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5023 states. [2019-11-28 00:26:42,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5023 to 4273. [2019-11-28 00:26:42,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4273 states. [2019-11-28 00:26:42,906 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4273 states to 4273 states and 5593 transitions. [2019-11-28 00:26:42,906 INFO L78 Accepts]: Start accepts. Automaton has 4273 states and 5593 transitions. Word has length 48 [2019-11-28 00:26:42,906 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:26:42,909 INFO L462 AbstractCegarLoop]: Abstraction has 4273 states and 5593 transitions. [2019-11-28 00:26:42,909 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:26:42,909 INFO L276 IsEmpty]: Start isEmpty. Operand 4273 states and 5593 transitions. [2019-11-28 00:26:42,911 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2019-11-28 00:26:42,911 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:26:42,912 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:26:42,912 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:26:42,912 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:26:42,912 INFO L82 PathProgramCache]: Analyzing trace with hash 403090641, now seen corresponding path program 1 times [2019-11-28 00:26:42,913 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:26:42,913 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1603007288] [2019-11-28 00:26:42,913 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:26:42,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:26:42,964 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:26:42,964 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1603007288] [2019-11-28 00:26:42,965 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:26:42,965 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:26:42,965 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2060456443] [2019-11-28 00:26:42,965 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:26:42,966 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:26:42,966 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:26:42,966 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:26:42,966 INFO L87 Difference]: Start difference. First operand 4273 states and 5593 transitions. Second operand 3 states. [2019-11-28 00:26:43,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:26:43,349 INFO L93 Difference]: Finished difference Result 8516 states and 11154 transitions. [2019-11-28 00:26:43,350 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:26:43,351 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2019-11-28 00:26:43,351 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:26:43,376 INFO L225 Difference]: With dead ends: 8516 [2019-11-28 00:26:43,376 INFO L226 Difference]: Without dead ends: 4275 [2019-11-28 00:26:43,383 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:26:43,391 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4275 states. [2019-11-28 00:26:43,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4275 to 4273. [2019-11-28 00:26:43,757 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4273 states. [2019-11-28 00:26:43,770 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4273 states to 4273 states and 5518 transitions. [2019-11-28 00:26:43,771 INFO L78 Accepts]: Start accepts. Automaton has 4273 states and 5518 transitions. Word has length 48 [2019-11-28 00:26:43,771 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:26:43,771 INFO L462 AbstractCegarLoop]: Abstraction has 4273 states and 5518 transitions. [2019-11-28 00:26:43,771 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:26:43,772 INFO L276 IsEmpty]: Start isEmpty. Operand 4273 states and 5518 transitions. [2019-11-28 00:26:43,773 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-11-28 00:26:43,773 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:26:43,773 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:26:43,773 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:26:43,774 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:26:43,774 INFO L82 PathProgramCache]: Analyzing trace with hash 57108908, now seen corresponding path program 1 times [2019-11-28 00:26:43,774 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:26:43,775 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2043382477] [2019-11-28 00:26:43,775 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:26:43,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:26:43,801 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:26:43,801 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2043382477] [2019-11-28 00:26:43,802 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:26:43,802 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:26:43,802 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1012111696] [2019-11-28 00:26:43,802 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:26:43,803 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:26:43,803 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:26:43,803 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:26:43,804 INFO L87 Difference]: Start difference. First operand 4273 states and 5518 transitions. Second operand 3 states. [2019-11-28 00:26:44,093 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:26:44,093 INFO L93 Difference]: Finished difference Result 7967 states and 10312 transitions. [2019-11-28 00:26:44,094 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:26:44,094 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 49 [2019-11-28 00:26:44,094 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:26:44,114 INFO L225 Difference]: With dead ends: 7967 [2019-11-28 00:26:44,115 INFO L226 Difference]: Without dead ends: 3610 [2019-11-28 00:26:44,123 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:26:44,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3610 states. [2019-11-28 00:26:44,476 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3610 to 3465. [2019-11-28 00:26:44,476 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3465 states. [2019-11-28 00:26:44,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3465 states to 3465 states and 4400 transitions. [2019-11-28 00:26:44,487 INFO L78 Accepts]: Start accepts. Automaton has 3465 states and 4400 transitions. Word has length 49 [2019-11-28 00:26:44,488 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:26:44,488 INFO L462 AbstractCegarLoop]: Abstraction has 3465 states and 4400 transitions. [2019-11-28 00:26:44,488 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:26:44,488 INFO L276 IsEmpty]: Start isEmpty. Operand 3465 states and 4400 transitions. [2019-11-28 00:26:44,491 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2019-11-28 00:26:44,491 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:26:44,492 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:26:44,492 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:26:44,492 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:26:44,492 INFO L82 PathProgramCache]: Analyzing trace with hash 652914839, now seen corresponding path program 1 times [2019-11-28 00:26:44,493 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:26:44,493 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1903035171] [2019-11-28 00:26:44,493 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:26:44,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:26:44,528 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 19 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-11-28 00:26:44,528 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1903035171] [2019-11-28 00:26:44,529 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:26:44,529 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 00:26:44,529 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [143494098] [2019-11-28 00:26:44,530 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:26:44,530 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:26:44,530 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:26:44,530 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:26:44,531 INFO L87 Difference]: Start difference. First operand 3465 states and 4400 transitions. Second operand 3 states. [2019-11-28 00:26:44,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:26:44,763 INFO L93 Difference]: Finished difference Result 6369 states and 8143 transitions. [2019-11-28 00:26:44,763 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:26:44,763 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 83 [2019-11-28 00:26:44,764 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:26:44,779 INFO L225 Difference]: With dead ends: 6369 [2019-11-28 00:26:44,780 INFO L226 Difference]: Without dead ends: 3465 [2019-11-28 00:26:44,785 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:26:44,790 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3465 states. [2019-11-28 00:26:45,115 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3465 to 3465. [2019-11-28 00:26:45,116 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3465 states. [2019-11-28 00:26:45,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3465 states to 3465 states and 4336 transitions. [2019-11-28 00:26:45,130 INFO L78 Accepts]: Start accepts. Automaton has 3465 states and 4336 transitions. Word has length 83 [2019-11-28 00:26:45,131 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:26:45,131 INFO L462 AbstractCegarLoop]: Abstraction has 3465 states and 4336 transitions. [2019-11-28 00:26:45,131 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:26:45,132 INFO L276 IsEmpty]: Start isEmpty. Operand 3465 states and 4336 transitions. [2019-11-28 00:26:45,135 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2019-11-28 00:26:45,136 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:26:45,136 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:26:45,136 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:26:45,136 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:26:45,137 INFO L82 PathProgramCache]: Analyzing trace with hash -608848062, now seen corresponding path program 1 times [2019-11-28 00:26:45,137 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:26:45,137 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [831707799] [2019-11-28 00:26:45,137 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:26:45,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:26:45,181 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 25 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:26:45,182 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [831707799] [2019-11-28 00:26:45,182 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:26:45,182 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:26:45,183 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [808744893] [2019-11-28 00:26:45,183 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:26:45,183 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:26:45,184 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:26:45,184 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:26:45,184 INFO L87 Difference]: Start difference. First operand 3465 states and 4336 transitions. Second operand 3 states. [2019-11-28 00:26:45,561 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:26:45,562 INFO L93 Difference]: Finished difference Result 7371 states and 9260 transitions. [2019-11-28 00:26:45,562 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:26:45,562 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 84 [2019-11-28 00:26:45,562 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:26:45,587 INFO L225 Difference]: With dead ends: 7371 [2019-11-28 00:26:45,587 INFO L226 Difference]: Without dead ends: 4154 [2019-11-28 00:26:45,594 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:26:45,599 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4154 states. [2019-11-28 00:26:46,124 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4154 to 3700. [2019-11-28 00:26:46,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3700 states. [2019-11-28 00:26:46,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3700 states to 3700 states and 4553 transitions. [2019-11-28 00:26:46,136 INFO L78 Accepts]: Start accepts. Automaton has 3700 states and 4553 transitions. Word has length 84 [2019-11-28 00:26:46,137 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:26:46,137 INFO L462 AbstractCegarLoop]: Abstraction has 3700 states and 4553 transitions. [2019-11-28 00:26:46,137 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:26:46,137 INFO L276 IsEmpty]: Start isEmpty. Operand 3700 states and 4553 transitions. [2019-11-28 00:26:46,140 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2019-11-28 00:26:46,140 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:26:46,141 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:26:46,141 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:26:46,141 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:26:46,141 INFO L82 PathProgramCache]: Analyzing trace with hash 885528412, now seen corresponding path program 1 times [2019-11-28 00:26:46,142 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:26:46,143 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1535870710] [2019-11-28 00:26:46,143 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:26:46,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:26:46,199 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-11-28 00:26:46,200 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1535870710] [2019-11-28 00:26:46,200 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:26:46,201 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 00:26:46,201 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1269699227] [2019-11-28 00:26:46,201 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:26:46,202 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:26:46,202 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:26:46,202 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:26:46,203 INFO L87 Difference]: Start difference. First operand 3700 states and 4553 transitions. Second operand 3 states. [2019-11-28 00:26:46,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:26:46,527 INFO L93 Difference]: Finished difference Result 7674 states and 9427 transitions. [2019-11-28 00:26:46,528 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:26:46,528 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 86 [2019-11-28 00:26:46,528 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:26:46,538 INFO L225 Difference]: With dead ends: 7674 [2019-11-28 00:26:46,538 INFO L226 Difference]: Without dead ends: 4176 [2019-11-28 00:26:46,545 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:26:46,551 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4176 states. [2019-11-28 00:26:46,820 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4176 to 4174. [2019-11-28 00:26:46,821 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4174 states. [2019-11-28 00:26:46,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4174 states to 4174 states and 5092 transitions. [2019-11-28 00:26:46,829 INFO L78 Accepts]: Start accepts. Automaton has 4174 states and 5092 transitions. Word has length 86 [2019-11-28 00:26:46,830 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:26:46,830 INFO L462 AbstractCegarLoop]: Abstraction has 4174 states and 5092 transitions. [2019-11-28 00:26:46,830 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:26:46,830 INFO L276 IsEmpty]: Start isEmpty. Operand 4174 states and 5092 transitions. [2019-11-28 00:26:46,833 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2019-11-28 00:26:46,833 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:26:46,833 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:26:46,833 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:26:46,834 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:26:46,834 INFO L82 PathProgramCache]: Analyzing trace with hash 1836340184, now seen corresponding path program 1 times [2019-11-28 00:26:46,834 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:26:46,835 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [253484737] [2019-11-28 00:26:46,835 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:26:46,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:26:46,871 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 27 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:26:46,872 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [253484737] [2019-11-28 00:26:46,872 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:26:46,872 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:26:46,873 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1097168494] [2019-11-28 00:26:46,873 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:26:46,874 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:26:46,874 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:26:46,874 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:26:46,874 INFO L87 Difference]: Start difference. First operand 4174 states and 5092 transitions. Second operand 3 states. [2019-11-28 00:26:47,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:26:47,175 INFO L93 Difference]: Finished difference Result 7056 states and 8680 transitions. [2019-11-28 00:26:47,175 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:26:47,175 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 98 [2019-11-28 00:26:47,176 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:26:47,183 INFO L225 Difference]: With dead ends: 7056 [2019-11-28 00:26:47,183 INFO L226 Difference]: Without dead ends: 3227 [2019-11-28 00:26:47,191 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:26:47,197 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3227 states. [2019-11-28 00:26:47,569 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3227 to 3223. [2019-11-28 00:26:47,570 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3223 states. [2019-11-28 00:26:47,575 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3223 states to 3223 states and 3862 transitions. [2019-11-28 00:26:47,576 INFO L78 Accepts]: Start accepts. Automaton has 3223 states and 3862 transitions. Word has length 98 [2019-11-28 00:26:47,576 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:26:47,576 INFO L462 AbstractCegarLoop]: Abstraction has 3223 states and 3862 transitions. [2019-11-28 00:26:47,576 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:26:47,576 INFO L276 IsEmpty]: Start isEmpty. Operand 3223 states and 3862 transitions. [2019-11-28 00:26:47,579 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2019-11-28 00:26:47,579 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:26:47,579 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:26:47,580 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:26:47,580 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:26:47,580 INFO L82 PathProgramCache]: Analyzing trace with hash 1328739563, now seen corresponding path program 1 times [2019-11-28 00:26:47,580 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:26:47,581 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [546010140] [2019-11-28 00:26:47,581 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:26:47,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:26:47,621 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-11-28 00:26:47,622 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [546010140] [2019-11-28 00:26:47,622 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:26:47,623 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 00:26:47,623 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1279517905] [2019-11-28 00:26:47,623 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:26:47,624 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:26:47,624 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:26:47,624 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:26:47,624 INFO L87 Difference]: Start difference. First operand 3223 states and 3862 transitions. Second operand 3 states. [2019-11-28 00:26:47,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:26:47,832 INFO L93 Difference]: Finished difference Result 5622 states and 6780 transitions. [2019-11-28 00:26:47,832 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:26:47,833 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 99 [2019-11-28 00:26:47,833 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:26:47,839 INFO L225 Difference]: With dead ends: 5622 [2019-11-28 00:26:47,839 INFO L226 Difference]: Without dead ends: 3075 [2019-11-28 00:26:47,843 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:26:47,847 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3075 states. [2019-11-28 00:26:48,064 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3075 to 3075. [2019-11-28 00:26:48,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3075 states. [2019-11-28 00:26:48,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3075 states to 3075 states and 3691 transitions. [2019-11-28 00:26:48,070 INFO L78 Accepts]: Start accepts. Automaton has 3075 states and 3691 transitions. Word has length 99 [2019-11-28 00:26:48,070 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:26:48,071 INFO L462 AbstractCegarLoop]: Abstraction has 3075 states and 3691 transitions. [2019-11-28 00:26:48,071 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:26:48,071 INFO L276 IsEmpty]: Start isEmpty. Operand 3075 states and 3691 transitions. [2019-11-28 00:26:48,073 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2019-11-28 00:26:48,074 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:26:48,074 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:26:48,074 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:26:48,075 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:26:48,075 INFO L82 PathProgramCache]: Analyzing trace with hash -472369520, now seen corresponding path program 1 times [2019-11-28 00:26:48,075 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:26:48,075 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1630312652] [2019-11-28 00:26:48,076 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:26:48,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:26:48,160 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 23 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2019-11-28 00:26:48,161 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1630312652] [2019-11-28 00:26:48,161 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:26:48,161 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-11-28 00:26:48,162 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1382790018] [2019-11-28 00:26:48,162 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-11-28 00:26:48,162 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:26:48,163 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-11-28 00:26:48,163 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2019-11-28 00:26:48,163 INFO L87 Difference]: Start difference. First operand 3075 states and 3691 transitions. Second operand 8 states. [2019-11-28 00:26:48,443 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:26:48,443 INFO L93 Difference]: Finished difference Result 5286 states and 6380 transitions. [2019-11-28 00:26:48,443 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-11-28 00:26:48,444 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 104 [2019-11-28 00:26:48,444 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:26:48,448 INFO L225 Difference]: With dead ends: 5286 [2019-11-28 00:26:48,448 INFO L226 Difference]: Without dead ends: 2229 [2019-11-28 00:26:48,453 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=80, Unknown=0, NotChecked=0, Total=110 [2019-11-28 00:26:48,456 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2229 states. [2019-11-28 00:26:48,601 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2229 to 1920. [2019-11-28 00:26:48,601 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1920 states. [2019-11-28 00:26:48,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1920 states to 1920 states and 2325 transitions. [2019-11-28 00:26:48,605 INFO L78 Accepts]: Start accepts. Automaton has 1920 states and 2325 transitions. Word has length 104 [2019-11-28 00:26:48,605 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:26:48,606 INFO L462 AbstractCegarLoop]: Abstraction has 1920 states and 2325 transitions. [2019-11-28 00:26:48,606 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-11-28 00:26:48,606 INFO L276 IsEmpty]: Start isEmpty. Operand 1920 states and 2325 transitions. [2019-11-28 00:26:48,607 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2019-11-28 00:26:48,608 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:26:48,608 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:26:48,608 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:26:48,608 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:26:48,609 INFO L82 PathProgramCache]: Analyzing trace with hash 663738500, now seen corresponding path program 1 times [2019-11-28 00:26:48,609 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:26:48,609 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1879379894] [2019-11-28 00:26:48,609 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:26:48,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:26:48,667 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-11-28 00:26:48,668 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1879379894] [2019-11-28 00:26:48,668 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:26:48,668 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 00:26:48,668 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1871017151] [2019-11-28 00:26:48,669 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 00:26:48,669 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:26:48,669 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 00:26:48,669 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-28 00:26:48,670 INFO L87 Difference]: Start difference. First operand 1920 states and 2325 transitions. Second operand 4 states. [2019-11-28 00:26:48,896 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:26:48,896 INFO L93 Difference]: Finished difference Result 4180 states and 5082 transitions. [2019-11-28 00:26:48,897 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-28 00:26:48,897 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 107 [2019-11-28 00:26:48,897 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:26:48,902 INFO L225 Difference]: With dead ends: 4180 [2019-11-28 00:26:48,903 INFO L226 Difference]: Without dead ends: 2423 [2019-11-28 00:26:48,906 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-28 00:26:48,909 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2423 states. [2019-11-28 00:26:49,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2423 to 2324. [2019-11-28 00:26:49,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2324 states. [2019-11-28 00:26:49,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2324 states to 2324 states and 2802 transitions. [2019-11-28 00:26:49,158 INFO L78 Accepts]: Start accepts. Automaton has 2324 states and 2802 transitions. Word has length 107 [2019-11-28 00:26:49,158 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:26:49,158 INFO L462 AbstractCegarLoop]: Abstraction has 2324 states and 2802 transitions. [2019-11-28 00:26:49,158 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 00:26:49,158 INFO L276 IsEmpty]: Start isEmpty. Operand 2324 states and 2802 transitions. [2019-11-28 00:26:49,160 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2019-11-28 00:26:49,160 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:26:49,161 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:26:49,161 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:26:49,161 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:26:49,161 INFO L82 PathProgramCache]: Analyzing trace with hash -1105184803, now seen corresponding path program 1 times [2019-11-28 00:26:49,162 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:26:49,162 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2079159372] [2019-11-28 00:26:49,162 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:26:49,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:26:49,209 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:26:49,209 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2079159372] [2019-11-28 00:26:49,209 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:26:49,209 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:26:49,210 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1783922935] [2019-11-28 00:26:49,210 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:26:49,211 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:26:49,211 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:26:49,211 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:26:49,211 INFO L87 Difference]: Start difference. First operand 2324 states and 2802 transitions. Second operand 3 states. [2019-11-28 00:26:49,406 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:26:49,406 INFO L93 Difference]: Finished difference Result 3902 states and 4743 transitions. [2019-11-28 00:26:49,406 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:26:49,407 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 113 [2019-11-28 00:26:49,407 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:26:49,414 INFO L225 Difference]: With dead ends: 3902 [2019-11-28 00:26:49,415 INFO L226 Difference]: Without dead ends: 1655 [2019-11-28 00:26:49,418 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:26:49,420 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1655 states. [2019-11-28 00:26:49,714 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1655 to 1653. [2019-11-28 00:26:49,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1653 states. [2019-11-28 00:26:49,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1653 states to 1653 states and 1933 transitions. [2019-11-28 00:26:49,718 INFO L78 Accepts]: Start accepts. Automaton has 1653 states and 1933 transitions. Word has length 113 [2019-11-28 00:26:49,718 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:26:49,719 INFO L462 AbstractCegarLoop]: Abstraction has 1653 states and 1933 transitions. [2019-11-28 00:26:49,719 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:26:49,719 INFO L276 IsEmpty]: Start isEmpty. Operand 1653 states and 1933 transitions. [2019-11-28 00:26:49,721 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2019-11-28 00:26:49,721 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:26:49,721 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:26:49,721 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:26:49,722 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:26:49,722 INFO L82 PathProgramCache]: Analyzing trace with hash 1508765653, now seen corresponding path program 1 times [2019-11-28 00:26:49,722 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:26:49,723 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1843811502] [2019-11-28 00:26:49,723 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:26:49,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:26:49,795 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-11-28 00:26:49,796 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1843811502] [2019-11-28 00:26:49,796 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:26:49,796 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 00:26:49,796 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2055923886] [2019-11-28 00:26:49,797 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 00:26:49,797 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:26:49,797 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 00:26:49,797 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 00:26:49,797 INFO L87 Difference]: Start difference. First operand 1653 states and 1933 transitions. Second operand 5 states. [2019-11-28 00:26:50,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:26:50,113 INFO L93 Difference]: Finished difference Result 4188 states and 4920 transitions. [2019-11-28 00:26:50,114 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-11-28 00:26:50,114 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 114 [2019-11-28 00:26:50,114 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:26:50,119 INFO L225 Difference]: With dead ends: 4188 [2019-11-28 00:26:50,120 INFO L226 Difference]: Without dead ends: 2940 [2019-11-28 00:26:50,122 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-11-28 00:26:50,125 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2940 states. [2019-11-28 00:26:50,278 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2940 to 1905. [2019-11-28 00:26:50,279 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1905 states. [2019-11-28 00:26:50,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1905 states to 1905 states and 2228 transitions. [2019-11-28 00:26:50,281 INFO L78 Accepts]: Start accepts. Automaton has 1905 states and 2228 transitions. Word has length 114 [2019-11-28 00:26:50,281 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:26:50,282 INFO L462 AbstractCegarLoop]: Abstraction has 1905 states and 2228 transitions. [2019-11-28 00:26:50,282 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 00:26:50,282 INFO L276 IsEmpty]: Start isEmpty. Operand 1905 states and 2228 transitions. [2019-11-28 00:26:50,283 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2019-11-28 00:26:50,283 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:26:50,284 INFO L410 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:26:50,284 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:26:50,284 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:26:50,284 INFO L82 PathProgramCache]: Analyzing trace with hash -1919382230, now seen corresponding path program 1 times [2019-11-28 00:26:50,285 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:26:50,285 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1730431204] [2019-11-28 00:26:50,285 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:26:50,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:26:50,401 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 0 proven. 35 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-11-28 00:26:50,402 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1730431204] [2019-11-28 00:26:50,402 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [752438389] [2019-11-28 00:26:50,403 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-28 00:26:50,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:26:50,500 INFO L255 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 9 conjunts are in the unsatisfiable core [2019-11-28 00:26:50,510 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-28 00:26:50,541 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 0 proven. 35 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-11-28 00:26:50,541 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-28 00:26:50,542 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 5 [2019-11-28 00:26:50,542 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1647152836] [2019-11-28 00:26:50,543 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 00:26:50,543 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:26:50,543 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 00:26:50,544 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 00:26:50,544 INFO L87 Difference]: Start difference. First operand 1905 states and 2228 transitions. Second operand 5 states. [2019-11-28 00:26:50,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:26:50,880 INFO L93 Difference]: Finished difference Result 4107 states and 4811 transitions. [2019-11-28 00:26:50,881 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-11-28 00:26:50,881 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 118 [2019-11-28 00:26:50,881 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:26:50,889 INFO L225 Difference]: With dead ends: 4107 [2019-11-28 00:26:50,890 INFO L226 Difference]: Without dead ends: 3084 [2019-11-28 00:26:50,893 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 125 GetRequests, 119 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-11-28 00:26:50,899 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3084 states. [2019-11-28 00:26:51,150 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3084 to 2067. [2019-11-28 00:26:51,151 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2067 states. [2019-11-28 00:26:51,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2067 states to 2067 states and 2410 transitions. [2019-11-28 00:26:51,156 INFO L78 Accepts]: Start accepts. Automaton has 2067 states and 2410 transitions. Word has length 118 [2019-11-28 00:26:51,156 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:26:51,157 INFO L462 AbstractCegarLoop]: Abstraction has 2067 states and 2410 transitions. [2019-11-28 00:26:51,157 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 00:26:51,157 INFO L276 IsEmpty]: Start isEmpty. Operand 2067 states and 2410 transitions. [2019-11-28 00:26:51,162 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 173 [2019-11-28 00:26:51,162 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:26:51,163 INFO L410 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:26:51,369 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-28 00:26:51,369 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:26:51,369 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:26:51,370 INFO L82 PathProgramCache]: Analyzing trace with hash -2045968037, now seen corresponding path program 1 times [2019-11-28 00:26:51,370 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:26:51,370 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1040404574] [2019-11-28 00:26:51,371 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:26:51,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:26:51,486 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 129 proven. 0 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2019-11-28 00:26:51,489 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1040404574] [2019-11-28 00:26:51,489 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:26:51,490 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:26:51,490 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1213149358] [2019-11-28 00:26:51,491 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:26:51,491 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:26:51,491 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:26:51,492 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:26:51,492 INFO L87 Difference]: Start difference. First operand 2067 states and 2410 transitions. Second operand 3 states. [2019-11-28 00:26:51,875 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:26:51,875 INFO L93 Difference]: Finished difference Result 5041 states and 5868 transitions. [2019-11-28 00:26:51,876 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:26:51,876 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 172 [2019-11-28 00:26:51,876 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:26:51,882 INFO L225 Difference]: With dead ends: 5041 [2019-11-28 00:26:51,882 INFO L226 Difference]: Without dead ends: 3137 [2019-11-28 00:26:51,886 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:26:51,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3137 states. [2019-11-28 00:26:52,241 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3137 to 3087. [2019-11-28 00:26:52,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3087 states. [2019-11-28 00:26:52,246 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3087 states to 3087 states and 3575 transitions. [2019-11-28 00:26:52,247 INFO L78 Accepts]: Start accepts. Automaton has 3087 states and 3575 transitions. Word has length 172 [2019-11-28 00:26:52,247 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:26:52,247 INFO L462 AbstractCegarLoop]: Abstraction has 3087 states and 3575 transitions. [2019-11-28 00:26:52,247 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:26:52,248 INFO L276 IsEmpty]: Start isEmpty. Operand 3087 states and 3575 transitions. [2019-11-28 00:26:52,252 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 173 [2019-11-28 00:26:52,252 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:26:52,253 INFO L410 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:26:52,253 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:26:52,253 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:26:52,253 INFO L82 PathProgramCache]: Analyzing trace with hash 1191161181, now seen corresponding path program 1 times [2019-11-28 00:26:52,254 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:26:52,254 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [869678628] [2019-11-28 00:26:52,254 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:26:52,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:26:52,304 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 99 proven. 0 refuted. 0 times theorem prover too weak. 57 trivial. 0 not checked. [2019-11-28 00:26:52,304 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [869678628] [2019-11-28 00:26:52,305 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:26:52,305 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:26:52,305 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [794872072] [2019-11-28 00:26:52,305 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:26:52,306 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:26:52,306 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:26:52,306 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:26:52,306 INFO L87 Difference]: Start difference. First operand 3087 states and 3575 transitions. Second operand 3 states. [2019-11-28 00:26:52,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:26:52,508 INFO L93 Difference]: Finished difference Result 4589 states and 5331 transitions. [2019-11-28 00:26:52,509 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:26:52,509 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 172 [2019-11-28 00:26:52,509 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:26:52,514 INFO L225 Difference]: With dead ends: 4589 [2019-11-28 00:26:52,514 INFO L226 Difference]: Without dead ends: 1619 [2019-11-28 00:26:52,519 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:26:52,526 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1619 states. [2019-11-28 00:26:52,714 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1619 to 1619. [2019-11-28 00:26:52,714 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1619 states. [2019-11-28 00:26:52,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1619 states to 1619 states and 1839 transitions. [2019-11-28 00:26:52,717 INFO L78 Accepts]: Start accepts. Automaton has 1619 states and 1839 transitions. Word has length 172 [2019-11-28 00:26:52,717 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:26:52,718 INFO L462 AbstractCegarLoop]: Abstraction has 1619 states and 1839 transitions. [2019-11-28 00:26:52,718 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:26:52,718 INFO L276 IsEmpty]: Start isEmpty. Operand 1619 states and 1839 transitions. [2019-11-28 00:26:52,722 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 191 [2019-11-28 00:26:52,722 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:26:52,722 INFO L410 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:26:52,723 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:26:52,724 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:26:52,724 INFO L82 PathProgramCache]: Analyzing trace with hash 1404970223, now seen corresponding path program 1 times [2019-11-28 00:26:52,724 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:26:52,724 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1368165452] [2019-11-28 00:26:52,725 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:26:52,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 00:26:52,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 00:26:52,887 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-28 00:26:52,887 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-28 00:26:53,135 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 12:26:53 BoogieIcfgContainer [2019-11-28 00:26:53,135 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-28 00:26:53,135 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-28 00:26:53,136 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-28 00:26:53,136 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-28 00:26:53,137 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 12:26:38" (3/4) ... [2019-11-28 00:26:53,140 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-28 00:26:53,415 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2019-11-28 00:26:53,415 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-28 00:26:53,418 INFO L168 Benchmark]: Toolchain (without parser) took 16022.67 ms. Allocated memory was 1.0 GB in the beginning and 2.2 GB in the end (delta: 1.1 GB). Free memory was 957.7 MB in the beginning and 1.7 GB in the end (delta: -778.7 MB). Peak memory consumption was 371.1 MB. Max. memory is 11.5 GB. [2019-11-28 00:26:53,418 INFO L168 Benchmark]: CDTParser took 0.25 ms. Allocated memory is still 1.0 GB. Free memory is still 987.2 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 00:26:53,419 INFO L168 Benchmark]: CACSL2BoogieTranslator took 419.11 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 86.5 MB). Free memory was 957.7 MB in the beginning and 1.1 GB in the end (delta: -116.4 MB). Peak memory consumption was 20.4 MB. Max. memory is 11.5 GB. [2019-11-28 00:26:53,419 INFO L168 Benchmark]: Boogie Procedure Inliner took 49.55 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 00:26:53,419 INFO L168 Benchmark]: Boogie Preprocessor took 43.37 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.8 MB). Peak memory consumption was 6.8 MB. Max. memory is 11.5 GB. [2019-11-28 00:26:53,420 INFO L168 Benchmark]: RCFGBuilder took 581.48 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 32.0 MB). Peak memory consumption was 32.0 MB. Max. memory is 11.5 GB. [2019-11-28 00:26:53,420 INFO L168 Benchmark]: TraceAbstraction took 14644.77 ms. Allocated memory was 1.1 GB in the beginning and 2.2 GB in the end (delta: 1.1 GB). Free memory was 1.0 GB in the beginning and 1.8 GB in the end (delta: -728.1 MB). Peak memory consumption was 335.1 MB. Max. memory is 11.5 GB. [2019-11-28 00:26:53,420 INFO L168 Benchmark]: Witness Printer took 279.51 ms. Allocated memory is still 2.2 GB. Free memory was 1.8 GB in the beginning and 1.7 GB in the end (delta: 27.0 MB). Peak memory consumption was 27.0 MB. Max. memory is 11.5 GB. [2019-11-28 00:26:53,422 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.25 ms. Allocated memory is still 1.0 GB. Free memory is still 987.2 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 419.11 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 86.5 MB). Free memory was 957.7 MB in the beginning and 1.1 GB in the end (delta: -116.4 MB). Peak memory consumption was 20.4 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 49.55 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 43.37 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.8 MB). Peak memory consumption was 6.8 MB. Max. memory is 11.5 GB. * RCFGBuilder took 581.48 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 32.0 MB). Peak memory consumption was 32.0 MB. Max. memory is 11.5 GB. * TraceAbstraction took 14644.77 ms. Allocated memory was 1.1 GB in the beginning and 2.2 GB in the end (delta: 1.1 GB). Free memory was 1.0 GB in the beginning and 1.8 GB in the end (delta: -728.1 MB). Peak memory consumption was 335.1 MB. Max. memory is 11.5 GB. * Witness Printer took 279.51 ms. Allocated memory is still 2.2 GB. Free memory was 1.8 GB in the beginning and 1.7 GB in the end (delta: 27.0 MB). Peak memory consumption was 27.0 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 9]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int max_loop ; [L16] int num ; [L17] int i ; [L18] int e ; [L19] int timer ; [L20] char data_0 ; [L21] char data_1 ; [L64] int P_1_pc; [L65] int P_1_st ; [L66] int P_1_i ; [L67] int P_1_ev ; [L122] int C_1_pc ; [L123] int C_1_st ; [L124] int C_1_i ; [L125] int C_1_ev ; [L126] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, timer=0] [L490] int count ; [L491] int __retres2 ; [L495] num = 0 [L496] i = 0 [L497] max_loop = 2 [L499] timer = 0 [L500] P_1_pc = 0 [L501] C_1_pc = 0 [L503] count = 0 [L483] P_1_i = 1 [L484] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L421] int kernel_st ; [L422] int tmp ; [L423] int tmp___0 ; [L427] kernel_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L226] COND TRUE (int )P_1_i == 1 [L227] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L231] COND TRUE (int )C_1_i == 1 [L232] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; [L104] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L107] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L117] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L119] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L371] tmp = is_P_1_triggered() [L373] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L186] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L189] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L199] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L209] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L211] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L435] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L438] kernel_st = 1 [L262] int tmp ; [L263] int tmp___0 ; [L264] int tmp___1 ; [L265] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L269] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L241] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L258] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L294] COND TRUE (int )C_1_st == 0 [L296] tmp___1 = __VERIFIER_nondet_int() [L298] COND TRUE \read(tmp___1) [L300] C_1_st = 1 [L128] char c ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L131] COND TRUE (int )C_1_pc == 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L146] COND TRUE i < max_loop VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L148] COND TRUE num == 0 [L149] timer = 1 [L150] i += 1 [L151] C_1_pc = 1 [L152] C_1_st = 2 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L269] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L258] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND TRUE \read(tmp) [L285] P_1_st = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L72] COND TRUE (int )P_1_pc == 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L83] COND TRUE i < max_loop VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L49] COND TRUE i___0 == 0 [L50] data_0 = c VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L87] num += 1 [L88] P_1_pc = 1 [L89] P_1_st = 2 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L294] COND FALSE !((int )C_1_st == 0) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L269] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND FALSE !(\read(tmp___2)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L442] kernel_st = 2 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L446] kernel_st = 3 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; [L104] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND FALSE !((int )P_1_ev == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L117] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L186] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L190] COND FALSE !((int )e == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L209] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L211] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L452] tmp = exists_runnable_thread() [L454] COND TRUE tmp == 0 [L456] kernel_st = 4 [L336] C_1_ev = 1 [L338] P_1_ev = 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; [L104] int __retres1 ; VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND TRUE (int )P_1_ev == 1 [L109] __retres1 = 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND TRUE \read(tmp) [L374] P_1_st = 0 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L186] int __retres1 ; VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L190] COND FALSE !((int )e == 1) VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L209] __retres1 = 0 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L211] return (__retres1); VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L350] COND TRUE (int )P_1_ev == 1 [L351] P_1_ev = 2 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L355] COND TRUE (int )C_1_ev == 1 [L356] C_1_ev = 2 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L402] int tmp ; [L403] int __retres2 ; [L241] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] tmp = exists_runnable_thread() [L409] COND TRUE \read(tmp) [L410] __retres2 = 0 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L417] return (__retres2); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L465] tmp___0 = stop_simulation() [L467] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L435] COND TRUE 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L438] kernel_st = 1 [L262] int tmp ; [L263] int tmp___0 ; [L264] int tmp___1 ; [L265] int tmp___2 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L269] COND TRUE 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND TRUE \read(tmp) [L285] P_1_st = 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L72] COND FALSE !((int )P_1_pc == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L75] COND TRUE (int )P_1_pc == 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L83] COND TRUE i < max_loop VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L49] COND FALSE !(i___0 == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L52] COND TRUE i___0 == 1 [L53] data_1 = c VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L87] num += 1 [L88] P_1_pc = 1 [L89] P_1_st = 2 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L294] COND FALSE !((int )C_1_st == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L269] COND TRUE 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND FALSE !(\read(tmp___2)) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L442] kernel_st = 2 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L446] kernel_st = 3 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; [L104] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND FALSE !((int )P_1_ev == 1) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L117] __retres1 = 0 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND FALSE !(\read(tmp)) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L186] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L190] COND FALSE !((int )e == 1) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L209] __retres1 = 0 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L211] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L452] tmp = exists_runnable_thread() [L454] COND TRUE tmp == 0 [L456] kernel_st = 4 [L336] C_1_ev = 1 [L338] P_1_ev = 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; [L104] int __retres1 ; VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND TRUE (int )P_1_ev == 1 [L109] __retres1 = 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND TRUE \read(tmp) [L374] P_1_st = 0 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L186] int __retres1 ; VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L190] COND FALSE !((int )e == 1) VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L209] __retres1 = 0 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L211] return (__retres1); VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L350] COND TRUE (int )P_1_ev == 1 [L351] P_1_ev = 2 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L355] COND TRUE (int )C_1_ev == 1 [L356] C_1_ev = 2 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L402] int tmp ; [L403] int __retres2 ; [L241] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] tmp = exists_runnable_thread() [L409] COND TRUE \read(tmp) [L410] __retres2 = 0 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L417] return (__retres2); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L465] tmp___0 = stop_simulation() [L467] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L435] COND TRUE 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L438] kernel_st = 1 [L262] int tmp ; [L263] int tmp___0 ; [L264] int tmp___1 ; [L265] int tmp___2 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L269] COND TRUE 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND TRUE \read(tmp) [L285] P_1_st = 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L72] COND FALSE !((int )P_1_pc == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L75] COND TRUE (int )P_1_pc == 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L83] COND TRUE i < max_loop VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L49] COND FALSE !(i___0 == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L52] COND FALSE !(i___0 == 1) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L9] __VERIFIER_error() VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 117 locations, 3 error locations. Result: UNSAFE, OverallTime: 14.3s, OverallIterations: 25, TraceHistogramMax: 6, AutomataDifference: 6.3s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 4775 SDtfs, 4830 SDslu, 6046 SDs, 0 SdLazy, 568 SolverSat, 139 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.6s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 232 GetRequests, 169 SyntacticMatches, 3 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.4s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=4273occurred in iteration=10, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 5.5s AutomataMinimizationTime, 24 MinimizatonAttempts, 6607 StatesRemovedByMinimization, 20 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 1.0s InterpolantComputationTime, 2135 NumberOfCodeBlocks, 2135 NumberOfCodeBlocksAsserted, 26 NumberOfCheckSat, 1920 ConstructedInterpolants, 0 QuantifiedInterpolants, 350700 SizeOfPredicates, 2 NumberOfNonLiveVariables, 344 ConjunctsInSsa, 9 ConjunctsInUnsatCore, 25 InterpolantComputations, 23 PerfectInterpolantSequences, 619/689 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...