./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/systemc/toy1.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 30f4e4ab Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx12G -Xms1G -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/systemc/toy1.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 133c91eb4ca703e3ebf3582d43ed0be6dbefca67 ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.24-30f4e4a [2019-11-28 00:28:18,731 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-28 00:28:18,734 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-28 00:28:18,748 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-28 00:28:18,749 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-28 00:28:18,750 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-28 00:28:18,752 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-28 00:28:18,754 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-28 00:28:18,763 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-28 00:28:18,766 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-28 00:28:18,768 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-28 00:28:18,769 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-28 00:28:18,771 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-28 00:28:18,774 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-28 00:28:18,776 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-28 00:28:18,778 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-28 00:28:18,781 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-28 00:28:18,785 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-28 00:28:18,788 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-28 00:28:18,794 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-28 00:28:18,795 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-28 00:28:18,798 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-28 00:28:18,802 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-28 00:28:18,803 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-28 00:28:18,807 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-28 00:28:18,807 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-28 00:28:18,808 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-28 00:28:18,810 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-28 00:28:18,811 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-28 00:28:18,814 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-28 00:28:18,814 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-28 00:28:18,815 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-28 00:28:18,816 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-28 00:28:18,817 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-28 00:28:18,819 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-28 00:28:18,819 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-28 00:28:18,821 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-28 00:28:18,821 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-28 00:28:18,821 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-28 00:28:18,823 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-28 00:28:18,825 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-28 00:28:18,826 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-28 00:28:18,864 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-28 00:28:18,867 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-28 00:28:18,868 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-28 00:28:18,870 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-28 00:28:18,870 INFO L138 SettingsManager]: * Use SBE=true [2019-11-28 00:28:18,873 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-28 00:28:18,873 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-28 00:28:18,873 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-28 00:28:18,874 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-28 00:28:18,874 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-28 00:28:18,874 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-28 00:28:18,875 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-28 00:28:18,875 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-28 00:28:18,875 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-28 00:28:18,875 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-28 00:28:18,877 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-28 00:28:18,877 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-28 00:28:18,877 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-28 00:28:18,878 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-28 00:28:18,878 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-28 00:28:18,879 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-28 00:28:18,879 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 00:28:18,879 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-28 00:28:18,880 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-28 00:28:18,880 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-28 00:28:18,881 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-28 00:28:18,881 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-28 00:28:18,881 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-28 00:28:18,882 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 133c91eb4ca703e3ebf3582d43ed0be6dbefca67 [2019-11-28 00:28:19,238 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-28 00:28:19,257 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-28 00:28:19,261 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-28 00:28:19,263 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-28 00:28:19,263 INFO L275 PluginConnector]: CDTParser initialized [2019-11-28 00:28:19,265 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/toy1.cil.c [2019-11-28 00:28:19,340 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7fde12496/f5e015ea6fb148d6aeb549cde365e11f/FLAG652ae83d1 [2019-11-28 00:28:19,927 INFO L306 CDTParser]: Found 1 translation units. [2019-11-28 00:28:19,928 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/toy1.cil.c [2019-11-28 00:28:19,950 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7fde12496/f5e015ea6fb148d6aeb549cde365e11f/FLAG652ae83d1 [2019-11-28 00:28:20,261 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7fde12496/f5e015ea6fb148d6aeb549cde365e11f [2019-11-28 00:28:20,265 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-28 00:28:20,268 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-28 00:28:20,272 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-28 00:28:20,273 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-28 00:28:20,277 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-28 00:28:20,278 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 12:28:20" (1/1) ... [2019-11-28 00:28:20,281 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2f061439 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:20, skipping insertion in model container [2019-11-28 00:28:20,282 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 12:28:20" (1/1) ... [2019-11-28 00:28:20,292 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-11-28 00:28:20,347 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-11-28 00:28:20,584 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 00:28:20,589 INFO L203 MainTranslator]: Completed pre-run [2019-11-28 00:28:20,738 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 00:28:20,756 INFO L208 MainTranslator]: Completed translation [2019-11-28 00:28:20,757 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:20 WrapperNode [2019-11-28 00:28:20,757 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-28 00:28:20,758 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-28 00:28:20,759 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-28 00:28:20,759 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-28 00:28:20,768 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:20" (1/1) ... [2019-11-28 00:28:20,778 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:20" (1/1) ... [2019-11-28 00:28:20,812 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-28 00:28:20,813 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-28 00:28:20,813 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-28 00:28:20,813 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-28 00:28:20,824 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:20" (1/1) ... [2019-11-28 00:28:20,825 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:20" (1/1) ... [2019-11-28 00:28:20,839 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:20" (1/1) ... [2019-11-28 00:28:20,839 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:20" (1/1) ... [2019-11-28 00:28:20,853 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:20" (1/1) ... [2019-11-28 00:28:20,874 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:20" (1/1) ... [2019-11-28 00:28:20,877 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:20" (1/1) ... [2019-11-28 00:28:20,881 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-28 00:28:20,882 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-28 00:28:20,882 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-28 00:28:20,883 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-28 00:28:20,884 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:20" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 00:28:20,947 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-28 00:28:20,948 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-28 00:28:21,608 INFO L292 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-28 00:28:21,608 INFO L297 CfgBuilder]: Removed 28 assume(true) statements. [2019-11-28 00:28:21,610 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 12:28:21 BoogieIcfgContainer [2019-11-28 00:28:21,611 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-28 00:28:21,613 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-28 00:28:21,614 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-28 00:28:21,617 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-28 00:28:21,617 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 12:28:20" (1/3) ... [2019-11-28 00:28:21,621 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2503f712 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 12:28:21, skipping insertion in model container [2019-11-28 00:28:21,621 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:20" (2/3) ... [2019-11-28 00:28:21,622 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2503f712 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 12:28:21, skipping insertion in model container [2019-11-28 00:28:21,622 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 12:28:21" (3/3) ... [2019-11-28 00:28:21,624 INFO L109 eAbstractionObserver]: Analyzing ICFG toy1.cil.c [2019-11-28 00:28:21,635 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-28 00:28:21,643 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-11-28 00:28:21,657 INFO L249 AbstractCegarLoop]: Starting to check reachability of 2 error locations. [2019-11-28 00:28:21,699 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-28 00:28:21,699 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-28 00:28:21,699 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-28 00:28:21,699 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-28 00:28:21,700 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-28 00:28:21,701 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-28 00:28:21,701 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-28 00:28:21,701 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-28 00:28:21,725 INFO L276 IsEmpty]: Start isEmpty. Operand 129 states. [2019-11-28 00:28:21,733 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-28 00:28:21,733 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:21,735 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:21,735 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:21,741 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:21,742 INFO L82 PathProgramCache]: Analyzing trace with hash -895778166, now seen corresponding path program 1 times [2019-11-28 00:28:21,751 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:21,752 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1235892673] [2019-11-28 00:28:21,752 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:21,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:21,930 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:21,931 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1235892673] [2019-11-28 00:28:21,933 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:21,933 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:21,935 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [863701285] [2019-11-28 00:28:21,941 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:21,941 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:21,956 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:21,957 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:21,959 INFO L87 Difference]: Start difference. First operand 129 states. Second operand 3 states. [2019-11-28 00:28:22,010 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:22,010 INFO L93 Difference]: Finished difference Result 250 states and 461 transitions. [2019-11-28 00:28:22,011 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:22,012 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 36 [2019-11-28 00:28:22,013 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:22,026 INFO L225 Difference]: With dead ends: 250 [2019-11-28 00:28:22,026 INFO L226 Difference]: Without dead ends: 125 [2019-11-28 00:28:22,030 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:22,047 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125 states. [2019-11-28 00:28:22,073 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125 to 125. [2019-11-28 00:28:22,074 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125 states. [2019-11-28 00:28:22,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 218 transitions. [2019-11-28 00:28:22,078 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 218 transitions. Word has length 36 [2019-11-28 00:28:22,079 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:22,079 INFO L462 AbstractCegarLoop]: Abstraction has 125 states and 218 transitions. [2019-11-28 00:28:22,079 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:22,079 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 218 transitions. [2019-11-28 00:28:22,081 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-28 00:28:22,081 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:22,081 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:22,082 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:22,082 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:22,082 INFO L82 PathProgramCache]: Analyzing trace with hash -1597378040, now seen corresponding path program 1 times [2019-11-28 00:28:22,082 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:22,083 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1669474563] [2019-11-28 00:28:22,083 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:22,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:22,152 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:22,153 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1669474563] [2019-11-28 00:28:22,153 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:22,153 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:22,153 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [752802959] [2019-11-28 00:28:22,155 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:22,156 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:22,156 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:22,156 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:22,156 INFO L87 Difference]: Start difference. First operand 125 states and 218 transitions. Second operand 3 states. [2019-11-28 00:28:22,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:22,186 INFO L93 Difference]: Finished difference Result 240 states and 420 transitions. [2019-11-28 00:28:22,187 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:22,187 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 36 [2019-11-28 00:28:22,188 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:22,189 INFO L225 Difference]: With dead ends: 240 [2019-11-28 00:28:22,189 INFO L226 Difference]: Without dead ends: 125 [2019-11-28 00:28:22,191 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:22,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125 states. [2019-11-28 00:28:22,209 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125 to 125. [2019-11-28 00:28:22,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125 states. [2019-11-28 00:28:22,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 217 transitions. [2019-11-28 00:28:22,212 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 217 transitions. Word has length 36 [2019-11-28 00:28:22,212 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:22,212 INFO L462 AbstractCegarLoop]: Abstraction has 125 states and 217 transitions. [2019-11-28 00:28:22,212 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:22,213 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 217 transitions. [2019-11-28 00:28:22,214 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-28 00:28:22,214 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:22,215 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:22,215 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:22,215 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:22,215 INFO L82 PathProgramCache]: Analyzing trace with hash -211174646, now seen corresponding path program 1 times [2019-11-28 00:28:22,216 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:22,216 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [863853531] [2019-11-28 00:28:22,216 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:22,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:22,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:22,314 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [863853531] [2019-11-28 00:28:22,314 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:22,314 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:22,315 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [476707199] [2019-11-28 00:28:22,316 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:22,316 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:22,317 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:22,317 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:22,317 INFO L87 Difference]: Start difference. First operand 125 states and 217 transitions. Second operand 3 states. [2019-11-28 00:28:22,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:22,476 INFO L93 Difference]: Finished difference Result 328 states and 568 transitions. [2019-11-28 00:28:22,477 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:22,477 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 36 [2019-11-28 00:28:22,478 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:22,484 INFO L225 Difference]: With dead ends: 328 [2019-11-28 00:28:22,484 INFO L226 Difference]: Without dead ends: 214 [2019-11-28 00:28:22,488 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:22,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 214 states. [2019-11-28 00:28:22,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 214 to 200. [2019-11-28 00:28:22,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 200 states. [2019-11-28 00:28:22,529 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 200 states to 200 states and 335 transitions. [2019-11-28 00:28:22,529 INFO L78 Accepts]: Start accepts. Automaton has 200 states and 335 transitions. Word has length 36 [2019-11-28 00:28:22,529 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:22,530 INFO L462 AbstractCegarLoop]: Abstraction has 200 states and 335 transitions. [2019-11-28 00:28:22,530 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:22,530 INFO L276 IsEmpty]: Start isEmpty. Operand 200 states and 335 transitions. [2019-11-28 00:28:22,531 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-28 00:28:22,532 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:22,532 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:22,532 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:22,533 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:22,533 INFO L82 PathProgramCache]: Analyzing trace with hash 1832431686, now seen corresponding path program 1 times [2019-11-28 00:28:22,533 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:22,534 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1603897831] [2019-11-28 00:28:22,534 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:22,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:22,583 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:22,585 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1603897831] [2019-11-28 00:28:22,585 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:22,585 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 00:28:22,586 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [561717509] [2019-11-28 00:28:22,586 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 00:28:22,586 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:22,587 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 00:28:22,587 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 00:28:22,587 INFO L87 Difference]: Start difference. First operand 200 states and 335 transitions. Second operand 4 states. [2019-11-28 00:28:22,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:22,731 INFO L93 Difference]: Finished difference Result 542 states and 911 transitions. [2019-11-28 00:28:22,731 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 00:28:22,732 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2019-11-28 00:28:22,732 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:22,735 INFO L225 Difference]: With dead ends: 542 [2019-11-28 00:28:22,735 INFO L226 Difference]: Without dead ends: 354 [2019-11-28 00:28:22,736 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 00:28:22,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 354 states. [2019-11-28 00:28:22,761 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 354 to 344. [2019-11-28 00:28:22,762 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 344 states. [2019-11-28 00:28:22,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 344 states to 344 states and 577 transitions. [2019-11-28 00:28:22,764 INFO L78 Accepts]: Start accepts. Automaton has 344 states and 577 transitions. Word has length 36 [2019-11-28 00:28:22,764 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:22,764 INFO L462 AbstractCegarLoop]: Abstraction has 344 states and 577 transitions. [2019-11-28 00:28:22,765 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 00:28:22,765 INFO L276 IsEmpty]: Start isEmpty. Operand 344 states and 577 transitions. [2019-11-28 00:28:22,767 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-28 00:28:22,767 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:22,767 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:22,768 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:22,768 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:22,768 INFO L82 PathProgramCache]: Analyzing trace with hash -539307576, now seen corresponding path program 1 times [2019-11-28 00:28:22,768 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:22,769 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1736719211] [2019-11-28 00:28:22,769 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:22,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:22,817 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:22,818 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1736719211] [2019-11-28 00:28:22,818 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:22,818 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 00:28:22,819 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [16049208] [2019-11-28 00:28:22,819 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 00:28:22,819 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:22,820 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 00:28:22,820 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 00:28:22,820 INFO L87 Difference]: Start difference. First operand 344 states and 577 transitions. Second operand 4 states. [2019-11-28 00:28:22,974 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:22,974 INFO L93 Difference]: Finished difference Result 967 states and 1626 transitions. [2019-11-28 00:28:22,975 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 00:28:22,975 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2019-11-28 00:28:22,976 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:22,980 INFO L225 Difference]: With dead ends: 967 [2019-11-28 00:28:22,981 INFO L226 Difference]: Without dead ends: 636 [2019-11-28 00:28:22,983 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 00:28:22,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 636 states. [2019-11-28 00:28:23,040 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 636 to 626. [2019-11-28 00:28:23,040 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 626 states. [2019-11-28 00:28:23,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 1047 transitions. [2019-11-28 00:28:23,044 INFO L78 Accepts]: Start accepts. Automaton has 626 states and 1047 transitions. Word has length 36 [2019-11-28 00:28:23,044 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:23,044 INFO L462 AbstractCegarLoop]: Abstraction has 626 states and 1047 transitions. [2019-11-28 00:28:23,044 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 00:28:23,045 INFO L276 IsEmpty]: Start isEmpty. Operand 626 states and 1047 transitions. [2019-11-28 00:28:23,048 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-28 00:28:23,048 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:23,048 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:23,048 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:23,049 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:23,049 INFO L82 PathProgramCache]: Analyzing trace with hash -477267962, now seen corresponding path program 1 times [2019-11-28 00:28:23,049 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:23,050 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1768576629] [2019-11-28 00:28:23,050 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:23,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:23,116 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:23,117 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1768576629] [2019-11-28 00:28:23,117 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:23,117 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 00:28:23,117 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1595220618] [2019-11-28 00:28:23,118 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 00:28:23,119 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:23,119 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 00:28:23,119 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 00:28:23,119 INFO L87 Difference]: Start difference. First operand 626 states and 1047 transitions. Second operand 4 states. [2019-11-28 00:28:23,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:23,282 INFO L93 Difference]: Finished difference Result 1903 states and 3163 transitions. [2019-11-28 00:28:23,282 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 00:28:23,283 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2019-11-28 00:28:23,283 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:23,291 INFO L225 Difference]: With dead ends: 1903 [2019-11-28 00:28:23,291 INFO L226 Difference]: Without dead ends: 1291 [2019-11-28 00:28:23,294 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 00:28:23,296 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1291 states. [2019-11-28 00:28:23,363 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1291 to 1281. [2019-11-28 00:28:23,364 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1281 states. [2019-11-28 00:28:23,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1281 states to 1281 states and 2107 transitions. [2019-11-28 00:28:23,372 INFO L78 Accepts]: Start accepts. Automaton has 1281 states and 2107 transitions. Word has length 36 [2019-11-28 00:28:23,372 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:23,372 INFO L462 AbstractCegarLoop]: Abstraction has 1281 states and 2107 transitions. [2019-11-28 00:28:23,373 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 00:28:23,373 INFO L276 IsEmpty]: Start isEmpty. Operand 1281 states and 2107 transitions. [2019-11-28 00:28:23,375 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-28 00:28:23,376 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:23,376 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:23,377 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:23,377 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:23,377 INFO L82 PathProgramCache]: Analyzing trace with hash -336719352, now seen corresponding path program 1 times [2019-11-28 00:28:23,378 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:23,378 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1717587270] [2019-11-28 00:28:23,378 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:23,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:23,496 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:23,496 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1717587270] [2019-11-28 00:28:23,497 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:23,497 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:23,497 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1020039436] [2019-11-28 00:28:23,499 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:23,499 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:23,500 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:23,500 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:23,500 INFO L87 Difference]: Start difference. First operand 1281 states and 2107 transitions. Second operand 3 states. [2019-11-28 00:28:23,654 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:23,655 INFO L93 Difference]: Finished difference Result 2615 states and 4310 transitions. [2019-11-28 00:28:23,655 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:23,655 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 36 [2019-11-28 00:28:23,656 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:23,664 INFO L225 Difference]: With dead ends: 2615 [2019-11-28 00:28:23,664 INFO L226 Difference]: Without dead ends: 1391 [2019-11-28 00:28:23,667 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:23,669 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1391 states. [2019-11-28 00:28:23,729 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1391 to 1382. [2019-11-28 00:28:23,729 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1382 states. [2019-11-28 00:28:23,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1382 states to 1382 states and 2266 transitions. [2019-11-28 00:28:23,736 INFO L78 Accepts]: Start accepts. Automaton has 1382 states and 2266 transitions. Word has length 36 [2019-11-28 00:28:23,737 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:23,737 INFO L462 AbstractCegarLoop]: Abstraction has 1382 states and 2266 transitions. [2019-11-28 00:28:23,737 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:23,737 INFO L276 IsEmpty]: Start isEmpty. Operand 1382 states and 2266 transitions. [2019-11-28 00:28:23,740 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-28 00:28:23,740 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:23,741 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:23,741 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:23,741 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:23,741 INFO L82 PathProgramCache]: Analyzing trace with hash 952985988, now seen corresponding path program 1 times [2019-11-28 00:28:23,742 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:23,742 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1852282849] [2019-11-28 00:28:23,742 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:23,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:23,802 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:23,803 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1852282849] [2019-11-28 00:28:23,803 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:23,803 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 00:28:23,804 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [184007440] [2019-11-28 00:28:23,804 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 00:28:23,804 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:23,805 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 00:28:23,805 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 00:28:23,806 INFO L87 Difference]: Start difference. First operand 1382 states and 2266 transitions. Second operand 4 states. [2019-11-28 00:28:23,970 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:23,971 INFO L93 Difference]: Finished difference Result 2900 states and 4764 transitions. [2019-11-28 00:28:23,971 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-28 00:28:23,971 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2019-11-28 00:28:23,972 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:23,980 INFO L225 Difference]: With dead ends: 2900 [2019-11-28 00:28:23,980 INFO L226 Difference]: Without dead ends: 1552 [2019-11-28 00:28:23,983 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 00:28:24,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1552 states. [2019-11-28 00:28:24,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1552 to 1539. [2019-11-28 00:28:24,089 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1539 states. [2019-11-28 00:28:24,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1539 states to 1539 states and 2488 transitions. [2019-11-28 00:28:24,095 INFO L78 Accepts]: Start accepts. Automaton has 1539 states and 2488 transitions. Word has length 36 [2019-11-28 00:28:24,096 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:24,096 INFO L462 AbstractCegarLoop]: Abstraction has 1539 states and 2488 transitions. [2019-11-28 00:28:24,096 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 00:28:24,096 INFO L276 IsEmpty]: Start isEmpty. Operand 1539 states and 2488 transitions. [2019-11-28 00:28:24,097 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-28 00:28:24,097 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:24,097 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:24,097 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:24,098 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:24,098 INFO L82 PathProgramCache]: Analyzing trace with hash -635361914, now seen corresponding path program 1 times [2019-11-28 00:28:24,098 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:24,099 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1029202703] [2019-11-28 00:28:24,099 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:24,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:24,137 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:24,138 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1029202703] [2019-11-28 00:28:24,138 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:24,138 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 00:28:24,139 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [716015043] [2019-11-28 00:28:24,139 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 00:28:24,139 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:24,140 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 00:28:24,140 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 00:28:24,140 INFO L87 Difference]: Start difference. First operand 1539 states and 2488 transitions. Second operand 4 states. [2019-11-28 00:28:24,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:24,301 INFO L93 Difference]: Finished difference Result 3378 states and 5467 transitions. [2019-11-28 00:28:24,301 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-28 00:28:24,302 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2019-11-28 00:28:24,302 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:24,312 INFO L225 Difference]: With dead ends: 3378 [2019-11-28 00:28:24,313 INFO L226 Difference]: Without dead ends: 1885 [2019-11-28 00:28:24,316 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 00:28:24,318 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1885 states. [2019-11-28 00:28:24,397 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1885 to 1859. [2019-11-28 00:28:24,397 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1859 states. [2019-11-28 00:28:24,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1859 states to 1859 states and 2968 transitions. [2019-11-28 00:28:24,405 INFO L78 Accepts]: Start accepts. Automaton has 1859 states and 2968 transitions. Word has length 36 [2019-11-28 00:28:24,405 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:24,405 INFO L462 AbstractCegarLoop]: Abstraction has 1859 states and 2968 transitions. [2019-11-28 00:28:24,405 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 00:28:24,406 INFO L276 IsEmpty]: Start isEmpty. Operand 1859 states and 2968 transitions. [2019-11-28 00:28:24,406 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-28 00:28:24,407 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:24,407 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:24,407 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:24,407 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:24,407 INFO L82 PathProgramCache]: Analyzing trace with hash -1915225592, now seen corresponding path program 1 times [2019-11-28 00:28:24,408 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:24,408 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1854424226] [2019-11-28 00:28:24,408 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:24,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:24,441 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:24,441 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1854424226] [2019-11-28 00:28:24,441 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:24,442 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:24,442 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [206698798] [2019-11-28 00:28:24,442 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:24,442 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:24,443 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:24,443 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:24,443 INFO L87 Difference]: Start difference. First operand 1859 states and 2968 transitions. Second operand 3 states. [2019-11-28 00:28:24,550 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:24,550 INFO L93 Difference]: Finished difference Result 3335 states and 5328 transitions. [2019-11-28 00:28:24,553 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:24,554 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 36 [2019-11-28 00:28:24,556 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:24,565 INFO L225 Difference]: With dead ends: 3335 [2019-11-28 00:28:24,565 INFO L226 Difference]: Without dead ends: 1504 [2019-11-28 00:28:24,569 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:24,572 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1504 states. [2019-11-28 00:28:24,650 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1504 to 1493. [2019-11-28 00:28:24,651 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1493 states. [2019-11-28 00:28:24,658 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1493 states to 1493 states and 2352 transitions. [2019-11-28 00:28:24,658 INFO L78 Accepts]: Start accepts. Automaton has 1493 states and 2352 transitions. Word has length 36 [2019-11-28 00:28:24,658 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:24,662 INFO L462 AbstractCegarLoop]: Abstraction has 1493 states and 2352 transitions. [2019-11-28 00:28:24,662 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:24,662 INFO L276 IsEmpty]: Start isEmpty. Operand 1493 states and 2352 transitions. [2019-11-28 00:28:24,666 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2019-11-28 00:28:24,666 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:24,666 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:24,667 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:24,667 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:24,667 INFO L82 PathProgramCache]: Analyzing trace with hash -547155332, now seen corresponding path program 1 times [2019-11-28 00:28:24,667 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:24,668 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2083879999] [2019-11-28 00:28:24,668 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:24,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:24,711 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:24,712 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2083879999] [2019-11-28 00:28:24,712 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:24,712 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:24,713 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1465082456] [2019-11-28 00:28:24,713 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:24,713 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:24,714 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:24,714 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:24,714 INFO L87 Difference]: Start difference. First operand 1493 states and 2352 transitions. Second operand 3 states. [2019-11-28 00:28:24,829 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:24,829 INFO L93 Difference]: Finished difference Result 3728 states and 5928 transitions. [2019-11-28 00:28:24,830 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:24,830 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 46 [2019-11-28 00:28:24,830 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:24,844 INFO L225 Difference]: With dead ends: 3728 [2019-11-28 00:28:24,844 INFO L226 Difference]: Without dead ends: 2289 [2019-11-28 00:28:24,849 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:24,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2289 states. [2019-11-28 00:28:24,966 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2289 to 2285. [2019-11-28 00:28:24,966 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2285 states. [2019-11-28 00:28:24,975 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2285 states to 2285 states and 3596 transitions. [2019-11-28 00:28:24,975 INFO L78 Accepts]: Start accepts. Automaton has 2285 states and 3596 transitions. Word has length 46 [2019-11-28 00:28:24,976 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:24,976 INFO L462 AbstractCegarLoop]: Abstraction has 2285 states and 3596 transitions. [2019-11-28 00:28:24,976 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:24,976 INFO L276 IsEmpty]: Start isEmpty. Operand 2285 states and 3596 transitions. [2019-11-28 00:28:24,979 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2019-11-28 00:28:24,979 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:24,979 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:24,979 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:24,980 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:24,980 INFO L82 PathProgramCache]: Analyzing trace with hash -299008838, now seen corresponding path program 1 times [2019-11-28 00:28:24,980 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:24,982 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [670402208] [2019-11-28 00:28:24,982 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:24,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:25,017 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2019-11-28 00:28:25,017 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [670402208] [2019-11-28 00:28:25,018 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:25,018 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:25,018 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [523348414] [2019-11-28 00:28:25,018 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:25,019 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:25,019 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:25,019 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:25,019 INFO L87 Difference]: Start difference. First operand 2285 states and 3596 transitions. Second operand 3 states. [2019-11-28 00:28:25,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:25,141 INFO L93 Difference]: Finished difference Result 4472 states and 7066 transitions. [2019-11-28 00:28:25,142 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:25,142 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 46 [2019-11-28 00:28:25,142 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:25,155 INFO L225 Difference]: With dead ends: 4472 [2019-11-28 00:28:25,155 INFO L226 Difference]: Without dead ends: 2241 [2019-11-28 00:28:25,159 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:25,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2241 states. [2019-11-28 00:28:25,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2241 to 2241. [2019-11-28 00:28:25,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2241 states. [2019-11-28 00:28:25,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2241 states to 2241 states and 3539 transitions. [2019-11-28 00:28:25,284 INFO L78 Accepts]: Start accepts. Automaton has 2241 states and 3539 transitions. Word has length 46 [2019-11-28 00:28:25,284 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:25,284 INFO L462 AbstractCegarLoop]: Abstraction has 2241 states and 3539 transitions. [2019-11-28 00:28:25,284 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:25,284 INFO L276 IsEmpty]: Start isEmpty. Operand 2241 states and 3539 transitions. [2019-11-28 00:28:25,286 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2019-11-28 00:28:25,287 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:25,287 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:25,287 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:25,287 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:25,288 INFO L82 PathProgramCache]: Analyzing trace with hash -336670593, now seen corresponding path program 1 times [2019-11-28 00:28:25,288 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:25,288 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1495472547] [2019-11-28 00:28:25,288 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:25,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:25,332 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:25,333 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1495472547] [2019-11-28 00:28:25,334 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:25,334 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:25,334 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1301600149] [2019-11-28 00:28:25,335 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:25,335 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:25,336 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:25,336 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:25,336 INFO L87 Difference]: Start difference. First operand 2241 states and 3539 transitions. Second operand 3 states. [2019-11-28 00:28:25,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:25,559 INFO L93 Difference]: Finished difference Result 5761 states and 9163 transitions. [2019-11-28 00:28:25,560 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:25,560 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 47 [2019-11-28 00:28:25,560 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:25,580 INFO L225 Difference]: With dead ends: 5761 [2019-11-28 00:28:25,580 INFO L226 Difference]: Without dead ends: 3574 [2019-11-28 00:28:25,586 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:25,592 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3574 states. [2019-11-28 00:28:25,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3574 to 3570. [2019-11-28 00:28:25,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3570 states. [2019-11-28 00:28:25,801 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3570 states to 3570 states and 5623 transitions. [2019-11-28 00:28:25,802 INFO L78 Accepts]: Start accepts. Automaton has 3570 states and 5623 transitions. Word has length 47 [2019-11-28 00:28:25,802 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:25,802 INFO L462 AbstractCegarLoop]: Abstraction has 3570 states and 5623 transitions. [2019-11-28 00:28:25,802 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:25,802 INFO L276 IsEmpty]: Start isEmpty. Operand 3570 states and 5623 transitions. [2019-11-28 00:28:25,805 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2019-11-28 00:28:25,808 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:25,808 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:25,808 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:25,808 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:25,808 INFO L82 PathProgramCache]: Analyzing trace with hash 1825522215, now seen corresponding path program 1 times [2019-11-28 00:28:25,809 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:25,813 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1736624503] [2019-11-28 00:28:25,813 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:25,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:25,858 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:25,859 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1736624503] [2019-11-28 00:28:25,859 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:25,859 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:25,859 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1412525113] [2019-11-28 00:28:25,861 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:25,861 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:25,861 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:25,861 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:25,862 INFO L87 Difference]: Start difference. First operand 3570 states and 5623 transitions. Second operand 3 states. [2019-11-28 00:28:26,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:26,200 INFO L93 Difference]: Finished difference Result 9081 states and 14487 transitions. [2019-11-28 00:28:26,200 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:26,201 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2019-11-28 00:28:26,202 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:26,241 INFO L225 Difference]: With dead ends: 9081 [2019-11-28 00:28:26,242 INFO L226 Difference]: Without dead ends: 5569 [2019-11-28 00:28:26,252 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:26,261 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5569 states. [2019-11-28 00:28:26,537 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5569 to 5565. [2019-11-28 00:28:26,538 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5565 states. [2019-11-28 00:28:26,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5565 states to 5565 states and 8840 transitions. [2019-11-28 00:28:26,568 INFO L78 Accepts]: Start accepts. Automaton has 5565 states and 8840 transitions. Word has length 48 [2019-11-28 00:28:26,569 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:26,570 INFO L462 AbstractCegarLoop]: Abstraction has 5565 states and 8840 transitions. [2019-11-28 00:28:26,570 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:26,570 INFO L276 IsEmpty]: Start isEmpty. Operand 5565 states and 8840 transitions. [2019-11-28 00:28:26,575 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2019-11-28 00:28:26,576 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:26,576 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:26,576 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:26,577 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:26,577 INFO L82 PathProgramCache]: Analyzing trace with hash 2073668709, now seen corresponding path program 1 times [2019-11-28 00:28:26,577 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:26,578 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1698173542] [2019-11-28 00:28:26,578 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:26,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:26,599 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2019-11-28 00:28:26,599 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1698173542] [2019-11-28 00:28:26,599 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:26,599 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:26,600 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1596415914] [2019-11-28 00:28:26,600 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:26,600 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:26,600 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:26,602 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:26,602 INFO L87 Difference]: Start difference. First operand 5565 states and 8840 transitions. Second operand 3 states. [2019-11-28 00:28:26,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:26,875 INFO L93 Difference]: Finished difference Result 11028 states and 17554 transitions. [2019-11-28 00:28:26,875 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:26,876 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2019-11-28 00:28:26,876 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:26,917 INFO L225 Difference]: With dead ends: 11028 [2019-11-28 00:28:26,917 INFO L226 Difference]: Without dead ends: 5521 [2019-11-28 00:28:26,929 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:26,937 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5521 states. [2019-11-28 00:28:27,275 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5521 to 5521. [2019-11-28 00:28:27,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5521 states. [2019-11-28 00:28:27,290 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5521 states to 5521 states and 8785 transitions. [2019-11-28 00:28:27,291 INFO L78 Accepts]: Start accepts. Automaton has 5521 states and 8785 transitions. Word has length 48 [2019-11-28 00:28:27,291 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:27,291 INFO L462 AbstractCegarLoop]: Abstraction has 5521 states and 8785 transitions. [2019-11-28 00:28:27,291 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:27,291 INFO L276 IsEmpty]: Start isEmpty. Operand 5521 states and 8785 transitions. [2019-11-28 00:28:27,295 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-11-28 00:28:27,296 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:27,296 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:27,296 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:27,296 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:27,297 INFO L82 PathProgramCache]: Analyzing trace with hash 963117268, now seen corresponding path program 1 times [2019-11-28 00:28:27,297 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:27,297 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1097168688] [2019-11-28 00:28:27,298 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:27,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:27,329 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:27,329 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1097168688] [2019-11-28 00:28:27,329 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:27,329 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:27,331 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1374123091] [2019-11-28 00:28:27,331 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:27,331 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:27,331 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:27,331 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:27,332 INFO L87 Difference]: Start difference. First operand 5521 states and 8785 transitions. Second operand 3 states. [2019-11-28 00:28:27,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:27,727 INFO L93 Difference]: Finished difference Result 15573 states and 24710 transitions. [2019-11-28 00:28:27,727 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:27,728 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 49 [2019-11-28 00:28:27,728 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:27,758 INFO L225 Difference]: With dead ends: 15573 [2019-11-28 00:28:27,758 INFO L226 Difference]: Without dead ends: 8340 [2019-11-28 00:28:27,771 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:27,782 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8340 states. [2019-11-28 00:28:28,141 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8340 to 8340. [2019-11-28 00:28:28,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8340 states. [2019-11-28 00:28:28,166 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8340 states to 8340 states and 13079 transitions. [2019-11-28 00:28:28,166 INFO L78 Accepts]: Start accepts. Automaton has 8340 states and 13079 transitions. Word has length 49 [2019-11-28 00:28:28,166 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:28,167 INFO L462 AbstractCegarLoop]: Abstraction has 8340 states and 13079 transitions. [2019-11-28 00:28:28,167 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:28,167 INFO L276 IsEmpty]: Start isEmpty. Operand 8340 states and 13079 transitions. [2019-11-28 00:28:28,175 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2019-11-28 00:28:28,176 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:28,176 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:28,177 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:28,177 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:28,177 INFO L82 PathProgramCache]: Analyzing trace with hash 1798060104, now seen corresponding path program 1 times [2019-11-28 00:28:28,178 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:28,178 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [474068638] [2019-11-28 00:28:28,178 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:28,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:28,223 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:28,224 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [474068638] [2019-11-28 00:28:28,224 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:28,224 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:28,225 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1043813662] [2019-11-28 00:28:28,225 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:28,225 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:28,226 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:28,226 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:28,226 INFO L87 Difference]: Start difference. First operand 8340 states and 13079 transitions. Second operand 3 states. [2019-11-28 00:28:28,596 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:28,596 INFO L93 Difference]: Finished difference Result 17187 states and 26897 transitions. [2019-11-28 00:28:28,597 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:28,597 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 53 [2019-11-28 00:28:28,597 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:28,623 INFO L225 Difference]: With dead ends: 17187 [2019-11-28 00:28:28,624 INFO L226 Difference]: Without dead ends: 8883 [2019-11-28 00:28:28,641 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:28,655 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8883 states. [2019-11-28 00:28:28,965 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8883 to 8322. [2019-11-28 00:28:28,965 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8322 states. [2019-11-28 00:28:28,983 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8322 states to 8322 states and 12796 transitions. [2019-11-28 00:28:28,984 INFO L78 Accepts]: Start accepts. Automaton has 8322 states and 12796 transitions. Word has length 53 [2019-11-28 00:28:28,984 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:28,984 INFO L462 AbstractCegarLoop]: Abstraction has 8322 states and 12796 transitions. [2019-11-28 00:28:28,985 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:28,985 INFO L276 IsEmpty]: Start isEmpty. Operand 8322 states and 12796 transitions. [2019-11-28 00:28:28,991 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-11-28 00:28:28,992 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:28,992 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:28,993 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:28,993 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:28,993 INFO L82 PathProgramCache]: Analyzing trace with hash -833394239, now seen corresponding path program 1 times [2019-11-28 00:28:28,993 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:28,994 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [268190715] [2019-11-28 00:28:28,994 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:28,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:29,014 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2019-11-28 00:28:29,014 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [268190715] [2019-11-28 00:28:29,014 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:29,015 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:29,015 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1703161413] [2019-11-28 00:28:29,015 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:29,015 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:29,015 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:29,016 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:29,016 INFO L87 Difference]: Start difference. First operand 8322 states and 12796 transitions. Second operand 3 states. [2019-11-28 00:28:29,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:29,614 INFO L93 Difference]: Finished difference Result 24654 states and 37995 transitions. [2019-11-28 00:28:29,614 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:29,614 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 55 [2019-11-28 00:28:29,615 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:29,669 INFO L225 Difference]: With dead ends: 24654 [2019-11-28 00:28:29,669 INFO L226 Difference]: Without dead ends: 16335 [2019-11-28 00:28:29,693 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:29,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16335 states. [2019-11-28 00:28:30,458 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16335 to 16203. [2019-11-28 00:28:30,459 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16203 states. [2019-11-28 00:28:30,493 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16203 states to 16203 states and 25040 transitions. [2019-11-28 00:28:30,494 INFO L78 Accepts]: Start accepts. Automaton has 16203 states and 25040 transitions. Word has length 55 [2019-11-28 00:28:30,494 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:30,494 INFO L462 AbstractCegarLoop]: Abstraction has 16203 states and 25040 transitions. [2019-11-28 00:28:30,494 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:30,494 INFO L276 IsEmpty]: Start isEmpty. Operand 16203 states and 25040 transitions. [2019-11-28 00:28:30,505 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2019-11-28 00:28:30,506 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:30,506 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:30,506 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:30,507 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:30,507 INFO L82 PathProgramCache]: Analyzing trace with hash -539805076, now seen corresponding path program 1 times [2019-11-28 00:28:30,507 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:30,508 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [323987218] [2019-11-28 00:28:30,508 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:30,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:30,546 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:30,546 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [323987218] [2019-11-28 00:28:30,547 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:30,547 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:30,547 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1267528193] [2019-11-28 00:28:30,548 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:30,548 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:30,548 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:30,548 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:30,549 INFO L87 Difference]: Start difference. First operand 16203 states and 25040 transitions. Second operand 3 states. [2019-11-28 00:28:31,347 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:31,348 INFO L93 Difference]: Finished difference Result 33061 states and 51038 transitions. [2019-11-28 00:28:31,348 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:31,348 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 86 [2019-11-28 00:28:31,349 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:31,398 INFO L225 Difference]: With dead ends: 33061 [2019-11-28 00:28:31,399 INFO L226 Difference]: Without dead ends: 16887 [2019-11-28 00:28:31,430 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:31,453 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16887 states. [2019-11-28 00:28:32,079 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16887 to 16823. [2019-11-28 00:28:32,080 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16823 states. [2019-11-28 00:28:32,110 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16823 states to 16823 states and 25342 transitions. [2019-11-28 00:28:32,110 INFO L78 Accepts]: Start accepts. Automaton has 16823 states and 25342 transitions. Word has length 86 [2019-11-28 00:28:32,111 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:32,111 INFO L462 AbstractCegarLoop]: Abstraction has 16823 states and 25342 transitions. [2019-11-28 00:28:32,111 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:32,111 INFO L276 IsEmpty]: Start isEmpty. Operand 16823 states and 25342 transitions. [2019-11-28 00:28:32,123 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2019-11-28 00:28:32,123 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:32,124 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:32,124 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:32,124 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:32,125 INFO L82 PathProgramCache]: Analyzing trace with hash -1404681213, now seen corresponding path program 1 times [2019-11-28 00:28:32,125 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:32,125 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1390460483] [2019-11-28 00:28:32,125 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:32,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:32,167 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-11-28 00:28:32,167 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1390460483] [2019-11-28 00:28:32,168 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:32,168 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 00:28:32,168 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2129445488] [2019-11-28 00:28:32,169 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 00:28:32,169 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:32,169 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 00:28:32,170 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 00:28:32,170 INFO L87 Difference]: Start difference. First operand 16823 states and 25342 transitions. Second operand 4 states. [2019-11-28 00:28:32,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:32,798 INFO L93 Difference]: Finished difference Result 27813 states and 42042 transitions. [2019-11-28 00:28:32,799 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-28 00:28:32,799 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 87 [2019-11-28 00:28:32,799 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:32,837 INFO L225 Difference]: With dead ends: 27813 [2019-11-28 00:28:32,837 INFO L226 Difference]: Without dead ends: 15935 [2019-11-28 00:28:32,854 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 00:28:32,869 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15935 states. [2019-11-28 00:28:33,799 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15935 to 15811. [2019-11-28 00:28:33,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15811 states. [2019-11-28 00:28:33,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15811 states to 15811 states and 23636 transitions. [2019-11-28 00:28:33,820 INFO L78 Accepts]: Start accepts. Automaton has 15811 states and 23636 transitions. Word has length 87 [2019-11-28 00:28:33,820 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:33,821 INFO L462 AbstractCegarLoop]: Abstraction has 15811 states and 23636 transitions. [2019-11-28 00:28:33,821 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 00:28:33,821 INFO L276 IsEmpty]: Start isEmpty. Operand 15811 states and 23636 transitions. [2019-11-28 00:28:33,830 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2019-11-28 00:28:33,830 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:33,830 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:33,831 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:33,831 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:33,831 INFO L82 PathProgramCache]: Analyzing trace with hash 1520792899, now seen corresponding path program 1 times [2019-11-28 00:28:33,831 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:33,832 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [116653905] [2019-11-28 00:28:33,832 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:33,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:33,862 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:33,863 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [116653905] [2019-11-28 00:28:33,863 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:33,863 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:33,863 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1573863881] [2019-11-28 00:28:33,864 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:33,864 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:33,864 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:33,865 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:33,865 INFO L87 Difference]: Start difference. First operand 15811 states and 23636 transitions. Second operand 3 states. [2019-11-28 00:28:34,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:34,349 INFO L93 Difference]: Finished difference Result 32391 states and 48370 transitions. [2019-11-28 00:28:34,350 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:34,350 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 87 [2019-11-28 00:28:34,350 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:34,383 INFO L225 Difference]: With dead ends: 32391 [2019-11-28 00:28:34,383 INFO L226 Difference]: Without dead ends: 16621 [2019-11-28 00:28:34,400 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:34,415 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16621 states. [2019-11-28 00:28:35,196 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16621 to 16541. [2019-11-28 00:28:35,197 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16541 states. [2019-11-28 00:28:35,219 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16541 states to 16541 states and 24008 transitions. [2019-11-28 00:28:35,220 INFO L78 Accepts]: Start accepts. Automaton has 16541 states and 24008 transitions. Word has length 87 [2019-11-28 00:28:35,220 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:35,220 INFO L462 AbstractCegarLoop]: Abstraction has 16541 states and 24008 transitions. [2019-11-28 00:28:35,220 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:35,220 INFO L276 IsEmpty]: Start isEmpty. Operand 16541 states and 24008 transitions. [2019-11-28 00:28:35,228 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2019-11-28 00:28:35,228 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:35,229 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:35,229 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:35,229 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:35,229 INFO L82 PathProgramCache]: Analyzing trace with hash -1973365524, now seen corresponding path program 1 times [2019-11-28 00:28:35,230 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:35,230 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [168056351] [2019-11-28 00:28:35,230 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:35,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:35,276 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:35,277 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [168056351] [2019-11-28 00:28:35,277 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:35,277 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:35,278 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [626914467] [2019-11-28 00:28:35,278 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:35,278 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:35,279 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:35,279 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:35,279 INFO L87 Difference]: Start difference. First operand 16541 states and 24008 transitions. Second operand 3 states. [2019-11-28 00:28:35,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:35,720 INFO L93 Difference]: Finished difference Result 33498 states and 48738 transitions. [2019-11-28 00:28:35,721 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:35,721 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 88 [2019-11-28 00:28:35,721 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:35,746 INFO L225 Difference]: With dead ends: 33498 [2019-11-28 00:28:35,746 INFO L226 Difference]: Without dead ends: 17018 [2019-11-28 00:28:35,766 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:35,782 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17018 states. [2019-11-28 00:28:36,208 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17018 to 13513. [2019-11-28 00:28:36,208 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13513 states. [2019-11-28 00:28:36,228 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13513 states to 13513 states and 18922 transitions. [2019-11-28 00:28:36,228 INFO L78 Accepts]: Start accepts. Automaton has 13513 states and 18922 transitions. Word has length 88 [2019-11-28 00:28:36,229 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:36,229 INFO L462 AbstractCegarLoop]: Abstraction has 13513 states and 18922 transitions. [2019-11-28 00:28:36,229 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:36,229 INFO L276 IsEmpty]: Start isEmpty. Operand 13513 states and 18922 transitions. [2019-11-28 00:28:36,238 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2019-11-28 00:28:36,238 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:36,239 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:36,239 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:36,239 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:36,240 INFO L82 PathProgramCache]: Analyzing trace with hash 663253701, now seen corresponding path program 1 times [2019-11-28 00:28:36,240 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:36,240 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1526522096] [2019-11-28 00:28:36,241 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:36,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:36,279 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-11-28 00:28:36,280 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1526522096] [2019-11-28 00:28:36,280 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:36,280 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:36,280 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1187423125] [2019-11-28 00:28:36,281 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:36,281 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:36,282 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:36,282 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:36,282 INFO L87 Difference]: Start difference. First operand 13513 states and 18922 transitions. Second operand 3 states. [2019-11-28 00:28:37,124 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:37,125 INFO L93 Difference]: Finished difference Result 24045 states and 33699 transitions. [2019-11-28 00:28:37,125 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:37,125 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 89 [2019-11-28 00:28:37,125 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:37,141 INFO L225 Difference]: With dead ends: 24045 [2019-11-28 00:28:37,141 INFO L226 Difference]: Without dead ends: 15655 [2019-11-28 00:28:37,151 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:37,162 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15655 states. [2019-11-28 00:28:37,561 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15655 to 15175. [2019-11-28 00:28:37,561 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15175 states. [2019-11-28 00:28:37,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15175 states to 15175 states and 20753 transitions. [2019-11-28 00:28:37,579 INFO L78 Accepts]: Start accepts. Automaton has 15175 states and 20753 transitions. Word has length 89 [2019-11-28 00:28:37,580 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:37,580 INFO L462 AbstractCegarLoop]: Abstraction has 15175 states and 20753 transitions. [2019-11-28 00:28:37,580 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:37,580 INFO L276 IsEmpty]: Start isEmpty. Operand 15175 states and 20753 transitions. [2019-11-28 00:28:37,594 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2019-11-28 00:28:37,594 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:37,594 INFO L410 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:37,594 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:37,595 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:37,595 INFO L82 PathProgramCache]: Analyzing trace with hash 1690650567, now seen corresponding path program 1 times [2019-11-28 00:28:37,595 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:37,595 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2077179104] [2019-11-28 00:28:37,595 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:37,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:37,627 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2019-11-28 00:28:37,627 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2077179104] [2019-11-28 00:28:37,628 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:37,628 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:37,628 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [918192272] [2019-11-28 00:28:37,628 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:37,628 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:37,629 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:37,629 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:37,629 INFO L87 Difference]: Start difference. First operand 15175 states and 20753 transitions. Second operand 3 states. [2019-11-28 00:28:38,031 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:38,031 INFO L93 Difference]: Finished difference Result 29588 states and 40424 transitions. [2019-11-28 00:28:38,031 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:38,031 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 116 [2019-11-28 00:28:38,032 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:38,047 INFO L225 Difference]: With dead ends: 29588 [2019-11-28 00:28:38,047 INFO L226 Difference]: Without dead ends: 15105 [2019-11-28 00:28:38,062 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:38,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15105 states. [2019-11-28 00:28:38,828 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15105 to 15105. [2019-11-28 00:28:38,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15105 states. [2019-11-28 00:28:38,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15105 states to 15105 states and 20599 transitions. [2019-11-28 00:28:38,845 INFO L78 Accepts]: Start accepts. Automaton has 15105 states and 20599 transitions. Word has length 116 [2019-11-28 00:28:38,845 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:38,845 INFO L462 AbstractCegarLoop]: Abstraction has 15105 states and 20599 transitions. [2019-11-28 00:28:38,846 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:38,846 INFO L276 IsEmpty]: Start isEmpty. Operand 15105 states and 20599 transitions. [2019-11-28 00:28:38,860 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2019-11-28 00:28:38,860 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:38,860 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:38,861 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:38,861 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:38,861 INFO L82 PathProgramCache]: Analyzing trace with hash -1184080698, now seen corresponding path program 1 times [2019-11-28 00:28:38,861 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:38,861 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [95696525] [2019-11-28 00:28:38,861 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:38,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:38,891 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2019-11-28 00:28:38,891 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [95696525] [2019-11-28 00:28:38,891 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:38,892 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:38,892 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1655867600] [2019-11-28 00:28:38,892 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:38,892 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:38,893 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:38,893 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:38,893 INFO L87 Difference]: Start difference. First operand 15105 states and 20599 transitions. Second operand 3 states. [2019-11-28 00:28:39,250 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:39,251 INFO L93 Difference]: Finished difference Result 25662 states and 34928 transitions. [2019-11-28 00:28:39,251 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:39,251 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 127 [2019-11-28 00:28:39,251 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:39,262 INFO L225 Difference]: With dead ends: 25662 [2019-11-28 00:28:39,262 INFO L226 Difference]: Without dead ends: 10614 [2019-11-28 00:28:39,272 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:39,279 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10614 states. [2019-11-28 00:28:39,514 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10614 to 8646. [2019-11-28 00:28:39,514 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8646 states. [2019-11-28 00:28:39,524 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8646 states to 8646 states and 11323 transitions. [2019-11-28 00:28:39,524 INFO L78 Accepts]: Start accepts. Automaton has 8646 states and 11323 transitions. Word has length 127 [2019-11-28 00:28:39,524 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:39,524 INFO L462 AbstractCegarLoop]: Abstraction has 8646 states and 11323 transitions. [2019-11-28 00:28:39,524 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:39,524 INFO L276 IsEmpty]: Start isEmpty. Operand 8646 states and 11323 transitions. [2019-11-28 00:28:39,534 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2019-11-28 00:28:39,534 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:39,535 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:39,535 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:39,535 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:39,535 INFO L82 PathProgramCache]: Analyzing trace with hash 762576065, now seen corresponding path program 1 times [2019-11-28 00:28:39,535 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:39,535 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [41560476] [2019-11-28 00:28:39,535 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:39,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:39,572 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 43 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2019-11-28 00:28:39,572 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [41560476] [2019-11-28 00:28:39,573 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:39,573 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:39,573 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1533799023] [2019-11-28 00:28:39,573 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:39,574 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:39,574 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:39,574 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:39,574 INFO L87 Difference]: Start difference. First operand 8646 states and 11323 transitions. Second operand 3 states. [2019-11-28 00:28:39,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:39,812 INFO L93 Difference]: Finished difference Result 14253 states and 18666 transitions. [2019-11-28 00:28:39,812 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:39,812 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 128 [2019-11-28 00:28:39,813 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:39,819 INFO L225 Difference]: With dead ends: 14253 [2019-11-28 00:28:39,819 INFO L226 Difference]: Without dead ends: 6761 [2019-11-28 00:28:39,824 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:39,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6761 states. [2019-11-28 00:28:40,020 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6761 to 6175. [2019-11-28 00:28:40,020 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6175 states. [2019-11-28 00:28:40,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6175 states to 6175 states and 7922 transitions. [2019-11-28 00:28:40,025 INFO L78 Accepts]: Start accepts. Automaton has 6175 states and 7922 transitions. Word has length 128 [2019-11-28 00:28:40,026 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:40,026 INFO L462 AbstractCegarLoop]: Abstraction has 6175 states and 7922 transitions. [2019-11-28 00:28:40,026 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:40,026 INFO L276 IsEmpty]: Start isEmpty. Operand 6175 states and 7922 transitions. [2019-11-28 00:28:40,030 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-11-28 00:28:40,031 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:40,031 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:40,031 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:40,031 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:40,031 INFO L82 PathProgramCache]: Analyzing trace with hash 843157933, now seen corresponding path program 1 times [2019-11-28 00:28:40,032 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:40,032 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1140046789] [2019-11-28 00:28:40,032 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:40,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:40,068 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2019-11-28 00:28:40,068 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1140046789] [2019-11-28 00:28:40,068 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:40,068 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:40,069 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1868506491] [2019-11-28 00:28:40,069 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:40,069 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:40,069 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:40,070 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:40,070 INFO L87 Difference]: Start difference. First operand 6175 states and 7922 transitions. Second operand 3 states. [2019-11-28 00:28:40,391 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:40,392 INFO L93 Difference]: Finished difference Result 11963 states and 15332 transitions. [2019-11-28 00:28:40,392 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:40,392 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 134 [2019-11-28 00:28:40,393 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:40,401 INFO L225 Difference]: With dead ends: 11963 [2019-11-28 00:28:40,402 INFO L226 Difference]: Without dead ends: 6174 [2019-11-28 00:28:40,407 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:40,413 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6174 states. [2019-11-28 00:28:40,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6174 to 6134. [2019-11-28 00:28:40,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6134 states. [2019-11-28 00:28:40,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6134 states to 6134 states and 7839 transitions. [2019-11-28 00:28:40,706 INFO L78 Accepts]: Start accepts. Automaton has 6134 states and 7839 transitions. Word has length 134 [2019-11-28 00:28:40,706 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:40,706 INFO L462 AbstractCegarLoop]: Abstraction has 6134 states and 7839 transitions. [2019-11-28 00:28:40,706 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:40,706 INFO L276 IsEmpty]: Start isEmpty. Operand 6134 states and 7839 transitions. [2019-11-28 00:28:40,712 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-11-28 00:28:40,712 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:40,712 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:40,712 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:40,713 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:40,713 INFO L82 PathProgramCache]: Analyzing trace with hash 713131341, now seen corresponding path program 1 times [2019-11-28 00:28:40,713 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:40,713 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [405258590] [2019-11-28 00:28:40,713 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:40,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:40,775 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2019-11-28 00:28:40,776 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [405258590] [2019-11-28 00:28:40,776 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:40,776 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:40,776 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [369934047] [2019-11-28 00:28:40,777 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:40,777 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:40,778 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:40,778 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:40,778 INFO L87 Difference]: Start difference. First operand 6134 states and 7839 transitions. Second operand 3 states. [2019-11-28 00:28:41,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:41,301 INFO L93 Difference]: Finished difference Result 11902 states and 15193 transitions. [2019-11-28 00:28:41,302 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:41,302 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 134 [2019-11-28 00:28:41,302 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:41,310 INFO L225 Difference]: With dead ends: 11902 [2019-11-28 00:28:41,311 INFO L226 Difference]: Without dead ends: 6144 [2019-11-28 00:28:41,317 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:41,323 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6144 states. [2019-11-28 00:28:41,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6144 to 6104. [2019-11-28 00:28:41,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6104 states. [2019-11-28 00:28:41,935 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6104 states to 6104 states and 7768 transitions. [2019-11-28 00:28:41,935 INFO L78 Accepts]: Start accepts. Automaton has 6104 states and 7768 transitions. Word has length 134 [2019-11-28 00:28:41,935 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:41,935 INFO L462 AbstractCegarLoop]: Abstraction has 6104 states and 7768 transitions. [2019-11-28 00:28:41,935 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:41,935 INFO L276 IsEmpty]: Start isEmpty. Operand 6104 states and 7768 transitions. [2019-11-28 00:28:41,940 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2019-11-28 00:28:41,941 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:41,941 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:41,941 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:41,941 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:41,942 INFO L82 PathProgramCache]: Analyzing trace with hash -57826629, now seen corresponding path program 1 times [2019-11-28 00:28:41,942 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:41,942 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1129177004] [2019-11-28 00:28:41,942 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:41,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:41,987 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 46 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2019-11-28 00:28:41,987 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1129177004] [2019-11-28 00:28:41,987 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:41,988 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:41,988 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [289123071] [2019-11-28 00:28:41,988 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:41,989 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:41,989 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:41,989 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:41,989 INFO L87 Difference]: Start difference. First operand 6104 states and 7768 transitions. Second operand 3 states. [2019-11-28 00:28:42,282 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:42,282 INFO L93 Difference]: Finished difference Result 10914 states and 13936 transitions. [2019-11-28 00:28:42,283 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:42,283 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 137 [2019-11-28 00:28:42,283 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:42,290 INFO L225 Difference]: With dead ends: 10914 [2019-11-28 00:28:42,290 INFO L226 Difference]: Without dead ends: 5174 [2019-11-28 00:28:42,299 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:42,304 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5174 states. [2019-11-28 00:28:42,558 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5174 to 5102. [2019-11-28 00:28:42,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5102 states. [2019-11-28 00:28:42,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5102 states to 5102 states and 6390 transitions. [2019-11-28 00:28:42,567 INFO L78 Accepts]: Start accepts. Automaton has 5102 states and 6390 transitions. Word has length 137 [2019-11-28 00:28:42,568 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:42,568 INFO L462 AbstractCegarLoop]: Abstraction has 5102 states and 6390 transitions. [2019-11-28 00:28:42,568 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:42,568 INFO L276 IsEmpty]: Start isEmpty. Operand 5102 states and 6390 transitions. [2019-11-28 00:28:42,573 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2019-11-28 00:28:42,573 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:42,573 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:42,574 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:42,574 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:42,574 INFO L82 PathProgramCache]: Analyzing trace with hash -76782736, now seen corresponding path program 1 times [2019-11-28 00:28:42,575 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:42,575 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [94731152] [2019-11-28 00:28:42,575 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:42,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:42,628 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 45 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2019-11-28 00:28:42,629 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [94731152] [2019-11-28 00:28:42,630 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:42,630 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:42,632 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1415059774] [2019-11-28 00:28:42,632 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:42,632 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:42,633 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:42,633 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:42,633 INFO L87 Difference]: Start difference. First operand 5102 states and 6390 transitions. Second operand 3 states. [2019-11-28 00:28:42,803 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:42,803 INFO L93 Difference]: Finished difference Result 9187 states and 11545 transitions. [2019-11-28 00:28:42,804 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:42,804 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 137 [2019-11-28 00:28:42,804 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:42,807 INFO L225 Difference]: With dead ends: 9187 [2019-11-28 00:28:42,808 INFO L226 Difference]: Without dead ends: 4126 [2019-11-28 00:28:42,811 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:42,813 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4126 states. [2019-11-28 00:28:42,918 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4126 to 4106. [2019-11-28 00:28:42,918 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4106 states. [2019-11-28 00:28:42,923 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4106 states to 4106 states and 5057 transitions. [2019-11-28 00:28:42,923 INFO L78 Accepts]: Start accepts. Automaton has 4106 states and 5057 transitions. Word has length 137 [2019-11-28 00:28:42,923 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:42,924 INFO L462 AbstractCegarLoop]: Abstraction has 4106 states and 5057 transitions. [2019-11-28 00:28:42,924 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:42,924 INFO L276 IsEmpty]: Start isEmpty. Operand 4106 states and 5057 transitions. [2019-11-28 00:28:42,927 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 171 [2019-11-28 00:28:42,927 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:42,927 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:42,928 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:42,928 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:42,928 INFO L82 PathProgramCache]: Analyzing trace with hash -691267920, now seen corresponding path program 1 times [2019-11-28 00:28:42,928 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:42,928 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [101631140] [2019-11-28 00:28:42,929 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:42,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:42,975 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 75 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2019-11-28 00:28:42,976 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [101631140] [2019-11-28 00:28:42,976 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:42,976 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:42,976 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [868158956] [2019-11-28 00:28:42,976 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:42,977 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:42,977 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:42,977 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:42,977 INFO L87 Difference]: Start difference. First operand 4106 states and 5057 transitions. Second operand 3 states. [2019-11-28 00:28:43,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:43,110 INFO L93 Difference]: Finished difference Result 7627 states and 9455 transitions. [2019-11-28 00:28:43,110 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:43,110 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 170 [2019-11-28 00:28:43,111 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:43,114 INFO L225 Difference]: With dead ends: 7627 [2019-11-28 00:28:43,114 INFO L226 Difference]: Without dead ends: 3797 [2019-11-28 00:28:43,117 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:43,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3797 states. [2019-11-28 00:28:43,219 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3797 to 3568. [2019-11-28 00:28:43,220 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3568 states. [2019-11-28 00:28:43,224 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3568 states to 3568 states and 4348 transitions. [2019-11-28 00:28:43,224 INFO L78 Accepts]: Start accepts. Automaton has 3568 states and 4348 transitions. Word has length 170 [2019-11-28 00:28:43,224 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:43,224 INFO L462 AbstractCegarLoop]: Abstraction has 3568 states and 4348 transitions. [2019-11-28 00:28:43,224 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:43,224 INFO L276 IsEmpty]: Start isEmpty. Operand 3568 states and 4348 transitions. [2019-11-28 00:28:43,227 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 178 [2019-11-28 00:28:43,227 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:43,228 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:43,228 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:43,228 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:43,228 INFO L82 PathProgramCache]: Analyzing trace with hash 307077909, now seen corresponding path program 1 times [2019-11-28 00:28:43,228 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:43,228 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [366999162] [2019-11-28 00:28:43,229 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:43,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:43,277 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 82 proven. 0 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2019-11-28 00:28:43,277 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [366999162] [2019-11-28 00:28:43,277 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:43,277 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:43,278 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1258233442] [2019-11-28 00:28:43,278 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:43,278 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:43,279 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:43,279 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:43,279 INFO L87 Difference]: Start difference. First operand 3568 states and 4348 transitions. Second operand 3 states. [2019-11-28 00:28:43,453 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:43,454 INFO L93 Difference]: Finished difference Result 8940 states and 10936 transitions. [2019-11-28 00:28:43,454 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:43,454 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 177 [2019-11-28 00:28:43,454 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:43,459 INFO L225 Difference]: With dead ends: 8940 [2019-11-28 00:28:43,460 INFO L226 Difference]: Without dead ends: 5648 [2019-11-28 00:28:43,463 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:43,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5648 states. [2019-11-28 00:28:43,614 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5648 to 5422. [2019-11-28 00:28:43,615 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5422 states. [2019-11-28 00:28:43,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5422 states to 5422 states and 6526 transitions. [2019-11-28 00:28:43,620 INFO L78 Accepts]: Start accepts. Automaton has 5422 states and 6526 transitions. Word has length 177 [2019-11-28 00:28:43,621 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:43,621 INFO L462 AbstractCegarLoop]: Abstraction has 5422 states and 6526 transitions. [2019-11-28 00:28:43,621 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:43,621 INFO L276 IsEmpty]: Start isEmpty. Operand 5422 states and 6526 transitions. [2019-11-28 00:28:43,624 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 181 [2019-11-28 00:28:43,624 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:43,625 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:43,625 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:43,625 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:43,625 INFO L82 PathProgramCache]: Analyzing trace with hash -2095538940, now seen corresponding path program 1 times [2019-11-28 00:28:43,625 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:43,625 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1355041205] [2019-11-28 00:28:43,625 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:43,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:43,665 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 79 proven. 0 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2019-11-28 00:28:43,665 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1355041205] [2019-11-28 00:28:43,666 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:43,666 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:43,666 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [606362726] [2019-11-28 00:28:43,666 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:43,667 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:43,667 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:43,667 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:43,667 INFO L87 Difference]: Start difference. First operand 5422 states and 6526 transitions. Second operand 3 states. [2019-11-28 00:28:43,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:43,875 INFO L93 Difference]: Finished difference Result 8854 states and 10720 transitions. [2019-11-28 00:28:43,875 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:43,875 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 180 [2019-11-28 00:28:43,875 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:43,880 INFO L225 Difference]: With dead ends: 8854 [2019-11-28 00:28:43,880 INFO L226 Difference]: Without dead ends: 3708 [2019-11-28 00:28:43,885 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:43,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3708 states. [2019-11-28 00:28:43,997 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3708 to 3100. [2019-11-28 00:28:43,997 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3100 states. [2019-11-28 00:28:44,000 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3100 states to 3100 states and 3693 transitions. [2019-11-28 00:28:44,001 INFO L78 Accepts]: Start accepts. Automaton has 3100 states and 3693 transitions. Word has length 180 [2019-11-28 00:28:44,001 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:44,001 INFO L462 AbstractCegarLoop]: Abstraction has 3100 states and 3693 transitions. [2019-11-28 00:28:44,001 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:44,001 INFO L276 IsEmpty]: Start isEmpty. Operand 3100 states and 3693 transitions. [2019-11-28 00:28:44,003 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 181 [2019-11-28 00:28:44,003 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:44,003 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:44,004 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:44,004 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:44,004 INFO L82 PathProgramCache]: Analyzing trace with hash -1037700862, now seen corresponding path program 1 times [2019-11-28 00:28:44,004 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:44,004 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [284457867] [2019-11-28 00:28:44,004 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:44,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:44,060 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 91 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-11-28 00:28:44,060 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [284457867] [2019-11-28 00:28:44,060 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:44,060 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 00:28:44,061 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [462411321] [2019-11-28 00:28:44,061 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 00:28:44,061 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:44,061 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 00:28:44,062 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 00:28:44,062 INFO L87 Difference]: Start difference. First operand 3100 states and 3693 transitions. Second operand 4 states. [2019-11-28 00:28:44,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:44,204 INFO L93 Difference]: Finished difference Result 4701 states and 5585 transitions. [2019-11-28 00:28:44,205 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 00:28:44,205 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 180 [2019-11-28 00:28:44,205 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:44,208 INFO L225 Difference]: With dead ends: 4701 [2019-11-28 00:28:44,208 INFO L226 Difference]: Without dead ends: 1877 [2019-11-28 00:28:44,210 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 00:28:44,212 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1877 states. [2019-11-28 00:28:44,304 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1877 to 1590. [2019-11-28 00:28:44,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1590 states. [2019-11-28 00:28:44,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1590 states to 1590 states and 1853 transitions. [2019-11-28 00:28:44,307 INFO L78 Accepts]: Start accepts. Automaton has 1590 states and 1853 transitions. Word has length 180 [2019-11-28 00:28:44,307 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:44,307 INFO L462 AbstractCegarLoop]: Abstraction has 1590 states and 1853 transitions. [2019-11-28 00:28:44,307 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 00:28:44,308 INFO L276 IsEmpty]: Start isEmpty. Operand 1590 states and 1853 transitions. [2019-11-28 00:28:44,309 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 185 [2019-11-28 00:28:44,309 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:44,310 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:44,310 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:44,310 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:44,310 INFO L82 PathProgramCache]: Analyzing trace with hash 1351947795, now seen corresponding path program 1 times [2019-11-28 00:28:44,311 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:44,311 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [300255161] [2019-11-28 00:28:44,311 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:44,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:44,391 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 100 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-28 00:28:44,391 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [300255161] [2019-11-28 00:28:44,391 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:44,391 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:44,392 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1048349070] [2019-11-28 00:28:44,392 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:44,392 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:44,392 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:44,392 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:44,393 INFO L87 Difference]: Start difference. First operand 1590 states and 1853 transitions. Second operand 3 states. [2019-11-28 00:28:44,640 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:44,640 INFO L93 Difference]: Finished difference Result 4058 states and 4759 transitions. [2019-11-28 00:28:44,640 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:44,641 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 184 [2019-11-28 00:28:44,641 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:44,644 INFO L225 Difference]: With dead ends: 4058 [2019-11-28 00:28:44,644 INFO L226 Difference]: Without dead ends: 2438 [2019-11-28 00:28:44,647 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:44,649 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2438 states. [2019-11-28 00:28:45,142 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2438 to 2426. [2019-11-28 00:28:45,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2426 states. [2019-11-28 00:28:45,146 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2426 states to 2426 states and 2829 transitions. [2019-11-28 00:28:45,146 INFO L78 Accepts]: Start accepts. Automaton has 2426 states and 2829 transitions. Word has length 184 [2019-11-28 00:28:45,146 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:45,146 INFO L462 AbstractCegarLoop]: Abstraction has 2426 states and 2829 transitions. [2019-11-28 00:28:45,146 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:45,147 INFO L276 IsEmpty]: Start isEmpty. Operand 2426 states and 2829 transitions. [2019-11-28 00:28:45,148 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 185 [2019-11-28 00:28:45,148 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:45,149 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:45,149 INFO L410 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:45,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:45,150 INFO L82 PathProgramCache]: Analyzing trace with hash 1047126543, now seen corresponding path program 1 times [2019-11-28 00:28:45,150 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:45,150 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1120069584] [2019-11-28 00:28:45,150 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:45,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:45,209 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 93 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-11-28 00:28:45,210 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1120069584] [2019-11-28 00:28:45,210 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:45,210 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:45,210 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1381980248] [2019-11-28 00:28:45,211 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:45,211 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:45,211 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:45,211 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:45,211 INFO L87 Difference]: Start difference. First operand 2426 states and 2829 transitions. Second operand 3 states. [2019-11-28 00:28:45,308 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:45,308 INFO L93 Difference]: Finished difference Result 3380 states and 3910 transitions. [2019-11-28 00:28:45,309 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:45,309 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 184 [2019-11-28 00:28:45,309 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:45,311 INFO L225 Difference]: With dead ends: 3380 [2019-11-28 00:28:45,311 INFO L226 Difference]: Without dead ends: 1220 [2019-11-28 00:28:45,314 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:45,316 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1220 states. [2019-11-28 00:28:45,411 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1220 to 1198. [2019-11-28 00:28:45,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1198 states. [2019-11-28 00:28:45,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1198 states to 1198 states and 1326 transitions. [2019-11-28 00:28:45,414 INFO L78 Accepts]: Start accepts. Automaton has 1198 states and 1326 transitions. Word has length 184 [2019-11-28 00:28:45,415 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:45,415 INFO L462 AbstractCegarLoop]: Abstraction has 1198 states and 1326 transitions. [2019-11-28 00:28:45,415 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:45,415 INFO L276 IsEmpty]: Start isEmpty. Operand 1198 states and 1326 transitions. [2019-11-28 00:28:45,417 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 186 [2019-11-28 00:28:45,417 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:45,418 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:45,418 INFO L410 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:45,418 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:45,419 INFO L82 PathProgramCache]: Analyzing trace with hash -1330592792, now seen corresponding path program 1 times [2019-11-28 00:28:45,419 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:45,419 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [935952832] [2019-11-28 00:28:45,420 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:45,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:45,511 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 107 trivial. 0 not checked. [2019-11-28 00:28:45,511 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [935952832] [2019-11-28 00:28:45,512 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:45,512 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:45,512 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1214044683] [2019-11-28 00:28:45,512 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:45,513 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:45,514 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:45,514 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:45,514 INFO L87 Difference]: Start difference. First operand 1198 states and 1326 transitions. Second operand 3 states. [2019-11-28 00:28:45,675 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:45,675 INFO L93 Difference]: Finished difference Result 1202 states and 1331 transitions. [2019-11-28 00:28:45,676 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:45,676 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 185 [2019-11-28 00:28:45,677 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:45,678 INFO L225 Difference]: With dead ends: 1202 [2019-11-28 00:28:45,678 INFO L226 Difference]: Without dead ends: 1200 [2019-11-28 00:28:45,680 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:45,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1200 states. [2019-11-28 00:28:45,800 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1200 to 1200. [2019-11-28 00:28:45,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1200 states. [2019-11-28 00:28:45,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1200 states to 1200 states and 1328 transitions. [2019-11-28 00:28:45,803 INFO L78 Accepts]: Start accepts. Automaton has 1200 states and 1328 transitions. Word has length 185 [2019-11-28 00:28:45,803 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:45,804 INFO L462 AbstractCegarLoop]: Abstraction has 1200 states and 1328 transitions. [2019-11-28 00:28:45,804 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:45,804 INFO L276 IsEmpty]: Start isEmpty. Operand 1200 states and 1328 transitions. [2019-11-28 00:28:45,806 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 186 [2019-11-28 00:28:45,806 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:45,807 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:45,807 INFO L410 AbstractCegarLoop]: === Iteration 38 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:45,807 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:45,807 INFO L82 PathProgramCache]: Analyzing trace with hash -1330591190, now seen corresponding path program 1 times [2019-11-28 00:28:45,808 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:45,808 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [145196542] [2019-11-28 00:28:45,808 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:45,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:46,070 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 81 proven. 15 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2019-11-28 00:28:46,071 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [145196542] [2019-11-28 00:28:46,071 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [534308072] [2019-11-28 00:28:46,071 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-28 00:28:46,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:46,177 INFO L255 TraceCheckSpWp]: Trace formula consists of 499 conjuncts, 19 conjunts are in the unsatisfiable core [2019-11-28 00:28:46,204 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2019-11-28 00:28:46,341 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 81 proven. 15 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2019-11-28 00:28:46,341 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-28 00:28:46,342 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 10 [2019-11-28 00:28:46,342 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [984482976] [2019-11-28 00:28:46,343 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-11-28 00:28:46,343 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:46,343 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-11-28 00:28:46,343 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2019-11-28 00:28:46,343 INFO L87 Difference]: Start difference. First operand 1200 states and 1328 transitions. Second operand 10 states. [2019-11-28 00:28:46,994 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:46,994 INFO L93 Difference]: Finished difference Result 2336 states and 2602 transitions. [2019-11-28 00:28:46,994 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-11-28 00:28:46,994 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 185 [2019-11-28 00:28:46,995 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:46,999 INFO L225 Difference]: With dead ends: 2336 [2019-11-28 00:28:47,000 INFO L226 Difference]: Without dead ends: 1732 [2019-11-28 00:28:47,001 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 206 GetRequests, 188 SyntacticMatches, 2 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=64, Invalid=242, Unknown=0, NotChecked=0, Total=306 [2019-11-28 00:28:47,008 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1732 states. [2019-11-28 00:28:47,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1732 to 1546. [2019-11-28 00:28:47,253 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1546 states. [2019-11-28 00:28:47,256 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1546 states to 1546 states and 1714 transitions. [2019-11-28 00:28:47,256 INFO L78 Accepts]: Start accepts. Automaton has 1546 states and 1714 transitions. Word has length 185 [2019-11-28 00:28:47,256 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:47,257 INFO L462 AbstractCegarLoop]: Abstraction has 1546 states and 1714 transitions. [2019-11-28 00:28:47,257 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-11-28 00:28:47,257 INFO L276 IsEmpty]: Start isEmpty. Operand 1546 states and 1714 transitions. [2019-11-28 00:28:47,261 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 187 [2019-11-28 00:28:47,261 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:47,263 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:47,475 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-28 00:28:47,476 INFO L410 AbstractCegarLoop]: === Iteration 39 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:47,476 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:47,477 INFO L82 PathProgramCache]: Analyzing trace with hash 1701344696, now seen corresponding path program 1 times [2019-11-28 00:28:47,477 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:47,477 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [966287273] [2019-11-28 00:28:47,477 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:47,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 00:28:47,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 00:28:47,659 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-28 00:28:47,660 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-28 00:28:47,980 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 12:28:47 BoogieIcfgContainer [2019-11-28 00:28:47,980 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-28 00:28:47,981 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-28 00:28:47,981 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-28 00:28:47,982 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-28 00:28:47,983 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 12:28:21" (3/4) ... [2019-11-28 00:28:47,986 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-28 00:28:48,256 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2019-11-28 00:28:48,256 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-28 00:28:48,259 INFO L168 Benchmark]: Toolchain (without parser) took 27991.23 ms. Allocated memory was 1.0 GB in the beginning and 3.8 GB in the end (delta: 2.8 GB). Free memory was 960.4 MB in the beginning and 2.6 GB in the end (delta: -1.6 GB). Peak memory consumption was 1.2 GB. Max. memory is 11.5 GB. [2019-11-28 00:28:48,260 INFO L168 Benchmark]: CDTParser took 0.34 ms. Allocated memory is still 1.0 GB. Free memory is still 987.2 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 00:28:48,261 INFO L168 Benchmark]: CACSL2BoogieTranslator took 485.79 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 119.0 MB). Free memory was 960.4 MB in the beginning and 1.1 GB in the end (delta: -148.2 MB). Peak memory consumption was 27.2 MB. Max. memory is 11.5 GB. [2019-11-28 00:28:48,261 INFO L168 Benchmark]: Boogie Procedure Inliner took 53.93 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 00:28:48,261 INFO L168 Benchmark]: Boogie Preprocessor took 69.19 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. [2019-11-28 00:28:48,262 INFO L168 Benchmark]: RCFGBuilder took 729.19 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 39.8 MB). Peak memory consumption was 39.8 MB. Max. memory is 11.5 GB. [2019-11-28 00:28:48,262 INFO L168 Benchmark]: TraceAbstraction took 26367.22 ms. Allocated memory was 1.1 GB in the beginning and 3.8 GB in the end (delta: 2.7 GB). Free memory was 1.1 GB in the beginning and 2.6 GB in the end (delta: -1.6 GB). Peak memory consumption was 1.1 GB. Max. memory is 11.5 GB. [2019-11-28 00:28:48,263 INFO L168 Benchmark]: Witness Printer took 275.49 ms. Allocated memory is still 3.8 GB. Free memory was 2.6 GB in the beginning and 2.6 GB in the end (delta: 56.9 MB). Peak memory consumption was 56.9 MB. Max. memory is 11.5 GB. [2019-11-28 00:28:48,265 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.34 ms. Allocated memory is still 1.0 GB. Free memory is still 987.2 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 485.79 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 119.0 MB). Free memory was 960.4 MB in the beginning and 1.1 GB in the end (delta: -148.2 MB). Peak memory consumption was 27.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 53.93 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 69.19 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 729.19 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 39.8 MB). Peak memory consumption was 39.8 MB. Max. memory is 11.5 GB. * TraceAbstraction took 26367.22 ms. Allocated memory was 1.1 GB in the beginning and 3.8 GB in the end (delta: 2.7 GB). Free memory was 1.1 GB in the beginning and 2.6 GB in the end (delta: -1.6 GB). Peak memory consumption was 1.1 GB. Max. memory is 11.5 GB. * Witness Printer took 275.49 ms. Allocated memory is still 3.8 GB. Free memory was 2.6 GB in the beginning and 2.6 GB in the end (delta: 56.9 MB). Peak memory consumption was 56.9 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 13]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L18] int c ; [L19] int c_t ; [L20] int c_req_up ; [L21] int p_in ; [L22] int p_out ; [L23] int wl_st ; [L24] int c1_st ; [L25] int c2_st ; [L26] int wb_st ; [L27] int r_st ; [L28] int wl_i ; [L29] int c1_i ; [L30] int c2_i ; [L31] int wb_i ; [L32] int r_i ; [L33] int wl_pc ; [L34] int c1_pc ; [L35] int c2_pc ; [L36] int wb_pc ; [L37] int e_e ; [L38] int e_f ; [L39] int e_g ; [L40] int e_c ; [L41] int e_p_in ; [L42] int e_wl ; [L48] int d ; [L49] int data ; [L50] int processed ; [L51] static int t_b ; VAL [c=0, c1_i=0, c1_pc=0, c1_st=0, c2_i=0, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=0, e_e=0, e_f=0, e_g=0, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=0, wb_pc=0, wb_st=0, wl_i=0, wl_pc=0, wl_st=0] [L691] int __retres1 ; [L695] e_wl = 2 [L696] e_c = e_wl [L697] e_g = e_c [L698] e_f = e_g [L699] e_e = e_f [L700] wl_pc = 0 [L701] c1_pc = 0 [L702] c2_pc = 0 [L703] wb_pc = 0 [L704] wb_i = 1 [L705] c2_i = wb_i [L706] c1_i = c2_i [L707] wl_i = c1_i [L708] r_i = 0 [L709] c_req_up = 0 [L710] d = 0 [L711] c = 0 [L402] int kernel_st ; [L405] kernel_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L406] COND FALSE !((int )c_req_up == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L417] COND TRUE (int )wl_i == 1 [L418] wl_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L422] COND TRUE (int )c1_i == 1 [L423] c1_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L427] COND TRUE (int )c2_i == 1 [L428] c2_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L432] COND TRUE (int )wb_i == 1 [L433] wb_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L437] COND FALSE !((int )r_i == 1) [L440] r_st = 2 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L442] COND FALSE !((int )e_f == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L447] COND FALSE !((int )e_g == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L452] COND FALSE !((int )e_e == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L457] COND FALSE !((int )e_c == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L462] COND FALSE !((int )e_wl == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L467] COND FALSE !((int )wl_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L475] COND FALSE !((int )wl_pc == 2) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L485] COND FALSE !((int )c1_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L494] COND FALSE !((int )c2_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L503] COND FALSE !((int )wb_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L512] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L517] COND FALSE !((int )e_e == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L522] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L527] COND FALSE !((int )e_g == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L532] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L537] COND FALSE !((int )e_wl == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L543] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L546] kernel_st = 1 [L288] int tmp ; [L289] int tmp___0 ; [L290] int tmp___1 ; [L291] int tmp___2 ; [L292] int tmp___3 ; VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L296] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L298] COND TRUE (int )wl_st == 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L319] COND TRUE (int )wl_st == 0 [L321] tmp = __VERIFIER_nondet_int() [L323] COND TRUE \read(tmp) [L325] wl_st = 1 [L53] int t ; VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L56] COND TRUE (int )wl_pc == 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L70] wl_st = 2 [L71] wl_pc = 1 [L72] e_wl = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L334] COND TRUE (int )c1_st == 0 [L336] tmp___0 = __VERIFIER_nondet_int() [L338] COND TRUE \read(tmp___0) [L340] c1_st = 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L139] COND TRUE (int )c1_pc == 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L150] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L152] c1_st = 2 [L153] c1_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L349] COND TRUE (int )c2_st == 0 [L351] tmp___1 = __VERIFIER_nondet_int() [L353] COND TRUE \read(tmp___1) [L355] c2_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L184] COND TRUE (int )c2_pc == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L195] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L197] c2_st = 2 [L198] c2_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L364] COND TRUE (int )wb_st == 0 [L366] tmp___2 = __VERIFIER_nondet_int() [L368] COND TRUE \read(tmp___2) [L370] wb_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L229] COND TRUE (int )wb_pc == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L240] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L242] wb_st = 2 [L243] wb_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L379] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L296] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L298] COND FALSE !((int )wl_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L301] COND FALSE !((int )c1_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L304] COND FALSE !((int )c2_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L307] COND FALSE !((int )wb_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L310] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L549] kernel_st = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L550] COND FALSE !((int )c_req_up == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L561] kernel_st = 3 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L562] COND FALSE !((int )e_f == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L567] COND FALSE !((int )e_g == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L572] COND FALSE !((int )e_e == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L577] COND FALSE !((int )e_c == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L582] COND TRUE (int )e_wl == 0 [L583] e_wl = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L587] COND TRUE (int )wl_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L588] COND TRUE (int )e_wl == 1 [L589] wl_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L605] COND TRUE (int )c1_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L606] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L614] COND TRUE (int )c2_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L615] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L623] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L624] COND FALSE !((int )e_g == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L632] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L637] COND FALSE !((int )e_e == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L642] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L647] COND FALSE !((int )e_g == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L652] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L657] COND TRUE (int )e_wl == 1 [L658] e_wl = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L662] COND TRUE (int )wl_st == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L543] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L546] kernel_st = 1 [L288] int tmp ; [L289] int tmp___0 ; [L290] int tmp___1 ; [L291] int tmp___2 ; [L292] int tmp___3 ; VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L296] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L298] COND TRUE (int )wl_st == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L319] COND TRUE (int )wl_st == 0 [L321] tmp = __VERIFIER_nondet_int() [L323] COND TRUE \read(tmp) [L325] wl_st = 1 [L53] int t ; VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L56] COND FALSE !((int )wl_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L59] COND FALSE !((int )wl_pc == 2) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L62] COND TRUE (int )wl_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L77] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L79] t = d [L80] data = d [L81] processed = 0 [L82] e_f = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L83] COND TRUE (int )c1_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L84] COND TRUE (int )e_f == 1 [L85] c1_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L92] COND TRUE (int )c2_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L93] COND TRUE (int )e_f == 1 [L94] c2_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L101] e_f = 2 [L102] wl_st = 2 [L103] wl_pc = 2 [L104] t_b = t VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L334] COND TRUE (int )c1_st == 0 [L336] tmp___0 = __VERIFIER_nondet_int() [L338] COND TRUE \read(tmp___0) [L340] c1_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L139] COND FALSE !((int )c1_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L142] COND TRUE (int )c1_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L157] COND TRUE ! processed [L158] data += 1 [L159] e_g = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L160] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L161] COND TRUE (int )e_g == 1 [L162] wb_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L169] e_g = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L150] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L152] c1_st = 2 [L153] c1_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L349] COND TRUE (int )c2_st == 0 [L351] tmp___1 = __VERIFIER_nondet_int() [L353] COND TRUE \read(tmp___1) [L355] c2_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L184] COND FALSE !((int )c2_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L187] COND TRUE (int )c2_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L202] COND TRUE ! processed [L203] data += 1 [L204] e_g = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L205] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L206] COND TRUE (int )e_g == 1 [L207] wb_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L214] e_g = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L195] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L197] c2_st = 2 [L198] c2_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L364] COND TRUE (int )wb_st == 0 [L366] tmp___2 = __VERIFIER_nondet_int() [L368] COND TRUE \read(tmp___2) [L370] wb_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L229] COND FALSE !((int )wb_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L232] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L247] c_t = data [L248] c_req_up = 1 [L249] processed = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L240] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L242] wb_st = 2 [L243] wb_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L379] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L296] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L298] COND FALSE !((int )wl_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L301] COND FALSE !((int )c1_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L304] COND FALSE !((int )c2_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L307] COND FALSE !((int )wb_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L310] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L549] kernel_st = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L550] COND TRUE (int )c_req_up == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L551] COND TRUE c != c_t [L552] c = c_t [L553] e_c = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L557] c_req_up = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L561] kernel_st = 3 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L562] COND FALSE !((int )e_f == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L567] COND FALSE !((int )e_g == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L572] COND FALSE !((int )e_e == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L577] COND TRUE (int )e_c == 0 [L578] e_c = 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L582] COND FALSE !((int )e_wl == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L587] COND FALSE !((int )wl_pc == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L595] COND TRUE (int )wl_pc == 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L596] COND FALSE !((int )e_e == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L605] COND TRUE (int )c1_pc == 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L606] COND FALSE !((int )e_f == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L614] COND TRUE (int )c2_pc == 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L615] COND FALSE !((int )e_f == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L623] COND TRUE (int )wb_pc == 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L624] COND FALSE !((int )e_g == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L632] COND TRUE (int )e_c == 1 [L633] r_st = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L637] COND FALSE !((int )e_e == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L642] COND FALSE !((int )e_f == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L647] COND FALSE !((int )e_g == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L652] COND TRUE (int )e_c == 1 [L653] e_c = 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L657] COND FALSE !((int )e_wl == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L662] COND FALSE !((int )wl_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L665] COND FALSE !((int )c1_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L668] COND FALSE !((int )c2_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L671] COND FALSE !((int )wb_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L674] COND TRUE (int )r_st == 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L543] COND TRUE 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L546] kernel_st = 1 [L288] int tmp ; [L289] int tmp___0 ; [L290] int tmp___1 ; [L291] int tmp___2 ; [L292] int tmp___3 ; VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L296] COND TRUE 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L298] COND FALSE !((int )wl_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L301] COND FALSE !((int )c1_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L304] COND FALSE !((int )c2_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L307] COND FALSE !((int )wb_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L310] COND TRUE (int )r_st == 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L319] COND FALSE !((int )wl_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L334] COND FALSE !((int )c1_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L349] COND FALSE !((int )c2_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L364] COND FALSE !((int )wb_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L379] COND TRUE (int )r_st == 0 [L381] tmp___3 = __VERIFIER_nondet_int() [L383] COND TRUE \read(tmp___3) [L385] r_st = 1 [L261] d = c [L262] e_e = 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L263] COND FALSE !((int )wl_pc == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L271] COND TRUE (int )wl_pc == 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L272] COND TRUE (int )e_e == 1 [L273] wl_st = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L281] e_e = 2 [L282] r_st = 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L296] COND TRUE 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L298] COND TRUE (int )wl_st == 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L319] COND TRUE (int )wl_st == 0 [L321] tmp = __VERIFIER_nondet_int() [L323] COND TRUE \read(tmp) [L325] wl_st = 1 [L53] int t ; VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L56] COND FALSE !((int )wl_pc == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L59] COND TRUE (int )wl_pc == 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L108] t = t_b VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L109] COND FALSE !(d == t + 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L112] COND TRUE d == t + 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L120] COND FALSE !(d == t + 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L13] __VERIFIER_error() VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 129 locations, 2 error locations. Result: UNSAFE, OverallTime: 25.9s, OverallIterations: 39, TraceHistogramMax: 6, AutomataDifference: 11.9s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 8305 SDtfs, 6676 SDslu, 6853 SDs, 0 SdLazy, 904 SolverSat, 221 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.2s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 337 GetRequests, 266 SyntacticMatches, 4 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=16823occurred in iteration=19, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 10.6s AutomataMinimizationTime, 38 MinimizatonAttempts, 9357 StatesRemovedByMinimization, 31 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 0.4s SatisfiabilityAnalysisTime, 1.4s InterpolantComputationTime, 3918 NumberOfCodeBlocks, 3918 NumberOfCodeBlocksAsserted, 40 NumberOfCheckSat, 3693 ConstructedInterpolants, 0 QuantifiedInterpolants, 995189 SizeOfPredicates, 8 NumberOfNonLiveVariables, 499 ConjunctsInSsa, 19 ConjunctsInUnsatCore, 39 InterpolantComputations, 37 PerfectInterpolantSequences, 1373/1403 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...