./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/systemc/toy2.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 30f4e4ab Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx12G -Xms1G -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/systemc/toy2.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c8989412e094655bcf4508d76eb9764ed06d0b34 ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.24-30f4e4a [2019-11-28 00:28:22,296 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-28 00:28:22,299 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-28 00:28:22,319 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-28 00:28:22,320 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-28 00:28:22,322 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-28 00:28:22,324 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-28 00:28:22,334 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-28 00:28:22,339 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-28 00:28:22,344 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-28 00:28:22,346 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-28 00:28:22,348 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-28 00:28:22,348 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-28 00:28:22,352 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-28 00:28:22,353 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-28 00:28:22,355 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-28 00:28:22,357 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-28 00:28:22,359 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-28 00:28:22,362 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-28 00:28:22,366 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-28 00:28:22,371 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-28 00:28:22,377 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-28 00:28:22,379 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-28 00:28:22,381 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-28 00:28:22,386 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-28 00:28:22,386 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-28 00:28:22,386 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-28 00:28:22,389 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-28 00:28:22,389 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-28 00:28:22,390 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-28 00:28:22,391 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-28 00:28:22,391 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-28 00:28:22,392 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-28 00:28:22,394 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-28 00:28:22,395 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-28 00:28:22,395 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-28 00:28:22,397 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-28 00:28:22,397 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-28 00:28:22,397 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-28 00:28:22,398 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-28 00:28:22,400 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-28 00:28:22,401 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-28 00:28:22,430 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-28 00:28:22,431 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-28 00:28:22,432 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-28 00:28:22,433 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-28 00:28:22,433 INFO L138 SettingsManager]: * Use SBE=true [2019-11-28 00:28:22,433 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-28 00:28:22,433 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-28 00:28:22,434 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-28 00:28:22,434 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-28 00:28:22,434 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-28 00:28:22,435 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-28 00:28:22,435 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-28 00:28:22,435 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-28 00:28:22,435 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-28 00:28:22,436 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-28 00:28:22,436 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-28 00:28:22,436 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-28 00:28:22,437 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-28 00:28:22,438 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-28 00:28:22,439 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-28 00:28:22,440 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-28 00:28:22,441 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 00:28:22,441 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-28 00:28:22,441 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-28 00:28:22,441 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-28 00:28:22,444 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-28 00:28:22,444 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-28 00:28:22,444 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-28 00:28:22,444 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c8989412e094655bcf4508d76eb9764ed06d0b34 [2019-11-28 00:28:22,753 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-28 00:28:22,777 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-28 00:28:22,781 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-28 00:28:22,783 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-28 00:28:22,783 INFO L275 PluginConnector]: CDTParser initialized [2019-11-28 00:28:22,784 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/toy2.cil.c [2019-11-28 00:28:22,859 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c16d32faf/831ba2eb34eb451ab18fc48c153b1600/FLAG006d24361 [2019-11-28 00:28:23,393 INFO L306 CDTParser]: Found 1 translation units. [2019-11-28 00:28:23,395 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/toy2.cil.c [2019-11-28 00:28:23,408 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c16d32faf/831ba2eb34eb451ab18fc48c153b1600/FLAG006d24361 [2019-11-28 00:28:23,701 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c16d32faf/831ba2eb34eb451ab18fc48c153b1600 [2019-11-28 00:28:23,705 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-28 00:28:23,707 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-28 00:28:23,710 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-28 00:28:23,710 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-28 00:28:23,714 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-28 00:28:23,715 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 12:28:23" (1/1) ... [2019-11-28 00:28:23,718 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@331559d1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:23, skipping insertion in model container [2019-11-28 00:28:23,718 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 12:28:23" (1/1) ... [2019-11-28 00:28:23,726 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-11-28 00:28:23,776 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-11-28 00:28:24,051 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 00:28:24,057 INFO L203 MainTranslator]: Completed pre-run [2019-11-28 00:28:24,175 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 00:28:24,192 INFO L208 MainTranslator]: Completed translation [2019-11-28 00:28:24,192 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:24 WrapperNode [2019-11-28 00:28:24,192 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-28 00:28:24,193 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-28 00:28:24,193 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-28 00:28:24,193 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-28 00:28:24,202 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:24" (1/1) ... [2019-11-28 00:28:24,210 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:24" (1/1) ... [2019-11-28 00:28:24,242 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-28 00:28:24,242 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-28 00:28:24,243 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-28 00:28:24,243 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-28 00:28:24,253 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:24" (1/1) ... [2019-11-28 00:28:24,254 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:24" (1/1) ... [2019-11-28 00:28:24,257 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:24" (1/1) ... [2019-11-28 00:28:24,257 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:24" (1/1) ... [2019-11-28 00:28:24,264 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:24" (1/1) ... [2019-11-28 00:28:24,280 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:24" (1/1) ... [2019-11-28 00:28:24,283 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:24" (1/1) ... [2019-11-28 00:28:24,287 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-28 00:28:24,288 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-28 00:28:24,288 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-28 00:28:24,289 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-28 00:28:24,290 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:24" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 00:28:24,355 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-28 00:28:24,355 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-28 00:28:25,065 INFO L292 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-28 00:28:25,066 INFO L297 CfgBuilder]: Removed 26 assume(true) statements. [2019-11-28 00:28:25,067 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 12:28:25 BoogieIcfgContainer [2019-11-28 00:28:25,068 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-28 00:28:25,069 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-28 00:28:25,069 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-28 00:28:25,073 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-28 00:28:25,074 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 12:28:23" (1/3) ... [2019-11-28 00:28:25,075 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5a669071 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 12:28:25, skipping insertion in model container [2019-11-28 00:28:25,075 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:24" (2/3) ... [2019-11-28 00:28:25,076 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5a669071 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 12:28:25, skipping insertion in model container [2019-11-28 00:28:25,078 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 12:28:25" (3/3) ... [2019-11-28 00:28:25,079 INFO L109 eAbstractionObserver]: Analyzing ICFG toy2.cil.c [2019-11-28 00:28:25,094 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-28 00:28:25,103 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-11-28 00:28:25,117 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-11-28 00:28:25,148 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-28 00:28:25,148 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-28 00:28:25,148 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-28 00:28:25,148 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-28 00:28:25,150 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-28 00:28:25,150 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-28 00:28:25,150 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-28 00:28:25,150 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-28 00:28:25,179 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states. [2019-11-28 00:28:25,186 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-11-28 00:28:25,186 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:25,187 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:25,188 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:25,193 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:25,193 INFO L82 PathProgramCache]: Analyzing trace with hash 1633671955, now seen corresponding path program 1 times [2019-11-28 00:28:25,203 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:25,203 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1312541459] [2019-11-28 00:28:25,204 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:25,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:25,393 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:25,395 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1312541459] [2019-11-28 00:28:25,397 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:25,397 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:25,399 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1678167497] [2019-11-28 00:28:25,407 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:25,407 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:25,421 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:25,422 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:25,424 INFO L87 Difference]: Start difference. First operand 125 states. Second operand 3 states. [2019-11-28 00:28:25,472 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:25,473 INFO L93 Difference]: Finished difference Result 242 states and 449 transitions. [2019-11-28 00:28:25,474 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:25,476 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 35 [2019-11-28 00:28:25,476 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:25,490 INFO L225 Difference]: With dead ends: 242 [2019-11-28 00:28:25,490 INFO L226 Difference]: Without dead ends: 121 [2019-11-28 00:28:25,495 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:25,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121 states. [2019-11-28 00:28:25,554 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121 to 121. [2019-11-28 00:28:25,555 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 121 states. [2019-11-28 00:28:25,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121 states to 121 states and 213 transitions. [2019-11-28 00:28:25,569 INFO L78 Accepts]: Start accepts. Automaton has 121 states and 213 transitions. Word has length 35 [2019-11-28 00:28:25,572 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:25,572 INFO L462 AbstractCegarLoop]: Abstraction has 121 states and 213 transitions. [2019-11-28 00:28:25,573 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:25,573 INFO L276 IsEmpty]: Start isEmpty. Operand 121 states and 213 transitions. [2019-11-28 00:28:25,577 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-11-28 00:28:25,577 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:25,578 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:25,579 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:25,579 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:25,579 INFO L82 PathProgramCache]: Analyzing trace with hash 1611039701, now seen corresponding path program 1 times [2019-11-28 00:28:25,579 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:25,580 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [687777851] [2019-11-28 00:28:25,580 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:25,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:25,666 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:25,666 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [687777851] [2019-11-28 00:28:25,667 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:25,667 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:25,667 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1152150514] [2019-11-28 00:28:25,669 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:25,670 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:25,670 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:25,671 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:25,671 INFO L87 Difference]: Start difference. First operand 121 states and 213 transitions. Second operand 3 states. [2019-11-28 00:28:25,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:25,714 INFO L93 Difference]: Finished difference Result 232 states and 410 transitions. [2019-11-28 00:28:25,716 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:25,716 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 35 [2019-11-28 00:28:25,717 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:25,718 INFO L225 Difference]: With dead ends: 232 [2019-11-28 00:28:25,720 INFO L226 Difference]: Without dead ends: 121 [2019-11-28 00:28:25,722 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:25,724 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121 states. [2019-11-28 00:28:25,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121 to 121. [2019-11-28 00:28:25,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 121 states. [2019-11-28 00:28:25,741 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121 states to 121 states and 212 transitions. [2019-11-28 00:28:25,742 INFO L78 Accepts]: Start accepts. Automaton has 121 states and 212 transitions. Word has length 35 [2019-11-28 00:28:25,742 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:25,742 INFO L462 AbstractCegarLoop]: Abstraction has 121 states and 212 transitions. [2019-11-28 00:28:25,742 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:25,743 INFO L276 IsEmpty]: Start isEmpty. Operand 121 states and 212 transitions. [2019-11-28 00:28:25,744 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-11-28 00:28:25,744 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:25,745 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:25,745 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:25,746 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:25,746 INFO L82 PathProgramCache]: Analyzing trace with hash 1101566611, now seen corresponding path program 1 times [2019-11-28 00:28:25,746 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:25,747 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [893507627] [2019-11-28 00:28:25,747 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:25,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:25,877 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:25,879 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [893507627] [2019-11-28 00:28:25,880 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:25,881 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:25,881 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1319933639] [2019-11-28 00:28:25,883 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:25,884 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:25,885 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:25,887 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:25,887 INFO L87 Difference]: Start difference. First operand 121 states and 212 transitions. Second operand 3 states. [2019-11-28 00:28:26,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:26,036 INFO L93 Difference]: Finished difference Result 316 states and 553 transitions. [2019-11-28 00:28:26,036 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:26,037 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 35 [2019-11-28 00:28:26,037 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:26,040 INFO L225 Difference]: With dead ends: 316 [2019-11-28 00:28:26,040 INFO L226 Difference]: Without dead ends: 206 [2019-11-28 00:28:26,041 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:26,042 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 206 states. [2019-11-28 00:28:26,062 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 206 to 196. [2019-11-28 00:28:26,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 196 states. [2019-11-28 00:28:26,064 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 196 states to 196 states and 330 transitions. [2019-11-28 00:28:26,064 INFO L78 Accepts]: Start accepts. Automaton has 196 states and 330 transitions. Word has length 35 [2019-11-28 00:28:26,064 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:26,065 INFO L462 AbstractCegarLoop]: Abstraction has 196 states and 330 transitions. [2019-11-28 00:28:26,065 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:26,065 INFO L276 IsEmpty]: Start isEmpty. Operand 196 states and 330 transitions. [2019-11-28 00:28:26,067 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-11-28 00:28:26,067 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:26,067 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:26,068 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:26,068 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:26,068 INFO L82 PathProgramCache]: Analyzing trace with hash 197658071, now seen corresponding path program 1 times [2019-11-28 00:28:26,069 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:26,069 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [214043065] [2019-11-28 00:28:26,070 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:26,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:26,138 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:26,139 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [214043065] [2019-11-28 00:28:26,139 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:26,139 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 00:28:26,141 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1207306973] [2019-11-28 00:28:26,141 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 00:28:26,142 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:26,142 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 00:28:26,142 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 00:28:26,143 INFO L87 Difference]: Start difference. First operand 196 states and 330 transitions. Second operand 4 states. [2019-11-28 00:28:26,294 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:26,294 INFO L93 Difference]: Finished difference Result 530 states and 896 transitions. [2019-11-28 00:28:26,295 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 00:28:26,296 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 35 [2019-11-28 00:28:26,296 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:26,299 INFO L225 Difference]: With dead ends: 530 [2019-11-28 00:28:26,300 INFO L226 Difference]: Without dead ends: 346 [2019-11-28 00:28:26,302 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 00:28:26,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 346 states. [2019-11-28 00:28:26,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 346 to 340. [2019-11-28 00:28:26,340 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 340 states. [2019-11-28 00:28:26,342 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 340 states to 340 states and 572 transitions. [2019-11-28 00:28:26,342 INFO L78 Accepts]: Start accepts. Automaton has 340 states and 572 transitions. Word has length 35 [2019-11-28 00:28:26,342 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:26,343 INFO L462 AbstractCegarLoop]: Abstraction has 340 states and 572 transitions. [2019-11-28 00:28:26,343 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 00:28:26,343 INFO L276 IsEmpty]: Start isEmpty. Operand 340 states and 572 transitions. [2019-11-28 00:28:26,345 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-11-28 00:28:26,346 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:26,346 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:26,346 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:26,347 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:26,347 INFO L82 PathProgramCache]: Analyzing trace with hash 259697685, now seen corresponding path program 1 times [2019-11-28 00:28:26,347 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:26,347 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1279063525] [2019-11-28 00:28:26,348 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:26,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:26,430 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:26,431 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1279063525] [2019-11-28 00:28:26,431 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:26,432 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 00:28:26,432 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [373369804] [2019-11-28 00:28:26,433 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 00:28:26,433 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:26,433 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 00:28:26,434 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 00:28:26,434 INFO L87 Difference]: Start difference. First operand 340 states and 572 transitions. Second operand 4 states. [2019-11-28 00:28:26,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:26,573 INFO L93 Difference]: Finished difference Result 955 states and 1611 transitions. [2019-11-28 00:28:26,573 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 00:28:26,573 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 35 [2019-11-28 00:28:26,574 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:26,578 INFO L225 Difference]: With dead ends: 955 [2019-11-28 00:28:26,578 INFO L226 Difference]: Without dead ends: 628 [2019-11-28 00:28:26,580 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 00:28:26,582 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 628 states. [2019-11-28 00:28:26,628 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 628 to 622. [2019-11-28 00:28:26,628 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 622 states. [2019-11-28 00:28:26,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 622 states to 622 states and 1042 transitions. [2019-11-28 00:28:26,632 INFO L78 Accepts]: Start accepts. Automaton has 622 states and 1042 transitions. Word has length 35 [2019-11-28 00:28:26,632 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:26,632 INFO L462 AbstractCegarLoop]: Abstraction has 622 states and 1042 transitions. [2019-11-28 00:28:26,633 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 00:28:26,633 INFO L276 IsEmpty]: Start isEmpty. Operand 622 states and 1042 transitions. [2019-11-28 00:28:26,642 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-11-28 00:28:26,642 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:26,642 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:26,643 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:26,643 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:26,643 INFO L82 PathProgramCache]: Analyzing trace with hash 400246295, now seen corresponding path program 1 times [2019-11-28 00:28:26,644 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:26,644 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1847935641] [2019-11-28 00:28:26,644 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:26,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:26,708 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:26,708 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1847935641] [2019-11-28 00:28:26,709 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:26,710 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 00:28:26,711 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [613723320] [2019-11-28 00:28:26,711 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 00:28:26,711 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:26,712 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 00:28:26,712 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 00:28:26,713 INFO L87 Difference]: Start difference. First operand 622 states and 1042 transitions. Second operand 4 states. [2019-11-28 00:28:26,884 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:26,884 INFO L93 Difference]: Finished difference Result 1891 states and 3148 transitions. [2019-11-28 00:28:26,885 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 00:28:26,885 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 35 [2019-11-28 00:28:26,885 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:26,895 INFO L225 Difference]: With dead ends: 1891 [2019-11-28 00:28:26,896 INFO L226 Difference]: Without dead ends: 1283 [2019-11-28 00:28:26,898 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 00:28:26,901 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1283 states. [2019-11-28 00:28:26,966 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1283 to 1277. [2019-11-28 00:28:26,967 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1277 states. [2019-11-28 00:28:26,973 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1277 states to 1277 states and 2102 transitions. [2019-11-28 00:28:26,974 INFO L78 Accepts]: Start accepts. Automaton has 1277 states and 2102 transitions. Word has length 35 [2019-11-28 00:28:26,974 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:26,974 INFO L462 AbstractCegarLoop]: Abstraction has 1277 states and 2102 transitions. [2019-11-28 00:28:26,975 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 00:28:26,975 INFO L276 IsEmpty]: Start isEmpty. Operand 1277 states and 2102 transitions. [2019-11-28 00:28:26,977 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-11-28 00:28:26,977 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:26,977 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:26,978 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:26,978 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:26,978 INFO L82 PathProgramCache]: Analyzing trace with hash 266232789, now seen corresponding path program 1 times [2019-11-28 00:28:26,979 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:26,979 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1020475077] [2019-11-28 00:28:26,979 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:26,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:27,066 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:27,068 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1020475077] [2019-11-28 00:28:27,069 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:27,069 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:27,070 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1159677129] [2019-11-28 00:28:27,070 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:27,071 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:27,077 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:27,078 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:27,079 INFO L87 Difference]: Start difference. First operand 1277 states and 2102 transitions. Second operand 3 states. [2019-11-28 00:28:27,213 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:27,214 INFO L93 Difference]: Finished difference Result 2603 states and 4295 transitions. [2019-11-28 00:28:27,215 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:27,215 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 35 [2019-11-28 00:28:27,215 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:27,223 INFO L225 Difference]: With dead ends: 2603 [2019-11-28 00:28:27,224 INFO L226 Difference]: Without dead ends: 1383 [2019-11-28 00:28:27,227 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:27,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1383 states. [2019-11-28 00:28:27,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1383 to 1376. [2019-11-28 00:28:27,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1376 states. [2019-11-28 00:28:27,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1376 states to 1376 states and 2257 transitions. [2019-11-28 00:28:27,300 INFO L78 Accepts]: Start accepts. Automaton has 1376 states and 2257 transitions. Word has length 35 [2019-11-28 00:28:27,300 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:27,300 INFO L462 AbstractCegarLoop]: Abstraction has 1376 states and 2257 transitions. [2019-11-28 00:28:27,301 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:27,301 INFO L276 IsEmpty]: Start isEmpty. Operand 1376 states and 2257 transitions. [2019-11-28 00:28:27,302 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-11-28 00:28:27,303 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:27,303 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:27,304 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:27,304 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:27,304 INFO L82 PathProgramCache]: Analyzing trace with hash -1908921127, now seen corresponding path program 1 times [2019-11-28 00:28:27,305 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:27,305 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [150782811] [2019-11-28 00:28:27,305 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:27,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:27,340 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:27,340 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [150782811] [2019-11-28 00:28:27,341 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:27,341 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 00:28:27,341 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1320435888] [2019-11-28 00:28:27,342 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 00:28:27,342 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:27,342 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 00:28:27,342 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 00:28:27,343 INFO L87 Difference]: Start difference. First operand 1376 states and 2257 transitions. Second operand 4 states. [2019-11-28 00:28:27,497 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:27,497 INFO L93 Difference]: Finished difference Result 2882 states and 4737 transitions. [2019-11-28 00:28:27,498 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-28 00:28:27,498 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 35 [2019-11-28 00:28:27,498 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:27,507 INFO L225 Difference]: With dead ends: 2882 [2019-11-28 00:28:27,507 INFO L226 Difference]: Without dead ends: 1540 [2019-11-28 00:28:27,510 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 00:28:27,512 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1540 states. [2019-11-28 00:28:27,614 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1540 to 1529. [2019-11-28 00:28:27,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1529 states. [2019-11-28 00:28:27,622 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1529 states to 1529 states and 2471 transitions. [2019-11-28 00:28:27,622 INFO L78 Accepts]: Start accepts. Automaton has 1529 states and 2471 transitions. Word has length 35 [2019-11-28 00:28:27,622 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:27,622 INFO L462 AbstractCegarLoop]: Abstraction has 1529 states and 2471 transitions. [2019-11-28 00:28:27,623 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 00:28:27,623 INFO L276 IsEmpty]: Start isEmpty. Operand 1529 states and 2471 transitions. [2019-11-28 00:28:27,624 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-11-28 00:28:27,624 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:27,624 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:27,624 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:27,624 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:27,625 INFO L82 PathProgramCache]: Analyzing trace with hash 1364977815, now seen corresponding path program 1 times [2019-11-28 00:28:27,625 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:27,626 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1484668240] [2019-11-28 00:28:27,626 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:27,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:27,682 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:27,682 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1484668240] [2019-11-28 00:28:27,683 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:27,683 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 00:28:27,683 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1514018829] [2019-11-28 00:28:27,684 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 00:28:27,684 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:27,684 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 00:28:27,685 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 00:28:27,685 INFO L87 Difference]: Start difference. First operand 1529 states and 2471 transitions. Second operand 4 states. [2019-11-28 00:28:27,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:27,898 INFO L93 Difference]: Finished difference Result 3348 states and 5416 transitions. [2019-11-28 00:28:27,899 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-28 00:28:27,899 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 35 [2019-11-28 00:28:27,900 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:27,914 INFO L225 Difference]: With dead ends: 3348 [2019-11-28 00:28:27,914 INFO L226 Difference]: Without dead ends: 1865 [2019-11-28 00:28:27,918 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 00:28:27,922 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1865 states. [2019-11-28 00:28:28,023 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1865 to 1841. [2019-11-28 00:28:28,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1841 states. [2019-11-28 00:28:28,036 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1841 states to 1841 states and 2935 transitions. [2019-11-28 00:28:28,037 INFO L78 Accepts]: Start accepts. Automaton has 1841 states and 2935 transitions. Word has length 35 [2019-11-28 00:28:28,037 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:28,038 INFO L462 AbstractCegarLoop]: Abstraction has 1841 states and 2935 transitions. [2019-11-28 00:28:28,038 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 00:28:28,038 INFO L276 IsEmpty]: Start isEmpty. Operand 1841 states and 2935 transitions. [2019-11-28 00:28:28,040 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-11-28 00:28:28,040 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:28,041 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:28,041 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:28,041 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:28,042 INFO L82 PathProgramCache]: Analyzing trace with hash 353860565, now seen corresponding path program 1 times [2019-11-28 00:28:28,042 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:28,043 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [400236874] [2019-11-28 00:28:28,043 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:28,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:28,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:28,101 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [400236874] [2019-11-28 00:28:28,102 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:28,102 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:28,102 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1043146376] [2019-11-28 00:28:28,103 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:28,103 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:28,104 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:28,104 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:28,105 INFO L87 Difference]: Start difference. First operand 1841 states and 2935 transitions. Second operand 3 states. [2019-11-28 00:28:28,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:28,243 INFO L93 Difference]: Finished difference Result 3307 states and 5278 transitions. [2019-11-28 00:28:28,248 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:28,248 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 35 [2019-11-28 00:28:28,251 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:28,262 INFO L225 Difference]: With dead ends: 3307 [2019-11-28 00:28:28,264 INFO L226 Difference]: Without dead ends: 1494 [2019-11-28 00:28:28,268 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:28,272 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1494 states. [2019-11-28 00:28:28,353 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1494 to 1483. [2019-11-28 00:28:28,354 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1483 states. [2019-11-28 00:28:28,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1483 states to 1483 states and 2335 transitions. [2019-11-28 00:28:28,361 INFO L78 Accepts]: Start accepts. Automaton has 1483 states and 2335 transitions. Word has length 35 [2019-11-28 00:28:28,362 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:28,365 INFO L462 AbstractCegarLoop]: Abstraction has 1483 states and 2335 transitions. [2019-11-28 00:28:28,365 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:28,366 INFO L276 IsEmpty]: Start isEmpty. Operand 1483 states and 2335 transitions. [2019-11-28 00:28:28,367 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2019-11-28 00:28:28,367 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:28,368 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:28,368 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:28,368 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:28,369 INFO L82 PathProgramCache]: Analyzing trace with hash -209495903, now seen corresponding path program 1 times [2019-11-28 00:28:28,369 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:28,369 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1592901503] [2019-11-28 00:28:28,369 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:28,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:28,423 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:28,424 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1592901503] [2019-11-28 00:28:28,424 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:28,424 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:28,425 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1636599125] [2019-11-28 00:28:28,425 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:28,426 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:28,426 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:28,426 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:28,426 INFO L87 Difference]: Start difference. First operand 1483 states and 2335 transitions. Second operand 3 states. [2019-11-28 00:28:28,535 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:28,535 INFO L93 Difference]: Finished difference Result 3698 states and 5877 transitions. [2019-11-28 00:28:28,536 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:28,536 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 45 [2019-11-28 00:28:28,536 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:28,548 INFO L225 Difference]: With dead ends: 3698 [2019-11-28 00:28:28,549 INFO L226 Difference]: Without dead ends: 2269 [2019-11-28 00:28:28,552 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:28,556 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2269 states. [2019-11-28 00:28:28,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2269 to 2267. [2019-11-28 00:28:28,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2267 states. [2019-11-28 00:28:28,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2267 states to 2267 states and 3563 transitions. [2019-11-28 00:28:28,667 INFO L78 Accepts]: Start accepts. Automaton has 2267 states and 3563 transitions. Word has length 45 [2019-11-28 00:28:28,668 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:28,668 INFO L462 AbstractCegarLoop]: Abstraction has 2267 states and 3563 transitions. [2019-11-28 00:28:28,668 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:28,668 INFO L276 IsEmpty]: Start isEmpty. Operand 2267 states and 3563 transitions. [2019-11-28 00:28:28,670 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2019-11-28 00:28:28,670 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:28,671 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:28,671 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:28,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:28,672 INFO L82 PathProgramCache]: Analyzing trace with hash 214150819, now seen corresponding path program 1 times [2019-11-28 00:28:28,672 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:28,673 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [202533302] [2019-11-28 00:28:28,674 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:28,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:28,700 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2019-11-28 00:28:28,701 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [202533302] [2019-11-28 00:28:28,701 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:28,701 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:28,701 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1392335552] [2019-11-28 00:28:28,702 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:28,702 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:28,702 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:28,702 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:28,702 INFO L87 Difference]: Start difference. First operand 2267 states and 3563 transitions. Second operand 3 states. [2019-11-28 00:28:28,796 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:28,797 INFO L93 Difference]: Finished difference Result 4436 states and 7000 transitions. [2019-11-28 00:28:28,797 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:28,798 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 45 [2019-11-28 00:28:28,798 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:28,809 INFO L225 Difference]: With dead ends: 4436 [2019-11-28 00:28:28,810 INFO L226 Difference]: Without dead ends: 2223 [2019-11-28 00:28:28,814 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:28,818 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2223 states. [2019-11-28 00:28:28,910 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2223 to 2223. [2019-11-28 00:28:28,910 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2223 states. [2019-11-28 00:28:28,919 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2223 states to 2223 states and 3506 transitions. [2019-11-28 00:28:28,919 INFO L78 Accepts]: Start accepts. Automaton has 2223 states and 3506 transitions. Word has length 45 [2019-11-28 00:28:28,919 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:28,919 INFO L462 AbstractCegarLoop]: Abstraction has 2223 states and 3506 transitions. [2019-11-28 00:28:28,920 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:28,920 INFO L276 IsEmpty]: Start isEmpty. Operand 2223 states and 3506 transitions. [2019-11-28 00:28:28,922 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2019-11-28 00:28:28,922 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:28,922 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:28,922 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:28,923 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:28,923 INFO L82 PathProgramCache]: Analyzing trace with hash 1700232685, now seen corresponding path program 1 times [2019-11-28 00:28:28,923 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:28,923 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1193166259] [2019-11-28 00:28:28,924 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:28,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:28,964 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:28,965 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1193166259] [2019-11-28 00:28:28,965 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:28,965 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:28,966 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1694382285] [2019-11-28 00:28:28,966 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:28,966 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:28,967 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:28,967 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:28,968 INFO L87 Difference]: Start difference. First operand 2223 states and 3506 transitions. Second operand 3 states. [2019-11-28 00:28:29,165 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:29,166 INFO L93 Difference]: Finished difference Result 5707 states and 9064 transitions. [2019-11-28 00:28:29,166 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:29,167 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 46 [2019-11-28 00:28:29,168 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:29,193 INFO L225 Difference]: With dead ends: 5707 [2019-11-28 00:28:29,194 INFO L226 Difference]: Without dead ends: 3538 [2019-11-28 00:28:29,201 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:29,209 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3538 states. [2019-11-28 00:28:29,508 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3538 to 3536. [2019-11-28 00:28:29,509 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3536 states. [2019-11-28 00:28:29,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3536 states to 3536 states and 5558 transitions. [2019-11-28 00:28:29,529 INFO L78 Accepts]: Start accepts. Automaton has 3536 states and 5558 transitions. Word has length 46 [2019-11-28 00:28:29,529 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:29,529 INFO L462 AbstractCegarLoop]: Abstraction has 3536 states and 5558 transitions. [2019-11-28 00:28:29,529 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:29,530 INFO L276 IsEmpty]: Start isEmpty. Operand 3536 states and 5558 transitions. [2019-11-28 00:28:29,533 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2019-11-28 00:28:29,533 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:29,533 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:29,534 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:29,534 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:29,534 INFO L82 PathProgramCache]: Analyzing trace with hash 1601371510, now seen corresponding path program 1 times [2019-11-28 00:28:29,535 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:29,535 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1281926820] [2019-11-28 00:28:29,535 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:29,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:29,570 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:29,571 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1281926820] [2019-11-28 00:28:29,571 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:29,572 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:29,573 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [806708128] [2019-11-28 00:28:29,573 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:29,573 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:29,573 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:29,574 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:29,574 INFO L87 Difference]: Start difference. First operand 3536 states and 5558 transitions. Second operand 3 states. [2019-11-28 00:28:29,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:29,879 INFO L93 Difference]: Finished difference Result 8979 states and 14292 transitions. [2019-11-28 00:28:29,879 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:29,880 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 47 [2019-11-28 00:28:29,881 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:29,913 INFO L225 Difference]: With dead ends: 8979 [2019-11-28 00:28:29,913 INFO L226 Difference]: Without dead ends: 5501 [2019-11-28 00:28:29,922 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:29,931 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5501 states. [2019-11-28 00:28:30,196 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5501 to 5499. [2019-11-28 00:28:30,197 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5499 states. [2019-11-28 00:28:30,227 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5499 states to 5499 states and 8711 transitions. [2019-11-28 00:28:30,228 INFO L78 Accepts]: Start accepts. Automaton has 5499 states and 8711 transitions. Word has length 47 [2019-11-28 00:28:30,229 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:30,229 INFO L462 AbstractCegarLoop]: Abstraction has 5499 states and 8711 transitions. [2019-11-28 00:28:30,229 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:30,229 INFO L276 IsEmpty]: Start isEmpty. Operand 5499 states and 8711 transitions. [2019-11-28 00:28:30,233 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2019-11-28 00:28:30,234 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:30,234 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:30,234 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:30,235 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:30,235 INFO L82 PathProgramCache]: Analyzing trace with hash 2025018232, now seen corresponding path program 1 times [2019-11-28 00:28:30,235 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:30,235 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1031283857] [2019-11-28 00:28:30,236 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:30,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:30,257 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2019-11-28 00:28:30,257 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1031283857] [2019-11-28 00:28:30,257 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:30,257 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:30,258 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1443548027] [2019-11-28 00:28:30,258 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:30,258 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:30,258 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:30,258 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:30,259 INFO L87 Difference]: Start difference. First operand 5499 states and 8711 transitions. Second operand 3 states. [2019-11-28 00:28:30,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:30,482 INFO L93 Difference]: Finished difference Result 10896 states and 17296 transitions. [2019-11-28 00:28:30,482 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:30,482 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 47 [2019-11-28 00:28:30,482 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:30,509 INFO L225 Difference]: With dead ends: 10896 [2019-11-28 00:28:30,510 INFO L226 Difference]: Without dead ends: 5455 [2019-11-28 00:28:30,520 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:30,529 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5455 states. [2019-11-28 00:28:30,879 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5455 to 5455. [2019-11-28 00:28:30,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5455 states. [2019-11-28 00:28:30,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5455 states to 5455 states and 8656 transitions. [2019-11-28 00:28:30,896 INFO L78 Accepts]: Start accepts. Automaton has 5455 states and 8656 transitions. Word has length 47 [2019-11-28 00:28:30,896 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:30,897 INFO L462 AbstractCegarLoop]: Abstraction has 5455 states and 8656 transitions. [2019-11-28 00:28:30,897 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:30,897 INFO L276 IsEmpty]: Start isEmpty. Operand 5455 states and 8656 transitions. [2019-11-28 00:28:30,902 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2019-11-28 00:28:30,903 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:30,903 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:30,903 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:30,904 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:30,904 INFO L82 PathProgramCache]: Analyzing trace with hash -2129316584, now seen corresponding path program 1 times [2019-11-28 00:28:30,904 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:30,905 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1043518527] [2019-11-28 00:28:30,905 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:30,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:30,938 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:30,938 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1043518527] [2019-11-28 00:28:30,939 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:30,939 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:30,939 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1099110298] [2019-11-28 00:28:30,940 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:30,940 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:30,940 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:30,940 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:30,941 INFO L87 Difference]: Start difference. First operand 5455 states and 8656 transitions. Second operand 3 states. [2019-11-28 00:28:31,255 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:31,256 INFO L93 Difference]: Finished difference Result 15441 states and 24452 transitions. [2019-11-28 00:28:31,257 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:31,257 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2019-11-28 00:28:31,257 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:31,286 INFO L225 Difference]: With dead ends: 15441 [2019-11-28 00:28:31,287 INFO L226 Difference]: Without dead ends: 8274 [2019-11-28 00:28:31,300 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:31,312 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8274 states. [2019-11-28 00:28:31,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8274 to 8274. [2019-11-28 00:28:31,646 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8274 states. [2019-11-28 00:28:31,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8274 states to 8274 states and 12950 transitions. [2019-11-28 00:28:31,671 INFO L78 Accepts]: Start accepts. Automaton has 8274 states and 12950 transitions. Word has length 48 [2019-11-28 00:28:31,671 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:31,671 INFO L462 AbstractCegarLoop]: Abstraction has 8274 states and 12950 transitions. [2019-11-28 00:28:31,672 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:31,672 INFO L276 IsEmpty]: Start isEmpty. Operand 8274 states and 12950 transitions. [2019-11-28 00:28:31,678 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2019-11-28 00:28:31,678 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:31,678 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:31,679 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:31,679 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:31,680 INFO L82 PathProgramCache]: Analyzing trace with hash -1392856220, now seen corresponding path program 1 times [2019-11-28 00:28:31,680 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:31,680 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1966497988] [2019-11-28 00:28:31,681 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:31,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:31,731 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:31,731 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1966497988] [2019-11-28 00:28:31,732 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:31,732 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:31,732 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [668221141] [2019-11-28 00:28:31,733 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:31,733 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:31,733 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:31,733 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:31,733 INFO L87 Difference]: Start difference. First operand 8274 states and 12950 transitions. Second operand 3 states. [2019-11-28 00:28:32,112 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:32,113 INFO L93 Difference]: Finished difference Result 17053 states and 26638 transitions. [2019-11-28 00:28:32,114 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:32,114 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 52 [2019-11-28 00:28:32,114 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:32,139 INFO L225 Difference]: With dead ends: 17053 [2019-11-28 00:28:32,140 INFO L226 Difference]: Without dead ends: 8815 [2019-11-28 00:28:32,155 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:32,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8815 states. [2019-11-28 00:28:32,461 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8815 to 8272. [2019-11-28 00:28:32,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8272 states. [2019-11-28 00:28:32,482 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8272 states to 8272 states and 12699 transitions. [2019-11-28 00:28:32,482 INFO L78 Accepts]: Start accepts. Automaton has 8272 states and 12699 transitions. Word has length 52 [2019-11-28 00:28:32,482 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:32,483 INFO L462 AbstractCegarLoop]: Abstraction has 8272 states and 12699 transitions. [2019-11-28 00:28:32,483 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:32,483 INFO L276 IsEmpty]: Start isEmpty. Operand 8272 states and 12699 transitions. [2019-11-28 00:28:32,489 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-11-28 00:28:32,489 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:32,489 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:32,490 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:32,490 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:32,490 INFO L82 PathProgramCache]: Analyzing trace with hash 1708846795, now seen corresponding path program 1 times [2019-11-28 00:28:32,490 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:32,491 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1893764443] [2019-11-28 00:28:32,491 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:32,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:32,515 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2019-11-28 00:28:32,516 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1893764443] [2019-11-28 00:28:32,516 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:32,516 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:32,516 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1996558722] [2019-11-28 00:28:32,517 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:32,517 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:32,517 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:32,517 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:32,518 INFO L87 Difference]: Start difference. First operand 8272 states and 12699 transitions. Second operand 3 states. [2019-11-28 00:28:33,062 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:33,062 INFO L93 Difference]: Finished difference Result 24504 states and 37704 transitions. [2019-11-28 00:28:33,063 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:33,063 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 54 [2019-11-28 00:28:33,063 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:33,106 INFO L225 Difference]: With dead ends: 24504 [2019-11-28 00:28:33,106 INFO L226 Difference]: Without dead ends: 16235 [2019-11-28 00:28:33,125 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:33,150 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16235 states. [2019-11-28 00:28:33,798 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16235 to 16105. [2019-11-28 00:28:33,798 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16105 states. [2019-11-28 00:28:33,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16105 states to 16105 states and 24847 transitions. [2019-11-28 00:28:33,836 INFO L78 Accepts]: Start accepts. Automaton has 16105 states and 24847 transitions. Word has length 54 [2019-11-28 00:28:33,836 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:33,836 INFO L462 AbstractCegarLoop]: Abstraction has 16105 states and 24847 transitions. [2019-11-28 00:28:33,836 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:33,836 INFO L276 IsEmpty]: Start isEmpty. Operand 16105 states and 24847 transitions. [2019-11-28 00:28:33,846 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2019-11-28 00:28:33,846 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:33,846 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:33,846 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:33,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:33,847 INFO L82 PathProgramCache]: Analyzing trace with hash 194830513, now seen corresponding path program 1 times [2019-11-28 00:28:33,847 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:33,847 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [748225760] [2019-11-28 00:28:33,847 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:33,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:33,882 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:33,883 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [748225760] [2019-11-28 00:28:33,883 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:33,884 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:33,884 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1838276483] [2019-11-28 00:28:33,884 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:33,885 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:33,885 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:33,885 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:33,886 INFO L87 Difference]: Start difference. First operand 16105 states and 24847 transitions. Second operand 3 states. [2019-11-28 00:28:34,297 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:34,297 INFO L93 Difference]: Finished difference Result 32865 states and 50652 transitions. [2019-11-28 00:28:34,298 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:34,298 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 85 [2019-11-28 00:28:34,298 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:34,336 INFO L225 Difference]: With dead ends: 32865 [2019-11-28 00:28:34,336 INFO L226 Difference]: Without dead ends: 16789 [2019-11-28 00:28:34,368 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:34,388 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16789 states. [2019-11-28 00:28:35,225 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16789 to 16725. [2019-11-28 00:28:35,225 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16725 states. [2019-11-28 00:28:35,255 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16725 states to 16725 states and 25149 transitions. [2019-11-28 00:28:35,255 INFO L78 Accepts]: Start accepts. Automaton has 16725 states and 25149 transitions. Word has length 85 [2019-11-28 00:28:35,256 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:35,256 INFO L462 AbstractCegarLoop]: Abstraction has 16725 states and 25149 transitions. [2019-11-28 00:28:35,256 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:35,256 INFO L276 IsEmpty]: Start isEmpty. Operand 16725 states and 25149 transitions. [2019-11-28 00:28:35,268 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2019-11-28 00:28:35,269 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:35,269 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:35,269 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:35,270 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:35,270 INFO L82 PathProgramCache]: Analyzing trace with hash 164482089, now seen corresponding path program 1 times [2019-11-28 00:28:35,270 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:35,270 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [987572961] [2019-11-28 00:28:35,271 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:35,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:35,312 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-11-28 00:28:35,313 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [987572961] [2019-11-28 00:28:35,313 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:35,313 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 00:28:35,314 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1882066569] [2019-11-28 00:28:35,314 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 00:28:35,315 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:35,315 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 00:28:35,315 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 00:28:35,316 INFO L87 Difference]: Start difference. First operand 16725 states and 25149 transitions. Second operand 4 states. [2019-11-28 00:28:35,793 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:35,793 INFO L93 Difference]: Finished difference Result 27583 states and 41591 transitions. [2019-11-28 00:28:35,794 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-28 00:28:35,794 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 86 [2019-11-28 00:28:35,794 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:35,824 INFO L225 Difference]: With dead ends: 27583 [2019-11-28 00:28:35,824 INFO L226 Difference]: Without dead ends: 15803 [2019-11-28 00:28:35,841 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 00:28:35,856 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15803 states. [2019-11-28 00:28:36,707 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15803 to 15713. [2019-11-28 00:28:36,707 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15713 states. [2019-11-28 00:28:36,726 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15713 states to 15713 states and 23443 transitions. [2019-11-28 00:28:36,726 INFO L78 Accepts]: Start accepts. Automaton has 15713 states and 23443 transitions. Word has length 86 [2019-11-28 00:28:36,726 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:36,727 INFO L462 AbstractCegarLoop]: Abstraction has 15713 states and 23443 transitions. [2019-11-28 00:28:36,727 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 00:28:36,727 INFO L276 IsEmpty]: Start isEmpty. Operand 15713 states and 23443 transitions. [2019-11-28 00:28:36,733 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2019-11-28 00:28:36,733 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:36,734 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:36,734 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:36,734 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:36,734 INFO L82 PathProgramCache]: Analyzing trace with hash -433884439, now seen corresponding path program 1 times [2019-11-28 00:28:36,735 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:36,735 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1408871774] [2019-11-28 00:28:36,735 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:36,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:36,762 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:36,763 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1408871774] [2019-11-28 00:28:36,763 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:36,763 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:36,764 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1726969282] [2019-11-28 00:28:36,764 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:36,764 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:36,764 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:36,765 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:36,765 INFO L87 Difference]: Start difference. First operand 15713 states and 23443 transitions. Second operand 3 states. [2019-11-28 00:28:37,221 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:37,222 INFO L93 Difference]: Finished difference Result 32195 states and 47984 transitions. [2019-11-28 00:28:37,222 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:37,222 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 86 [2019-11-28 00:28:37,222 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:37,251 INFO L225 Difference]: With dead ends: 32195 [2019-11-28 00:28:37,252 INFO L226 Difference]: Without dead ends: 16523 [2019-11-28 00:28:37,268 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:37,284 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16523 states. [2019-11-28 00:28:38,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16523 to 16443. [2019-11-28 00:28:38,042 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16443 states. [2019-11-28 00:28:38,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16443 states to 16443 states and 23815 transitions. [2019-11-28 00:28:38,080 INFO L78 Accepts]: Start accepts. Automaton has 16443 states and 23815 transitions. Word has length 86 [2019-11-28 00:28:38,081 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:38,081 INFO L462 AbstractCegarLoop]: Abstraction has 16443 states and 23815 transitions. [2019-11-28 00:28:38,081 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:38,081 INFO L276 IsEmpty]: Start isEmpty. Operand 16443 states and 23815 transitions. [2019-11-28 00:28:38,091 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2019-11-28 00:28:38,091 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:38,092 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:38,092 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:38,092 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:38,093 INFO L82 PathProgramCache]: Analyzing trace with hash -1869450223, now seen corresponding path program 1 times [2019-11-28 00:28:38,093 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:38,094 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1923505605] [2019-11-28 00:28:38,094 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:38,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:38,169 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:38,169 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1923505605] [2019-11-28 00:28:38,170 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:38,170 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:38,170 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1598366396] [2019-11-28 00:28:38,170 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:38,171 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:38,171 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:38,172 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:38,172 INFO L87 Difference]: Start difference. First operand 16443 states and 23815 transitions. Second operand 3 states. [2019-11-28 00:28:38,909 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:38,911 INFO L93 Difference]: Finished difference Result 33302 states and 48352 transitions. [2019-11-28 00:28:38,912 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:38,912 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 87 [2019-11-28 00:28:38,913 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:38,939 INFO L225 Difference]: With dead ends: 33302 [2019-11-28 00:28:38,940 INFO L226 Difference]: Without dead ends: 16920 [2019-11-28 00:28:38,958 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:38,973 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16920 states. [2019-11-28 00:28:39,385 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16920 to 13439. [2019-11-28 00:28:39,385 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13439 states. [2019-11-28 00:28:39,403 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13439 states to 13439 states and 18777 transitions. [2019-11-28 00:28:39,403 INFO L78 Accepts]: Start accepts. Automaton has 13439 states and 18777 transitions. Word has length 87 [2019-11-28 00:28:39,404 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:39,404 INFO L462 AbstractCegarLoop]: Abstraction has 13439 states and 18777 transitions. [2019-11-28 00:28:39,404 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:39,404 INFO L276 IsEmpty]: Start isEmpty. Operand 13439 states and 18777 transitions. [2019-11-28 00:28:39,412 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2019-11-28 00:28:39,412 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:39,412 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:39,413 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:39,413 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:39,413 INFO L82 PathProgramCache]: Analyzing trace with hash -2059863225, now seen corresponding path program 1 times [2019-11-28 00:28:39,414 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:39,414 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [724769349] [2019-11-28 00:28:39,414 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:39,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:39,448 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-11-28 00:28:39,449 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [724769349] [2019-11-28 00:28:39,449 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:39,449 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:39,449 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1146488002] [2019-11-28 00:28:39,450 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:39,450 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:39,450 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:39,450 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:39,451 INFO L87 Difference]: Start difference. First operand 13439 states and 18777 transitions. Second operand 3 states. [2019-11-28 00:28:39,895 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:39,895 INFO L93 Difference]: Finished difference Result 23921 states and 33457 transitions. [2019-11-28 00:28:39,896 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:39,896 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 88 [2019-11-28 00:28:39,896 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:39,919 INFO L225 Difference]: With dead ends: 23921 [2019-11-28 00:28:39,919 INFO L226 Difference]: Without dead ends: 15605 [2019-11-28 00:28:39,931 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:39,946 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15605 states. [2019-11-28 00:28:40,822 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15605 to 15125. [2019-11-28 00:28:40,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15125 states. [2019-11-28 00:28:40,838 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15125 states to 15125 states and 20656 transitions. [2019-11-28 00:28:40,839 INFO L78 Accepts]: Start accepts. Automaton has 15125 states and 20656 transitions. Word has length 88 [2019-11-28 00:28:40,839 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:40,839 INFO L462 AbstractCegarLoop]: Abstraction has 15125 states and 20656 transitions. [2019-11-28 00:28:40,839 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:40,839 INFO L276 IsEmpty]: Start isEmpty. Operand 15125 states and 20656 transitions. [2019-11-28 00:28:40,855 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2019-11-28 00:28:40,855 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:40,855 INFO L410 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:40,855 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:40,855 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:40,856 INFO L82 PathProgramCache]: Analyzing trace with hash 1061949686, now seen corresponding path program 1 times [2019-11-28 00:28:40,856 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:40,856 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [570681126] [2019-11-28 00:28:40,856 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:40,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:40,892 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2019-11-28 00:28:40,892 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [570681126] [2019-11-28 00:28:40,893 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:40,893 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:40,893 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [159894812] [2019-11-28 00:28:40,894 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:40,894 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:40,894 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:40,894 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:40,895 INFO L87 Difference]: Start difference. First operand 15125 states and 20656 transitions. Second operand 3 states. [2019-11-28 00:28:41,288 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:41,289 INFO L93 Difference]: Finished difference Result 29488 states and 40230 transitions. [2019-11-28 00:28:41,289 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:41,289 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 115 [2019-11-28 00:28:41,289 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:41,305 INFO L225 Difference]: With dead ends: 29488 [2019-11-28 00:28:41,305 INFO L226 Difference]: Without dead ends: 15055 [2019-11-28 00:28:41,317 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:41,331 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15055 states. [2019-11-28 00:28:41,720 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15055 to 15055. [2019-11-28 00:28:41,720 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15055 states. [2019-11-28 00:28:41,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15055 states to 15055 states and 20502 transitions. [2019-11-28 00:28:41,737 INFO L78 Accepts]: Start accepts. Automaton has 15055 states and 20502 transitions. Word has length 115 [2019-11-28 00:28:41,737 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:41,737 INFO L462 AbstractCegarLoop]: Abstraction has 15055 states and 20502 transitions. [2019-11-28 00:28:41,737 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:41,737 INFO L276 IsEmpty]: Start isEmpty. Operand 15055 states and 20502 transitions. [2019-11-28 00:28:41,751 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 127 [2019-11-28 00:28:41,751 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:41,751 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:41,751 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:41,752 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:41,752 INFO L82 PathProgramCache]: Analyzing trace with hash -1410428474, now seen corresponding path program 1 times [2019-11-28 00:28:41,752 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:41,752 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2021497457] [2019-11-28 00:28:41,752 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:41,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:41,782 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2019-11-28 00:28:41,782 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2021497457] [2019-11-28 00:28:41,783 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:41,783 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:41,783 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1568933645] [2019-11-28 00:28:41,784 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:41,784 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:41,784 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:41,784 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:41,785 INFO L87 Difference]: Start difference. First operand 15055 states and 20502 transitions. Second operand 3 states. [2019-11-28 00:28:42,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:42,122 INFO L93 Difference]: Finished difference Result 25586 states and 34782 transitions. [2019-11-28 00:28:42,122 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:42,122 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 126 [2019-11-28 00:28:42,122 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:42,134 INFO L225 Difference]: With dead ends: 25586 [2019-11-28 00:28:42,134 INFO L226 Difference]: Without dead ends: 10588 [2019-11-28 00:28:42,145 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:42,151 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10588 states. [2019-11-28 00:28:42,759 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10588 to 8620. [2019-11-28 00:28:42,759 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8620 states. [2019-11-28 00:28:42,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8620 states to 8620 states and 11274 transitions. [2019-11-28 00:28:42,768 INFO L78 Accepts]: Start accepts. Automaton has 8620 states and 11274 transitions. Word has length 126 [2019-11-28 00:28:42,768 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:42,768 INFO L462 AbstractCegarLoop]: Abstraction has 8620 states and 11274 transitions. [2019-11-28 00:28:42,769 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:42,769 INFO L276 IsEmpty]: Start isEmpty. Operand 8620 states and 11274 transitions. [2019-11-28 00:28:42,779 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2019-11-28 00:28:42,779 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:42,779 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:42,780 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:42,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:42,780 INFO L82 PathProgramCache]: Analyzing trace with hash 314934891, now seen corresponding path program 1 times [2019-11-28 00:28:42,780 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:42,781 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1423549013] [2019-11-28 00:28:42,781 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:42,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:42,817 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 43 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2019-11-28 00:28:42,818 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1423549013] [2019-11-28 00:28:42,818 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:42,818 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:42,819 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1168862598] [2019-11-28 00:28:42,819 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:42,819 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:42,819 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:42,820 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:42,820 INFO L87 Difference]: Start difference. First operand 8620 states and 11274 transitions. Second operand 3 states. [2019-11-28 00:28:43,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:43,056 INFO L93 Difference]: Finished difference Result 14199 states and 18567 transitions. [2019-11-28 00:28:43,057 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:43,057 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 127 [2019-11-28 00:28:43,057 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:43,064 INFO L225 Difference]: With dead ends: 14199 [2019-11-28 00:28:43,064 INFO L226 Difference]: Without dead ends: 6733 [2019-11-28 00:28:43,070 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:43,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6733 states. [2019-11-28 00:28:43,239 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6733 to 6149. [2019-11-28 00:28:43,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6149 states. [2019-11-28 00:28:43,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6149 states to 6149 states and 7873 transitions. [2019-11-28 00:28:43,245 INFO L78 Accepts]: Start accepts. Automaton has 6149 states and 7873 transitions. Word has length 127 [2019-11-28 00:28:43,245 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:43,246 INFO L462 AbstractCegarLoop]: Abstraction has 6149 states and 7873 transitions. [2019-11-28 00:28:43,246 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:43,246 INFO L276 IsEmpty]: Start isEmpty. Operand 6149 states and 7873 transitions. [2019-11-28 00:28:43,252 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2019-11-28 00:28:43,252 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:43,252 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:43,253 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:43,253 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:43,253 INFO L82 PathProgramCache]: Analyzing trace with hash -146147841, now seen corresponding path program 1 times [2019-11-28 00:28:43,253 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:43,254 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [452783961] [2019-11-28 00:28:43,254 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:43,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:43,299 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2019-11-28 00:28:43,300 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [452783961] [2019-11-28 00:28:43,300 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:43,300 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:43,301 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [942892293] [2019-11-28 00:28:43,301 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:43,301 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:43,301 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:43,302 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:43,302 INFO L87 Difference]: Start difference. First operand 6149 states and 7873 transitions. Second operand 3 states. [2019-11-28 00:28:43,529 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:43,529 INFO L93 Difference]: Finished difference Result 11907 states and 15226 transitions. [2019-11-28 00:28:43,530 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:43,530 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 133 [2019-11-28 00:28:43,530 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:43,535 INFO L225 Difference]: With dead ends: 11907 [2019-11-28 00:28:43,535 INFO L226 Difference]: Without dead ends: 6149 [2019-11-28 00:28:43,538 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:43,541 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6149 states. [2019-11-28 00:28:43,695 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6149 to 6109. [2019-11-28 00:28:43,695 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6109 states. [2019-11-28 00:28:43,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6109 states to 6109 states and 7791 transitions. [2019-11-28 00:28:43,701 INFO L78 Accepts]: Start accepts. Automaton has 6109 states and 7791 transitions. Word has length 133 [2019-11-28 00:28:43,701 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:43,701 INFO L462 AbstractCegarLoop]: Abstraction has 6109 states and 7791 transitions. [2019-11-28 00:28:43,701 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:43,701 INFO L276 IsEmpty]: Start isEmpty. Operand 6109 states and 7791 transitions. [2019-11-28 00:28:43,706 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2019-11-28 00:28:43,706 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:43,707 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:43,707 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:43,707 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:43,707 INFO L82 PathProgramCache]: Analyzing trace with hash 1797709215, now seen corresponding path program 1 times [2019-11-28 00:28:43,708 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:43,708 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1013087011] [2019-11-28 00:28:43,708 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:43,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:43,745 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2019-11-28 00:28:43,745 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1013087011] [2019-11-28 00:28:43,745 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:43,746 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:43,746 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1622066649] [2019-11-28 00:28:43,746 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:43,747 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:43,747 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:43,747 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:43,747 INFO L87 Difference]: Start difference. First operand 6109 states and 7791 transitions. Second operand 3 states. [2019-11-28 00:28:44,107 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:44,107 INFO L93 Difference]: Finished difference Result 11855 states and 15104 transitions. [2019-11-28 00:28:44,108 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:44,108 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 133 [2019-11-28 00:28:44,109 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:44,117 INFO L225 Difference]: With dead ends: 11855 [2019-11-28 00:28:44,117 INFO L226 Difference]: Without dead ends: 6118 [2019-11-28 00:28:44,123 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:44,129 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6118 states. [2019-11-28 00:28:44,386 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6118 to 6078. [2019-11-28 00:28:44,386 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6078 states. [2019-11-28 00:28:44,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6078 states to 6078 states and 7719 transitions. [2019-11-28 00:28:44,393 INFO L78 Accepts]: Start accepts. Automaton has 6078 states and 7719 transitions. Word has length 133 [2019-11-28 00:28:44,393 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:44,393 INFO L462 AbstractCegarLoop]: Abstraction has 6078 states and 7719 transitions. [2019-11-28 00:28:44,393 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:44,393 INFO L276 IsEmpty]: Start isEmpty. Operand 6078 states and 7719 transitions. [2019-11-28 00:28:44,397 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2019-11-28 00:28:44,398 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:44,398 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:44,398 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:44,398 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:44,399 INFO L82 PathProgramCache]: Analyzing trace with hash 282610594, now seen corresponding path program 1 times [2019-11-28 00:28:44,399 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:44,399 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2033907184] [2019-11-28 00:28:44,399 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:44,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:44,432 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 46 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2019-11-28 00:28:44,433 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2033907184] [2019-11-28 00:28:44,433 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:44,433 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:44,433 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1228473383] [2019-11-28 00:28:44,433 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:44,434 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:44,434 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:44,434 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:44,434 INFO L87 Difference]: Start difference. First operand 6078 states and 7719 transitions. Second operand 3 states. [2019-11-28 00:28:44,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:44,713 INFO L93 Difference]: Finished difference Result 10860 states and 13837 transitions. [2019-11-28 00:28:44,713 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:44,714 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 136 [2019-11-28 00:28:44,714 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:44,722 INFO L225 Difference]: With dead ends: 10860 [2019-11-28 00:28:44,722 INFO L226 Difference]: Without dead ends: 5146 [2019-11-28 00:28:44,729 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:44,733 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5146 states. [2019-11-28 00:28:44,970 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5146 to 5076. [2019-11-28 00:28:44,970 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5076 states. [2019-11-28 00:28:44,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5076 states to 5076 states and 6341 transitions. [2019-11-28 00:28:44,979 INFO L78 Accepts]: Start accepts. Automaton has 5076 states and 6341 transitions. Word has length 136 [2019-11-28 00:28:44,979 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:44,979 INFO L462 AbstractCegarLoop]: Abstraction has 5076 states and 6341 transitions. [2019-11-28 00:28:44,979 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:44,980 INFO L276 IsEmpty]: Start isEmpty. Operand 5076 states and 6341 transitions. [2019-11-28 00:28:44,984 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2019-11-28 00:28:44,984 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:44,984 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:44,985 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:44,985 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:44,985 INFO L82 PathProgramCache]: Analyzing trace with hash -1519116211, now seen corresponding path program 1 times [2019-11-28 00:28:44,985 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:44,985 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1771541398] [2019-11-28 00:28:44,986 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:44,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:45,048 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 45 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2019-11-28 00:28:45,049 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1771541398] [2019-11-28 00:28:45,049 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:45,049 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:45,050 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [585664390] [2019-11-28 00:28:45,050 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:45,050 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:45,051 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:45,051 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:45,051 INFO L87 Difference]: Start difference. First operand 5076 states and 6341 transitions. Second operand 3 states. [2019-11-28 00:28:45,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:45,279 INFO L93 Difference]: Finished difference Result 9133 states and 11446 transitions. [2019-11-28 00:28:45,280 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:45,280 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 136 [2019-11-28 00:28:45,281 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:45,287 INFO L225 Difference]: With dead ends: 9133 [2019-11-28 00:28:45,288 INFO L226 Difference]: Without dead ends: 4098 [2019-11-28 00:28:45,294 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:45,299 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4098 states. [2019-11-28 00:28:45,603 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4098 to 4080. [2019-11-28 00:28:45,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4080 states. [2019-11-28 00:28:45,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4080 states to 4080 states and 5008 transitions. [2019-11-28 00:28:45,611 INFO L78 Accepts]: Start accepts. Automaton has 4080 states and 5008 transitions. Word has length 136 [2019-11-28 00:28:45,612 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:45,612 INFO L462 AbstractCegarLoop]: Abstraction has 4080 states and 5008 transitions. [2019-11-28 00:28:45,612 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:45,612 INFO L276 IsEmpty]: Start isEmpty. Operand 4080 states and 5008 transitions. [2019-11-28 00:28:45,618 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 170 [2019-11-28 00:28:45,619 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:45,619 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:45,620 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:45,620 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:45,620 INFO L82 PathProgramCache]: Analyzing trace with hash -1856914244, now seen corresponding path program 1 times [2019-11-28 00:28:45,620 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:45,621 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [204014624] [2019-11-28 00:28:45,621 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:45,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:45,697 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 75 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2019-11-28 00:28:45,698 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [204014624] [2019-11-28 00:28:45,698 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:45,698 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:45,699 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1956156136] [2019-11-28 00:28:45,699 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:45,700 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:45,700 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:45,700 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:45,701 INFO L87 Difference]: Start difference. First operand 4080 states and 5008 transitions. Second operand 3 states. [2019-11-28 00:28:45,924 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:45,924 INFO L93 Difference]: Finished difference Result 7575 states and 9357 transitions. [2019-11-28 00:28:45,925 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:45,925 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 169 [2019-11-28 00:28:45,925 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:45,929 INFO L225 Difference]: With dead ends: 7575 [2019-11-28 00:28:45,929 INFO L226 Difference]: Without dead ends: 3771 [2019-11-28 00:28:45,932 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:45,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3771 states. [2019-11-28 00:28:46,082 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3771 to 3560. [2019-11-28 00:28:46,083 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3560 states. [2019-11-28 00:28:46,087 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3560 states to 3560 states and 4335 transitions. [2019-11-28 00:28:46,088 INFO L78 Accepts]: Start accepts. Automaton has 3560 states and 4335 transitions. Word has length 169 [2019-11-28 00:28:46,088 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:46,088 INFO L462 AbstractCegarLoop]: Abstraction has 3560 states and 4335 transitions. [2019-11-28 00:28:46,089 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:46,089 INFO L276 IsEmpty]: Start isEmpty. Operand 3560 states and 4335 transitions. [2019-11-28 00:28:46,092 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2019-11-28 00:28:46,093 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:46,093 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:46,094 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:46,094 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:46,094 INFO L82 PathProgramCache]: Analyzing trace with hash 38014472, now seen corresponding path program 1 times [2019-11-28 00:28:46,094 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:46,095 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2077684703] [2019-11-28 00:28:46,095 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:46,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:46,155 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 82 proven. 0 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2019-11-28 00:28:46,155 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2077684703] [2019-11-28 00:28:46,156 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:46,156 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:46,156 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [783395544] [2019-11-28 00:28:46,157 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:46,157 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:46,158 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:46,158 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:46,158 INFO L87 Difference]: Start difference. First operand 3560 states and 4335 transitions. Second operand 3 states. [2019-11-28 00:28:46,497 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:46,497 INFO L93 Difference]: Finished difference Result 8918 states and 10901 transitions. [2019-11-28 00:28:46,497 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:46,497 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 176 [2019-11-28 00:28:46,498 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:46,503 INFO L225 Difference]: With dead ends: 8918 [2019-11-28 00:28:46,503 INFO L226 Difference]: Without dead ends: 5634 [2019-11-28 00:28:46,507 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:46,511 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5634 states. [2019-11-28 00:28:46,664 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5634 to 5414. [2019-11-28 00:28:46,664 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5414 states. [2019-11-28 00:28:46,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5414 states to 5414 states and 6513 transitions. [2019-11-28 00:28:46,671 INFO L78 Accepts]: Start accepts. Automaton has 5414 states and 6513 transitions. Word has length 176 [2019-11-28 00:28:46,671 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:46,671 INFO L462 AbstractCegarLoop]: Abstraction has 5414 states and 6513 transitions. [2019-11-28 00:28:46,672 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:46,672 INFO L276 IsEmpty]: Start isEmpty. Operand 5414 states and 6513 transitions. [2019-11-28 00:28:46,675 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-11-28 00:28:46,675 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:46,675 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:46,676 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:46,676 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:46,676 INFO L82 PathProgramCache]: Analyzing trace with hash -1974043446, now seen corresponding path program 1 times [2019-11-28 00:28:46,676 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:46,676 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1791456426] [2019-11-28 00:28:46,676 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:46,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:46,721 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 79 proven. 0 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2019-11-28 00:28:46,722 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1791456426] [2019-11-28 00:28:46,722 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:46,722 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:46,723 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [218206209] [2019-11-28 00:28:46,723 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:46,723 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:46,724 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:46,724 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:46,724 INFO L87 Difference]: Start difference. First operand 5414 states and 6513 transitions. Second operand 3 states. [2019-11-28 00:28:46,883 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:46,883 INFO L93 Difference]: Finished difference Result 8838 states and 10694 transitions. [2019-11-28 00:28:46,883 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:46,883 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 179 [2019-11-28 00:28:46,883 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:46,886 INFO L225 Difference]: With dead ends: 8838 [2019-11-28 00:28:46,887 INFO L226 Difference]: Without dead ends: 3700 [2019-11-28 00:28:46,890 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:46,892 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3700 states. [2019-11-28 00:28:46,989 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3700 to 3094. [2019-11-28 00:28:46,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3094 states. [2019-11-28 00:28:46,992 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3094 states to 3094 states and 3684 transitions. [2019-11-28 00:28:46,992 INFO L78 Accepts]: Start accepts. Automaton has 3094 states and 3684 transitions. Word has length 179 [2019-11-28 00:28:46,992 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:46,992 INFO L462 AbstractCegarLoop]: Abstraction has 3094 states and 3684 transitions. [2019-11-28 00:28:46,992 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:46,993 INFO L276 IsEmpty]: Start isEmpty. Operand 3094 states and 3684 transitions. [2019-11-28 00:28:46,994 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-11-28 00:28:46,995 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:46,995 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:46,995 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:46,995 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:46,995 INFO L82 PathProgramCache]: Analyzing trace with hash -831540980, now seen corresponding path program 1 times [2019-11-28 00:28:46,995 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:46,996 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1812779606] [2019-11-28 00:28:46,996 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:47,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:47,047 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 91 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-11-28 00:28:47,047 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1812779606] [2019-11-28 00:28:47,047 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:47,047 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 00:28:47,047 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [257342692] [2019-11-28 00:28:47,048 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 00:28:47,048 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:47,048 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 00:28:47,048 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 00:28:47,048 INFO L87 Difference]: Start difference. First operand 3094 states and 3684 transitions. Second operand 4 states. [2019-11-28 00:28:47,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:47,187 INFO L93 Difference]: Finished difference Result 4689 states and 5567 transitions. [2019-11-28 00:28:47,187 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 00:28:47,188 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 179 [2019-11-28 00:28:47,188 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:47,190 INFO L225 Difference]: With dead ends: 4689 [2019-11-28 00:28:47,190 INFO L226 Difference]: Without dead ends: 1871 [2019-11-28 00:28:47,192 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 00:28:47,193 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1871 states. [2019-11-28 00:28:47,268 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1871 to 1584. [2019-11-28 00:28:47,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1584 states. [2019-11-28 00:28:47,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1584 states to 1584 states and 1844 transitions. [2019-11-28 00:28:47,270 INFO L78 Accepts]: Start accepts. Automaton has 1584 states and 1844 transitions. Word has length 179 [2019-11-28 00:28:47,270 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:47,270 INFO L462 AbstractCegarLoop]: Abstraction has 1584 states and 1844 transitions. [2019-11-28 00:28:47,270 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 00:28:47,270 INFO L276 IsEmpty]: Start isEmpty. Operand 1584 states and 1844 transitions. [2019-11-28 00:28:47,271 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 184 [2019-11-28 00:28:47,271 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:47,271 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:47,271 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:47,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:47,272 INFO L82 PathProgramCache]: Analyzing trace with hash 1681635082, now seen corresponding path program 1 times [2019-11-28 00:28:47,272 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:47,272 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [738990443] [2019-11-28 00:28:47,272 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:47,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:47,326 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 100 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-28 00:28:47,328 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [738990443] [2019-11-28 00:28:47,328 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:47,328 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:47,328 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1445933512] [2019-11-28 00:28:47,329 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:47,329 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:47,329 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:47,329 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:47,329 INFO L87 Difference]: Start difference. First operand 1584 states and 1844 transitions. Second operand 3 states. [2019-11-28 00:28:47,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:47,471 INFO L93 Difference]: Finished difference Result 4040 states and 4732 transitions. [2019-11-28 00:28:47,471 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:47,471 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 183 [2019-11-28 00:28:47,472 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:47,475 INFO L225 Difference]: With dead ends: 4040 [2019-11-28 00:28:47,475 INFO L226 Difference]: Without dead ends: 2426 [2019-11-28 00:28:47,477 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:47,479 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2426 states. [2019-11-28 00:28:47,559 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2426 to 2416. [2019-11-28 00:28:47,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2416 states. [2019-11-28 00:28:47,562 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2416 states to 2416 states and 2812 transitions. [2019-11-28 00:28:47,562 INFO L78 Accepts]: Start accepts. Automaton has 2416 states and 2812 transitions. Word has length 183 [2019-11-28 00:28:47,562 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:47,562 INFO L462 AbstractCegarLoop]: Abstraction has 2416 states and 2812 transitions. [2019-11-28 00:28:47,562 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:47,563 INFO L276 IsEmpty]: Start isEmpty. Operand 2416 states and 2812 transitions. [2019-11-28 00:28:47,564 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 184 [2019-11-28 00:28:47,564 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:47,564 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:47,564 INFO L410 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:47,565 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:47,565 INFO L82 PathProgramCache]: Analyzing trace with hash 1256160142, now seen corresponding path program 1 times [2019-11-28 00:28:47,565 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:47,565 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1605898195] [2019-11-28 00:28:47,565 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:47,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:47,614 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 93 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-11-28 00:28:47,615 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1605898195] [2019-11-28 00:28:47,615 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:47,615 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:47,615 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [438522422] [2019-11-28 00:28:47,616 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:47,616 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:47,616 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:47,616 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:47,616 INFO L87 Difference]: Start difference. First operand 2416 states and 2812 transitions. Second operand 3 states. [2019-11-28 00:28:47,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:47,713 INFO L93 Difference]: Finished difference Result 3364 states and 3884 transitions. [2019-11-28 00:28:47,713 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:47,713 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 183 [2019-11-28 00:28:47,714 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:47,715 INFO L225 Difference]: With dead ends: 3364 [2019-11-28 00:28:47,715 INFO L226 Difference]: Without dead ends: 1214 [2019-11-28 00:28:47,717 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:47,718 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1214 states. [2019-11-28 00:28:47,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1214 to 1192. [2019-11-28 00:28:47,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1192 states. [2019-11-28 00:28:47,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1192 states to 1192 states and 1317 transitions. [2019-11-28 00:28:47,789 INFO L78 Accepts]: Start accepts. Automaton has 1192 states and 1317 transitions. Word has length 183 [2019-11-28 00:28:47,789 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:47,789 INFO L462 AbstractCegarLoop]: Abstraction has 1192 states and 1317 transitions. [2019-11-28 00:28:47,789 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:47,789 INFO L276 IsEmpty]: Start isEmpty. Operand 1192 states and 1317 transitions. [2019-11-28 00:28:47,791 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 185 [2019-11-28 00:28:47,791 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:47,791 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:47,791 INFO L410 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:47,792 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:47,792 INFO L82 PathProgramCache]: Analyzing trace with hash 1772258692, now seen corresponding path program 1 times [2019-11-28 00:28:47,792 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:47,792 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1942359959] [2019-11-28 00:28:47,792 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:47,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 00:28:47,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 00:28:47,945 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-28 00:28:47,946 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-28 00:28:48,169 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 12:28:48 BoogieIcfgContainer [2019-11-28 00:28:48,174 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-28 00:28:48,175 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-28 00:28:48,175 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-28 00:28:48,175 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-28 00:28:48,176 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 12:28:25" (3/4) ... [2019-11-28 00:28:48,178 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-28 00:28:48,412 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2019-11-28 00:28:48,413 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-28 00:28:48,415 INFO L168 Benchmark]: Toolchain (without parser) took 24707.88 ms. Allocated memory was 1.0 GB in the beginning and 3.2 GB in the end (delta: 2.2 GB). Free memory was 953.7 MB in the beginning and 1.7 GB in the end (delta: -712.6 MB). Peak memory consumption was 1.5 GB. Max. memory is 11.5 GB. [2019-11-28 00:28:48,416 INFO L168 Benchmark]: CDTParser took 0.29 ms. Allocated memory is still 1.0 GB. Free memory is still 981.8 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 00:28:48,416 INFO L168 Benchmark]: CACSL2BoogieTranslator took 482.49 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 129.5 MB). Free memory was 953.7 MB in the beginning and 1.1 GB in the end (delta: -165.4 MB). Peak memory consumption was 25.9 MB. Max. memory is 11.5 GB. [2019-11-28 00:28:48,416 INFO L168 Benchmark]: Boogie Procedure Inliner took 49.33 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 00:28:48,417 INFO L168 Benchmark]: Boogie Preprocessor took 45.36 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. [2019-11-28 00:28:48,417 INFO L168 Benchmark]: RCFGBuilder took 779.91 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 39.7 MB). Peak memory consumption was 39.7 MB. Max. memory is 11.5 GB. [2019-11-28 00:28:48,417 INFO L168 Benchmark]: TraceAbstraction took 23105.45 ms. Allocated memory was 1.2 GB in the beginning and 3.2 GB in the end (delta: 2.1 GB). Free memory was 1.1 GB in the beginning and 1.7 GB in the end (delta: -593.6 MB). Peak memory consumption was 1.5 GB. Max. memory is 11.5 GB. [2019-11-28 00:28:48,418 INFO L168 Benchmark]: Witness Printer took 238.06 ms. Allocated memory is still 3.2 GB. Free memory was 1.7 GB in the beginning and 1.7 GB in the end (delta: 24 B). Peak memory consumption was 24 B. Max. memory is 11.5 GB. [2019-11-28 00:28:48,420 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.29 ms. Allocated memory is still 1.0 GB. Free memory is still 981.8 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 482.49 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 129.5 MB). Free memory was 953.7 MB in the beginning and 1.1 GB in the end (delta: -165.4 MB). Peak memory consumption was 25.9 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 49.33 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 45.36 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 779.91 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 39.7 MB). Peak memory consumption was 39.7 MB. Max. memory is 11.5 GB. * TraceAbstraction took 23105.45 ms. Allocated memory was 1.2 GB in the beginning and 3.2 GB in the end (delta: 2.1 GB). Free memory was 1.1 GB in the beginning and 1.7 GB in the end (delta: -593.6 MB). Peak memory consumption was 1.5 GB. Max. memory is 11.5 GB. * Witness Printer took 238.06 ms. Allocated memory is still 3.2 GB. Free memory was 1.7 GB in the beginning and 1.7 GB in the end (delta: 24 B). Peak memory consumption was 24 B. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 13]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L18] int c ; [L19] int c_t ; [L20] int c_req_up ; [L21] int p_in ; [L22] int p_out ; [L23] int wl_st ; [L24] int c1_st ; [L25] int c2_st ; [L26] int wb_st ; [L27] int r_st ; [L28] int wl_i ; [L29] int c1_i ; [L30] int c2_i ; [L31] int wb_i ; [L32] int r_i ; [L33] int wl_pc ; [L34] int c1_pc ; [L35] int c2_pc ; [L36] int wb_pc ; [L37] int e_e ; [L38] int e_f ; [L39] int e_g ; [L40] int e_c ; [L41] int e_p_in ; [L42] int e_wl ; [L48] int d ; [L49] int data ; [L50] int processed ; [L51] static int t_b ; VAL [c=0, c1_i=0, c1_pc=0, c1_st=0, c2_i=0, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=0, e_e=0, e_f=0, e_g=0, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=0, wb_pc=0, wb_st=0, wl_i=0, wl_pc=0, wl_st=0] [L679] int __retres1 ; [L683] e_wl = 2 [L684] e_c = e_wl [L685] e_g = e_c [L686] e_f = e_g [L687] e_e = e_f [L688] wl_pc = 0 [L689] c1_pc = 0 [L690] c2_pc = 0 [L691] wb_pc = 0 [L692] wb_i = 1 [L693] c2_i = wb_i [L694] c1_i = c2_i [L695] wl_i = c1_i [L696] r_i = 0 [L697] c_req_up = 0 [L698] d = 0 [L699] c = 0 [L390] int kernel_st ; [L393] kernel_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L394] COND FALSE !((int )c_req_up == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L405] COND TRUE (int )wl_i == 1 [L406] wl_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L410] COND TRUE (int )c1_i == 1 [L411] c1_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L415] COND TRUE (int )c2_i == 1 [L416] c2_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L420] COND TRUE (int )wb_i == 1 [L421] wb_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L425] COND FALSE !((int )r_i == 1) [L428] r_st = 2 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L430] COND FALSE !((int )e_f == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L435] COND FALSE !((int )e_g == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L440] COND FALSE !((int )e_e == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L445] COND FALSE !((int )e_c == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L450] COND FALSE !((int )e_wl == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L455] COND FALSE !((int )wl_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L463] COND FALSE !((int )wl_pc == 2) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L473] COND FALSE !((int )c1_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L482] COND FALSE !((int )c2_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L491] COND FALSE !((int )wb_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L500] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L505] COND FALSE !((int )e_e == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L510] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L515] COND FALSE !((int )e_g == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L520] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L525] COND FALSE !((int )e_wl == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L531] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L534] kernel_st = 1 [L276] int tmp ; [L277] int tmp___0 ; [L278] int tmp___1 ; [L279] int tmp___2 ; [L280] int tmp___3 ; VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L284] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L286] COND TRUE (int )wl_st == 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L307] COND TRUE (int )wl_st == 0 [L309] tmp = __VERIFIER_nondet_int() [L311] COND TRUE \read(tmp) [L313] wl_st = 1 [L53] int t ; VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L56] COND TRUE (int )wl_pc == 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L70] wl_st = 2 [L71] wl_pc = 1 [L72] e_wl = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L322] COND TRUE (int )c1_st == 0 [L324] tmp___0 = __VERIFIER_nondet_int() [L326] COND TRUE \read(tmp___0) [L328] c1_st = 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L127] COND TRUE (int )c1_pc == 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L138] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L140] c1_st = 2 [L141] c1_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L337] COND TRUE (int )c2_st == 0 [L339] tmp___1 = __VERIFIER_nondet_int() [L341] COND TRUE \read(tmp___1) [L343] c2_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L172] COND TRUE (int )c2_pc == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L183] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L185] c2_st = 2 [L186] c2_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L352] COND TRUE (int )wb_st == 0 [L354] tmp___2 = __VERIFIER_nondet_int() [L356] COND TRUE \read(tmp___2) [L358] wb_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L217] COND TRUE (int )wb_pc == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L228] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L230] wb_st = 2 [L231] wb_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L367] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L284] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L286] COND FALSE !((int )wl_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L289] COND FALSE !((int )c1_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L292] COND FALSE !((int )c2_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L295] COND FALSE !((int )wb_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L298] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L537] kernel_st = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L538] COND FALSE !((int )c_req_up == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L549] kernel_st = 3 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L550] COND FALSE !((int )e_f == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L555] COND FALSE !((int )e_g == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L560] COND FALSE !((int )e_e == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L565] COND FALSE !((int )e_c == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L570] COND TRUE (int )e_wl == 0 [L571] e_wl = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L575] COND TRUE (int )wl_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L576] COND TRUE (int )e_wl == 1 [L577] wl_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L593] COND TRUE (int )c1_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L594] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L602] COND TRUE (int )c2_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L603] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L611] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L612] COND FALSE !((int )e_g == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L620] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L625] COND FALSE !((int )e_e == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L630] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L635] COND FALSE !((int )e_g == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L640] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L645] COND TRUE (int )e_wl == 1 [L646] e_wl = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L650] COND TRUE (int )wl_st == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L531] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L534] kernel_st = 1 [L276] int tmp ; [L277] int tmp___0 ; [L278] int tmp___1 ; [L279] int tmp___2 ; [L280] int tmp___3 ; VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L284] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L286] COND TRUE (int )wl_st == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L307] COND TRUE (int )wl_st == 0 [L309] tmp = __VERIFIER_nondet_int() [L311] COND TRUE \read(tmp) [L313] wl_st = 1 [L53] int t ; VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L56] COND FALSE !((int )wl_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L59] COND FALSE !((int )wl_pc == 2) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L62] COND TRUE (int )wl_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L77] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L79] t = d [L80] data = d [L81] processed = 0 [L82] e_f = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L83] COND TRUE (int )c1_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L84] COND TRUE (int )e_f == 1 [L85] c1_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L92] COND TRUE (int )c2_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L93] COND TRUE (int )e_f == 1 [L94] c2_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L101] e_f = 2 [L102] wl_st = 2 [L103] wl_pc = 2 [L104] t_b = t VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L322] COND TRUE (int )c1_st == 0 [L324] tmp___0 = __VERIFIER_nondet_int() [L326] COND TRUE \read(tmp___0) [L328] c1_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L127] COND FALSE !((int )c1_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L130] COND TRUE (int )c1_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L145] COND TRUE ! processed [L146] data += 1 [L147] e_g = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L148] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L149] COND TRUE (int )e_g == 1 [L150] wb_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L157] e_g = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L138] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L140] c1_st = 2 [L141] c1_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L337] COND TRUE (int )c2_st == 0 [L339] tmp___1 = __VERIFIER_nondet_int() [L341] COND TRUE \read(tmp___1) [L343] c2_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L172] COND FALSE !((int )c2_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L175] COND TRUE (int )c2_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L190] COND TRUE ! processed [L191] data += 1 [L192] e_g = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L193] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L194] COND TRUE (int )e_g == 1 [L195] wb_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L202] e_g = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L183] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L185] c2_st = 2 [L186] c2_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L352] COND TRUE (int )wb_st == 0 [L354] tmp___2 = __VERIFIER_nondet_int() [L356] COND TRUE \read(tmp___2) [L358] wb_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L217] COND FALSE !((int )wb_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L220] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L235] c_t = data [L236] c_req_up = 1 [L237] processed = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L228] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L230] wb_st = 2 [L231] wb_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L367] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L284] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L286] COND FALSE !((int )wl_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L289] COND FALSE !((int )c1_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L292] COND FALSE !((int )c2_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L295] COND FALSE !((int )wb_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L298] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L537] kernel_st = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L538] COND TRUE (int )c_req_up == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L539] COND TRUE c != c_t [L540] c = c_t [L541] e_c = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L545] c_req_up = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L549] kernel_st = 3 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L550] COND FALSE !((int )e_f == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L555] COND FALSE !((int )e_g == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L560] COND FALSE !((int )e_e == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L565] COND TRUE (int )e_c == 0 [L566] e_c = 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L570] COND FALSE !((int )e_wl == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L575] COND FALSE !((int )wl_pc == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L583] COND TRUE (int )wl_pc == 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L584] COND FALSE !((int )e_e == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L593] COND TRUE (int )c1_pc == 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L594] COND FALSE !((int )e_f == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L602] COND TRUE (int )c2_pc == 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L603] COND FALSE !((int )e_f == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L611] COND TRUE (int )wb_pc == 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L612] COND FALSE !((int )e_g == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L620] COND TRUE (int )e_c == 1 [L621] r_st = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L625] COND FALSE !((int )e_e == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L630] COND FALSE !((int )e_f == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L635] COND FALSE !((int )e_g == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L640] COND TRUE (int )e_c == 1 [L641] e_c = 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L645] COND FALSE !((int )e_wl == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L650] COND FALSE !((int )wl_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L653] COND FALSE !((int )c1_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L656] COND FALSE !((int )c2_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L659] COND FALSE !((int )wb_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L662] COND TRUE (int )r_st == 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L531] COND TRUE 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L534] kernel_st = 1 [L276] int tmp ; [L277] int tmp___0 ; [L278] int tmp___1 ; [L279] int tmp___2 ; [L280] int tmp___3 ; VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L284] COND TRUE 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L286] COND FALSE !((int )wl_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L289] COND FALSE !((int )c1_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L292] COND FALSE !((int )c2_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L295] COND FALSE !((int )wb_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L298] COND TRUE (int )r_st == 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L307] COND FALSE !((int )wl_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L322] COND FALSE !((int )c1_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L337] COND FALSE !((int )c2_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L352] COND FALSE !((int )wb_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L367] COND TRUE (int )r_st == 0 [L369] tmp___3 = __VERIFIER_nondet_int() [L371] COND TRUE \read(tmp___3) [L373] r_st = 1 [L249] d = c [L250] e_e = 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L251] COND FALSE !((int )wl_pc == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L259] COND TRUE (int )wl_pc == 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L260] COND TRUE (int )e_e == 1 [L261] wl_st = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L269] e_e = 2 [L270] r_st = 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L284] COND TRUE 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L286] COND TRUE (int )wl_st == 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L307] COND TRUE (int )wl_st == 0 [L309] tmp = __VERIFIER_nondet_int() [L311] COND TRUE \read(tmp) [L313] wl_st = 1 [L53] int t ; VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L56] COND FALSE !((int )wl_pc == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L59] COND TRUE (int )wl_pc == 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L108] t = t_b VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L109] COND FALSE !(d == t + 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L13] __VERIFIER_error() VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 125 locations, 1 error locations. Result: UNSAFE, OverallTime: 22.8s, OverallIterations: 37, TraceHistogramMax: 6, AutomataDifference: 10.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 7566 SDtfs, 5932 SDslu, 4273 SDs, 0 SdLazy, 705 SolverSat, 210 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.9s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 128 GetRequests, 76 SyntacticMatches, 2 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=16725occurred in iteration=19, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 10.0s AutomataMinimizationTime, 36 MinimizatonAttempts, 9031 StatesRemovedByMinimization, 30 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 0.4s SatisfiabilityAnalysisTime, 1.0s InterpolantComputationTime, 3325 NumberOfCodeBlocks, 3325 NumberOfCodeBlocksAsserted, 37 NumberOfCheckSat, 3105 ConstructedInterpolants, 0 QuantifiedInterpolants, 546256 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 36 InterpolantComputations, 36 PerfectInterpolantSequences, 1082/1082 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...