./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/systemc/transmitter.03.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 30f4e4ab Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx12G -Xms1G -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/systemc/transmitter.03.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 447c919af4e106e36f468570351956f4c77293d2 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.24-30f4e4a [2019-11-28 00:28:34,349 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-28 00:28:34,352 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-28 00:28:34,365 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-28 00:28:34,365 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-28 00:28:34,367 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-28 00:28:34,368 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-28 00:28:34,370 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-28 00:28:34,372 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-28 00:28:34,373 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-28 00:28:34,374 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-28 00:28:34,376 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-28 00:28:34,383 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-28 00:28:34,385 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-28 00:28:34,386 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-28 00:28:34,388 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-28 00:28:34,392 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-28 00:28:34,393 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-28 00:28:34,395 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-28 00:28:34,398 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-28 00:28:34,402 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-28 00:28:34,405 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-28 00:28:34,408 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-28 00:28:34,409 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-28 00:28:34,412 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-28 00:28:34,415 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-28 00:28:34,415 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-28 00:28:34,416 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-28 00:28:34,418 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-28 00:28:34,419 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-28 00:28:34,421 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-28 00:28:34,422 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-28 00:28:34,423 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-28 00:28:34,424 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-28 00:28:34,426 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-28 00:28:34,426 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-28 00:28:34,427 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-28 00:28:34,427 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-28 00:28:34,428 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-28 00:28:34,430 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-28 00:28:34,432 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-28 00:28:34,432 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-28 00:28:34,450 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-28 00:28:34,450 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-28 00:28:34,451 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-28 00:28:34,452 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-28 00:28:34,452 INFO L138 SettingsManager]: * Use SBE=true [2019-11-28 00:28:34,452 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-28 00:28:34,453 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-28 00:28:34,453 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-28 00:28:34,453 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-28 00:28:34,453 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-28 00:28:34,454 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-28 00:28:34,454 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-28 00:28:34,454 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-28 00:28:34,455 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-28 00:28:34,455 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-28 00:28:34,455 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-28 00:28:34,455 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-28 00:28:34,456 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-28 00:28:34,456 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-28 00:28:34,456 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-28 00:28:34,456 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-28 00:28:34,457 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 00:28:34,457 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-28 00:28:34,457 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-28 00:28:34,458 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-28 00:28:34,458 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-28 00:28:34,458 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-28 00:28:34,459 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-28 00:28:34,459 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 447c919af4e106e36f468570351956f4c77293d2 [2019-11-28 00:28:34,779 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-28 00:28:34,794 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-28 00:28:34,798 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-28 00:28:34,799 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-28 00:28:34,800 INFO L275 PluginConnector]: CDTParser initialized [2019-11-28 00:28:34,801 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.03.cil.c [2019-11-28 00:28:34,866 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/fcea2b182/1e826ae7ff254e90a1b2ae67721b8eda/FLAGf61f7586d [2019-11-28 00:28:35,379 INFO L306 CDTParser]: Found 1 translation units. [2019-11-28 00:28:35,380 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.03.cil.c [2019-11-28 00:28:35,391 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/fcea2b182/1e826ae7ff254e90a1b2ae67721b8eda/FLAGf61f7586d [2019-11-28 00:28:35,708 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/fcea2b182/1e826ae7ff254e90a1b2ae67721b8eda [2019-11-28 00:28:35,712 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-28 00:28:35,714 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-28 00:28:35,715 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-28 00:28:35,715 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-28 00:28:35,719 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-28 00:28:35,720 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 12:28:35" (1/1) ... [2019-11-28 00:28:35,723 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@331559d1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:35, skipping insertion in model container [2019-11-28 00:28:35,724 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 12:28:35" (1/1) ... [2019-11-28 00:28:35,732 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-11-28 00:28:35,784 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-11-28 00:28:36,072 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 00:28:36,080 INFO L203 MainTranslator]: Completed pre-run [2019-11-28 00:28:36,190 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 00:28:36,213 INFO L208 MainTranslator]: Completed translation [2019-11-28 00:28:36,214 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:36 WrapperNode [2019-11-28 00:28:36,214 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-28 00:28:36,215 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-28 00:28:36,215 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-28 00:28:36,216 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-28 00:28:36,226 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:36" (1/1) ... [2019-11-28 00:28:36,242 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:36" (1/1) ... [2019-11-28 00:28:36,297 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-28 00:28:36,298 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-28 00:28:36,298 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-28 00:28:36,298 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-28 00:28:36,312 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:36" (1/1) ... [2019-11-28 00:28:36,312 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:36" (1/1) ... [2019-11-28 00:28:36,317 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:36" (1/1) ... [2019-11-28 00:28:36,318 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:36" (1/1) ... [2019-11-28 00:28:36,332 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:36" (1/1) ... [2019-11-28 00:28:36,365 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:36" (1/1) ... [2019-11-28 00:28:36,369 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:36" (1/1) ... [2019-11-28 00:28:36,375 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-28 00:28:36,376 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-28 00:28:36,376 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-28 00:28:36,376 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-28 00:28:36,378 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:36" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 00:28:36,462 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-28 00:28:36,463 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-28 00:28:37,540 INFO L292 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-28 00:28:37,541 INFO L297 CfgBuilder]: Removed 119 assume(true) statements. [2019-11-28 00:28:37,542 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 12:28:37 BoogieIcfgContainer [2019-11-28 00:28:37,542 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-28 00:28:37,544 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-28 00:28:37,544 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-28 00:28:37,550 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-28 00:28:37,551 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 12:28:35" (1/3) ... [2019-11-28 00:28:37,554 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4e15353f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 12:28:37, skipping insertion in model container [2019-11-28 00:28:37,555 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 12:28:36" (2/3) ... [2019-11-28 00:28:37,555 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4e15353f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 12:28:37, skipping insertion in model container [2019-11-28 00:28:37,556 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 12:28:37" (3/3) ... [2019-11-28 00:28:37,558 INFO L109 eAbstractionObserver]: Analyzing ICFG transmitter.03.cil.c [2019-11-28 00:28:37,569 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-28 00:28:37,577 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-11-28 00:28:37,588 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-11-28 00:28:37,618 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-28 00:28:37,618 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-28 00:28:37,619 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-28 00:28:37,619 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-28 00:28:37,619 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-28 00:28:37,619 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-28 00:28:37,620 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-28 00:28:37,620 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-28 00:28:37,644 INFO L276 IsEmpty]: Start isEmpty. Operand 276 states. [2019-11-28 00:28:37,653 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-28 00:28:37,653 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:37,655 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:37,655 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:37,660 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:37,661 INFO L82 PathProgramCache]: Analyzing trace with hash -1838342379, now seen corresponding path program 1 times [2019-11-28 00:28:37,668 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:37,669 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1569149610] [2019-11-28 00:28:37,669 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:37,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:37,838 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:37,839 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1569149610] [2019-11-28 00:28:37,841 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:37,841 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:37,843 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [315310419] [2019-11-28 00:28:37,849 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:37,850 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:37,864 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:37,866 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:37,868 INFO L87 Difference]: Start difference. First operand 276 states. Second operand 3 states. [2019-11-28 00:28:37,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:37,959 INFO L93 Difference]: Finished difference Result 547 states and 857 transitions. [2019-11-28 00:28:37,961 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:37,966 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-28 00:28:37,967 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:37,991 INFO L225 Difference]: With dead ends: 547 [2019-11-28 00:28:37,992 INFO L226 Difference]: Without dead ends: 272 [2019-11-28 00:28:38,004 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:38,027 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 272 states. [2019-11-28 00:28:38,073 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 272 to 272. [2019-11-28 00:28:38,074 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 272 states. [2019-11-28 00:28:38,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 272 states to 272 states and 412 transitions. [2019-11-28 00:28:38,080 INFO L78 Accepts]: Start accepts. Automaton has 272 states and 412 transitions. Word has length 61 [2019-11-28 00:28:38,081 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:38,081 INFO L462 AbstractCegarLoop]: Abstraction has 272 states and 412 transitions. [2019-11-28 00:28:38,081 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:38,082 INFO L276 IsEmpty]: Start isEmpty. Operand 272 states and 412 transitions. [2019-11-28 00:28:38,084 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-28 00:28:38,084 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:38,085 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:38,085 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:38,086 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:38,086 INFO L82 PathProgramCache]: Analyzing trace with hash 1195707667, now seen corresponding path program 1 times [2019-11-28 00:28:38,087 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:38,087 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1238770344] [2019-11-28 00:28:38,087 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:38,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:38,192 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:38,193 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1238770344] [2019-11-28 00:28:38,193 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:38,193 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 00:28:38,194 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1870757569] [2019-11-28 00:28:38,201 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:38,201 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:38,202 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:38,202 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:38,203 INFO L87 Difference]: Start difference. First operand 272 states and 412 transitions. Second operand 3 states. [2019-11-28 00:28:38,340 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:38,340 INFO L93 Difference]: Finished difference Result 730 states and 1104 transitions. [2019-11-28 00:28:38,341 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:38,341 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-28 00:28:38,342 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:38,346 INFO L225 Difference]: With dead ends: 730 [2019-11-28 00:28:38,346 INFO L226 Difference]: Without dead ends: 466 [2019-11-28 00:28:38,350 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:38,351 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 466 states. [2019-11-28 00:28:38,390 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 466 to 464. [2019-11-28 00:28:38,391 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-11-28 00:28:38,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 694 transitions. [2019-11-28 00:28:38,394 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 694 transitions. Word has length 61 [2019-11-28 00:28:38,394 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:38,394 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 694 transitions. [2019-11-28 00:28:38,394 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:38,395 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 694 transitions. [2019-11-28 00:28:38,397 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-28 00:28:38,397 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:38,397 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:38,398 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:38,398 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:38,398 INFO L82 PathProgramCache]: Analyzing trace with hash 266288339, now seen corresponding path program 1 times [2019-11-28 00:28:38,399 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:38,399 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [335221983] [2019-11-28 00:28:38,400 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:38,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:38,468 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:38,469 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [335221983] [2019-11-28 00:28:38,470 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:38,470 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 00:28:38,470 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [136781360] [2019-11-28 00:28:38,471 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:38,471 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:38,472 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:38,472 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:38,472 INFO L87 Difference]: Start difference. First operand 464 states and 694 transitions. Second operand 3 states. [2019-11-28 00:28:38,517 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:38,518 INFO L93 Difference]: Finished difference Result 919 states and 1375 transitions. [2019-11-28 00:28:38,518 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:38,519 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-28 00:28:38,519 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:38,522 INFO L225 Difference]: With dead ends: 919 [2019-11-28 00:28:38,522 INFO L226 Difference]: Without dead ends: 464 [2019-11-28 00:28:38,524 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:38,525 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-11-28 00:28:38,553 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-11-28 00:28:38,553 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-11-28 00:28:38,556 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 686 transitions. [2019-11-28 00:28:38,556 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 686 transitions. Word has length 61 [2019-11-28 00:28:38,556 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:38,557 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 686 transitions. [2019-11-28 00:28:38,557 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:38,557 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 686 transitions. [2019-11-28 00:28:38,559 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-28 00:28:38,560 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:38,560 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:38,560 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:38,561 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:38,561 INFO L82 PathProgramCache]: Analyzing trace with hash 710189013, now seen corresponding path program 1 times [2019-11-28 00:28:38,561 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:38,562 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1751393621] [2019-11-28 00:28:38,562 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:38,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:38,641 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:38,642 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1751393621] [2019-11-28 00:28:38,643 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:38,643 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 00:28:38,644 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1686390202] [2019-11-28 00:28:38,644 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:38,645 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:38,645 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:38,645 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:38,646 INFO L87 Difference]: Start difference. First operand 464 states and 686 transitions. Second operand 3 states. [2019-11-28 00:28:38,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:38,685 INFO L93 Difference]: Finished difference Result 918 states and 1358 transitions. [2019-11-28 00:28:38,686 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:38,686 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-28 00:28:38,686 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:38,689 INFO L225 Difference]: With dead ends: 918 [2019-11-28 00:28:38,689 INFO L226 Difference]: Without dead ends: 464 [2019-11-28 00:28:38,690 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:38,692 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-11-28 00:28:38,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-11-28 00:28:38,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-11-28 00:28:38,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 678 transitions. [2019-11-28 00:28:38,717 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 678 transitions. Word has length 61 [2019-11-28 00:28:38,718 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:38,718 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 678 transitions. [2019-11-28 00:28:38,718 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:38,718 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 678 transitions. [2019-11-28 00:28:38,720 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-28 00:28:38,720 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:38,720 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:38,720 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:38,721 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:38,721 INFO L82 PathProgramCache]: Analyzing trace with hash -1623736427, now seen corresponding path program 1 times [2019-11-28 00:28:38,721 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:38,722 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1980639738] [2019-11-28 00:28:38,722 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:38,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:38,771 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:38,771 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1980639738] [2019-11-28 00:28:38,772 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:38,772 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 00:28:38,772 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [333782128] [2019-11-28 00:28:38,773 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:38,773 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:38,773 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:38,773 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:38,774 INFO L87 Difference]: Start difference. First operand 464 states and 678 transitions. Second operand 3 states. [2019-11-28 00:28:38,820 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:38,821 INFO L93 Difference]: Finished difference Result 917 states and 1341 transitions. [2019-11-28 00:28:38,822 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:38,822 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-28 00:28:38,822 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:38,825 INFO L225 Difference]: With dead ends: 917 [2019-11-28 00:28:38,826 INFO L226 Difference]: Without dead ends: 464 [2019-11-28 00:28:38,827 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:38,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-11-28 00:28:38,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-11-28 00:28:38,851 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-11-28 00:28:38,854 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 670 transitions. [2019-11-28 00:28:38,854 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 670 transitions. Word has length 61 [2019-11-28 00:28:38,854 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:38,855 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 670 transitions. [2019-11-28 00:28:38,855 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:38,855 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 670 transitions. [2019-11-28 00:28:38,861 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-28 00:28:38,861 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:38,862 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:38,862 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:38,862 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:38,863 INFO L82 PathProgramCache]: Analyzing trace with hash -175003691, now seen corresponding path program 1 times [2019-11-28 00:28:38,863 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:38,864 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1880058084] [2019-11-28 00:28:38,864 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:38,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:38,935 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:38,936 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1880058084] [2019-11-28 00:28:38,937 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:38,938 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 00:28:38,938 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [676294015] [2019-11-28 00:28:38,938 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:38,939 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:38,939 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:38,940 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:38,940 INFO L87 Difference]: Start difference. First operand 464 states and 670 transitions. Second operand 3 states. [2019-11-28 00:28:39,009 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:39,010 INFO L93 Difference]: Finished difference Result 916 states and 1324 transitions. [2019-11-28 00:28:39,011 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:39,011 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-28 00:28:39,011 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:39,014 INFO L225 Difference]: With dead ends: 916 [2019-11-28 00:28:39,015 INFO L226 Difference]: Without dead ends: 464 [2019-11-28 00:28:39,016 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:39,018 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-11-28 00:28:39,043 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-11-28 00:28:39,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-11-28 00:28:39,045 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 654 transitions. [2019-11-28 00:28:39,046 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 654 transitions. Word has length 61 [2019-11-28 00:28:39,046 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:39,046 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 654 transitions. [2019-11-28 00:28:39,047 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:39,047 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 654 transitions. [2019-11-28 00:28:39,048 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-28 00:28:39,048 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:39,049 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:39,049 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:39,049 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:39,050 INFO L82 PathProgramCache]: Analyzing trace with hash -1945036492, now seen corresponding path program 1 times [2019-11-28 00:28:39,050 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:39,050 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1432588488] [2019-11-28 00:28:39,051 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:39,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:39,116 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:39,118 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1432588488] [2019-11-28 00:28:39,118 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:39,119 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 00:28:39,119 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [871698179] [2019-11-28 00:28:39,120 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:39,120 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:39,127 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:39,128 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:39,129 INFO L87 Difference]: Start difference. First operand 464 states and 654 transitions. Second operand 3 states. [2019-11-28 00:28:39,214 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:39,215 INFO L93 Difference]: Finished difference Result 914 states and 1289 transitions. [2019-11-28 00:28:39,216 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:39,216 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-28 00:28:39,216 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:39,220 INFO L225 Difference]: With dead ends: 914 [2019-11-28 00:28:39,220 INFO L226 Difference]: Without dead ends: 464 [2019-11-28 00:28:39,223 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:39,224 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-11-28 00:28:39,248 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-11-28 00:28:39,249 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-11-28 00:28:39,251 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 638 transitions. [2019-11-28 00:28:39,252 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 638 transitions. Word has length 61 [2019-11-28 00:28:39,252 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:39,252 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 638 transitions. [2019-11-28 00:28:39,253 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:39,253 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 638 transitions. [2019-11-28 00:28:39,254 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-28 00:28:39,254 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:39,255 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:39,255 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:39,255 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:39,255 INFO L82 PathProgramCache]: Analyzing trace with hash -1902661357, now seen corresponding path program 1 times [2019-11-28 00:28:39,256 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:39,257 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1029742450] [2019-11-28 00:28:39,258 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:39,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:39,386 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:39,387 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1029742450] [2019-11-28 00:28:39,388 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:39,388 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 00:28:39,389 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [780750331] [2019-11-28 00:28:39,390 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:39,390 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:39,390 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:39,391 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:39,391 INFO L87 Difference]: Start difference. First operand 464 states and 638 transitions. Second operand 3 states. [2019-11-28 00:28:39,472 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:39,473 INFO L93 Difference]: Finished difference Result 915 states and 1259 transitions. [2019-11-28 00:28:39,473 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:39,474 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-28 00:28:39,475 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:39,479 INFO L225 Difference]: With dead ends: 915 [2019-11-28 00:28:39,479 INFO L226 Difference]: Without dead ends: 464 [2019-11-28 00:28:39,481 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:39,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-11-28 00:28:39,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-11-28 00:28:39,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-11-28 00:28:39,524 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 622 transitions. [2019-11-28 00:28:39,525 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 622 transitions. Word has length 61 [2019-11-28 00:28:39,525 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:39,525 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 622 transitions. [2019-11-28 00:28:39,526 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:39,526 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 622 transitions. [2019-11-28 00:28:39,527 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-28 00:28:39,527 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:39,527 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:39,528 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:39,528 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:39,528 INFO L82 PathProgramCache]: Analyzing trace with hash 398161233, now seen corresponding path program 1 times [2019-11-28 00:28:39,529 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:39,531 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [776206686] [2019-11-28 00:28:39,531 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:39,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:39,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:39,615 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [776206686] [2019-11-28 00:28:39,615 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:39,616 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:39,620 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [517610262] [2019-11-28 00:28:39,621 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:39,621 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:39,622 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:39,623 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:39,623 INFO L87 Difference]: Start difference. First operand 464 states and 622 transitions. Second operand 3 states. [2019-11-28 00:28:39,776 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:39,776 INFO L93 Difference]: Finished difference Result 1299 states and 1732 transitions. [2019-11-28 00:28:39,777 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:39,777 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-28 00:28:39,779 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:39,785 INFO L225 Difference]: With dead ends: 1299 [2019-11-28 00:28:39,785 INFO L226 Difference]: Without dead ends: 884 [2019-11-28 00:28:39,787 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:39,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 884 states. [2019-11-28 00:28:39,842 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 884 to 834. [2019-11-28 00:28:39,843 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 834 states. [2019-11-28 00:28:39,847 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 834 states to 834 states and 1099 transitions. [2019-11-28 00:28:39,847 INFO L78 Accepts]: Start accepts. Automaton has 834 states and 1099 transitions. Word has length 61 [2019-11-28 00:28:39,850 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:39,850 INFO L462 AbstractCegarLoop]: Abstraction has 834 states and 1099 transitions. [2019-11-28 00:28:39,851 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:39,851 INFO L276 IsEmpty]: Start isEmpty. Operand 834 states and 1099 transitions. [2019-11-28 00:28:39,852 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2019-11-28 00:28:39,853 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:39,853 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:39,853 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:39,854 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:39,854 INFO L82 PathProgramCache]: Analyzing trace with hash -276756042, now seen corresponding path program 1 times [2019-11-28 00:28:39,855 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:39,855 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [529797927] [2019-11-28 00:28:39,856 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:39,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:39,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:39,903 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [529797927] [2019-11-28 00:28:39,903 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:39,904 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:39,904 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [416426612] [2019-11-28 00:28:39,904 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:39,904 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:39,905 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:39,906 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:39,906 INFO L87 Difference]: Start difference. First operand 834 states and 1099 transitions. Second operand 3 states. [2019-11-28 00:28:40,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:40,017 INFO L93 Difference]: Finished difference Result 2234 states and 2945 transitions. [2019-11-28 00:28:40,019 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:40,020 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 62 [2019-11-28 00:28:40,020 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:40,027 INFO L225 Difference]: With dead ends: 2234 [2019-11-28 00:28:40,028 INFO L226 Difference]: Without dead ends: 1494 [2019-11-28 00:28:40,030 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:40,032 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1494 states. [2019-11-28 00:28:40,099 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1494 to 1424. [2019-11-28 00:28:40,099 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1424 states. [2019-11-28 00:28:40,104 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1424 states to 1424 states and 1862 transitions. [2019-11-28 00:28:40,104 INFO L78 Accepts]: Start accepts. Automaton has 1424 states and 1862 transitions. Word has length 62 [2019-11-28 00:28:40,105 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:40,107 INFO L462 AbstractCegarLoop]: Abstraction has 1424 states and 1862 transitions. [2019-11-28 00:28:40,108 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:40,108 INFO L276 IsEmpty]: Start isEmpty. Operand 1424 states and 1862 transitions. [2019-11-28 00:28:40,109 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-11-28 00:28:40,109 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:40,109 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:40,110 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:40,110 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:40,110 INFO L82 PathProgramCache]: Analyzing trace with hash -2032591659, now seen corresponding path program 1 times [2019-11-28 00:28:40,110 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:40,111 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1362014445] [2019-11-28 00:28:40,111 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:40,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:40,156 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:40,156 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1362014445] [2019-11-28 00:28:40,156 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:40,157 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:40,158 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [677433909] [2019-11-28 00:28:40,158 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:40,158 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:40,159 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:40,159 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:40,159 INFO L87 Difference]: Start difference. First operand 1424 states and 1862 transitions. Second operand 3 states. [2019-11-28 00:28:40,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:40,321 INFO L93 Difference]: Finished difference Result 3972 states and 5180 transitions. [2019-11-28 00:28:40,321 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:40,321 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 63 [2019-11-28 00:28:40,323 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:40,336 INFO L225 Difference]: With dead ends: 3972 [2019-11-28 00:28:40,337 INFO L226 Difference]: Without dead ends: 2642 [2019-11-28 00:28:40,340 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:40,343 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2642 states. [2019-11-28 00:28:40,461 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2642 to 2560. [2019-11-28 00:28:40,462 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2560 states. [2019-11-28 00:28:40,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2560 states to 2560 states and 3314 transitions. [2019-11-28 00:28:40,471 INFO L78 Accepts]: Start accepts. Automaton has 2560 states and 3314 transitions. Word has length 63 [2019-11-28 00:28:40,472 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:40,473 INFO L462 AbstractCegarLoop]: Abstraction has 2560 states and 3314 transitions. [2019-11-28 00:28:40,473 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:40,473 INFO L276 IsEmpty]: Start isEmpty. Operand 2560 states and 3314 transitions. [2019-11-28 00:28:40,474 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-11-28 00:28:40,475 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:40,475 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:40,475 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:40,475 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:40,476 INFO L82 PathProgramCache]: Analyzing trace with hash -1324102959, now seen corresponding path program 1 times [2019-11-28 00:28:40,476 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:40,477 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [201433835] [2019-11-28 00:28:40,477 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:40,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:40,504 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:40,505 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [201433835] [2019-11-28 00:28:40,505 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:40,505 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:40,505 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [904053084] [2019-11-28 00:28:40,506 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:40,506 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:40,506 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:40,506 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:40,507 INFO L87 Difference]: Start difference. First operand 2560 states and 3314 transitions. Second operand 3 states. [2019-11-28 00:28:40,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:40,631 INFO L93 Difference]: Finished difference Result 4968 states and 6441 transitions. [2019-11-28 00:28:40,632 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:40,632 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 63 [2019-11-28 00:28:40,632 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:40,645 INFO L225 Difference]: With dead ends: 4968 [2019-11-28 00:28:40,645 INFO L226 Difference]: Without dead ends: 2474 [2019-11-28 00:28:40,650 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:40,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2474 states. [2019-11-28 00:28:40,769 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2474 to 2474. [2019-11-28 00:28:40,769 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2474 states. [2019-11-28 00:28:40,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2474 states to 2474 states and 3208 transitions. [2019-11-28 00:28:40,780 INFO L78 Accepts]: Start accepts. Automaton has 2474 states and 3208 transitions. Word has length 63 [2019-11-28 00:28:40,780 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:40,780 INFO L462 AbstractCegarLoop]: Abstraction has 2474 states and 3208 transitions. [2019-11-28 00:28:40,780 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:40,780 INFO L276 IsEmpty]: Start isEmpty. Operand 2474 states and 3208 transitions. [2019-11-28 00:28:40,781 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2019-11-28 00:28:40,782 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:40,782 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:40,782 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:40,782 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:40,782 INFO L82 PathProgramCache]: Analyzing trace with hash -1607983393, now seen corresponding path program 1 times [2019-11-28 00:28:40,783 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:40,783 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1621695752] [2019-11-28 00:28:40,783 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:40,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:40,826 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:40,826 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1621695752] [2019-11-28 00:28:40,827 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:40,827 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 00:28:40,827 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1952699591] [2019-11-28 00:28:40,828 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:40,828 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:40,828 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:40,829 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:40,829 INFO L87 Difference]: Start difference. First operand 2474 states and 3208 transitions. Second operand 3 states. [2019-11-28 00:28:41,100 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:41,100 INFO L93 Difference]: Finished difference Result 7190 states and 9333 transitions. [2019-11-28 00:28:41,101 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:41,101 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 64 [2019-11-28 00:28:41,101 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:41,125 INFO L225 Difference]: With dead ends: 7190 [2019-11-28 00:28:41,126 INFO L226 Difference]: Without dead ends: 4786 [2019-11-28 00:28:41,132 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:41,138 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4786 states. [2019-11-28 00:28:41,388 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4786 to 4754. [2019-11-28 00:28:41,388 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4754 states. [2019-11-28 00:28:41,404 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4754 states to 4754 states and 6114 transitions. [2019-11-28 00:28:41,404 INFO L78 Accepts]: Start accepts. Automaton has 4754 states and 6114 transitions. Word has length 64 [2019-11-28 00:28:41,404 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:41,404 INFO L462 AbstractCegarLoop]: Abstraction has 4754 states and 6114 transitions. [2019-11-28 00:28:41,404 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:41,405 INFO L276 IsEmpty]: Start isEmpty. Operand 4754 states and 6114 transitions. [2019-11-28 00:28:41,407 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2019-11-28 00:28:41,407 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:41,408 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:41,408 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:41,408 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:41,408 INFO L82 PathProgramCache]: Analyzing trace with hash 93244939, now seen corresponding path program 1 times [2019-11-28 00:28:41,409 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:41,409 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [434361787] [2019-11-28 00:28:41,409 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:41,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:41,467 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:41,468 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [434361787] [2019-11-28 00:28:41,468 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:41,469 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:41,469 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1947393772] [2019-11-28 00:28:41,469 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:41,470 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:41,470 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:41,470 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:41,470 INFO L87 Difference]: Start difference. First operand 4754 states and 6114 transitions. Second operand 3 states. [2019-11-28 00:28:41,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:41,832 INFO L93 Difference]: Finished difference Result 14046 states and 18043 transitions. [2019-11-28 00:28:41,833 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:41,833 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 81 [2019-11-28 00:28:41,833 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:41,883 INFO L225 Difference]: With dead ends: 14046 [2019-11-28 00:28:41,883 INFO L226 Difference]: Without dead ends: 9384 [2019-11-28 00:28:41,894 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:41,911 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9384 states. [2019-11-28 00:28:42,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9384 to 9384. [2019-11-28 00:28:42,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9384 states. [2019-11-28 00:28:42,400 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9384 states to 9384 states and 11994 transitions. [2019-11-28 00:28:42,400 INFO L78 Accepts]: Start accepts. Automaton has 9384 states and 11994 transitions. Word has length 81 [2019-11-28 00:28:42,400 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:42,401 INFO L462 AbstractCegarLoop]: Abstraction has 9384 states and 11994 transitions. [2019-11-28 00:28:42,401 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:42,401 INFO L276 IsEmpty]: Start isEmpty. Operand 9384 states and 11994 transitions. [2019-11-28 00:28:42,409 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-11-28 00:28:42,409 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:42,409 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:42,410 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:42,410 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:42,410 INFO L82 PathProgramCache]: Analyzing trace with hash -447123663, now seen corresponding path program 1 times [2019-11-28 00:28:42,410 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:42,411 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [380301363] [2019-11-28 00:28:42,411 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:42,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:42,485 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2019-11-28 00:28:42,486 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [380301363] [2019-11-28 00:28:42,486 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:42,486 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 00:28:42,486 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [547566582] [2019-11-28 00:28:42,487 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:42,487 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:42,487 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:42,488 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:42,488 INFO L87 Difference]: Start difference. First operand 9384 states and 11994 transitions. Second operand 3 states. [2019-11-28 00:28:43,073 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:43,073 INFO L93 Difference]: Finished difference Result 22768 states and 29084 transitions. [2019-11-28 00:28:43,074 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:43,074 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 110 [2019-11-28 00:28:43,074 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:43,140 INFO L225 Difference]: With dead ends: 22768 [2019-11-28 00:28:43,140 INFO L226 Difference]: Without dead ends: 13486 [2019-11-28 00:28:43,161 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:43,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13486 states. [2019-11-28 00:28:43,846 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13486 to 13420. [2019-11-28 00:28:43,847 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13420 states. [2019-11-28 00:28:43,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13420 states to 13420 states and 17034 transitions. [2019-11-28 00:28:43,887 INFO L78 Accepts]: Start accepts. Automaton has 13420 states and 17034 transitions. Word has length 110 [2019-11-28 00:28:43,887 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:43,888 INFO L462 AbstractCegarLoop]: Abstraction has 13420 states and 17034 transitions. [2019-11-28 00:28:43,888 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:43,888 INFO L276 IsEmpty]: Start isEmpty. Operand 13420 states and 17034 transitions. [2019-11-28 00:28:43,899 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-11-28 00:28:43,900 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:43,900 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:43,901 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:43,901 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:43,901 INFO L82 PathProgramCache]: Analyzing trace with hash -2122456675, now seen corresponding path program 1 times [2019-11-28 00:28:43,902 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:43,902 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [611300325] [2019-11-28 00:28:43,902 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:43,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:43,952 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2019-11-28 00:28:43,953 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [611300325] [2019-11-28 00:28:43,953 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:43,953 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 00:28:43,953 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1880371256] [2019-11-28 00:28:43,954 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:43,954 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:43,954 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:43,955 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:43,955 INFO L87 Difference]: Start difference. First operand 13420 states and 17034 transitions. Second operand 3 states. [2019-11-28 00:28:44,661 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:44,662 INFO L93 Difference]: Finished difference Result 32624 states and 41352 transitions. [2019-11-28 00:28:44,662 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:44,662 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 110 [2019-11-28 00:28:44,663 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:44,709 INFO L225 Difference]: With dead ends: 32624 [2019-11-28 00:28:44,710 INFO L226 Difference]: Without dead ends: 19278 [2019-11-28 00:28:44,736 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:44,763 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19278 states. [2019-11-28 00:28:45,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19278 to 19180. [2019-11-28 00:28:45,894 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19180 states. [2019-11-28 00:28:45,948 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19180 states to 19180 states and 24146 transitions. [2019-11-28 00:28:45,948 INFO L78 Accepts]: Start accepts. Automaton has 19180 states and 24146 transitions. Word has length 110 [2019-11-28 00:28:45,949 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:45,949 INFO L462 AbstractCegarLoop]: Abstraction has 19180 states and 24146 transitions. [2019-11-28 00:28:45,949 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:45,950 INFO L276 IsEmpty]: Start isEmpty. Operand 19180 states and 24146 transitions. [2019-11-28 00:28:45,967 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-11-28 00:28:45,968 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:45,969 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:45,969 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:45,969 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:45,970 INFO L82 PathProgramCache]: Analyzing trace with hash -4233773, now seen corresponding path program 1 times [2019-11-28 00:28:45,970 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:45,971 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [77292651] [2019-11-28 00:28:45,971 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:45,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:46,054 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-28 00:28:46,055 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [77292651] [2019-11-28 00:28:46,055 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:46,055 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 00:28:46,056 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [410034248] [2019-11-28 00:28:46,057 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 00:28:46,057 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:46,058 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 00:28:46,058 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 00:28:46,058 INFO L87 Difference]: Start difference. First operand 19180 states and 24146 transitions. Second operand 5 states. [2019-11-28 00:28:48,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:48,155 INFO L93 Difference]: Finished difference Result 47102 states and 59685 transitions. [2019-11-28 00:28:48,156 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 00:28:48,156 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 110 [2019-11-28 00:28:48,156 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:48,214 INFO L225 Difference]: With dead ends: 47102 [2019-11-28 00:28:48,214 INFO L226 Difference]: Without dead ends: 28012 [2019-11-28 00:28:48,246 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-28 00:28:48,277 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28012 states. [2019-11-28 00:28:49,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28012 to 19324. [2019-11-28 00:28:49,106 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19324 states. [2019-11-28 00:28:49,148 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19324 states to 19324 states and 23950 transitions. [2019-11-28 00:28:49,148 INFO L78 Accepts]: Start accepts. Automaton has 19324 states and 23950 transitions. Word has length 110 [2019-11-28 00:28:49,149 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:49,149 INFO L462 AbstractCegarLoop]: Abstraction has 19324 states and 23950 transitions. [2019-11-28 00:28:49,149 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 00:28:49,149 INFO L276 IsEmpty]: Start isEmpty. Operand 19324 states and 23950 transitions. [2019-11-28 00:28:49,165 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-11-28 00:28:49,165 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:49,165 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:49,166 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:49,166 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:49,166 INFO L82 PathProgramCache]: Analyzing trace with hash 2012797655, now seen corresponding path program 1 times [2019-11-28 00:28:49,167 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:49,167 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1032157533] [2019-11-28 00:28:49,167 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:49,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:49,263 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-28 00:28:49,264 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1032157533] [2019-11-28 00:28:49,265 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:49,265 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 00:28:49,265 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1806370283] [2019-11-28 00:28:49,266 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 00:28:49,267 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:49,268 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 00:28:49,269 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 00:28:49,269 INFO L87 Difference]: Start difference. First operand 19324 states and 23950 transitions. Second operand 5 states. [2019-11-28 00:28:51,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:51,066 INFO L93 Difference]: Finished difference Result 45442 states and 56677 transitions. [2019-11-28 00:28:51,067 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 00:28:51,067 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 110 [2019-11-28 00:28:51,067 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:51,140 INFO L225 Difference]: With dead ends: 45442 [2019-11-28 00:28:51,141 INFO L226 Difference]: Without dead ends: 26232 [2019-11-28 00:28:51,183 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-28 00:28:51,220 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26232 states. [2019-11-28 00:28:52,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26232 to 19420. [2019-11-28 00:28:52,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19420 states. [2019-11-28 00:28:52,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19420 states to 19420 states and 23690 transitions. [2019-11-28 00:28:52,035 INFO L78 Accepts]: Start accepts. Automaton has 19420 states and 23690 transitions. Word has length 110 [2019-11-28 00:28:52,036 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:52,036 INFO L462 AbstractCegarLoop]: Abstraction has 19420 states and 23690 transitions. [2019-11-28 00:28:52,036 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 00:28:52,036 INFO L276 IsEmpty]: Start isEmpty. Operand 19420 states and 23690 transitions. [2019-11-28 00:28:52,049 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-11-28 00:28:52,050 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:52,050 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:52,051 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:52,051 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:52,051 INFO L82 PathProgramCache]: Analyzing trace with hash 564093659, now seen corresponding path program 1 times [2019-11-28 00:28:52,051 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:52,052 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2041976397] [2019-11-28 00:28:52,052 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:52,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:52,097 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:52,097 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2041976397] [2019-11-28 00:28:52,097 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:52,098 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:52,098 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1977200691] [2019-11-28 00:28:52,098 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:52,099 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:52,099 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:52,099 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:52,099 INFO L87 Difference]: Start difference. First operand 19420 states and 23690 transitions. Second operand 3 states. [2019-11-28 00:28:53,193 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:53,194 INFO L93 Difference]: Finished difference Result 29198 states and 35739 transitions. [2019-11-28 00:28:53,194 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:53,194 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 110 [2019-11-28 00:28:53,195 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:53,241 INFO L225 Difference]: With dead ends: 29198 [2019-11-28 00:28:53,241 INFO L226 Difference]: Without dead ends: 19420 [2019-11-28 00:28:53,255 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:53,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19420 states. [2019-11-28 00:28:53,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19420 to 19350. [2019-11-28 00:28:53,958 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19350 states. [2019-11-28 00:28:53,980 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19350 states to 19350 states and 23356 transitions. [2019-11-28 00:28:53,980 INFO L78 Accepts]: Start accepts. Automaton has 19350 states and 23356 transitions. Word has length 110 [2019-11-28 00:28:53,980 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:53,980 INFO L462 AbstractCegarLoop]: Abstraction has 19350 states and 23356 transitions. [2019-11-28 00:28:53,980 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:53,981 INFO L276 IsEmpty]: Start isEmpty. Operand 19350 states and 23356 transitions. [2019-11-28 00:28:53,990 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2019-11-28 00:28:53,991 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:53,991 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:53,991 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:53,992 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:53,992 INFO L82 PathProgramCache]: Analyzing trace with hash 770898653, now seen corresponding path program 1 times [2019-11-28 00:28:53,992 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:53,992 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [20187797] [2019-11-28 00:28:53,993 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:54,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:54,045 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-28 00:28:54,045 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [20187797] [2019-11-28 00:28:54,045 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:54,046 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 00:28:54,046 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2105786329] [2019-11-28 00:28:54,046 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 00:28:54,047 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:54,047 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 00:28:54,047 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 00:28:54,047 INFO L87 Difference]: Start difference. First operand 19350 states and 23356 transitions. Second operand 5 states. [2019-11-28 00:28:55,250 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:55,250 INFO L93 Difference]: Finished difference Result 37116 states and 45101 transitions. [2019-11-28 00:28:55,250 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 00:28:55,250 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 111 [2019-11-28 00:28:55,251 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:55,282 INFO L225 Difference]: With dead ends: 37116 [2019-11-28 00:28:55,282 INFO L226 Difference]: Without dead ends: 17840 [2019-11-28 00:28:55,299 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-28 00:28:55,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17840 states. [2019-11-28 00:28:55,900 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17840 to 13178. [2019-11-28 00:28:55,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13178 states. [2019-11-28 00:28:55,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13178 states to 13178 states and 15698 transitions. [2019-11-28 00:28:55,914 INFO L78 Accepts]: Start accepts. Automaton has 13178 states and 15698 transitions. Word has length 111 [2019-11-28 00:28:55,914 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:55,914 INFO L462 AbstractCegarLoop]: Abstraction has 13178 states and 15698 transitions. [2019-11-28 00:28:55,914 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 00:28:55,915 INFO L276 IsEmpty]: Start isEmpty. Operand 13178 states and 15698 transitions. [2019-11-28 00:28:55,921 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2019-11-28 00:28:55,921 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:55,921 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:55,921 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:55,922 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:55,922 INFO L82 PathProgramCache]: Analyzing trace with hash 273196097, now seen corresponding path program 1 times [2019-11-28 00:28:55,922 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:55,922 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1427045428] [2019-11-28 00:28:55,923 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:55,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:55,956 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 18 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:55,957 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1427045428] [2019-11-28 00:28:55,957 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:55,957 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:55,957 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1607156020] [2019-11-28 00:28:55,958 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:55,958 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:55,958 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:55,958 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:55,959 INFO L87 Difference]: Start difference. First operand 13178 states and 15698 transitions. Second operand 3 states. [2019-11-28 00:28:56,339 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:56,340 INFO L93 Difference]: Finished difference Result 21196 states and 25354 transitions. [2019-11-28 00:28:56,341 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:56,341 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 113 [2019-11-28 00:28:56,341 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:56,358 INFO L225 Difference]: With dead ends: 21196 [2019-11-28 00:28:56,358 INFO L226 Difference]: Without dead ends: 11030 [2019-11-28 00:28:56,371 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:56,381 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11030 states. [2019-11-28 00:28:56,790 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11030 to 11026. [2019-11-28 00:28:56,790 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11026 states. [2019-11-28 00:28:56,802 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11026 states to 11026 states and 13114 transitions. [2019-11-28 00:28:56,802 INFO L78 Accepts]: Start accepts. Automaton has 11026 states and 13114 transitions. Word has length 113 [2019-11-28 00:28:56,802 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:56,802 INFO L462 AbstractCegarLoop]: Abstraction has 11026 states and 13114 transitions. [2019-11-28 00:28:56,802 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:56,802 INFO L276 IsEmpty]: Start isEmpty. Operand 11026 states and 13114 transitions. [2019-11-28 00:28:56,999 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 147 [2019-11-28 00:28:57,000 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:57,000 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:57,000 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:57,001 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:57,001 INFO L82 PathProgramCache]: Analyzing trace with hash 1857340375, now seen corresponding path program 1 times [2019-11-28 00:28:57,001 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:57,001 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [599816354] [2019-11-28 00:28:57,001 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:57,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:57,048 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:57,048 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [599816354] [2019-11-28 00:28:57,048 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:57,048 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:57,049 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1211492931] [2019-11-28 00:28:57,049 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:57,049 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:57,049 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:57,050 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:57,050 INFO L87 Difference]: Start difference. First operand 11026 states and 13114 transitions. Second operand 3 states. [2019-11-28 00:28:57,400 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:57,400 INFO L93 Difference]: Finished difference Result 20200 states and 24102 transitions. [2019-11-28 00:28:57,402 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:28:57,402 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 146 [2019-11-28 00:28:57,403 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:57,419 INFO L225 Difference]: With dead ends: 20200 [2019-11-28 00:28:57,419 INFO L226 Difference]: Without dead ends: 11030 [2019-11-28 00:28:57,430 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:57,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11030 states. [2019-11-28 00:28:57,810 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11030 to 11026. [2019-11-28 00:28:57,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11026 states. [2019-11-28 00:28:57,821 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11026 states to 11026 states and 13034 transitions. [2019-11-28 00:28:57,822 INFO L78 Accepts]: Start accepts. Automaton has 11026 states and 13034 transitions. Word has length 146 [2019-11-28 00:28:57,822 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:57,822 INFO L462 AbstractCegarLoop]: Abstraction has 11026 states and 13034 transitions. [2019-11-28 00:28:57,822 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:28:57,822 INFO L276 IsEmpty]: Start isEmpty. Operand 11026 states and 13034 transitions. [2019-11-28 00:28:57,831 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2019-11-28 00:28:57,831 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:57,832 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:57,832 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:57,832 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:57,832 INFO L82 PathProgramCache]: Analyzing trace with hash 1216535548, now seen corresponding path program 1 times [2019-11-28 00:28:57,833 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:57,833 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1928935247] [2019-11-28 00:28:57,833 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:57,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:57,894 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-28 00:28:57,895 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1928935247] [2019-11-28 00:28:57,895 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:57,895 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 00:28:57,895 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [503246787] [2019-11-28 00:28:57,896 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 00:28:57,898 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:57,898 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 00:28:57,899 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 00:28:57,899 INFO L87 Difference]: Start difference. First operand 11026 states and 13034 transitions. Second operand 5 states. [2019-11-28 00:28:58,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:28:58,816 INFO L93 Difference]: Finished difference Result 35306 states and 41589 transitions. [2019-11-28 00:28:58,817 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 00:28:58,817 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 176 [2019-11-28 00:28:58,817 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:28:58,842 INFO L225 Difference]: With dead ends: 35306 [2019-11-28 00:28:58,842 INFO L226 Difference]: Without dead ends: 24343 [2019-11-28 00:28:58,855 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-28 00:28:58,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24343 states. [2019-11-28 00:28:59,484 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24343 to 11410. [2019-11-28 00:28:59,485 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11410 states. [2019-11-28 00:28:59,499 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11410 states to 11410 states and 13328 transitions. [2019-11-28 00:28:59,500 INFO L78 Accepts]: Start accepts. Automaton has 11410 states and 13328 transitions. Word has length 176 [2019-11-28 00:28:59,500 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:28:59,500 INFO L462 AbstractCegarLoop]: Abstraction has 11410 states and 13328 transitions. [2019-11-28 00:28:59,500 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 00:28:59,500 INFO L276 IsEmpty]: Start isEmpty. Operand 11410 states and 13328 transitions. [2019-11-28 00:28:59,508 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2019-11-28 00:28:59,508 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:28:59,508 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:28:59,508 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:28:59,509 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:28:59,509 INFO L82 PathProgramCache]: Analyzing trace with hash 2104709508, now seen corresponding path program 1 times [2019-11-28 00:28:59,509 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:28:59,509 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2016397667] [2019-11-28 00:28:59,510 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:28:59,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:28:59,587 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:28:59,587 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2016397667] [2019-11-28 00:28:59,587 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:28:59,587 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:28:59,588 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [613394530] [2019-11-28 00:28:59,588 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:28:59,588 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:28:59,589 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:28:59,589 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:28:59,589 INFO L87 Difference]: Start difference. First operand 11410 states and 13328 transitions. Second operand 3 states. [2019-11-28 00:29:00,564 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:29:00,564 INFO L93 Difference]: Finished difference Result 19722 states and 23103 transitions. [2019-11-28 00:29:00,565 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:29:00,565 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 176 [2019-11-28 00:29:00,565 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:29:00,582 INFO L225 Difference]: With dead ends: 19722 [2019-11-28 00:29:00,582 INFO L226 Difference]: Without dead ends: 11442 [2019-11-28 00:29:00,594 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:29:00,606 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11442 states. [2019-11-28 00:29:01,129 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11442 to 11410. [2019-11-28 00:29:01,129 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11410 states. [2019-11-28 00:29:01,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11410 states to 11410 states and 13120 transitions. [2019-11-28 00:29:01,142 INFO L78 Accepts]: Start accepts. Automaton has 11410 states and 13120 transitions. Word has length 176 [2019-11-28 00:29:01,142 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:29:01,142 INFO L462 AbstractCegarLoop]: Abstraction has 11410 states and 13120 transitions. [2019-11-28 00:29:01,142 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:29:01,142 INFO L276 IsEmpty]: Start isEmpty. Operand 11410 states and 13120 transitions. [2019-11-28 00:29:01,148 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-28 00:29:01,148 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:29:01,148 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:29:01,149 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:29:01,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:29:01,149 INFO L82 PathProgramCache]: Analyzing trace with hash 251088387, now seen corresponding path program 1 times [2019-11-28 00:29:01,149 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:29:01,149 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [244258006] [2019-11-28 00:29:01,149 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:29:01,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:29:01,192 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-28 00:29:01,192 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [244258006] [2019-11-28 00:29:01,192 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:29:01,192 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:29:01,193 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1774419054] [2019-11-28 00:29:01,193 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:29:01,193 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:29:01,193 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:29:01,194 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:29:01,194 INFO L87 Difference]: Start difference. First operand 11410 states and 13120 transitions. Second operand 3 states. [2019-11-28 00:29:01,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:29:01,989 INFO L93 Difference]: Finished difference Result 22664 states and 25875 transitions. [2019-11-28 00:29:01,989 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:29:01,989 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-28 00:29:01,990 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:29:02,000 INFO L225 Difference]: With dead ends: 22664 [2019-11-28 00:29:02,000 INFO L226 Difference]: Without dead ends: 6788 [2019-11-28 00:29:02,011 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:29:02,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6788 states. [2019-11-28 00:29:02,258 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6788 to 6580. [2019-11-28 00:29:02,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6580 states. [2019-11-28 00:29:02,266 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6580 states to 6580 states and 7290 transitions. [2019-11-28 00:29:02,266 INFO L78 Accepts]: Start accepts. Automaton has 6580 states and 7290 transitions. Word has length 178 [2019-11-28 00:29:02,266 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:29:02,266 INFO L462 AbstractCegarLoop]: Abstraction has 6580 states and 7290 transitions. [2019-11-28 00:29:02,266 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:29:02,267 INFO L276 IsEmpty]: Start isEmpty. Operand 6580 states and 7290 transitions. [2019-11-28 00:29:02,272 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 181 [2019-11-28 00:29:02,272 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:29:02,272 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:29:02,273 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:29:02,273 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:29:02,273 INFO L82 PathProgramCache]: Analyzing trace with hash -32931800, now seen corresponding path program 1 times [2019-11-28 00:29:02,273 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:29:02,273 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [63218617] [2019-11-28 00:29:02,273 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:29:02,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 00:29:02,328 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 00:29:02,328 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [63218617] [2019-11-28 00:29:02,329 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 00:29:02,329 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 00:29:02,329 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [226625671] [2019-11-28 00:29:02,330 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 00:29:02,330 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 00:29:02,330 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 00:29:02,330 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:29:02,330 INFO L87 Difference]: Start difference. First operand 6580 states and 7290 transitions. Second operand 3 states. [2019-11-28 00:29:02,772 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 00:29:02,772 INFO L93 Difference]: Finished difference Result 11554 states and 12829 transitions. [2019-11-28 00:29:02,773 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 00:29:02,773 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 180 [2019-11-28 00:29:02,773 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 00:29:02,783 INFO L225 Difference]: With dead ends: 11554 [2019-11-28 00:29:02,783 INFO L226 Difference]: Without dead ends: 6580 [2019-11-28 00:29:02,789 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 00:29:02,795 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6580 states. [2019-11-28 00:29:03,150 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6580 to 6580. [2019-11-28 00:29:03,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6580 states. [2019-11-28 00:29:03,156 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6580 states to 6580 states and 7212 transitions. [2019-11-28 00:29:03,156 INFO L78 Accepts]: Start accepts. Automaton has 6580 states and 7212 transitions. Word has length 180 [2019-11-28 00:29:03,157 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 00:29:03,157 INFO L462 AbstractCegarLoop]: Abstraction has 6580 states and 7212 transitions. [2019-11-28 00:29:03,157 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 00:29:03,157 INFO L276 IsEmpty]: Start isEmpty. Operand 6580 states and 7212 transitions. [2019-11-28 00:29:03,162 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 183 [2019-11-28 00:29:03,162 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 00:29:03,163 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 00:29:03,163 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 00:29:03,163 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 00:29:03,164 INFO L82 PathProgramCache]: Analyzing trace with hash 1382104249, now seen corresponding path program 1 times [2019-11-28 00:29:03,164 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 00:29:03,164 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2013865343] [2019-11-28 00:29:03,164 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 00:29:03,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 00:29:03,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 00:29:03,291 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-28 00:29:03,292 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-28 00:29:03,470 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 12:29:03 BoogieIcfgContainer [2019-11-28 00:29:03,470 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-28 00:29:03,471 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-28 00:29:03,471 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-28 00:29:03,471 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-28 00:29:03,472 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 12:28:37" (3/4) ... [2019-11-28 00:29:03,474 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-28 00:29:03,660 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2019-11-28 00:29:03,660 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-28 00:29:03,663 INFO L168 Benchmark]: Toolchain (without parser) took 27948.50 ms. Allocated memory was 1.0 GB in the beginning and 3.9 GB in the end (delta: 2.9 GB). Free memory was 960.4 MB in the beginning and 3.4 GB in the end (delta: -2.5 GB). Peak memory consumption was 404.0 MB. Max. memory is 11.5 GB. [2019-11-28 00:29:03,663 INFO L168 Benchmark]: CDTParser took 0.27 ms. Allocated memory is still 1.0 GB. Free memory is still 987.2 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 00:29:03,664 INFO L168 Benchmark]: CACSL2BoogieTranslator took 499.86 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 90.2 MB). Free memory was 960.4 MB in the beginning and 1.1 GB in the end (delta: -118.9 MB). Peak memory consumption was 25.8 MB. Max. memory is 11.5 GB. [2019-11-28 00:29:03,664 INFO L168 Benchmark]: Boogie Procedure Inliner took 82.02 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.9 MB). Peak memory consumption was 6.9 MB. Max. memory is 11.5 GB. [2019-11-28 00:29:03,665 INFO L168 Benchmark]: Boogie Preprocessor took 78.04 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.9 MB). Peak memory consumption was 6.9 MB. Max. memory is 11.5 GB. [2019-11-28 00:29:03,665 INFO L168 Benchmark]: RCFGBuilder took 1166.54 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 998.0 MB in the end (delta: 67.5 MB). Peak memory consumption was 67.5 MB. Max. memory is 11.5 GB. [2019-11-28 00:29:03,665 INFO L168 Benchmark]: TraceAbstraction took 25926.61 ms. Allocated memory was 1.1 GB in the beginning and 3.9 GB in the end (delta: 2.8 GB). Free memory was 998.0 MB in the beginning and 3.4 GB in the end (delta: -2.4 GB). Peak memory consumption was 351.4 MB. Max. memory is 11.5 GB. [2019-11-28 00:29:03,666 INFO L168 Benchmark]: Witness Printer took 189.76 ms. Allocated memory is still 3.9 GB. Free memory was 3.4 GB in the beginning and 3.4 GB in the end (delta: 24 B). Peak memory consumption was 24 B. Max. memory is 11.5 GB. [2019-11-28 00:29:03,668 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.27 ms. Allocated memory is still 1.0 GB. Free memory is still 987.2 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 499.86 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 90.2 MB). Free memory was 960.4 MB in the beginning and 1.1 GB in the end (delta: -118.9 MB). Peak memory consumption was 25.8 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 82.02 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.9 MB). Peak memory consumption was 6.9 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 78.04 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.9 MB). Peak memory consumption was 6.9 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1166.54 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 998.0 MB in the end (delta: 67.5 MB). Peak memory consumption was 67.5 MB. Max. memory is 11.5 GB. * TraceAbstraction took 25926.61 ms. Allocated memory was 1.1 GB in the beginning and 3.9 GB in the end (delta: 2.8 GB). Free memory was 998.0 MB in the beginning and 3.4 GB in the end (delta: -2.4 GB). Peak memory consumption was 351.4 MB. Max. memory is 11.5 GB. * Witness Printer took 189.76 ms. Allocated memory is still 3.9 GB. Free memory was 3.4 GB in the beginning and 3.4 GB in the end (delta: 24 B). Peak memory consumption was 24 B. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int m_st ; [L20] int t1_st ; [L21] int t2_st ; [L22] int t3_st ; [L23] int m_i ; [L24] int t1_i ; [L25] int t2_i ; [L26] int t3_i ; [L27] int M_E = 2; [L28] int T1_E = 2; [L29] int T2_E = 2; [L30] int T3_E = 2; [L31] int E_1 = 2; [L32] int E_2 = 2; [L33] int E_3 = 2; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0] [L687] int __retres1 ; [L600] m_i = 1 [L601] t1_i = 1 [L602] t2_i = 1 [L603] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L628] int kernel_st ; [L629] int tmp ; [L630] int tmp___0 ; [L634] kernel_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L271] COND TRUE m_i == 1 [L272] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L276] COND TRUE t1_i == 1 [L277] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L281] COND TRUE t2_i == 1 [L282] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L286] COND TRUE t3_i == 1 [L287] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L408] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L413] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L418] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L423] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L428] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L433] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L438] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; [L184] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L187] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L197] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L199] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L203] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L206] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L216] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L218] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L506] tmp___0 = is_transmit1_triggered() [L508] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L222] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L225] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L235] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L237] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L514] tmp___1 = is_transmit2_triggered() [L516] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L241] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L244] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L254] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L256] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L522] tmp___2 = is_transmit3_triggered() [L524] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L451] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L456] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L461] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L466] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L471] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L476] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L481] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L642] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L645] kernel_st = 1 [L327] int tmp ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L331] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L296] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L299] COND TRUE m_st == 0 [L300] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L322] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L334] tmp = exists_runnable_thread() [L336] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L341] COND TRUE m_st == 0 [L342] int tmp_ndt_1; [L343] tmp_ndt_1 = __VERIFIER_nondet_int() [L344] COND FALSE !(\read(tmp_ndt_1)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L355] COND TRUE t1_st == 0 [L356] int tmp_ndt_2; [L357] tmp_ndt_2 = __VERIFIER_nondet_int() [L358] COND TRUE \read(tmp_ndt_2) [L360] t1_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L84] COND TRUE t1_pc == 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L95] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L97] t1_pc = 1 [L98] t1_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L369] COND TRUE t2_st == 0 [L370] int tmp_ndt_3; [L371] tmp_ndt_3 = __VERIFIER_nondet_int() [L372] COND TRUE \read(tmp_ndt_3) [L374] t2_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L119] COND TRUE t2_pc == 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L130] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L132] t2_pc = 1 [L133] t2_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L383] COND TRUE t3_st == 0 [L384] int tmp_ndt_4; [L385] tmp_ndt_4 = __VERIFIER_nondet_int() [L386] COND TRUE \read(tmp_ndt_4) [L388] t3_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1] [L154] COND TRUE t3_pc == 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1] [L165] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1] [L167] t3_pc = 1 [L168] t3_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L331] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L296] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L299] COND TRUE m_st == 0 [L300] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L322] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L334] tmp = exists_runnable_thread() [L336] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L341] COND TRUE m_st == 0 [L342] int tmp_ndt_1; [L343] tmp_ndt_1 = __VERIFIER_nondet_int() [L344] COND TRUE \read(tmp_ndt_1) [L346] m_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L43] COND TRUE m_pc == 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L54] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L57] E_1 = 1 [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; [L184] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L187] COND FALSE !(m_pc == 1) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L197] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L199] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L203] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L206] COND TRUE t1_pc == 1 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L207] COND TRUE E_1 == 1 [L208] __retres1 = 1 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L218] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L506] tmp___0 = is_transmit1_triggered() [L508] COND TRUE \read(tmp___0) [L509] t1_st = 0 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L222] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L225] COND TRUE t2_pc == 1 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L226] COND FALSE !(E_2 == 1) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L235] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L237] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L514] tmp___1 = is_transmit2_triggered() [L516] COND FALSE !(\read(tmp___1)) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L241] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L244] COND TRUE t3_pc == 1 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L245] COND FALSE !(E_3 == 1) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L254] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L256] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L522] tmp___2 = is_transmit3_triggered() [L524] COND FALSE !(\read(tmp___2)) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L59] E_1 = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L62] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L64] m_pc = 1 [L65] m_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L355] COND TRUE t1_st == 0 [L356] int tmp_ndt_2; [L357] tmp_ndt_2 = __VERIFIER_nondet_int() [L358] COND TRUE \read(tmp_ndt_2) [L360] t1_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L84] COND FALSE !(t1_pc == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L87] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L103] E_2 = 1 [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; [L184] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L187] COND TRUE m_pc == 1 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L188] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L197] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L199] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L203] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L206] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L207] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L216] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L218] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L506] tmp___0 = is_transmit1_triggered() [L508] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L222] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L225] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L226] COND TRUE E_2 == 1 [L227] __retres1 = 1 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L237] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L514] tmp___1 = is_transmit2_triggered() [L516] COND TRUE \read(tmp___1) [L517] t2_st = 0 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L241] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L244] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L245] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L254] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L256] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L522] tmp___2 = is_transmit3_triggered() [L524] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L105] E_2 = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L95] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L97] t1_pc = 1 [L98] t1_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L369] COND TRUE t2_st == 0 [L370] int tmp_ndt_3; [L371] tmp_ndt_3 = __VERIFIER_nondet_int() [L372] COND TRUE \read(tmp_ndt_3) [L374] t2_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L119] COND FALSE !(t2_pc == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L122] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L138] E_3 = 1 [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; [L184] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L187] COND TRUE m_pc == 1 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L188] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L197] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L199] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L203] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L206] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L207] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L216] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L218] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L506] tmp___0 = is_transmit1_triggered() [L508] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L222] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L225] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L226] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L235] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L237] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L514] tmp___1 = is_transmit2_triggered() [L516] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L241] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L244] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L245] COND TRUE E_3 == 1 [L246] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L256] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L522] tmp___2 = is_transmit3_triggered() [L524] COND TRUE \read(tmp___2) [L525] t3_st = 0 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L140] E_3 = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L130] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L132] t2_pc = 1 [L133] t2_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L383] COND TRUE t3_st == 0 [L384] int tmp_ndt_4; [L385] tmp_ndt_4 = __VERIFIER_nondet_int() [L386] COND TRUE \read(tmp_ndt_4) [L388] t3_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] [L154] COND FALSE !(t3_pc == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] [L157] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] [L11] __VERIFIER_error() VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 276 locations, 1 error locations. Result: UNSAFE, OverallTime: 25.6s, OverallIterations: 27, TraceHistogramMax: 2, AutomataDifference: 14.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 10884 SDtfs, 10117 SDslu, 7643 SDs, 0 SdLazy, 500 SolverSat, 248 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.7s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 92 GetRequests, 50 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=19420occurred in iteration=18, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 9.1s AutomataMinimizationTime, 26 MinimizatonAttempts, 33813 StatesRemovedByMinimization, 16 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 0.9s InterpolantComputationTime, 2694 NumberOfCodeBlocks, 2694 NumberOfCodeBlocksAsserted, 27 NumberOfCheckSat, 2486 ConstructedInterpolants, 0 QuantifiedInterpolants, 403400 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 26 InterpolantComputations, 26 PerfectInterpolantSequences, 228/228 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...