./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/systemc/kundu1.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx12G -Xms1G -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/systemc/kundu1.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 532163d21d7e473fbfa4a073427e9fd2a45c7337 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-11-28 17:30:44,617 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-28 17:30:44,619 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-28 17:30:44,631 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-28 17:30:44,631 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-28 17:30:44,632 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-28 17:30:44,634 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-28 17:30:44,636 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-28 17:30:44,637 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-28 17:30:44,638 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-28 17:30:44,639 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-28 17:30:44,641 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-28 17:30:44,641 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-28 17:30:44,642 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-28 17:30:44,643 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-28 17:30:44,644 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-28 17:30:44,649 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-28 17:30:44,650 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-28 17:30:44,655 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-28 17:30:44,657 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-28 17:30:44,663 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-28 17:30:44,664 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-28 17:30:44,666 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-28 17:30:44,667 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-28 17:30:44,670 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-28 17:30:44,670 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-28 17:30:44,670 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-28 17:30:44,672 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-28 17:30:44,673 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-28 17:30:44,674 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-28 17:30:44,676 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-28 17:30:44,676 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-28 17:30:44,678 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-28 17:30:44,679 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-28 17:30:44,681 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-28 17:30:44,684 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-28 17:30:44,685 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-28 17:30:44,685 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-28 17:30:44,685 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-28 17:30:44,686 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-28 17:30:44,687 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-28 17:30:44,688 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-28 17:30:44,702 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-28 17:30:44,702 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-28 17:30:44,703 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-28 17:30:44,704 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-28 17:30:44,704 INFO L138 SettingsManager]: * Use SBE=true [2019-11-28 17:30:44,704 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-28 17:30:44,705 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-28 17:30:44,705 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-28 17:30:44,705 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-28 17:30:44,705 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-28 17:30:44,706 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-28 17:30:44,706 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-28 17:30:44,706 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-28 17:30:44,707 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-28 17:30:44,707 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-28 17:30:44,707 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-28 17:30:44,707 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-28 17:30:44,708 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-28 17:30:44,708 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-28 17:30:44,708 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-28 17:30:44,709 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-28 17:30:44,709 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 17:30:44,709 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-28 17:30:44,709 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-28 17:30:44,710 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-28 17:30:44,710 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-28 17:30:44,710 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-28 17:30:44,711 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-28 17:30:44,711 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-11-28 17:30:44,711 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 532163d21d7e473fbfa4a073427e9fd2a45c7337 [2019-11-28 17:30:44,989 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-28 17:30:45,006 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-28 17:30:45,010 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-28 17:30:45,013 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-28 17:30:45,014 INFO L275 PluginConnector]: CDTParser initialized [2019-11-28 17:30:45,015 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/kundu1.cil.c [2019-11-28 17:30:45,083 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ae04f14ac/655de963b1cc4aef94b2bbb75f59ffcc/FLAGd53656b2c [2019-11-28 17:30:45,557 INFO L306 CDTParser]: Found 1 translation units. [2019-11-28 17:30:45,558 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/kundu1.cil.c [2019-11-28 17:30:45,566 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ae04f14ac/655de963b1cc4aef94b2bbb75f59ffcc/FLAGd53656b2c [2019-11-28 17:30:45,962 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ae04f14ac/655de963b1cc4aef94b2bbb75f59ffcc [2019-11-28 17:30:45,965 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-28 17:30:45,966 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-28 17:30:45,967 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-28 17:30:45,967 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-28 17:30:45,971 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-28 17:30:45,972 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 05:30:45" (1/1) ... [2019-11-28 17:30:45,974 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@388be10d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:30:45, skipping insertion in model container [2019-11-28 17:30:45,974 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 05:30:45" (1/1) ... [2019-11-28 17:30:45,983 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-11-28 17:30:46,033 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-11-28 17:30:46,259 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 17:30:46,264 INFO L203 MainTranslator]: Completed pre-run [2019-11-28 17:30:46,300 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 17:30:46,380 INFO L208 MainTranslator]: Completed translation [2019-11-28 17:30:46,381 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:30:46 WrapperNode [2019-11-28 17:30:46,381 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-28 17:30:46,382 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-28 17:30:46,382 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-28 17:30:46,382 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-28 17:30:46,388 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:30:46" (1/1) ... [2019-11-28 17:30:46,395 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:30:46" (1/1) ... [2019-11-28 17:30:46,431 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-28 17:30:46,432 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-28 17:30:46,432 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-28 17:30:46,432 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-28 17:30:46,442 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:30:46" (1/1) ... [2019-11-28 17:30:46,442 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:30:46" (1/1) ... [2019-11-28 17:30:46,444 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:30:46" (1/1) ... [2019-11-28 17:30:46,444 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:30:46" (1/1) ... [2019-11-28 17:30:46,451 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:30:46" (1/1) ... [2019-11-28 17:30:46,459 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:30:46" (1/1) ... [2019-11-28 17:30:46,461 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:30:46" (1/1) ... [2019-11-28 17:30:46,465 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-28 17:30:46,466 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-28 17:30:46,466 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-28 17:30:46,466 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-28 17:30:46,467 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:30:46" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 17:30:46,519 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-28 17:30:46,519 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-28 17:30:47,041 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-28 17:30:47,041 INFO L287 CfgBuilder]: Removed 72 assume(true) statements. [2019-11-28 17:30:47,043 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 05:30:47 BoogieIcfgContainer [2019-11-28 17:30:47,043 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-28 17:30:47,045 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-28 17:30:47,046 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-28 17:30:47,049 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-28 17:30:47,050 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 05:30:45" (1/3) ... [2019-11-28 17:30:47,051 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@653e8676 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 05:30:47, skipping insertion in model container [2019-11-28 17:30:47,051 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:30:46" (2/3) ... [2019-11-28 17:30:47,052 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@653e8676 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 05:30:47, skipping insertion in model container [2019-11-28 17:30:47,052 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 05:30:47" (3/3) ... [2019-11-28 17:30:47,054 INFO L109 eAbstractionObserver]: Analyzing ICFG kundu1.cil.c [2019-11-28 17:30:47,064 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-28 17:30:47,072 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 3 error locations. [2019-11-28 17:30:47,084 INFO L249 AbstractCegarLoop]: Starting to check reachability of 3 error locations. [2019-11-28 17:30:47,127 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-28 17:30:47,127 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-28 17:30:47,128 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-28 17:30:47,128 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-28 17:30:47,128 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-28 17:30:47,129 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-28 17:30:47,129 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-28 17:30:47,130 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-28 17:30:47,156 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states. [2019-11-28 17:30:47,165 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-11-28 17:30:47,166 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:30:47,167 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:30:47,167 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:30:47,175 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:30:47,175 INFO L82 PathProgramCache]: Analyzing trace with hash 1913091172, now seen corresponding path program 1 times [2019-11-28 17:30:47,184 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:30:47,185 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [827556001] [2019-11-28 17:30:47,185 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:30:47,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:30:47,323 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:30:47,324 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [827556001] [2019-11-28 17:30:47,324 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:30:47,325 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:30:47,326 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1291170059] [2019-11-28 17:30:47,331 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:30:47,332 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:30:47,342 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:30:47,342 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:30:47,344 INFO L87 Difference]: Start difference. First operand 117 states. Second operand 3 states. [2019-11-28 17:30:47,396 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:30:47,396 INFO L93 Difference]: Finished difference Result 228 states and 346 transitions. [2019-11-28 17:30:47,397 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:30:47,399 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 33 [2019-11-28 17:30:47,399 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:30:47,410 INFO L225 Difference]: With dead ends: 228 [2019-11-28 17:30:47,411 INFO L226 Difference]: Without dead ends: 112 [2019-11-28 17:30:47,414 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:30:47,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2019-11-28 17:30:47,459 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 112. [2019-11-28 17:30:47,460 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112 states. [2019-11-28 17:30:47,463 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 162 transitions. [2019-11-28 17:30:47,464 INFO L78 Accepts]: Start accepts. Automaton has 112 states and 162 transitions. Word has length 33 [2019-11-28 17:30:47,464 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:30:47,465 INFO L462 AbstractCegarLoop]: Abstraction has 112 states and 162 transitions. [2019-11-28 17:30:47,465 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:30:47,465 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 162 transitions. [2019-11-28 17:30:47,466 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-11-28 17:30:47,467 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:30:47,467 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:30:47,467 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:30:47,468 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:30:47,468 INFO L82 PathProgramCache]: Analyzing trace with hash 526887778, now seen corresponding path program 1 times [2019-11-28 17:30:47,468 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:30:47,468 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1510176950] [2019-11-28 17:30:47,469 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:30:47,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:30:47,519 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:30:47,520 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1510176950] [2019-11-28 17:30:47,520 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:30:47,520 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:30:47,520 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [362764227] [2019-11-28 17:30:47,522 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:30:47,522 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:30:47,522 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:30:47,523 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:30:47,523 INFO L87 Difference]: Start difference. First operand 112 states and 162 transitions. Second operand 3 states. [2019-11-28 17:30:47,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:30:47,628 INFO L93 Difference]: Finished difference Result 305 states and 441 transitions. [2019-11-28 17:30:47,628 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:30:47,628 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 33 [2019-11-28 17:30:47,628 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:30:47,633 INFO L225 Difference]: With dead ends: 305 [2019-11-28 17:30:47,636 INFO L226 Difference]: Without dead ends: 200 [2019-11-28 17:30:47,638 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:30:47,639 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 200 states. [2019-11-28 17:30:47,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 200 to 190. [2019-11-28 17:30:47,672 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 190 states. [2019-11-28 17:30:47,675 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190 states to 190 states and 275 transitions. [2019-11-28 17:30:47,675 INFO L78 Accepts]: Start accepts. Automaton has 190 states and 275 transitions. Word has length 33 [2019-11-28 17:30:47,675 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:30:47,675 INFO L462 AbstractCegarLoop]: Abstraction has 190 states and 275 transitions. [2019-11-28 17:30:47,676 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:30:47,676 INFO L276 IsEmpty]: Start isEmpty. Operand 190 states and 275 transitions. [2019-11-28 17:30:47,677 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-11-28 17:30:47,677 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:30:47,677 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:30:47,677 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:30:47,678 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:30:47,678 INFO L82 PathProgramCache]: Analyzing trace with hash -1145629853, now seen corresponding path program 1 times [2019-11-28 17:30:47,678 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:30:47,678 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1533271664] [2019-11-28 17:30:47,679 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:30:47,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:30:47,722 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:30:47,722 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1533271664] [2019-11-28 17:30:47,723 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:30:47,723 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:30:47,723 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1397813241] [2019-11-28 17:30:47,724 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:30:47,724 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:30:47,724 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:30:47,725 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:30:47,725 INFO L87 Difference]: Start difference. First operand 190 states and 275 transitions. Second operand 3 states. [2019-11-28 17:30:47,813 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:30:47,814 INFO L93 Difference]: Finished difference Result 527 states and 762 transitions. [2019-11-28 17:30:47,817 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:30:47,818 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 33 [2019-11-28 17:30:47,818 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:30:47,822 INFO L225 Difference]: With dead ends: 527 [2019-11-28 17:30:47,822 INFO L226 Difference]: Without dead ends: 350 [2019-11-28 17:30:47,826 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:30:47,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 350 states. [2019-11-28 17:30:47,874 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 350 to 328. [2019-11-28 17:30:47,874 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 328 states. [2019-11-28 17:30:47,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 328 states to 328 states and 462 transitions. [2019-11-28 17:30:47,882 INFO L78 Accepts]: Start accepts. Automaton has 328 states and 462 transitions. Word has length 33 [2019-11-28 17:30:47,882 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:30:47,882 INFO L462 AbstractCegarLoop]: Abstraction has 328 states and 462 transitions. [2019-11-28 17:30:47,882 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:30:47,884 INFO L276 IsEmpty]: Start isEmpty. Operand 328 states and 462 transitions. [2019-11-28 17:30:47,885 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-11-28 17:30:47,887 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:30:47,887 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:30:47,887 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:30:47,888 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:30:47,888 INFO L82 PathProgramCache]: Analyzing trace with hash -1045714737, now seen corresponding path program 1 times [2019-11-28 17:30:47,888 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:30:47,889 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1567532844] [2019-11-28 17:30:47,889 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:30:47,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:30:47,984 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:30:47,985 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1567532844] [2019-11-28 17:30:47,985 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:30:47,985 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 17:30:47,985 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [318975135] [2019-11-28 17:30:47,986 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 17:30:47,987 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:30:47,987 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 17:30:47,987 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:30:47,988 INFO L87 Difference]: Start difference. First operand 328 states and 462 transitions. Second operand 5 states. [2019-11-28 17:30:48,128 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:30:48,128 INFO L93 Difference]: Finished difference Result 1045 states and 1489 transitions. [2019-11-28 17:30:48,129 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 17:30:48,129 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 34 [2019-11-28 17:30:48,130 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:30:48,134 INFO L225 Difference]: With dead ends: 1045 [2019-11-28 17:30:48,134 INFO L226 Difference]: Without dead ends: 728 [2019-11-28 17:30:48,135 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-28 17:30:48,137 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 728 states. [2019-11-28 17:30:48,168 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 728 to 340. [2019-11-28 17:30:48,169 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 340 states. [2019-11-28 17:30:48,170 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 340 states to 340 states and 469 transitions. [2019-11-28 17:30:48,171 INFO L78 Accepts]: Start accepts. Automaton has 340 states and 469 transitions. Word has length 34 [2019-11-28 17:30:48,171 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:30:48,171 INFO L462 AbstractCegarLoop]: Abstraction has 340 states and 469 transitions. [2019-11-28 17:30:48,172 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 17:30:48,172 INFO L276 IsEmpty]: Start isEmpty. Operand 340 states and 469 transitions. [2019-11-28 17:30:48,173 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-11-28 17:30:48,173 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:30:48,173 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:30:48,174 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:30:48,174 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:30:48,175 INFO L82 PathProgramCache]: Analyzing trace with hash -1179728243, now seen corresponding path program 1 times [2019-11-28 17:30:48,175 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:30:48,175 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1694373092] [2019-11-28 17:30:48,176 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:30:48,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:30:48,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:30:48,269 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1694373092] [2019-11-28 17:30:48,269 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:30:48,269 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 17:30:48,270 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1735921823] [2019-11-28 17:30:48,270 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 17:30:48,270 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:30:48,271 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 17:30:48,271 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:30:48,272 INFO L87 Difference]: Start difference. First operand 340 states and 469 transitions. Second operand 5 states. [2019-11-28 17:30:48,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:30:48,426 INFO L93 Difference]: Finished difference Result 1046 states and 1465 transitions. [2019-11-28 17:30:48,427 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 17:30:48,427 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 34 [2019-11-28 17:30:48,428 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:30:48,432 INFO L225 Difference]: With dead ends: 1046 [2019-11-28 17:30:48,432 INFO L226 Difference]: Without dead ends: 724 [2019-11-28 17:30:48,433 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-28 17:30:48,435 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 724 states. [2019-11-28 17:30:48,476 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 724 to 352. [2019-11-28 17:30:48,477 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 352 states. [2019-11-28 17:30:48,479 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 352 states to 352 states and 476 transitions. [2019-11-28 17:30:48,479 INFO L78 Accepts]: Start accepts. Automaton has 352 states and 476 transitions. Word has length 34 [2019-11-28 17:30:48,480 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:30:48,480 INFO L462 AbstractCegarLoop]: Abstraction has 352 states and 476 transitions. [2019-11-28 17:30:48,481 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 17:30:48,481 INFO L276 IsEmpty]: Start isEmpty. Operand 352 states and 476 transitions. [2019-11-28 17:30:48,482 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-11-28 17:30:48,482 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:30:48,483 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:30:48,483 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:30:48,483 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:30:48,484 INFO L82 PathProgramCache]: Analyzing trace with hash 1526891151, now seen corresponding path program 1 times [2019-11-28 17:30:48,484 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:30:48,484 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1256443790] [2019-11-28 17:30:48,485 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:30:48,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:30:48,555 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:30:48,555 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1256443790] [2019-11-28 17:30:48,556 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:30:48,556 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 17:30:48,557 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1615992967] [2019-11-28 17:30:48,557 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 17:30:48,558 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:30:48,558 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 17:30:48,558 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 17:30:48,559 INFO L87 Difference]: Start difference. First operand 352 states and 476 transitions. Second operand 4 states. [2019-11-28 17:30:48,747 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:30:48,747 INFO L93 Difference]: Finished difference Result 1638 states and 2239 transitions. [2019-11-28 17:30:48,748 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 17:30:48,748 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 34 [2019-11-28 17:30:48,748 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:30:48,757 INFO L225 Difference]: With dead ends: 1638 [2019-11-28 17:30:48,757 INFO L226 Difference]: Without dead ends: 1304 [2019-11-28 17:30:48,759 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:30:48,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1304 states. [2019-11-28 17:30:48,843 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1304 to 662. [2019-11-28 17:30:48,843 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 662 states. [2019-11-28 17:30:48,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 662 states to 662 states and 900 transitions. [2019-11-28 17:30:48,846 INFO L78 Accepts]: Start accepts. Automaton has 662 states and 900 transitions. Word has length 34 [2019-11-28 17:30:48,847 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:30:48,847 INFO L462 AbstractCegarLoop]: Abstraction has 662 states and 900 transitions. [2019-11-28 17:30:48,847 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 17:30:48,847 INFO L276 IsEmpty]: Start isEmpty. Operand 662 states and 900 transitions. [2019-11-28 17:30:48,848 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2019-11-28 17:30:48,849 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:30:48,849 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:30:48,849 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:30:48,850 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:30:48,850 INFO L82 PathProgramCache]: Analyzing trace with hash -1026068075, now seen corresponding path program 1 times [2019-11-28 17:30:48,850 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:30:48,850 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1930020624] [2019-11-28 17:30:48,851 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:30:48,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:30:48,904 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:30:48,904 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1930020624] [2019-11-28 17:30:48,905 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:30:48,905 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 17:30:48,905 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [795864444] [2019-11-28 17:30:48,906 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 17:30:48,906 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:30:48,906 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 17:30:48,906 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-28 17:30:48,906 INFO L87 Difference]: Start difference. First operand 662 states and 900 transitions. Second operand 4 states. [2019-11-28 17:30:49,069 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:30:49,069 INFO L93 Difference]: Finished difference Result 1626 states and 2222 transitions. [2019-11-28 17:30:49,070 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-28 17:30:49,070 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 41 [2019-11-28 17:30:49,071 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:30:49,076 INFO L225 Difference]: With dead ends: 1626 [2019-11-28 17:30:49,077 INFO L226 Difference]: Without dead ends: 982 [2019-11-28 17:30:49,078 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-28 17:30:49,080 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 982 states. [2019-11-28 17:30:49,191 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 982 to 972. [2019-11-28 17:30:49,191 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 972 states. [2019-11-28 17:30:49,195 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 972 states to 972 states and 1324 transitions. [2019-11-28 17:30:49,195 INFO L78 Accepts]: Start accepts. Automaton has 972 states and 1324 transitions. Word has length 41 [2019-11-28 17:30:49,196 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:30:49,196 INFO L462 AbstractCegarLoop]: Abstraction has 972 states and 1324 transitions. [2019-11-28 17:30:49,196 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 17:30:49,196 INFO L276 IsEmpty]: Start isEmpty. Operand 972 states and 1324 transitions. [2019-11-28 17:30:49,197 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2019-11-28 17:30:49,197 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:30:49,198 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:30:49,198 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:30:49,198 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:30:49,198 INFO L82 PathProgramCache]: Analyzing trace with hash -305826283, now seen corresponding path program 1 times [2019-11-28 17:30:49,199 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:30:49,199 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2018122320] [2019-11-28 17:30:49,199 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:30:49,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:30:49,273 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:30:49,274 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2018122320] [2019-11-28 17:30:49,274 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:30:49,274 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-28 17:30:49,274 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1219175062] [2019-11-28 17:30:49,276 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-28 17:30:49,276 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:30:49,277 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-28 17:30:49,277 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2019-11-28 17:30:49,277 INFO L87 Difference]: Start difference. First operand 972 states and 1324 transitions. Second operand 6 states. [2019-11-28 17:30:49,651 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:30:49,652 INFO L93 Difference]: Finished difference Result 3850 states and 5260 transitions. [2019-11-28 17:30:49,652 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-11-28 17:30:49,652 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 44 [2019-11-28 17:30:49,653 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:30:49,670 INFO L225 Difference]: With dead ends: 3850 [2019-11-28 17:30:49,670 INFO L226 Difference]: Without dead ends: 2896 [2019-11-28 17:30:49,672 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2019-11-28 17:30:49,676 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2896 states. [2019-11-28 17:30:49,833 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2896 to 1606. [2019-11-28 17:30:49,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1606 states. [2019-11-28 17:30:49,839 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1606 states to 1606 states and 2192 transitions. [2019-11-28 17:30:49,839 INFO L78 Accepts]: Start accepts. Automaton has 1606 states and 2192 transitions. Word has length 44 [2019-11-28 17:30:49,840 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:30:49,840 INFO L462 AbstractCegarLoop]: Abstraction has 1606 states and 2192 transitions. [2019-11-28 17:30:49,840 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-28 17:30:49,840 INFO L276 IsEmpty]: Start isEmpty. Operand 1606 states and 2192 transitions. [2019-11-28 17:30:49,841 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2019-11-28 17:30:49,841 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:30:49,841 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:30:49,841 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:30:49,842 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:30:49,842 INFO L82 PathProgramCache]: Analyzing trace with hash -1702134670, now seen corresponding path program 1 times [2019-11-28 17:30:49,842 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:30:49,842 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2113123743] [2019-11-28 17:30:49,843 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:30:49,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:30:49,872 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2019-11-28 17:30:49,872 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2113123743] [2019-11-28 17:30:49,873 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:30:49,873 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:30:49,873 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [18684548] [2019-11-28 17:30:49,873 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:30:49,875 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:30:49,875 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:30:49,875 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:30:49,876 INFO L87 Difference]: Start difference. First operand 1606 states and 2192 transitions. Second operand 3 states. [2019-11-28 17:30:50,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:30:50,176 INFO L93 Difference]: Finished difference Result 4614 states and 6233 transitions. [2019-11-28 17:30:50,177 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:30:50,177 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 46 [2019-11-28 17:30:50,177 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:30:50,193 INFO L225 Difference]: With dead ends: 4614 [2019-11-28 17:30:50,193 INFO L226 Difference]: Without dead ends: 3026 [2019-11-28 17:30:50,197 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:30:50,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3026 states. [2019-11-28 17:30:50,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3026 to 3022. [2019-11-28 17:30:50,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3022 states. [2019-11-28 17:30:50,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3022 states to 3022 states and 3978 transitions. [2019-11-28 17:30:50,530 INFO L78 Accepts]: Start accepts. Automaton has 3022 states and 3978 transitions. Word has length 46 [2019-11-28 17:30:50,530 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:30:50,531 INFO L462 AbstractCegarLoop]: Abstraction has 3022 states and 3978 transitions. [2019-11-28 17:30:50,531 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:30:50,531 INFO L276 IsEmpty]: Start isEmpty. Operand 3022 states and 3978 transitions. [2019-11-28 17:30:50,532 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2019-11-28 17:30:50,532 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:30:50,532 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:30:50,532 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:30:50,533 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:30:50,533 INFO L82 PathProgramCache]: Analyzing trace with hash 1664931104, now seen corresponding path program 1 times [2019-11-28 17:30:50,533 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:30:50,533 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [432787315] [2019-11-28 17:30:50,533 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:30:50,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:30:50,560 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:30:50,560 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [432787315] [2019-11-28 17:30:50,560 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:30:50,561 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:30:50,561 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1285334329] [2019-11-28 17:30:50,561 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:30:50,561 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:30:50,562 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:30:50,562 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:30:50,562 INFO L87 Difference]: Start difference. First operand 3022 states and 3978 transitions. Second operand 3 states. [2019-11-28 17:30:50,983 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:30:50,983 INFO L93 Difference]: Finished difference Result 8013 states and 10530 transitions. [2019-11-28 17:30:50,984 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:30:50,984 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2019-11-28 17:30:50,984 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:30:51,017 INFO L225 Difference]: With dead ends: 8013 [2019-11-28 17:30:51,017 INFO L226 Difference]: Without dead ends: 5023 [2019-11-28 17:30:51,024 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:30:51,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5023 states. [2019-11-28 17:30:51,405 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5023 to 4273. [2019-11-28 17:30:51,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4273 states. [2019-11-28 17:30:51,421 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4273 states to 4273 states and 5593 transitions. [2019-11-28 17:30:51,422 INFO L78 Accepts]: Start accepts. Automaton has 4273 states and 5593 transitions. Word has length 48 [2019-11-28 17:30:51,424 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:30:51,424 INFO L462 AbstractCegarLoop]: Abstraction has 4273 states and 5593 transitions. [2019-11-28 17:30:51,424 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:30:51,425 INFO L276 IsEmpty]: Start isEmpty. Operand 4273 states and 5593 transitions. [2019-11-28 17:30:51,427 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2019-11-28 17:30:51,427 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:30:51,428 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:30:51,428 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:30:51,428 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:30:51,429 INFO L82 PathProgramCache]: Analyzing trace with hash 403090641, now seen corresponding path program 1 times [2019-11-28 17:30:51,429 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:30:51,429 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1975941365] [2019-11-28 17:30:51,430 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:30:51,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:30:51,506 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:30:51,507 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1975941365] [2019-11-28 17:30:51,507 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:30:51,508 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:30:51,508 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [424435142] [2019-11-28 17:30:51,510 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:30:51,510 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:30:51,511 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:30:51,511 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:30:51,512 INFO L87 Difference]: Start difference. First operand 4273 states and 5593 transitions. Second operand 3 states. [2019-11-28 17:30:51,989 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:30:51,990 INFO L93 Difference]: Finished difference Result 8516 states and 11154 transitions. [2019-11-28 17:30:51,990 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:30:51,991 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2019-11-28 17:30:51,992 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:30:52,013 INFO L225 Difference]: With dead ends: 8516 [2019-11-28 17:30:52,013 INFO L226 Difference]: Without dead ends: 4275 [2019-11-28 17:30:52,021 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:30:52,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4275 states. [2019-11-28 17:30:52,336 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4275 to 4273. [2019-11-28 17:30:52,337 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4273 states. [2019-11-28 17:30:52,356 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4273 states to 4273 states and 5518 transitions. [2019-11-28 17:30:52,356 INFO L78 Accepts]: Start accepts. Automaton has 4273 states and 5518 transitions. Word has length 48 [2019-11-28 17:30:52,358 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:30:52,358 INFO L462 AbstractCegarLoop]: Abstraction has 4273 states and 5518 transitions. [2019-11-28 17:30:52,358 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:30:52,358 INFO L276 IsEmpty]: Start isEmpty. Operand 4273 states and 5518 transitions. [2019-11-28 17:30:52,360 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-11-28 17:30:52,360 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:30:52,361 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:30:52,361 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:30:52,361 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:30:52,362 INFO L82 PathProgramCache]: Analyzing trace with hash 57108908, now seen corresponding path program 1 times [2019-11-28 17:30:52,362 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:30:52,364 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [758694222] [2019-11-28 17:30:52,364 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:30:52,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:30:52,403 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:30:52,404 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [758694222] [2019-11-28 17:30:52,404 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:30:52,404 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:30:52,404 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1533174959] [2019-11-28 17:30:52,405 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:30:52,405 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:30:52,405 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:30:52,406 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:30:52,406 INFO L87 Difference]: Start difference. First operand 4273 states and 5518 transitions. Second operand 3 states. [2019-11-28 17:30:52,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:30:52,693 INFO L93 Difference]: Finished difference Result 7967 states and 10312 transitions. [2019-11-28 17:30:52,693 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:30:52,694 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 49 [2019-11-28 17:30:52,694 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:30:52,710 INFO L225 Difference]: With dead ends: 7967 [2019-11-28 17:30:52,711 INFO L226 Difference]: Without dead ends: 3610 [2019-11-28 17:30:52,718 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:30:52,722 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3610 states. [2019-11-28 17:30:52,983 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3610 to 3465. [2019-11-28 17:30:52,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3465 states. [2019-11-28 17:30:52,991 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3465 states to 3465 states and 4400 transitions. [2019-11-28 17:30:52,992 INFO L78 Accepts]: Start accepts. Automaton has 3465 states and 4400 transitions. Word has length 49 [2019-11-28 17:30:52,992 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:30:52,992 INFO L462 AbstractCegarLoop]: Abstraction has 3465 states and 4400 transitions. [2019-11-28 17:30:52,992 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:30:52,992 INFO L276 IsEmpty]: Start isEmpty. Operand 3465 states and 4400 transitions. [2019-11-28 17:30:52,995 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2019-11-28 17:30:52,995 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:30:52,995 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:30:52,996 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:30:52,996 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:30:52,996 INFO L82 PathProgramCache]: Analyzing trace with hash 652914839, now seen corresponding path program 1 times [2019-11-28 17:30:52,996 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:30:52,997 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [752802959] [2019-11-28 17:30:52,997 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:30:53,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:30:53,040 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 19 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-11-28 17:30:53,041 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [752802959] [2019-11-28 17:30:53,041 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:30:53,041 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 17:30:53,041 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1244122405] [2019-11-28 17:30:53,042 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:30:53,042 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:30:53,042 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:30:53,042 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:30:53,043 INFO L87 Difference]: Start difference. First operand 3465 states and 4400 transitions. Second operand 3 states. [2019-11-28 17:30:53,336 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:30:53,336 INFO L93 Difference]: Finished difference Result 6369 states and 8143 transitions. [2019-11-28 17:30:53,337 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:30:53,337 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 83 [2019-11-28 17:30:53,338 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:30:53,378 INFO L225 Difference]: With dead ends: 6369 [2019-11-28 17:30:53,378 INFO L226 Difference]: Without dead ends: 3465 [2019-11-28 17:30:53,386 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:30:53,392 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3465 states. [2019-11-28 17:30:53,664 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3465 to 3465. [2019-11-28 17:30:53,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3465 states. [2019-11-28 17:30:53,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3465 states to 3465 states and 4336 transitions. [2019-11-28 17:30:53,675 INFO L78 Accepts]: Start accepts. Automaton has 3465 states and 4336 transitions. Word has length 83 [2019-11-28 17:30:53,675 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:30:53,675 INFO L462 AbstractCegarLoop]: Abstraction has 3465 states and 4336 transitions. [2019-11-28 17:30:53,675 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:30:53,675 INFO L276 IsEmpty]: Start isEmpty. Operand 3465 states and 4336 transitions. [2019-11-28 17:30:53,684 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2019-11-28 17:30:53,684 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:30:53,685 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:30:53,685 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:30:53,685 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:30:53,685 INFO L82 PathProgramCache]: Analyzing trace with hash -608848062, now seen corresponding path program 1 times [2019-11-28 17:30:53,686 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:30:53,692 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [217445483] [2019-11-28 17:30:53,692 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:30:53,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:30:53,748 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 25 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:30:53,748 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [217445483] [2019-11-28 17:30:53,749 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:30:53,750 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:30:53,750 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1603897831] [2019-11-28 17:30:53,751 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:30:53,751 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:30:53,751 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:30:53,751 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:30:53,752 INFO L87 Difference]: Start difference. First operand 3465 states and 4336 transitions. Second operand 3 states. [2019-11-28 17:30:54,102 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:30:54,102 INFO L93 Difference]: Finished difference Result 7371 states and 9260 transitions. [2019-11-28 17:30:54,103 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:30:54,103 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 84 [2019-11-28 17:30:54,103 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:30:54,123 INFO L225 Difference]: With dead ends: 7371 [2019-11-28 17:30:54,123 INFO L226 Difference]: Without dead ends: 4154 [2019-11-28 17:30:54,130 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:30:54,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4154 states. [2019-11-28 17:30:54,525 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4154 to 3700. [2019-11-28 17:30:54,525 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3700 states. [2019-11-28 17:30:54,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3700 states to 3700 states and 4553 transitions. [2019-11-28 17:30:54,531 INFO L78 Accepts]: Start accepts. Automaton has 3700 states and 4553 transitions. Word has length 84 [2019-11-28 17:30:54,531 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:30:54,531 INFO L462 AbstractCegarLoop]: Abstraction has 3700 states and 4553 transitions. [2019-11-28 17:30:54,532 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:30:54,532 INFO L276 IsEmpty]: Start isEmpty. Operand 3700 states and 4553 transitions. [2019-11-28 17:30:54,533 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2019-11-28 17:30:54,534 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:30:54,534 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:30:54,534 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:30:54,534 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:30:54,534 INFO L82 PathProgramCache]: Analyzing trace with hash 885528412, now seen corresponding path program 1 times [2019-11-28 17:30:54,535 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:30:54,535 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1021119757] [2019-11-28 17:30:54,535 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:30:54,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:30:54,579 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-11-28 17:30:54,580 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1021119757] [2019-11-28 17:30:54,580 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:30:54,580 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 17:30:54,581 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [174853239] [2019-11-28 17:30:54,581 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:30:54,581 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:30:54,581 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:30:54,582 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:30:54,582 INFO L87 Difference]: Start difference. First operand 3700 states and 4553 transitions. Second operand 3 states. [2019-11-28 17:30:54,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:30:54,799 INFO L93 Difference]: Finished difference Result 7674 states and 9427 transitions. [2019-11-28 17:30:54,800 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:30:54,800 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 86 [2019-11-28 17:30:54,800 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:30:54,807 INFO L225 Difference]: With dead ends: 7674 [2019-11-28 17:30:54,807 INFO L226 Difference]: Without dead ends: 4176 [2019-11-28 17:30:54,812 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:30:54,816 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4176 states. [2019-11-28 17:30:55,057 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4176 to 4174. [2019-11-28 17:30:55,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4174 states. [2019-11-28 17:30:55,063 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4174 states to 4174 states and 5092 transitions. [2019-11-28 17:30:55,063 INFO L78 Accepts]: Start accepts. Automaton has 4174 states and 5092 transitions. Word has length 86 [2019-11-28 17:30:55,063 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:30:55,063 INFO L462 AbstractCegarLoop]: Abstraction has 4174 states and 5092 transitions. [2019-11-28 17:30:55,063 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:30:55,063 INFO L276 IsEmpty]: Start isEmpty. Operand 4174 states and 5092 transitions. [2019-11-28 17:30:55,065 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2019-11-28 17:30:55,065 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:30:55,066 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:30:55,066 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:30:55,066 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:30:55,066 INFO L82 PathProgramCache]: Analyzing trace with hash 1836340184, now seen corresponding path program 1 times [2019-11-28 17:30:55,067 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:30:55,067 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1276054193] [2019-11-28 17:30:55,067 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:30:55,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:30:55,103 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 27 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:30:55,104 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1276054193] [2019-11-28 17:30:55,106 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:30:55,106 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:30:55,106 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [749419315] [2019-11-28 17:30:55,107 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:30:55,107 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:30:55,107 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:30:55,107 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:30:55,107 INFO L87 Difference]: Start difference. First operand 4174 states and 5092 transitions. Second operand 3 states. [2019-11-28 17:30:55,312 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:30:55,312 INFO L93 Difference]: Finished difference Result 7056 states and 8680 transitions. [2019-11-28 17:30:55,312 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:30:55,312 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 98 [2019-11-28 17:30:55,313 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:30:55,319 INFO L225 Difference]: With dead ends: 7056 [2019-11-28 17:30:55,319 INFO L226 Difference]: Without dead ends: 3227 [2019-11-28 17:30:55,325 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:30:55,329 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3227 states. [2019-11-28 17:30:55,561 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3227 to 3223. [2019-11-28 17:30:55,561 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3223 states. [2019-11-28 17:30:55,565 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3223 states to 3223 states and 3862 transitions. [2019-11-28 17:30:55,565 INFO L78 Accepts]: Start accepts. Automaton has 3223 states and 3862 transitions. Word has length 98 [2019-11-28 17:30:55,565 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:30:55,565 INFO L462 AbstractCegarLoop]: Abstraction has 3223 states and 3862 transitions. [2019-11-28 17:30:55,566 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:30:55,566 INFO L276 IsEmpty]: Start isEmpty. Operand 3223 states and 3862 transitions. [2019-11-28 17:30:55,568 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2019-11-28 17:30:55,568 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:30:55,568 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:30:55,569 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:30:55,569 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:30:55,569 INFO L82 PathProgramCache]: Analyzing trace with hash 1328739563, now seen corresponding path program 1 times [2019-11-28 17:30:55,569 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:30:55,569 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1733400409] [2019-11-28 17:30:55,570 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:30:55,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:30:55,608 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-11-28 17:30:55,609 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1733400409] [2019-11-28 17:30:55,609 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:30:55,609 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 17:30:55,609 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [894907799] [2019-11-28 17:30:55,609 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:30:55,610 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:30:55,610 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:30:55,610 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:30:55,610 INFO L87 Difference]: Start difference. First operand 3223 states and 3862 transitions. Second operand 3 states. [2019-11-28 17:30:55,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:30:55,762 INFO L93 Difference]: Finished difference Result 5622 states and 6780 transitions. [2019-11-28 17:30:55,763 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:30:55,763 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 99 [2019-11-28 17:30:55,763 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:30:55,768 INFO L225 Difference]: With dead ends: 5622 [2019-11-28 17:30:55,768 INFO L226 Difference]: Without dead ends: 3075 [2019-11-28 17:30:55,772 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:30:55,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3075 states. [2019-11-28 17:30:55,927 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3075 to 3075. [2019-11-28 17:30:55,928 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3075 states. [2019-11-28 17:30:55,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3075 states to 3075 states and 3691 transitions. [2019-11-28 17:30:55,932 INFO L78 Accepts]: Start accepts. Automaton has 3075 states and 3691 transitions. Word has length 99 [2019-11-28 17:30:55,932 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:30:55,932 INFO L462 AbstractCegarLoop]: Abstraction has 3075 states and 3691 transitions. [2019-11-28 17:30:55,932 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:30:55,933 INFO L276 IsEmpty]: Start isEmpty. Operand 3075 states and 3691 transitions. [2019-11-28 17:30:55,935 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2019-11-28 17:30:55,935 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:30:55,936 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:30:55,936 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:30:55,936 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:30:55,936 INFO L82 PathProgramCache]: Analyzing trace with hash -472369520, now seen corresponding path program 1 times [2019-11-28 17:30:55,936 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:30:55,937 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1028375050] [2019-11-28 17:30:55,937 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:30:55,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:30:56,004 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 23 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2019-11-28 17:30:56,004 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1028375050] [2019-11-28 17:30:56,004 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:30:56,005 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-11-28 17:30:56,005 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1415831549] [2019-11-28 17:30:56,005 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-11-28 17:30:56,005 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:30:56,005 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-11-28 17:30:56,006 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2019-11-28 17:30:56,006 INFO L87 Difference]: Start difference. First operand 3075 states and 3691 transitions. Second operand 8 states. [2019-11-28 17:30:56,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:30:56,287 INFO L93 Difference]: Finished difference Result 5286 states and 6380 transitions. [2019-11-28 17:30:56,287 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-11-28 17:30:56,288 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 104 [2019-11-28 17:30:56,288 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:30:56,293 INFO L225 Difference]: With dead ends: 5286 [2019-11-28 17:30:56,293 INFO L226 Difference]: Without dead ends: 2229 [2019-11-28 17:30:56,298 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=80, Unknown=0, NotChecked=0, Total=110 [2019-11-28 17:30:56,300 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2229 states. [2019-11-28 17:30:56,438 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2229 to 1920. [2019-11-28 17:30:56,438 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1920 states. [2019-11-28 17:30:56,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1920 states to 1920 states and 2325 transitions. [2019-11-28 17:30:56,441 INFO L78 Accepts]: Start accepts. Automaton has 1920 states and 2325 transitions. Word has length 104 [2019-11-28 17:30:56,442 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:30:56,442 INFO L462 AbstractCegarLoop]: Abstraction has 1920 states and 2325 transitions. [2019-11-28 17:30:56,442 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-11-28 17:30:56,442 INFO L276 IsEmpty]: Start isEmpty. Operand 1920 states and 2325 transitions. [2019-11-28 17:30:56,444 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2019-11-28 17:30:56,444 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:30:56,444 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:30:56,445 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:30:56,445 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:30:56,445 INFO L82 PathProgramCache]: Analyzing trace with hash 663738500, now seen corresponding path program 1 times [2019-11-28 17:30:56,445 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:30:56,446 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [911807753] [2019-11-28 17:30:56,446 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:30:56,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:30:56,521 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-11-28 17:30:56,522 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [911807753] [2019-11-28 17:30:56,522 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:30:56,522 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 17:30:56,522 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [935026032] [2019-11-28 17:30:56,524 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 17:30:56,524 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:30:56,524 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 17:30:56,524 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-28 17:30:56,524 INFO L87 Difference]: Start difference. First operand 1920 states and 2325 transitions. Second operand 4 states. [2019-11-28 17:30:56,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:30:56,791 INFO L93 Difference]: Finished difference Result 4180 states and 5082 transitions. [2019-11-28 17:30:56,791 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-28 17:30:56,792 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 107 [2019-11-28 17:30:56,792 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:30:56,797 INFO L225 Difference]: With dead ends: 4180 [2019-11-28 17:30:56,798 INFO L226 Difference]: Without dead ends: 2423 [2019-11-28 17:30:56,801 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-28 17:30:56,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2423 states. [2019-11-28 17:30:56,963 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2423 to 2324. [2019-11-28 17:30:56,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2324 states. [2019-11-28 17:30:56,966 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2324 states to 2324 states and 2802 transitions. [2019-11-28 17:30:56,966 INFO L78 Accepts]: Start accepts. Automaton has 2324 states and 2802 transitions. Word has length 107 [2019-11-28 17:30:56,967 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:30:56,967 INFO L462 AbstractCegarLoop]: Abstraction has 2324 states and 2802 transitions. [2019-11-28 17:30:56,967 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 17:30:56,967 INFO L276 IsEmpty]: Start isEmpty. Operand 2324 states and 2802 transitions. [2019-11-28 17:30:56,968 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2019-11-28 17:30:56,968 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:30:56,969 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:30:56,969 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:30:56,969 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:30:56,969 INFO L82 PathProgramCache]: Analyzing trace with hash -1105184803, now seen corresponding path program 1 times [2019-11-28 17:30:56,970 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:30:56,970 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [912433653] [2019-11-28 17:30:56,970 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:30:56,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:30:57,013 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:30:57,013 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [912433653] [2019-11-28 17:30:57,013 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:30:57,014 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:30:57,014 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1736624503] [2019-11-28 17:30:57,014 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:30:57,014 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:30:57,015 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:30:57,015 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:30:57,015 INFO L87 Difference]: Start difference. First operand 2324 states and 2802 transitions. Second operand 3 states. [2019-11-28 17:30:57,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:30:57,191 INFO L93 Difference]: Finished difference Result 3902 states and 4743 transitions. [2019-11-28 17:30:57,191 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:30:57,191 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 113 [2019-11-28 17:30:57,192 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:30:57,196 INFO L225 Difference]: With dead ends: 3902 [2019-11-28 17:30:57,196 INFO L226 Difference]: Without dead ends: 1655 [2019-11-28 17:30:57,199 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:30:57,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1655 states. [2019-11-28 17:30:57,306 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1655 to 1653. [2019-11-28 17:30:57,306 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1653 states. [2019-11-28 17:30:57,308 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1653 states to 1653 states and 1933 transitions. [2019-11-28 17:30:57,308 INFO L78 Accepts]: Start accepts. Automaton has 1653 states and 1933 transitions. Word has length 113 [2019-11-28 17:30:57,308 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:30:57,308 INFO L462 AbstractCegarLoop]: Abstraction has 1653 states and 1933 transitions. [2019-11-28 17:30:57,308 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:30:57,309 INFO L276 IsEmpty]: Start isEmpty. Operand 1653 states and 1933 transitions. [2019-11-28 17:30:57,310 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2019-11-28 17:30:57,310 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:30:57,310 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:30:57,310 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:30:57,310 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:30:57,311 INFO L82 PathProgramCache]: Analyzing trace with hash 1508765653, now seen corresponding path program 1 times [2019-11-28 17:30:57,311 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:30:57,311 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [793742226] [2019-11-28 17:30:57,311 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:30:57,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:30:57,370 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-11-28 17:30:57,371 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [793742226] [2019-11-28 17:30:57,372 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:30:57,372 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 17:30:57,372 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1097168688] [2019-11-28 17:30:57,373 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 17:30:57,373 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:30:57,373 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 17:30:57,373 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:30:57,374 INFO L87 Difference]: Start difference. First operand 1653 states and 1933 transitions. Second operand 5 states. [2019-11-28 17:30:57,670 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:30:57,670 INFO L93 Difference]: Finished difference Result 4188 states and 4920 transitions. [2019-11-28 17:30:57,671 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-11-28 17:30:57,671 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 114 [2019-11-28 17:30:57,672 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:30:57,677 INFO L225 Difference]: With dead ends: 4188 [2019-11-28 17:30:57,677 INFO L226 Difference]: Without dead ends: 2940 [2019-11-28 17:30:57,680 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-11-28 17:30:57,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2940 states. [2019-11-28 17:30:57,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2940 to 1905. [2019-11-28 17:30:57,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1905 states. [2019-11-28 17:30:57,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1905 states to 1905 states and 2228 transitions. [2019-11-28 17:30:57,838 INFO L78 Accepts]: Start accepts. Automaton has 1905 states and 2228 transitions. Word has length 114 [2019-11-28 17:30:57,838 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:30:57,838 INFO L462 AbstractCegarLoop]: Abstraction has 1905 states and 2228 transitions. [2019-11-28 17:30:57,839 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 17:30:57,839 INFO L276 IsEmpty]: Start isEmpty. Operand 1905 states and 2228 transitions. [2019-11-28 17:30:57,840 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2019-11-28 17:30:57,840 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:30:57,841 INFO L410 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:30:57,841 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:30:57,841 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:30:57,841 INFO L82 PathProgramCache]: Analyzing trace with hash -1919382230, now seen corresponding path program 1 times [2019-11-28 17:30:57,842 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:30:57,842 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [8750973] [2019-11-28 17:30:57,842 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:30:57,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:30:57,942 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 0 proven. 35 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-11-28 17:30:57,943 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [8750973] [2019-11-28 17:30:57,943 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [75846298] [2019-11-28 17:30:57,943 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-28 17:30:58,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:30:58,035 INFO L264 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 9 conjunts are in the unsatisfiable core [2019-11-28 17:30:58,044 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-11-28 17:30:58,074 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 0 proven. 35 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-11-28 17:30:58,075 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-28 17:30:58,075 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 5 [2019-11-28 17:30:58,076 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [887872535] [2019-11-28 17:30:58,076 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 17:30:58,076 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:30:58,077 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 17:30:58,077 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:30:58,077 INFO L87 Difference]: Start difference. First operand 1905 states and 2228 transitions. Second operand 5 states. [2019-11-28 17:30:58,635 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:30:58,635 INFO L93 Difference]: Finished difference Result 4107 states and 4811 transitions. [2019-11-28 17:30:58,636 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-11-28 17:30:58,636 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 118 [2019-11-28 17:30:58,636 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:30:58,644 INFO L225 Difference]: With dead ends: 4107 [2019-11-28 17:30:58,644 INFO L226 Difference]: Without dead ends: 3084 [2019-11-28 17:30:58,647 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 125 GetRequests, 119 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-11-28 17:30:58,652 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3084 states. [2019-11-28 17:30:58,932 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3084 to 2067. [2019-11-28 17:30:58,932 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2067 states. [2019-11-28 17:30:58,936 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2067 states to 2067 states and 2410 transitions. [2019-11-28 17:30:58,936 INFO L78 Accepts]: Start accepts. Automaton has 2067 states and 2410 transitions. Word has length 118 [2019-11-28 17:30:58,936 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:30:58,937 INFO L462 AbstractCegarLoop]: Abstraction has 2067 states and 2410 transitions. [2019-11-28 17:30:58,937 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 17:30:58,937 INFO L276 IsEmpty]: Start isEmpty. Operand 2067 states and 2410 transitions. [2019-11-28 17:30:58,942 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 173 [2019-11-28 17:30:58,942 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:30:58,943 INFO L410 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:30:59,149 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-28 17:30:59,150 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:30:59,150 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:30:59,151 INFO L82 PathProgramCache]: Analyzing trace with hash -2045968037, now seen corresponding path program 1 times [2019-11-28 17:30:59,151 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:30:59,151 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1839484717] [2019-11-28 17:30:59,152 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:30:59,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:30:59,286 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 129 proven. 0 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2019-11-28 17:30:59,291 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1839484717] [2019-11-28 17:30:59,291 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:30:59,291 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:30:59,291 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2130486265] [2019-11-28 17:30:59,292 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:30:59,293 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:30:59,293 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:30:59,293 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:30:59,294 INFO L87 Difference]: Start difference. First operand 2067 states and 2410 transitions. Second operand 3 states. [2019-11-28 17:30:59,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:30:59,800 INFO L93 Difference]: Finished difference Result 5041 states and 5868 transitions. [2019-11-28 17:30:59,801 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:30:59,801 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 172 [2019-11-28 17:30:59,801 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:30:59,816 INFO L225 Difference]: With dead ends: 5041 [2019-11-28 17:30:59,817 INFO L226 Difference]: Without dead ends: 3137 [2019-11-28 17:30:59,820 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:30:59,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3137 states. [2019-11-28 17:31:00,228 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3137 to 3087. [2019-11-28 17:31:00,228 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3087 states. [2019-11-28 17:31:00,232 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3087 states to 3087 states and 3575 transitions. [2019-11-28 17:31:00,232 INFO L78 Accepts]: Start accepts. Automaton has 3087 states and 3575 transitions. Word has length 172 [2019-11-28 17:31:00,232 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:31:00,232 INFO L462 AbstractCegarLoop]: Abstraction has 3087 states and 3575 transitions. [2019-11-28 17:31:00,232 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:31:00,233 INFO L276 IsEmpty]: Start isEmpty. Operand 3087 states and 3575 transitions. [2019-11-28 17:31:00,236 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 173 [2019-11-28 17:31:00,236 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:31:00,237 INFO L410 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:31:00,237 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:31:00,239 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:31:00,239 INFO L82 PathProgramCache]: Analyzing trace with hash 1191161181, now seen corresponding path program 1 times [2019-11-28 17:31:00,239 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:31:00,240 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [310872608] [2019-11-28 17:31:00,240 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:31:00,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:31:00,287 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 99 proven. 0 refuted. 0 times theorem prover too weak. 57 trivial. 0 not checked. [2019-11-28 17:31:00,287 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [310872608] [2019-11-28 17:31:00,287 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:31:00,288 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:31:00,288 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1379555991] [2019-11-28 17:31:00,290 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:31:00,290 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:31:00,291 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:31:00,291 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:31:00,291 INFO L87 Difference]: Start difference. First operand 3087 states and 3575 transitions. Second operand 3 states. [2019-11-28 17:31:00,432 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:31:00,433 INFO L93 Difference]: Finished difference Result 4589 states and 5331 transitions. [2019-11-28 17:31:00,433 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:31:00,433 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 172 [2019-11-28 17:31:00,433 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:31:00,436 INFO L225 Difference]: With dead ends: 4589 [2019-11-28 17:31:00,436 INFO L226 Difference]: Without dead ends: 1619 [2019-11-28 17:31:00,440 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:31:00,444 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1619 states. [2019-11-28 17:31:00,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1619 to 1619. [2019-11-28 17:31:00,568 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1619 states. [2019-11-28 17:31:00,570 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1619 states to 1619 states and 1839 transitions. [2019-11-28 17:31:00,570 INFO L78 Accepts]: Start accepts. Automaton has 1619 states and 1839 transitions. Word has length 172 [2019-11-28 17:31:00,570 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:31:00,570 INFO L462 AbstractCegarLoop]: Abstraction has 1619 states and 1839 transitions. [2019-11-28 17:31:00,570 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:31:00,570 INFO L276 IsEmpty]: Start isEmpty. Operand 1619 states and 1839 transitions. [2019-11-28 17:31:00,573 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 191 [2019-11-28 17:31:00,573 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:31:00,573 INFO L410 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:31:00,573 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:31:00,574 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:31:00,574 INFO L82 PathProgramCache]: Analyzing trace with hash 1404970223, now seen corresponding path program 1 times [2019-11-28 17:31:00,574 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:31:00,574 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1685157262] [2019-11-28 17:31:00,574 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:31:00,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 17:31:00,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 17:31:00,742 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-28 17:31:00,742 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-28 17:31:01,007 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 05:31:01 BoogieIcfgContainer [2019-11-28 17:31:01,007 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-28 17:31:01,008 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-28 17:31:01,008 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-28 17:31:01,008 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-28 17:31:01,009 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 05:30:47" (3/4) ... [2019-11-28 17:31:01,012 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-28 17:31:01,252 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2019-11-28 17:31:01,253 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-28 17:31:01,255 INFO L168 Benchmark]: Toolchain (without parser) took 15288.02 ms. Allocated memory was 1.0 GB in the beginning and 2.1 GB in the end (delta: 1.0 GB). Free memory was 953.6 MB in the beginning and 1.5 GB in the end (delta: -582.8 MB). Peak memory consumption was 462.6 MB. Max. memory is 11.5 GB. [2019-11-28 17:31:01,255 INFO L168 Benchmark]: CDTParser took 0.75 ms. Allocated memory is still 1.0 GB. Free memory is still 981.8 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 17:31:01,256 INFO L168 Benchmark]: CACSL2BoogieTranslator took 413.97 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 148.9 MB). Free memory was 953.6 MB in the beginning and 1.1 GB in the end (delta: -185.3 MB). Peak memory consumption was 26.1 MB. Max. memory is 11.5 GB. [2019-11-28 17:31:01,256 INFO L168 Benchmark]: Boogie Procedure Inliner took 49.67 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.5 MB). Peak memory consumption was 6.5 MB. Max. memory is 11.5 GB. [2019-11-28 17:31:01,257 INFO L168 Benchmark]: Boogie Preprocessor took 33.70 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 17:31:01,257 INFO L168 Benchmark]: RCFGBuilder took 577.77 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 36.9 MB). Peak memory consumption was 36.9 MB. Max. memory is 11.5 GB. [2019-11-28 17:31:01,258 INFO L168 Benchmark]: TraceAbstraction took 13962.55 ms. Allocated memory was 1.2 GB in the beginning and 2.1 GB in the end (delta: 896.5 MB). Free memory was 1.1 GB in the beginning and 1.6 GB in the end (delta: -464.9 MB). Peak memory consumption was 431.6 MB. Max. memory is 11.5 GB. [2019-11-28 17:31:01,258 INFO L168 Benchmark]: Witness Printer took 245.08 ms. Allocated memory is still 2.1 GB. Free memory was 1.6 GB in the beginning and 1.5 GB in the end (delta: 24.0 MB). Peak memory consumption was 24.0 MB. Max. memory is 11.5 GB. [2019-11-28 17:31:01,260 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.75 ms. Allocated memory is still 1.0 GB. Free memory is still 981.8 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 413.97 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 148.9 MB). Free memory was 953.6 MB in the beginning and 1.1 GB in the end (delta: -185.3 MB). Peak memory consumption was 26.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 49.67 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.5 MB). Peak memory consumption was 6.5 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 33.70 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 577.77 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 36.9 MB). Peak memory consumption was 36.9 MB. Max. memory is 11.5 GB. * TraceAbstraction took 13962.55 ms. Allocated memory was 1.2 GB in the beginning and 2.1 GB in the end (delta: 896.5 MB). Free memory was 1.1 GB in the beginning and 1.6 GB in the end (delta: -464.9 MB). Peak memory consumption was 431.6 MB. Max. memory is 11.5 GB. * Witness Printer took 245.08 ms. Allocated memory is still 2.1 GB. Free memory was 1.6 GB in the beginning and 1.5 GB in the end (delta: 24.0 MB). Peak memory consumption was 24.0 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 9]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int max_loop ; [L16] int num ; [L17] int i ; [L18] int e ; [L19] int timer ; [L20] char data_0 ; [L21] char data_1 ; [L64] int P_1_pc; [L65] int P_1_st ; [L66] int P_1_i ; [L67] int P_1_ev ; [L122] int C_1_pc ; [L123] int C_1_st ; [L124] int C_1_i ; [L125] int C_1_ev ; [L126] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, timer=0] [L490] int count ; [L491] int __retres2 ; [L495] num = 0 [L496] i = 0 [L497] max_loop = 2 [L499] timer = 0 [L500] P_1_pc = 0 [L501] C_1_pc = 0 [L503] count = 0 [L483] P_1_i = 1 [L484] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L421] int kernel_st ; [L422] int tmp ; [L423] int tmp___0 ; [L427] kernel_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L226] COND TRUE (int )P_1_i == 1 [L227] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L231] COND TRUE (int )C_1_i == 1 [L232] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; [L104] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L107] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L117] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L119] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L371] tmp = is_P_1_triggered() [L373] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L186] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L189] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L199] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L209] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L211] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L435] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L438] kernel_st = 1 [L262] int tmp ; [L263] int tmp___0 ; [L264] int tmp___1 ; [L265] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L269] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L241] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L258] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L294] COND TRUE (int )C_1_st == 0 [L296] tmp___1 = __VERIFIER_nondet_int() [L298] COND TRUE \read(tmp___1) [L300] C_1_st = 1 [L128] char c ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L131] COND TRUE (int )C_1_pc == 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L146] COND TRUE i < max_loop VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L148] COND TRUE num == 0 [L149] timer = 1 [L150] i += 1 [L151] C_1_pc = 1 [L152] C_1_st = 2 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L269] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L258] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND TRUE \read(tmp) [L285] P_1_st = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L72] COND TRUE (int )P_1_pc == 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L83] COND TRUE i < max_loop VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L49] COND TRUE i___0 == 0 [L50] data_0 = c VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L87] num += 1 [L88] P_1_pc = 1 [L89] P_1_st = 2 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L294] COND FALSE !((int )C_1_st == 0) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L269] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND FALSE !(\read(tmp___2)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L442] kernel_st = 2 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L446] kernel_st = 3 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; [L104] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND FALSE !((int )P_1_ev == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L117] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L186] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L190] COND FALSE !((int )e == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L209] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L211] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L452] tmp = exists_runnable_thread() [L454] COND TRUE tmp == 0 [L456] kernel_st = 4 [L336] C_1_ev = 1 [L338] P_1_ev = 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; [L104] int __retres1 ; VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND TRUE (int )P_1_ev == 1 [L109] __retres1 = 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND TRUE \read(tmp) [L374] P_1_st = 0 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L186] int __retres1 ; VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L190] COND FALSE !((int )e == 1) VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L209] __retres1 = 0 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L211] return (__retres1); VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L350] COND TRUE (int )P_1_ev == 1 [L351] P_1_ev = 2 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L355] COND TRUE (int )C_1_ev == 1 [L356] C_1_ev = 2 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L402] int tmp ; [L403] int __retres2 ; [L241] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] tmp = exists_runnable_thread() [L409] COND TRUE \read(tmp) [L410] __retres2 = 0 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L417] return (__retres2); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L465] tmp___0 = stop_simulation() [L467] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L435] COND TRUE 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L438] kernel_st = 1 [L262] int tmp ; [L263] int tmp___0 ; [L264] int tmp___1 ; [L265] int tmp___2 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L269] COND TRUE 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND TRUE \read(tmp) [L285] P_1_st = 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L72] COND FALSE !((int )P_1_pc == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L75] COND TRUE (int )P_1_pc == 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L83] COND TRUE i < max_loop VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L49] COND FALSE !(i___0 == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L52] COND TRUE i___0 == 1 [L53] data_1 = c VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L87] num += 1 [L88] P_1_pc = 1 [L89] P_1_st = 2 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L294] COND FALSE !((int )C_1_st == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L269] COND TRUE 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND FALSE !(\read(tmp___2)) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L442] kernel_st = 2 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L446] kernel_st = 3 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; [L104] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND FALSE !((int )P_1_ev == 1) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L117] __retres1 = 0 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND FALSE !(\read(tmp)) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L186] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L190] COND FALSE !((int )e == 1) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L209] __retres1 = 0 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L211] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L452] tmp = exists_runnable_thread() [L454] COND TRUE tmp == 0 [L456] kernel_st = 4 [L336] C_1_ev = 1 [L338] P_1_ev = 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; [L104] int __retres1 ; VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND TRUE (int )P_1_ev == 1 [L109] __retres1 = 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND TRUE \read(tmp) [L374] P_1_st = 0 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L186] int __retres1 ; VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L190] COND FALSE !((int )e == 1) VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L209] __retres1 = 0 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L211] return (__retres1); VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L350] COND TRUE (int )P_1_ev == 1 [L351] P_1_ev = 2 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L355] COND TRUE (int )C_1_ev == 1 [L356] C_1_ev = 2 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L402] int tmp ; [L403] int __retres2 ; [L241] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] tmp = exists_runnable_thread() [L409] COND TRUE \read(tmp) [L410] __retres2 = 0 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L417] return (__retres2); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L465] tmp___0 = stop_simulation() [L467] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L435] COND TRUE 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L438] kernel_st = 1 [L262] int tmp ; [L263] int tmp___0 ; [L264] int tmp___1 ; [L265] int tmp___2 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L269] COND TRUE 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND TRUE \read(tmp) [L285] P_1_st = 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L72] COND FALSE !((int )P_1_pc == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L75] COND TRUE (int )P_1_pc == 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L83] COND TRUE i < max_loop VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L49] COND FALSE !(i___0 == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L52] COND FALSE !(i___0 == 1) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L9] __VERIFIER_error() VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 117 locations, 3 error locations. Result: UNSAFE, OverallTime: 13.6s, OverallIterations: 25, TraceHistogramMax: 6, AutomataDifference: 6.6s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 4775 SDtfs, 4830 SDslu, 6046 SDs, 0 SdLazy, 568 SolverSat, 139 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.6s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 232 GetRequests, 169 SyntacticMatches, 3 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.4s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=4273occurred in iteration=10, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 4.6s AutomataMinimizationTime, 24 MinimizatonAttempts, 6607 StatesRemovedByMinimization, 20 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 0.9s InterpolantComputationTime, 2135 NumberOfCodeBlocks, 2135 NumberOfCodeBlocksAsserted, 26 NumberOfCheckSat, 1920 ConstructedInterpolants, 0 QuantifiedInterpolants, 350700 SizeOfPredicates, 2 NumberOfNonLiveVariables, 344 ConjunctsInSsa, 9 ConjunctsInUnsatCore, 25 InterpolantComputations, 23 PerfectInterpolantSequences, 619/689 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...