./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/pthread-wmm/mix042_pso.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx12G -Xms1G -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/pthread-wmm/mix042_pso.opt.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e635a02f2d7438928806d3267842b22f0deee00c ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-11-28 18:15:06,561 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-28 18:15:06,563 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-28 18:15:06,575 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-28 18:15:06,576 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-28 18:15:06,577 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-28 18:15:06,579 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-28 18:15:06,581 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-28 18:15:06,583 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-28 18:15:06,584 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-28 18:15:06,585 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-28 18:15:06,586 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-28 18:15:06,587 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-28 18:15:06,588 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-28 18:15:06,589 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-28 18:15:06,590 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-28 18:15:06,591 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-28 18:15:06,592 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-28 18:15:06,594 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-28 18:15:06,596 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-28 18:15:06,598 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-28 18:15:06,599 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-28 18:15:06,600 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-28 18:15:06,601 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-28 18:15:06,604 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-28 18:15:06,604 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-28 18:15:06,604 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-28 18:15:06,605 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-28 18:15:06,606 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-28 18:15:06,607 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-28 18:15:06,607 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-28 18:15:06,608 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-28 18:15:06,609 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-28 18:15:06,610 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-28 18:15:06,611 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-28 18:15:06,611 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-28 18:15:06,612 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-28 18:15:06,613 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-28 18:15:06,613 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-28 18:15:06,614 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-28 18:15:06,615 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-28 18:15:06,616 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-28 18:15:06,631 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-28 18:15:06,631 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-28 18:15:06,633 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-28 18:15:06,633 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-28 18:15:06,633 INFO L138 SettingsManager]: * Use SBE=true [2019-11-28 18:15:06,634 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-28 18:15:06,634 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-28 18:15:06,634 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-28 18:15:06,635 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-28 18:15:06,635 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-28 18:15:06,635 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-28 18:15:06,635 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-28 18:15:06,636 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-28 18:15:06,636 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-28 18:15:06,636 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-28 18:15:06,637 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-28 18:15:06,637 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-28 18:15:06,637 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-28 18:15:06,637 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-28 18:15:06,638 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-28 18:15:06,638 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-28 18:15:06,638 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 18:15:06,639 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-28 18:15:06,639 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-28 18:15:06,639 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-28 18:15:06,640 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-28 18:15:06,640 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-28 18:15:06,640 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-28 18:15:06,641 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-11-28 18:15:06,641 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e635a02f2d7438928806d3267842b22f0deee00c [2019-11-28 18:15:06,941 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-28 18:15:06,957 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-28 18:15:06,960 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-28 18:15:06,962 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-28 18:15:06,963 INFO L275 PluginConnector]: CDTParser initialized [2019-11-28 18:15:06,963 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/pthread-wmm/mix042_pso.opt.i [2019-11-28 18:15:07,025 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/83f147d69/b3563f1c5e0b4cfcaf1b1450a1467eed/FLAG64d14ec12 [2019-11-28 18:15:07,602 INFO L306 CDTParser]: Found 1 translation units. [2019-11-28 18:15:07,603 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/pthread-wmm/mix042_pso.opt.i [2019-11-28 18:15:07,619 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/83f147d69/b3563f1c5e0b4cfcaf1b1450a1467eed/FLAG64d14ec12 [2019-11-28 18:15:07,863 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/83f147d69/b3563f1c5e0b4cfcaf1b1450a1467eed [2019-11-28 18:15:07,867 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-28 18:15:07,868 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-28 18:15:07,870 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-28 18:15:07,870 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-28 18:15:07,874 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-28 18:15:07,875 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 06:15:07" (1/1) ... [2019-11-28 18:15:07,878 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@332255e6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:15:07, skipping insertion in model container [2019-11-28 18:15:07,878 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 06:15:07" (1/1) ... [2019-11-28 18:15:07,886 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-11-28 18:15:07,950 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-11-28 18:15:08,446 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 18:15:08,459 INFO L203 MainTranslator]: Completed pre-run [2019-11-28 18:15:08,539 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 18:15:08,615 INFO L208 MainTranslator]: Completed translation [2019-11-28 18:15:08,616 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:15:08 WrapperNode [2019-11-28 18:15:08,616 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-28 18:15:08,617 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-28 18:15:08,617 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-28 18:15:08,617 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-28 18:15:08,626 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:15:08" (1/1) ... [2019-11-28 18:15:08,647 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:15:08" (1/1) ... [2019-11-28 18:15:08,690 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-28 18:15:08,690 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-28 18:15:08,691 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-28 18:15:08,691 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-28 18:15:08,701 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:15:08" (1/1) ... [2019-11-28 18:15:08,702 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:15:08" (1/1) ... [2019-11-28 18:15:08,707 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:15:08" (1/1) ... [2019-11-28 18:15:08,707 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:15:08" (1/1) ... [2019-11-28 18:15:08,720 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:15:08" (1/1) ... [2019-11-28 18:15:08,727 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:15:08" (1/1) ... [2019-11-28 18:15:08,735 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:15:08" (1/1) ... [2019-11-28 18:15:08,741 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-28 18:15:08,742 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-28 18:15:08,742 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-28 18:15:08,742 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-28 18:15:08,743 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:15:08" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 18:15:08,810 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-11-28 18:15:08,810 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-11-28 18:15:08,811 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-11-28 18:15:08,811 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-11-28 18:15:08,811 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-11-28 18:15:08,812 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-11-28 18:15:08,812 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-11-28 18:15:08,812 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-11-28 18:15:08,812 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-11-28 18:15:08,812 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-11-28 18:15:08,812 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-11-28 18:15:08,813 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-28 18:15:08,813 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-28 18:15:08,815 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-11-28 18:15:09,587 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-28 18:15:09,587 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-11-28 18:15:09,588 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:15:09 BoogieIcfgContainer [2019-11-28 18:15:09,589 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-28 18:15:09,590 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-28 18:15:09,590 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-28 18:15:09,594 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-28 18:15:09,594 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 06:15:07" (1/3) ... [2019-11-28 18:15:09,595 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@31e49b74 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 06:15:09, skipping insertion in model container [2019-11-28 18:15:09,596 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:15:08" (2/3) ... [2019-11-28 18:15:09,596 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@31e49b74 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 06:15:09, skipping insertion in model container [2019-11-28 18:15:09,596 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:15:09" (3/3) ... [2019-11-28 18:15:09,598 INFO L109 eAbstractionObserver]: Analyzing ICFG mix042_pso.opt.i [2019-11-28 18:15:09,609 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-11-28 18:15:09,610 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-28 18:15:09,619 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-11-28 18:15:09,620 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-11-28 18:15:09,662 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,662 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,663 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,663 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,664 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,664 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,665 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,665 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,665 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,666 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,666 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,666 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,666 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,667 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,667 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,667 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,668 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,668 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,668 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,669 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,669 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,669 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,670 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,670 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,671 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,671 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,671 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,672 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,672 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,672 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,672 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,673 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,673 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,673 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,674 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,674 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,675 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,675 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,675 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,676 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,676 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,676 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,676 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,677 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,677 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,678 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,678 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,678 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,678 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,679 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,679 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,679 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,680 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,680 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,680 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,680 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,681 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,681 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,681 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,681 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,682 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,682 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,682 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,683 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,683 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,683 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,683 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,684 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,684 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,684 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:15:09,705 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-11-28 18:15:09,722 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-28 18:15:09,722 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-28 18:15:09,722 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-28 18:15:09,722 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-28 18:15:09,722 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-28 18:15:09,723 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-28 18:15:09,723 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-28 18:15:09,723 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-28 18:15:09,741 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 165 places, 196 transitions [2019-11-28 18:15:09,743 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 165 places, 196 transitions [2019-11-28 18:15:09,830 INFO L134 PetriNetUnfolder]: 41/193 cut-off events. [2019-11-28 18:15:09,830 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-11-28 18:15:09,846 INFO L76 FinitePrefix]: Finished finitePrefix Result has 203 conditions, 193 events. 41/193 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 8. Compared 476 event pairs. 9/159 useless extension candidates. Maximal degree in co-relation 161. Up to 2 conditions per place. [2019-11-28 18:15:09,870 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 165 places, 196 transitions [2019-11-28 18:15:09,920 INFO L134 PetriNetUnfolder]: 41/193 cut-off events. [2019-11-28 18:15:09,920 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-11-28 18:15:09,929 INFO L76 FinitePrefix]: Finished finitePrefix Result has 203 conditions, 193 events. 41/193 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 8. Compared 476 event pairs. 9/159 useless extension candidates. Maximal degree in co-relation 161. Up to 2 conditions per place. [2019-11-28 18:15:09,948 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 11490 [2019-11-28 18:15:09,949 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-11-28 18:15:14,922 WARN L192 SmtUtils]: Spent 301.00 ms on a formula simplification. DAG size of input: 93 DAG size of output: 91 [2019-11-28 18:15:15,051 WARN L192 SmtUtils]: Spent 126.00 ms on a formula simplification that was a NOOP. DAG size: 89 [2019-11-28 18:15:15,071 INFO L206 etLargeBlockEncoding]: Checked pairs total: 50142 [2019-11-28 18:15:15,071 INFO L214 etLargeBlockEncoding]: Total number of compositions: 117 [2019-11-28 18:15:15,075 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 79 places, 86 transitions [2019-11-28 18:15:16,333 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 14254 states. [2019-11-28 18:15:16,336 INFO L276 IsEmpty]: Start isEmpty. Operand 14254 states. [2019-11-28 18:15:16,343 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2019-11-28 18:15:16,343 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:15:16,344 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:15:16,345 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:15:16,351 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:15:16,351 INFO L82 PathProgramCache]: Analyzing trace with hash -632784469, now seen corresponding path program 1 times [2019-11-28 18:15:16,361 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:15:16,362 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [811008642] [2019-11-28 18:15:16,362 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:15:16,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:15:16,660 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:15:16,661 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [811008642] [2019-11-28 18:15:16,662 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:15:16,662 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-11-28 18:15:16,663 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1152201110] [2019-11-28 18:15:16,668 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:15:16,668 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:15:16,679 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:15:16,680 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:15:16,681 INFO L87 Difference]: Start difference. First operand 14254 states. Second operand 3 states. [2019-11-28 18:15:17,018 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:15:17,018 INFO L93 Difference]: Finished difference Result 14182 states and 53160 transitions. [2019-11-28 18:15:17,019 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:15:17,020 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2019-11-28 18:15:17,021 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:15:17,197 INFO L225 Difference]: With dead ends: 14182 [2019-11-28 18:15:17,198 INFO L226 Difference]: Without dead ends: 13870 [2019-11-28 18:15:17,199 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:15:17,502 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13870 states. [2019-11-28 18:15:18,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13870 to 13870. [2019-11-28 18:15:18,089 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13870 states. [2019-11-28 18:15:18,176 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13870 states to 13870 states and 52042 transitions. [2019-11-28 18:15:18,177 INFO L78 Accepts]: Start accepts. Automaton has 13870 states and 52042 transitions. Word has length 7 [2019-11-28 18:15:18,178 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:15:18,178 INFO L462 AbstractCegarLoop]: Abstraction has 13870 states and 52042 transitions. [2019-11-28 18:15:18,179 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:15:18,179 INFO L276 IsEmpty]: Start isEmpty. Operand 13870 states and 52042 transitions. [2019-11-28 18:15:18,188 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-11-28 18:15:18,188 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:15:18,188 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:15:18,189 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:15:18,189 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:15:18,189 INFO L82 PathProgramCache]: Analyzing trace with hash -1056225825, now seen corresponding path program 1 times [2019-11-28 18:15:18,190 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:15:18,190 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [263566116] [2019-11-28 18:15:18,190 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:15:18,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:15:18,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:15:18,321 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [263566116] [2019-11-28 18:15:18,321 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:15:18,321 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:15:18,322 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [157743322] [2019-11-28 18:15:18,323 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:15:18,324 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:15:18,324 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:15:18,324 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:15:18,324 INFO L87 Difference]: Start difference. First operand 13870 states and 52042 transitions. Second operand 4 states. [2019-11-28 18:15:18,715 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:15:18,716 INFO L93 Difference]: Finished difference Result 19034 states and 69248 transitions. [2019-11-28 18:15:18,716 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:15:18,716 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-11-28 18:15:18,716 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:15:18,806 INFO L225 Difference]: With dead ends: 19034 [2019-11-28 18:15:18,806 INFO L226 Difference]: Without dead ends: 19034 [2019-11-28 18:15:18,807 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:15:18,952 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19034 states. [2019-11-28 18:15:19,427 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19034 to 18800. [2019-11-28 18:15:19,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18800 states. [2019-11-28 18:15:19,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18800 states to 18800 states and 68487 transitions. [2019-11-28 18:15:19,927 INFO L78 Accepts]: Start accepts. Automaton has 18800 states and 68487 transitions. Word has length 13 [2019-11-28 18:15:19,929 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:15:19,929 INFO L462 AbstractCegarLoop]: Abstraction has 18800 states and 68487 transitions. [2019-11-28 18:15:19,929 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:15:19,929 INFO L276 IsEmpty]: Start isEmpty. Operand 18800 states and 68487 transitions. [2019-11-28 18:15:19,933 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-11-28 18:15:19,933 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:15:19,933 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:15:19,934 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:15:19,934 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:15:19,935 INFO L82 PathProgramCache]: Analyzing trace with hash 746093816, now seen corresponding path program 1 times [2019-11-28 18:15:19,935 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:15:19,935 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [23099389] [2019-11-28 18:15:19,935 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:15:19,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:15:20,062 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:15:20,062 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [23099389] [2019-11-28 18:15:20,062 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:15:20,063 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:15:20,064 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [771559607] [2019-11-28 18:15:20,064 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:15:20,064 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:15:20,065 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:15:20,065 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:15:20,065 INFO L87 Difference]: Start difference. First operand 18800 states and 68487 transitions. Second operand 4 states. [2019-11-28 18:15:20,452 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:15:20,453 INFO L93 Difference]: Finished difference Result 27022 states and 96312 transitions. [2019-11-28 18:15:20,453 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:15:20,453 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-11-28 18:15:20,453 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:15:20,578 INFO L225 Difference]: With dead ends: 27022 [2019-11-28 18:15:20,578 INFO L226 Difference]: Without dead ends: 27008 [2019-11-28 18:15:20,579 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:15:20,754 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27008 states. [2019-11-28 18:15:21,247 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27008 to 22366. [2019-11-28 18:15:21,248 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22366 states. [2019-11-28 18:15:21,336 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22366 states to 22366 states and 80994 transitions. [2019-11-28 18:15:21,336 INFO L78 Accepts]: Start accepts. Automaton has 22366 states and 80994 transitions. Word has length 13 [2019-11-28 18:15:21,336 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:15:21,337 INFO L462 AbstractCegarLoop]: Abstraction has 22366 states and 80994 transitions. [2019-11-28 18:15:21,337 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:15:21,337 INFO L276 IsEmpty]: Start isEmpty. Operand 22366 states and 80994 transitions. [2019-11-28 18:15:21,343 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-11-28 18:15:21,344 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:15:21,344 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:15:21,345 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:15:21,345 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:15:21,345 INFO L82 PathProgramCache]: Analyzing trace with hash -1347005908, now seen corresponding path program 1 times [2019-11-28 18:15:21,345 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:15:21,346 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1761052259] [2019-11-28 18:15:21,346 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:15:21,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:15:21,442 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:15:21,443 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1761052259] [2019-11-28 18:15:21,443 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:15:21,443 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:15:21,443 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [176570548] [2019-11-28 18:15:21,444 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:15:21,444 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:15:21,444 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:15:21,444 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:15:21,445 INFO L87 Difference]: Start difference. First operand 22366 states and 80994 transitions. Second operand 5 states. [2019-11-28 18:15:22,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:15:22,345 INFO L93 Difference]: Finished difference Result 30132 states and 106959 transitions. [2019-11-28 18:15:22,345 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-11-28 18:15:22,345 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-11-28 18:15:22,345 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:15:22,450 INFO L225 Difference]: With dead ends: 30132 [2019-11-28 18:15:22,450 INFO L226 Difference]: Without dead ends: 30118 [2019-11-28 18:15:22,451 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-11-28 18:15:22,647 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30118 states. [2019-11-28 18:15:23,114 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30118 to 22270. [2019-11-28 18:15:23,115 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22270 states. [2019-11-28 18:15:23,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22270 states to 22270 states and 80486 transitions. [2019-11-28 18:15:23,191 INFO L78 Accepts]: Start accepts. Automaton has 22270 states and 80486 transitions. Word has length 19 [2019-11-28 18:15:23,192 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:15:23,192 INFO L462 AbstractCegarLoop]: Abstraction has 22270 states and 80486 transitions. [2019-11-28 18:15:23,192 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:15:23,192 INFO L276 IsEmpty]: Start isEmpty. Operand 22270 states and 80486 transitions. [2019-11-28 18:15:23,220 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-11-28 18:15:23,221 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:15:23,221 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:15:23,222 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:15:23,222 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:15:23,222 INFO L82 PathProgramCache]: Analyzing trace with hash 1614023153, now seen corresponding path program 1 times [2019-11-28 18:15:23,223 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:15:23,223 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [764932572] [2019-11-28 18:15:23,223 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:15:23,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:15:23,339 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:15:23,339 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [764932572] [2019-11-28 18:15:23,339 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:15:23,340 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:15:23,340 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1711869044] [2019-11-28 18:15:23,340 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:15:23,341 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:15:23,341 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:15:23,341 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:15:23,341 INFO L87 Difference]: Start difference. First operand 22270 states and 80486 transitions. Second operand 4 states. [2019-11-28 18:15:23,416 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:15:23,417 INFO L93 Difference]: Finished difference Result 13342 states and 41523 transitions. [2019-11-28 18:15:23,417 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-28 18:15:23,417 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 27 [2019-11-28 18:15:23,417 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:15:23,448 INFO L225 Difference]: With dead ends: 13342 [2019-11-28 18:15:23,449 INFO L226 Difference]: Without dead ends: 12812 [2019-11-28 18:15:23,449 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:15:23,548 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12812 states. [2019-11-28 18:15:24,202 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12812 to 12812. [2019-11-28 18:15:24,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12812 states. [2019-11-28 18:15:24,251 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12812 states to 12812 states and 40017 transitions. [2019-11-28 18:15:24,251 INFO L78 Accepts]: Start accepts. Automaton has 12812 states and 40017 transitions. Word has length 27 [2019-11-28 18:15:24,252 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:15:24,252 INFO L462 AbstractCegarLoop]: Abstraction has 12812 states and 40017 transitions. [2019-11-28 18:15:24,252 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:15:24,252 INFO L276 IsEmpty]: Start isEmpty. Operand 12812 states and 40017 transitions. [2019-11-28 18:15:24,266 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-11-28 18:15:24,266 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:15:24,267 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:15:24,267 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:15:24,267 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:15:24,268 INFO L82 PathProgramCache]: Analyzing trace with hash -1806206056, now seen corresponding path program 1 times [2019-11-28 18:15:24,268 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:15:24,269 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [146987665] [2019-11-28 18:15:24,269 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:15:24,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:15:24,373 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:15:24,374 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [146987665] [2019-11-28 18:15:24,374 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:15:24,374 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 18:15:24,374 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [417641232] [2019-11-28 18:15:24,375 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:15:24,375 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:15:24,375 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:15:24,375 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:15:24,376 INFO L87 Difference]: Start difference. First operand 12812 states and 40017 transitions. Second operand 5 states. [2019-11-28 18:15:24,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:15:24,429 INFO L93 Difference]: Finished difference Result 2336 states and 5507 transitions. [2019-11-28 18:15:24,429 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:15:24,429 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 28 [2019-11-28 18:15:24,430 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:15:24,434 INFO L225 Difference]: With dead ends: 2336 [2019-11-28 18:15:24,434 INFO L226 Difference]: Without dead ends: 2027 [2019-11-28 18:15:24,435 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-11-28 18:15:24,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2027 states. [2019-11-28 18:15:24,463 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2027 to 2027. [2019-11-28 18:15:24,464 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2027 states. [2019-11-28 18:15:24,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2027 states to 2027 states and 4646 transitions. [2019-11-28 18:15:24,468 INFO L78 Accepts]: Start accepts. Automaton has 2027 states and 4646 transitions. Word has length 28 [2019-11-28 18:15:24,469 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:15:24,469 INFO L462 AbstractCegarLoop]: Abstraction has 2027 states and 4646 transitions. [2019-11-28 18:15:24,469 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:15:24,469 INFO L276 IsEmpty]: Start isEmpty. Operand 2027 states and 4646 transitions. [2019-11-28 18:15:24,473 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2019-11-28 18:15:24,473 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:15:24,473 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:15:24,474 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:15:24,474 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:15:24,474 INFO L82 PathProgramCache]: Analyzing trace with hash -1654876811, now seen corresponding path program 1 times [2019-11-28 18:15:24,474 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:15:24,475 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1834163262] [2019-11-28 18:15:24,475 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:15:24,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:15:24,577 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:15:24,580 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1834163262] [2019-11-28 18:15:24,581 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:15:24,581 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 18:15:24,581 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1033290700] [2019-11-28 18:15:24,582 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-28 18:15:24,583 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:15:24,583 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-28 18:15:24,583 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2019-11-28 18:15:24,584 INFO L87 Difference]: Start difference. First operand 2027 states and 4646 transitions. Second operand 6 states. [2019-11-28 18:15:24,650 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:15:24,650 INFO L93 Difference]: Finished difference Result 690 states and 1578 transitions. [2019-11-28 18:15:24,651 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 18:15:24,651 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 40 [2019-11-28 18:15:24,651 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:15:24,652 INFO L225 Difference]: With dead ends: 690 [2019-11-28 18:15:24,652 INFO L226 Difference]: Without dead ends: 644 [2019-11-28 18:15:24,654 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2019-11-28 18:15:24,655 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 644 states. [2019-11-28 18:15:24,661 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 644 to 588. [2019-11-28 18:15:24,662 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 588 states. [2019-11-28 18:15:24,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 588 states to 588 states and 1356 transitions. [2019-11-28 18:15:24,666 INFO L78 Accepts]: Start accepts. Automaton has 588 states and 1356 transitions. Word has length 40 [2019-11-28 18:15:24,666 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:15:24,666 INFO L462 AbstractCegarLoop]: Abstraction has 588 states and 1356 transitions. [2019-11-28 18:15:24,667 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-28 18:15:24,667 INFO L276 IsEmpty]: Start isEmpty. Operand 588 states and 1356 transitions. [2019-11-28 18:15:24,670 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-11-28 18:15:24,671 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:15:24,671 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:15:24,671 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:15:24,671 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:15:24,672 INFO L82 PathProgramCache]: Analyzing trace with hash 149828223, now seen corresponding path program 1 times [2019-11-28 18:15:24,674 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:15:24,675 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1037898800] [2019-11-28 18:15:24,675 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:15:24,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:15:24,764 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:15:24,764 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1037898800] [2019-11-28 18:15:24,764 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:15:24,764 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:15:24,765 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1465774441] [2019-11-28 18:15:24,765 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:15:24,765 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:15:24,765 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:15:24,766 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:15:24,766 INFO L87 Difference]: Start difference. First operand 588 states and 1356 transitions. Second operand 3 states. [2019-11-28 18:15:24,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:15:24,807 INFO L93 Difference]: Finished difference Result 602 states and 1375 transitions. [2019-11-28 18:15:24,807 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:15:24,807 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 55 [2019-11-28 18:15:24,808 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:15:24,809 INFO L225 Difference]: With dead ends: 602 [2019-11-28 18:15:24,809 INFO L226 Difference]: Without dead ends: 602 [2019-11-28 18:15:24,809 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:15:24,813 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 602 states. [2019-11-28 18:15:24,817 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 602 to 596. [2019-11-28 18:15:24,817 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 596 states. [2019-11-28 18:15:24,818 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 596 states to 596 states and 1368 transitions. [2019-11-28 18:15:24,818 INFO L78 Accepts]: Start accepts. Automaton has 596 states and 1368 transitions. Word has length 55 [2019-11-28 18:15:24,819 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:15:24,819 INFO L462 AbstractCegarLoop]: Abstraction has 596 states and 1368 transitions. [2019-11-28 18:15:24,819 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:15:24,819 INFO L276 IsEmpty]: Start isEmpty. Operand 596 states and 1368 transitions. [2019-11-28 18:15:24,821 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-11-28 18:15:24,821 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:15:24,821 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:15:24,821 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:15:24,821 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:15:24,821 INFO L82 PathProgramCache]: Analyzing trace with hash 1719525699, now seen corresponding path program 1 times [2019-11-28 18:15:24,822 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:15:24,822 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [894822690] [2019-11-28 18:15:24,822 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:15:24,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:15:24,915 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:15:24,915 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [894822690] [2019-11-28 18:15:24,916 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:15:24,916 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 18:15:24,916 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [463040259] [2019-11-28 18:15:24,916 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:15:24,917 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:15:24,917 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:15:24,917 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:15:24,917 INFO L87 Difference]: Start difference. First operand 596 states and 1368 transitions. Second operand 5 states. [2019-11-28 18:15:25,124 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:15:25,124 INFO L93 Difference]: Finished difference Result 867 states and 1997 transitions. [2019-11-28 18:15:25,124 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 18:15:25,124 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 55 [2019-11-28 18:15:25,125 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:15:25,126 INFO L225 Difference]: With dead ends: 867 [2019-11-28 18:15:25,126 INFO L226 Difference]: Without dead ends: 867 [2019-11-28 18:15:25,126 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-11-28 18:15:25,129 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 867 states. [2019-11-28 18:15:25,138 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 867 to 789. [2019-11-28 18:15:25,138 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 789 states. [2019-11-28 18:15:25,140 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 789 states to 789 states and 1820 transitions. [2019-11-28 18:15:25,140 INFO L78 Accepts]: Start accepts. Automaton has 789 states and 1820 transitions. Word has length 55 [2019-11-28 18:15:25,140 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:15:25,140 INFO L462 AbstractCegarLoop]: Abstraction has 789 states and 1820 transitions. [2019-11-28 18:15:25,140 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:15:25,140 INFO L276 IsEmpty]: Start isEmpty. Operand 789 states and 1820 transitions. [2019-11-28 18:15:25,142 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-11-28 18:15:25,142 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:15:25,142 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:15:25,142 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:15:25,143 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:15:25,143 INFO L82 PathProgramCache]: Analyzing trace with hash 1740404695, now seen corresponding path program 2 times [2019-11-28 18:15:25,143 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:15:25,143 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [727599956] [2019-11-28 18:15:25,143 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:15:25,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:15:25,219 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:15:25,220 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [727599956] [2019-11-28 18:15:25,220 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:15:25,220 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:15:25,221 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1866405835] [2019-11-28 18:15:25,221 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:15:25,221 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:15:25,222 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:15:25,222 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:15:25,222 INFO L87 Difference]: Start difference. First operand 789 states and 1820 transitions. Second operand 3 states. [2019-11-28 18:15:25,262 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:15:25,262 INFO L93 Difference]: Finished difference Result 789 states and 1819 transitions. [2019-11-28 18:15:25,263 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:15:25,263 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 55 [2019-11-28 18:15:25,263 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:15:25,264 INFO L225 Difference]: With dead ends: 789 [2019-11-28 18:15:25,264 INFO L226 Difference]: Without dead ends: 789 [2019-11-28 18:15:25,265 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:15:25,267 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 789 states. [2019-11-28 18:15:25,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 789 to 632. [2019-11-28 18:15:25,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 632 states. [2019-11-28 18:15:25,276 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 632 states to 632 states and 1459 transitions. [2019-11-28 18:15:25,276 INFO L78 Accepts]: Start accepts. Automaton has 632 states and 1459 transitions. Word has length 55 [2019-11-28 18:15:25,278 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:15:25,278 INFO L462 AbstractCegarLoop]: Abstraction has 632 states and 1459 transitions. [2019-11-28 18:15:25,279 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:15:25,279 INFO L276 IsEmpty]: Start isEmpty. Operand 632 states and 1459 transitions. [2019-11-28 18:15:25,280 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-11-28 18:15:25,280 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:15:25,281 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:15:25,281 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:15:25,281 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:15:25,281 INFO L82 PathProgramCache]: Analyzing trace with hash 1993080434, now seen corresponding path program 1 times [2019-11-28 18:15:25,282 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:15:25,282 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [399977760] [2019-11-28 18:15:25,283 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:15:25,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:15:25,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:15:25,390 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [399977760] [2019-11-28 18:15:25,390 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:15:25,390 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:15:25,390 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1165233968] [2019-11-28 18:15:25,391 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:15:25,392 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:15:25,392 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:15:25,393 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:15:25,393 INFO L87 Difference]: Start difference. First operand 632 states and 1459 transitions. Second operand 3 states. [2019-11-28 18:15:25,406 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:15:25,407 INFO L93 Difference]: Finished difference Result 632 states and 1429 transitions. [2019-11-28 18:15:25,408 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:15:25,408 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 56 [2019-11-28 18:15:25,408 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:15:25,409 INFO L225 Difference]: With dead ends: 632 [2019-11-28 18:15:25,409 INFO L226 Difference]: Without dead ends: 632 [2019-11-28 18:15:25,410 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:15:25,411 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 632 states. [2019-11-28 18:15:25,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 632 to 596. [2019-11-28 18:15:25,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 596 states. [2019-11-28 18:15:25,418 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 596 states to 596 states and 1343 transitions. [2019-11-28 18:15:25,419 INFO L78 Accepts]: Start accepts. Automaton has 596 states and 1343 transitions. Word has length 56 [2019-11-28 18:15:25,419 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:15:25,419 INFO L462 AbstractCegarLoop]: Abstraction has 596 states and 1343 transitions. [2019-11-28 18:15:25,419 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:15:25,419 INFO L276 IsEmpty]: Start isEmpty. Operand 596 states and 1343 transitions. [2019-11-28 18:15:25,421 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:15:25,421 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:15:25,421 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:15:25,421 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:15:25,422 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:15:25,422 INFO L82 PathProgramCache]: Analyzing trace with hash 2052620165, now seen corresponding path program 1 times [2019-11-28 18:15:25,422 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:15:25,422 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1068841812] [2019-11-28 18:15:25,423 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:15:25,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:15:25,791 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:15:25,792 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1068841812] [2019-11-28 18:15:25,792 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:15:25,792 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-11-28 18:15:25,793 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [840704483] [2019-11-28 18:15:25,793 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-11-28 18:15:25,794 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:15:25,794 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-11-28 18:15:25,794 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=96, Unknown=0, NotChecked=0, Total=132 [2019-11-28 18:15:25,795 INFO L87 Difference]: Start difference. First operand 596 states and 1343 transitions. Second operand 12 states. [2019-11-28 18:15:26,433 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:15:26,433 INFO L93 Difference]: Finished difference Result 1200 states and 2407 transitions. [2019-11-28 18:15:26,434 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-11-28 18:15:26,434 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 57 [2019-11-28 18:15:26,434 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:15:26,436 INFO L225 Difference]: With dead ends: 1200 [2019-11-28 18:15:26,436 INFO L226 Difference]: Without dead ends: 600 [2019-11-28 18:15:26,436 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 94 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=173, Invalid=427, Unknown=0, NotChecked=0, Total=600 [2019-11-28 18:15:26,438 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 600 states. [2019-11-28 18:15:26,441 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 600 to 534. [2019-11-28 18:15:26,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 534 states. [2019-11-28 18:15:26,442 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 534 states to 534 states and 1164 transitions. [2019-11-28 18:15:26,442 INFO L78 Accepts]: Start accepts. Automaton has 534 states and 1164 transitions. Word has length 57 [2019-11-28 18:15:26,443 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:15:26,443 INFO L462 AbstractCegarLoop]: Abstraction has 534 states and 1164 transitions. [2019-11-28 18:15:26,443 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-11-28 18:15:26,443 INFO L276 IsEmpty]: Start isEmpty. Operand 534 states and 1164 transitions. [2019-11-28 18:15:26,444 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:15:26,444 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:15:26,444 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:15:26,444 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:15:26,444 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:15:26,444 INFO L82 PathProgramCache]: Analyzing trace with hash -892812541, now seen corresponding path program 2 times [2019-11-28 18:15:26,444 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:15:26,445 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [532043859] [2019-11-28 18:15:26,445 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:15:26,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:15:26,988 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:15:26,988 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [532043859] [2019-11-28 18:15:26,989 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:15:26,989 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [16] imperfect sequences [] total 16 [2019-11-28 18:15:26,989 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1789403160] [2019-11-28 18:15:26,990 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-11-28 18:15:26,990 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:15:26,990 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-11-28 18:15:26,991 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=47, Invalid=259, Unknown=0, NotChecked=0, Total=306 [2019-11-28 18:15:26,991 INFO L87 Difference]: Start difference. First operand 534 states and 1164 transitions. Second operand 18 states. [2019-11-28 18:15:28,402 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:15:28,402 INFO L93 Difference]: Finished difference Result 1295 states and 2888 transitions. [2019-11-28 18:15:28,402 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-11-28 18:15:28,402 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 57 [2019-11-28 18:15:28,403 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:15:28,405 INFO L225 Difference]: With dead ends: 1295 [2019-11-28 18:15:28,405 INFO L226 Difference]: Without dead ends: 1265 [2019-11-28 18:15:28,406 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 1 SyntacticMatches, 4 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 235 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=209, Invalid=1051, Unknown=0, NotChecked=0, Total=1260 [2019-11-28 18:15:28,408 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1265 states. [2019-11-28 18:15:28,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1265 to 716. [2019-11-28 18:15:28,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 716 states. [2019-11-28 18:15:28,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 716 states to 716 states and 1564 transitions. [2019-11-28 18:15:28,419 INFO L78 Accepts]: Start accepts. Automaton has 716 states and 1564 transitions. Word has length 57 [2019-11-28 18:15:28,419 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:15:28,420 INFO L462 AbstractCegarLoop]: Abstraction has 716 states and 1564 transitions. [2019-11-28 18:15:28,420 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-11-28 18:15:28,420 INFO L276 IsEmpty]: Start isEmpty. Operand 716 states and 1564 transitions. [2019-11-28 18:15:28,421 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:15:28,422 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:15:28,422 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:15:28,422 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:15:28,422 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:15:28,423 INFO L82 PathProgramCache]: Analyzing trace with hash -495942269, now seen corresponding path program 3 times [2019-11-28 18:15:28,423 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:15:28,423 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [356240305] [2019-11-28 18:15:28,423 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:15:28,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:15:28,944 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:15:28,945 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [356240305] [2019-11-28 18:15:28,945 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:15:28,945 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2019-11-28 18:15:28,945 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1017520424] [2019-11-28 18:15:28,946 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2019-11-28 18:15:28,946 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:15:28,946 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2019-11-28 18:15:28,946 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=63, Invalid=279, Unknown=0, NotChecked=0, Total=342 [2019-11-28 18:15:28,947 INFO L87 Difference]: Start difference. First operand 716 states and 1564 transitions. Second operand 19 states. [2019-11-28 18:15:30,606 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:15:30,606 INFO L93 Difference]: Finished difference Result 1445 states and 3171 transitions. [2019-11-28 18:15:30,607 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2019-11-28 18:15:30,607 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 57 [2019-11-28 18:15:30,607 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:15:30,609 INFO L225 Difference]: With dead ends: 1445 [2019-11-28 18:15:30,609 INFO L226 Difference]: Without dead ends: 1415 [2019-11-28 18:15:30,610 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 269 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=238, Invalid=1094, Unknown=0, NotChecked=0, Total=1332 [2019-11-28 18:15:30,612 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1415 states. [2019-11-28 18:15:30,618 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1415 to 752. [2019-11-28 18:15:30,619 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 752 states. [2019-11-28 18:15:30,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 752 states to 752 states and 1652 transitions. [2019-11-28 18:15:30,620 INFO L78 Accepts]: Start accepts. Automaton has 752 states and 1652 transitions. Word has length 57 [2019-11-28 18:15:30,620 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:15:30,620 INFO L462 AbstractCegarLoop]: Abstraction has 752 states and 1652 transitions. [2019-11-28 18:15:30,620 INFO L463 AbstractCegarLoop]: Interpolant automaton has 19 states. [2019-11-28 18:15:30,621 INFO L276 IsEmpty]: Start isEmpty. Operand 752 states and 1652 transitions. [2019-11-28 18:15:30,622 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:15:30,622 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:15:30,623 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:15:30,623 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:15:30,623 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:15:30,623 INFO L82 PathProgramCache]: Analyzing trace with hash 1918154831, now seen corresponding path program 4 times [2019-11-28 18:15:30,624 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:15:30,624 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [425230213] [2019-11-28 18:15:30,624 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:15:30,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:15:30,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:15:30,921 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [425230213] [2019-11-28 18:15:30,921 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:15:30,921 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-11-28 18:15:30,922 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [641616419] [2019-11-28 18:15:30,922 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-11-28 18:15:30,922 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:15:30,923 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-11-28 18:15:30,923 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=149, Unknown=0, NotChecked=0, Total=182 [2019-11-28 18:15:30,923 INFO L87 Difference]: Start difference. First operand 752 states and 1652 transitions. Second operand 14 states. [2019-11-28 18:15:31,640 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:15:31,640 INFO L93 Difference]: Finished difference Result 1198 states and 2625 transitions. [2019-11-28 18:15:31,641 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-11-28 18:15:31,641 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 57 [2019-11-28 18:15:31,641 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:15:31,643 INFO L225 Difference]: With dead ends: 1198 [2019-11-28 18:15:31,643 INFO L226 Difference]: Without dead ends: 1168 [2019-11-28 18:15:31,644 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 96 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=130, Invalid=520, Unknown=0, NotChecked=0, Total=650 [2019-11-28 18:15:31,646 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1168 states. [2019-11-28 18:15:31,654 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1168 to 776. [2019-11-28 18:15:31,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 776 states. [2019-11-28 18:15:31,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1710 transitions. [2019-11-28 18:15:31,656 INFO L78 Accepts]: Start accepts. Automaton has 776 states and 1710 transitions. Word has length 57 [2019-11-28 18:15:31,657 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:15:31,657 INFO L462 AbstractCegarLoop]: Abstraction has 776 states and 1710 transitions. [2019-11-28 18:15:31,657 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-11-28 18:15:31,657 INFO L276 IsEmpty]: Start isEmpty. Operand 776 states and 1710 transitions. [2019-11-28 18:15:31,662 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:15:31,662 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:15:31,662 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:15:31,663 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:15:31,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:15:31,663 INFO L82 PathProgramCache]: Analyzing trace with hash 60491955, now seen corresponding path program 5 times [2019-11-28 18:15:31,663 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:15:31,663 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1158281501] [2019-11-28 18:15:31,663 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:15:31,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:15:31,988 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:15:31,989 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1158281501] [2019-11-28 18:15:31,989 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:15:31,989 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-11-28 18:15:31,990 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [545161832] [2019-11-28 18:15:31,990 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-11-28 18:15:31,990 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:15:31,991 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-11-28 18:15:31,991 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=174, Unknown=0, NotChecked=0, Total=210 [2019-11-28 18:15:31,991 INFO L87 Difference]: Start difference. First operand 776 states and 1710 transitions. Second operand 15 states. [2019-11-28 18:15:32,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:15:32,731 INFO L93 Difference]: Finished difference Result 1150 states and 2505 transitions. [2019-11-28 18:15:32,731 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2019-11-28 18:15:32,732 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 57 [2019-11-28 18:15:32,732 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:15:32,733 INFO L225 Difference]: With dead ends: 1150 [2019-11-28 18:15:32,734 INFO L226 Difference]: Without dead ends: 1120 [2019-11-28 18:15:32,734 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 120 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=144, Invalid=612, Unknown=0, NotChecked=0, Total=756 [2019-11-28 18:15:32,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1120 states. [2019-11-28 18:15:32,742 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1120 to 772. [2019-11-28 18:15:32,743 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 772 states. [2019-11-28 18:15:32,744 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 772 states to 772 states and 1700 transitions. [2019-11-28 18:15:32,744 INFO L78 Accepts]: Start accepts. Automaton has 772 states and 1700 transitions. Word has length 57 [2019-11-28 18:15:32,744 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:15:32,745 INFO L462 AbstractCegarLoop]: Abstraction has 772 states and 1700 transitions. [2019-11-28 18:15:32,745 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-11-28 18:15:32,745 INFO L276 IsEmpty]: Start isEmpty. Operand 772 states and 1700 transitions. [2019-11-28 18:15:32,746 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:15:32,746 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:15:32,746 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:15:32,747 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:15:32,747 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:15:32,747 INFO L82 PathProgramCache]: Analyzing trace with hash 729108355, now seen corresponding path program 6 times [2019-11-28 18:15:32,747 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:15:32,748 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1922423279] [2019-11-28 18:15:32,748 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:15:32,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 18:15:32,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 18:15:32,892 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-28 18:15:32,892 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-28 18:15:32,897 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [756] [756] ULTIMATE.startENTRY-->L812: Formula: (let ((.cse0 (store |v_#valid_56| 0 0))) (and (= v_~y$w_buff0_used~0_565 0) (= v_~y$w_buff1_used~0_304 0) (< |v_#StackHeapBarrier_14| |v_ULTIMATE.start_main_~#t1114~0.base_27|) (= v_~main$tmp_guard0~0_30 0) (= v_~y$r_buff0_thd0~0_292 0) (= 0 v_~weak$$choice2~0_82) (= 0 v_~y$read_delayed_var~0.offset_8) (= (select .cse0 |v_ULTIMATE.start_main_~#t1114~0.base_27|) 0) (= 0 v_~__unbuffered_cnt~0_94) (= 0 v_~y$r_buff1_thd3~0_89) (= v_~y$read_delayed~0_8 0) (= 0 v_~y$r_buff1_thd2~0_113) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1114~0.base_27| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1114~0.base_27|) |v_ULTIMATE.start_main_~#t1114~0.offset_21| 0)) |v_#memory_int_15|) (= v_~main$tmp_guard1~0_30 0) (= v_~x~0_51 0) (= v_~y$w_buff1~0_136 0) (= |v_#length_19| (store |v_#length_20| |v_ULTIMATE.start_main_~#t1114~0.base_27| 4)) (= 0 v_~y$r_buff0_thd2~0_108) (< 0 |v_#StackHeapBarrier_14|) (= v_~y$r_buff0_thd1~0_41 0) (= 0 |v_ULTIMATE.start_main_~#t1114~0.offset_21|) (= v_~a~0_57 0) (= v_~y$mem_tmp~0_17 0) (= v_~z~0_41 0) (= 0 v_~y$r_buff1_thd1~0_40) (= v_~__unbuffered_p2_EBX~0_54 0) (= |v_#valid_54| (store .cse0 |v_ULTIMATE.start_main_~#t1114~0.base_27| 1)) (= v_~y~0_123 0) (= v_~y$r_buff1_thd0~0_196 0) (= |v_#NULL.offset_5| 0) (= 0 v_~y$r_buff0_thd3~0_130) (= 0 v_~y$read_delayed_var~0.base_8) (= 0 v_~__unbuffered_p2_EAX~0_54) (= 0 v_~__unbuffered_p0_EAX~0_39) (= 0 v_~weak$$choice0~0_13) (= 0 |v_#NULL.base_5|) (= 0 v_~y$flush_delayed~0_34) (= 0 v_~y$w_buff0~0_162))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_56|, #memory_int=|v_#memory_int_16|, #length=|v_#length_20|} OutVars{ULTIMATE.start_main_~#t1114~0.offset=|v_ULTIMATE.start_main_~#t1114~0.offset_21|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_28|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_35|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_29|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_51|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_35|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_50|, ~y$read_delayed~0=v_~y$read_delayed~0_8, ~a~0=v_~a~0_57, ~y$mem_tmp~0=v_~y$mem_tmp~0_17, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_39, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_89, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_41, ~y$flush_delayed~0=v_~y$flush_delayed~0_34, #length=|v_#length_19|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_54, ULTIMATE.start_main_~#t1115~0.base=|v_ULTIMATE.start_main_~#t1115~0.base_26|, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_54, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_29|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_30|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_17|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_116|, ULTIMATE.start_main_~#t1116~0.offset=|v_ULTIMATE.start_main_~#t1116~0.offset_16|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_33|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_32|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_25|, ~weak$$choice0~0=v_~weak$$choice0~0_13, #StackHeapBarrier=|v_#StackHeapBarrier_14|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_26|, ~y$w_buff1~0=v_~y$w_buff1~0_136, ULTIMATE.start_main_~#t1116~0.base=|v_ULTIMATE.start_main_~#t1116~0.base_21|, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_8, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_108, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_10|, ULTIMATE.start_main_~#t1115~0.offset=|v_ULTIMATE.start_main_~#t1115~0.offset_20|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_20|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_94, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_196, ~x~0=v_~x~0_51, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_8, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_565, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_34|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_36|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_30, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_49|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_31|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_27|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_27|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_42|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_40, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_28|, ~y$w_buff0~0=v_~y$w_buff0~0_162, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_130, ~y~0=v_~y~0_123, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_32|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_17|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_196|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_28|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_30, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_34|, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_110|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_113, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_26|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_21|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_292, #valid=|v_#valid_54|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_~#t1114~0.base=|v_ULTIMATE.start_main_~#t1114~0.base_27|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_10|, ~z~0=v_~z~0_41, ~weak$$choice2~0=v_~weak$$choice2~0_82, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_304} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1114~0.offset, ULTIMATE.start_main_#t~ite28, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~y$read_delayed~0, ~a~0, ~y$mem_tmp~0, ~__unbuffered_p0_EAX~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_~#t1115~0.base, ~__unbuffered_p2_EBX~0, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_~#t1116~0.offset, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ULTIMATE.start_main_~#t1116~0.base, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_~#t1115~0.offset, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_~#t1114~0.base, ULTIMATE.start_main_#t~nondet16, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:15:32,898 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [704] [704] L812-1-->L814: Formula: (and (= |v_#length_13| (store |v_#length_14| |v_ULTIMATE.start_main_~#t1115~0.base_9| 4)) (< |v_#StackHeapBarrier_9| |v_ULTIMATE.start_main_~#t1115~0.base_9|) (= |v_ULTIMATE.start_main_~#t1115~0.offset_8| 0) (= (select |v_#valid_28| |v_ULTIMATE.start_main_~#t1115~0.base_9|) 0) (= |v_#valid_27| (store |v_#valid_28| |v_ULTIMATE.start_main_~#t1115~0.base_9| 1)) (not (= |v_ULTIMATE.start_main_~#t1115~0.base_9| 0)) (= |v_#memory_int_9| (store |v_#memory_int_10| |v_ULTIMATE.start_main_~#t1115~0.base_9| (store (select |v_#memory_int_10| |v_ULTIMATE.start_main_~#t1115~0.base_9|) |v_ULTIMATE.start_main_~#t1115~0.offset_8| 1)))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_28|, #memory_int=|v_#memory_int_10|, #length=|v_#length_14|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_27|, #memory_int=|v_#memory_int_9|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_4|, ULTIMATE.start_main_~#t1115~0.offset=|v_ULTIMATE.start_main_~#t1115~0.offset_8|, #length=|v_#length_13|, ULTIMATE.start_main_~#t1115~0.base=|v_ULTIMATE.start_main_~#t1115~0.base_9|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_~#t1115~0.offset, #length, ULTIMATE.start_main_~#t1115~0.base] because there is no mapped edge [2019-11-28 18:15:32,899 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [712] [712] L814-1-->L816: Formula: (and (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t1116~0.base_10|) (= 0 (select |v_#valid_30| |v_ULTIMATE.start_main_~#t1116~0.base_10|)) (= |v_ULTIMATE.start_main_~#t1116~0.offset_10| 0) (= |v_#valid_29| (store |v_#valid_30| |v_ULTIMATE.start_main_~#t1116~0.base_10| 1)) (= (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t1116~0.base_10| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t1116~0.base_10|) |v_ULTIMATE.start_main_~#t1116~0.offset_10| 2)) |v_#memory_int_11|) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t1116~0.base_10| 4)) (not (= 0 |v_ULTIMATE.start_main_~#t1116~0.base_10|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_30|, #memory_int=|v_#memory_int_12|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_10|, ULTIMATE.start_main_~#t1116~0.base=|v_ULTIMATE.start_main_~#t1116~0.base_10|, #valid=|v_#valid_29|, #memory_int=|v_#memory_int_11|, ULTIMATE.start_main_~#t1116~0.offset=|v_ULTIMATE.start_main_~#t1116~0.offset_10|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, #length=|v_#length_15|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1116~0.base, #valid, #memory_int, ULTIMATE.start_main_~#t1116~0.offset, ULTIMATE.start_main_#t~nondet16, #length] because there is no mapped edge [2019-11-28 18:15:32,901 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [740] [740] L4-->L789: Formula: (and (not (= P2Thread1of1ForFork1___VERIFIER_assert_~expression_In-1787557029 0)) (= ~z~0_Out-1787557029 ~__unbuffered_p2_EAX~0_Out-1787557029) (= ~y$r_buff0_thd3~0_Out-1787557029 1) (= ~y$r_buff1_thd0~0_Out-1787557029 ~y$r_buff0_thd0~0_In-1787557029) (= ~y$r_buff0_thd3~0_In-1787557029 ~y$r_buff1_thd3~0_Out-1787557029) (= ~a~0_In-1787557029 ~__unbuffered_p2_EBX~0_Out-1787557029) (= ~y$r_buff0_thd1~0_In-1787557029 ~y$r_buff1_thd1~0_Out-1787557029) (= ~z~0_Out-1787557029 1) (= ~y$r_buff1_thd2~0_Out-1787557029 ~y$r_buff0_thd2~0_In-1787557029)) InVars {~a~0=~a~0_In-1787557029, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1787557029, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1787557029, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1787557029, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In-1787557029, P2Thread1of1ForFork1___VERIFIER_assert_~expression=P2Thread1of1ForFork1___VERIFIER_assert_~expression_In-1787557029} OutVars{~__unbuffered_p2_EBX~0=~__unbuffered_p2_EBX~0_Out-1787557029, P2Thread1of1ForFork1___VERIFIER_assert_~expression=P2Thread1of1ForFork1___VERIFIER_assert_~expression_In-1787557029, ~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_Out-1787557029, ~a~0=~a~0_In-1787557029, ~y$r_buff1_thd1~0=~y$r_buff1_thd1~0_Out-1787557029, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_Out-1787557029, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out-1787557029, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1787557029, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1787557029, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In-1787557029, ~__unbuffered_p2_EAX~0=~__unbuffered_p2_EAX~0_Out-1787557029, ~z~0=~z~0_Out-1787557029, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_Out-1787557029} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, ~y$r_buff1_thd1~0, ~__unbuffered_p2_EBX~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd3~0, ~__unbuffered_p2_EAX~0, ~z~0, ~y$r_buff1_thd0~0] because there is no mapped edge [2019-11-28 18:15:32,901 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [711] [711] P0ENTRY-->P0EXIT: Formula: (and (= v_P0Thread1of1ForFork2_~arg.base_8 |v_P0Thread1of1ForFork2_#in~arg.base_10|) (= v_~a~0_22 1) (= v_~x~0_29 v_~__unbuffered_p0_EAX~0_17) (= (+ v_~__unbuffered_cnt~0_41 1) v_~__unbuffered_cnt~0_40) (= v_P0Thread1of1ForFork2_~arg.offset_8 |v_P0Thread1of1ForFork2_#in~arg.offset_10|) (= |v_P0Thread1of1ForFork2_#res.offset_3| 0) (= 0 |v_P0Thread1of1ForFork2_#res.base_3|)) InVars {P0Thread1of1ForFork2_#in~arg.offset=|v_P0Thread1of1ForFork2_#in~arg.offset_10|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_41, P0Thread1of1ForFork2_#in~arg.base=|v_P0Thread1of1ForFork2_#in~arg.base_10|, ~x~0=v_~x~0_29} OutVars{~a~0=v_~a~0_22, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_17, P0Thread1of1ForFork2_#in~arg.offset=|v_P0Thread1of1ForFork2_#in~arg.offset_10|, P0Thread1of1ForFork2_~arg.offset=v_P0Thread1of1ForFork2_~arg.offset_8, P0Thread1of1ForFork2_#res.offset=|v_P0Thread1of1ForFork2_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_40, P0Thread1of1ForFork2_#in~arg.base=|v_P0Thread1of1ForFork2_#in~arg.base_10|, P0Thread1of1ForFork2_#res.base=|v_P0Thread1of1ForFork2_#res.base_3|, ~x~0=v_~x~0_29, P0Thread1of1ForFork2_~arg.base=v_P0Thread1of1ForFork2_~arg.base_8} AuxVars[] AssignedVars[~a~0, ~__unbuffered_p0_EAX~0, P0Thread1of1ForFork2_~arg.offset, P0Thread1of1ForFork2_#res.offset, ~__unbuffered_cnt~0, P0Thread1of1ForFork2_#res.base, P0Thread1of1ForFork2_~arg.base] because there is no mapped edge [2019-11-28 18:15:32,903 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [682] [682] L754-2-->L754-5: Formula: (let ((.cse0 (= (mod ~y$w_buff1_used~0_In113155889 256) 0)) (.cse2 (= (mod ~y$r_buff1_thd2~0_In113155889 256) 0)) (.cse1 (= |P1Thread1of1ForFork0_#t~ite4_Out113155889| |P1Thread1of1ForFork0_#t~ite3_Out113155889|))) (or (and (= ~y$w_buff1~0_In113155889 |P1Thread1of1ForFork0_#t~ite3_Out113155889|) (not .cse0) .cse1 (not .cse2)) (and (or .cse0 .cse2) (= ~y~0_In113155889 |P1Thread1of1ForFork0_#t~ite3_Out113155889|) .cse1))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In113155889, ~y$w_buff1~0=~y$w_buff1~0_In113155889, ~y~0=~y~0_In113155889, ~y$w_buff1_used~0=~y$w_buff1_used~0_In113155889} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In113155889, ~y$w_buff1~0=~y$w_buff1~0_In113155889, P1Thread1of1ForFork0_#t~ite3=|P1Thread1of1ForFork0_#t~ite3_Out113155889|, ~y~0=~y~0_In113155889, P1Thread1of1ForFork0_#t~ite4=|P1Thread1of1ForFork0_#t~ite4_Out113155889|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In113155889} AuxVars[] AssignedVars[P1Thread1of1ForFork0_#t~ite3, P1Thread1of1ForFork0_#t~ite4] because there is no mapped edge [2019-11-28 18:15:32,904 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L790-->L790-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In-2059670464 256))) (.cse1 (= (mod ~y$r_buff0_thd3~0_In-2059670464 256) 0))) (or (and (not .cse0) (= 0 |P2Thread1of1ForFork1_#t~ite11_Out-2059670464|) (not .cse1)) (and (= |P2Thread1of1ForFork1_#t~ite11_Out-2059670464| ~y$w_buff0_used~0_In-2059670464) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-2059670464, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-2059670464} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-2059670464, P2Thread1of1ForFork1_#t~ite11=|P2Thread1of1ForFork1_#t~ite11_Out-2059670464|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-2059670464} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-11-28 18:15:32,904 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [686] [686] L791-->L791-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In-2094201678 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In-2094201678 256) 0)) (.cse3 (= 0 (mod ~y$r_buff1_thd3~0_In-2094201678 256))) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In-2094201678 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork1_#t~ite12_Out-2094201678| 0)) (and (= |P2Thread1of1ForFork1_#t~ite12_Out-2094201678| ~y$w_buff1_used~0_In-2094201678) (or .cse0 .cse1) (or .cse3 .cse2)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-2094201678, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2094201678, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-2094201678, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2094201678} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-2094201678, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2094201678, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-2094201678, P2Thread1of1ForFork1_#t~ite12=|P2Thread1of1ForFork1_#t~ite12_Out-2094201678|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2094201678} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-11-28 18:15:32,905 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [689] [689] L792-->L793: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd3~0_In1441516150 256) 0)) (.cse0 (= (mod ~y$w_buff0_used~0_In1441516150 256) 0)) (.cse2 (= ~y$r_buff0_thd3~0_Out1441516150 ~y$r_buff0_thd3~0_In1441516150))) (or (and (= 0 ~y$r_buff0_thd3~0_Out1441516150) (not .cse0) (not .cse1)) (and .cse2 .cse1) (and .cse0 .cse2))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1441516150, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1441516150} OutVars{P2Thread1of1ForFork1_#t~ite13=|P2Thread1of1ForFork1_#t~ite13_Out1441516150|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1441516150, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out1441516150} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite13, ~y$r_buff0_thd3~0] because there is no mapped edge [2019-11-28 18:15:32,905 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [699] [699] L793-->L793-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In741858247 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In741858247 256))) (.cse2 (= (mod ~y$w_buff1_used~0_In741858247 256) 0)) (.cse3 (= 0 (mod ~y$r_buff1_thd3~0_In741858247 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork1_#t~ite14_Out741858247|)) (and (or .cse0 .cse1) (= |P2Thread1of1ForFork1_#t~ite14_Out741858247| ~y$r_buff1_thd3~0_In741858247) (or .cse2 .cse3)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In741858247, ~y$w_buff0_used~0=~y$w_buff0_used~0_In741858247, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In741858247, ~y$w_buff1_used~0=~y$w_buff1_used~0_In741858247} OutVars{P2Thread1of1ForFork1_#t~ite14=|P2Thread1of1ForFork1_#t~ite14_Out741858247|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In741858247, ~y$w_buff0_used~0=~y$w_buff0_used~0_In741858247, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In741858247, ~y$w_buff1_used~0=~y$w_buff1_used~0_In741858247} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-11-28 18:15:32,905 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [717] [717] L793-2-->P2EXIT: Formula: (and (= 0 |v_P2Thread1of1ForFork1_#res.offset_3|) (= (+ v_~__unbuffered_cnt~0_59 1) v_~__unbuffered_cnt~0_58) (= |v_P2Thread1of1ForFork1_#t~ite14_34| v_~y$r_buff1_thd3~0_55) (= 0 |v_P2Thread1of1ForFork1_#res.base_3|)) InVars {P2Thread1of1ForFork1_#t~ite14=|v_P2Thread1of1ForFork1_#t~ite14_34|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_59} OutVars{P2Thread1of1ForFork1_#t~ite14=|v_P2Thread1of1ForFork1_#t~ite14_33|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_55, P2Thread1of1ForFork1_#res.base=|v_P2Thread1of1ForFork1_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_58, P2Thread1of1ForFork1_#res.offset=|v_P2Thread1of1ForFork1_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork1_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork1_#res.offset] because there is no mapped edge [2019-11-28 18:15:32,906 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [687] [687] L755-->L755-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In1328626474 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In1328626474 256)))) (or (and (= |P1Thread1of1ForFork0_#t~ite5_Out1328626474| ~y$w_buff0_used~0_In1328626474) (or .cse0 .cse1)) (and (not .cse1) (= |P1Thread1of1ForFork0_#t~ite5_Out1328626474| 0) (not .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1328626474, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1328626474} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1328626474, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1328626474, P1Thread1of1ForFork0_#t~ite5=|P1Thread1of1ForFork0_#t~ite5_Out1328626474|} AuxVars[] AssignedVars[P1Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-11-28 18:15:32,906 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [680] [680] L756-->L756-2: Formula: (let ((.cse0 (= (mod ~y$w_buff1_used~0_In988825553 256) 0)) (.cse1 (= (mod ~y$r_buff1_thd2~0_In988825553 256) 0)) (.cse3 (= (mod ~y$w_buff0_used~0_In988825553 256) 0)) (.cse2 (= 0 (mod ~y$r_buff0_thd2~0_In988825553 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork0_#t~ite6_Out988825553| 0)) (and (= |P1Thread1of1ForFork0_#t~ite6_Out988825553| ~y$w_buff1_used~0_In988825553) (or .cse0 .cse1) (or .cse3 .cse2)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In988825553, ~y$w_buff0_used~0=~y$w_buff0_used~0_In988825553, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In988825553, ~y$w_buff1_used~0=~y$w_buff1_used~0_In988825553} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In988825553, ~y$w_buff0_used~0=~y$w_buff0_used~0_In988825553, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In988825553, P1Thread1of1ForFork0_#t~ite6=|P1Thread1of1ForFork0_#t~ite6_Out988825553|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In988825553} AuxVars[] AssignedVars[P1Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-11-28 18:15:32,907 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [679] [679] L757-->L757-2: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd2~0_In799384886 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In799384886 256)))) (or (and (= ~y$r_buff0_thd2~0_In799384886 |P1Thread1of1ForFork0_#t~ite7_Out799384886|) (or .cse0 .cse1)) (and (= |P1Thread1of1ForFork0_#t~ite7_Out799384886| 0) (not .cse1) (not .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In799384886, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In799384886} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In799384886, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In799384886, P1Thread1of1ForFork0_#t~ite7=|P1Thread1of1ForFork0_#t~ite7_Out799384886|} AuxVars[] AssignedVars[P1Thread1of1ForFork0_#t~ite7] because there is no mapped edge [2019-11-28 18:15:32,907 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [694] [694] L758-->L758-2: Formula: (let ((.cse2 (= 0 (mod ~y$r_buff1_thd2~0_In2075033157 256))) (.cse3 (= 0 (mod ~y$w_buff1_used~0_In2075033157 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In2075033157 256))) (.cse1 (= (mod ~y$r_buff0_thd2~0_In2075033157 256) 0))) (or (and (= 0 |P1Thread1of1ForFork0_#t~ite8_Out2075033157|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse2 .cse3) (= ~y$r_buff1_thd2~0_In2075033157 |P1Thread1of1ForFork0_#t~ite8_Out2075033157|) (or .cse0 .cse1)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In2075033157, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2075033157, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2075033157, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2075033157} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In2075033157, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2075033157, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2075033157, P1Thread1of1ForFork0_#t~ite8=|P1Thread1of1ForFork0_#t~ite8_Out2075033157|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2075033157} AuxVars[] AssignedVars[P1Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-11-28 18:15:32,908 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [732] [732] L758-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork0_#res.offset_3|) (= v_~__unbuffered_cnt~0_75 (+ v_~__unbuffered_cnt~0_76 1)) (= v_~y$r_buff1_thd2~0_82 |v_P1Thread1of1ForFork0_#t~ite8_36|) (= 0 |v_P1Thread1of1ForFork0_#res.base_3|)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_76, P1Thread1of1ForFork0_#t~ite8=|v_P1Thread1of1ForFork0_#t~ite8_36|} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_82, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_75, P1Thread1of1ForFork0_#res.offset=|v_P1Thread1of1ForFork0_#res.offset_3|, P1Thread1of1ForFork0_#t~ite8=|v_P1Thread1of1ForFork0_#t~ite8_35|, P1Thread1of1ForFork0_#res.base=|v_P1Thread1of1ForFork0_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork0_#res.offset, P1Thread1of1ForFork0_#t~ite8, P1Thread1of1ForFork0_#res.base] because there is no mapped edge [2019-11-28 18:15:32,908 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [673] [673] L820-->L822-2: Formula: (and (or (= 0 (mod v_~y$w_buff0_used~0_253 256)) (= (mod v_~y$r_buff0_thd0~0_142 256) 0)) (not (= 0 (mod v_~main$tmp_guard0~0_6 256)))) InVars {~y$w_buff0_used~0=v_~y$w_buff0_used~0_253, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_142, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} OutVars{~y$w_buff0_used~0=v_~y$w_buff0_used~0_253, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_142, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[] because there is no mapped edge [2019-11-28 18:15:32,909 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [696] [696] L822-2-->L822-5: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff1_used~0_In-139363583 256))) (.cse1 (= (mod ~y$r_buff1_thd0~0_In-139363583 256) 0)) (.cse2 (= |ULTIMATE.start_main_#t~ite18_Out-139363583| |ULTIMATE.start_main_#t~ite19_Out-139363583|))) (or (and (not .cse0) (= ~y$w_buff1~0_In-139363583 |ULTIMATE.start_main_#t~ite18_Out-139363583|) (not .cse1) .cse2) (and (= |ULTIMATE.start_main_#t~ite18_Out-139363583| ~y~0_In-139363583) (or .cse0 .cse1) .cse2))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-139363583, ~y~0=~y~0_In-139363583, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-139363583, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-139363583} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-139363583, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out-139363583|, ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out-139363583|, ~y~0=~y~0_In-139363583, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-139363583, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-139363583} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-11-28 18:15:32,909 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [700] [700] L823-->L823-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd0~0_In-1013926846 256) 0)) (.cse1 (= (mod ~y$w_buff0_used~0_In-1013926846 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite20_Out-1013926846| ~y$w_buff0_used~0_In-1013926846) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite20_Out-1013926846|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1013926846, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1013926846} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1013926846, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1013926846, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out-1013926846|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-11-28 18:15:32,910 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [688] [688] L824-->L824-2: Formula: (let ((.cse3 (= (mod ~y$r_buff1_thd0~0_In-1361838364 256) 0)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In-1361838364 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In-1361838364 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In-1361838364 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite21_Out-1361838364| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |ULTIMATE.start_main_#t~ite21_Out-1361838364| ~y$w_buff1_used~0_In-1361838364) (or .cse3 .cse2) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1361838364, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1361838364, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1361838364, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1361838364} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1361838364, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1361838364, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out-1361838364|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1361838364, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1361838364} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-11-28 18:15:32,910 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [683] [683] L825-->L825-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In1103973071 256) 0)) (.cse1 (= (mod ~y$r_buff0_thd0~0_In1103973071 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite22_Out1103973071| ~y$r_buff0_thd0~0_In1103973071) (or .cse0 .cse1)) (and (not .cse0) (= |ULTIMATE.start_main_#t~ite22_Out1103973071| 0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1103973071, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1103973071} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1103973071, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1103973071, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out1103973071|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-11-28 18:15:32,911 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [695] [695] L826-->L826-2: Formula: (let ((.cse2 (= 0 (mod ~y$r_buff1_thd0~0_In-215016201 256))) (.cse3 (= 0 (mod ~y$w_buff1_used~0_In-215016201 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In-215016201 256) 0)) (.cse0 (= (mod ~y$r_buff0_thd0~0_In-215016201 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite23_Out-215016201| ~y$r_buff1_thd0~0_In-215016201) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= |ULTIMATE.start_main_#t~ite23_Out-215016201| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-215016201, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-215016201, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-215016201, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-215016201} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-215016201, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-215016201, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-215016201, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out-215016201|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-215016201} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-11-28 18:15:32,912 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [739] [739] L834-->L834-8: Formula: (let ((.cse1 (= (mod ~weak$$choice2~0_In1113467591 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite29_Out1113467591| |ULTIMATE.start_main_#t~ite30_Out1113467591|) (let ((.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In1113467591 256)))) (or (and .cse0 (= 0 (mod ~y$r_buff1_thd0~0_In1113467591 256))) (= (mod ~y$w_buff0_used~0_In1113467591 256) 0) (and .cse0 (= (mod ~y$w_buff1_used~0_In1113467591 256) 0)))) (= |ULTIMATE.start_main_#t~ite29_Out1113467591| ~y$w_buff0~0_In1113467591) .cse1) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite30_Out1113467591| ~y$w_buff0~0_In1113467591) (= |ULTIMATE.start_main_#t~ite29_In1113467591| |ULTIMATE.start_main_#t~ite29_Out1113467591|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1113467591, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_In1113467591|, ~y$w_buff0~0=~y$w_buff0~0_In1113467591, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1113467591, ~weak$$choice2~0=~weak$$choice2~0_In1113467591, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1113467591, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1113467591} OutVars{ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out1113467591|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1113467591, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out1113467591|, ~y$w_buff0~0=~y$w_buff0~0_In1113467591, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1113467591, ~weak$$choice2~0=~weak$$choice2~0_In1113467591, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1113467591, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1113467591} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-11-28 18:15:32,914 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [737] [737] L836-->L836-8: Formula: (let ((.cse1 (= 0 (mod ~weak$$choice2~0_In-111275815 256)))) (or (and (let ((.cse0 (= (mod ~y$r_buff0_thd0~0_In-111275815 256) 0))) (or (= (mod ~y$w_buff0_used~0_In-111275815 256) 0) (and .cse0 (= (mod ~y$w_buff1_used~0_In-111275815 256) 0)) (and (= (mod ~y$r_buff1_thd0~0_In-111275815 256) 0) .cse0))) (= |ULTIMATE.start_main_#t~ite35_Out-111275815| |ULTIMATE.start_main_#t~ite36_Out-111275815|) .cse1 (= |ULTIMATE.start_main_#t~ite35_Out-111275815| ~y$w_buff0_used~0_In-111275815)) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite35_In-111275815| |ULTIMATE.start_main_#t~ite35_Out-111275815|) (= |ULTIMATE.start_main_#t~ite36_Out-111275815| ~y$w_buff0_used~0_In-111275815)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-111275815, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-111275815, ULTIMATE.start_main_#t~ite35=|ULTIMATE.start_main_#t~ite35_In-111275815|, ~weak$$choice2~0=~weak$$choice2~0_In-111275815, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-111275815, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-111275815} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-111275815, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-111275815, ULTIMATE.start_main_#t~ite35=|ULTIMATE.start_main_#t~ite35_Out-111275815|, ULTIMATE.start_main_#t~ite36=|ULTIMATE.start_main_#t~ite36_Out-111275815|, ~weak$$choice2~0=~weak$$choice2~0_In-111275815, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-111275815, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-111275815} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite36] because there is no mapped edge [2019-11-28 18:15:32,914 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [736] [736] L837-->L837-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-1481401754 256)))) (or (and (= ~y$w_buff1_used~0_In-1481401754 |ULTIMATE.start_main_#t~ite38_Out-1481401754|) .cse0 (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In-1481401754 256) 0))) (or (and .cse1 (= 0 (mod ~y$w_buff1_used~0_In-1481401754 256))) (= (mod ~y$w_buff0_used~0_In-1481401754 256) 0) (and .cse1 (= 0 (mod ~y$r_buff1_thd0~0_In-1481401754 256))))) (= |ULTIMATE.start_main_#t~ite39_Out-1481401754| |ULTIMATE.start_main_#t~ite38_Out-1481401754|)) (and (= |ULTIMATE.start_main_#t~ite38_In-1481401754| |ULTIMATE.start_main_#t~ite38_Out-1481401754|) (not .cse0) (= ~y$w_buff1_used~0_In-1481401754 |ULTIMATE.start_main_#t~ite39_Out-1481401754|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1481401754, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1481401754, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_In-1481401754|, ~weak$$choice2~0=~weak$$choice2~0_In-1481401754, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1481401754, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1481401754} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1481401754, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out-1481401754|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1481401754, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_Out-1481401754|, ~weak$$choice2~0=~weak$$choice2~0_In-1481401754, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1481401754, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1481401754} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite38] because there is no mapped edge [2019-11-28 18:15:32,915 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [659] [659] L838-->L839: Formula: (and (not (= (mod v_~weak$$choice2~0_22 256) 0)) (= v_~y$r_buff0_thd0~0_108 v_~y$r_buff0_thd0~0_107)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_108, ~weak$$choice2~0=v_~weak$$choice2~0_22} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_10|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_11|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_107, ~weak$$choice2~0=v_~weak$$choice2~0_22, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_8|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-11-28 18:15:32,915 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [738] [738] L839-->L839-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In-647857068 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite45_Out-647857068| ~y$r_buff1_thd0~0_In-647857068) (= |ULTIMATE.start_main_#t~ite44_In-647857068| |ULTIMATE.start_main_#t~ite44_Out-647857068|) (not .cse0)) (and (= |ULTIMATE.start_main_#t~ite44_Out-647857068| |ULTIMATE.start_main_#t~ite45_Out-647857068|) (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In-647857068 256)))) (or (= 0 (mod ~y$w_buff0_used~0_In-647857068 256)) (and (= 0 (mod ~y$r_buff1_thd0~0_In-647857068 256)) .cse1) (and (= (mod ~y$w_buff1_used~0_In-647857068 256) 0) .cse1))) .cse0 (= |ULTIMATE.start_main_#t~ite44_Out-647857068| ~y$r_buff1_thd0~0_In-647857068)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-647857068, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-647857068, ~weak$$choice2~0=~weak$$choice2~0_In-647857068, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-647857068, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-647857068, ULTIMATE.start_main_#t~ite44=|ULTIMATE.start_main_#t~ite44_In-647857068|} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-647857068, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-647857068, ~weak$$choice2~0=~weak$$choice2~0_In-647857068, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-647857068, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_Out-647857068|, ULTIMATE.start_main_#t~ite44=|ULTIMATE.start_main_#t~ite44_Out-647857068|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-647857068} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44] because there is no mapped edge [2019-11-28 18:15:32,916 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [731] [731] L841-->L4: Formula: (and (= 0 v_~y$flush_delayed~0_27) (= v_~y~0_103 v_~y$mem_tmp~0_13) (not (= 0 (mod v_~y$flush_delayed~0_28 256))) (= (mod v_~main$tmp_guard1~0_17 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|)) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_13, ~y$flush_delayed~0=v_~y$flush_delayed~0_28, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_17} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_13, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_12, ~y$flush_delayed~0=v_~y$flush_delayed~0_27, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_27|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_17, ~y~0=v_~y~0_103, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ~y$flush_delayed~0, ULTIMATE.start_main_#t~ite46, ~y~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-11-28 18:15:32,916 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [728] [728] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_9 0) (= v_ULTIMATE.start___VERIFIER_assert_~expression_9 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_9, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-11-28 18:15:33,004 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 06:15:33 BasicIcfg [2019-11-28 18:15:33,004 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-28 18:15:33,005 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-28 18:15:33,005 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-28 18:15:33,005 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-28 18:15:33,006 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:15:09" (3/4) ... [2019-11-28 18:15:33,009 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-28 18:15:33,010 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [756] [756] ULTIMATE.startENTRY-->L812: Formula: (let ((.cse0 (store |v_#valid_56| 0 0))) (and (= v_~y$w_buff0_used~0_565 0) (= v_~y$w_buff1_used~0_304 0) (< |v_#StackHeapBarrier_14| |v_ULTIMATE.start_main_~#t1114~0.base_27|) (= v_~main$tmp_guard0~0_30 0) (= v_~y$r_buff0_thd0~0_292 0) (= 0 v_~weak$$choice2~0_82) (= 0 v_~y$read_delayed_var~0.offset_8) (= (select .cse0 |v_ULTIMATE.start_main_~#t1114~0.base_27|) 0) (= 0 v_~__unbuffered_cnt~0_94) (= 0 v_~y$r_buff1_thd3~0_89) (= v_~y$read_delayed~0_8 0) (= 0 v_~y$r_buff1_thd2~0_113) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1114~0.base_27| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1114~0.base_27|) |v_ULTIMATE.start_main_~#t1114~0.offset_21| 0)) |v_#memory_int_15|) (= v_~main$tmp_guard1~0_30 0) (= v_~x~0_51 0) (= v_~y$w_buff1~0_136 0) (= |v_#length_19| (store |v_#length_20| |v_ULTIMATE.start_main_~#t1114~0.base_27| 4)) (= 0 v_~y$r_buff0_thd2~0_108) (< 0 |v_#StackHeapBarrier_14|) (= v_~y$r_buff0_thd1~0_41 0) (= 0 |v_ULTIMATE.start_main_~#t1114~0.offset_21|) (= v_~a~0_57 0) (= v_~y$mem_tmp~0_17 0) (= v_~z~0_41 0) (= 0 v_~y$r_buff1_thd1~0_40) (= v_~__unbuffered_p2_EBX~0_54 0) (= |v_#valid_54| (store .cse0 |v_ULTIMATE.start_main_~#t1114~0.base_27| 1)) (= v_~y~0_123 0) (= v_~y$r_buff1_thd0~0_196 0) (= |v_#NULL.offset_5| 0) (= 0 v_~y$r_buff0_thd3~0_130) (= 0 v_~y$read_delayed_var~0.base_8) (= 0 v_~__unbuffered_p2_EAX~0_54) (= 0 v_~__unbuffered_p0_EAX~0_39) (= 0 v_~weak$$choice0~0_13) (= 0 |v_#NULL.base_5|) (= 0 v_~y$flush_delayed~0_34) (= 0 v_~y$w_buff0~0_162))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_56|, #memory_int=|v_#memory_int_16|, #length=|v_#length_20|} OutVars{ULTIMATE.start_main_~#t1114~0.offset=|v_ULTIMATE.start_main_~#t1114~0.offset_21|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_28|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_35|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_29|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_51|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_35|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_50|, ~y$read_delayed~0=v_~y$read_delayed~0_8, ~a~0=v_~a~0_57, ~y$mem_tmp~0=v_~y$mem_tmp~0_17, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_39, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_89, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_41, ~y$flush_delayed~0=v_~y$flush_delayed~0_34, #length=|v_#length_19|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_54, ULTIMATE.start_main_~#t1115~0.base=|v_ULTIMATE.start_main_~#t1115~0.base_26|, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_54, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_29|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_30|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_17|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_116|, ULTIMATE.start_main_~#t1116~0.offset=|v_ULTIMATE.start_main_~#t1116~0.offset_16|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_33|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_32|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_25|, ~weak$$choice0~0=v_~weak$$choice0~0_13, #StackHeapBarrier=|v_#StackHeapBarrier_14|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_26|, ~y$w_buff1~0=v_~y$w_buff1~0_136, ULTIMATE.start_main_~#t1116~0.base=|v_ULTIMATE.start_main_~#t1116~0.base_21|, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_8, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_108, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_10|, ULTIMATE.start_main_~#t1115~0.offset=|v_ULTIMATE.start_main_~#t1115~0.offset_20|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_20|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_94, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_196, ~x~0=v_~x~0_51, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_8, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_565, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_34|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_36|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_30, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_49|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_31|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_27|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_27|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_42|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_40, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_28|, ~y$w_buff0~0=v_~y$w_buff0~0_162, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_130, ~y~0=v_~y~0_123, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_32|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_17|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_196|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_28|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_30, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_34|, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_110|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_113, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_26|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_21|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_292, #valid=|v_#valid_54|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_~#t1114~0.base=|v_ULTIMATE.start_main_~#t1114~0.base_27|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_10|, ~z~0=v_~z~0_41, ~weak$$choice2~0=v_~weak$$choice2~0_82, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_304} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1114~0.offset, ULTIMATE.start_main_#t~ite28, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~y$read_delayed~0, ~a~0, ~y$mem_tmp~0, ~__unbuffered_p0_EAX~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_~#t1115~0.base, ~__unbuffered_p2_EBX~0, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_~#t1116~0.offset, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ULTIMATE.start_main_~#t1116~0.base, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_~#t1115~0.offset, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_~#t1114~0.base, ULTIMATE.start_main_#t~nondet16, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:15:33,011 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [704] [704] L812-1-->L814: Formula: (and (= |v_#length_13| (store |v_#length_14| |v_ULTIMATE.start_main_~#t1115~0.base_9| 4)) (< |v_#StackHeapBarrier_9| |v_ULTIMATE.start_main_~#t1115~0.base_9|) (= |v_ULTIMATE.start_main_~#t1115~0.offset_8| 0) (= (select |v_#valid_28| |v_ULTIMATE.start_main_~#t1115~0.base_9|) 0) (= |v_#valid_27| (store |v_#valid_28| |v_ULTIMATE.start_main_~#t1115~0.base_9| 1)) (not (= |v_ULTIMATE.start_main_~#t1115~0.base_9| 0)) (= |v_#memory_int_9| (store |v_#memory_int_10| |v_ULTIMATE.start_main_~#t1115~0.base_9| (store (select |v_#memory_int_10| |v_ULTIMATE.start_main_~#t1115~0.base_9|) |v_ULTIMATE.start_main_~#t1115~0.offset_8| 1)))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_28|, #memory_int=|v_#memory_int_10|, #length=|v_#length_14|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_27|, #memory_int=|v_#memory_int_9|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_4|, ULTIMATE.start_main_~#t1115~0.offset=|v_ULTIMATE.start_main_~#t1115~0.offset_8|, #length=|v_#length_13|, ULTIMATE.start_main_~#t1115~0.base=|v_ULTIMATE.start_main_~#t1115~0.base_9|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_~#t1115~0.offset, #length, ULTIMATE.start_main_~#t1115~0.base] because there is no mapped edge [2019-11-28 18:15:33,011 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [712] [712] L814-1-->L816: Formula: (and (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t1116~0.base_10|) (= 0 (select |v_#valid_30| |v_ULTIMATE.start_main_~#t1116~0.base_10|)) (= |v_ULTIMATE.start_main_~#t1116~0.offset_10| 0) (= |v_#valid_29| (store |v_#valid_30| |v_ULTIMATE.start_main_~#t1116~0.base_10| 1)) (= (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t1116~0.base_10| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t1116~0.base_10|) |v_ULTIMATE.start_main_~#t1116~0.offset_10| 2)) |v_#memory_int_11|) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t1116~0.base_10| 4)) (not (= 0 |v_ULTIMATE.start_main_~#t1116~0.base_10|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_30|, #memory_int=|v_#memory_int_12|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_10|, ULTIMATE.start_main_~#t1116~0.base=|v_ULTIMATE.start_main_~#t1116~0.base_10|, #valid=|v_#valid_29|, #memory_int=|v_#memory_int_11|, ULTIMATE.start_main_~#t1116~0.offset=|v_ULTIMATE.start_main_~#t1116~0.offset_10|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, #length=|v_#length_15|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1116~0.base, #valid, #memory_int, ULTIMATE.start_main_~#t1116~0.offset, ULTIMATE.start_main_#t~nondet16, #length] because there is no mapped edge [2019-11-28 18:15:33,012 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [740] [740] L4-->L789: Formula: (and (not (= P2Thread1of1ForFork1___VERIFIER_assert_~expression_In-1787557029 0)) (= ~z~0_Out-1787557029 ~__unbuffered_p2_EAX~0_Out-1787557029) (= ~y$r_buff0_thd3~0_Out-1787557029 1) (= ~y$r_buff1_thd0~0_Out-1787557029 ~y$r_buff0_thd0~0_In-1787557029) (= ~y$r_buff0_thd3~0_In-1787557029 ~y$r_buff1_thd3~0_Out-1787557029) (= ~a~0_In-1787557029 ~__unbuffered_p2_EBX~0_Out-1787557029) (= ~y$r_buff0_thd1~0_In-1787557029 ~y$r_buff1_thd1~0_Out-1787557029) (= ~z~0_Out-1787557029 1) (= ~y$r_buff1_thd2~0_Out-1787557029 ~y$r_buff0_thd2~0_In-1787557029)) InVars {~a~0=~a~0_In-1787557029, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1787557029, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1787557029, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1787557029, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In-1787557029, P2Thread1of1ForFork1___VERIFIER_assert_~expression=P2Thread1of1ForFork1___VERIFIER_assert_~expression_In-1787557029} OutVars{~__unbuffered_p2_EBX~0=~__unbuffered_p2_EBX~0_Out-1787557029, P2Thread1of1ForFork1___VERIFIER_assert_~expression=P2Thread1of1ForFork1___VERIFIER_assert_~expression_In-1787557029, ~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_Out-1787557029, ~a~0=~a~0_In-1787557029, ~y$r_buff1_thd1~0=~y$r_buff1_thd1~0_Out-1787557029, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_Out-1787557029, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out-1787557029, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1787557029, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1787557029, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In-1787557029, ~__unbuffered_p2_EAX~0=~__unbuffered_p2_EAX~0_Out-1787557029, ~z~0=~z~0_Out-1787557029, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_Out-1787557029} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, ~y$r_buff1_thd1~0, ~__unbuffered_p2_EBX~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd3~0, ~__unbuffered_p2_EAX~0, ~z~0, ~y$r_buff1_thd0~0] because there is no mapped edge [2019-11-28 18:15:33,012 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [711] [711] P0ENTRY-->P0EXIT: Formula: (and (= v_P0Thread1of1ForFork2_~arg.base_8 |v_P0Thread1of1ForFork2_#in~arg.base_10|) (= v_~a~0_22 1) (= v_~x~0_29 v_~__unbuffered_p0_EAX~0_17) (= (+ v_~__unbuffered_cnt~0_41 1) v_~__unbuffered_cnt~0_40) (= v_P0Thread1of1ForFork2_~arg.offset_8 |v_P0Thread1of1ForFork2_#in~arg.offset_10|) (= |v_P0Thread1of1ForFork2_#res.offset_3| 0) (= 0 |v_P0Thread1of1ForFork2_#res.base_3|)) InVars {P0Thread1of1ForFork2_#in~arg.offset=|v_P0Thread1of1ForFork2_#in~arg.offset_10|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_41, P0Thread1of1ForFork2_#in~arg.base=|v_P0Thread1of1ForFork2_#in~arg.base_10|, ~x~0=v_~x~0_29} OutVars{~a~0=v_~a~0_22, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_17, P0Thread1of1ForFork2_#in~arg.offset=|v_P0Thread1of1ForFork2_#in~arg.offset_10|, P0Thread1of1ForFork2_~arg.offset=v_P0Thread1of1ForFork2_~arg.offset_8, P0Thread1of1ForFork2_#res.offset=|v_P0Thread1of1ForFork2_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_40, P0Thread1of1ForFork2_#in~arg.base=|v_P0Thread1of1ForFork2_#in~arg.base_10|, P0Thread1of1ForFork2_#res.base=|v_P0Thread1of1ForFork2_#res.base_3|, ~x~0=v_~x~0_29, P0Thread1of1ForFork2_~arg.base=v_P0Thread1of1ForFork2_~arg.base_8} AuxVars[] AssignedVars[~a~0, ~__unbuffered_p0_EAX~0, P0Thread1of1ForFork2_~arg.offset, P0Thread1of1ForFork2_#res.offset, ~__unbuffered_cnt~0, P0Thread1of1ForFork2_#res.base, P0Thread1of1ForFork2_~arg.base] because there is no mapped edge [2019-11-28 18:15:33,013 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [682] [682] L754-2-->L754-5: Formula: (let ((.cse0 (= (mod ~y$w_buff1_used~0_In113155889 256) 0)) (.cse2 (= (mod ~y$r_buff1_thd2~0_In113155889 256) 0)) (.cse1 (= |P1Thread1of1ForFork0_#t~ite4_Out113155889| |P1Thread1of1ForFork0_#t~ite3_Out113155889|))) (or (and (= ~y$w_buff1~0_In113155889 |P1Thread1of1ForFork0_#t~ite3_Out113155889|) (not .cse0) .cse1 (not .cse2)) (and (or .cse0 .cse2) (= ~y~0_In113155889 |P1Thread1of1ForFork0_#t~ite3_Out113155889|) .cse1))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In113155889, ~y$w_buff1~0=~y$w_buff1~0_In113155889, ~y~0=~y~0_In113155889, ~y$w_buff1_used~0=~y$w_buff1_used~0_In113155889} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In113155889, ~y$w_buff1~0=~y$w_buff1~0_In113155889, P1Thread1of1ForFork0_#t~ite3=|P1Thread1of1ForFork0_#t~ite3_Out113155889|, ~y~0=~y~0_In113155889, P1Thread1of1ForFork0_#t~ite4=|P1Thread1of1ForFork0_#t~ite4_Out113155889|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In113155889} AuxVars[] AssignedVars[P1Thread1of1ForFork0_#t~ite3, P1Thread1of1ForFork0_#t~ite4] because there is no mapped edge [2019-11-28 18:15:33,014 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L790-->L790-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In-2059670464 256))) (.cse1 (= (mod ~y$r_buff0_thd3~0_In-2059670464 256) 0))) (or (and (not .cse0) (= 0 |P2Thread1of1ForFork1_#t~ite11_Out-2059670464|) (not .cse1)) (and (= |P2Thread1of1ForFork1_#t~ite11_Out-2059670464| ~y$w_buff0_used~0_In-2059670464) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-2059670464, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-2059670464} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-2059670464, P2Thread1of1ForFork1_#t~ite11=|P2Thread1of1ForFork1_#t~ite11_Out-2059670464|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-2059670464} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-11-28 18:15:33,015 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [686] [686] L791-->L791-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In-2094201678 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In-2094201678 256) 0)) (.cse3 (= 0 (mod ~y$r_buff1_thd3~0_In-2094201678 256))) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In-2094201678 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork1_#t~ite12_Out-2094201678| 0)) (and (= |P2Thread1of1ForFork1_#t~ite12_Out-2094201678| ~y$w_buff1_used~0_In-2094201678) (or .cse0 .cse1) (or .cse3 .cse2)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-2094201678, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2094201678, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-2094201678, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2094201678} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-2094201678, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2094201678, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-2094201678, P2Thread1of1ForFork1_#t~ite12=|P2Thread1of1ForFork1_#t~ite12_Out-2094201678|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2094201678} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-11-28 18:15:33,015 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [689] [689] L792-->L793: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd3~0_In1441516150 256) 0)) (.cse0 (= (mod ~y$w_buff0_used~0_In1441516150 256) 0)) (.cse2 (= ~y$r_buff0_thd3~0_Out1441516150 ~y$r_buff0_thd3~0_In1441516150))) (or (and (= 0 ~y$r_buff0_thd3~0_Out1441516150) (not .cse0) (not .cse1)) (and .cse2 .cse1) (and .cse0 .cse2))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1441516150, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1441516150} OutVars{P2Thread1of1ForFork1_#t~ite13=|P2Thread1of1ForFork1_#t~ite13_Out1441516150|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1441516150, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out1441516150} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite13, ~y$r_buff0_thd3~0] because there is no mapped edge [2019-11-28 18:15:33,016 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [699] [699] L793-->L793-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In741858247 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In741858247 256))) (.cse2 (= (mod ~y$w_buff1_used~0_In741858247 256) 0)) (.cse3 (= 0 (mod ~y$r_buff1_thd3~0_In741858247 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork1_#t~ite14_Out741858247|)) (and (or .cse0 .cse1) (= |P2Thread1of1ForFork1_#t~ite14_Out741858247| ~y$r_buff1_thd3~0_In741858247) (or .cse2 .cse3)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In741858247, ~y$w_buff0_used~0=~y$w_buff0_used~0_In741858247, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In741858247, ~y$w_buff1_used~0=~y$w_buff1_used~0_In741858247} OutVars{P2Thread1of1ForFork1_#t~ite14=|P2Thread1of1ForFork1_#t~ite14_Out741858247|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In741858247, ~y$w_buff0_used~0=~y$w_buff0_used~0_In741858247, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In741858247, ~y$w_buff1_used~0=~y$w_buff1_used~0_In741858247} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-11-28 18:15:33,016 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [717] [717] L793-2-->P2EXIT: Formula: (and (= 0 |v_P2Thread1of1ForFork1_#res.offset_3|) (= (+ v_~__unbuffered_cnt~0_59 1) v_~__unbuffered_cnt~0_58) (= |v_P2Thread1of1ForFork1_#t~ite14_34| v_~y$r_buff1_thd3~0_55) (= 0 |v_P2Thread1of1ForFork1_#res.base_3|)) InVars {P2Thread1of1ForFork1_#t~ite14=|v_P2Thread1of1ForFork1_#t~ite14_34|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_59} OutVars{P2Thread1of1ForFork1_#t~ite14=|v_P2Thread1of1ForFork1_#t~ite14_33|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_55, P2Thread1of1ForFork1_#res.base=|v_P2Thread1of1ForFork1_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_58, P2Thread1of1ForFork1_#res.offset=|v_P2Thread1of1ForFork1_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork1_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork1_#res.offset] because there is no mapped edge [2019-11-28 18:15:33,016 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [687] [687] L755-->L755-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In1328626474 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In1328626474 256)))) (or (and (= |P1Thread1of1ForFork0_#t~ite5_Out1328626474| ~y$w_buff0_used~0_In1328626474) (or .cse0 .cse1)) (and (not .cse1) (= |P1Thread1of1ForFork0_#t~ite5_Out1328626474| 0) (not .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1328626474, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1328626474} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1328626474, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1328626474, P1Thread1of1ForFork0_#t~ite5=|P1Thread1of1ForFork0_#t~ite5_Out1328626474|} AuxVars[] AssignedVars[P1Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-11-28 18:15:33,017 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [680] [680] L756-->L756-2: Formula: (let ((.cse0 (= (mod ~y$w_buff1_used~0_In988825553 256) 0)) (.cse1 (= (mod ~y$r_buff1_thd2~0_In988825553 256) 0)) (.cse3 (= (mod ~y$w_buff0_used~0_In988825553 256) 0)) (.cse2 (= 0 (mod ~y$r_buff0_thd2~0_In988825553 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork0_#t~ite6_Out988825553| 0)) (and (= |P1Thread1of1ForFork0_#t~ite6_Out988825553| ~y$w_buff1_used~0_In988825553) (or .cse0 .cse1) (or .cse3 .cse2)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In988825553, ~y$w_buff0_used~0=~y$w_buff0_used~0_In988825553, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In988825553, ~y$w_buff1_used~0=~y$w_buff1_used~0_In988825553} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In988825553, ~y$w_buff0_used~0=~y$w_buff0_used~0_In988825553, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In988825553, P1Thread1of1ForFork0_#t~ite6=|P1Thread1of1ForFork0_#t~ite6_Out988825553|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In988825553} AuxVars[] AssignedVars[P1Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-11-28 18:15:33,017 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [679] [679] L757-->L757-2: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd2~0_In799384886 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In799384886 256)))) (or (and (= ~y$r_buff0_thd2~0_In799384886 |P1Thread1of1ForFork0_#t~ite7_Out799384886|) (or .cse0 .cse1)) (and (= |P1Thread1of1ForFork0_#t~ite7_Out799384886| 0) (not .cse1) (not .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In799384886, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In799384886} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In799384886, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In799384886, P1Thread1of1ForFork0_#t~ite7=|P1Thread1of1ForFork0_#t~ite7_Out799384886|} AuxVars[] AssignedVars[P1Thread1of1ForFork0_#t~ite7] because there is no mapped edge [2019-11-28 18:15:33,018 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [694] [694] L758-->L758-2: Formula: (let ((.cse2 (= 0 (mod ~y$r_buff1_thd2~0_In2075033157 256))) (.cse3 (= 0 (mod ~y$w_buff1_used~0_In2075033157 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In2075033157 256))) (.cse1 (= (mod ~y$r_buff0_thd2~0_In2075033157 256) 0))) (or (and (= 0 |P1Thread1of1ForFork0_#t~ite8_Out2075033157|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse2 .cse3) (= ~y$r_buff1_thd2~0_In2075033157 |P1Thread1of1ForFork0_#t~ite8_Out2075033157|) (or .cse0 .cse1)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In2075033157, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2075033157, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2075033157, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2075033157} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In2075033157, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2075033157, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2075033157, P1Thread1of1ForFork0_#t~ite8=|P1Thread1of1ForFork0_#t~ite8_Out2075033157|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2075033157} AuxVars[] AssignedVars[P1Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-11-28 18:15:33,018 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [732] [732] L758-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork0_#res.offset_3|) (= v_~__unbuffered_cnt~0_75 (+ v_~__unbuffered_cnt~0_76 1)) (= v_~y$r_buff1_thd2~0_82 |v_P1Thread1of1ForFork0_#t~ite8_36|) (= 0 |v_P1Thread1of1ForFork0_#res.base_3|)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_76, P1Thread1of1ForFork0_#t~ite8=|v_P1Thread1of1ForFork0_#t~ite8_36|} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_82, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_75, P1Thread1of1ForFork0_#res.offset=|v_P1Thread1of1ForFork0_#res.offset_3|, P1Thread1of1ForFork0_#t~ite8=|v_P1Thread1of1ForFork0_#t~ite8_35|, P1Thread1of1ForFork0_#res.base=|v_P1Thread1of1ForFork0_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork0_#res.offset, P1Thread1of1ForFork0_#t~ite8, P1Thread1of1ForFork0_#res.base] because there is no mapped edge [2019-11-28 18:15:33,019 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [673] [673] L820-->L822-2: Formula: (and (or (= 0 (mod v_~y$w_buff0_used~0_253 256)) (= (mod v_~y$r_buff0_thd0~0_142 256) 0)) (not (= 0 (mod v_~main$tmp_guard0~0_6 256)))) InVars {~y$w_buff0_used~0=v_~y$w_buff0_used~0_253, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_142, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} OutVars{~y$w_buff0_used~0=v_~y$w_buff0_used~0_253, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_142, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[] because there is no mapped edge [2019-11-28 18:15:33,019 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [696] [696] L822-2-->L822-5: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff1_used~0_In-139363583 256))) (.cse1 (= (mod ~y$r_buff1_thd0~0_In-139363583 256) 0)) (.cse2 (= |ULTIMATE.start_main_#t~ite18_Out-139363583| |ULTIMATE.start_main_#t~ite19_Out-139363583|))) (or (and (not .cse0) (= ~y$w_buff1~0_In-139363583 |ULTIMATE.start_main_#t~ite18_Out-139363583|) (not .cse1) .cse2) (and (= |ULTIMATE.start_main_#t~ite18_Out-139363583| ~y~0_In-139363583) (or .cse0 .cse1) .cse2))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-139363583, ~y~0=~y~0_In-139363583, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-139363583, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-139363583} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-139363583, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out-139363583|, ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out-139363583|, ~y~0=~y~0_In-139363583, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-139363583, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-139363583} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-11-28 18:15:33,020 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [700] [700] L823-->L823-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd0~0_In-1013926846 256) 0)) (.cse1 (= (mod ~y$w_buff0_used~0_In-1013926846 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite20_Out-1013926846| ~y$w_buff0_used~0_In-1013926846) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite20_Out-1013926846|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1013926846, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1013926846} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1013926846, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1013926846, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out-1013926846|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-11-28 18:15:33,020 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [688] [688] L824-->L824-2: Formula: (let ((.cse3 (= (mod ~y$r_buff1_thd0~0_In-1361838364 256) 0)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In-1361838364 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In-1361838364 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In-1361838364 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite21_Out-1361838364| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |ULTIMATE.start_main_#t~ite21_Out-1361838364| ~y$w_buff1_used~0_In-1361838364) (or .cse3 .cse2) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1361838364, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1361838364, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1361838364, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1361838364} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1361838364, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1361838364, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out-1361838364|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1361838364, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1361838364} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-11-28 18:15:33,021 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [683] [683] L825-->L825-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In1103973071 256) 0)) (.cse1 (= (mod ~y$r_buff0_thd0~0_In1103973071 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite22_Out1103973071| ~y$r_buff0_thd0~0_In1103973071) (or .cse0 .cse1)) (and (not .cse0) (= |ULTIMATE.start_main_#t~ite22_Out1103973071| 0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1103973071, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1103973071} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1103973071, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1103973071, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out1103973071|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-11-28 18:15:33,021 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [695] [695] L826-->L826-2: Formula: (let ((.cse2 (= 0 (mod ~y$r_buff1_thd0~0_In-215016201 256))) (.cse3 (= 0 (mod ~y$w_buff1_used~0_In-215016201 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In-215016201 256) 0)) (.cse0 (= (mod ~y$r_buff0_thd0~0_In-215016201 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite23_Out-215016201| ~y$r_buff1_thd0~0_In-215016201) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= |ULTIMATE.start_main_#t~ite23_Out-215016201| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-215016201, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-215016201, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-215016201, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-215016201} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-215016201, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-215016201, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-215016201, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out-215016201|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-215016201} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-11-28 18:15:33,023 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [739] [739] L834-->L834-8: Formula: (let ((.cse1 (= (mod ~weak$$choice2~0_In1113467591 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite29_Out1113467591| |ULTIMATE.start_main_#t~ite30_Out1113467591|) (let ((.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In1113467591 256)))) (or (and .cse0 (= 0 (mod ~y$r_buff1_thd0~0_In1113467591 256))) (= (mod ~y$w_buff0_used~0_In1113467591 256) 0) (and .cse0 (= (mod ~y$w_buff1_used~0_In1113467591 256) 0)))) (= |ULTIMATE.start_main_#t~ite29_Out1113467591| ~y$w_buff0~0_In1113467591) .cse1) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite30_Out1113467591| ~y$w_buff0~0_In1113467591) (= |ULTIMATE.start_main_#t~ite29_In1113467591| |ULTIMATE.start_main_#t~ite29_Out1113467591|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1113467591, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_In1113467591|, ~y$w_buff0~0=~y$w_buff0~0_In1113467591, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1113467591, ~weak$$choice2~0=~weak$$choice2~0_In1113467591, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1113467591, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1113467591} OutVars{ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out1113467591|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1113467591, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out1113467591|, ~y$w_buff0~0=~y$w_buff0~0_In1113467591, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1113467591, ~weak$$choice2~0=~weak$$choice2~0_In1113467591, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1113467591, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1113467591} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-11-28 18:15:33,024 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [737] [737] L836-->L836-8: Formula: (let ((.cse1 (= 0 (mod ~weak$$choice2~0_In-111275815 256)))) (or (and (let ((.cse0 (= (mod ~y$r_buff0_thd0~0_In-111275815 256) 0))) (or (= (mod ~y$w_buff0_used~0_In-111275815 256) 0) (and .cse0 (= (mod ~y$w_buff1_used~0_In-111275815 256) 0)) (and (= (mod ~y$r_buff1_thd0~0_In-111275815 256) 0) .cse0))) (= |ULTIMATE.start_main_#t~ite35_Out-111275815| |ULTIMATE.start_main_#t~ite36_Out-111275815|) .cse1 (= |ULTIMATE.start_main_#t~ite35_Out-111275815| ~y$w_buff0_used~0_In-111275815)) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite35_In-111275815| |ULTIMATE.start_main_#t~ite35_Out-111275815|) (= |ULTIMATE.start_main_#t~ite36_Out-111275815| ~y$w_buff0_used~0_In-111275815)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-111275815, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-111275815, ULTIMATE.start_main_#t~ite35=|ULTIMATE.start_main_#t~ite35_In-111275815|, ~weak$$choice2~0=~weak$$choice2~0_In-111275815, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-111275815, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-111275815} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-111275815, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-111275815, ULTIMATE.start_main_#t~ite35=|ULTIMATE.start_main_#t~ite35_Out-111275815|, ULTIMATE.start_main_#t~ite36=|ULTIMATE.start_main_#t~ite36_Out-111275815|, ~weak$$choice2~0=~weak$$choice2~0_In-111275815, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-111275815, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-111275815} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite36] because there is no mapped edge [2019-11-28 18:15:33,025 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [736] [736] L837-->L837-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-1481401754 256)))) (or (and (= ~y$w_buff1_used~0_In-1481401754 |ULTIMATE.start_main_#t~ite38_Out-1481401754|) .cse0 (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In-1481401754 256) 0))) (or (and .cse1 (= 0 (mod ~y$w_buff1_used~0_In-1481401754 256))) (= (mod ~y$w_buff0_used~0_In-1481401754 256) 0) (and .cse1 (= 0 (mod ~y$r_buff1_thd0~0_In-1481401754 256))))) (= |ULTIMATE.start_main_#t~ite39_Out-1481401754| |ULTIMATE.start_main_#t~ite38_Out-1481401754|)) (and (= |ULTIMATE.start_main_#t~ite38_In-1481401754| |ULTIMATE.start_main_#t~ite38_Out-1481401754|) (not .cse0) (= ~y$w_buff1_used~0_In-1481401754 |ULTIMATE.start_main_#t~ite39_Out-1481401754|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1481401754, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1481401754, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_In-1481401754|, ~weak$$choice2~0=~weak$$choice2~0_In-1481401754, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1481401754, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1481401754} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1481401754, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out-1481401754|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1481401754, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_Out-1481401754|, ~weak$$choice2~0=~weak$$choice2~0_In-1481401754, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1481401754, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1481401754} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite38] because there is no mapped edge [2019-11-28 18:15:33,025 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [659] [659] L838-->L839: Formula: (and (not (= (mod v_~weak$$choice2~0_22 256) 0)) (= v_~y$r_buff0_thd0~0_108 v_~y$r_buff0_thd0~0_107)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_108, ~weak$$choice2~0=v_~weak$$choice2~0_22} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_10|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_11|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_107, ~weak$$choice2~0=v_~weak$$choice2~0_22, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_8|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-11-28 18:15:33,025 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [738] [738] L839-->L839-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In-647857068 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite45_Out-647857068| ~y$r_buff1_thd0~0_In-647857068) (= |ULTIMATE.start_main_#t~ite44_In-647857068| |ULTIMATE.start_main_#t~ite44_Out-647857068|) (not .cse0)) (and (= |ULTIMATE.start_main_#t~ite44_Out-647857068| |ULTIMATE.start_main_#t~ite45_Out-647857068|) (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In-647857068 256)))) (or (= 0 (mod ~y$w_buff0_used~0_In-647857068 256)) (and (= 0 (mod ~y$r_buff1_thd0~0_In-647857068 256)) .cse1) (and (= (mod ~y$w_buff1_used~0_In-647857068 256) 0) .cse1))) .cse0 (= |ULTIMATE.start_main_#t~ite44_Out-647857068| ~y$r_buff1_thd0~0_In-647857068)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-647857068, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-647857068, ~weak$$choice2~0=~weak$$choice2~0_In-647857068, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-647857068, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-647857068, ULTIMATE.start_main_#t~ite44=|ULTIMATE.start_main_#t~ite44_In-647857068|} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-647857068, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-647857068, ~weak$$choice2~0=~weak$$choice2~0_In-647857068, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-647857068, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_Out-647857068|, ULTIMATE.start_main_#t~ite44=|ULTIMATE.start_main_#t~ite44_Out-647857068|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-647857068} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44] because there is no mapped edge [2019-11-28 18:15:33,026 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [731] [731] L841-->L4: Formula: (and (= 0 v_~y$flush_delayed~0_27) (= v_~y~0_103 v_~y$mem_tmp~0_13) (not (= 0 (mod v_~y$flush_delayed~0_28 256))) (= (mod v_~main$tmp_guard1~0_17 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|)) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_13, ~y$flush_delayed~0=v_~y$flush_delayed~0_28, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_17} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_13, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_12, ~y$flush_delayed~0=v_~y$flush_delayed~0_27, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_27|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_17, ~y~0=v_~y~0_103, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ~y$flush_delayed~0, ULTIMATE.start_main_#t~ite46, ~y~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-11-28 18:15:33,026 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [728] [728] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_9 0) (= v_ULTIMATE.start___VERIFIER_assert_~expression_9 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_9, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-11-28 18:15:33,155 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2019-11-28 18:15:33,155 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-28 18:15:33,157 INFO L168 Benchmark]: Toolchain (without parser) took 25288.95 ms. Allocated memory was 1.0 GB in the beginning and 2.0 GB in the end (delta: 966.3 MB). Free memory was 956.3 MB in the beginning and 1.3 GB in the end (delta: -341.1 MB). Peak memory consumption was 625.1 MB. Max. memory is 11.5 GB. [2019-11-28 18:15:33,157 INFO L168 Benchmark]: CDTParser took 0.33 ms. Allocated memory is still 1.0 GB. Free memory is still 987.2 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 18:15:33,158 INFO L168 Benchmark]: CACSL2BoogieTranslator took 746.72 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 145.2 MB). Free memory was 956.3 MB in the beginning and 1.1 GB in the end (delta: -157.1 MB). Peak memory consumption was 25.9 MB. Max. memory is 11.5 GB. [2019-11-28 18:15:33,158 INFO L168 Benchmark]: Boogie Procedure Inliner took 73.54 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.6 MB). Peak memory consumption was 6.6 MB. Max. memory is 11.5 GB. [2019-11-28 18:15:33,158 INFO L168 Benchmark]: Boogie Preprocessor took 51.04 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 18:15:33,159 INFO L168 Benchmark]: RCFGBuilder took 847.04 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 50.8 MB). Peak memory consumption was 50.8 MB. Max. memory is 11.5 GB. [2019-11-28 18:15:33,159 INFO L168 Benchmark]: TraceAbstraction took 23414.45 ms. Allocated memory was 1.2 GB in the beginning and 2.0 GB in the end (delta: 821.0 MB). Free memory was 1.1 GB in the beginning and 1.3 GB in the end (delta: -259.8 MB). Peak memory consumption was 561.2 MB. Max. memory is 11.5 GB. [2019-11-28 18:15:33,160 INFO L168 Benchmark]: Witness Printer took 150.42 ms. Allocated memory is still 2.0 GB. Free memory was 1.3 GB in the beginning and 1.3 GB in the end (delta: 18.3 MB). Peak memory consumption was 18.3 MB. Max. memory is 11.5 GB. [2019-11-28 18:15:33,162 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.33 ms. Allocated memory is still 1.0 GB. Free memory is still 987.2 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 746.72 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 145.2 MB). Free memory was 956.3 MB in the beginning and 1.1 GB in the end (delta: -157.1 MB). Peak memory consumption was 25.9 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 73.54 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.6 MB). Peak memory consumption was 6.6 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 51.04 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 847.04 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 50.8 MB). Peak memory consumption was 50.8 MB. Max. memory is 11.5 GB. * TraceAbstraction took 23414.45 ms. Allocated memory was 1.2 GB in the beginning and 2.0 GB in the end (delta: 821.0 MB). Free memory was 1.1 GB in the beginning and 1.3 GB in the end (delta: -259.8 MB). Peak memory consumption was 561.2 MB. Max. memory is 11.5 GB. * Witness Printer took 150.42 ms. Allocated memory is still 2.0 GB. Free memory was 1.3 GB in the beginning and 1.3 GB in the end (delta: 18.3 MB). Peak memory consumption was 18.3 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 5.3s, 165 ProgramPointsBefore, 79 ProgramPointsAfterwards, 196 TransitionsBefore, 86 TransitionsAfterwards, 11490 CoEnabledTransitionPairs, 8 FixpointIterations, 34 TrivialSequentialCompositions, 45 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 38 ConcurrentYvCompositions, 28 ChoiceCompositions, 4263 VarBasedMoverChecksPositive, 162 VarBasedMoverChecksNegative, 17 SemBasedMoverChecksPositive, 192 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 1.1s, 0 MoverChecksTotal, 50142 CheckedPairsTotal, 117 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L812] FCALL, FORK 0 pthread_create(&t1114, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L814] FCALL, FORK 0 pthread_create(&t1115, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L816] FCALL, FORK 0 pthread_create(&t1116, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L768] 3 y$w_buff1 = y$w_buff0 [L769] 3 y$w_buff0 = 2 [L770] 3 y$w_buff1_used = y$w_buff0_used [L771] 3 y$w_buff0_used = (_Bool)1 [L789] EXPR 3 y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L748] 2 x = 1 [L751] 2 y = 1 VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L754] EXPR 2 y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L754] 2 y = y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) [L789] 3 y = y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) [L790] 3 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : y$w_buff0_used [L791] 3 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd3 || y$w_buff1_used && y$r_buff1_thd3 ? (_Bool)0 : y$w_buff1_used [L755] 2 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$w_buff0_used [L756] 2 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used [L757] 2 y$r_buff0_thd2 = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$r_buff0_thd2 [L818] 0 main$tmp_guard0 = __unbuffered_cnt == 3 VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L822] 0 y = y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) [L823] 0 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used [L824] 0 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$w_buff1_used [L825] 0 y$r_buff0_thd0 = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$r_buff0_thd0 [L826] 0 y$r_buff1_thd0 = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$r_buff1_thd0 [L829] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L830] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L831] 0 y$flush_delayed = weak$$choice2 [L832] 0 y$mem_tmp = y VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L833] EXPR 0 !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L833] 0 y = !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) [L834] 0 y$w_buff0 = weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) [L835] EXPR 0 weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L835] 0 y$w_buff1 = weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) [L836] 0 y$w_buff0_used = weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) [L837] 0 y$w_buff1_used = weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L839] 0 y$r_buff1_thd0 = weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L840] 0 main$tmp_guard1 = !(y == 2 && __unbuffered_p0_EAX == 0 && __unbuffered_p2_EAX == 1 && __unbuffered_p2_EBX == 0) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 156 locations, 2 error locations. Result: UNSAFE, OverallTime: 23.1s, OverallIterations: 17, TraceHistogramMax: 1, AutomataDifference: 8.2s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 1709 SDtfs, 2498 SDslu, 5627 SDs, 0 SdLazy, 4377 SolverSat, 267 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 4.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 212 GetRequests, 19 SyntacticMatches, 15 SemanticMatches, 178 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 825 ImplicationChecksByTransitivity, 2.9s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=22366occurred in iteration=3, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 4.5s AutomataMinimizationTime, 16 MinimizatonAttempts, 15075 StatesRemovedByMinimization, 13 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.5s SatisfiabilityAnalysisTime, 2.5s InterpolantComputationTime, 710 NumberOfCodeBlocks, 710 NumberOfCodeBlocksAsserted, 17 NumberOfCheckSat, 637 ConstructedInterpolants, 0 QuantifiedInterpolants, 161997 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 16 InterpolantComputations, 16 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...