./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/pthread-wmm/mix045_rmo.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx12G -Xms1G -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/pthread-wmm/mix045_rmo.opt.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ffdb96218020f2881bb98b194a2936942fa2529d ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-11-28 18:16:14,446 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-28 18:16:14,448 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-28 18:16:14,461 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-28 18:16:14,462 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-28 18:16:14,463 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-28 18:16:14,465 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-28 18:16:14,467 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-28 18:16:14,469 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-28 18:16:14,470 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-28 18:16:14,471 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-28 18:16:14,472 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-28 18:16:14,473 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-28 18:16:14,474 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-28 18:16:14,475 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-28 18:16:14,478 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-28 18:16:14,479 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-28 18:16:14,480 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-28 18:16:14,482 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-28 18:16:14,484 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-28 18:16:14,486 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-28 18:16:14,487 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-28 18:16:14,488 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-28 18:16:14,489 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-28 18:16:14,491 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-28 18:16:14,492 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-28 18:16:14,492 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-28 18:16:14,493 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-28 18:16:14,494 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-28 18:16:14,495 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-28 18:16:14,495 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-28 18:16:14,496 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-28 18:16:14,497 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-28 18:16:14,498 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-28 18:16:14,499 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-28 18:16:14,499 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-28 18:16:14,500 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-28 18:16:14,500 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-28 18:16:14,501 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-28 18:16:14,502 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-28 18:16:14,503 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-28 18:16:14,504 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-28 18:16:14,518 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-28 18:16:14,519 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-28 18:16:14,520 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-28 18:16:14,521 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-28 18:16:14,521 INFO L138 SettingsManager]: * Use SBE=true [2019-11-28 18:16:14,521 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-28 18:16:14,522 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-28 18:16:14,522 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-28 18:16:14,522 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-28 18:16:14,522 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-28 18:16:14,523 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-28 18:16:14,523 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-28 18:16:14,523 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-28 18:16:14,524 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-28 18:16:14,524 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-28 18:16:14,524 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-28 18:16:14,524 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-28 18:16:14,525 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-28 18:16:14,525 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-28 18:16:14,525 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-28 18:16:14,526 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-28 18:16:14,526 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 18:16:14,526 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-28 18:16:14,527 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-28 18:16:14,527 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-28 18:16:14,527 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-28 18:16:14,527 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-28 18:16:14,528 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-28 18:16:14,528 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-11-28 18:16:14,528 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ffdb96218020f2881bb98b194a2936942fa2529d [2019-11-28 18:16:14,838 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-28 18:16:14,852 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-28 18:16:14,856 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-28 18:16:14,858 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-28 18:16:14,858 INFO L275 PluginConnector]: CDTParser initialized [2019-11-28 18:16:14,859 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/pthread-wmm/mix045_rmo.opt.i [2019-11-28 18:16:14,925 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/69ac40f0c/ba286f1b36a048d8b3f2080f6983fbaf/FLAG6b615ea87 [2019-11-28 18:16:15,498 INFO L306 CDTParser]: Found 1 translation units. [2019-11-28 18:16:15,499 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/pthread-wmm/mix045_rmo.opt.i [2019-11-28 18:16:15,515 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/69ac40f0c/ba286f1b36a048d8b3f2080f6983fbaf/FLAG6b615ea87 [2019-11-28 18:16:15,742 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/69ac40f0c/ba286f1b36a048d8b3f2080f6983fbaf [2019-11-28 18:16:15,745 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-28 18:16:15,746 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-28 18:16:15,747 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-28 18:16:15,748 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-28 18:16:15,751 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-28 18:16:15,752 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 06:16:15" (1/1) ... [2019-11-28 18:16:15,755 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5a736f88 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:16:15, skipping insertion in model container [2019-11-28 18:16:15,756 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 06:16:15" (1/1) ... [2019-11-28 18:16:15,764 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-11-28 18:16:15,831 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-11-28 18:16:16,336 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 18:16:16,355 INFO L203 MainTranslator]: Completed pre-run [2019-11-28 18:16:16,457 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 18:16:16,539 INFO L208 MainTranslator]: Completed translation [2019-11-28 18:16:16,540 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:16:16 WrapperNode [2019-11-28 18:16:16,540 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-28 18:16:16,541 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-28 18:16:16,542 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-28 18:16:16,542 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-28 18:16:16,552 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:16:16" (1/1) ... [2019-11-28 18:16:16,583 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:16:16" (1/1) ... [2019-11-28 18:16:16,630 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-28 18:16:16,631 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-28 18:16:16,631 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-28 18:16:16,631 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-28 18:16:16,643 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:16:16" (1/1) ... [2019-11-28 18:16:16,644 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:16:16" (1/1) ... [2019-11-28 18:16:16,648 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:16:16" (1/1) ... [2019-11-28 18:16:16,649 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:16:16" (1/1) ... [2019-11-28 18:16:16,659 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:16:16" (1/1) ... [2019-11-28 18:16:16,664 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:16:16" (1/1) ... [2019-11-28 18:16:16,668 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:16:16" (1/1) ... [2019-11-28 18:16:16,673 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-28 18:16:16,674 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-28 18:16:16,674 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-28 18:16:16,674 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-28 18:16:16,675 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:16:16" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 18:16:16,754 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-11-28 18:16:16,754 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-11-28 18:16:16,755 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-11-28 18:16:16,756 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-11-28 18:16:16,756 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-11-28 18:16:16,756 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-11-28 18:16:16,757 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-11-28 18:16:16,757 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-11-28 18:16:16,757 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-11-28 18:16:16,758 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-11-28 18:16:16,758 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-11-28 18:16:16,759 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-28 18:16:16,759 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-28 18:16:16,761 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-11-28 18:16:17,499 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-28 18:16:17,500 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-11-28 18:16:17,501 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:16:17 BoogieIcfgContainer [2019-11-28 18:16:17,501 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-28 18:16:17,503 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-28 18:16:17,503 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-28 18:16:17,506 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-28 18:16:17,506 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 06:16:15" (1/3) ... [2019-11-28 18:16:17,507 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@11fb0e43 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 06:16:17, skipping insertion in model container [2019-11-28 18:16:17,508 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:16:16" (2/3) ... [2019-11-28 18:16:17,508 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@11fb0e43 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 06:16:17, skipping insertion in model container [2019-11-28 18:16:17,508 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:16:17" (3/3) ... [2019-11-28 18:16:17,510 INFO L109 eAbstractionObserver]: Analyzing ICFG mix045_rmo.opt.i [2019-11-28 18:16:17,522 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-11-28 18:16:17,522 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-28 18:16:17,531 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-11-28 18:16:17,532 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-11-28 18:16:17,586 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,587 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,587 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,588 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,588 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,589 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,591 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,592 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,592 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,592 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,593 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,593 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,593 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,593 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,594 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,594 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,594 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,595 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,595 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,595 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,596 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,596 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,597 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,597 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,598 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,598 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,598 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,599 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,599 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,599 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,600 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,600 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,601 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,601 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,602 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,603 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,606 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,607 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,607 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,608 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,608 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,609 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,609 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,609 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,610 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,610 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,610 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,611 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,611 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,611 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,612 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,612 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,612 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,612 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,613 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,613 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,613 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,613 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,614 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,614 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,614 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,614 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,614 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,615 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,615 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,615 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,615 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,616 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,616 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,616 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:16:17,637 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-11-28 18:16:17,658 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-28 18:16:17,658 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-28 18:16:17,658 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-28 18:16:17,658 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-28 18:16:17,659 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-28 18:16:17,659 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-28 18:16:17,659 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-28 18:16:17,659 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-28 18:16:17,676 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 164 places, 195 transitions [2019-11-28 18:16:17,678 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 164 places, 195 transitions [2019-11-28 18:16:17,771 INFO L134 PetriNetUnfolder]: 41/192 cut-off events. [2019-11-28 18:16:17,772 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-11-28 18:16:17,790 INFO L76 FinitePrefix]: Finished finitePrefix Result has 202 conditions, 192 events. 41/192 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 469 event pairs. 9/158 useless extension candidates. Maximal degree in co-relation 161. Up to 2 conditions per place. [2019-11-28 18:16:17,821 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 164 places, 195 transitions [2019-11-28 18:16:17,872 INFO L134 PetriNetUnfolder]: 41/192 cut-off events. [2019-11-28 18:16:17,873 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-11-28 18:16:17,880 INFO L76 FinitePrefix]: Finished finitePrefix Result has 202 conditions, 192 events. 41/192 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 469 event pairs. 9/158 useless extension candidates. Maximal degree in co-relation 161. Up to 2 conditions per place. [2019-11-28 18:16:17,897 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 11490 [2019-11-28 18:16:17,898 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-11-28 18:16:20,617 WARN L192 SmtUtils]: Spent 126.00 ms on a formula simplification. DAG size of input: 44 DAG size of output: 32 [2019-11-28 18:16:23,032 WARN L192 SmtUtils]: Spent 295.00 ms on a formula simplification. DAG size of input: 91 DAG size of output: 89 [2019-11-28 18:16:23,163 WARN L192 SmtUtils]: Spent 128.00 ms on a formula simplification that was a NOOP. DAG size: 87 [2019-11-28 18:16:23,190 INFO L206 etLargeBlockEncoding]: Checked pairs total: 46792 [2019-11-28 18:16:23,190 INFO L214 etLargeBlockEncoding]: Total number of compositions: 114 [2019-11-28 18:16:23,196 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 82 places, 91 transitions [2019-11-28 18:16:24,806 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 16134 states. [2019-11-28 18:16:24,809 INFO L276 IsEmpty]: Start isEmpty. Operand 16134 states. [2019-11-28 18:16:24,821 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2019-11-28 18:16:24,822 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:16:24,824 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:16:24,824 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:16:24,831 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:16:24,832 INFO L82 PathProgramCache]: Analyzing trace with hash 1643101290, now seen corresponding path program 1 times [2019-11-28 18:16:24,842 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:16:24,843 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2141650966] [2019-11-28 18:16:24,852 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:16:25,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:16:25,205 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:16:25,206 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2141650966] [2019-11-28 18:16:25,207 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:16:25,207 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-11-28 18:16:25,207 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1407321536] [2019-11-28 18:16:25,213 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:16:25,214 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:16:25,229 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:16:25,231 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:16:25,233 INFO L87 Difference]: Start difference. First operand 16134 states. Second operand 3 states. [2019-11-28 18:16:25,611 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:16:25,612 INFO L93 Difference]: Finished difference Result 16034 states and 60310 transitions. [2019-11-28 18:16:25,612 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:16:25,614 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2019-11-28 18:16:25,615 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:16:25,796 INFO L225 Difference]: With dead ends: 16034 [2019-11-28 18:16:25,796 INFO L226 Difference]: Without dead ends: 15698 [2019-11-28 18:16:25,798 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:16:26,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15698 states. [2019-11-28 18:16:26,615 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15698 to 15698. [2019-11-28 18:16:26,618 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15698 states. [2019-11-28 18:16:26,713 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15698 states to 15698 states and 59106 transitions. [2019-11-28 18:16:26,715 INFO L78 Accepts]: Start accepts. Automaton has 15698 states and 59106 transitions. Word has length 7 [2019-11-28 18:16:26,716 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:16:26,716 INFO L462 AbstractCegarLoop]: Abstraction has 15698 states and 59106 transitions. [2019-11-28 18:16:26,717 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:16:26,717 INFO L276 IsEmpty]: Start isEmpty. Operand 15698 states and 59106 transitions. [2019-11-28 18:16:26,721 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-11-28 18:16:26,721 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:16:26,722 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:16:26,722 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:16:26,723 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:16:26,723 INFO L82 PathProgramCache]: Analyzing trace with hash 565568960, now seen corresponding path program 1 times [2019-11-28 18:16:26,723 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:16:26,724 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [211620613] [2019-11-28 18:16:26,724 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:16:26,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:16:26,861 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:16:26,861 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [211620613] [2019-11-28 18:16:26,861 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:16:26,862 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:16:26,862 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2032847635] [2019-11-28 18:16:26,864 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:16:26,864 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:16:26,864 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:16:26,865 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:16:26,865 INFO L87 Difference]: Start difference. First operand 15698 states and 59106 transitions. Second operand 4 states. [2019-11-28 18:16:27,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:16:27,302 INFO L93 Difference]: Finished difference Result 24414 states and 88322 transitions. [2019-11-28 18:16:27,302 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:16:27,303 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-11-28 18:16:27,303 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:16:27,426 INFO L225 Difference]: With dead ends: 24414 [2019-11-28 18:16:27,426 INFO L226 Difference]: Without dead ends: 24400 [2019-11-28 18:16:27,429 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:16:27,598 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24400 states. [2019-11-28 18:16:28,426 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24400 to 22284. [2019-11-28 18:16:28,427 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22284 states. [2019-11-28 18:16:28,518 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22284 states to 22284 states and 81513 transitions. [2019-11-28 18:16:28,519 INFO L78 Accepts]: Start accepts. Automaton has 22284 states and 81513 transitions. Word has length 13 [2019-11-28 18:16:28,520 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:16:28,520 INFO L462 AbstractCegarLoop]: Abstraction has 22284 states and 81513 transitions. [2019-11-28 18:16:28,520 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:16:28,520 INFO L276 IsEmpty]: Start isEmpty. Operand 22284 states and 81513 transitions. [2019-11-28 18:16:28,523 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-11-28 18:16:28,523 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:16:28,523 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:16:28,524 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:16:28,524 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:16:28,524 INFO L82 PathProgramCache]: Analyzing trace with hash 1863901117, now seen corresponding path program 1 times [2019-11-28 18:16:28,525 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:16:28,525 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1996761518] [2019-11-28 18:16:28,525 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:16:28,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:16:28,571 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:16:28,571 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1996761518] [2019-11-28 18:16:28,571 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:16:28,572 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:16:28,572 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1732013300] [2019-11-28 18:16:28,572 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:16:28,572 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:16:28,573 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:16:28,574 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:16:28,574 INFO L87 Difference]: Start difference. First operand 22284 states and 81513 transitions. Second operand 3 states. [2019-11-28 18:16:28,646 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:16:28,646 INFO L93 Difference]: Finished difference Result 12731 states and 40311 transitions. [2019-11-28 18:16:28,646 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:16:28,647 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 13 [2019-11-28 18:16:28,647 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:16:28,689 INFO L225 Difference]: With dead ends: 12731 [2019-11-28 18:16:28,689 INFO L226 Difference]: Without dead ends: 12731 [2019-11-28 18:16:28,690 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:16:28,769 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12731 states. [2019-11-28 18:16:29,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12731 to 12731. [2019-11-28 18:16:29,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12731 states. [2019-11-28 18:16:29,053 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12731 states to 12731 states and 40311 transitions. [2019-11-28 18:16:29,054 INFO L78 Accepts]: Start accepts. Automaton has 12731 states and 40311 transitions. Word has length 13 [2019-11-28 18:16:29,054 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:16:29,054 INFO L462 AbstractCegarLoop]: Abstraction has 12731 states and 40311 transitions. [2019-11-28 18:16:29,055 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:16:29,055 INFO L276 IsEmpty]: Start isEmpty. Operand 12731 states and 40311 transitions. [2019-11-28 18:16:29,056 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2019-11-28 18:16:29,057 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:16:29,057 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:16:29,057 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:16:29,057 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:16:29,058 INFO L82 PathProgramCache]: Analyzing trace with hash -709244429, now seen corresponding path program 1 times [2019-11-28 18:16:29,058 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:16:29,058 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1081038830] [2019-11-28 18:16:29,059 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:16:29,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:16:29,174 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:16:29,174 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1081038830] [2019-11-28 18:16:29,174 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:16:29,175 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:16:29,175 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1884342863] [2019-11-28 18:16:29,175 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:16:29,175 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:16:29,176 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:16:29,176 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:16:29,176 INFO L87 Difference]: Start difference. First operand 12731 states and 40311 transitions. Second operand 4 states. [2019-11-28 18:16:29,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:16:29,425 INFO L93 Difference]: Finished difference Result 15391 states and 48077 transitions. [2019-11-28 18:16:29,425 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:16:29,426 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 14 [2019-11-28 18:16:29,427 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:16:29,474 INFO L225 Difference]: With dead ends: 15391 [2019-11-28 18:16:29,475 INFO L226 Difference]: Without dead ends: 15391 [2019-11-28 18:16:29,475 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:16:29,572 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15391 states. [2019-11-28 18:16:29,886 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15391 to 13966. [2019-11-28 18:16:29,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13966 states. [2019-11-28 18:16:29,962 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13966 states to 13966 states and 44017 transitions. [2019-11-28 18:16:29,963 INFO L78 Accepts]: Start accepts. Automaton has 13966 states and 44017 transitions. Word has length 14 [2019-11-28 18:16:29,963 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:16:29,964 INFO L462 AbstractCegarLoop]: Abstraction has 13966 states and 44017 transitions. [2019-11-28 18:16:29,964 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:16:29,964 INFO L276 IsEmpty]: Start isEmpty. Operand 13966 states and 44017 transitions. [2019-11-28 18:16:29,970 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2019-11-28 18:16:29,971 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:16:29,971 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:16:29,972 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:16:29,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:16:29,973 INFO L82 PathProgramCache]: Analyzing trace with hash 1059334979, now seen corresponding path program 1 times [2019-11-28 18:16:29,973 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:16:29,974 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1922622771] [2019-11-28 18:16:29,974 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:16:30,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:16:30,035 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:16:30,036 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1922622771] [2019-11-28 18:16:30,036 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:16:30,037 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:16:30,037 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [889459389] [2019-11-28 18:16:30,038 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:16:30,038 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:16:30,039 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:16:30,039 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:16:30,040 INFO L87 Difference]: Start difference. First operand 13966 states and 44017 transitions. Second operand 4 states. [2019-11-28 18:16:30,080 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:16:30,081 INFO L93 Difference]: Finished difference Result 1935 states and 4522 transitions. [2019-11-28 18:16:30,081 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-28 18:16:30,081 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 20 [2019-11-28 18:16:30,082 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:16:30,087 INFO L225 Difference]: With dead ends: 1935 [2019-11-28 18:16:30,087 INFO L226 Difference]: Without dead ends: 1935 [2019-11-28 18:16:30,089 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:16:30,098 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1935 states. [2019-11-28 18:16:30,476 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1935 to 1935. [2019-11-28 18:16:30,476 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1935 states. [2019-11-28 18:16:30,481 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1935 states to 1935 states and 4522 transitions. [2019-11-28 18:16:30,482 INFO L78 Accepts]: Start accepts. Automaton has 1935 states and 4522 transitions. Word has length 20 [2019-11-28 18:16:30,483 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:16:30,483 INFO L462 AbstractCegarLoop]: Abstraction has 1935 states and 4522 transitions. [2019-11-28 18:16:30,483 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:16:30,483 INFO L276 IsEmpty]: Start isEmpty. Operand 1935 states and 4522 transitions. [2019-11-28 18:16:30,485 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2019-11-28 18:16:30,486 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:16:30,486 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:16:30,486 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:16:30,486 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:16:30,487 INFO L82 PathProgramCache]: Analyzing trace with hash -1471989024, now seen corresponding path program 1 times [2019-11-28 18:16:30,487 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:16:30,487 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2000329896] [2019-11-28 18:16:30,488 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:16:30,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:16:30,768 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:16:30,769 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2000329896] [2019-11-28 18:16:30,770 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:16:30,771 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 18:16:30,772 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1683502272] [2019-11-28 18:16:30,772 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-11-28 18:16:30,773 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:16:30,773 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-11-28 18:16:30,773 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2019-11-28 18:16:30,774 INFO L87 Difference]: Start difference. First operand 1935 states and 4522 transitions. Second operand 7 states. [2019-11-28 18:16:31,133 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:16:31,134 INFO L93 Difference]: Finished difference Result 2347 states and 5328 transitions. [2019-11-28 18:16:31,134 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-11-28 18:16:31,134 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 26 [2019-11-28 18:16:31,135 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:16:31,138 INFO L225 Difference]: With dead ends: 2347 [2019-11-28 18:16:31,138 INFO L226 Difference]: Without dead ends: 2347 [2019-11-28 18:16:31,138 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2019-11-28 18:16:31,143 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2347 states. [2019-11-28 18:16:31,182 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2347 to 2152. [2019-11-28 18:16:31,182 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2152 states. [2019-11-28 18:16:31,188 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2152 states to 2152 states and 4956 transitions. [2019-11-28 18:16:31,188 INFO L78 Accepts]: Start accepts. Automaton has 2152 states and 4956 transitions. Word has length 26 [2019-11-28 18:16:31,189 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:16:31,189 INFO L462 AbstractCegarLoop]: Abstraction has 2152 states and 4956 transitions. [2019-11-28 18:16:31,189 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-11-28 18:16:31,189 INFO L276 IsEmpty]: Start isEmpty. Operand 2152 states and 4956 transitions. [2019-11-28 18:16:31,204 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2019-11-28 18:16:31,205 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:16:31,205 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:16:31,205 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:16:31,205 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:16:31,206 INFO L82 PathProgramCache]: Analyzing trace with hash -1098055765, now seen corresponding path program 1 times [2019-11-28 18:16:31,206 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:16:31,207 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1018611813] [2019-11-28 18:16:31,207 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:16:31,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:16:31,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:16:31,333 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1018611813] [2019-11-28 18:16:31,333 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:16:31,334 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 18:16:31,334 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1941225683] [2019-11-28 18:16:31,334 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:16:31,335 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:16:31,335 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:16:31,336 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:16:31,336 INFO L87 Difference]: Start difference. First operand 2152 states and 4956 transitions. Second operand 5 states. [2019-11-28 18:16:31,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:16:31,361 INFO L93 Difference]: Finished difference Result 670 states and 1551 transitions. [2019-11-28 18:16:31,361 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:16:31,362 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 40 [2019-11-28 18:16:31,362 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:16:31,363 INFO L225 Difference]: With dead ends: 670 [2019-11-28 18:16:31,363 INFO L226 Difference]: Without dead ends: 670 [2019-11-28 18:16:31,364 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:16:31,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 670 states. [2019-11-28 18:16:31,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 670 to 614. [2019-11-28 18:16:31,375 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 614 states. [2019-11-28 18:16:31,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 614 states to 614 states and 1419 transitions. [2019-11-28 18:16:31,378 INFO L78 Accepts]: Start accepts. Automaton has 614 states and 1419 transitions. Word has length 40 [2019-11-28 18:16:31,378 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:16:31,378 INFO L462 AbstractCegarLoop]: Abstraction has 614 states and 1419 transitions. [2019-11-28 18:16:31,378 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:16:31,379 INFO L276 IsEmpty]: Start isEmpty. Operand 614 states and 1419 transitions. [2019-11-28 18:16:31,383 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-11-28 18:16:31,383 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:16:31,384 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:16:31,384 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:16:31,385 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:16:31,385 INFO L82 PathProgramCache]: Analyzing trace with hash 827870922, now seen corresponding path program 1 times [2019-11-28 18:16:31,385 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:16:31,386 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [781580483] [2019-11-28 18:16:31,386 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:16:31,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:16:31,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:16:31,478 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [781580483] [2019-11-28 18:16:31,478 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:16:31,478 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:16:31,479 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1791202375] [2019-11-28 18:16:31,479 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:16:31,479 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:16:31,480 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:16:31,480 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:16:31,480 INFO L87 Difference]: Start difference. First operand 614 states and 1419 transitions. Second operand 3 states. [2019-11-28 18:16:31,523 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:16:31,523 INFO L93 Difference]: Finished difference Result 629 states and 1439 transitions. [2019-11-28 18:16:31,523 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:16:31,523 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 55 [2019-11-28 18:16:31,524 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:16:31,528 INFO L225 Difference]: With dead ends: 629 [2019-11-28 18:16:31,528 INFO L226 Difference]: Without dead ends: 629 [2019-11-28 18:16:31,528 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:16:31,530 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 629 states. [2019-11-28 18:16:31,538 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 629 to 625. [2019-11-28 18:16:31,538 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 625 states. [2019-11-28 18:16:31,540 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 625 states to 625 states and 1435 transitions. [2019-11-28 18:16:31,540 INFO L78 Accepts]: Start accepts. Automaton has 625 states and 1435 transitions. Word has length 55 [2019-11-28 18:16:31,542 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:16:31,542 INFO L462 AbstractCegarLoop]: Abstraction has 625 states and 1435 transitions. [2019-11-28 18:16:31,543 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:16:31,543 INFO L276 IsEmpty]: Start isEmpty. Operand 625 states and 1435 transitions. [2019-11-28 18:16:31,545 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-11-28 18:16:31,545 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:16:31,545 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:16:31,545 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:16:31,546 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:16:31,546 INFO L82 PathProgramCache]: Analyzing trace with hash -345025503, now seen corresponding path program 1 times [2019-11-28 18:16:31,546 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:16:31,551 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [46336360] [2019-11-28 18:16:31,551 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:16:31,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:16:31,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:16:31,629 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [46336360] [2019-11-28 18:16:31,629 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:16:31,629 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:16:31,629 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1837223343] [2019-11-28 18:16:31,631 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:16:31,631 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:16:31,632 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:16:31,632 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:16:31,632 INFO L87 Difference]: Start difference. First operand 625 states and 1435 transitions. Second operand 3 states. [2019-11-28 18:16:31,672 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:16:31,672 INFO L93 Difference]: Finished difference Result 629 states and 1432 transitions. [2019-11-28 18:16:31,673 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:16:31,673 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 55 [2019-11-28 18:16:31,673 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:16:31,674 INFO L225 Difference]: With dead ends: 629 [2019-11-28 18:16:31,674 INFO L226 Difference]: Without dead ends: 629 [2019-11-28 18:16:31,675 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:16:31,676 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 629 states. [2019-11-28 18:16:31,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 629 to 621. [2019-11-28 18:16:31,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 621 states. [2019-11-28 18:16:31,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 621 states to 621 states and 1424 transitions. [2019-11-28 18:16:31,685 INFO L78 Accepts]: Start accepts. Automaton has 621 states and 1424 transitions. Word has length 55 [2019-11-28 18:16:31,686 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:16:31,687 INFO L462 AbstractCegarLoop]: Abstraction has 621 states and 1424 transitions. [2019-11-28 18:16:31,687 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:16:31,687 INFO L276 IsEmpty]: Start isEmpty. Operand 621 states and 1424 transitions. [2019-11-28 18:16:31,690 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-11-28 18:16:31,690 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:16:31,690 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:16:31,690 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:16:31,691 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:16:31,691 INFO L82 PathProgramCache]: Analyzing trace with hash -349465323, now seen corresponding path program 1 times [2019-11-28 18:16:31,691 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:16:31,691 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [448454552] [2019-11-28 18:16:31,692 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:16:31,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:16:31,813 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:16:31,813 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [448454552] [2019-11-28 18:16:31,813 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:16:31,813 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 18:16:31,814 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [182016702] [2019-11-28 18:16:31,814 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:16:31,814 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:16:31,815 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:16:31,815 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:16:31,815 INFO L87 Difference]: Start difference. First operand 621 states and 1424 transitions. Second operand 5 states. [2019-11-28 18:16:32,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:16:32,028 INFO L93 Difference]: Finished difference Result 910 states and 2096 transitions. [2019-11-28 18:16:32,028 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 18:16:32,028 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 55 [2019-11-28 18:16:32,029 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:16:32,030 INFO L225 Difference]: With dead ends: 910 [2019-11-28 18:16:32,030 INFO L226 Difference]: Without dead ends: 910 [2019-11-28 18:16:32,030 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-11-28 18:16:32,032 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 910 states. [2019-11-28 18:16:32,040 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 910 to 820. [2019-11-28 18:16:32,041 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 820 states. [2019-11-28 18:16:32,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 820 states to 820 states and 1891 transitions. [2019-11-28 18:16:32,043 INFO L78 Accepts]: Start accepts. Automaton has 820 states and 1891 transitions. Word has length 55 [2019-11-28 18:16:32,043 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:16:32,043 INFO L462 AbstractCegarLoop]: Abstraction has 820 states and 1891 transitions. [2019-11-28 18:16:32,043 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:16:32,043 INFO L276 IsEmpty]: Start isEmpty. Operand 820 states and 1891 transitions. [2019-11-28 18:16:32,046 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-11-28 18:16:32,046 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:16:32,046 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:16:32,046 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:16:32,046 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:16:32,047 INFO L82 PathProgramCache]: Analyzing trace with hash -1055549477, now seen corresponding path program 2 times [2019-11-28 18:16:32,047 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:16:32,047 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1017113769] [2019-11-28 18:16:32,047 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:16:32,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:16:32,132 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:16:32,133 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1017113769] [2019-11-28 18:16:32,133 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:16:32,133 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:16:32,133 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1690623455] [2019-11-28 18:16:32,134 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:16:32,134 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:16:32,134 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:16:32,134 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:16:32,135 INFO L87 Difference]: Start difference. First operand 820 states and 1891 transitions. Second operand 3 states. [2019-11-28 18:16:32,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:16:32,150 INFO L93 Difference]: Finished difference Result 790 states and 1786 transitions. [2019-11-28 18:16:32,151 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:16:32,151 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 55 [2019-11-28 18:16:32,151 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:16:32,152 INFO L225 Difference]: With dead ends: 790 [2019-11-28 18:16:32,152 INFO L226 Difference]: Without dead ends: 790 [2019-11-28 18:16:32,152 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:16:32,154 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 790 states. [2019-11-28 18:16:32,163 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 790 to 766. [2019-11-28 18:16:32,163 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 766 states. [2019-11-28 18:16:32,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 766 states to 766 states and 1730 transitions. [2019-11-28 18:16:32,165 INFO L78 Accepts]: Start accepts. Automaton has 766 states and 1730 transitions. Word has length 55 [2019-11-28 18:16:32,166 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:16:32,166 INFO L462 AbstractCegarLoop]: Abstraction has 766 states and 1730 transitions. [2019-11-28 18:16:32,166 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:16:32,166 INFO L276 IsEmpty]: Start isEmpty. Operand 766 states and 1730 transitions. [2019-11-28 18:16:32,168 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-11-28 18:16:32,168 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:16:32,168 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:16:32,169 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:16:32,169 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:16:32,169 INFO L82 PathProgramCache]: Analyzing trace with hash 746177187, now seen corresponding path program 1 times [2019-11-28 18:16:32,169 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:16:32,169 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1877377077] [2019-11-28 18:16:32,169 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:16:32,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:16:32,258 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:16:32,258 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1877377077] [2019-11-28 18:16:32,259 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:16:32,259 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:16:32,259 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1920819416] [2019-11-28 18:16:32,259 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:16:32,259 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:16:32,260 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:16:32,260 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:16:32,260 INFO L87 Difference]: Start difference. First operand 766 states and 1730 transitions. Second operand 3 states. [2019-11-28 18:16:32,305 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:16:32,305 INFO L93 Difference]: Finished difference Result 766 states and 1729 transitions. [2019-11-28 18:16:32,305 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:16:32,305 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 56 [2019-11-28 18:16:32,306 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:16:32,307 INFO L225 Difference]: With dead ends: 766 [2019-11-28 18:16:32,307 INFO L226 Difference]: Without dead ends: 766 [2019-11-28 18:16:32,307 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:16:32,309 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 766 states. [2019-11-28 18:16:32,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 766 to 597. [2019-11-28 18:16:32,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 597 states. [2019-11-28 18:16:32,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 597 states to 597 states and 1339 transitions. [2019-11-28 18:16:32,318 INFO L78 Accepts]: Start accepts. Automaton has 597 states and 1339 transitions. Word has length 56 [2019-11-28 18:16:32,318 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:16:32,318 INFO L462 AbstractCegarLoop]: Abstraction has 597 states and 1339 transitions. [2019-11-28 18:16:32,318 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:16:32,318 INFO L276 IsEmpty]: Start isEmpty. Operand 597 states and 1339 transitions. [2019-11-28 18:16:32,320 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:16:32,320 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:16:32,320 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:16:32,320 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:16:32,321 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:16:32,321 INFO L82 PathProgramCache]: Analyzing trace with hash -897693906, now seen corresponding path program 1 times [2019-11-28 18:16:32,321 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:16:32,321 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1192176399] [2019-11-28 18:16:32,321 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:16:32,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:16:32,459 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:16:32,460 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1192176399] [2019-11-28 18:16:32,460 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:16:32,460 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-28 18:16:32,460 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2002593821] [2019-11-28 18:16:32,460 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-11-28 18:16:32,461 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:16:32,461 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-11-28 18:16:32,461 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-11-28 18:16:32,461 INFO L87 Difference]: Start difference. First operand 597 states and 1339 transitions. Second operand 7 states. [2019-11-28 18:16:32,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:16:32,620 INFO L93 Difference]: Finished difference Result 1128 states and 2318 transitions. [2019-11-28 18:16:32,620 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-11-28 18:16:32,621 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 57 [2019-11-28 18:16:32,621 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:16:32,622 INFO L225 Difference]: With dead ends: 1128 [2019-11-28 18:16:32,623 INFO L226 Difference]: Without dead ends: 755 [2019-11-28 18:16:32,623 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=40, Invalid=70, Unknown=0, NotChecked=0, Total=110 [2019-11-28 18:16:32,625 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 755 states. [2019-11-28 18:16:32,635 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 755 to 535. [2019-11-28 18:16:32,635 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 535 states. [2019-11-28 18:16:32,636 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 535 states to 535 states and 1160 transitions. [2019-11-28 18:16:32,637 INFO L78 Accepts]: Start accepts. Automaton has 535 states and 1160 transitions. Word has length 57 [2019-11-28 18:16:32,637 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:16:32,637 INFO L462 AbstractCegarLoop]: Abstraction has 535 states and 1160 transitions. [2019-11-28 18:16:32,637 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-11-28 18:16:32,637 INFO L276 IsEmpty]: Start isEmpty. Operand 535 states and 1160 transitions. [2019-11-28 18:16:32,640 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:16:32,640 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:16:32,640 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:16:32,640 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:16:32,641 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:16:32,641 INFO L82 PathProgramCache]: Analyzing trace with hash 704044892, now seen corresponding path program 2 times [2019-11-28 18:16:32,641 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:16:32,641 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1245145422] [2019-11-28 18:16:32,642 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:16:32,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:16:32,786 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:16:32,787 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1245145422] [2019-11-28 18:16:32,787 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:16:32,788 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 18:16:32,788 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [770468039] [2019-11-28 18:16:32,788 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-28 18:16:32,789 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:16:32,789 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-28 18:16:32,789 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-11-28 18:16:32,789 INFO L87 Difference]: Start difference. First operand 535 states and 1160 transitions. Second operand 6 states. [2019-11-28 18:16:32,862 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:16:32,862 INFO L93 Difference]: Finished difference Result 770 states and 1612 transitions. [2019-11-28 18:16:32,863 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 18:16:32,863 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 57 [2019-11-28 18:16:32,863 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:16:32,863 INFO L225 Difference]: With dead ends: 770 [2019-11-28 18:16:32,863 INFO L226 Difference]: Without dead ends: 233 [2019-11-28 18:16:32,864 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-11-28 18:16:32,865 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 233 states. [2019-11-28 18:16:32,866 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 233 to 209. [2019-11-28 18:16:32,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 209 states. [2019-11-28 18:16:32,867 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 209 states to 209 states and 361 transitions. [2019-11-28 18:16:32,867 INFO L78 Accepts]: Start accepts. Automaton has 209 states and 361 transitions. Word has length 57 [2019-11-28 18:16:32,867 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:16:32,867 INFO L462 AbstractCegarLoop]: Abstraction has 209 states and 361 transitions. [2019-11-28 18:16:32,867 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-28 18:16:32,868 INFO L276 IsEmpty]: Start isEmpty. Operand 209 states and 361 transitions. [2019-11-28 18:16:32,868 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:16:32,868 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:16:32,868 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:16:32,869 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:16:32,869 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:16:32,869 INFO L82 PathProgramCache]: Analyzing trace with hash -876750572, now seen corresponding path program 3 times [2019-11-28 18:16:32,869 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:16:32,869 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [467958918] [2019-11-28 18:16:32,869 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:16:32,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:16:33,059 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:16:33,059 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [467958918] [2019-11-28 18:16:33,060 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:16:33,060 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-11-28 18:16:33,060 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1828504706] [2019-11-28 18:16:33,060 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-11-28 18:16:33,060 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:16:33,061 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-11-28 18:16:33,061 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=105, Unknown=0, NotChecked=0, Total=132 [2019-11-28 18:16:33,061 INFO L87 Difference]: Start difference. First operand 209 states and 361 transitions. Second operand 12 states. [2019-11-28 18:16:33,340 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:16:33,341 INFO L93 Difference]: Finished difference Result 360 states and 604 transitions. [2019-11-28 18:16:33,341 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-11-28 18:16:33,341 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 57 [2019-11-28 18:16:33,341 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:16:33,342 INFO L225 Difference]: With dead ends: 360 [2019-11-28 18:16:33,342 INFO L226 Difference]: Without dead ends: 327 [2019-11-28 18:16:33,343 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 43 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=60, Invalid=246, Unknown=0, NotChecked=0, Total=306 [2019-11-28 18:16:33,344 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 327 states. [2019-11-28 18:16:33,347 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 327 to 317. [2019-11-28 18:16:33,347 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 317 states. [2019-11-28 18:16:33,348 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 317 states to 317 states and 546 transitions. [2019-11-28 18:16:33,348 INFO L78 Accepts]: Start accepts. Automaton has 317 states and 546 transitions. Word has length 57 [2019-11-28 18:16:33,348 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:16:33,348 INFO L462 AbstractCegarLoop]: Abstraction has 317 states and 546 transitions. [2019-11-28 18:16:33,348 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-11-28 18:16:33,349 INFO L276 IsEmpty]: Start isEmpty. Operand 317 states and 546 transitions. [2019-11-28 18:16:33,349 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:16:33,349 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:16:33,350 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:16:33,350 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:16:33,350 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:16:33,350 INFO L82 PathProgramCache]: Analyzing trace with hash -1963724718, now seen corresponding path program 4 times [2019-11-28 18:16:33,350 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:16:33,350 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [737980638] [2019-11-28 18:16:33,351 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:16:33,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 18:16:33,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 18:16:33,472 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-28 18:16:33,472 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-28 18:16:33,476 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [749] [749] ULTIMATE.startENTRY-->L810: Formula: (let ((.cse0 (store |v_#valid_64| 0 0))) (and (= 0 v_~y$w_buff0~0_225) (= v_~x~0_72 0) (= 0 v_~y$read_delayed_var~0.offset_7) (= v_~y$r_buff0_thd1~0_30 0) (= 0 v_~__unbuffered_cnt~0_82) (= (store |v_#memory_int_22| |v_ULTIMATE.start_main_~#t1208~0.base_25| (store (select |v_#memory_int_22| |v_ULTIMATE.start_main_~#t1208~0.base_25|) |v_ULTIMATE.start_main_~#t1208~0.offset_19| 0)) |v_#memory_int_21|) (= v_~y$w_buff1_used~0_382 0) (= |v_#NULL.offset_6| 0) (= v_~y$read_delayed~0_7 0) (= (store .cse0 |v_ULTIMATE.start_main_~#t1208~0.base_25| 1) |v_#valid_62|) (= v_~__unbuffered_p2_EBX~0_120 0) (= 0 v_~y$r_buff1_thd2~0_163) (= v_~y$r_buff1_thd1~0_106 0) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t1208~0.base_25|) (< 0 |v_#StackHeapBarrier_17|) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t1208~0.base_25|)) (= v_~main$tmp_guard0~0_23 0) (= 0 v_~y$r_buff0_thd3~0_195) (= 0 |v_ULTIMATE.start_main_~#t1208~0.offset_19|) (= 0 v_~y$r_buff0_thd2~0_108) (= 0 v_~y$flush_delayed~0_58) (= 0 |v_#NULL.base_6|) (= v_~z~0_106 0) (= 0 v_~y$read_delayed_var~0.base_7) (= v_~y$w_buff1~0_183 0) (= v_~y$mem_tmp~0_20 0) (= 0 v_~__unbuffered_p2_EAX~0_120) (= v_~main$tmp_guard1~0_32 0) (= 0 v_~weak$$choice0~0_16) (= v_~a~0_45 0) (= (store |v_#length_24| |v_ULTIMATE.start_main_~#t1208~0.base_25| 4) |v_#length_23|) (= v_~y~0_155 0) (= 0 v_~y$r_buff1_thd3~0_156) (= v_~y$r_buff0_thd0~0_325 0) (= v_~weak$$choice2~0_108 0) (= v_~y$r_buff1_thd0~0_281 0) (= v_~y$w_buff0_used~0_625 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_64|, #memory_int=|v_#memory_int_22|, #length=|v_#length_24|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_37|, ULTIMATE.start_main_~#t1210~0.base=|v_ULTIMATE.start_main_~#t1210~0.base_25|, #NULL.offset=|v_#NULL.offset_6|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_22|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_28|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_45|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_26|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_45|, ~y$read_delayed~0=v_~y$read_delayed~0_7, ~a~0=v_~a~0_45, ~y$mem_tmp~0=v_~y$mem_tmp~0_20, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_156, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_30, ULTIMATE.start_main_~#t1210~0.offset=|v_ULTIMATE.start_main_~#t1210~0.offset_19|, ~y$flush_delayed~0=v_~y$flush_delayed~0_58, #length=|v_#length_23|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_120, ULTIMATE.start_main_~#t1208~0.offset=|v_ULTIMATE.start_main_~#t1208~0.offset_19|, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_120, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_26|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_30|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_24|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_37|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_38|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_48|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_68|, ~weak$$choice0~0=v_~weak$$choice0~0_16, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_26|, ~y$w_buff1~0=v_~y$w_buff1~0_183, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_7, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_108, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_8|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_22|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_82, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_281, ~x~0=v_~x~0_72, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_7, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_625, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_41|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_67|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_28|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_106|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_33|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_38|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_53|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_106, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_24|, ~y$w_buff0~0=v_~y$w_buff0~0_225, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_195, ~y~0=v_~y~0_155, ULTIMATE.start_main_~#t1209~0.offset=|v_ULTIMATE.start_main_~#t1209~0.offset_19|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_28|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_24|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_33|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_47|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_23, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_48|, ULTIMATE.start_main_~#t1209~0.base=|v_ULTIMATE.start_main_~#t1209~0.base_25|, #NULL.base=|v_#NULL.base_6|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_29|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_163, ULTIMATE.start_main_~#t1208~0.base=|v_ULTIMATE.start_main_~#t1208~0.base_25|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_36|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_19|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_325, #valid=|v_#valid_62|, #memory_int=|v_#memory_int_21|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_8|, ~z~0=v_~z~0_106, ~weak$$choice2~0=v_~weak$$choice2~0_108, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_382} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_~#t1210~0.base, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~y$read_delayed~0, ~a~0, ~y$mem_tmp~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ULTIMATE.start_main_~#t1210~0.offset, ~y$flush_delayed~0, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_~#t1208~0.offset, ~__unbuffered_p2_EBX~0, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_~#t1209~0.offset, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, ULTIMATE.start_main_~#t1209~0.base, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_~#t1208~0.base, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:16:33,477 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [718] [718] L810-1-->L812: Formula: (and (= |v_#valid_42| (store |v_#valid_43| |v_ULTIMATE.start_main_~#t1209~0.base_13| 1)) (= (store |v_#length_18| |v_ULTIMATE.start_main_~#t1209~0.base_13| 4) |v_#length_17|) (not (= |v_ULTIMATE.start_main_~#t1209~0.base_13| 0)) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1209~0.base_13|) (= 0 (select |v_#valid_43| |v_ULTIMATE.start_main_~#t1209~0.base_13|)) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1209~0.base_13| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1209~0.base_13|) |v_ULTIMATE.start_main_~#t1209~0.offset_11| 1)) |v_#memory_int_15|) (= 0 |v_ULTIMATE.start_main_~#t1209~0.offset_11|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_43|, #memory_int=|v_#memory_int_16|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t1209~0.offset=|v_ULTIMATE.start_main_~#t1209~0.offset_11|, #StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_42|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, #length=|v_#length_17|, ULTIMATE.start_main_~#t1209~0.base=|v_ULTIMATE.start_main_~#t1209~0.base_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1209~0.offset, #valid, #memory_int, ULTIMATE.start_main_#t~nondet15, #length, ULTIMATE.start_main_~#t1209~0.base] because there is no mapped edge [2019-11-28 18:16:33,478 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [717] [717] L812-1-->L814: Formula: (and (= |v_ULTIMATE.start_main_~#t1210~0.offset_11| 0) (= |v_#valid_40| (store |v_#valid_41| |v_ULTIMATE.start_main_~#t1210~0.base_13| 1)) (not (= |v_ULTIMATE.start_main_~#t1210~0.base_13| 0)) (= 0 (select |v_#valid_41| |v_ULTIMATE.start_main_~#t1210~0.base_13|)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1210~0.base_13| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1210~0.base_13|) |v_ULTIMATE.start_main_~#t1210~0.offset_11| 2)) |v_#memory_int_13|) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t1210~0.base_13|) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t1210~0.base_13| 4))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_41|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_~#t1210~0.base=|v_ULTIMATE.start_main_~#t1210~0.base_13|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_~#t1210~0.offset=|v_ULTIMATE.start_main_~#t1210~0.offset_11|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, #length=|v_#length_15|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1210~0.base, #valid, #memory_int, ULTIMATE.start_main_~#t1210~0.offset, ULTIMATE.start_main_#t~nondet16, #length] because there is no mapped edge [2019-11-28 18:16:33,478 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [634] [634] P2ENTRY-->L4-3: Formula: (and (= |v_P2Thread1of1ForFork0_#in~arg.base_12| v_P2Thread1of1ForFork0_~arg.base_10) (= |v_P2Thread1of1ForFork0_#in~arg.offset_12| v_P2Thread1of1ForFork0_~arg.offset_10) (= v_~y$w_buff0~0_33 v_~y$w_buff1~0_29) (not (= 0 v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_12)) (= v_~y$w_buff0_used~0_130 1) (= (ite (not (and (not (= (mod v_~y$w_buff0_used~0_130 256) 0)) (not (= 0 (mod v_~y$w_buff1_used~0_75 256))))) 1 0) |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_10|) (= 2 v_~y$w_buff0~0_32) (= v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_12 |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_10|) (= v_~y$w_buff1_used~0_75 v_~y$w_buff0_used~0_131)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_12|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_131, ~y$w_buff0~0=v_~y$w_buff0~0_33, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_12|} OutVars{P2Thread1of1ForFork0_~arg.base=v_P2Thread1of1ForFork0_~arg.base_10, P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_12|, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_10|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_130, ~y$w_buff1~0=v_~y$w_buff1~0_29, ~y$w_buff0~0=v_~y$w_buff0~0_32, P2Thread1of1ForFork0_~arg.offset=v_P2Thread1of1ForFork0_~arg.offset_10, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_12|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_12, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_75} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:16:33,479 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] P0ENTRY-->P0EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_71 1) v_~__unbuffered_cnt~0_70) (= 0 |v_P0Thread1of1ForFork1_#res.offset_7|) (= |v_P0Thread1of1ForFork1_#in~arg.base_15| v_P0Thread1of1ForFork1_~arg.base_13) (= v_~a~0_29 1) (= v_P0Thread1of1ForFork1_~arg.offset_13 |v_P0Thread1of1ForFork1_#in~arg.offset_15|) (= v_~x~0_52 1) (= 0 |v_P0Thread1of1ForFork1_#res.base_7|)) InVars {P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_15|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_71, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_15|} OutVars{~a~0=v_~a~0_29, P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_7|, P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_15|, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_7|, P0Thread1of1ForFork1_~arg.offset=v_P0Thread1of1ForFork1_~arg.offset_13, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_70, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_15|, ~x~0=v_~x~0_52, P0Thread1of1ForFork1_~arg.base=v_P0Thread1of1ForFork1_~arg.base_13} AuxVars[] AssignedVars[~a~0, P0Thread1of1ForFork1_#res.offset, P0Thread1of1ForFork1_#res.base, P0Thread1of1ForFork1_~arg.offset, ~__unbuffered_cnt~0, ~x~0, P0Thread1of1ForFork1_~arg.base] because there is no mapped edge [2019-11-28 18:16:33,480 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [680] [680] L788-->L788-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In617750741 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In617750741 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite11_Out617750741| 0) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= |P2Thread1of1ForFork0_#t~ite11_Out617750741| ~y$w_buff0_used~0_In617750741)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In617750741, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In617750741} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In617750741, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out617750741|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In617750741} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-11-28 18:16:33,481 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [691] [691] L789-->L789-2: Formula: (let ((.cse3 (= 0 (mod ~y$r_buff1_thd3~0_In-1979345276 256))) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In-1979345276 256))) (.cse1 (= (mod ~y$r_buff0_thd3~0_In-1979345276 256) 0)) (.cse0 (= (mod ~y$w_buff0_used~0_In-1979345276 256) 0))) (or (and (= |P2Thread1of1ForFork0_#t~ite12_Out-1979345276| ~y$w_buff1_used~0_In-1979345276) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0))) (= |P2Thread1of1ForFork0_#t~ite12_Out-1979345276| 0)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1979345276, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1979345276, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1979345276, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1979345276} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1979345276, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1979345276, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out-1979345276|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1979345276, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1979345276} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-11-28 18:16:33,481 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [683] [683] L790-->L791: Formula: (let ((.cse0 (= ~y$r_buff0_thd3~0_Out-520363234 ~y$r_buff0_thd3~0_In-520363234)) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In-520363234 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In-520363234 256)))) (or (and .cse0 .cse1) (and .cse0 .cse2) (and (= ~y$r_buff0_thd3~0_Out-520363234 0) (not .cse2) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-520363234, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-520363234} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-520363234, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out-520363234, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out-520363234|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-11-28 18:16:33,481 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [684] [684] L791-->L791-2: Formula: (let ((.cse2 (= 0 (mod ~y$w_buff1_used~0_In333289055 256))) (.cse3 (= (mod ~y$r_buff1_thd3~0_In333289055 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In333289055 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In333289055 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork0_#t~ite14_Out333289055| 0)) (and (or .cse2 .cse3) (or .cse0 .cse1) (= |P2Thread1of1ForFork0_#t~ite14_Out333289055| ~y$r_buff1_thd3~0_In333289055)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In333289055, ~y$w_buff0_used~0=~y$w_buff0_used~0_In333289055, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In333289055, ~y$w_buff1_used~0=~y$w_buff1_used~0_In333289055} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out333289055|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In333289055, ~y$w_buff0_used~0=~y$w_buff0_used~0_In333289055, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In333289055, ~y$w_buff1_used~0=~y$w_buff1_used~0_In333289055} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-11-28 18:16:33,481 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [706] [706] L791-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= v_~__unbuffered_cnt~0_54 (+ v_~__unbuffered_cnt~0_55 1)) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0) (= |v_P2Thread1of1ForFork0_#t~ite14_26| v_~y$r_buff1_thd3~0_94)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_26|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_25|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_94, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_54, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-11-28 18:16:33,482 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [698] [698] L752-2-->L752-4: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff1_thd2~0_In-28250289 256))) (.cse1 (= (mod ~y$w_buff1_used~0_In-28250289 256) 0))) (or (and (not .cse0) (= |P1Thread1of1ForFork2_#t~ite3_Out-28250289| ~y$w_buff1~0_In-28250289) (not .cse1)) (and (or .cse0 .cse1) (= |P1Thread1of1ForFork2_#t~ite3_Out-28250289| ~y~0_In-28250289)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-28250289, ~y$w_buff1~0=~y$w_buff1~0_In-28250289, ~y~0=~y~0_In-28250289, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-28250289} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-28250289, ~y$w_buff1~0=~y$w_buff1~0_In-28250289, ~y~0=~y~0_In-28250289, P1Thread1of1ForFork2_#t~ite3=|P1Thread1of1ForFork2_#t~ite3_Out-28250289|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-28250289} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-11-28 18:16:33,482 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [629] [629] L752-4-->L753: Formula: (= v_~y~0_39 |v_P1Thread1of1ForFork2_#t~ite3_6|) InVars {P1Thread1of1ForFork2_#t~ite3=|v_P1Thread1of1ForFork2_#t~ite3_6|} OutVars{P1Thread1of1ForFork2_#t~ite4=|v_P1Thread1of1ForFork2_#t~ite4_7|, ~y~0=v_~y~0_39, P1Thread1of1ForFork2_#t~ite3=|v_P1Thread1of1ForFork2_#t~ite3_5|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite4, ~y~0, P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-11-28 18:16:33,482 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [681] [681] L753-->L753-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In-929564192 256))) (.cse0 (= (mod ~y$w_buff0_used~0_In-929564192 256) 0))) (or (and (= 0 |P1Thread1of1ForFork2_#t~ite5_Out-929564192|) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= ~y$w_buff0_used~0_In-929564192 |P1Thread1of1ForFork2_#t~ite5_Out-929564192|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-929564192, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-929564192} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-929564192, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-929564192, P1Thread1of1ForFork2_#t~ite5=|P1Thread1of1ForFork2_#t~ite5_Out-929564192|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-11-28 18:16:33,483 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L754-->L754-2: Formula: (let ((.cse0 (= (mod ~y$w_buff1_used~0_In965768522 256) 0)) (.cse1 (= (mod ~y$r_buff1_thd2~0_In965768522 256) 0)) (.cse3 (= 0 (mod ~y$w_buff0_used~0_In965768522 256))) (.cse2 (= 0 (mod ~y$r_buff0_thd2~0_In965768522 256)))) (or (and (= 0 |P1Thread1of1ForFork2_#t~ite6_Out965768522|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |P1Thread1of1ForFork2_#t~ite6_Out965768522| ~y$w_buff1_used~0_In965768522) (or .cse0 .cse1) (or .cse3 .cse2)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In965768522, ~y$w_buff0_used~0=~y$w_buff0_used~0_In965768522, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In965768522, ~y$w_buff1_used~0=~y$w_buff1_used~0_In965768522} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In965768522, ~y$w_buff0_used~0=~y$w_buff0_used~0_In965768522, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In965768522, P1Thread1of1ForFork2_#t~ite6=|P1Thread1of1ForFork2_#t~ite6_Out965768522|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In965768522} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-11-28 18:16:33,483 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [696] [696] L755-->L755-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In-1261772594 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-1261772594 256)))) (or (and (= 0 |P1Thread1of1ForFork2_#t~ite7_Out-1261772594|) (not .cse0) (not .cse1)) (and (= ~y$r_buff0_thd2~0_In-1261772594 |P1Thread1of1ForFork2_#t~ite7_Out-1261772594|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1261772594, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1261772594} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1261772594, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1261772594, P1Thread1of1ForFork2_#t~ite7=|P1Thread1of1ForFork2_#t~ite7_Out-1261772594|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-11-28 18:16:33,484 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [688] [688] L756-->L756-2: Formula: (let ((.cse2 (= (mod ~y$r_buff1_thd2~0_In329483848 256) 0)) (.cse3 (= (mod ~y$w_buff1_used~0_In329483848 256) 0)) (.cse0 (= (mod ~y$w_buff0_used~0_In329483848 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In329483848 256)))) (or (and (= |P1Thread1of1ForFork2_#t~ite8_Out329483848| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |P1Thread1of1ForFork2_#t~ite8_Out329483848| ~y$r_buff1_thd2~0_In329483848) (or .cse2 .cse3) (or .cse0 .cse1)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In329483848, ~y$w_buff0_used~0=~y$w_buff0_used~0_In329483848, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In329483848, ~y$w_buff1_used~0=~y$w_buff1_used~0_In329483848} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In329483848, ~y$w_buff0_used~0=~y$w_buff0_used~0_In329483848, P1Thread1of1ForFork2_#t~ite8=|P1Thread1of1ForFork2_#t~ite8_Out329483848|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In329483848, ~y$w_buff1_used~0=~y$w_buff1_used~0_In329483848} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-11-28 18:16:33,484 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [713] [713] L756-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_61 1) v_~__unbuffered_cnt~0_60) (= |v_P1Thread1of1ForFork2_#t~ite8_28| v_~y$r_buff1_thd2~0_111)) InVars {P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_28|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_61} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_111, P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_27|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_60, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork2_#res.offset, P1Thread1of1ForFork2_#t~ite8, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-11-28 18:16:33,484 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [661] [661] L814-1-->L820: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_11 256))) (= v_~main$tmp_guard0~0_11 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_28) 1 0) 0) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_28} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_28, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_10|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_11} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet17, ~main$tmp_guard0~0] because there is no mapped edge [2019-11-28 18:16:33,484 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [690] [690] L820-2-->L820-5: Formula: (let ((.cse0 (= |ULTIMATE.start_main_#t~ite19_Out-1833701866| |ULTIMATE.start_main_#t~ite18_Out-1833701866|)) (.cse2 (= 0 (mod ~y$r_buff1_thd0~0_In-1833701866 256))) (.cse1 (= (mod ~y$w_buff1_used~0_In-1833701866 256) 0))) (or (and .cse0 (or .cse1 .cse2) (= ~y~0_In-1833701866 |ULTIMATE.start_main_#t~ite18_Out-1833701866|)) (and .cse0 (= ~y$w_buff1~0_In-1833701866 |ULTIMATE.start_main_#t~ite18_Out-1833701866|) (not .cse2) (not .cse1)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-1833701866, ~y~0=~y~0_In-1833701866, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1833701866, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1833701866} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-1833701866, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out-1833701866|, ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out-1833701866|, ~y~0=~y~0_In-1833701866, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1833701866, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1833701866} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-11-28 18:16:33,485 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [689] [689] L821-->L821-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In1825762319 256))) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In1825762319 256)))) (or (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite20_Out1825762319|)) (and (= ~y$w_buff0_used~0_In1825762319 |ULTIMATE.start_main_#t~ite20_Out1825762319|) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1825762319, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1825762319} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1825762319, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1825762319, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out1825762319|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-11-28 18:16:33,486 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [695] [695] L822-->L822-2: Formula: (let ((.cse0 (= (mod ~y$r_buff1_thd0~0_In1161852877 256) 0)) (.cse1 (= (mod ~y$w_buff1_used~0_In1161852877 256) 0)) (.cse3 (= (mod ~y$w_buff0_used~0_In1161852877 256) 0)) (.cse2 (= (mod ~y$r_buff0_thd0~0_In1161852877 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite21_Out1161852877|)) (and (or .cse0 .cse1) (or .cse3 .cse2) (= ~y$w_buff1_used~0_In1161852877 |ULTIMATE.start_main_#t~ite21_Out1161852877|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1161852877, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1161852877, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1161852877, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1161852877} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1161852877, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1161852877, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out1161852877|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1161852877, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1161852877} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-11-28 18:16:33,486 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [678] [678] L823-->L823-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-568231170 256) 0)) (.cse0 (= (mod ~y$r_buff0_thd0~0_In-568231170 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite22_Out-568231170| ~y$r_buff0_thd0~0_In-568231170) (or .cse0 .cse1)) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite22_Out-568231170| 0) (not .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-568231170, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-568231170} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-568231170, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-568231170, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out-568231170|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-11-28 18:16:33,487 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [687] [687] L824-->L824-2: Formula: (let ((.cse1 (= (mod ~y$w_buff1_used~0_In117435581 256) 0)) (.cse0 (= (mod ~y$r_buff1_thd0~0_In117435581 256) 0)) (.cse2 (= (mod ~y$w_buff0_used~0_In117435581 256) 0)) (.cse3 (= (mod ~y$r_buff0_thd0~0_In117435581 256) 0))) (or (and (= 0 |ULTIMATE.start_main_#t~ite23_Out117435581|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~y$r_buff1_thd0~0_In117435581 |ULTIMATE.start_main_#t~ite23_Out117435581|) (or .cse1 .cse0) (or .cse2 .cse3)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In117435581, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In117435581, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In117435581, ~y$w_buff1_used~0=~y$w_buff1_used~0_In117435581} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In117435581, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In117435581, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In117435581, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out117435581|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In117435581} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-11-28 18:16:33,489 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [733] [733] L833-->L833-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In1490883923 256) 0))) (or (and (= ~y$w_buff1~0_In1490883923 |ULTIMATE.start_main_#t~ite33_Out1490883923|) (= |ULTIMATE.start_main_#t~ite32_In1490883923| |ULTIMATE.start_main_#t~ite32_Out1490883923|) (not .cse0)) (and (= ~y$w_buff1~0_In1490883923 |ULTIMATE.start_main_#t~ite32_Out1490883923|) (= |ULTIMATE.start_main_#t~ite33_Out1490883923| |ULTIMATE.start_main_#t~ite32_Out1490883923|) (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In1490883923 256)))) (or (and (= 0 (mod ~y$w_buff1_used~0_In1490883923 256)) .cse1) (and (= 0 (mod ~y$r_buff1_thd0~0_In1490883923 256)) .cse1) (= (mod ~y$w_buff0_used~0_In1490883923 256) 0))) .cse0))) InVars {~y$w_buff1~0=~y$w_buff1~0_In1490883923, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1490883923, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1490883923, ~weak$$choice2~0=~weak$$choice2~0_In1490883923, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1490883923, ULTIMATE.start_main_#t~ite32=|ULTIMATE.start_main_#t~ite32_In1490883923|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1490883923} OutVars{~y$w_buff1~0=~y$w_buff1~0_In1490883923, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1490883923, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1490883923, ~weak$$choice2~0=~weak$$choice2~0_In1490883923, ULTIMATE.start_main_#t~ite32=|ULTIMATE.start_main_#t~ite32_Out1490883923|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1490883923, ULTIMATE.start_main_#t~ite33=|ULTIMATE.start_main_#t~ite33_Out1490883923|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1490883923} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite32, ULTIMATE.start_main_#t~ite33] because there is no mapped edge [2019-11-28 18:16:33,489 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [734] [734] L834-->L834-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In667456928 256)))) (or (and .cse0 (= |ULTIMATE.start_main_#t~ite35_Out667456928| ~y$w_buff0_used~0_In667456928) (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In667456928 256)))) (or (= 0 (mod ~y$w_buff0_used~0_In667456928 256)) (and (= 0 (mod ~y$r_buff1_thd0~0_In667456928 256)) .cse1) (and (= 0 (mod ~y$w_buff1_used~0_In667456928 256)) .cse1))) (= |ULTIMATE.start_main_#t~ite35_Out667456928| |ULTIMATE.start_main_#t~ite36_Out667456928|)) (and (= ~y$w_buff0_used~0_In667456928 |ULTIMATE.start_main_#t~ite36_Out667456928|) (not .cse0) (= |ULTIMATE.start_main_#t~ite35_In667456928| |ULTIMATE.start_main_#t~ite35_Out667456928|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In667456928, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In667456928, ULTIMATE.start_main_#t~ite35=|ULTIMATE.start_main_#t~ite35_In667456928|, ~weak$$choice2~0=~weak$$choice2~0_In667456928, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In667456928, ~y$w_buff1_used~0=~y$w_buff1_used~0_In667456928} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In667456928, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In667456928, ULTIMATE.start_main_#t~ite35=|ULTIMATE.start_main_#t~ite35_Out667456928|, ULTIMATE.start_main_#t~ite36=|ULTIMATE.start_main_#t~ite36_Out667456928|, ~weak$$choice2~0=~weak$$choice2~0_In667456928, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In667456928, ~y$w_buff1_used~0=~y$w_buff1_used~0_In667456928} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite36] because there is no mapped edge [2019-11-28 18:16:33,490 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [732] [732] L835-->L835-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In1394441445 256) 0))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite38_In1394441445| |ULTIMATE.start_main_#t~ite38_Out1394441445|) (= |ULTIMATE.start_main_#t~ite39_Out1394441445| ~y$w_buff1_used~0_In1394441445)) (and (= |ULTIMATE.start_main_#t~ite38_Out1394441445| ~y$w_buff1_used~0_In1394441445) (= |ULTIMATE.start_main_#t~ite38_Out1394441445| |ULTIMATE.start_main_#t~ite39_Out1394441445|) (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In1394441445 256) 0))) (or (and (= 0 (mod ~y$w_buff1_used~0_In1394441445 256)) .cse1) (and (= 0 (mod ~y$r_buff1_thd0~0_In1394441445 256)) .cse1) (= (mod ~y$w_buff0_used~0_In1394441445 256) 0))) .cse0))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1394441445, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1394441445, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_In1394441445|, ~weak$$choice2~0=~weak$$choice2~0_In1394441445, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1394441445, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1394441445} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1394441445, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out1394441445|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1394441445, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_Out1394441445|, ~weak$$choice2~0=~weak$$choice2~0_In1394441445, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1394441445, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1394441445} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite38] because there is no mapped edge [2019-11-28 18:16:33,490 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [665] [665] L836-->L837: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_29 256))) (= v_~y$r_buff0_thd0~0_100 v_~y$r_buff0_thd0~0_99)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_100, ~weak$$choice2~0=v_~weak$$choice2~0_29} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_13|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_8|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_99, ~weak$$choice2~0=v_~weak$$choice2~0_29, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-11-28 18:16:33,491 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [731] [731] L839-->L4: Formula: (and (= v_~y~0_138 v_~y$mem_tmp~0_17) (= (mod v_~main$tmp_guard1~0_23 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|) (= 0 v_~y$flush_delayed~0_52) (not (= (mod v_~y$flush_delayed~0_53 256) 0))) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_17, ~y$flush_delayed~0=v_~y$flush_delayed~0_53, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_23} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_17, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_12, ~y$flush_delayed~0=v_~y$flush_delayed~0_52, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_60|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_23, ~y~0=v_~y~0_138, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ~y$flush_delayed~0, ULTIMATE.start_main_#t~ite46, ~y~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-11-28 18:16:33,491 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [726] [726] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-11-28 18:16:33,571 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 06:16:33 BasicIcfg [2019-11-28 18:16:33,571 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-28 18:16:33,573 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-28 18:16:33,573 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-28 18:16:33,573 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-28 18:16:33,574 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:16:17" (3/4) ... [2019-11-28 18:16:33,576 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-28 18:16:33,577 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [749] [749] ULTIMATE.startENTRY-->L810: Formula: (let ((.cse0 (store |v_#valid_64| 0 0))) (and (= 0 v_~y$w_buff0~0_225) (= v_~x~0_72 0) (= 0 v_~y$read_delayed_var~0.offset_7) (= v_~y$r_buff0_thd1~0_30 0) (= 0 v_~__unbuffered_cnt~0_82) (= (store |v_#memory_int_22| |v_ULTIMATE.start_main_~#t1208~0.base_25| (store (select |v_#memory_int_22| |v_ULTIMATE.start_main_~#t1208~0.base_25|) |v_ULTIMATE.start_main_~#t1208~0.offset_19| 0)) |v_#memory_int_21|) (= v_~y$w_buff1_used~0_382 0) (= |v_#NULL.offset_6| 0) (= v_~y$read_delayed~0_7 0) (= (store .cse0 |v_ULTIMATE.start_main_~#t1208~0.base_25| 1) |v_#valid_62|) (= v_~__unbuffered_p2_EBX~0_120 0) (= 0 v_~y$r_buff1_thd2~0_163) (= v_~y$r_buff1_thd1~0_106 0) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t1208~0.base_25|) (< 0 |v_#StackHeapBarrier_17|) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t1208~0.base_25|)) (= v_~main$tmp_guard0~0_23 0) (= 0 v_~y$r_buff0_thd3~0_195) (= 0 |v_ULTIMATE.start_main_~#t1208~0.offset_19|) (= 0 v_~y$r_buff0_thd2~0_108) (= 0 v_~y$flush_delayed~0_58) (= 0 |v_#NULL.base_6|) (= v_~z~0_106 0) (= 0 v_~y$read_delayed_var~0.base_7) (= v_~y$w_buff1~0_183 0) (= v_~y$mem_tmp~0_20 0) (= 0 v_~__unbuffered_p2_EAX~0_120) (= v_~main$tmp_guard1~0_32 0) (= 0 v_~weak$$choice0~0_16) (= v_~a~0_45 0) (= (store |v_#length_24| |v_ULTIMATE.start_main_~#t1208~0.base_25| 4) |v_#length_23|) (= v_~y~0_155 0) (= 0 v_~y$r_buff1_thd3~0_156) (= v_~y$r_buff0_thd0~0_325 0) (= v_~weak$$choice2~0_108 0) (= v_~y$r_buff1_thd0~0_281 0) (= v_~y$w_buff0_used~0_625 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_64|, #memory_int=|v_#memory_int_22|, #length=|v_#length_24|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_37|, ULTIMATE.start_main_~#t1210~0.base=|v_ULTIMATE.start_main_~#t1210~0.base_25|, #NULL.offset=|v_#NULL.offset_6|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_22|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_28|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_45|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_26|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_45|, ~y$read_delayed~0=v_~y$read_delayed~0_7, ~a~0=v_~a~0_45, ~y$mem_tmp~0=v_~y$mem_tmp~0_20, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_156, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_30, ULTIMATE.start_main_~#t1210~0.offset=|v_ULTIMATE.start_main_~#t1210~0.offset_19|, ~y$flush_delayed~0=v_~y$flush_delayed~0_58, #length=|v_#length_23|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_120, ULTIMATE.start_main_~#t1208~0.offset=|v_ULTIMATE.start_main_~#t1208~0.offset_19|, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_120, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_26|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_30|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_24|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_37|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_38|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_48|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_68|, ~weak$$choice0~0=v_~weak$$choice0~0_16, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_26|, ~y$w_buff1~0=v_~y$w_buff1~0_183, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_7, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_108, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_8|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_22|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_82, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_281, ~x~0=v_~x~0_72, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_7, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_625, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_41|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_67|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_28|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_106|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_33|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_38|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_53|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_106, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_24|, ~y$w_buff0~0=v_~y$w_buff0~0_225, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_195, ~y~0=v_~y~0_155, ULTIMATE.start_main_~#t1209~0.offset=|v_ULTIMATE.start_main_~#t1209~0.offset_19|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_28|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_24|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_33|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_47|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_23, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_48|, ULTIMATE.start_main_~#t1209~0.base=|v_ULTIMATE.start_main_~#t1209~0.base_25|, #NULL.base=|v_#NULL.base_6|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_29|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_163, ULTIMATE.start_main_~#t1208~0.base=|v_ULTIMATE.start_main_~#t1208~0.base_25|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_36|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_19|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_325, #valid=|v_#valid_62|, #memory_int=|v_#memory_int_21|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_8|, ~z~0=v_~z~0_106, ~weak$$choice2~0=v_~weak$$choice2~0_108, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_382} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_~#t1210~0.base, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~y$read_delayed~0, ~a~0, ~y$mem_tmp~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ULTIMATE.start_main_~#t1210~0.offset, ~y$flush_delayed~0, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_~#t1208~0.offset, ~__unbuffered_p2_EBX~0, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_~#t1209~0.offset, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, ULTIMATE.start_main_~#t1209~0.base, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_~#t1208~0.base, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:16:33,577 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [718] [718] L810-1-->L812: Formula: (and (= |v_#valid_42| (store |v_#valid_43| |v_ULTIMATE.start_main_~#t1209~0.base_13| 1)) (= (store |v_#length_18| |v_ULTIMATE.start_main_~#t1209~0.base_13| 4) |v_#length_17|) (not (= |v_ULTIMATE.start_main_~#t1209~0.base_13| 0)) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1209~0.base_13|) (= 0 (select |v_#valid_43| |v_ULTIMATE.start_main_~#t1209~0.base_13|)) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1209~0.base_13| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1209~0.base_13|) |v_ULTIMATE.start_main_~#t1209~0.offset_11| 1)) |v_#memory_int_15|) (= 0 |v_ULTIMATE.start_main_~#t1209~0.offset_11|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_43|, #memory_int=|v_#memory_int_16|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t1209~0.offset=|v_ULTIMATE.start_main_~#t1209~0.offset_11|, #StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_42|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, #length=|v_#length_17|, ULTIMATE.start_main_~#t1209~0.base=|v_ULTIMATE.start_main_~#t1209~0.base_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1209~0.offset, #valid, #memory_int, ULTIMATE.start_main_#t~nondet15, #length, ULTIMATE.start_main_~#t1209~0.base] because there is no mapped edge [2019-11-28 18:16:33,578 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [717] [717] L812-1-->L814: Formula: (and (= |v_ULTIMATE.start_main_~#t1210~0.offset_11| 0) (= |v_#valid_40| (store |v_#valid_41| |v_ULTIMATE.start_main_~#t1210~0.base_13| 1)) (not (= |v_ULTIMATE.start_main_~#t1210~0.base_13| 0)) (= 0 (select |v_#valid_41| |v_ULTIMATE.start_main_~#t1210~0.base_13|)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1210~0.base_13| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1210~0.base_13|) |v_ULTIMATE.start_main_~#t1210~0.offset_11| 2)) |v_#memory_int_13|) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t1210~0.base_13|) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t1210~0.base_13| 4))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_41|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_~#t1210~0.base=|v_ULTIMATE.start_main_~#t1210~0.base_13|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_~#t1210~0.offset=|v_ULTIMATE.start_main_~#t1210~0.offset_11|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, #length=|v_#length_15|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1210~0.base, #valid, #memory_int, ULTIMATE.start_main_~#t1210~0.offset, ULTIMATE.start_main_#t~nondet16, #length] because there is no mapped edge [2019-11-28 18:16:33,578 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [634] [634] P2ENTRY-->L4-3: Formula: (and (= |v_P2Thread1of1ForFork0_#in~arg.base_12| v_P2Thread1of1ForFork0_~arg.base_10) (= |v_P2Thread1of1ForFork0_#in~arg.offset_12| v_P2Thread1of1ForFork0_~arg.offset_10) (= v_~y$w_buff0~0_33 v_~y$w_buff1~0_29) (not (= 0 v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_12)) (= v_~y$w_buff0_used~0_130 1) (= (ite (not (and (not (= (mod v_~y$w_buff0_used~0_130 256) 0)) (not (= 0 (mod v_~y$w_buff1_used~0_75 256))))) 1 0) |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_10|) (= 2 v_~y$w_buff0~0_32) (= v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_12 |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_10|) (= v_~y$w_buff1_used~0_75 v_~y$w_buff0_used~0_131)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_12|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_131, ~y$w_buff0~0=v_~y$w_buff0~0_33, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_12|} OutVars{P2Thread1of1ForFork0_~arg.base=v_P2Thread1of1ForFork0_~arg.base_10, P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_12|, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_10|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_130, ~y$w_buff1~0=v_~y$w_buff1~0_29, ~y$w_buff0~0=v_~y$w_buff0~0_32, P2Thread1of1ForFork0_~arg.offset=v_P2Thread1of1ForFork0_~arg.offset_10, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_12|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_12, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_75} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:16:33,579 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] P0ENTRY-->P0EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_71 1) v_~__unbuffered_cnt~0_70) (= 0 |v_P0Thread1of1ForFork1_#res.offset_7|) (= |v_P0Thread1of1ForFork1_#in~arg.base_15| v_P0Thread1of1ForFork1_~arg.base_13) (= v_~a~0_29 1) (= v_P0Thread1of1ForFork1_~arg.offset_13 |v_P0Thread1of1ForFork1_#in~arg.offset_15|) (= v_~x~0_52 1) (= 0 |v_P0Thread1of1ForFork1_#res.base_7|)) InVars {P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_15|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_71, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_15|} OutVars{~a~0=v_~a~0_29, P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_7|, P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_15|, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_7|, P0Thread1of1ForFork1_~arg.offset=v_P0Thread1of1ForFork1_~arg.offset_13, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_70, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_15|, ~x~0=v_~x~0_52, P0Thread1of1ForFork1_~arg.base=v_P0Thread1of1ForFork1_~arg.base_13} AuxVars[] AssignedVars[~a~0, P0Thread1of1ForFork1_#res.offset, P0Thread1of1ForFork1_#res.base, P0Thread1of1ForFork1_~arg.offset, ~__unbuffered_cnt~0, ~x~0, P0Thread1of1ForFork1_~arg.base] because there is no mapped edge [2019-11-28 18:16:33,580 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [680] [680] L788-->L788-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In617750741 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In617750741 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite11_Out617750741| 0) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= |P2Thread1of1ForFork0_#t~ite11_Out617750741| ~y$w_buff0_used~0_In617750741)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In617750741, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In617750741} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In617750741, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out617750741|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In617750741} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-11-28 18:16:33,581 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [691] [691] L789-->L789-2: Formula: (let ((.cse3 (= 0 (mod ~y$r_buff1_thd3~0_In-1979345276 256))) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In-1979345276 256))) (.cse1 (= (mod ~y$r_buff0_thd3~0_In-1979345276 256) 0)) (.cse0 (= (mod ~y$w_buff0_used~0_In-1979345276 256) 0))) (or (and (= |P2Thread1of1ForFork0_#t~ite12_Out-1979345276| ~y$w_buff1_used~0_In-1979345276) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0))) (= |P2Thread1of1ForFork0_#t~ite12_Out-1979345276| 0)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1979345276, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1979345276, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1979345276, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1979345276} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1979345276, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1979345276, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out-1979345276|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1979345276, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1979345276} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-11-28 18:16:33,581 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [683] [683] L790-->L791: Formula: (let ((.cse0 (= ~y$r_buff0_thd3~0_Out-520363234 ~y$r_buff0_thd3~0_In-520363234)) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In-520363234 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In-520363234 256)))) (or (and .cse0 .cse1) (and .cse0 .cse2) (and (= ~y$r_buff0_thd3~0_Out-520363234 0) (not .cse2) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-520363234, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-520363234} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-520363234, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out-520363234, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out-520363234|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-11-28 18:16:33,581 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [684] [684] L791-->L791-2: Formula: (let ((.cse2 (= 0 (mod ~y$w_buff1_used~0_In333289055 256))) (.cse3 (= (mod ~y$r_buff1_thd3~0_In333289055 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In333289055 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In333289055 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork0_#t~ite14_Out333289055| 0)) (and (or .cse2 .cse3) (or .cse0 .cse1) (= |P2Thread1of1ForFork0_#t~ite14_Out333289055| ~y$r_buff1_thd3~0_In333289055)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In333289055, ~y$w_buff0_used~0=~y$w_buff0_used~0_In333289055, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In333289055, ~y$w_buff1_used~0=~y$w_buff1_used~0_In333289055} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out333289055|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In333289055, ~y$w_buff0_used~0=~y$w_buff0_used~0_In333289055, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In333289055, ~y$w_buff1_used~0=~y$w_buff1_used~0_In333289055} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-11-28 18:16:33,581 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [706] [706] L791-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= v_~__unbuffered_cnt~0_54 (+ v_~__unbuffered_cnt~0_55 1)) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0) (= |v_P2Thread1of1ForFork0_#t~ite14_26| v_~y$r_buff1_thd3~0_94)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_26|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_25|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_94, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_54, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-11-28 18:16:33,582 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [698] [698] L752-2-->L752-4: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff1_thd2~0_In-28250289 256))) (.cse1 (= (mod ~y$w_buff1_used~0_In-28250289 256) 0))) (or (and (not .cse0) (= |P1Thread1of1ForFork2_#t~ite3_Out-28250289| ~y$w_buff1~0_In-28250289) (not .cse1)) (and (or .cse0 .cse1) (= |P1Thread1of1ForFork2_#t~ite3_Out-28250289| ~y~0_In-28250289)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-28250289, ~y$w_buff1~0=~y$w_buff1~0_In-28250289, ~y~0=~y~0_In-28250289, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-28250289} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-28250289, ~y$w_buff1~0=~y$w_buff1~0_In-28250289, ~y~0=~y~0_In-28250289, P1Thread1of1ForFork2_#t~ite3=|P1Thread1of1ForFork2_#t~ite3_Out-28250289|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-28250289} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-11-28 18:16:33,582 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [629] [629] L752-4-->L753: Formula: (= v_~y~0_39 |v_P1Thread1of1ForFork2_#t~ite3_6|) InVars {P1Thread1of1ForFork2_#t~ite3=|v_P1Thread1of1ForFork2_#t~ite3_6|} OutVars{P1Thread1of1ForFork2_#t~ite4=|v_P1Thread1of1ForFork2_#t~ite4_7|, ~y~0=v_~y~0_39, P1Thread1of1ForFork2_#t~ite3=|v_P1Thread1of1ForFork2_#t~ite3_5|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite4, ~y~0, P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-11-28 18:16:33,582 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [681] [681] L753-->L753-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In-929564192 256))) (.cse0 (= (mod ~y$w_buff0_used~0_In-929564192 256) 0))) (or (and (= 0 |P1Thread1of1ForFork2_#t~ite5_Out-929564192|) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= ~y$w_buff0_used~0_In-929564192 |P1Thread1of1ForFork2_#t~ite5_Out-929564192|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-929564192, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-929564192} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-929564192, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-929564192, P1Thread1of1ForFork2_#t~ite5=|P1Thread1of1ForFork2_#t~ite5_Out-929564192|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-11-28 18:16:33,583 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L754-->L754-2: Formula: (let ((.cse0 (= (mod ~y$w_buff1_used~0_In965768522 256) 0)) (.cse1 (= (mod ~y$r_buff1_thd2~0_In965768522 256) 0)) (.cse3 (= 0 (mod ~y$w_buff0_used~0_In965768522 256))) (.cse2 (= 0 (mod ~y$r_buff0_thd2~0_In965768522 256)))) (or (and (= 0 |P1Thread1of1ForFork2_#t~ite6_Out965768522|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |P1Thread1of1ForFork2_#t~ite6_Out965768522| ~y$w_buff1_used~0_In965768522) (or .cse0 .cse1) (or .cse3 .cse2)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In965768522, ~y$w_buff0_used~0=~y$w_buff0_used~0_In965768522, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In965768522, ~y$w_buff1_used~0=~y$w_buff1_used~0_In965768522} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In965768522, ~y$w_buff0_used~0=~y$w_buff0_used~0_In965768522, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In965768522, P1Thread1of1ForFork2_#t~ite6=|P1Thread1of1ForFork2_#t~ite6_Out965768522|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In965768522} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-11-28 18:16:33,583 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [696] [696] L755-->L755-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In-1261772594 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-1261772594 256)))) (or (and (= 0 |P1Thread1of1ForFork2_#t~ite7_Out-1261772594|) (not .cse0) (not .cse1)) (and (= ~y$r_buff0_thd2~0_In-1261772594 |P1Thread1of1ForFork2_#t~ite7_Out-1261772594|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1261772594, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1261772594} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1261772594, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1261772594, P1Thread1of1ForFork2_#t~ite7=|P1Thread1of1ForFork2_#t~ite7_Out-1261772594|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-11-28 18:16:33,584 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [688] [688] L756-->L756-2: Formula: (let ((.cse2 (= (mod ~y$r_buff1_thd2~0_In329483848 256) 0)) (.cse3 (= (mod ~y$w_buff1_used~0_In329483848 256) 0)) (.cse0 (= (mod ~y$w_buff0_used~0_In329483848 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In329483848 256)))) (or (and (= |P1Thread1of1ForFork2_#t~ite8_Out329483848| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |P1Thread1of1ForFork2_#t~ite8_Out329483848| ~y$r_buff1_thd2~0_In329483848) (or .cse2 .cse3) (or .cse0 .cse1)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In329483848, ~y$w_buff0_used~0=~y$w_buff0_used~0_In329483848, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In329483848, ~y$w_buff1_used~0=~y$w_buff1_used~0_In329483848} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In329483848, ~y$w_buff0_used~0=~y$w_buff0_used~0_In329483848, P1Thread1of1ForFork2_#t~ite8=|P1Thread1of1ForFork2_#t~ite8_Out329483848|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In329483848, ~y$w_buff1_used~0=~y$w_buff1_used~0_In329483848} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-11-28 18:16:33,584 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [713] [713] L756-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_61 1) v_~__unbuffered_cnt~0_60) (= |v_P1Thread1of1ForFork2_#t~ite8_28| v_~y$r_buff1_thd2~0_111)) InVars {P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_28|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_61} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_111, P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_27|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_60, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork2_#res.offset, P1Thread1of1ForFork2_#t~ite8, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-11-28 18:16:33,584 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [661] [661] L814-1-->L820: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_11 256))) (= v_~main$tmp_guard0~0_11 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_28) 1 0) 0) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_28} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_28, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_10|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_11} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet17, ~main$tmp_guard0~0] because there is no mapped edge [2019-11-28 18:16:33,585 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [690] [690] L820-2-->L820-5: Formula: (let ((.cse0 (= |ULTIMATE.start_main_#t~ite19_Out-1833701866| |ULTIMATE.start_main_#t~ite18_Out-1833701866|)) (.cse2 (= 0 (mod ~y$r_buff1_thd0~0_In-1833701866 256))) (.cse1 (= (mod ~y$w_buff1_used~0_In-1833701866 256) 0))) (or (and .cse0 (or .cse1 .cse2) (= ~y~0_In-1833701866 |ULTIMATE.start_main_#t~ite18_Out-1833701866|)) (and .cse0 (= ~y$w_buff1~0_In-1833701866 |ULTIMATE.start_main_#t~ite18_Out-1833701866|) (not .cse2) (not .cse1)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-1833701866, ~y~0=~y~0_In-1833701866, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1833701866, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1833701866} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-1833701866, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out-1833701866|, ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out-1833701866|, ~y~0=~y~0_In-1833701866, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1833701866, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1833701866} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-11-28 18:16:33,585 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [689] [689] L821-->L821-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In1825762319 256))) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In1825762319 256)))) (or (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite20_Out1825762319|)) (and (= ~y$w_buff0_used~0_In1825762319 |ULTIMATE.start_main_#t~ite20_Out1825762319|) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1825762319, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1825762319} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1825762319, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1825762319, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out1825762319|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-11-28 18:16:33,586 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [695] [695] L822-->L822-2: Formula: (let ((.cse0 (= (mod ~y$r_buff1_thd0~0_In1161852877 256) 0)) (.cse1 (= (mod ~y$w_buff1_used~0_In1161852877 256) 0)) (.cse3 (= (mod ~y$w_buff0_used~0_In1161852877 256) 0)) (.cse2 (= (mod ~y$r_buff0_thd0~0_In1161852877 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite21_Out1161852877|)) (and (or .cse0 .cse1) (or .cse3 .cse2) (= ~y$w_buff1_used~0_In1161852877 |ULTIMATE.start_main_#t~ite21_Out1161852877|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1161852877, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1161852877, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1161852877, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1161852877} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1161852877, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1161852877, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out1161852877|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1161852877, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1161852877} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-11-28 18:16:33,586 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [678] [678] L823-->L823-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-568231170 256) 0)) (.cse0 (= (mod ~y$r_buff0_thd0~0_In-568231170 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite22_Out-568231170| ~y$r_buff0_thd0~0_In-568231170) (or .cse0 .cse1)) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite22_Out-568231170| 0) (not .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-568231170, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-568231170} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-568231170, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-568231170, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out-568231170|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-11-28 18:16:33,587 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [687] [687] L824-->L824-2: Formula: (let ((.cse1 (= (mod ~y$w_buff1_used~0_In117435581 256) 0)) (.cse0 (= (mod ~y$r_buff1_thd0~0_In117435581 256) 0)) (.cse2 (= (mod ~y$w_buff0_used~0_In117435581 256) 0)) (.cse3 (= (mod ~y$r_buff0_thd0~0_In117435581 256) 0))) (or (and (= 0 |ULTIMATE.start_main_#t~ite23_Out117435581|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~y$r_buff1_thd0~0_In117435581 |ULTIMATE.start_main_#t~ite23_Out117435581|) (or .cse1 .cse0) (or .cse2 .cse3)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In117435581, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In117435581, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In117435581, ~y$w_buff1_used~0=~y$w_buff1_used~0_In117435581} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In117435581, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In117435581, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In117435581, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out117435581|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In117435581} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-11-28 18:16:33,589 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [733] [733] L833-->L833-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In1490883923 256) 0))) (or (and (= ~y$w_buff1~0_In1490883923 |ULTIMATE.start_main_#t~ite33_Out1490883923|) (= |ULTIMATE.start_main_#t~ite32_In1490883923| |ULTIMATE.start_main_#t~ite32_Out1490883923|) (not .cse0)) (and (= ~y$w_buff1~0_In1490883923 |ULTIMATE.start_main_#t~ite32_Out1490883923|) (= |ULTIMATE.start_main_#t~ite33_Out1490883923| |ULTIMATE.start_main_#t~ite32_Out1490883923|) (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In1490883923 256)))) (or (and (= 0 (mod ~y$w_buff1_used~0_In1490883923 256)) .cse1) (and (= 0 (mod ~y$r_buff1_thd0~0_In1490883923 256)) .cse1) (= (mod ~y$w_buff0_used~0_In1490883923 256) 0))) .cse0))) InVars {~y$w_buff1~0=~y$w_buff1~0_In1490883923, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1490883923, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1490883923, ~weak$$choice2~0=~weak$$choice2~0_In1490883923, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1490883923, ULTIMATE.start_main_#t~ite32=|ULTIMATE.start_main_#t~ite32_In1490883923|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1490883923} OutVars{~y$w_buff1~0=~y$w_buff1~0_In1490883923, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1490883923, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1490883923, ~weak$$choice2~0=~weak$$choice2~0_In1490883923, ULTIMATE.start_main_#t~ite32=|ULTIMATE.start_main_#t~ite32_Out1490883923|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1490883923, ULTIMATE.start_main_#t~ite33=|ULTIMATE.start_main_#t~ite33_Out1490883923|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1490883923} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite32, ULTIMATE.start_main_#t~ite33] because there is no mapped edge [2019-11-28 18:16:33,589 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [734] [734] L834-->L834-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In667456928 256)))) (or (and .cse0 (= |ULTIMATE.start_main_#t~ite35_Out667456928| ~y$w_buff0_used~0_In667456928) (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In667456928 256)))) (or (= 0 (mod ~y$w_buff0_used~0_In667456928 256)) (and (= 0 (mod ~y$r_buff1_thd0~0_In667456928 256)) .cse1) (and (= 0 (mod ~y$w_buff1_used~0_In667456928 256)) .cse1))) (= |ULTIMATE.start_main_#t~ite35_Out667456928| |ULTIMATE.start_main_#t~ite36_Out667456928|)) (and (= ~y$w_buff0_used~0_In667456928 |ULTIMATE.start_main_#t~ite36_Out667456928|) (not .cse0) (= |ULTIMATE.start_main_#t~ite35_In667456928| |ULTIMATE.start_main_#t~ite35_Out667456928|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In667456928, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In667456928, ULTIMATE.start_main_#t~ite35=|ULTIMATE.start_main_#t~ite35_In667456928|, ~weak$$choice2~0=~weak$$choice2~0_In667456928, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In667456928, ~y$w_buff1_used~0=~y$w_buff1_used~0_In667456928} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In667456928, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In667456928, ULTIMATE.start_main_#t~ite35=|ULTIMATE.start_main_#t~ite35_Out667456928|, ULTIMATE.start_main_#t~ite36=|ULTIMATE.start_main_#t~ite36_Out667456928|, ~weak$$choice2~0=~weak$$choice2~0_In667456928, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In667456928, ~y$w_buff1_used~0=~y$w_buff1_used~0_In667456928} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite36] because there is no mapped edge [2019-11-28 18:16:33,590 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [732] [732] L835-->L835-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In1394441445 256) 0))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite38_In1394441445| |ULTIMATE.start_main_#t~ite38_Out1394441445|) (= |ULTIMATE.start_main_#t~ite39_Out1394441445| ~y$w_buff1_used~0_In1394441445)) (and (= |ULTIMATE.start_main_#t~ite38_Out1394441445| ~y$w_buff1_used~0_In1394441445) (= |ULTIMATE.start_main_#t~ite38_Out1394441445| |ULTIMATE.start_main_#t~ite39_Out1394441445|) (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In1394441445 256) 0))) (or (and (= 0 (mod ~y$w_buff1_used~0_In1394441445 256)) .cse1) (and (= 0 (mod ~y$r_buff1_thd0~0_In1394441445 256)) .cse1) (= (mod ~y$w_buff0_used~0_In1394441445 256) 0))) .cse0))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1394441445, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1394441445, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_In1394441445|, ~weak$$choice2~0=~weak$$choice2~0_In1394441445, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1394441445, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1394441445} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1394441445, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out1394441445|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1394441445, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_Out1394441445|, ~weak$$choice2~0=~weak$$choice2~0_In1394441445, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1394441445, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1394441445} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite38] because there is no mapped edge [2019-11-28 18:16:33,590 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [665] [665] L836-->L837: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_29 256))) (= v_~y$r_buff0_thd0~0_100 v_~y$r_buff0_thd0~0_99)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_100, ~weak$$choice2~0=v_~weak$$choice2~0_29} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_13|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_8|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_99, ~weak$$choice2~0=v_~weak$$choice2~0_29, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-11-28 18:16:33,591 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [731] [731] L839-->L4: Formula: (and (= v_~y~0_138 v_~y$mem_tmp~0_17) (= (mod v_~main$tmp_guard1~0_23 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|) (= 0 v_~y$flush_delayed~0_52) (not (= (mod v_~y$flush_delayed~0_53 256) 0))) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_17, ~y$flush_delayed~0=v_~y$flush_delayed~0_53, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_23} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_17, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_12, ~y$flush_delayed~0=v_~y$flush_delayed~0_52, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_60|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_23, ~y~0=v_~y~0_138, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_7|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ~y$flush_delayed~0, ULTIMATE.start_main_#t~ite46, ~y~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-11-28 18:16:33,592 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [726] [726] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-11-28 18:16:33,698 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2019-11-28 18:16:33,699 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-28 18:16:33,700 INFO L168 Benchmark]: Toolchain (without parser) took 17953.96 ms. Allocated memory was 1.0 GB in the beginning and 1.5 GB in the end (delta: 497.5 MB). Free memory was 949.6 MB in the beginning and 673.6 MB in the end (delta: 276.0 MB). Peak memory consumption was 773.6 MB. Max. memory is 11.5 GB. [2019-11-28 18:16:33,701 INFO L168 Benchmark]: CDTParser took 0.30 ms. Allocated memory is still 1.0 GB. Free memory is still 981.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 18:16:33,701 INFO L168 Benchmark]: CACSL2BoogieTranslator took 793.34 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 111.1 MB). Free memory was 949.6 MB in the beginning and 1.1 GB in the end (delta: -121.8 MB). Peak memory consumption was 20.6 MB. Max. memory is 11.5 GB. [2019-11-28 18:16:33,702 INFO L168 Benchmark]: Boogie Procedure Inliner took 89.35 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.8 MB). Peak memory consumption was 6.8 MB. Max. memory is 11.5 GB. [2019-11-28 18:16:33,702 INFO L168 Benchmark]: Boogie Preprocessor took 42.64 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 18:16:33,702 INFO L168 Benchmark]: RCFGBuilder took 827.62 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 52.3 MB). Peak memory consumption was 52.3 MB. Max. memory is 11.5 GB. [2019-11-28 18:16:33,703 INFO L168 Benchmark]: TraceAbstraction took 16068.60 ms. Allocated memory was 1.1 GB in the beginning and 1.5 GB in the end (delta: 386.4 MB). Free memory was 1.0 GB in the beginning and 685.6 MB in the end (delta: 326.7 MB). Peak memory consumption was 713.1 MB. Max. memory is 11.5 GB. [2019-11-28 18:16:33,703 INFO L168 Benchmark]: Witness Printer took 125.78 ms. Allocated memory is still 1.5 GB. Free memory was 685.6 MB in the beginning and 673.6 MB in the end (delta: 12.0 MB). Peak memory consumption was 12.0 MB. Max. memory is 11.5 GB. [2019-11-28 18:16:33,705 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.30 ms. Allocated memory is still 1.0 GB. Free memory is still 981.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 793.34 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 111.1 MB). Free memory was 949.6 MB in the beginning and 1.1 GB in the end (delta: -121.8 MB). Peak memory consumption was 20.6 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 89.35 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.8 MB). Peak memory consumption was 6.8 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 42.64 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 827.62 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 52.3 MB). Peak memory consumption was 52.3 MB. Max. memory is 11.5 GB. * TraceAbstraction took 16068.60 ms. Allocated memory was 1.1 GB in the beginning and 1.5 GB in the end (delta: 386.4 MB). Free memory was 1.0 GB in the beginning and 685.6 MB in the end (delta: 326.7 MB). Peak memory consumption was 713.1 MB. Max. memory is 11.5 GB. * Witness Printer took 125.78 ms. Allocated memory is still 1.5 GB. Free memory was 685.6 MB in the beginning and 673.6 MB in the end (delta: 12.0 MB). Peak memory consumption was 12.0 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 5.5s, 164 ProgramPointsBefore, 82 ProgramPointsAfterwards, 195 TransitionsBefore, 91 TransitionsAfterwards, 11490 CoEnabledTransitionPairs, 7 FixpointIterations, 33 TrivialSequentialCompositions, 42 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 39 ConcurrentYvCompositions, 26 ChoiceCompositions, 4376 VarBasedMoverChecksPositive, 193 VarBasedMoverChecksNegative, 58 SemBasedMoverChecksPositive, 191 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 1.2s, 0 MoverChecksTotal, 46792 CheckedPairsTotal, 114 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L810] FCALL, FORK 0 pthread_create(&t1208, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L812] FCALL, FORK 0 pthread_create(&t1209, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L814] FCALL, FORK 0 pthread_create(&t1210, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L771] 3 y$r_buff1_thd0 = y$r_buff0_thd0 [L772] 3 y$r_buff1_thd1 = y$r_buff0_thd1 [L773] 3 y$r_buff1_thd2 = y$r_buff0_thd2 [L774] 3 y$r_buff1_thd3 = y$r_buff0_thd3 [L775] 3 y$r_buff0_thd3 = (_Bool)1 [L778] 3 z = 1 [L781] 3 __unbuffered_p2_EAX = z [L784] 3 __unbuffered_p2_EBX = a VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L787] EXPR 3 y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L746] 2 x = 2 [L749] 2 y = 1 VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L787] 3 y = y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) [L788] 3 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : y$w_buff0_used [L789] 3 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd3 || y$w_buff1_used && y$r_buff1_thd3 ? (_Bool)0 : y$w_buff1_used [L752] 2 y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=2, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L753] 2 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$w_buff0_used [L754] 2 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used [L755] 2 y$r_buff0_thd2 = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$r_buff0_thd2 [L820] EXPR 0 y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L820] 0 y = y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) [L821] 0 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used [L822] 0 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$w_buff1_used [L823] 0 y$r_buff0_thd0 = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$r_buff0_thd0 [L824] 0 y$r_buff1_thd0 = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$r_buff1_thd0 [L827] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L828] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L829] 0 y$flush_delayed = weak$$choice2 [L830] 0 y$mem_tmp = y VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L831] EXPR 0 !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L831] 0 y = !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) [L832] EXPR 0 weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L832] 0 y$w_buff0 = weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) [L833] 0 y$w_buff1 = weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) [L834] 0 y$w_buff0_used = weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) [L835] 0 y$w_buff1_used = weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L837] EXPR 0 weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L837] 0 y$r_buff1_thd0 = weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L838] 0 main$tmp_guard1 = !(x == 2 && y == 2 && __unbuffered_p2_EAX == 1 && __unbuffered_p2_EBX == 0) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 155 locations, 2 error locations. Result: UNSAFE, OverallTime: 15.8s, OverallIterations: 16, TraceHistogramMax: 1, AutomataDifference: 2.9s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 1550 SDtfs, 1301 SDslu, 2783 SDs, 0 SdLazy, 1082 SolverSat, 92 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.2s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 83 GetRequests, 17 SyntacticMatches, 7 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 51 ImplicationChecksByTransitivity, 0.7s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=22284occurred in iteration=2, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 3.3s AutomataMinimizationTime, 15 MinimizatonAttempts, 4341 StatesRemovedByMinimization, 12 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.4s SatisfiabilityAnalysisTime, 1.3s InterpolantComputationTime, 637 NumberOfCodeBlocks, 637 NumberOfCodeBlocksAsserted, 16 NumberOfCheckSat, 565 ConstructedInterpolants, 0 QuantifiedInterpolants, 127132 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 15 InterpolantComputations, 15 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...