./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/pthread-wmm/mix054_pso.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx12G -Xms1G -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/pthread-wmm/mix054_pso.opt.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 530d9436aa4f4ef82834180462660e57d00a5021 ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-11-28 18:19:30,696 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-28 18:19:30,699 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-28 18:19:30,718 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-28 18:19:30,718 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-28 18:19:30,720 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-28 18:19:30,723 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-28 18:19:30,733 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-28 18:19:30,738 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-28 18:19:30,742 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-28 18:19:30,743 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-28 18:19:30,745 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-28 18:19:30,746 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-28 18:19:30,749 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-28 18:19:30,750 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-28 18:19:30,751 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-28 18:19:30,753 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-28 18:19:30,754 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-28 18:19:30,756 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-28 18:19:30,760 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-28 18:19:30,765 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-28 18:19:30,770 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-28 18:19:30,771 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-28 18:19:30,773 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-28 18:19:30,776 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-28 18:19:30,776 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-28 18:19:30,777 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-28 18:19:30,779 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-28 18:19:30,779 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-28 18:19:30,780 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-28 18:19:30,781 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-28 18:19:30,782 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-28 18:19:30,782 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-28 18:19:30,784 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-28 18:19:30,785 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-28 18:19:30,785 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-28 18:19:30,786 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-28 18:19:30,787 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-28 18:19:30,787 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-28 18:19:30,788 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-28 18:19:30,789 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-28 18:19:30,790 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-28 18:19:30,821 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-28 18:19:30,822 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-28 18:19:30,823 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-28 18:19:30,824 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-28 18:19:30,824 INFO L138 SettingsManager]: * Use SBE=true [2019-11-28 18:19:30,824 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-28 18:19:30,824 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-28 18:19:30,825 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-28 18:19:30,825 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-28 18:19:30,825 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-28 18:19:30,826 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-28 18:19:30,826 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-28 18:19:30,826 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-28 18:19:30,826 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-28 18:19:30,827 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-28 18:19:30,827 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-28 18:19:30,827 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-28 18:19:30,827 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-28 18:19:30,828 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-28 18:19:30,828 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-28 18:19:30,828 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-28 18:19:30,829 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 18:19:30,829 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-28 18:19:30,829 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-28 18:19:30,830 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-28 18:19:30,830 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-28 18:19:30,830 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-28 18:19:30,830 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-28 18:19:30,831 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-11-28 18:19:30,831 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 530d9436aa4f4ef82834180462660e57d00a5021 [2019-11-28 18:19:31,141 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-28 18:19:31,160 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-28 18:19:31,164 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-28 18:19:31,166 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-28 18:19:31,168 INFO L275 PluginConnector]: CDTParser initialized [2019-11-28 18:19:31,169 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/pthread-wmm/mix054_pso.opt.i [2019-11-28 18:19:31,249 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ce26546d9/69e063cdc8ab4a47b8f7ac001b535e9c/FLAG783fad668 [2019-11-28 18:19:31,882 INFO L306 CDTParser]: Found 1 translation units. [2019-11-28 18:19:31,883 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/pthread-wmm/mix054_pso.opt.i [2019-11-28 18:19:31,899 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ce26546d9/69e063cdc8ab4a47b8f7ac001b535e9c/FLAG783fad668 [2019-11-28 18:19:32,119 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ce26546d9/69e063cdc8ab4a47b8f7ac001b535e9c [2019-11-28 18:19:32,123 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-28 18:19:32,124 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-28 18:19:32,126 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-28 18:19:32,126 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-28 18:19:32,129 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-28 18:19:32,131 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 06:19:32" (1/1) ... [2019-11-28 18:19:32,134 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@76576ffa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:19:32, skipping insertion in model container [2019-11-28 18:19:32,134 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 06:19:32" (1/1) ... [2019-11-28 18:19:32,142 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-11-28 18:19:32,206 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-11-28 18:19:32,832 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 18:19:32,851 INFO L203 MainTranslator]: Completed pre-run [2019-11-28 18:19:32,927 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 18:19:33,023 INFO L208 MainTranslator]: Completed translation [2019-11-28 18:19:33,024 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:19:33 WrapperNode [2019-11-28 18:19:33,024 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-28 18:19:33,025 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-28 18:19:33,025 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-28 18:19:33,025 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-28 18:19:33,035 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:19:33" (1/1) ... [2019-11-28 18:19:33,058 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:19:33" (1/1) ... [2019-11-28 18:19:33,100 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-28 18:19:33,100 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-28 18:19:33,100 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-28 18:19:33,101 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-28 18:19:33,111 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:19:33" (1/1) ... [2019-11-28 18:19:33,112 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:19:33" (1/1) ... [2019-11-28 18:19:33,116 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:19:33" (1/1) ... [2019-11-28 18:19:33,117 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:19:33" (1/1) ... [2019-11-28 18:19:33,127 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:19:33" (1/1) ... [2019-11-28 18:19:33,131 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:19:33" (1/1) ... [2019-11-28 18:19:33,137 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:19:33" (1/1) ... [2019-11-28 18:19:33,148 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-28 18:19:33,150 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-28 18:19:33,151 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-28 18:19:33,153 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-28 18:19:33,155 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:19:33" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 18:19:33,225 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-11-28 18:19:33,225 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-11-28 18:19:33,226 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-11-28 18:19:33,226 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-11-28 18:19:33,226 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-11-28 18:19:33,226 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-11-28 18:19:33,226 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-11-28 18:19:33,226 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-11-28 18:19:33,227 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-11-28 18:19:33,227 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-28 18:19:33,227 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-28 18:19:33,229 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-11-28 18:19:33,981 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-28 18:19:33,981 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-11-28 18:19:33,982 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:19:33 BoogieIcfgContainer [2019-11-28 18:19:33,983 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-28 18:19:33,984 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-28 18:19:33,984 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-28 18:19:33,987 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-28 18:19:33,988 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 06:19:32" (1/3) ... [2019-11-28 18:19:33,989 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4f315f1b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 06:19:33, skipping insertion in model container [2019-11-28 18:19:33,989 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:19:33" (2/3) ... [2019-11-28 18:19:33,989 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4f315f1b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 06:19:33, skipping insertion in model container [2019-11-28 18:19:33,989 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:19:33" (3/3) ... [2019-11-28 18:19:33,991 INFO L109 eAbstractionObserver]: Analyzing ICFG mix054_pso.opt.i [2019-11-28 18:19:34,002 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-11-28 18:19:34,002 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-28 18:19:34,011 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-11-28 18:19:34,012 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-11-28 18:19:34,047 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,047 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,047 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,047 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,048 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,048 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,048 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,049 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,049 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,049 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,049 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,050 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,050 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,050 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,050 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,051 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,051 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,051 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,051 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,052 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,052 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,052 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,052 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,053 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,053 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,053 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,053 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,054 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,054 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,054 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,055 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,055 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,055 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,056 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,056 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,056 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,056 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,057 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,057 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,057 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,058 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,058 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,058 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,058 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,059 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,059 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,059 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,059 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,060 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,060 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,060 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,060 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,061 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,061 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,061 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,061 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,062 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,062 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,062 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,062 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,063 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,063 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,063 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,063 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:19:34,081 INFO L249 AbstractCegarLoop]: Starting to check reachability of 5 error locations. [2019-11-28 18:19:34,100 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-28 18:19:34,100 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-28 18:19:34,100 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-28 18:19:34,100 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-28 18:19:34,101 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-28 18:19:34,101 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-28 18:19:34,101 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-28 18:19:34,101 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-28 18:19:34,117 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 146 places, 180 transitions [2019-11-28 18:19:34,119 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 146 places, 180 transitions [2019-11-28 18:19:34,218 INFO L134 PetriNetUnfolder]: 41/178 cut-off events. [2019-11-28 18:19:34,218 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-11-28 18:19:34,238 INFO L76 FinitePrefix]: Finished finitePrefix Result has 185 conditions, 178 events. 41/178 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 458 event pairs. 6/141 useless extension candidates. Maximal degree in co-relation 150. Up to 2 conditions per place. [2019-11-28 18:19:34,257 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 146 places, 180 transitions [2019-11-28 18:19:34,320 INFO L134 PetriNetUnfolder]: 41/178 cut-off events. [2019-11-28 18:19:34,320 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-11-28 18:19:34,327 INFO L76 FinitePrefix]: Finished finitePrefix Result has 185 conditions, 178 events. 41/178 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 458 event pairs. 6/141 useless extension candidates. Maximal degree in co-relation 150. Up to 2 conditions per place. [2019-11-28 18:19:34,341 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 10378 [2019-11-28 18:19:34,343 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-11-28 18:19:38,855 WARN L192 SmtUtils]: Spent 207.00 ms on a formula simplification. DAG size of input: 81 DAG size of output: 79 [2019-11-28 18:19:38,965 WARN L192 SmtUtils]: Spent 107.00 ms on a formula simplification that was a NOOP. DAG size: 77 [2019-11-28 18:19:39,009 INFO L206 etLargeBlockEncoding]: Checked pairs total: 46078 [2019-11-28 18:19:39,010 INFO L214 etLargeBlockEncoding]: Total number of compositions: 100 [2019-11-28 18:19:39,014 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 78 places, 90 transitions [2019-11-28 18:19:39,645 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 8413 states. [2019-11-28 18:19:39,647 INFO L276 IsEmpty]: Start isEmpty. Operand 8413 states. [2019-11-28 18:19:39,659 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-11-28 18:19:39,660 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:19:39,661 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-11-28 18:19:39,661 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:19:39,668 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:19:39,672 INFO L82 PathProgramCache]: Analyzing trace with hash 693777882, now seen corresponding path program 1 times [2019-11-28 18:19:39,682 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:19:39,683 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [402064025] [2019-11-28 18:19:39,683 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:19:39,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:19:39,925 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:19:39,926 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [402064025] [2019-11-28 18:19:39,928 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:19:39,928 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-11-28 18:19:39,929 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [737062193] [2019-11-28 18:19:39,935 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:19:39,935 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:19:39,956 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:19:39,957 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:19:39,959 INFO L87 Difference]: Start difference. First operand 8413 states. Second operand 3 states. [2019-11-28 18:19:40,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:19:40,205 INFO L93 Difference]: Finished difference Result 8377 states and 27415 transitions. [2019-11-28 18:19:40,205 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:19:40,207 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 5 [2019-11-28 18:19:40,208 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:19:40,292 INFO L225 Difference]: With dead ends: 8377 [2019-11-28 18:19:40,293 INFO L226 Difference]: Without dead ends: 8208 [2019-11-28 18:19:40,294 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:19:40,397 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8208 states. [2019-11-28 18:19:40,684 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8208 to 8208. [2019-11-28 18:19:40,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8208 states. [2019-11-28 18:19:40,743 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8208 states to 8208 states and 26895 transitions. [2019-11-28 18:19:40,745 INFO L78 Accepts]: Start accepts. Automaton has 8208 states and 26895 transitions. Word has length 5 [2019-11-28 18:19:40,745 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:19:40,745 INFO L462 AbstractCegarLoop]: Abstraction has 8208 states and 26895 transitions. [2019-11-28 18:19:40,746 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:19:40,746 INFO L276 IsEmpty]: Start isEmpty. Operand 8208 states and 26895 transitions. [2019-11-28 18:19:40,750 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-11-28 18:19:40,751 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:19:40,751 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:19:40,751 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:19:40,752 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:19:40,752 INFO L82 PathProgramCache]: Analyzing trace with hash 2143808117, now seen corresponding path program 1 times [2019-11-28 18:19:40,752 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:19:40,752 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [352924651] [2019-11-28 18:19:40,752 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:19:40,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:19:40,910 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:19:40,911 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [352924651] [2019-11-28 18:19:40,911 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:19:40,911 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:19:40,911 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1344192621] [2019-11-28 18:19:40,914 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:19:40,914 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:19:40,914 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:19:40,915 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:19:40,915 INFO L87 Difference]: Start difference. First operand 8208 states and 26895 transitions. Second operand 3 states. [2019-11-28 18:19:40,950 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:19:40,951 INFO L93 Difference]: Finished difference Result 1326 states and 3037 transitions. [2019-11-28 18:19:40,951 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:19:40,951 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2019-11-28 18:19:40,951 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:19:40,961 INFO L225 Difference]: With dead ends: 1326 [2019-11-28 18:19:40,962 INFO L226 Difference]: Without dead ends: 1326 [2019-11-28 18:19:40,964 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:19:40,970 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1326 states. [2019-11-28 18:19:40,997 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1326 to 1326. [2019-11-28 18:19:40,997 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1326 states. [2019-11-28 18:19:41,004 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1326 states to 1326 states and 3037 transitions. [2019-11-28 18:19:41,004 INFO L78 Accepts]: Start accepts. Automaton has 1326 states and 3037 transitions. Word has length 11 [2019-11-28 18:19:41,004 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:19:41,004 INFO L462 AbstractCegarLoop]: Abstraction has 1326 states and 3037 transitions. [2019-11-28 18:19:41,005 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:19:41,005 INFO L276 IsEmpty]: Start isEmpty. Operand 1326 states and 3037 transitions. [2019-11-28 18:19:41,007 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-11-28 18:19:41,007 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:19:41,007 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:19:41,008 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:19:41,008 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:19:41,008 INFO L82 PathProgramCache]: Analyzing trace with hash 1923085964, now seen corresponding path program 1 times [2019-11-28 18:19:41,008 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:19:41,009 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1913588365] [2019-11-28 18:19:41,009 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:19:41,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:19:41,143 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:19:41,143 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1913588365] [2019-11-28 18:19:41,144 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:19:41,144 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:19:41,144 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [163690118] [2019-11-28 18:19:41,144 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:19:41,145 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:19:41,145 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:19:41,145 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:19:41,145 INFO L87 Difference]: Start difference. First operand 1326 states and 3037 transitions. Second operand 4 states. [2019-11-28 18:19:41,439 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:19:41,439 INFO L93 Difference]: Finished difference Result 1806 states and 4001 transitions. [2019-11-28 18:19:41,440 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:19:41,440 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-11-28 18:19:41,440 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:19:41,450 INFO L225 Difference]: With dead ends: 1806 [2019-11-28 18:19:41,451 INFO L226 Difference]: Without dead ends: 1806 [2019-11-28 18:19:41,451 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:19:41,457 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1806 states. [2019-11-28 18:19:41,493 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1806 to 1654. [2019-11-28 18:19:41,494 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1654 states. [2019-11-28 18:19:41,499 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1654 states to 1654 states and 3712 transitions. [2019-11-28 18:19:41,499 INFO L78 Accepts]: Start accepts. Automaton has 1654 states and 3712 transitions. Word has length 11 [2019-11-28 18:19:41,499 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:19:41,500 INFO L462 AbstractCegarLoop]: Abstraction has 1654 states and 3712 transitions. [2019-11-28 18:19:41,500 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:19:41,500 INFO L276 IsEmpty]: Start isEmpty. Operand 1654 states and 3712 transitions. [2019-11-28 18:19:41,503 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2019-11-28 18:19:41,503 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:19:41,503 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:19:41,503 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:19:41,504 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:19:41,504 INFO L82 PathProgramCache]: Analyzing trace with hash 909891733, now seen corresponding path program 1 times [2019-11-28 18:19:41,504 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:19:41,504 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [596026326] [2019-11-28 18:19:41,504 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:19:41,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:19:41,573 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:19:41,573 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [596026326] [2019-11-28 18:19:41,573 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:19:41,573 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:19:41,574 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [837264441] [2019-11-28 18:19:41,574 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:19:41,574 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:19:41,575 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:19:41,575 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:19:41,575 INFO L87 Difference]: Start difference. First operand 1654 states and 3712 transitions. Second operand 4 states. [2019-11-28 18:19:41,590 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:19:41,591 INFO L93 Difference]: Finished difference Result 356 states and 659 transitions. [2019-11-28 18:19:41,595 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-28 18:19:41,595 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 23 [2019-11-28 18:19:41,595 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:19:41,597 INFO L225 Difference]: With dead ends: 356 [2019-11-28 18:19:41,597 INFO L226 Difference]: Without dead ends: 356 [2019-11-28 18:19:41,598 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:19:41,599 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 356 states. [2019-11-28 18:19:41,605 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 356 to 321. [2019-11-28 18:19:41,605 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 321 states. [2019-11-28 18:19:41,606 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 321 states to 321 states and 594 transitions. [2019-11-28 18:19:41,606 INFO L78 Accepts]: Start accepts. Automaton has 321 states and 594 transitions. Word has length 23 [2019-11-28 18:19:41,606 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:19:41,609 INFO L462 AbstractCegarLoop]: Abstraction has 321 states and 594 transitions. [2019-11-28 18:19:41,609 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:19:41,609 INFO L276 IsEmpty]: Start isEmpty. Operand 321 states and 594 transitions. [2019-11-28 18:19:41,611 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2019-11-28 18:19:41,611 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:19:41,612 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:19:41,612 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:19:41,612 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:19:41,612 INFO L82 PathProgramCache]: Analyzing trace with hash 763517816, now seen corresponding path program 1 times [2019-11-28 18:19:41,613 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:19:41,613 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1075540711] [2019-11-28 18:19:41,613 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:19:41,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:19:41,741 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:19:41,741 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1075540711] [2019-11-28 18:19:41,742 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:19:41,742 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:19:41,742 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [951947500] [2019-11-28 18:19:41,742 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:19:41,743 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:19:41,743 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:19:41,743 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:19:41,743 INFO L87 Difference]: Start difference. First operand 321 states and 594 transitions. Second operand 3 states. [2019-11-28 18:19:41,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:19:41,791 INFO L93 Difference]: Finished difference Result 331 states and 608 transitions. [2019-11-28 18:19:41,791 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:19:41,792 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 52 [2019-11-28 18:19:41,792 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:19:41,793 INFO L225 Difference]: With dead ends: 331 [2019-11-28 18:19:41,794 INFO L226 Difference]: Without dead ends: 331 [2019-11-28 18:19:41,794 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:19:41,795 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 331 states. [2019-11-28 18:19:41,801 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 331 to 327. [2019-11-28 18:19:41,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 327 states. [2019-11-28 18:19:41,802 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 327 states to 327 states and 604 transitions. [2019-11-28 18:19:41,803 INFO L78 Accepts]: Start accepts. Automaton has 327 states and 604 transitions. Word has length 52 [2019-11-28 18:19:41,804 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:19:41,804 INFO L462 AbstractCegarLoop]: Abstraction has 327 states and 604 transitions. [2019-11-28 18:19:41,804 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:19:41,805 INFO L276 IsEmpty]: Start isEmpty. Operand 327 states and 604 transitions. [2019-11-28 18:19:41,806 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2019-11-28 18:19:41,806 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:19:41,807 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:19:41,807 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:19:41,807 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:19:41,807 INFO L82 PathProgramCache]: Analyzing trace with hash 1269350019, now seen corresponding path program 1 times [2019-11-28 18:19:41,807 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:19:41,808 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [570363172] [2019-11-28 18:19:41,808 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:19:41,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:19:41,911 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:19:41,912 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [570363172] [2019-11-28 18:19:41,912 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:19:41,912 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 18:19:41,912 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [810445533] [2019-11-28 18:19:41,913 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:19:41,913 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:19:41,913 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:19:41,914 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:19:41,914 INFO L87 Difference]: Start difference. First operand 327 states and 604 transitions. Second operand 5 states. [2019-11-28 18:19:42,163 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:19:42,163 INFO L93 Difference]: Finished difference Result 458 states and 840 transitions. [2019-11-28 18:19:42,164 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 18:19:42,164 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 52 [2019-11-28 18:19:42,164 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:19:42,168 INFO L225 Difference]: With dead ends: 458 [2019-11-28 18:19:42,168 INFO L226 Difference]: Without dead ends: 458 [2019-11-28 18:19:42,169 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-11-28 18:19:42,171 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 458 states. [2019-11-28 18:19:42,178 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 458 to 374. [2019-11-28 18:19:42,179 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 374 states. [2019-11-28 18:19:42,180 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 374 states to 374 states and 695 transitions. [2019-11-28 18:19:42,180 INFO L78 Accepts]: Start accepts. Automaton has 374 states and 695 transitions. Word has length 52 [2019-11-28 18:19:42,181 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:19:42,181 INFO L462 AbstractCegarLoop]: Abstraction has 374 states and 695 transitions. [2019-11-28 18:19:42,181 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:19:42,181 INFO L276 IsEmpty]: Start isEmpty. Operand 374 states and 695 transitions. [2019-11-28 18:19:42,183 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2019-11-28 18:19:42,183 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:19:42,183 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:19:42,183 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:19:42,184 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:19:42,184 INFO L82 PathProgramCache]: Analyzing trace with hash 544633013, now seen corresponding path program 2 times [2019-11-28 18:19:42,184 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:19:42,185 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [165031585] [2019-11-28 18:19:42,185 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:19:42,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:19:42,314 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:19:42,370 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [165031585] [2019-11-28 18:19:42,370 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:19:42,370 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-28 18:19:42,371 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [515217618] [2019-11-28 18:19:42,371 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-28 18:19:42,371 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:19:42,371 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-28 18:19:42,372 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-28 18:19:42,372 INFO L87 Difference]: Start difference. First operand 374 states and 695 transitions. Second operand 6 states. [2019-11-28 18:19:42,710 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:19:42,710 INFO L93 Difference]: Finished difference Result 513 states and 942 transitions. [2019-11-28 18:19:42,710 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-28 18:19:42,710 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 52 [2019-11-28 18:19:42,711 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:19:42,713 INFO L225 Difference]: With dead ends: 513 [2019-11-28 18:19:42,714 INFO L226 Difference]: Without dead ends: 513 [2019-11-28 18:19:42,714 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 5 SyntacticMatches, 2 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=32, Invalid=78, Unknown=0, NotChecked=0, Total=110 [2019-11-28 18:19:42,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 513 states. [2019-11-28 18:19:42,723 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 513 to 406. [2019-11-28 18:19:42,723 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 406 states. [2019-11-28 18:19:42,724 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 406 states to 406 states and 754 transitions. [2019-11-28 18:19:42,725 INFO L78 Accepts]: Start accepts. Automaton has 406 states and 754 transitions. Word has length 52 [2019-11-28 18:19:42,725 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:19:42,725 INFO L462 AbstractCegarLoop]: Abstraction has 406 states and 754 transitions. [2019-11-28 18:19:42,725 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-28 18:19:42,725 INFO L276 IsEmpty]: Start isEmpty. Operand 406 states and 754 transitions. [2019-11-28 18:19:42,727 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2019-11-28 18:19:42,727 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:19:42,727 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:19:42,727 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:19:42,727 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:19:42,727 INFO L82 PathProgramCache]: Analyzing trace with hash 1227473235, now seen corresponding path program 3 times [2019-11-28 18:19:42,728 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:19:42,728 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [61361890] [2019-11-28 18:19:42,728 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:19:42,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:19:42,850 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:19:42,850 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [61361890] [2019-11-28 18:19:42,850 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:19:42,851 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-28 18:19:42,851 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [40329594] [2019-11-28 18:19:42,851 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-28 18:19:42,851 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:19:42,852 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-28 18:19:42,852 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-11-28 18:19:42,852 INFO L87 Difference]: Start difference. First operand 406 states and 754 transitions. Second operand 6 states. [2019-11-28 18:19:43,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:19:43,190 INFO L93 Difference]: Finished difference Result 694 states and 1274 transitions. [2019-11-28 18:19:43,191 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-11-28 18:19:43,191 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 52 [2019-11-28 18:19:43,191 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:19:43,195 INFO L225 Difference]: With dead ends: 694 [2019-11-28 18:19:43,195 INFO L226 Difference]: Without dead ends: 694 [2019-11-28 18:19:43,195 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2019-11-28 18:19:43,197 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 694 states. [2019-11-28 18:19:43,204 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 694 to 445. [2019-11-28 18:19:43,204 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 445 states. [2019-11-28 18:19:43,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 445 states to 445 states and 833 transitions. [2019-11-28 18:19:43,205 INFO L78 Accepts]: Start accepts. Automaton has 445 states and 833 transitions. Word has length 52 [2019-11-28 18:19:43,206 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:19:43,206 INFO L462 AbstractCegarLoop]: Abstraction has 445 states and 833 transitions. [2019-11-28 18:19:43,206 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-28 18:19:43,206 INFO L276 IsEmpty]: Start isEmpty. Operand 445 states and 833 transitions. [2019-11-28 18:19:43,207 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2019-11-28 18:19:43,207 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:19:43,207 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:19:43,207 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:19:43,208 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:19:43,208 INFO L82 PathProgramCache]: Analyzing trace with hash 1833025349, now seen corresponding path program 4 times [2019-11-28 18:19:43,208 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:19:43,208 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [955789888] [2019-11-28 18:19:43,208 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:19:43,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:19:43,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:19:43,322 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [955789888] [2019-11-28 18:19:43,323 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:19:43,323 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-11-28 18:19:43,323 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1019872280] [2019-11-28 18:19:43,323 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-11-28 18:19:43,324 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:19:43,324 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-11-28 18:19:43,324 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-11-28 18:19:43,324 INFO L87 Difference]: Start difference. First operand 445 states and 833 transitions. Second operand 7 states. [2019-11-28 18:19:43,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:19:43,741 INFO L93 Difference]: Finished difference Result 702 states and 1289 transitions. [2019-11-28 18:19:43,742 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-28 18:19:43,742 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 52 [2019-11-28 18:19:43,742 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:19:43,745 INFO L225 Difference]: With dead ends: 702 [2019-11-28 18:19:43,745 INFO L226 Difference]: Without dead ends: 702 [2019-11-28 18:19:43,746 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 6 SyntacticMatches, 3 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=80, Unknown=0, NotChecked=0, Total=110 [2019-11-28 18:19:43,748 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 702 states. [2019-11-28 18:19:43,754 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 702 to 424. [2019-11-28 18:19:43,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 424 states. [2019-11-28 18:19:43,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 424 states to 424 states and 792 transitions. [2019-11-28 18:19:43,756 INFO L78 Accepts]: Start accepts. Automaton has 424 states and 792 transitions. Word has length 52 [2019-11-28 18:19:43,756 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:19:43,757 INFO L462 AbstractCegarLoop]: Abstraction has 424 states and 792 transitions. [2019-11-28 18:19:43,757 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-11-28 18:19:43,757 INFO L276 IsEmpty]: Start isEmpty. Operand 424 states and 792 transitions. [2019-11-28 18:19:43,758 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2019-11-28 18:19:43,758 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:19:43,758 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:19:43,759 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:19:43,759 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:19:43,759 INFO L82 PathProgramCache]: Analyzing trace with hash 513839464, now seen corresponding path program 1 times [2019-11-28 18:19:43,760 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:19:43,760 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2120346026] [2019-11-28 18:19:43,760 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:19:43,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:19:44,033 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:19:44,034 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2120346026] [2019-11-28 18:19:44,034 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:19:44,034 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-11-28 18:19:44,035 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [355436092] [2019-11-28 18:19:44,035 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-11-28 18:19:44,035 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:19:44,035 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-11-28 18:19:44,035 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=80, Unknown=0, NotChecked=0, Total=110 [2019-11-28 18:19:44,035 INFO L87 Difference]: Start difference. First operand 424 states and 792 transitions. Second operand 11 states. [2019-11-28 18:19:44,553 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:19:44,553 INFO L93 Difference]: Finished difference Result 458 states and 803 transitions. [2019-11-28 18:19:44,554 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-11-28 18:19:44,554 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 53 [2019-11-28 18:19:44,555 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:19:44,557 INFO L225 Difference]: With dead ends: 458 [2019-11-28 18:19:44,557 INFO L226 Difference]: Without dead ends: 458 [2019-11-28 18:19:44,558 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=70, Invalid=170, Unknown=0, NotChecked=0, Total=240 [2019-11-28 18:19:44,559 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 458 states. [2019-11-28 18:19:44,564 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 458 to 340. [2019-11-28 18:19:44,564 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 340 states. [2019-11-28 18:19:44,565 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 340 states to 340 states and 601 transitions. [2019-11-28 18:19:44,566 INFO L78 Accepts]: Start accepts. Automaton has 340 states and 601 transitions. Word has length 53 [2019-11-28 18:19:44,566 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:19:44,566 INFO L462 AbstractCegarLoop]: Abstraction has 340 states and 601 transitions. [2019-11-28 18:19:44,566 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-11-28 18:19:44,566 INFO L276 IsEmpty]: Start isEmpty. Operand 340 states and 601 transitions. [2019-11-28 18:19:44,567 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2019-11-28 18:19:44,567 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:19:44,567 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:19:44,568 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:19:44,568 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:19:44,568 INFO L82 PathProgramCache]: Analyzing trace with hash -1617311510, now seen corresponding path program 2 times [2019-11-28 18:19:44,568 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:19:44,569 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [414154560] [2019-11-28 18:19:44,569 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:19:44,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:19:44,925 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:19:44,926 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [414154560] [2019-11-28 18:19:44,926 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:19:44,926 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-11-28 18:19:44,927 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [549130423] [2019-11-28 18:19:44,927 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-11-28 18:19:44,927 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:19:44,928 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-11-28 18:19:44,928 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=64, Unknown=0, NotChecked=0, Total=90 [2019-11-28 18:19:44,928 INFO L87 Difference]: Start difference. First operand 340 states and 601 transitions. Second operand 10 states. [2019-11-28 18:19:45,289 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:19:45,289 INFO L93 Difference]: Finished difference Result 440 states and 769 transitions. [2019-11-28 18:19:45,290 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-11-28 18:19:45,290 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 53 [2019-11-28 18:19:45,290 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:19:45,293 INFO L225 Difference]: With dead ends: 440 [2019-11-28 18:19:45,294 INFO L226 Difference]: Without dead ends: 440 [2019-11-28 18:19:45,294 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 1 SyntacticMatches, 4 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 47 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=76, Invalid=196, Unknown=0, NotChecked=0, Total=272 [2019-11-28 18:19:45,296 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 440 states. [2019-11-28 18:19:45,303 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 440 to 336. [2019-11-28 18:19:45,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 336 states. [2019-11-28 18:19:45,305 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 336 states to 336 states and 593 transitions. [2019-11-28 18:19:45,306 INFO L78 Accepts]: Start accepts. Automaton has 336 states and 593 transitions. Word has length 53 [2019-11-28 18:19:45,306 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:19:45,306 INFO L462 AbstractCegarLoop]: Abstraction has 336 states and 593 transitions. [2019-11-28 18:19:45,306 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-11-28 18:19:45,306 INFO L276 IsEmpty]: Start isEmpty. Operand 336 states and 593 transitions. [2019-11-28 18:19:45,308 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2019-11-28 18:19:45,308 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:19:45,308 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:19:45,308 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:19:45,309 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:19:45,309 INFO L82 PathProgramCache]: Analyzing trace with hash -446396804, now seen corresponding path program 3 times [2019-11-28 18:19:45,309 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:19:45,310 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [693188638] [2019-11-28 18:19:45,310 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:19:45,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:19:45,632 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:19:45,633 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [693188638] [2019-11-28 18:19:45,633 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:19:45,633 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-11-28 18:19:45,633 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1891650295] [2019-11-28 18:19:45,634 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-11-28 18:19:45,634 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:19:45,634 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-11-28 18:19:45,634 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2019-11-28 18:19:45,635 INFO L87 Difference]: Start difference. First operand 336 states and 593 transitions. Second operand 10 states. [2019-11-28 18:19:46,122 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:19:46,122 INFO L93 Difference]: Finished difference Result 474 states and 820 transitions. [2019-11-28 18:19:46,123 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-11-28 18:19:46,123 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 53 [2019-11-28 18:19:46,123 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:19:46,126 INFO L225 Difference]: With dead ends: 474 [2019-11-28 18:19:46,126 INFO L226 Difference]: Without dead ends: 474 [2019-11-28 18:19:46,126 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 1 SyntacticMatches, 4 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 56 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=80, Invalid=226, Unknown=0, NotChecked=0, Total=306 [2019-11-28 18:19:46,127 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 474 states. [2019-11-28 18:19:46,132 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 474 to 328. [2019-11-28 18:19:46,132 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 328 states. [2019-11-28 18:19:46,133 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 328 states to 328 states and 577 transitions. [2019-11-28 18:19:46,133 INFO L78 Accepts]: Start accepts. Automaton has 328 states and 577 transitions. Word has length 53 [2019-11-28 18:19:46,133 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:19:46,134 INFO L462 AbstractCegarLoop]: Abstraction has 328 states and 577 transitions. [2019-11-28 18:19:46,134 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-11-28 18:19:46,134 INFO L276 IsEmpty]: Start isEmpty. Operand 328 states and 577 transitions. [2019-11-28 18:19:46,135 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2019-11-28 18:19:46,135 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:19:46,135 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:19:46,135 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:19:46,135 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:19:46,136 INFO L82 PathProgramCache]: Analyzing trace with hash -162355984, now seen corresponding path program 4 times [2019-11-28 18:19:46,136 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:19:46,136 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [504140726] [2019-11-28 18:19:46,136 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:19:46,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:19:46,442 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:19:46,443 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [504140726] [2019-11-28 18:19:46,443 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:19:46,443 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-11-28 18:19:46,444 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1188328611] [2019-11-28 18:19:46,444 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-11-28 18:19:46,444 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:19:46,445 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-11-28 18:19:46,446 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=118, Unknown=0, NotChecked=0, Total=156 [2019-11-28 18:19:46,446 INFO L87 Difference]: Start difference. First operand 328 states and 577 transitions. Second operand 13 states. [2019-11-28 18:19:47,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:19:47,048 INFO L93 Difference]: Finished difference Result 686 states and 1201 transitions. [2019-11-28 18:19:47,048 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-11-28 18:19:47,049 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 53 [2019-11-28 18:19:47,049 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:19:47,051 INFO L225 Difference]: With dead ends: 686 [2019-11-28 18:19:47,051 INFO L226 Difference]: Without dead ends: 345 [2019-11-28 18:19:47,052 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 75 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=126, Invalid=380, Unknown=0, NotChecked=0, Total=506 [2019-11-28 18:19:47,053 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 345 states. [2019-11-28 18:19:47,058 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 345 to 312. [2019-11-28 18:19:47,058 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 312 states. [2019-11-28 18:19:47,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 312 states to 312 states and 531 transitions. [2019-11-28 18:19:47,060 INFO L78 Accepts]: Start accepts. Automaton has 312 states and 531 transitions. Word has length 53 [2019-11-28 18:19:47,060 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:19:47,060 INFO L462 AbstractCegarLoop]: Abstraction has 312 states and 531 transitions. [2019-11-28 18:19:47,060 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-11-28 18:19:47,060 INFO L276 IsEmpty]: Start isEmpty. Operand 312 states and 531 transitions. [2019-11-28 18:19:47,061 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2019-11-28 18:19:47,061 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:19:47,062 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:19:47,062 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:19:47,062 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:19:47,063 INFO L82 PathProgramCache]: Analyzing trace with hash 1236840700, now seen corresponding path program 5 times [2019-11-28 18:19:47,063 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:19:47,063 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1116823492] [2019-11-28 18:19:47,063 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:19:47,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:19:47,115 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:19:47,115 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1116823492] [2019-11-28 18:19:47,116 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:19:47,116 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:19:47,116 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1591354145] [2019-11-28 18:19:47,116 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:19:47,116 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:19:47,117 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:19:47,117 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:19:47,117 INFO L87 Difference]: Start difference. First operand 312 states and 531 transitions. Second operand 3 states. [2019-11-28 18:19:47,156 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:19:47,156 INFO L93 Difference]: Finished difference Result 312 states and 530 transitions. [2019-11-28 18:19:47,156 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:19:47,157 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 53 [2019-11-28 18:19:47,157 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:19:47,158 INFO L225 Difference]: With dead ends: 312 [2019-11-28 18:19:47,158 INFO L226 Difference]: Without dead ends: 312 [2019-11-28 18:19:47,159 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:19:47,160 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 312 states. [2019-11-28 18:19:47,164 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 312 to 251. [2019-11-28 18:19:47,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 251 states. [2019-11-28 18:19:47,166 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 251 states to 251 states and 426 transitions. [2019-11-28 18:19:47,166 INFO L78 Accepts]: Start accepts. Automaton has 251 states and 426 transitions. Word has length 53 [2019-11-28 18:19:47,166 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:19:47,166 INFO L462 AbstractCegarLoop]: Abstraction has 251 states and 426 transitions. [2019-11-28 18:19:47,166 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:19:47,167 INFO L276 IsEmpty]: Start isEmpty. Operand 251 states and 426 transitions. [2019-11-28 18:19:47,167 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-11-28 18:19:47,168 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:19:47,168 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:19:47,168 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:19:47,168 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:19:47,169 INFO L82 PathProgramCache]: Analyzing trace with hash 1221221950, now seen corresponding path program 1 times [2019-11-28 18:19:47,169 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:19:47,169 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [714643657] [2019-11-28 18:19:47,169 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:19:47,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:19:47,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:19:47,413 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [714643657] [2019-11-28 18:19:47,413 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:19:47,413 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-11-28 18:19:47,414 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1160628291] [2019-11-28 18:19:47,414 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-11-28 18:19:47,414 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:19:47,415 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-11-28 18:19:47,415 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=96, Unknown=0, NotChecked=0, Total=132 [2019-11-28 18:19:47,415 INFO L87 Difference]: Start difference. First operand 251 states and 426 transitions. Second operand 12 states. [2019-11-28 18:19:48,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:19:48,017 INFO L93 Difference]: Finished difference Result 436 states and 700 transitions. [2019-11-28 18:19:48,018 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-11-28 18:19:48,018 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 54 [2019-11-28 18:19:48,018 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:19:48,020 INFO L225 Difference]: With dead ends: 436 [2019-11-28 18:19:48,020 INFO L226 Difference]: Without dead ends: 207 [2019-11-28 18:19:48,021 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 86 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=162, Invalid=390, Unknown=0, NotChecked=0, Total=552 [2019-11-28 18:19:48,027 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 207 states. [2019-11-28 18:19:48,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 207 to 183. [2019-11-28 18:19:48,032 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 183 states. [2019-11-28 18:19:48,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 183 states to 183 states and 306 transitions. [2019-11-28 18:19:48,033 INFO L78 Accepts]: Start accepts. Automaton has 183 states and 306 transitions. Word has length 54 [2019-11-28 18:19:48,033 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:19:48,034 INFO L462 AbstractCegarLoop]: Abstraction has 183 states and 306 transitions. [2019-11-28 18:19:48,034 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-11-28 18:19:48,034 INFO L276 IsEmpty]: Start isEmpty. Operand 183 states and 306 transitions. [2019-11-28 18:19:48,035 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-11-28 18:19:48,035 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:19:48,035 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:19:48,035 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:19:48,036 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:19:48,036 INFO L82 PathProgramCache]: Analyzing trace with hash 2120402622, now seen corresponding path program 2 times [2019-11-28 18:19:48,036 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:19:48,036 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1744719607] [2019-11-28 18:19:48,039 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:19:48,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:19:48,336 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:19:48,337 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1744719607] [2019-11-28 18:19:48,337 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:19:48,337 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-11-28 18:19:48,338 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2059747811] [2019-11-28 18:19:48,338 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-11-28 18:19:48,338 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:19:48,339 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-11-28 18:19:48,339 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=129, Unknown=0, NotChecked=0, Total=156 [2019-11-28 18:19:48,339 INFO L87 Difference]: Start difference. First operand 183 states and 306 transitions. Second operand 13 states. [2019-11-28 18:19:48,905 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:19:48,906 INFO L93 Difference]: Finished difference Result 336 states and 559 transitions. [2019-11-28 18:19:48,910 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-11-28 18:19:48,910 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 54 [2019-11-28 18:19:48,911 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:19:48,912 INFO L225 Difference]: With dead ends: 336 [2019-11-28 18:19:48,912 INFO L226 Difference]: Without dead ends: 301 [2019-11-28 18:19:48,913 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 83 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=112, Invalid=488, Unknown=0, NotChecked=0, Total=600 [2019-11-28 18:19:48,914 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 301 states. [2019-11-28 18:19:48,923 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 301 to 291. [2019-11-28 18:19:48,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 291 states. [2019-11-28 18:19:48,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 291 states to 291 states and 491 transitions. [2019-11-28 18:19:48,925 INFO L78 Accepts]: Start accepts. Automaton has 291 states and 491 transitions. Word has length 54 [2019-11-28 18:19:48,925 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:19:48,925 INFO L462 AbstractCegarLoop]: Abstraction has 291 states and 491 transitions. [2019-11-28 18:19:48,925 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-11-28 18:19:48,925 INFO L276 IsEmpty]: Start isEmpty. Operand 291 states and 491 transitions. [2019-11-28 18:19:48,926 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-11-28 18:19:48,926 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:19:48,926 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:19:48,926 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:19:48,926 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:19:48,927 INFO L82 PathProgramCache]: Analyzing trace with hash 1631137646, now seen corresponding path program 3 times [2019-11-28 18:19:48,927 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:19:48,927 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1112169592] [2019-11-28 18:19:48,927 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:19:48,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 18:19:49,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 18:19:49,059 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-28 18:19:49,059 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-28 18:19:49,064 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [701] [701] ULTIMATE.startENTRY-->L779: Formula: (let ((.cse0 (store |v_#valid_49| 0 0))) (and (= 0 v_~x$read_delayed_var~0.base_6) (= v_~x$r_buff0_thd0~0_317 0) (= 0 v_~x$read_delayed_var~0.offset_6) (= v_~x$mem_tmp~0_19 0) (= 0 v_~x$r_buff1_thd2~0_153) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t1447~0.base_22| 4)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1447~0.base_22| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1447~0.base_22|) |v_ULTIMATE.start_main_~#t1447~0.offset_17| 0)) |v_#memory_int_13|) (= (select .cse0 |v_ULTIMATE.start_main_~#t1447~0.base_22|) 0) (= 0 v_~x~0_144) (= v_~x$r_buff0_thd1~0_115 0) (= |v_ULTIMATE.start_main_~#t1447~0.offset_17| 0) (= 0 v_~__unbuffered_cnt~0_78) (= v_~__unbuffered_p1_EAX~0_103 0) (= 0 v_~x$read_delayed~0_6) (< 0 |v_#StackHeapBarrier_14|) (= 0 v_~x$w_buff1_used~0_381) (= v_~x$flush_delayed~0_36 0) (= 0 |v_#NULL.base_4|) (= 0 v_~x$r_buff0_thd2~0_168) (< |v_#StackHeapBarrier_14| |v_ULTIMATE.start_main_~#t1447~0.base_22|) (= 0 v_~x$w_buff1~0_166) (= |v_#NULL.offset_4| 0) (= v_~main$tmp_guard1~0_24 0) (= v_~y~0_67 0) (= 0 v_~x$w_buff0~0_193) (= v_~x$r_buff1_thd0~0_243 0) (= v_~main$tmp_guard0~0_24 0) (= (store .cse0 |v_ULTIMATE.start_main_~#t1447~0.base_22| 1) |v_#valid_47|) (= v_~weak$$choice2~0_114 0) (= 0 v_~weak$$choice0~0_12) (= 0 v_~x$w_buff0_used~0_609) (= v_~x$r_buff1_thd1~0_167 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_49|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_193, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_44|, ~x$flush_delayed~0=v_~x$flush_delayed~0_36, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_29|, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_167, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_139|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_42|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_31|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_34|, ULTIMATE.start_main_~#t1448~0.offset=|v_ULTIMATE.start_main_~#t1448~0.offset_14|, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_103, #length=|v_#length_15|, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_317, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_29|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_31|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_19|, ~x$w_buff1~0=v_~x$w_buff1~0_166, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_28|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_381, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_153, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_37|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_32|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_31|, ~x$read_delayed_var~0.base=v_~x$read_delayed_var~0.base_6, ~weak$$choice0~0=v_~weak$$choice0~0_12, #StackHeapBarrier=|v_#StackHeapBarrier_14|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_27|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_8|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_78, ULTIMATE.start_main_~#t1448~0.base=|v_ULTIMATE.start_main_~#t1448~0.base_17|, ~x~0=v_~x~0_144, ULTIMATE.start_main_~#t1447~0.offset=|v_ULTIMATE.start_main_~#t1447~0.offset_17|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_115, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_25|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_23|, ULTIMATE.start_main_~#t1447~0.base=|v_ULTIMATE.start_main_~#t1447~0.base_22|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_24, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_40|, ~x$mem_tmp~0=v_~x$mem_tmp~0_19, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_25|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_36|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_32|, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_36|, ~y~0=v_~y~0_67, ULTIMATE.start_main_#t~ite17=|v_ULTIMATE.start_main_#t~ite17_29|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_19|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_27|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_39|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_23|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_24, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_243, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_168, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_29|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_29|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_609, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_15|, ~x$read_delayed_var~0.offset=v_~x$read_delayed_var~0.offset_6, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_17|, #valid=|v_#valid_47|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_21|, ~weak$$choice2~0=v_~weak$$choice2~0_114, ~x$read_delayed~0=v_~x$read_delayed~0_6} AuxVars[] AssignedVars[~x$w_buff0~0, ULTIMATE.start_main_#t~ite28, ~x$flush_delayed~0, #NULL.offset, ULTIMATE.start_main_#t~ite26, ~x$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_~#t1448~0.offset, ~__unbuffered_p1_EAX~0, #length, ~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ~x$w_buff1~0, ULTIMATE.start_main_#t~ite35, ~x$w_buff1_used~0, ~x$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~x$read_delayed_var~0.base, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~nondet15, ~__unbuffered_cnt~0, ULTIMATE.start_main_~#t1448~0.base, ~x~0, ULTIMATE.start_main_~#t1447~0.offset, ~x$r_buff0_thd1~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_~#t1447~0.base, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ~x$mem_tmp~0, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite30, ~y~0, ULTIMATE.start_main_#t~ite17, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ~x$r_buff1_thd0~0, ~x$r_buff0_thd2~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~x$w_buff0_used~0, ULTIMATE.start_main_#t~ite41, ~x$read_delayed_var~0.offset, ULTIMATE.start_main_#res, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ~weak$$choice2~0, ~x$read_delayed~0] because there is no mapped edge [2019-11-28 18:19:49,066 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [668] [668] L779-1-->L781: Formula: (and (= (store |v_#length_10| |v_ULTIMATE.start_main_~#t1448~0.base_10| 4) |v_#length_9|) (not (= 0 |v_ULTIMATE.start_main_~#t1448~0.base_10|)) (= |v_#valid_25| (store |v_#valid_26| |v_ULTIMATE.start_main_~#t1448~0.base_10| 1)) (= 0 (select |v_#valid_26| |v_ULTIMATE.start_main_~#t1448~0.base_10|)) (< |v_#StackHeapBarrier_7| |v_ULTIMATE.start_main_~#t1448~0.base_10|) (= 0 |v_ULTIMATE.start_main_~#t1448~0.offset_9|) (= |v_#memory_int_7| (store |v_#memory_int_8| |v_ULTIMATE.start_main_~#t1448~0.base_10| (store (select |v_#memory_int_8| |v_ULTIMATE.start_main_~#t1448~0.base_10|) |v_ULTIMATE.start_main_~#t1448~0.offset_9| 1)))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_7|, #valid=|v_#valid_26|, #memory_int=|v_#memory_int_8|, #length=|v_#length_10|} OutVars{ULTIMATE.start_main_~#t1448~0.offset=|v_ULTIMATE.start_main_~#t1448~0.offset_9|, #StackHeapBarrier=|v_#StackHeapBarrier_7|, #valid=|v_#valid_25|, #memory_int=|v_#memory_int_7|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, #length=|v_#length_9|, ULTIMATE.start_main_~#t1448~0.base=|v_ULTIMATE.start_main_~#t1448~0.base_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1448~0.offset, #valid, #memory_int, ULTIMATE.start_main_#t~nondet15, #length, ULTIMATE.start_main_~#t1448~0.base] because there is no mapped edge [2019-11-28 18:19:49,066 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [623] [623] P1ENTRY-->L4-3: Formula: (and (= |v_P1Thread1of1ForFork1_#in~arg.offset_17| v_P1Thread1of1ForFork1_~arg.offset_15) (not (= 0 v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_17)) (= v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_17 |v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_15|) (= 2 v_~x$w_buff0~0_54) (= |v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_15| (ite (not (and (not (= 0 (mod v_~x$w_buff0_used~0_216 256))) (not (= 0 (mod v_~x$w_buff1_used~0_127 256))))) 1 0)) (= v_P1Thread1of1ForFork1_~arg.base_15 |v_P1Thread1of1ForFork1_#in~arg.base_17|) (= 1 v_~x$w_buff0_used~0_216) (= v_~x$w_buff0~0_55 v_~x$w_buff1~0_48) (= v_~x$w_buff0_used~0_217 v_~x$w_buff1_used~0_127)) InVars {~x$w_buff0~0=v_~x$w_buff0~0_55, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_17|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_17|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_217} OutVars{P1Thread1of1ForFork1___VERIFIER_assert_~expression=v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_17, ~x$w_buff0~0=v_~x$w_buff0~0_54, P1Thread1of1ForFork1_~arg.offset=v_P1Thread1of1ForFork1_~arg.offset_15, P1Thread1of1ForFork1___VERIFIER_assert_#in~expression=|v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_15|, P1Thread1of1ForFork1_~arg.base=v_P1Thread1of1ForFork1_~arg.base_15, ~x$w_buff1~0=v_~x$w_buff1~0_48, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_17|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_17|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_127, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_216} AuxVars[] AssignedVars[P1Thread1of1ForFork1___VERIFIER_assert_~expression, ~x$w_buff0~0, P1Thread1of1ForFork1_~arg.offset, P1Thread1of1ForFork1___VERIFIER_assert_#in~expression, P1Thread1of1ForFork1_~arg.base, ~x$w_buff1~0, ~x$w_buff1_used~0, ~x$w_buff0_used~0] because there is no mapped edge [2019-11-28 18:19:49,069 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [650] [650] L728-2-->L728-5: Formula: (let ((.cse2 (= |P0Thread1of1ForFork0_#t~ite4_Out-1259508779| |P0Thread1of1ForFork0_#t~ite3_Out-1259508779|)) (.cse0 (= 0 (mod ~x$w_buff1_used~0_In-1259508779 256))) (.cse1 (= (mod ~x$r_buff1_thd1~0_In-1259508779 256) 0))) (or (and (not .cse0) (not .cse1) (= ~x$w_buff1~0_In-1259508779 |P0Thread1of1ForFork0_#t~ite3_Out-1259508779|) .cse2) (and (= |P0Thread1of1ForFork0_#t~ite3_Out-1259508779| ~x~0_In-1259508779) .cse2 (or .cse0 .cse1)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In-1259508779, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1259508779, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-1259508779, ~x~0=~x~0_In-1259508779} OutVars{P0Thread1of1ForFork0_#t~ite3=|P0Thread1of1ForFork0_#t~ite3_Out-1259508779|, P0Thread1of1ForFork0_#t~ite4=|P0Thread1of1ForFork0_#t~ite4_Out-1259508779|, ~x$w_buff1~0=~x$w_buff1~0_In-1259508779, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1259508779, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-1259508779, ~x~0=~x~0_In-1259508779} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite3, P0Thread1of1ForFork0_#t~ite4] because there is no mapped edge [2019-11-28 18:19:49,070 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [658] [658] L729-->L729-2: Formula: (let ((.cse0 (= (mod ~x$w_buff0_used~0_In-790376854 256) 0)) (.cse1 (= (mod ~x$r_buff0_thd1~0_In-790376854 256) 0))) (or (and (or .cse0 .cse1) (= ~x$w_buff0_used~0_In-790376854 |P0Thread1of1ForFork0_#t~ite5_Out-790376854|)) (and (not .cse0) (= |P0Thread1of1ForFork0_#t~ite5_Out-790376854| 0) (not .cse1)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-790376854, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-790376854} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out-790376854|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-790376854, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-790376854} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-11-28 18:19:49,070 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [640] [640] L730-->L730-2: Formula: (let ((.cse0 (= (mod ~x$r_buff0_thd1~0_In-663410552 256) 0)) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In-663410552 256))) (.cse2 (= 0 (mod ~x$r_buff1_thd1~0_In-663410552 256))) (.cse3 (= (mod ~x$w_buff1_used~0_In-663410552 256) 0))) (or (and (or .cse0 .cse1) (= ~x$w_buff1_used~0_In-663410552 |P0Thread1of1ForFork0_#t~ite6_Out-663410552|) (or .cse2 .cse3)) (and (= 0 |P0Thread1of1ForFork0_#t~ite6_Out-663410552|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-663410552, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-663410552, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-663410552, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-663410552} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out-663410552|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-663410552, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-663410552, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-663410552, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-663410552} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-11-28 18:19:49,071 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [647] [647] L757-->L757-2: Formula: (let ((.cse1 (= (mod ~x$r_buff0_thd2~0_In-1994167087 256) 0)) (.cse0 (= (mod ~x$w_buff0_used~0_In-1994167087 256) 0))) (or (and (not .cse0) (= 0 |P1Thread1of1ForFork1_#t~ite11_Out-1994167087|) (not .cse1)) (and (= |P1Thread1of1ForFork1_#t~ite11_Out-1994167087| ~x$w_buff0_used~0_In-1994167087) (or .cse1 .cse0)))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1994167087, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1994167087} OutVars{P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out-1994167087|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1994167087, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1994167087} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-11-28 18:19:49,071 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [652] [652] L731-->L731-2: Formula: (let ((.cse1 (= (mod ~x$w_buff0_used~0_In-546511316 256) 0)) (.cse0 (= (mod ~x$r_buff0_thd1~0_In-546511316 256) 0))) (or (and (= |P0Thread1of1ForFork0_#t~ite7_Out-546511316| ~x$r_buff0_thd1~0_In-546511316) (or .cse0 .cse1)) (and (not .cse1) (= |P0Thread1of1ForFork0_#t~ite7_Out-546511316| 0) (not .cse0)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-546511316, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-546511316} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-546511316, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out-546511316|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-546511316} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7] because there is no mapped edge [2019-11-28 18:19:49,072 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [642] [642] L732-->L732-2: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff0_used~0_In-1413675482 256))) (.cse1 (= (mod ~x$r_buff0_thd1~0_In-1413675482 256) 0)) (.cse3 (= 0 (mod ~x$r_buff1_thd1~0_In-1413675482 256))) (.cse2 (= (mod ~x$w_buff1_used~0_In-1413675482 256) 0))) (or (and (= |P0Thread1of1ForFork0_#t~ite8_Out-1413675482| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (or .cse3 .cse2) (= |P0Thread1of1ForFork0_#t~ite8_Out-1413675482| ~x$r_buff1_thd1~0_In-1413675482)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-1413675482, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1413675482, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-1413675482, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1413675482} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-1413675482, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out-1413675482|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1413675482, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-1413675482, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1413675482} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-11-28 18:19:49,072 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [681] [681] L732-2-->P0EXIT: Formula: (and (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~x$r_buff1_thd1~0_125 |v_P0Thread1of1ForFork0_#t~ite8_36|) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_40 1) v_~__unbuffered_cnt~0_39)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_36|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_40} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_35|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_39, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_125} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, ~x$r_buff1_thd1~0] because there is no mapped edge [2019-11-28 18:19:49,072 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [655] [655] L758-->L758-2: Formula: (let ((.cse0 (= 0 (mod ~x$r_buff1_thd2~0_In1469281263 256))) (.cse1 (= 0 (mod ~x$w_buff1_used~0_In1469281263 256))) (.cse2 (= (mod ~x$w_buff0_used~0_In1469281263 256) 0)) (.cse3 (= (mod ~x$r_buff0_thd2~0_In1469281263 256) 0))) (or (and (= ~x$w_buff1_used~0_In1469281263 |P1Thread1of1ForFork1_#t~ite12_Out1469281263|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P1Thread1of1ForFork1_#t~ite12_Out1469281263|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In1469281263, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In1469281263, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In1469281263, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1469281263} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In1469281263, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In1469281263, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out1469281263|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In1469281263, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1469281263} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-11-28 18:19:49,073 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [656] [656] L759-->L760: Formula: (let ((.cse1 (= (mod ~x$r_buff0_thd2~0_In-1942467726 256) 0)) (.cse0 (= ~x$r_buff0_thd2~0_In-1942467726 ~x$r_buff0_thd2~0_Out-1942467726)) (.cse2 (= 0 (mod ~x$w_buff0_used~0_In-1942467726 256)))) (or (and .cse0 .cse1) (and (= 0 ~x$r_buff0_thd2~0_Out-1942467726) (not .cse1) (not .cse2)) (and .cse0 .cse2))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1942467726, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1942467726} OutVars{P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out-1942467726|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_Out-1942467726, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1942467726} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13, ~x$r_buff0_thd2~0] because there is no mapped edge [2019-11-28 18:19:49,073 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [657] [657] L760-->L760-2: Formula: (let ((.cse3 (= (mod ~x$r_buff1_thd2~0_In-863968006 256) 0)) (.cse2 (= (mod ~x$w_buff1_used~0_In-863968006 256) 0)) (.cse1 (= (mod ~x$w_buff0_used~0_In-863968006 256) 0)) (.cse0 (= 0 (mod ~x$r_buff0_thd2~0_In-863968006 256)))) (or (and (= 0 |P1Thread1of1ForFork1_#t~ite14_Out-863968006|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |P1Thread1of1ForFork1_#t~ite14_Out-863968006| ~x$r_buff1_thd2~0_In-863968006) (or .cse3 .cse2) (or .cse1 .cse0)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-863968006, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-863968006, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-863968006, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-863968006} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-863968006, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-863968006, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-863968006, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out-863968006|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-863968006} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-11-28 18:19:49,074 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [684] [684] L760-2-->P1EXIT: Formula: (and (= v_~x$r_buff1_thd2~0_125 |v_P1Thread1of1ForFork1_#t~ite14_34|) (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_56 1) v_~__unbuffered_cnt~0_55) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_56, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_34|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_125, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_33|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~x$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-11-28 18:19:49,074 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [586] [586] L781-1-->L787: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_6 256))) (= v_~main$tmp_guard0~0_6 (ite (= 0 (ite (= 2 v_~__unbuffered_cnt~0_11) 1 0)) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_11} OutVars{ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_11, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet16, ~main$tmp_guard0~0] because there is no mapped edge [2019-11-28 18:19:49,074 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [651] [651] L787-2-->L787-5: Formula: (let ((.cse0 (= |ULTIMATE.start_main_#t~ite17_Out1361323342| |ULTIMATE.start_main_#t~ite18_Out1361323342|)) (.cse2 (= (mod ~x$r_buff1_thd0~0_In1361323342 256) 0)) (.cse1 (= (mod ~x$w_buff1_used~0_In1361323342 256) 0))) (or (and .cse0 (or .cse1 .cse2) (= |ULTIMATE.start_main_#t~ite17_Out1361323342| ~x~0_In1361323342)) (and .cse0 (= |ULTIMATE.start_main_#t~ite17_Out1361323342| ~x$w_buff1~0_In1361323342) (not .cse2) (not .cse1)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In1361323342, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1361323342, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1361323342, ~x~0=~x~0_In1361323342} OutVars{ULTIMATE.start_main_#t~ite17=|ULTIMATE.start_main_#t~ite17_Out1361323342|, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out1361323342|, ~x$w_buff1~0=~x$w_buff1~0_In1361323342, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1361323342, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1361323342, ~x~0=~x~0_In1361323342} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite17, ULTIMATE.start_main_#t~ite18] because there is no mapped edge [2019-11-28 18:19:49,075 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [648] [648] L788-->L788-2: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff0_thd0~0_In-1729981687 256))) (.cse0 (= (mod ~x$w_buff0_used~0_In-1729981687 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite19_Out-1729981687| ~x$w_buff0_used~0_In-1729981687)) (and (= |ULTIMATE.start_main_#t~ite19_Out-1729981687| 0) (not .cse1) (not .cse0)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1729981687, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1729981687} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1729981687, ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out-1729981687|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1729981687} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-11-28 18:19:49,075 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [643] [643] L789-->L789-2: Formula: (let ((.cse3 (= 0 (mod ~x$r_buff1_thd0~0_In2090176556 256))) (.cse2 (= 0 (mod ~x$w_buff1_used~0_In2090176556 256))) (.cse0 (= (mod ~x$r_buff0_thd0~0_In2090176556 256) 0)) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In2090176556 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~x$w_buff1_used~0_In2090176556 |ULTIMATE.start_main_#t~ite20_Out2090176556|)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1))) (= 0 |ULTIMATE.start_main_#t~ite20_Out2090176556|)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In2090176556, ~x$w_buff1_used~0=~x$w_buff1_used~0_In2090176556, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In2090176556, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2090176556} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In2090176556, ~x$w_buff1_used~0=~x$w_buff1_used~0_In2090176556, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out2090176556|, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In2090176556, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2090176556} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-11-28 18:19:49,076 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [661] [661] L790-->L790-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff0_used~0_In-72501470 256))) (.cse0 (= (mod ~x$r_buff0_thd0~0_In-72501470 256) 0))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite21_Out-72501470| 0) (not .cse1)) (and (or .cse1 .cse0) (= |ULTIMATE.start_main_#t~ite21_Out-72501470| ~x$r_buff0_thd0~0_In-72501470)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-72501470, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-72501470} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-72501470, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out-72501470|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-72501470} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-11-28 18:19:49,076 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [653] [653] L791-->L791-2: Formula: (let ((.cse1 (= (mod ~x$r_buff0_thd0~0_In1612781311 256) 0)) (.cse0 (= 0 (mod ~x$w_buff0_used~0_In1612781311 256))) (.cse2 (= (mod ~x$w_buff1_used~0_In1612781311 256) 0)) (.cse3 (= 0 (mod ~x$r_buff1_thd0~0_In1612781311 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |ULTIMATE.start_main_#t~ite22_Out1612781311| 0)) (and (= ~x$r_buff1_thd0~0_In1612781311 |ULTIMATE.start_main_#t~ite22_Out1612781311|) (or .cse1 .cse0) (or .cse2 .cse3)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In1612781311, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1612781311, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1612781311, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1612781311} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In1612781311, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1612781311, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1612781311, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out1612781311|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1612781311} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-11-28 18:19:49,078 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [687] [687] L800-->L800-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In504911359 256)))) (or (and (= |ULTIMATE.start_main_#t~ite31_In504911359| |ULTIMATE.start_main_#t~ite31_Out504911359|) (not .cse0) (= ~x$w_buff1~0_In504911359 |ULTIMATE.start_main_#t~ite32_Out504911359|)) (and (let ((.cse1 (= 0 (mod ~x$r_buff0_thd0~0_In504911359 256)))) (or (and (= (mod ~x$r_buff1_thd0~0_In504911359 256) 0) .cse1) (and (= 0 (mod ~x$w_buff1_used~0_In504911359 256)) .cse1) (= 0 (mod ~x$w_buff0_used~0_In504911359 256)))) (= ~x$w_buff1~0_In504911359 |ULTIMATE.start_main_#t~ite31_Out504911359|) (= |ULTIMATE.start_main_#t~ite32_Out504911359| |ULTIMATE.start_main_#t~ite31_Out504911359|) .cse0))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In504911359, ~x$w_buff1~0=~x$w_buff1~0_In504911359, ~x$w_buff1_used~0=~x$w_buff1_used~0_In504911359, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In504911359, ~weak$$choice2~0=~weak$$choice2~0_In504911359, ULTIMATE.start_main_#t~ite31=|ULTIMATE.start_main_#t~ite31_In504911359|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In504911359} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In504911359, ~x$w_buff1~0=~x$w_buff1~0_In504911359, ~x$w_buff1_used~0=~x$w_buff1_used~0_In504911359, ULTIMATE.start_main_#t~ite31=|ULTIMATE.start_main_#t~ite31_Out504911359|, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In504911359, ~weak$$choice2~0=~weak$$choice2~0_In504911359, ULTIMATE.start_main_#t~ite32=|ULTIMATE.start_main_#t~ite32_Out504911359|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In504911359} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite32] because there is no mapped edge [2019-11-28 18:19:49,080 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [628] [628] L803-->L804: Formula: (and (= v_~x$r_buff0_thd0~0_125 v_~x$r_buff0_thd0~0_124) (not (= (mod v_~weak$$choice2~0_35 256) 0))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_125, ~weak$$choice2~0=v_~weak$$choice2~0_35} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_124, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_8|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_10|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_19|, ~weak$$choice2~0=v_~weak$$choice2~0_35} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~ite39] because there is no mapped edge [2019-11-28 18:19:49,081 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [682] [682] L806-->L809-1: Formula: (and (not (= (mod v_~x$flush_delayed~0_27 256) 0)) (= v_~x$mem_tmp~0_15 v_~x~0_118) (= v_~x$flush_delayed~0_26 0) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6| (mod v_~main$tmp_guard1~0_15 256))) InVars {~x$flush_delayed~0=v_~x$flush_delayed~0_27, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_15, ~x$mem_tmp~0=v_~x$mem_tmp~0_15} OutVars{~x$flush_delayed~0=v_~x$flush_delayed~0_26, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_15, ~x$mem_tmp~0=v_~x$mem_tmp~0_15, ~x~0=v_~x~0_118, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_21|, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[~x$flush_delayed~0, ~x~0, ULTIMATE.start_main_#t~ite45, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-11-28 18:19:49,081 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [679] [679] L809-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-11-28 18:19:49,174 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 06:19:49 BasicIcfg [2019-11-28 18:19:49,175 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-28 18:19:49,175 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-28 18:19:49,175 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-28 18:19:49,176 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-28 18:19:49,176 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:19:33" (3/4) ... [2019-11-28 18:19:49,178 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-28 18:19:49,179 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [701] [701] ULTIMATE.startENTRY-->L779: Formula: (let ((.cse0 (store |v_#valid_49| 0 0))) (and (= 0 v_~x$read_delayed_var~0.base_6) (= v_~x$r_buff0_thd0~0_317 0) (= 0 v_~x$read_delayed_var~0.offset_6) (= v_~x$mem_tmp~0_19 0) (= 0 v_~x$r_buff1_thd2~0_153) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t1447~0.base_22| 4)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1447~0.base_22| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1447~0.base_22|) |v_ULTIMATE.start_main_~#t1447~0.offset_17| 0)) |v_#memory_int_13|) (= (select .cse0 |v_ULTIMATE.start_main_~#t1447~0.base_22|) 0) (= 0 v_~x~0_144) (= v_~x$r_buff0_thd1~0_115 0) (= |v_ULTIMATE.start_main_~#t1447~0.offset_17| 0) (= 0 v_~__unbuffered_cnt~0_78) (= v_~__unbuffered_p1_EAX~0_103 0) (= 0 v_~x$read_delayed~0_6) (< 0 |v_#StackHeapBarrier_14|) (= 0 v_~x$w_buff1_used~0_381) (= v_~x$flush_delayed~0_36 0) (= 0 |v_#NULL.base_4|) (= 0 v_~x$r_buff0_thd2~0_168) (< |v_#StackHeapBarrier_14| |v_ULTIMATE.start_main_~#t1447~0.base_22|) (= 0 v_~x$w_buff1~0_166) (= |v_#NULL.offset_4| 0) (= v_~main$tmp_guard1~0_24 0) (= v_~y~0_67 0) (= 0 v_~x$w_buff0~0_193) (= v_~x$r_buff1_thd0~0_243 0) (= v_~main$tmp_guard0~0_24 0) (= (store .cse0 |v_ULTIMATE.start_main_~#t1447~0.base_22| 1) |v_#valid_47|) (= v_~weak$$choice2~0_114 0) (= 0 v_~weak$$choice0~0_12) (= 0 v_~x$w_buff0_used~0_609) (= v_~x$r_buff1_thd1~0_167 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_49|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{~x$w_buff0~0=v_~x$w_buff0~0_193, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_44|, ~x$flush_delayed~0=v_~x$flush_delayed~0_36, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_29|, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_167, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_139|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_42|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_31|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_34|, ULTIMATE.start_main_~#t1448~0.offset=|v_ULTIMATE.start_main_~#t1448~0.offset_14|, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_103, #length=|v_#length_15|, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_317, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_29|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_31|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_19|, ~x$w_buff1~0=v_~x$w_buff1~0_166, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_28|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_381, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_153, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_37|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_32|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_31|, ~x$read_delayed_var~0.base=v_~x$read_delayed_var~0.base_6, ~weak$$choice0~0=v_~weak$$choice0~0_12, #StackHeapBarrier=|v_#StackHeapBarrier_14|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_27|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_8|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_78, ULTIMATE.start_main_~#t1448~0.base=|v_ULTIMATE.start_main_~#t1448~0.base_17|, ~x~0=v_~x~0_144, ULTIMATE.start_main_~#t1447~0.offset=|v_ULTIMATE.start_main_~#t1447~0.offset_17|, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_115, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_25|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_23|, ULTIMATE.start_main_~#t1447~0.base=|v_ULTIMATE.start_main_~#t1447~0.base_22|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_24, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_40|, ~x$mem_tmp~0=v_~x$mem_tmp~0_19, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_25|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_36|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_32|, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_36|, ~y~0=v_~y~0_67, ULTIMATE.start_main_#t~ite17=|v_ULTIMATE.start_main_#t~ite17_29|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_19|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_27|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_39|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_23|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_24, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_243, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_168, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_29|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_29|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_609, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_15|, ~x$read_delayed_var~0.offset=v_~x$read_delayed_var~0.offset_6, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_17|, #valid=|v_#valid_47|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_21|, ~weak$$choice2~0=v_~weak$$choice2~0_114, ~x$read_delayed~0=v_~x$read_delayed~0_6} AuxVars[] AssignedVars[~x$w_buff0~0, ULTIMATE.start_main_#t~ite28, ~x$flush_delayed~0, #NULL.offset, ULTIMATE.start_main_#t~ite26, ~x$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_~#t1448~0.offset, ~__unbuffered_p1_EAX~0, #length, ~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ~x$w_buff1~0, ULTIMATE.start_main_#t~ite35, ~x$w_buff1_used~0, ~x$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~x$read_delayed_var~0.base, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~nondet15, ~__unbuffered_cnt~0, ULTIMATE.start_main_~#t1448~0.base, ~x~0, ULTIMATE.start_main_~#t1447~0.offset, ~x$r_buff0_thd1~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_~#t1447~0.base, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ~x$mem_tmp~0, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite30, ~y~0, ULTIMATE.start_main_#t~ite17, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ~x$r_buff1_thd0~0, ~x$r_buff0_thd2~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~x$w_buff0_used~0, ULTIMATE.start_main_#t~ite41, ~x$read_delayed_var~0.offset, ULTIMATE.start_main_#res, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ~weak$$choice2~0, ~x$read_delayed~0] because there is no mapped edge [2019-11-28 18:19:49,179 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [668] [668] L779-1-->L781: Formula: (and (= (store |v_#length_10| |v_ULTIMATE.start_main_~#t1448~0.base_10| 4) |v_#length_9|) (not (= 0 |v_ULTIMATE.start_main_~#t1448~0.base_10|)) (= |v_#valid_25| (store |v_#valid_26| |v_ULTIMATE.start_main_~#t1448~0.base_10| 1)) (= 0 (select |v_#valid_26| |v_ULTIMATE.start_main_~#t1448~0.base_10|)) (< |v_#StackHeapBarrier_7| |v_ULTIMATE.start_main_~#t1448~0.base_10|) (= 0 |v_ULTIMATE.start_main_~#t1448~0.offset_9|) (= |v_#memory_int_7| (store |v_#memory_int_8| |v_ULTIMATE.start_main_~#t1448~0.base_10| (store (select |v_#memory_int_8| |v_ULTIMATE.start_main_~#t1448~0.base_10|) |v_ULTIMATE.start_main_~#t1448~0.offset_9| 1)))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_7|, #valid=|v_#valid_26|, #memory_int=|v_#memory_int_8|, #length=|v_#length_10|} OutVars{ULTIMATE.start_main_~#t1448~0.offset=|v_ULTIMATE.start_main_~#t1448~0.offset_9|, #StackHeapBarrier=|v_#StackHeapBarrier_7|, #valid=|v_#valid_25|, #memory_int=|v_#memory_int_7|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, #length=|v_#length_9|, ULTIMATE.start_main_~#t1448~0.base=|v_ULTIMATE.start_main_~#t1448~0.base_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1448~0.offset, #valid, #memory_int, ULTIMATE.start_main_#t~nondet15, #length, ULTIMATE.start_main_~#t1448~0.base] because there is no mapped edge [2019-11-28 18:19:49,179 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [623] [623] P1ENTRY-->L4-3: Formula: (and (= |v_P1Thread1of1ForFork1_#in~arg.offset_17| v_P1Thread1of1ForFork1_~arg.offset_15) (not (= 0 v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_17)) (= v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_17 |v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_15|) (= 2 v_~x$w_buff0~0_54) (= |v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_15| (ite (not (and (not (= 0 (mod v_~x$w_buff0_used~0_216 256))) (not (= 0 (mod v_~x$w_buff1_used~0_127 256))))) 1 0)) (= v_P1Thread1of1ForFork1_~arg.base_15 |v_P1Thread1of1ForFork1_#in~arg.base_17|) (= 1 v_~x$w_buff0_used~0_216) (= v_~x$w_buff0~0_55 v_~x$w_buff1~0_48) (= v_~x$w_buff0_used~0_217 v_~x$w_buff1_used~0_127)) InVars {~x$w_buff0~0=v_~x$w_buff0~0_55, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_17|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_17|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_217} OutVars{P1Thread1of1ForFork1___VERIFIER_assert_~expression=v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_17, ~x$w_buff0~0=v_~x$w_buff0~0_54, P1Thread1of1ForFork1_~arg.offset=v_P1Thread1of1ForFork1_~arg.offset_15, P1Thread1of1ForFork1___VERIFIER_assert_#in~expression=|v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_15|, P1Thread1of1ForFork1_~arg.base=v_P1Thread1of1ForFork1_~arg.base_15, ~x$w_buff1~0=v_~x$w_buff1~0_48, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_17|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_17|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_127, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_216} AuxVars[] AssignedVars[P1Thread1of1ForFork1___VERIFIER_assert_~expression, ~x$w_buff0~0, P1Thread1of1ForFork1_~arg.offset, P1Thread1of1ForFork1___VERIFIER_assert_#in~expression, P1Thread1of1ForFork1_~arg.base, ~x$w_buff1~0, ~x$w_buff1_used~0, ~x$w_buff0_used~0] because there is no mapped edge [2019-11-28 18:19:49,180 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [650] [650] L728-2-->L728-5: Formula: (let ((.cse2 (= |P0Thread1of1ForFork0_#t~ite4_Out-1259508779| |P0Thread1of1ForFork0_#t~ite3_Out-1259508779|)) (.cse0 (= 0 (mod ~x$w_buff1_used~0_In-1259508779 256))) (.cse1 (= (mod ~x$r_buff1_thd1~0_In-1259508779 256) 0))) (or (and (not .cse0) (not .cse1) (= ~x$w_buff1~0_In-1259508779 |P0Thread1of1ForFork0_#t~ite3_Out-1259508779|) .cse2) (and (= |P0Thread1of1ForFork0_#t~ite3_Out-1259508779| ~x~0_In-1259508779) .cse2 (or .cse0 .cse1)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In-1259508779, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1259508779, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-1259508779, ~x~0=~x~0_In-1259508779} OutVars{P0Thread1of1ForFork0_#t~ite3=|P0Thread1of1ForFork0_#t~ite3_Out-1259508779|, P0Thread1of1ForFork0_#t~ite4=|P0Thread1of1ForFork0_#t~ite4_Out-1259508779|, ~x$w_buff1~0=~x$w_buff1~0_In-1259508779, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1259508779, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-1259508779, ~x~0=~x~0_In-1259508779} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite3, P0Thread1of1ForFork0_#t~ite4] because there is no mapped edge [2019-11-28 18:19:49,180 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [658] [658] L729-->L729-2: Formula: (let ((.cse0 (= (mod ~x$w_buff0_used~0_In-790376854 256) 0)) (.cse1 (= (mod ~x$r_buff0_thd1~0_In-790376854 256) 0))) (or (and (or .cse0 .cse1) (= ~x$w_buff0_used~0_In-790376854 |P0Thread1of1ForFork0_#t~ite5_Out-790376854|)) (and (not .cse0) (= |P0Thread1of1ForFork0_#t~ite5_Out-790376854| 0) (not .cse1)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-790376854, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-790376854} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out-790376854|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-790376854, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-790376854} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-11-28 18:19:49,181 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [640] [640] L730-->L730-2: Formula: (let ((.cse0 (= (mod ~x$r_buff0_thd1~0_In-663410552 256) 0)) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In-663410552 256))) (.cse2 (= 0 (mod ~x$r_buff1_thd1~0_In-663410552 256))) (.cse3 (= (mod ~x$w_buff1_used~0_In-663410552 256) 0))) (or (and (or .cse0 .cse1) (= ~x$w_buff1_used~0_In-663410552 |P0Thread1of1ForFork0_#t~ite6_Out-663410552|) (or .cse2 .cse3)) (and (= 0 |P0Thread1of1ForFork0_#t~ite6_Out-663410552|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-663410552, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-663410552, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-663410552, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-663410552} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out-663410552|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-663410552, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-663410552, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-663410552, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-663410552} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-11-28 18:19:49,181 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [647] [647] L757-->L757-2: Formula: (let ((.cse1 (= (mod ~x$r_buff0_thd2~0_In-1994167087 256) 0)) (.cse0 (= (mod ~x$w_buff0_used~0_In-1994167087 256) 0))) (or (and (not .cse0) (= 0 |P1Thread1of1ForFork1_#t~ite11_Out-1994167087|) (not .cse1)) (and (= |P1Thread1of1ForFork1_#t~ite11_Out-1994167087| ~x$w_buff0_used~0_In-1994167087) (or .cse1 .cse0)))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1994167087, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1994167087} OutVars{P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out-1994167087|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1994167087, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1994167087} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-11-28 18:19:49,182 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [652] [652] L731-->L731-2: Formula: (let ((.cse1 (= (mod ~x$w_buff0_used~0_In-546511316 256) 0)) (.cse0 (= (mod ~x$r_buff0_thd1~0_In-546511316 256) 0))) (or (and (= |P0Thread1of1ForFork0_#t~ite7_Out-546511316| ~x$r_buff0_thd1~0_In-546511316) (or .cse0 .cse1)) (and (not .cse1) (= |P0Thread1of1ForFork0_#t~ite7_Out-546511316| 0) (not .cse0)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-546511316, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-546511316} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-546511316, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out-546511316|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-546511316} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7] because there is no mapped edge [2019-11-28 18:19:49,182 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [642] [642] L732-->L732-2: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff0_used~0_In-1413675482 256))) (.cse1 (= (mod ~x$r_buff0_thd1~0_In-1413675482 256) 0)) (.cse3 (= 0 (mod ~x$r_buff1_thd1~0_In-1413675482 256))) (.cse2 (= (mod ~x$w_buff1_used~0_In-1413675482 256) 0))) (or (and (= |P0Thread1of1ForFork0_#t~ite8_Out-1413675482| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (or .cse3 .cse2) (= |P0Thread1of1ForFork0_#t~ite8_Out-1413675482| ~x$r_buff1_thd1~0_In-1413675482)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-1413675482, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1413675482, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-1413675482, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1413675482} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-1413675482, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out-1413675482|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1413675482, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-1413675482, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1413675482} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-11-28 18:19:49,182 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [681] [681] L732-2-->P0EXIT: Formula: (and (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~x$r_buff1_thd1~0_125 |v_P0Thread1of1ForFork0_#t~ite8_36|) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_40 1) v_~__unbuffered_cnt~0_39)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_36|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_40} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_35|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_39, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_125} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, ~x$r_buff1_thd1~0] because there is no mapped edge [2019-11-28 18:19:49,182 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [655] [655] L758-->L758-2: Formula: (let ((.cse0 (= 0 (mod ~x$r_buff1_thd2~0_In1469281263 256))) (.cse1 (= 0 (mod ~x$w_buff1_used~0_In1469281263 256))) (.cse2 (= (mod ~x$w_buff0_used~0_In1469281263 256) 0)) (.cse3 (= (mod ~x$r_buff0_thd2~0_In1469281263 256) 0))) (or (and (= ~x$w_buff1_used~0_In1469281263 |P1Thread1of1ForFork1_#t~ite12_Out1469281263|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P1Thread1of1ForFork1_#t~ite12_Out1469281263|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In1469281263, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In1469281263, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In1469281263, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1469281263} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In1469281263, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In1469281263, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out1469281263|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In1469281263, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1469281263} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-11-28 18:19:49,182 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [656] [656] L759-->L760: Formula: (let ((.cse1 (= (mod ~x$r_buff0_thd2~0_In-1942467726 256) 0)) (.cse0 (= ~x$r_buff0_thd2~0_In-1942467726 ~x$r_buff0_thd2~0_Out-1942467726)) (.cse2 (= 0 (mod ~x$w_buff0_used~0_In-1942467726 256)))) (or (and .cse0 .cse1) (and (= 0 ~x$r_buff0_thd2~0_Out-1942467726) (not .cse1) (not .cse2)) (and .cse0 .cse2))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1942467726, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1942467726} OutVars{P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out-1942467726|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_Out-1942467726, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1942467726} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13, ~x$r_buff0_thd2~0] because there is no mapped edge [2019-11-28 18:19:49,183 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [657] [657] L760-->L760-2: Formula: (let ((.cse3 (= (mod ~x$r_buff1_thd2~0_In-863968006 256) 0)) (.cse2 (= (mod ~x$w_buff1_used~0_In-863968006 256) 0)) (.cse1 (= (mod ~x$w_buff0_used~0_In-863968006 256) 0)) (.cse0 (= 0 (mod ~x$r_buff0_thd2~0_In-863968006 256)))) (or (and (= 0 |P1Thread1of1ForFork1_#t~ite14_Out-863968006|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |P1Thread1of1ForFork1_#t~ite14_Out-863968006| ~x$r_buff1_thd2~0_In-863968006) (or .cse3 .cse2) (or .cse1 .cse0)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-863968006, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-863968006, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-863968006, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-863968006} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-863968006, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-863968006, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-863968006, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out-863968006|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-863968006} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-11-28 18:19:49,183 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [684] [684] L760-2-->P1EXIT: Formula: (and (= v_~x$r_buff1_thd2~0_125 |v_P1Thread1of1ForFork1_#t~ite14_34|) (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_56 1) v_~__unbuffered_cnt~0_55) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_56, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_34|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_125, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_33|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~x$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-11-28 18:19:49,183 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [586] [586] L781-1-->L787: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_6 256))) (= v_~main$tmp_guard0~0_6 (ite (= 0 (ite (= 2 v_~__unbuffered_cnt~0_11) 1 0)) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_11} OutVars{ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_11, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet16, ~main$tmp_guard0~0] because there is no mapped edge [2019-11-28 18:19:49,183 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [651] [651] L787-2-->L787-5: Formula: (let ((.cse0 (= |ULTIMATE.start_main_#t~ite17_Out1361323342| |ULTIMATE.start_main_#t~ite18_Out1361323342|)) (.cse2 (= (mod ~x$r_buff1_thd0~0_In1361323342 256) 0)) (.cse1 (= (mod ~x$w_buff1_used~0_In1361323342 256) 0))) (or (and .cse0 (or .cse1 .cse2) (= |ULTIMATE.start_main_#t~ite17_Out1361323342| ~x~0_In1361323342)) (and .cse0 (= |ULTIMATE.start_main_#t~ite17_Out1361323342| ~x$w_buff1~0_In1361323342) (not .cse2) (not .cse1)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In1361323342, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1361323342, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1361323342, ~x~0=~x~0_In1361323342} OutVars{ULTIMATE.start_main_#t~ite17=|ULTIMATE.start_main_#t~ite17_Out1361323342|, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out1361323342|, ~x$w_buff1~0=~x$w_buff1~0_In1361323342, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1361323342, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1361323342, ~x~0=~x~0_In1361323342} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite17, ULTIMATE.start_main_#t~ite18] because there is no mapped edge [2019-11-28 18:19:49,184 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [648] [648] L788-->L788-2: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff0_thd0~0_In-1729981687 256))) (.cse0 (= (mod ~x$w_buff0_used~0_In-1729981687 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite19_Out-1729981687| ~x$w_buff0_used~0_In-1729981687)) (and (= |ULTIMATE.start_main_#t~ite19_Out-1729981687| 0) (not .cse1) (not .cse0)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1729981687, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1729981687} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1729981687, ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out-1729981687|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1729981687} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-11-28 18:19:49,184 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [643] [643] L789-->L789-2: Formula: (let ((.cse3 (= 0 (mod ~x$r_buff1_thd0~0_In2090176556 256))) (.cse2 (= 0 (mod ~x$w_buff1_used~0_In2090176556 256))) (.cse0 (= (mod ~x$r_buff0_thd0~0_In2090176556 256) 0)) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In2090176556 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~x$w_buff1_used~0_In2090176556 |ULTIMATE.start_main_#t~ite20_Out2090176556|)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1))) (= 0 |ULTIMATE.start_main_#t~ite20_Out2090176556|)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In2090176556, ~x$w_buff1_used~0=~x$w_buff1_used~0_In2090176556, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In2090176556, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2090176556} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In2090176556, ~x$w_buff1_used~0=~x$w_buff1_used~0_In2090176556, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out2090176556|, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In2090176556, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2090176556} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-11-28 18:19:49,184 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [661] [661] L790-->L790-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff0_used~0_In-72501470 256))) (.cse0 (= (mod ~x$r_buff0_thd0~0_In-72501470 256) 0))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite21_Out-72501470| 0) (not .cse1)) (and (or .cse1 .cse0) (= |ULTIMATE.start_main_#t~ite21_Out-72501470| ~x$r_buff0_thd0~0_In-72501470)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-72501470, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-72501470} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-72501470, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out-72501470|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-72501470} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-11-28 18:19:49,185 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [653] [653] L791-->L791-2: Formula: (let ((.cse1 (= (mod ~x$r_buff0_thd0~0_In1612781311 256) 0)) (.cse0 (= 0 (mod ~x$w_buff0_used~0_In1612781311 256))) (.cse2 (= (mod ~x$w_buff1_used~0_In1612781311 256) 0)) (.cse3 (= 0 (mod ~x$r_buff1_thd0~0_In1612781311 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |ULTIMATE.start_main_#t~ite22_Out1612781311| 0)) (and (= ~x$r_buff1_thd0~0_In1612781311 |ULTIMATE.start_main_#t~ite22_Out1612781311|) (or .cse1 .cse0) (or .cse2 .cse3)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In1612781311, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1612781311, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1612781311, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1612781311} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In1612781311, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1612781311, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1612781311, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out1612781311|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1612781311} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-11-28 18:19:49,186 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [687] [687] L800-->L800-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In504911359 256)))) (or (and (= |ULTIMATE.start_main_#t~ite31_In504911359| |ULTIMATE.start_main_#t~ite31_Out504911359|) (not .cse0) (= ~x$w_buff1~0_In504911359 |ULTIMATE.start_main_#t~ite32_Out504911359|)) (and (let ((.cse1 (= 0 (mod ~x$r_buff0_thd0~0_In504911359 256)))) (or (and (= (mod ~x$r_buff1_thd0~0_In504911359 256) 0) .cse1) (and (= 0 (mod ~x$w_buff1_used~0_In504911359 256)) .cse1) (= 0 (mod ~x$w_buff0_used~0_In504911359 256)))) (= ~x$w_buff1~0_In504911359 |ULTIMATE.start_main_#t~ite31_Out504911359|) (= |ULTIMATE.start_main_#t~ite32_Out504911359| |ULTIMATE.start_main_#t~ite31_Out504911359|) .cse0))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In504911359, ~x$w_buff1~0=~x$w_buff1~0_In504911359, ~x$w_buff1_used~0=~x$w_buff1_used~0_In504911359, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In504911359, ~weak$$choice2~0=~weak$$choice2~0_In504911359, ULTIMATE.start_main_#t~ite31=|ULTIMATE.start_main_#t~ite31_In504911359|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In504911359} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In504911359, ~x$w_buff1~0=~x$w_buff1~0_In504911359, ~x$w_buff1_used~0=~x$w_buff1_used~0_In504911359, ULTIMATE.start_main_#t~ite31=|ULTIMATE.start_main_#t~ite31_Out504911359|, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In504911359, ~weak$$choice2~0=~weak$$choice2~0_In504911359, ULTIMATE.start_main_#t~ite32=|ULTIMATE.start_main_#t~ite32_Out504911359|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In504911359} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite32] because there is no mapped edge [2019-11-28 18:19:49,188 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [628] [628] L803-->L804: Formula: (and (= v_~x$r_buff0_thd0~0_125 v_~x$r_buff0_thd0~0_124) (not (= (mod v_~weak$$choice2~0_35 256) 0))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_125, ~weak$$choice2~0=v_~weak$$choice2~0_35} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_124, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_8|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_10|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_19|, ~weak$$choice2~0=v_~weak$$choice2~0_35} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~ite39] because there is no mapped edge [2019-11-28 18:19:49,188 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [682] [682] L806-->L809-1: Formula: (and (not (= (mod v_~x$flush_delayed~0_27 256) 0)) (= v_~x$mem_tmp~0_15 v_~x~0_118) (= v_~x$flush_delayed~0_26 0) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6| (mod v_~main$tmp_guard1~0_15 256))) InVars {~x$flush_delayed~0=v_~x$flush_delayed~0_27, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_15, ~x$mem_tmp~0=v_~x$mem_tmp~0_15} OutVars{~x$flush_delayed~0=v_~x$flush_delayed~0_26, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_15, ~x$mem_tmp~0=v_~x$mem_tmp~0_15, ~x~0=v_~x~0_118, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_21|, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[~x$flush_delayed~0, ~x~0, ULTIMATE.start_main_#t~ite45, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-11-28 18:19:49,188 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [679] [679] L809-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-11-28 18:19:49,295 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2019-11-28 18:19:49,297 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-28 18:19:49,299 INFO L168 Benchmark]: Toolchain (without parser) took 17174.21 ms. Allocated memory was 1.0 GB in the beginning and 1.4 GB in the end (delta: 405.8 MB). Free memory was 960.4 MB in the beginning and 898.9 MB in the end (delta: 61.5 MB). Peak memory consumption was 467.3 MB. Max. memory is 11.5 GB. [2019-11-28 18:19:49,300 INFO L168 Benchmark]: CDTParser took 0.94 ms. Allocated memory is still 1.0 GB. Free memory is still 987.2 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 18:19:49,301 INFO L168 Benchmark]: CACSL2BoogieTranslator took 898.80 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 163.6 MB). Free memory was 955.0 MB in the beginning and 1.1 GB in the end (delta: -170.1 MB). Peak memory consumption was 20.5 MB. Max. memory is 11.5 GB. [2019-11-28 18:19:49,301 INFO L168 Benchmark]: Boogie Procedure Inliner took 75.15 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.6 MB). Peak memory consumption was 6.6 MB. Max. memory is 11.5 GB. [2019-11-28 18:19:49,302 INFO L168 Benchmark]: Boogie Preprocessor took 49.73 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 18:19:49,302 INFO L168 Benchmark]: RCFGBuilder took 832.56 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 45.2 MB). Peak memory consumption was 45.2 MB. Max. memory is 11.5 GB. [2019-11-28 18:19:49,303 INFO L168 Benchmark]: TraceAbstraction took 15190.78 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 242.2 MB). Free memory was 1.1 GB in the beginning and 920.3 MB in the end (delta: 152.9 MB). Peak memory consumption was 395.1 MB. Max. memory is 11.5 GB. [2019-11-28 18:19:49,304 INFO L168 Benchmark]: Witness Printer took 121.59 ms. Allocated memory is still 1.4 GB. Free memory was 920.3 MB in the beginning and 898.9 MB in the end (delta: 21.5 MB). Peak memory consumption was 21.5 MB. Max. memory is 11.5 GB. [2019-11-28 18:19:49,308 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.94 ms. Allocated memory is still 1.0 GB. Free memory is still 987.2 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 898.80 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 163.6 MB). Free memory was 955.0 MB in the beginning and 1.1 GB in the end (delta: -170.1 MB). Peak memory consumption was 20.5 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 75.15 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.6 MB). Peak memory consumption was 6.6 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 49.73 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 832.56 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 45.2 MB). Peak memory consumption was 45.2 MB. Max. memory is 11.5 GB. * TraceAbstraction took 15190.78 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 242.2 MB). Free memory was 1.1 GB in the beginning and 920.3 MB in the end (delta: 152.9 MB). Peak memory consumption was 395.1 MB. Max. memory is 11.5 GB. * Witness Printer took 121.59 ms. Allocated memory is still 1.4 GB. Free memory was 920.3 MB in the beginning and 898.9 MB in the end (delta: 21.5 MB). Peak memory consumption was 21.5 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 4.8s, 146 ProgramPointsBefore, 78 ProgramPointsAfterwards, 180 TransitionsBefore, 90 TransitionsAfterwards, 10378 CoEnabledTransitionPairs, 7 FixpointIterations, 28 TrivialSequentialCompositions, 36 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 36 ConcurrentYvCompositions, 25 ChoiceCompositions, 3816 VarBasedMoverChecksPositive, 194 VarBasedMoverChecksNegative, 52 SemBasedMoverChecksPositive, 191 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 1.2s, 0 MoverChecksTotal, 46078 CheckedPairsTotal, 100 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L779] FCALL, FORK 0 pthread_create(&t1447, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L781] FCALL, FORK 0 pthread_create(&t1448, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0] [L747] 2 x$r_buff1_thd0 = x$r_buff0_thd0 [L748] 2 x$r_buff1_thd1 = x$r_buff0_thd1 [L749] 2 x$r_buff1_thd2 = x$r_buff0_thd2 [L750] 2 x$r_buff0_thd2 = (_Bool)1 [L753] 2 __unbuffered_p1_EAX = y VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=0] [L756] EXPR 2 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=0] [L722] 1 y = 1 [L725] 1 x = 1 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L728] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1] [L728] 1 x = x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) [L729] 1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used [L730] 1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used [L756] 2 x = x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) [L757] 2 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used [L731] 1 x$r_buff0_thd1 = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 [L758] 2 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used [L787] EXPR 0 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [\result={0:0}, __unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L787] 0 x = x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) [L788] 0 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used [L789] 0 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used [L790] 0 x$r_buff0_thd0 = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 [L791] 0 x$r_buff1_thd0 = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 [L794] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L795] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L796] 0 x$flush_delayed = weak$$choice2 [L797] 0 x$mem_tmp = x VAL [\result={0:0}, __unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=6, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L798] EXPR 0 !x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff1) VAL [\result={0:0}, __unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=6, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L798] 0 x = !x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff1) [L799] EXPR 0 weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff0)) VAL [\result={0:0}, __unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=6, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L799] 0 x$w_buff0 = weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff0)) [L800] 0 x$w_buff1 = weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff1 : x$w_buff1)) [L801] EXPR 0 weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used)) VAL [\result={0:0}, __unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=6, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L801] 0 x$w_buff0_used = weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used)) [L802] EXPR 0 weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, __unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=6, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L802] 0 x$w_buff1_used = weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L804] EXPR 0 weak$$choice2 ? x$r_buff1_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff1_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, __unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=6, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] [L804] 0 x$r_buff1_thd0 = weak$$choice2 ? x$r_buff1_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff1_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L805] 0 main$tmp_guard1 = !(x == 2 && __unbuffered_p1_EAX == 0) VAL [\result={0:0}, __unbuffered_cnt=2, __unbuffered_p1_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=6, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 3 procedures, 140 locations, 2 error locations. Result: UNSAFE, OverallTime: 14.9s, OverallIterations: 17, TraceHistogramMax: 1, AutomataDifference: 5.3s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 1645 SDtfs, 1659 SDslu, 4474 SDs, 0 SdLazy, 3370 SolverSat, 173 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 3.2s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 204 GetRequests, 31 SyntacticMatches, 24 SemanticMatches, 149 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 400 ImplicationChecksByTransitivity, 2.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=8413occurred in iteration=0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.6s AutomataMinimizationTime, 16 MinimizatonAttempts, 1405 StatesRemovedByMinimization, 14 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.4s SatisfiabilityAnalysisTime, 2.3s InterpolantComputationTime, 737 NumberOfCodeBlocks, 737 NumberOfCodeBlocksAsserted, 17 NumberOfCheckSat, 667 ConstructedInterpolants, 0 QuantifiedInterpolants, 130230 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 16 InterpolantComputations, 16 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...