./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/pthread-wmm/mix056_power.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx12G -Xms1G -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/pthread-wmm/mix056_power.opt.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 61139f82df0df72db7fcd3fd3dc1d76e3572b602 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-11-28 18:19:56,682 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-28 18:19:56,685 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-28 18:19:56,703 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-28 18:19:56,704 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-28 18:19:56,706 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-28 18:19:56,708 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-28 18:19:56,721 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-28 18:19:56,723 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-28 18:19:56,727 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-28 18:19:56,729 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-28 18:19:56,730 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-28 18:19:56,731 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-28 18:19:56,733 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-28 18:19:56,734 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-28 18:19:56,735 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-28 18:19:56,737 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-28 18:19:56,738 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-28 18:19:56,739 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-28 18:19:56,741 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-28 18:19:56,743 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-28 18:19:56,744 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-28 18:19:56,745 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-28 18:19:56,746 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-28 18:19:56,748 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-28 18:19:56,748 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-28 18:19:56,749 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-28 18:19:56,750 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-28 18:19:56,750 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-28 18:19:56,751 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-28 18:19:56,751 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-28 18:19:56,752 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-28 18:19:56,753 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-28 18:19:56,754 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-28 18:19:56,755 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-28 18:19:56,755 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-28 18:19:56,756 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-28 18:19:56,756 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-28 18:19:56,756 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-28 18:19:56,757 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-28 18:19:56,758 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-28 18:19:56,759 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-28 18:19:56,773 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-28 18:19:56,774 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-28 18:19:56,775 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-28 18:19:56,775 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-28 18:19:56,776 INFO L138 SettingsManager]: * Use SBE=true [2019-11-28 18:19:56,776 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-28 18:19:56,776 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-28 18:19:56,776 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-28 18:19:56,777 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-28 18:19:56,777 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-28 18:19:56,777 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-28 18:19:56,777 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-28 18:19:56,777 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-28 18:19:56,778 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-28 18:19:56,778 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-28 18:19:56,778 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-28 18:19:56,778 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-28 18:19:56,779 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-28 18:19:56,779 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-28 18:19:56,779 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-28 18:19:56,779 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-28 18:19:56,779 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 18:19:56,780 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-28 18:19:56,780 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-28 18:19:56,780 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-28 18:19:56,780 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-28 18:19:56,781 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-28 18:19:56,781 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-28 18:19:56,781 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-11-28 18:19:56,781 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 61139f82df0df72db7fcd3fd3dc1d76e3572b602 [2019-11-28 18:19:57,073 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-28 18:19:57,086 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-28 18:19:57,090 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-28 18:19:57,091 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-28 18:19:57,092 INFO L275 PluginConnector]: CDTParser initialized [2019-11-28 18:19:57,093 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/pthread-wmm/mix056_power.opt.i [2019-11-28 18:19:57,170 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8680cf1c5/c1e0aa850fda4336ab48f3e4b18a473f/FLAGcd597e2bf [2019-11-28 18:19:57,808 INFO L306 CDTParser]: Found 1 translation units. [2019-11-28 18:19:57,808 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/pthread-wmm/mix056_power.opt.i [2019-11-28 18:19:57,823 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8680cf1c5/c1e0aa850fda4336ab48f3e4b18a473f/FLAGcd597e2bf [2019-11-28 18:19:58,090 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8680cf1c5/c1e0aa850fda4336ab48f3e4b18a473f [2019-11-28 18:19:58,093 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-28 18:19:58,094 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-28 18:19:58,096 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-28 18:19:58,096 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-28 18:19:58,100 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-28 18:19:58,101 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 06:19:58" (1/1) ... [2019-11-28 18:19:58,104 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1af9092c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:19:58, skipping insertion in model container [2019-11-28 18:19:58,104 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 06:19:58" (1/1) ... [2019-11-28 18:19:58,113 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-11-28 18:19:58,173 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-11-28 18:19:58,818 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 18:19:58,836 INFO L203 MainTranslator]: Completed pre-run [2019-11-28 18:19:58,954 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 18:19:59,048 INFO L208 MainTranslator]: Completed translation [2019-11-28 18:19:59,049 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:19:59 WrapperNode [2019-11-28 18:19:59,049 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-28 18:19:59,050 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-28 18:19:59,050 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-28 18:19:59,050 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-28 18:19:59,060 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:19:59" (1/1) ... [2019-11-28 18:19:59,080 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:19:59" (1/1) ... [2019-11-28 18:19:59,123 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-28 18:19:59,123 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-28 18:19:59,123 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-28 18:19:59,124 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-28 18:19:59,134 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:19:59" (1/1) ... [2019-11-28 18:19:59,134 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:19:59" (1/1) ... [2019-11-28 18:19:59,139 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:19:59" (1/1) ... [2019-11-28 18:19:59,140 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:19:59" (1/1) ... [2019-11-28 18:19:59,152 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:19:59" (1/1) ... [2019-11-28 18:19:59,161 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:19:59" (1/1) ... [2019-11-28 18:19:59,165 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:19:59" (1/1) ... [2019-11-28 18:19:59,170 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-28 18:19:59,171 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-28 18:19:59,171 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-28 18:19:59,171 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-28 18:19:59,173 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:19:59" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 18:19:59,246 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-11-28 18:19:59,246 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-11-28 18:19:59,246 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-11-28 18:19:59,247 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-11-28 18:19:59,247 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-11-28 18:19:59,247 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-11-28 18:19:59,247 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-11-28 18:19:59,247 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-11-28 18:19:59,247 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-11-28 18:19:59,248 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-11-28 18:19:59,248 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-11-28 18:19:59,248 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-28 18:19:59,248 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-28 18:19:59,250 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-11-28 18:20:00,058 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-28 18:20:00,058 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-11-28 18:20:00,060 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:20:00 BoogieIcfgContainer [2019-11-28 18:20:00,060 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-28 18:20:00,061 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-28 18:20:00,061 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-28 18:20:00,064 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-28 18:20:00,065 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 06:19:58" (1/3) ... [2019-11-28 18:20:00,066 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@224b7db3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 06:20:00, skipping insertion in model container [2019-11-28 18:20:00,066 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:19:59" (2/3) ... [2019-11-28 18:20:00,066 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@224b7db3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 06:20:00, skipping insertion in model container [2019-11-28 18:20:00,067 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:20:00" (3/3) ... [2019-11-28 18:20:00,069 INFO L109 eAbstractionObserver]: Analyzing ICFG mix056_power.opt.i [2019-11-28 18:20:00,079 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-11-28 18:20:00,079 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-28 18:20:00,087 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-11-28 18:20:00,088 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-11-28 18:20:00,123 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,123 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,123 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,123 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,124 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,124 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,124 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,124 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,125 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,125 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,125 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,125 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,126 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,126 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,126 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,126 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,127 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,127 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,127 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,127 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,128 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,128 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,128 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,128 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,129 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,129 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,129 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,129 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,130 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,130 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,130 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,130 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,131 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,131 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,131 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,131 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,132 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,133 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,133 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,133 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,133 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,133 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,134 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,134 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,134 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,135 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,135 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,135 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,135 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,135 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,136 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,136 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,136 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,136 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,137 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,137 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,137 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,138 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,138 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,138 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,138 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,139 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,139 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,139 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,139 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,139 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,140 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,140 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,140 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,140 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:00,166 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-11-28 18:20:00,182 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-28 18:20:00,182 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-28 18:20:00,183 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-28 18:20:00,183 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-28 18:20:00,183 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-28 18:20:00,183 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-28 18:20:00,183 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-28 18:20:00,183 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-28 18:20:00,202 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 162 places, 193 transitions [2019-11-28 18:20:00,205 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 162 places, 193 transitions [2019-11-28 18:20:00,294 INFO L134 PetriNetUnfolder]: 41/190 cut-off events. [2019-11-28 18:20:00,294 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-11-28 18:20:00,311 INFO L76 FinitePrefix]: Finished finitePrefix Result has 200 conditions, 190 events. 41/190 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 465 event pairs. 9/156 useless extension candidates. Maximal degree in co-relation 161. Up to 2 conditions per place. [2019-11-28 18:20:00,333 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 162 places, 193 transitions [2019-11-28 18:20:00,412 INFO L134 PetriNetUnfolder]: 41/190 cut-off events. [2019-11-28 18:20:00,412 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-11-28 18:20:00,422 INFO L76 FinitePrefix]: Finished finitePrefix Result has 200 conditions, 190 events. 41/190 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 465 event pairs. 9/156 useless extension candidates. Maximal degree in co-relation 161. Up to 2 conditions per place. [2019-11-28 18:20:00,446 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 11490 [2019-11-28 18:20:00,448 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-11-28 18:20:05,206 WARN L192 SmtUtils]: Spent 327.00 ms on a formula simplification. DAG size of input: 87 DAG size of output: 85 [2019-11-28 18:20:05,370 WARN L192 SmtUtils]: Spent 161.00 ms on a formula simplification that was a NOOP. DAG size: 83 [2019-11-28 18:20:05,393 INFO L206 etLargeBlockEncoding]: Checked pairs total: 48383 [2019-11-28 18:20:05,394 INFO L214 etLargeBlockEncoding]: Total number of compositions: 109 [2019-11-28 18:20:05,401 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 83 places, 92 transitions [2019-11-28 18:20:06,744 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 16526 states. [2019-11-28 18:20:06,747 INFO L276 IsEmpty]: Start isEmpty. Operand 16526 states. [2019-11-28 18:20:06,754 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2019-11-28 18:20:06,755 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:06,756 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:06,756 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:06,762 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:06,763 INFO L82 PathProgramCache]: Analyzing trace with hash 2128093424, now seen corresponding path program 1 times [2019-11-28 18:20:06,773 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:06,773 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1436960463] [2019-11-28 18:20:06,774 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:06,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:07,054 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:07,055 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1436960463] [2019-11-28 18:20:07,055 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:07,056 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-11-28 18:20:07,056 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [696042794] [2019-11-28 18:20:07,060 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:20:07,061 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:07,073 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:20:07,074 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:07,075 INFO L87 Difference]: Start difference. First operand 16526 states. Second operand 3 states. [2019-11-28 18:20:07,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:07,528 INFO L93 Difference]: Finished difference Result 16398 states and 61580 transitions. [2019-11-28 18:20:07,529 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:20:07,530 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2019-11-28 18:20:07,531 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:07,751 INFO L225 Difference]: With dead ends: 16398 [2019-11-28 18:20:07,751 INFO L226 Difference]: Without dead ends: 16062 [2019-11-28 18:20:07,753 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:07,962 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16062 states. [2019-11-28 18:20:08,617 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16062 to 16062. [2019-11-28 18:20:08,618 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16062 states. [2019-11-28 18:20:08,729 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16062 states to 16062 states and 60376 transitions. [2019-11-28 18:20:08,730 INFO L78 Accepts]: Start accepts. Automaton has 16062 states and 60376 transitions. Word has length 7 [2019-11-28 18:20:08,732 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:08,733 INFO L462 AbstractCegarLoop]: Abstraction has 16062 states and 60376 transitions. [2019-11-28 18:20:08,733 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:20:08,733 INFO L276 IsEmpty]: Start isEmpty. Operand 16062 states and 60376 transitions. [2019-11-28 18:20:08,746 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-11-28 18:20:08,746 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:08,747 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:08,747 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:08,747 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:08,748 INFO L82 PathProgramCache]: Analyzing trace with hash -1390331573, now seen corresponding path program 1 times [2019-11-28 18:20:08,748 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:08,748 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [507407673] [2019-11-28 18:20:08,748 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:08,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:08,875 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:08,876 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [507407673] [2019-11-28 18:20:08,876 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:08,876 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:20:08,877 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [56997469] [2019-11-28 18:20:08,878 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:20:08,879 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:08,879 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:20:08,879 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:20:08,879 INFO L87 Difference]: Start difference. First operand 16062 states and 60376 transitions. Second operand 4 states. [2019-11-28 18:20:09,474 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:09,475 INFO L93 Difference]: Finished difference Result 24942 states and 90524 transitions. [2019-11-28 18:20:09,475 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:20:09,475 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-11-28 18:20:09,476 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:09,586 INFO L225 Difference]: With dead ends: 24942 [2019-11-28 18:20:09,587 INFO L226 Difference]: Without dead ends: 24928 [2019-11-28 18:20:09,588 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:20:09,766 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24928 states. [2019-11-28 18:20:10,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24928 to 22166. [2019-11-28 18:20:10,580 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22166 states. [2019-11-28 18:20:10,648 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22166 states to 22166 states and 81470 transitions. [2019-11-28 18:20:10,648 INFO L78 Accepts]: Start accepts. Automaton has 22166 states and 81470 transitions. Word has length 13 [2019-11-28 18:20:10,649 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:10,649 INFO L462 AbstractCegarLoop]: Abstraction has 22166 states and 81470 transitions. [2019-11-28 18:20:10,649 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:20:10,649 INFO L276 IsEmpty]: Start isEmpty. Operand 22166 states and 81470 transitions. [2019-11-28 18:20:10,650 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-11-28 18:20:10,650 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:10,651 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:10,651 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:10,651 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:10,651 INFO L82 PathProgramCache]: Analyzing trace with hash -1371832765, now seen corresponding path program 1 times [2019-11-28 18:20:10,652 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:10,652 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [285696690] [2019-11-28 18:20:10,652 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:10,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:10,779 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:10,781 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [285696690] [2019-11-28 18:20:10,781 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:10,781 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:20:10,782 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1993860369] [2019-11-28 18:20:10,782 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:20:10,783 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:10,783 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:20:10,783 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:20:10,783 INFO L87 Difference]: Start difference. First operand 22166 states and 81470 transitions. Second operand 4 states. [2019-11-28 18:20:11,094 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:11,094 INFO L93 Difference]: Finished difference Result 27782 states and 100994 transitions. [2019-11-28 18:20:11,095 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:20:11,095 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-11-28 18:20:11,095 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:11,219 INFO L225 Difference]: With dead ends: 27782 [2019-11-28 18:20:11,220 INFO L226 Difference]: Without dead ends: 27782 [2019-11-28 18:20:11,220 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:20:11,395 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27782 states. [2019-11-28 18:20:12,010 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27782 to 24630. [2019-11-28 18:20:12,010 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24630 states. [2019-11-28 18:20:12,128 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24630 states to 24630 states and 90262 transitions. [2019-11-28 18:20:12,128 INFO L78 Accepts]: Start accepts. Automaton has 24630 states and 90262 transitions. Word has length 13 [2019-11-28 18:20:12,129 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:12,129 INFO L462 AbstractCegarLoop]: Abstraction has 24630 states and 90262 transitions. [2019-11-28 18:20:12,129 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:20:12,129 INFO L276 IsEmpty]: Start isEmpty. Operand 24630 states and 90262 transitions. [2019-11-28 18:20:12,139 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-11-28 18:20:12,139 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:12,139 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:12,139 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:12,140 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:12,140 INFO L82 PathProgramCache]: Analyzing trace with hash -1003212910, now seen corresponding path program 1 times [2019-11-28 18:20:12,140 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:12,140 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1185606143] [2019-11-28 18:20:12,141 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:12,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:12,262 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:12,263 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1185606143] [2019-11-28 18:20:12,264 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:12,264 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:20:12,264 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1188998506] [2019-11-28 18:20:12,265 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:20:12,265 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:12,266 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:20:12,266 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:20:12,266 INFO L87 Difference]: Start difference. First operand 24630 states and 90262 transitions. Second operand 5 states. [2019-11-28 18:20:13,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:13,279 INFO L93 Difference]: Finished difference Result 33042 states and 118962 transitions. [2019-11-28 18:20:13,280 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-11-28 18:20:13,280 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-11-28 18:20:13,280 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:13,388 INFO L225 Difference]: With dead ends: 33042 [2019-11-28 18:20:13,397 INFO L226 Difference]: Without dead ends: 33028 [2019-11-28 18:20:13,398 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-11-28 18:20:13,579 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33028 states. [2019-11-28 18:20:14,075 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33028 to 24716. [2019-11-28 18:20:14,076 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24716 states. [2019-11-28 18:20:14,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24716 states to 24716 states and 90325 transitions. [2019-11-28 18:20:14,143 INFO L78 Accepts]: Start accepts. Automaton has 24716 states and 90325 transitions. Word has length 19 [2019-11-28 18:20:14,143 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:14,144 INFO L462 AbstractCegarLoop]: Abstraction has 24716 states and 90325 transitions. [2019-11-28 18:20:14,144 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:20:14,144 INFO L276 IsEmpty]: Start isEmpty. Operand 24716 states and 90325 transitions. [2019-11-28 18:20:14,174 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-11-28 18:20:14,174 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:14,174 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:14,175 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:14,175 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:14,175 INFO L82 PathProgramCache]: Analyzing trace with hash -1251036613, now seen corresponding path program 1 times [2019-11-28 18:20:14,175 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:14,176 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [779423472] [2019-11-28 18:20:14,176 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:14,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:14,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:14,261 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [779423472] [2019-11-28 18:20:14,261 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:14,261 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:20:14,262 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [610664721] [2019-11-28 18:20:14,262 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:20:14,262 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:14,262 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:20:14,264 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:14,264 INFO L87 Difference]: Start difference. First operand 24716 states and 90325 transitions. Second operand 3 states. [2019-11-28 18:20:14,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:14,482 INFO L93 Difference]: Finished difference Result 30008 states and 109703 transitions. [2019-11-28 18:20:14,483 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:20:14,483 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-11-28 18:20:14,483 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:15,281 INFO L225 Difference]: With dead ends: 30008 [2019-11-28 18:20:15,282 INFO L226 Difference]: Without dead ends: 30008 [2019-11-28 18:20:15,282 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:15,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30008 states. [2019-11-28 18:20:15,871 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30008 to 28190. [2019-11-28 18:20:15,871 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28190 states. [2019-11-28 18:20:15,948 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28190 states to 28190 states and 103378 transitions. [2019-11-28 18:20:15,948 INFO L78 Accepts]: Start accepts. Automaton has 28190 states and 103378 transitions. Word has length 27 [2019-11-28 18:20:15,948 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:15,949 INFO L462 AbstractCegarLoop]: Abstraction has 28190 states and 103378 transitions. [2019-11-28 18:20:15,949 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:20:15,949 INFO L276 IsEmpty]: Start isEmpty. Operand 28190 states and 103378 transitions. [2019-11-28 18:20:15,973 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-11-28 18:20:15,974 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:15,974 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:15,974 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:15,974 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:15,974 INFO L82 PathProgramCache]: Analyzing trace with hash -1250824263, now seen corresponding path program 1 times [2019-11-28 18:20:15,975 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:15,975 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1840023721] [2019-11-28 18:20:15,975 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:16,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:16,035 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:16,035 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1840023721] [2019-11-28 18:20:16,035 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:16,035 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:20:16,035 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2082179907] [2019-11-28 18:20:16,036 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:20:16,036 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:16,036 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:20:16,036 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:16,036 INFO L87 Difference]: Start difference. First operand 28190 states and 103378 transitions. Second operand 3 states. [2019-11-28 18:20:16,097 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:16,097 INFO L93 Difference]: Finished difference Result 16100 states and 51114 transitions. [2019-11-28 18:20:16,097 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:20:16,097 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-11-28 18:20:16,098 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:16,124 INFO L225 Difference]: With dead ends: 16100 [2019-11-28 18:20:16,124 INFO L226 Difference]: Without dead ends: 16100 [2019-11-28 18:20:16,125 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:16,187 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16100 states. [2019-11-28 18:20:16,369 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16100 to 16100. [2019-11-28 18:20:16,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16100 states. [2019-11-28 18:20:16,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16100 states to 16100 states and 51114 transitions. [2019-11-28 18:20:16,405 INFO L78 Accepts]: Start accepts. Automaton has 16100 states and 51114 transitions. Word has length 27 [2019-11-28 18:20:16,405 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:16,405 INFO L462 AbstractCegarLoop]: Abstraction has 16100 states and 51114 transitions. [2019-11-28 18:20:16,406 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:20:16,406 INFO L276 IsEmpty]: Start isEmpty. Operand 16100 states and 51114 transitions. [2019-11-28 18:20:16,414 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-11-28 18:20:16,415 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:16,415 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:16,415 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:16,415 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:16,415 INFO L82 PathProgramCache]: Analyzing trace with hash 411430761, now seen corresponding path program 1 times [2019-11-28 18:20:16,416 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:16,416 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [457367855] [2019-11-28 18:20:16,416 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:16,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:16,468 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:16,469 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [457367855] [2019-11-28 18:20:16,470 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:16,470 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:20:16,470 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1309143190] [2019-11-28 18:20:16,470 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:20:16,471 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:16,471 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:20:16,471 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:20:16,471 INFO L87 Difference]: Start difference. First operand 16100 states and 51114 transitions. Second operand 4 states. [2019-11-28 18:20:16,494 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:16,494 INFO L93 Difference]: Finished difference Result 2377 states and 5510 transitions. [2019-11-28 18:20:16,494 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-28 18:20:16,495 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 28 [2019-11-28 18:20:16,495 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:16,498 INFO L225 Difference]: With dead ends: 2377 [2019-11-28 18:20:16,498 INFO L226 Difference]: Without dead ends: 2377 [2019-11-28 18:20:16,499 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:20:16,504 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2377 states. [2019-11-28 18:20:16,524 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2377 to 2377. [2019-11-28 18:20:16,524 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2377 states. [2019-11-28 18:20:16,529 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2377 states to 2377 states and 5510 transitions. [2019-11-28 18:20:16,529 INFO L78 Accepts]: Start accepts. Automaton has 2377 states and 5510 transitions. Word has length 28 [2019-11-28 18:20:16,529 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:16,529 INFO L462 AbstractCegarLoop]: Abstraction has 2377 states and 5510 transitions. [2019-11-28 18:20:16,529 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:20:16,530 INFO L276 IsEmpty]: Start isEmpty. Operand 2377 states and 5510 transitions. [2019-11-28 18:20:16,532 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2019-11-28 18:20:16,532 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:16,533 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:16,533 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:16,533 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:16,533 INFO L82 PathProgramCache]: Analyzing trace with hash -1388136454, now seen corresponding path program 1 times [2019-11-28 18:20:16,534 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:16,534 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2047706242] [2019-11-28 18:20:16,534 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:16,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:16,599 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:16,600 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2047706242] [2019-11-28 18:20:16,600 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:16,600 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 18:20:16,600 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1239956475] [2019-11-28 18:20:16,601 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:20:16,601 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:16,602 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:20:16,602 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:20:16,602 INFO L87 Difference]: Start difference. First operand 2377 states and 5510 transitions. Second operand 5 states. [2019-11-28 18:20:16,625 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:16,625 INFO L93 Difference]: Finished difference Result 678 states and 1563 transitions. [2019-11-28 18:20:16,626 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:20:16,626 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 40 [2019-11-28 18:20:16,626 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:16,627 INFO L225 Difference]: With dead ends: 678 [2019-11-28 18:20:16,628 INFO L226 Difference]: Without dead ends: 678 [2019-11-28 18:20:16,628 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:20:16,631 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 678 states. [2019-11-28 18:20:16,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 678 to 622. [2019-11-28 18:20:16,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 622 states. [2019-11-28 18:20:16,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 622 states to 622 states and 1431 transitions. [2019-11-28 18:20:16,639 INFO L78 Accepts]: Start accepts. Automaton has 622 states and 1431 transitions. Word has length 40 [2019-11-28 18:20:16,641 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:16,642 INFO L462 AbstractCegarLoop]: Abstraction has 622 states and 1431 transitions. [2019-11-28 18:20:16,642 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:20:16,642 INFO L276 IsEmpty]: Start isEmpty. Operand 622 states and 1431 transitions. [2019-11-28 18:20:16,644 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-11-28 18:20:16,644 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:16,644 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:16,644 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:16,645 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:16,645 INFO L82 PathProgramCache]: Analyzing trace with hash -826083081, now seen corresponding path program 1 times [2019-11-28 18:20:16,645 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:16,646 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [855362572] [2019-11-28 18:20:16,646 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:16,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:16,797 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:16,798 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [855362572] [2019-11-28 18:20:16,798 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:16,798 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 18:20:16,799 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [721065989] [2019-11-28 18:20:16,799 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:20:16,799 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:16,800 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:20:16,800 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:20:16,800 INFO L87 Difference]: Start difference. First operand 622 states and 1431 transitions. Second operand 5 states. [2019-11-28 18:20:16,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:16,988 INFO L93 Difference]: Finished difference Result 911 states and 2103 transitions. [2019-11-28 18:20:16,989 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 18:20:16,989 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 55 [2019-11-28 18:20:16,989 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:16,991 INFO L225 Difference]: With dead ends: 911 [2019-11-28 18:20:16,991 INFO L226 Difference]: Without dead ends: 911 [2019-11-28 18:20:16,991 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-11-28 18:20:16,993 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 911 states. [2019-11-28 18:20:16,998 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 911 to 821. [2019-11-28 18:20:16,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 821 states. [2019-11-28 18:20:17,000 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 821 states to 821 states and 1898 transitions. [2019-11-28 18:20:17,000 INFO L78 Accepts]: Start accepts. Automaton has 821 states and 1898 transitions. Word has length 55 [2019-11-28 18:20:17,000 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:17,000 INFO L462 AbstractCegarLoop]: Abstraction has 821 states and 1898 transitions. [2019-11-28 18:20:17,000 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:20:17,000 INFO L276 IsEmpty]: Start isEmpty. Operand 821 states and 1898 transitions. [2019-11-28 18:20:17,002 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-11-28 18:20:17,002 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:17,002 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:17,002 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:17,003 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:17,003 INFO L82 PathProgramCache]: Analyzing trace with hash 297273929, now seen corresponding path program 2 times [2019-11-28 18:20:17,003 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:17,003 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1137094392] [2019-11-28 18:20:17,003 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:17,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:17,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:17,110 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1137094392] [2019-11-28 18:20:17,110 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:17,110 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-28 18:20:17,110 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1165877530] [2019-11-28 18:20:17,111 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-28 18:20:17,111 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:17,111 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-28 18:20:17,111 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-11-28 18:20:17,111 INFO L87 Difference]: Start difference. First operand 821 states and 1898 transitions. Second operand 6 states. [2019-11-28 18:20:17,430 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:17,430 INFO L93 Difference]: Finished difference Result 1208 states and 2794 transitions. [2019-11-28 18:20:17,431 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-11-28 18:20:17,431 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 55 [2019-11-28 18:20:17,431 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:17,433 INFO L225 Difference]: With dead ends: 1208 [2019-11-28 18:20:17,433 INFO L226 Difference]: Without dead ends: 1208 [2019-11-28 18:20:17,433 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2019-11-28 18:20:17,436 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1208 states. [2019-11-28 18:20:17,445 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1208 to 893. [2019-11-28 18:20:17,446 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 893 states. [2019-11-28 18:20:17,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 893 states to 893 states and 2076 transitions. [2019-11-28 18:20:17,448 INFO L78 Accepts]: Start accepts. Automaton has 893 states and 2076 transitions. Word has length 55 [2019-11-28 18:20:17,448 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:17,448 INFO L462 AbstractCegarLoop]: Abstraction has 893 states and 2076 transitions. [2019-11-28 18:20:17,448 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-28 18:20:17,448 INFO L276 IsEmpty]: Start isEmpty. Operand 893 states and 2076 transitions. [2019-11-28 18:20:17,450 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-11-28 18:20:17,450 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:17,451 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:17,451 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:17,451 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:17,451 INFO L82 PathProgramCache]: Analyzing trace with hash 1649215159, now seen corresponding path program 3 times [2019-11-28 18:20:17,451 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:17,452 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1533567115] [2019-11-28 18:20:17,452 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:17,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:17,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:17,604 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1533567115] [2019-11-28 18:20:17,605 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:17,605 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-28 18:20:17,605 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [259307894] [2019-11-28 18:20:17,606 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-28 18:20:17,606 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:17,607 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-28 18:20:17,607 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-28 18:20:17,607 INFO L87 Difference]: Start difference. First operand 893 states and 2076 transitions. Second operand 6 states. [2019-11-28 18:20:17,959 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:17,959 INFO L93 Difference]: Finished difference Result 1289 states and 2973 transitions. [2019-11-28 18:20:17,960 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-28 18:20:17,960 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 55 [2019-11-28 18:20:17,960 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:17,963 INFO L225 Difference]: With dead ends: 1289 [2019-11-28 18:20:17,963 INFO L226 Difference]: Without dead ends: 1289 [2019-11-28 18:20:17,964 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 7 SyntacticMatches, 3 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=32, Invalid=78, Unknown=0, NotChecked=0, Total=110 [2019-11-28 18:20:17,966 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1289 states. [2019-11-28 18:20:17,976 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1289 to 959. [2019-11-28 18:20:17,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 959 states. [2019-11-28 18:20:17,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 959 states to 959 states and 2231 transitions. [2019-11-28 18:20:17,978 INFO L78 Accepts]: Start accepts. Automaton has 959 states and 2231 transitions. Word has length 55 [2019-11-28 18:20:17,978 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:17,979 INFO L462 AbstractCegarLoop]: Abstraction has 959 states and 2231 transitions. [2019-11-28 18:20:17,979 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-28 18:20:17,979 INFO L276 IsEmpty]: Start isEmpty. Operand 959 states and 2231 transitions. [2019-11-28 18:20:17,980 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-11-28 18:20:17,980 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:17,981 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:17,981 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:17,981 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:17,981 INFO L82 PathProgramCache]: Analyzing trace with hash 817618467, now seen corresponding path program 4 times [2019-11-28 18:20:17,981 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:17,982 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1053016297] [2019-11-28 18:20:17,982 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:18,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:18,072 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:18,073 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1053016297] [2019-11-28 18:20:18,073 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:18,074 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:20:18,074 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [357865363] [2019-11-28 18:20:18,074 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:20:18,075 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:18,075 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:20:18,075 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:18,076 INFO L87 Difference]: Start difference. First operand 959 states and 2231 transitions. Second operand 3 states. [2019-11-28 18:20:18,133 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:18,133 INFO L93 Difference]: Finished difference Result 958 states and 2229 transitions. [2019-11-28 18:20:18,134 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:20:18,134 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 55 [2019-11-28 18:20:18,135 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:18,137 INFO L225 Difference]: With dead ends: 958 [2019-11-28 18:20:18,137 INFO L226 Difference]: Without dead ends: 958 [2019-11-28 18:20:18,137 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:18,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 958 states. [2019-11-28 18:20:18,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 958 to 665. [2019-11-28 18:20:18,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 665 states. [2019-11-28 18:20:18,156 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 665 states to 665 states and 1545 transitions. [2019-11-28 18:20:18,156 INFO L78 Accepts]: Start accepts. Automaton has 665 states and 1545 transitions. Word has length 55 [2019-11-28 18:20:18,157 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:18,157 INFO L462 AbstractCegarLoop]: Abstraction has 665 states and 1545 transitions. [2019-11-28 18:20:18,157 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:20:18,157 INFO L276 IsEmpty]: Start isEmpty. Operand 665 states and 1545 transitions. [2019-11-28 18:20:18,159 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-11-28 18:20:18,159 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:18,160 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:18,160 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:18,160 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:18,160 INFO L82 PathProgramCache]: Analyzing trace with hash 1696047106, now seen corresponding path program 1 times [2019-11-28 18:20:18,161 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:18,161 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1587058078] [2019-11-28 18:20:18,161 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:18,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:18,341 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:18,343 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1587058078] [2019-11-28 18:20:18,343 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:18,344 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 18:20:18,344 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [35844937] [2019-11-28 18:20:18,345 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-28 18:20:18,345 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:18,346 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-28 18:20:18,346 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-28 18:20:18,347 INFO L87 Difference]: Start difference. First operand 665 states and 1545 transitions. Second operand 6 states. [2019-11-28 18:20:18,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:18,423 INFO L93 Difference]: Finished difference Result 963 states and 2083 transitions. [2019-11-28 18:20:18,424 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 18:20:18,425 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 56 [2019-11-28 18:20:18,425 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:18,427 INFO L225 Difference]: With dead ends: 963 [2019-11-28 18:20:18,430 INFO L226 Difference]: Without dead ends: 600 [2019-11-28 18:20:18,430 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-11-28 18:20:18,436 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 600 states. [2019-11-28 18:20:18,449 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 600 to 600. [2019-11-28 18:20:18,450 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 600 states. [2019-11-28 18:20:18,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 600 states to 600 states and 1356 transitions. [2019-11-28 18:20:18,453 INFO L78 Accepts]: Start accepts. Automaton has 600 states and 1356 transitions. Word has length 56 [2019-11-28 18:20:18,453 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:18,453 INFO L462 AbstractCegarLoop]: Abstraction has 600 states and 1356 transitions. [2019-11-28 18:20:18,454 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-28 18:20:18,454 INFO L276 IsEmpty]: Start isEmpty. Operand 600 states and 1356 transitions. [2019-11-28 18:20:18,456 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-11-28 18:20:18,457 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:18,457 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:18,458 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:18,458 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:18,458 INFO L82 PathProgramCache]: Analyzing trace with hash -1631888206, now seen corresponding path program 2 times [2019-11-28 18:20:18,459 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:18,459 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [688720545] [2019-11-28 18:20:18,460 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:18,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:18,662 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:18,662 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [688720545] [2019-11-28 18:20:18,663 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:18,663 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 18:20:18,663 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1557255114] [2019-11-28 18:20:18,664 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-28 18:20:18,664 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:18,665 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-28 18:20:18,665 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-11-28 18:20:18,665 INFO L87 Difference]: Start difference. First operand 600 states and 1356 transitions. Second operand 6 states. [2019-11-28 18:20:18,757 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:18,758 INFO L93 Difference]: Finished difference Result 898 states and 1996 transitions. [2019-11-28 18:20:18,758 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 18:20:18,758 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 56 [2019-11-28 18:20:18,759 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:18,759 INFO L225 Difference]: With dead ends: 898 [2019-11-28 18:20:18,759 INFO L226 Difference]: Without dead ends: 294 [2019-11-28 18:20:18,760 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-11-28 18:20:18,762 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 294 states. [2019-11-28 18:20:18,765 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 294 to 254. [2019-11-28 18:20:18,766 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 254 states. [2019-11-28 18:20:18,766 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 254 states to 254 states and 470 transitions. [2019-11-28 18:20:18,767 INFO L78 Accepts]: Start accepts. Automaton has 254 states and 470 transitions. Word has length 56 [2019-11-28 18:20:18,767 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:18,767 INFO L462 AbstractCegarLoop]: Abstraction has 254 states and 470 transitions. [2019-11-28 18:20:18,767 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-28 18:20:18,767 INFO L276 IsEmpty]: Start isEmpty. Operand 254 states and 470 transitions. [2019-11-28 18:20:18,768 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-11-28 18:20:18,768 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:18,769 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:18,769 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:18,769 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:18,770 INFO L82 PathProgramCache]: Analyzing trace with hash -318870370, now seen corresponding path program 3 times [2019-11-28 18:20:18,770 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:18,770 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [141282282] [2019-11-28 18:20:18,770 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:19,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:19,332 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:19,332 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [141282282] [2019-11-28 18:20:19,332 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:19,332 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:20:19,332 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [3456635] [2019-11-28 18:20:19,333 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:20:19,333 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:19,333 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:20:19,333 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:19,333 INFO L87 Difference]: Start difference. First operand 254 states and 470 transitions. Second operand 3 states. [2019-11-28 18:20:19,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:19,344 INFO L93 Difference]: Finished difference Result 234 states and 415 transitions. [2019-11-28 18:20:19,345 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:20:19,345 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 56 [2019-11-28 18:20:19,345 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:19,345 INFO L225 Difference]: With dead ends: 234 [2019-11-28 18:20:19,346 INFO L226 Difference]: Without dead ends: 234 [2019-11-28 18:20:19,346 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:19,347 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 234 states. [2019-11-28 18:20:19,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 234 to 207. [2019-11-28 18:20:19,349 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 207 states. [2019-11-28 18:20:19,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 364 transitions. [2019-11-28 18:20:19,350 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 364 transitions. Word has length 56 [2019-11-28 18:20:19,350 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:19,350 INFO L462 AbstractCegarLoop]: Abstraction has 207 states and 364 transitions. [2019-11-28 18:20:19,350 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:20:19,351 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 364 transitions. [2019-11-28 18:20:19,351 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:20:19,351 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:19,352 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:19,352 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:19,352 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:19,352 INFO L82 PathProgramCache]: Analyzing trace with hash -1516556909, now seen corresponding path program 1 times [2019-11-28 18:20:19,353 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:19,353 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [991370832] [2019-11-28 18:20:19,353 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:19,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:19,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:19,659 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [991370832] [2019-11-28 18:20:19,663 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:19,663 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-11-28 18:20:19,663 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [435740901] [2019-11-28 18:20:19,664 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-11-28 18:20:19,664 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:19,664 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-11-28 18:20:19,664 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=106, Unknown=0, NotChecked=0, Total=132 [2019-11-28 18:20:19,665 INFO L87 Difference]: Start difference. First operand 207 states and 364 transitions. Second operand 12 states. [2019-11-28 18:20:20,084 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:20,085 INFO L93 Difference]: Finished difference Result 363 states and 623 transitions. [2019-11-28 18:20:20,085 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-11-28 18:20:20,085 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 57 [2019-11-28 18:20:20,085 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:20,086 INFO L225 Difference]: With dead ends: 363 [2019-11-28 18:20:20,086 INFO L226 Difference]: Without dead ends: 333 [2019-11-28 18:20:20,086 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 47 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=62, Invalid=280, Unknown=0, NotChecked=0, Total=342 [2019-11-28 18:20:20,087 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 333 states. [2019-11-28 18:20:20,089 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 333 to 303. [2019-11-28 18:20:20,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 303 states. [2019-11-28 18:20:20,090 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 303 states to 303 states and 528 transitions. [2019-11-28 18:20:20,090 INFO L78 Accepts]: Start accepts. Automaton has 303 states and 528 transitions. Word has length 57 [2019-11-28 18:20:20,091 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:20,091 INFO L462 AbstractCegarLoop]: Abstraction has 303 states and 528 transitions. [2019-11-28 18:20:20,091 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-11-28 18:20:20,091 INFO L276 IsEmpty]: Start isEmpty. Operand 303 states and 528 transitions. [2019-11-28 18:20:20,092 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:20:20,092 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:20,092 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:20,092 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:20,092 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:20,093 INFO L82 PathProgramCache]: Analyzing trace with hash 1886575453, now seen corresponding path program 2 times [2019-11-28 18:20:20,093 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:20,093 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1701043047] [2019-11-28 18:20:20,093 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:20,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:20,373 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:20,373 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1701043047] [2019-11-28 18:20:20,374 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:20,374 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-11-28 18:20:20,374 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [108864055] [2019-11-28 18:20:20,375 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-11-28 18:20:20,375 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:20,375 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-11-28 18:20:20,376 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=149, Unknown=0, NotChecked=0, Total=182 [2019-11-28 18:20:20,376 INFO L87 Difference]: Start difference. First operand 303 states and 528 transitions. Second operand 14 states. [2019-11-28 18:20:20,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:20,833 INFO L93 Difference]: Finished difference Result 411 states and 696 transitions. [2019-11-28 18:20:20,834 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-11-28 18:20:20,834 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 57 [2019-11-28 18:20:20,834 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:20,835 INFO L225 Difference]: With dead ends: 411 [2019-11-28 18:20:20,835 INFO L226 Difference]: Without dead ends: 381 [2019-11-28 18:20:20,835 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 83 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=112, Invalid=488, Unknown=0, NotChecked=0, Total=600 [2019-11-28 18:20:20,836 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 381 states. [2019-11-28 18:20:20,840 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 381 to 315. [2019-11-28 18:20:20,840 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 315 states. [2019-11-28 18:20:20,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 315 states to 315 states and 549 transitions. [2019-11-28 18:20:20,841 INFO L78 Accepts]: Start accepts. Automaton has 315 states and 549 transitions. Word has length 57 [2019-11-28 18:20:20,841 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:20,841 INFO L462 AbstractCegarLoop]: Abstraction has 315 states and 549 transitions. [2019-11-28 18:20:20,841 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-11-28 18:20:20,841 INFO L276 IsEmpty]: Start isEmpty. Operand 315 states and 549 transitions. [2019-11-28 18:20:20,842 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:20:20,842 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:20,843 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:20,843 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:20,843 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:20,843 INFO L82 PathProgramCache]: Analyzing trace with hash 731376245, now seen corresponding path program 3 times [2019-11-28 18:20:20,843 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:20,844 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [112342769] [2019-11-28 18:20:20,844 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:20,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 18:20:20,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 18:20:20,973 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-28 18:20:20,974 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-28 18:20:20,978 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [740] [740] ULTIMATE.startENTRY-->L800: Formula: (let ((.cse0 (store |v_#valid_62| 0 0))) (and (= 0 v_~y$read_delayed_var~0.base_6) (= 0 v_~weak$$choice0~0_25) (= 0 v_~y$r_buff0_thd3~0_151) (= |v_#length_23| (store |v_#length_24| |v_ULTIMATE.start_main_~#t1492~0.base_26| 4)) (= v_~y$w_buff1~0_200 0) (= v_~y$w_buff0_used~0_650 0) (= v_~__unbuffered_cnt~0_109 0) (< 0 |v_#StackHeapBarrier_16|) (< |v_#StackHeapBarrier_16| |v_ULTIMATE.start_main_~#t1492~0.base_26|) (= 0 v_~y$w_buff0~0_308) (= 0 v_~y$r_buff1_thd3~0_122) (= v_~y$read_delayed~0_6 0) (= 0 v_~y$r_buff1_thd1~0_76) (= 0 |v_ULTIMATE.start_main_~#t1492~0.offset_19|) (= v_~z~0_51 0) (= v_~y$r_buff0_thd1~0_29 0) (= v_~main$tmp_guard1~0_28 0) (= v_~y$r_buff0_thd0~0_312 0) (= 0 v_~__unbuffered_p2_EAX~0_90) (= 0 v_~y$flush_delayed~0_45) (= v_~y$w_buff1_used~0_407 0) (= v_~y$r_buff0_thd2~0_88 0) (= |v_#NULL.offset_5| 0) (= (store |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1492~0.base_26| (store (select |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1492~0.base_26|) |v_ULTIMATE.start_main_~#t1492~0.offset_19| 0)) |v_#memory_int_23|) (= 0 v_~y$r_buff1_thd2~0_131) (= (store .cse0 |v_ULTIMATE.start_main_~#t1492~0.base_26| 1) |v_#valid_60|) (= v_~y$mem_tmp~0_31 0) (= 0 v_~y$read_delayed_var~0.offset_6) (= v_~y~0_150 0) (= v_~weak$$choice2~0_131 0) (= v_~y$r_buff1_thd0~0_254 0) (= v_~main$tmp_guard0~0_24 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t1492~0.base_26|)) (= 0 |v_#NULL.base_5|) (= v_~x~0_80 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_16|, #valid=|v_#valid_62|, #memory_int=|v_#memory_int_24|, #length=|v_#length_24|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_28|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_26|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_104|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_52|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_26|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_38|, ULTIMATE.start_main_~#t1493~0.offset=|v_ULTIMATE.start_main_~#t1493~0.offset_19|, ~y$read_delayed~0=v_~y$read_delayed~0_6, ~y$mem_tmp~0=v_~y$mem_tmp~0_31, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_122, ULTIMATE.start_main_~#t1494~0.base=|v_ULTIMATE.start_main_~#t1494~0.base_21|, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_29, ~y$flush_delayed~0=v_~y$flush_delayed~0_45, #length=|v_#length_23|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_90, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_34|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_142|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_44|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_31|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_98|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_27|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_26|, ULTIMATE.start_main_~#t1494~0.offset=|v_ULTIMATE.start_main_~#t1494~0.offset_14|, ~weak$$choice0~0=v_~weak$$choice0~0_25, #StackHeapBarrier=|v_#StackHeapBarrier_16|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_28|, ~y$w_buff1~0=v_~y$w_buff1~0_200, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_6, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_88, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_8|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_22|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_109, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_254, ~x~0=v_~x~0_80, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_6, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_650, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_38|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_31|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_28, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_28|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_32|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_16|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_58|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_50|, ULTIMATE.start_main_~#t1493~0.base=|v_ULTIMATE.start_main_~#t1493~0.base_26|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_76, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_44|, ~y$w_buff0~0=v_~y$w_buff0~0_308, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_151, ~y~0=v_~y~0_150, ULTIMATE.start_main_~#t1492~0.offset=|v_ULTIMATE.start_main_~#t1492~0.offset_19|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_30|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_44|, ULTIMATE.start_main_~#t1492~0.base=|v_ULTIMATE.start_main_~#t1492~0.base_26|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_26|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_96|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_24, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_31|, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_31|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_131, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_28|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_18|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_312, #valid=|v_#valid_60|, #memory_int=|v_#memory_int_23|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_8|, ~z~0=v_~z~0_51, ~weak$$choice2~0=v_~weak$$choice2~0_131, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_407} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_~#t1493~0.offset, ~y$read_delayed~0, ~y$mem_tmp~0, ~y$r_buff1_thd3~0, ULTIMATE.start_main_~#t1494~0.base, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ULTIMATE.start_main_~#t1494~0.offset, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_~#t1493~0.base, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_~#t1492~0.offset, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ULTIMATE.start_main_~#t1492~0.base, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:20:20,979 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [715] [715] L800-1-->L802: Formula: (and (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1493~0.base_13|) (not (= |v_ULTIMATE.start_main_~#t1493~0.base_13| 0)) (= |v_#valid_40| (store |v_#valid_41| |v_ULTIMATE.start_main_~#t1493~0.base_13| 1)) (= 0 |v_ULTIMATE.start_main_~#t1493~0.offset_11|) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t1493~0.base_13| 4)) (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1493~0.base_13| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1493~0.base_13|) |v_ULTIMATE.start_main_~#t1493~0.offset_11| 1)) |v_#memory_int_17|) (= 0 (select |v_#valid_41| |v_ULTIMATE.start_main_~#t1493~0.base_13|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_41|, #memory_int=|v_#memory_int_18|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_17|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, #length=|v_#length_17|, ULTIMATE.start_main_~#t1493~0.offset=|v_ULTIMATE.start_main_~#t1493~0.offset_11|, ULTIMATE.start_main_~#t1493~0.base=|v_ULTIMATE.start_main_~#t1493~0.base_13|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_#t~nondet15, #length, ULTIMATE.start_main_~#t1493~0.offset, ULTIMATE.start_main_~#t1493~0.base] because there is no mapped edge [2019-11-28 18:20:20,979 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L802-1-->L804: Formula: (and (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t1494~0.base_12| 4)) (= 0 |v_ULTIMATE.start_main_~#t1494~0.offset_10|) (= 0 (select |v_#valid_39| |v_ULTIMATE.start_main_~#t1494~0.base_12|)) (not (= 0 |v_ULTIMATE.start_main_~#t1494~0.base_12|)) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t1494~0.base_12|) (= (store |v_#valid_39| |v_ULTIMATE.start_main_~#t1494~0.base_12| 1) |v_#valid_38|) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1494~0.base_12| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1494~0.base_12|) |v_ULTIMATE.start_main_~#t1494~0.offset_10| 2)) |v_#memory_int_15|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_39|, #memory_int=|v_#memory_int_16|, #length=|v_#length_16|} OutVars{ULTIMATE.start_main_~#t1494~0.offset=|v_ULTIMATE.start_main_~#t1494~0.offset_10|, #StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_~#t1494~0.base=|v_ULTIMATE.start_main_~#t1494~0.base_12|, #valid=|v_#valid_38|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, #length=|v_#length_15|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1494~0.offset, ULTIMATE.start_main_~#t1494~0.base, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, #length] because there is no mapped edge [2019-11-28 18:20:20,980 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [641] [641] P2ENTRY-->L4-3: Formula: (and (not (= 0 v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_10)) (= 2 v_~y$w_buff0~0_40) (= v_~y$w_buff0_used~0_161 1) (= v_~y$w_buff0~0_41 v_~y$w_buff1~0_32) (= v_P2Thread1of1ForFork0_~arg.base_6 |v_P2Thread1of1ForFork0_#in~arg.base_8|) (= v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_10 |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|) (= |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6| (ite (not (and (not (= (mod v_~y$w_buff1_used~0_89 256) 0)) (not (= 0 (mod v_~y$w_buff0_used~0_161 256))))) 1 0)) (= v_P2Thread1of1ForFork0_~arg.offset_6 |v_P2Thread1of1ForFork0_#in~arg.offset_8|) (= v_~y$w_buff1_used~0_89 v_~y$w_buff0_used~0_162)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_8|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_162, ~y$w_buff0~0=v_~y$w_buff0~0_41, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_8|} OutVars{P2Thread1of1ForFork0_~arg.base=v_P2Thread1of1ForFork0_~arg.base_6, P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_8|, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_161, ~y$w_buff1~0=v_~y$w_buff1~0_32, ~y$w_buff0~0=v_~y$w_buff0~0_40, P2Thread1of1ForFork0_~arg.offset=v_P2Thread1of1ForFork0_~arg.offset_6, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_8|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_10, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_89} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:20:20,982 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [704] [704] P0ENTRY-->P0EXIT: Formula: (and (= v_~z~0_35 1) (= 0 |v_P0Thread1of1ForFork1_#res.base_9|) (= 0 |v_P0Thread1of1ForFork1_#res.offset_9|) (= |v_P0Thread1of1ForFork1_#in~arg.base_21| v_P0Thread1of1ForFork1_~arg.base_19) (= v_P0Thread1of1ForFork1_~arg.offset_19 |v_P0Thread1of1ForFork1_#in~arg.offset_21|) (= v_~x~0_49 1) (= v_~__unbuffered_cnt~0_67 (+ v_~__unbuffered_cnt~0_68 1))) InVars {P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_21|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_68, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_21|} OutVars{P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_9|, P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_21|, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_9|, P0Thread1of1ForFork1_~arg.offset=v_P0Thread1of1ForFork1_~arg.offset_19, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_67, ~z~0=v_~z~0_35, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_21|, ~x~0=v_~x~0_49, P0Thread1of1ForFork1_~arg.base=v_P0Thread1of1ForFork1_~arg.base_19} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#res.offset, P0Thread1of1ForFork1_#res.base, P0Thread1of1ForFork1_~arg.offset, ~__unbuffered_cnt~0, ~z~0, ~x~0, P0Thread1of1ForFork1_~arg.base] because there is no mapped edge [2019-11-28 18:20:20,983 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [679] [679] L778-->L778-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-1527392779 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In-1527392779 256)))) (or (and (= ~y$w_buff0_used~0_In-1527392779 |P2Thread1of1ForFork0_#t~ite11_Out-1527392779|) (or .cse0 .cse1)) (and (= |P2Thread1of1ForFork0_#t~ite11_Out-1527392779| 0) (not .cse1) (not .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1527392779, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1527392779} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1527392779, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out-1527392779|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1527392779} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-11-28 18:20:20,984 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [694] [694] L748-2-->L748-4: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff1_thd2~0_In2036878197 256))) (.cse0 (= 0 (mod ~y$w_buff1_used~0_In2036878197 256)))) (or (and (= |P1Thread1of1ForFork2_#t~ite3_Out2036878197| ~y$w_buff1~0_In2036878197) (not .cse0) (not .cse1)) (and (= |P1Thread1of1ForFork2_#t~ite3_Out2036878197| ~y~0_In2036878197) (or .cse1 .cse0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In2036878197, ~y$w_buff1~0=~y$w_buff1~0_In2036878197, ~y~0=~y~0_In2036878197, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2036878197} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In2036878197, ~y$w_buff1~0=~y$w_buff1~0_In2036878197, ~y~0=~y~0_In2036878197, P1Thread1of1ForFork2_#t~ite3=|P1Thread1of1ForFork2_#t~ite3_Out2036878197|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2036878197} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-11-28 18:20:20,984 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [618] [618] L748-4-->L749: Formula: (= |v_P1Thread1of1ForFork2_#t~ite3_10| v_~y~0_21) InVars {P1Thread1of1ForFork2_#t~ite3=|v_P1Thread1of1ForFork2_#t~ite3_10|} OutVars{P1Thread1of1ForFork2_#t~ite4=|v_P1Thread1of1ForFork2_#t~ite4_11|, ~y~0=v_~y~0_21, P1Thread1of1ForFork2_#t~ite3=|v_P1Thread1of1ForFork2_#t~ite3_9|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite4, ~y~0, P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-11-28 18:20:20,984 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [677] [677] L749-->L749-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd2~0_In273667384 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In273667384 256)))) (or (and (not .cse0) (= 0 |P1Thread1of1ForFork2_#t~ite5_Out273667384|) (not .cse1)) (and (or .cse0 .cse1) (= |P1Thread1of1ForFork2_#t~ite5_Out273667384| ~y$w_buff0_used~0_In273667384)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In273667384, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In273667384} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In273667384, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In273667384, P1Thread1of1ForFork2_#t~ite5=|P1Thread1of1ForFork2_#t~ite5_Out273667384|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-11-28 18:20:20,985 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [689] [689] L750-->L750-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In-1361278008 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In-1361278008 256))) (.cse2 (= (mod ~y$r_buff1_thd2~0_In-1361278008 256) 0)) (.cse3 (= 0 (mod ~y$w_buff1_used~0_In-1361278008 256)))) (or (and (= |P1Thread1of1ForFork2_#t~ite6_Out-1361278008| ~y$w_buff1_used~0_In-1361278008) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P1Thread1of1ForFork2_#t~ite6_Out-1361278008|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1361278008, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1361278008, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1361278008, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1361278008} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1361278008, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1361278008, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1361278008, P1Thread1of1ForFork2_#t~ite6=|P1Thread1of1ForFork2_#t~ite6_Out-1361278008|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1361278008} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-11-28 18:20:20,985 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [688] [688] L751-->L751-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd2~0_In1285062482 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In1285062482 256)))) (or (and (not .cse0) (= 0 |P1Thread1of1ForFork2_#t~ite7_Out1285062482|) (not .cse1)) (and (or .cse0 .cse1) (= ~y$r_buff0_thd2~0_In1285062482 |P1Thread1of1ForFork2_#t~ite7_Out1285062482|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1285062482, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1285062482} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1285062482, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1285062482, P1Thread1of1ForFork2_#t~ite7=|P1Thread1of1ForFork2_#t~ite7_Out1285062482|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-11-28 18:20:20,986 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [690] [690] L779-->L779-2: Formula: (let ((.cse3 (= (mod ~y$r_buff0_thd3~0_In-1722087360 256) 0)) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In-1722087360 256))) (.cse0 (= 0 (mod ~y$w_buff1_used~0_In-1722087360 256))) (.cse1 (= (mod ~y$r_buff1_thd3~0_In-1722087360 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P2Thread1of1ForFork0_#t~ite12_Out-1722087360| ~y$w_buff1_used~0_In-1722087360)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1))) (= |P2Thread1of1ForFork0_#t~ite12_Out-1722087360| 0)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1722087360, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1722087360, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1722087360, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1722087360} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1722087360, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1722087360, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out-1722087360|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1722087360, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1722087360} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-11-28 18:20:20,986 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [686] [686] L752-->L752-2: Formula: (let ((.cse3 (= (mod ~y$w_buff0_used~0_In-2090380999 256) 0)) (.cse2 (= 0 (mod ~y$r_buff0_thd2~0_In-2090380999 256))) (.cse0 (= (mod ~y$w_buff1_used~0_In-2090380999 256) 0)) (.cse1 (= (mod ~y$r_buff1_thd2~0_In-2090380999 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork2_#t~ite8_Out-2090380999|)) (and (or .cse3 .cse2) (= ~y$r_buff1_thd2~0_In-2090380999 |P1Thread1of1ForFork2_#t~ite8_Out-2090380999|) (or .cse0 .cse1)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-2090380999, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2090380999, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-2090380999, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2090380999} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-2090380999, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2090380999, P1Thread1of1ForFork2_#t~ite8=|P1Thread1of1ForFork2_#t~ite8_Out-2090380999|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-2090380999, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2090380999} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-11-28 18:20:20,987 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L752-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= |v_P1Thread1of1ForFork2_#t~ite8_26| v_~y$r_buff1_thd2~0_56) (= (+ v_~__unbuffered_cnt~0_75 1) v_~__unbuffered_cnt~0_74)) InVars {P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_26|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_75} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_56, P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_25|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_74, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork2_#res.offset, P1Thread1of1ForFork2_#t~ite8, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-11-28 18:20:20,987 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L780-->L781: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In841071643 256))) (.cse2 (= (mod ~y$w_buff0_used~0_In841071643 256) 0)) (.cse0 (= ~y$r_buff0_thd3~0_In841071643 ~y$r_buff0_thd3~0_Out841071643))) (or (and .cse0 .cse1) (and (not .cse1) (= ~y$r_buff0_thd3~0_Out841071643 0) (not .cse2)) (and .cse2 .cse0))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In841071643, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In841071643} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In841071643, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out841071643, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out841071643|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-11-28 18:20:20,987 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [681] [681] L781-->L781-2: Formula: (let ((.cse2 (= 0 (mod ~y$r_buff0_thd3~0_In1375844735 256))) (.cse3 (= 0 (mod ~y$w_buff0_used~0_In1375844735 256))) (.cse0 (= (mod ~y$w_buff1_used~0_In1375844735 256) 0)) (.cse1 (= (mod ~y$r_buff1_thd3~0_In1375844735 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork0_#t~ite14_Out1375844735| 0)) (and (= |P2Thread1of1ForFork0_#t~ite14_Out1375844735| ~y$r_buff1_thd3~0_In1375844735) (or .cse2 .cse3) (or .cse0 .cse1)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1375844735, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1375844735, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1375844735, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1375844735} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out1375844735|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1375844735, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1375844735, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1375844735, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1375844735} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-11-28 18:20:20,987 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [722] [722] L781-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#t~ite14_38| v_~y$r_buff1_thd3~0_68) (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0) (= v_~__unbuffered_cnt~0_90 (+ v_~__unbuffered_cnt~0_91 1))) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_38|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_91} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_37|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_68, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_90, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-11-28 18:20:20,988 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [617] [617] L804-1-->L810: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_6 256))) (= v_~main$tmp_guard0~0_6 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_13) 1 0)) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_5|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet17, ~main$tmp_guard0~0] because there is no mapped edge [2019-11-28 18:20:20,988 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L810-2-->L810-4: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff1_used~0_In-607942364 256))) (.cse0 (= (mod ~y$r_buff1_thd0~0_In-607942364 256) 0))) (or (and (= ~y$w_buff1~0_In-607942364 |ULTIMATE.start_main_#t~ite18_Out-607942364|) (not .cse0) (not .cse1)) (and (= |ULTIMATE.start_main_#t~ite18_Out-607942364| ~y~0_In-607942364) (or .cse1 .cse0)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-607942364, ~y~0=~y~0_In-607942364, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-607942364, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-607942364} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-607942364, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out-607942364|, ~y~0=~y~0_In-607942364, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-607942364, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-607942364} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18] because there is no mapped edge [2019-11-28 18:20:20,988 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [636] [636] L810-4-->L811: Formula: (= v_~y~0_40 |v_ULTIMATE.start_main_#t~ite18_13|) InVars {ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_13|} OutVars{ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_12|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_12|, ~y~0=v_~y~0_40} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite19, ~y~0] because there is no mapped edge [2019-11-28 18:20:20,988 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [692] [692] L811-->L811-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In-1423681203 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In-1423681203 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite20_Out-1423681203| 0) (not .cse1)) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite20_Out-1423681203| ~y$w_buff0_used~0_In-1423681203)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1423681203, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1423681203} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1423681203, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1423681203, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out-1423681203|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-11-28 18:20:20,989 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [678] [678] L812-->L812-2: Formula: (let ((.cse3 (= (mod ~y$r_buff1_thd0~0_In713027833 256) 0)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In713027833 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In713027833 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In713027833 256)))) (or (and (= ~y$w_buff1_used~0_In713027833 |ULTIMATE.start_main_#t~ite21_Out713027833|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0))) (= 0 |ULTIMATE.start_main_#t~ite21_Out713027833|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In713027833, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In713027833, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In713027833, ~y$w_buff1_used~0=~y$w_buff1_used~0_In713027833} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In713027833, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In713027833, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out713027833|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In713027833, ~y$w_buff1_used~0=~y$w_buff1_used~0_In713027833} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-11-28 18:20:20,989 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [682] [682] L813-->L813-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In104154828 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In104154828 256) 0))) (or (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite22_Out104154828| 0)) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite22_Out104154828| ~y$r_buff0_thd0~0_In104154828)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In104154828, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In104154828} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In104154828, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In104154828, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out104154828|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-11-28 18:20:20,990 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [684] [684] L814-->L814-2: Formula: (let ((.cse3 (= (mod ~y$w_buff0_used~0_In-883137790 256) 0)) (.cse2 (= 0 (mod ~y$r_buff0_thd0~0_In-883137790 256))) (.cse0 (= (mod ~y$w_buff1_used~0_In-883137790 256) 0)) (.cse1 (= (mod ~y$r_buff1_thd0~0_In-883137790 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite23_Out-883137790| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite23_Out-883137790| ~y$r_buff1_thd0~0_In-883137790)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-883137790, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-883137790, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-883137790, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-883137790} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-883137790, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-883137790, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-883137790, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out-883137790|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-883137790} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-11-28 18:20:20,991 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L822-->L822-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In1224882351 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite29_In1224882351| |ULTIMATE.start_main_#t~ite29_Out1224882351|) (= |ULTIMATE.start_main_#t~ite30_Out1224882351| ~y$w_buff0~0_In1224882351) (not .cse0)) (and .cse0 (= |ULTIMATE.start_main_#t~ite30_Out1224882351| |ULTIMATE.start_main_#t~ite29_Out1224882351|) (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In1224882351 256) 0))) (or (and .cse1 (= 0 (mod ~y$r_buff1_thd0~0_In1224882351 256))) (= (mod ~y$w_buff0_used~0_In1224882351 256) 0) (and .cse1 (= (mod ~y$w_buff1_used~0_In1224882351 256) 0)))) (= ~y$w_buff0~0_In1224882351 |ULTIMATE.start_main_#t~ite29_Out1224882351|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1224882351, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_In1224882351|, ~y$w_buff0~0=~y$w_buff0~0_In1224882351, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1224882351, ~weak$$choice2~0=~weak$$choice2~0_In1224882351, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1224882351, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1224882351} OutVars{ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out1224882351|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1224882351, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out1224882351|, ~y$w_buff0~0=~y$w_buff0~0_In1224882351, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1224882351, ~weak$$choice2~0=~weak$$choice2~0_In1224882351, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1224882351, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1224882351} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-11-28 18:20:20,994 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [631] [631] L826-->L827: Formula: (and (not (= (mod v_~weak$$choice2~0_27 256) 0)) (= v_~y$r_buff0_thd0~0_86 v_~y$r_buff0_thd0~0_85)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_86, ~weak$$choice2~0=v_~weak$$choice2~0_27} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_6|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_10|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_85, ~weak$$choice2~0=v_~weak$$choice2~0_27, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-11-28 18:20:20,995 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [709] [709] L829-->L832-1: Formula: (and (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5| (mod v_~main$tmp_guard1~0_12 256)) (= v_~y~0_109 v_~y$mem_tmp~0_21) (not (= 0 (mod v_~y$flush_delayed~0_33 256))) (= 0 v_~y$flush_delayed~0_32)) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_21, ~y$flush_delayed~0=v_~y$flush_delayed~0_33, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_21, ~y$flush_delayed~0=v_~y$flush_delayed~0_32, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_24|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12, ~y~0=v_~y~0_109, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[~y$flush_delayed~0, ULTIMATE.start_main_#t~ite46, ~y~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-11-28 18:20:20,995 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] L832-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-11-28 18:20:21,096 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 06:20:21 BasicIcfg [2019-11-28 18:20:21,096 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-28 18:20:21,097 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-28 18:20:21,097 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-28 18:20:21,097 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-28 18:20:21,098 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:20:00" (3/4) ... [2019-11-28 18:20:21,100 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-28 18:20:21,101 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [740] [740] ULTIMATE.startENTRY-->L800: Formula: (let ((.cse0 (store |v_#valid_62| 0 0))) (and (= 0 v_~y$read_delayed_var~0.base_6) (= 0 v_~weak$$choice0~0_25) (= 0 v_~y$r_buff0_thd3~0_151) (= |v_#length_23| (store |v_#length_24| |v_ULTIMATE.start_main_~#t1492~0.base_26| 4)) (= v_~y$w_buff1~0_200 0) (= v_~y$w_buff0_used~0_650 0) (= v_~__unbuffered_cnt~0_109 0) (< 0 |v_#StackHeapBarrier_16|) (< |v_#StackHeapBarrier_16| |v_ULTIMATE.start_main_~#t1492~0.base_26|) (= 0 v_~y$w_buff0~0_308) (= 0 v_~y$r_buff1_thd3~0_122) (= v_~y$read_delayed~0_6 0) (= 0 v_~y$r_buff1_thd1~0_76) (= 0 |v_ULTIMATE.start_main_~#t1492~0.offset_19|) (= v_~z~0_51 0) (= v_~y$r_buff0_thd1~0_29 0) (= v_~main$tmp_guard1~0_28 0) (= v_~y$r_buff0_thd0~0_312 0) (= 0 v_~__unbuffered_p2_EAX~0_90) (= 0 v_~y$flush_delayed~0_45) (= v_~y$w_buff1_used~0_407 0) (= v_~y$r_buff0_thd2~0_88 0) (= |v_#NULL.offset_5| 0) (= (store |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1492~0.base_26| (store (select |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1492~0.base_26|) |v_ULTIMATE.start_main_~#t1492~0.offset_19| 0)) |v_#memory_int_23|) (= 0 v_~y$r_buff1_thd2~0_131) (= (store .cse0 |v_ULTIMATE.start_main_~#t1492~0.base_26| 1) |v_#valid_60|) (= v_~y$mem_tmp~0_31 0) (= 0 v_~y$read_delayed_var~0.offset_6) (= v_~y~0_150 0) (= v_~weak$$choice2~0_131 0) (= v_~y$r_buff1_thd0~0_254 0) (= v_~main$tmp_guard0~0_24 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t1492~0.base_26|)) (= 0 |v_#NULL.base_5|) (= v_~x~0_80 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_16|, #valid=|v_#valid_62|, #memory_int=|v_#memory_int_24|, #length=|v_#length_24|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_28|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_26|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_104|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_52|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_26|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_38|, ULTIMATE.start_main_~#t1493~0.offset=|v_ULTIMATE.start_main_~#t1493~0.offset_19|, ~y$read_delayed~0=v_~y$read_delayed~0_6, ~y$mem_tmp~0=v_~y$mem_tmp~0_31, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_122, ULTIMATE.start_main_~#t1494~0.base=|v_ULTIMATE.start_main_~#t1494~0.base_21|, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_29, ~y$flush_delayed~0=v_~y$flush_delayed~0_45, #length=|v_#length_23|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_90, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_34|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_142|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_44|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_31|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_98|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_27|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_26|, ULTIMATE.start_main_~#t1494~0.offset=|v_ULTIMATE.start_main_~#t1494~0.offset_14|, ~weak$$choice0~0=v_~weak$$choice0~0_25, #StackHeapBarrier=|v_#StackHeapBarrier_16|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_28|, ~y$w_buff1~0=v_~y$w_buff1~0_200, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_6, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_88, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_8|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_22|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_109, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_254, ~x~0=v_~x~0_80, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_6, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_650, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_38|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_31|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_28, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_28|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_32|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_16|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_58|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_50|, ULTIMATE.start_main_~#t1493~0.base=|v_ULTIMATE.start_main_~#t1493~0.base_26|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_76, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_44|, ~y$w_buff0~0=v_~y$w_buff0~0_308, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_151, ~y~0=v_~y~0_150, ULTIMATE.start_main_~#t1492~0.offset=|v_ULTIMATE.start_main_~#t1492~0.offset_19|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_30|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_44|, ULTIMATE.start_main_~#t1492~0.base=|v_ULTIMATE.start_main_~#t1492~0.base_26|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_26|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_96|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_24, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_31|, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_31|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_131, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_28|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_18|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_312, #valid=|v_#valid_60|, #memory_int=|v_#memory_int_23|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_8|, ~z~0=v_~z~0_51, ~weak$$choice2~0=v_~weak$$choice2~0_131, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_407} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_~#t1493~0.offset, ~y$read_delayed~0, ~y$mem_tmp~0, ~y$r_buff1_thd3~0, ULTIMATE.start_main_~#t1494~0.base, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ULTIMATE.start_main_~#t1494~0.offset, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_~#t1493~0.base, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_~#t1492~0.offset, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ULTIMATE.start_main_~#t1492~0.base, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:20:21,102 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [715] [715] L800-1-->L802: Formula: (and (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1493~0.base_13|) (not (= |v_ULTIMATE.start_main_~#t1493~0.base_13| 0)) (= |v_#valid_40| (store |v_#valid_41| |v_ULTIMATE.start_main_~#t1493~0.base_13| 1)) (= 0 |v_ULTIMATE.start_main_~#t1493~0.offset_11|) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t1493~0.base_13| 4)) (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1493~0.base_13| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1493~0.base_13|) |v_ULTIMATE.start_main_~#t1493~0.offset_11| 1)) |v_#memory_int_17|) (= 0 (select |v_#valid_41| |v_ULTIMATE.start_main_~#t1493~0.base_13|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_41|, #memory_int=|v_#memory_int_18|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_17|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, #length=|v_#length_17|, ULTIMATE.start_main_~#t1493~0.offset=|v_ULTIMATE.start_main_~#t1493~0.offset_11|, ULTIMATE.start_main_~#t1493~0.base=|v_ULTIMATE.start_main_~#t1493~0.base_13|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_#t~nondet15, #length, ULTIMATE.start_main_~#t1493~0.offset, ULTIMATE.start_main_~#t1493~0.base] because there is no mapped edge [2019-11-28 18:20:21,103 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L802-1-->L804: Formula: (and (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t1494~0.base_12| 4)) (= 0 |v_ULTIMATE.start_main_~#t1494~0.offset_10|) (= 0 (select |v_#valid_39| |v_ULTIMATE.start_main_~#t1494~0.base_12|)) (not (= 0 |v_ULTIMATE.start_main_~#t1494~0.base_12|)) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t1494~0.base_12|) (= (store |v_#valid_39| |v_ULTIMATE.start_main_~#t1494~0.base_12| 1) |v_#valid_38|) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1494~0.base_12| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1494~0.base_12|) |v_ULTIMATE.start_main_~#t1494~0.offset_10| 2)) |v_#memory_int_15|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_39|, #memory_int=|v_#memory_int_16|, #length=|v_#length_16|} OutVars{ULTIMATE.start_main_~#t1494~0.offset=|v_ULTIMATE.start_main_~#t1494~0.offset_10|, #StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_~#t1494~0.base=|v_ULTIMATE.start_main_~#t1494~0.base_12|, #valid=|v_#valid_38|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, #length=|v_#length_15|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1494~0.offset, ULTIMATE.start_main_~#t1494~0.base, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, #length] because there is no mapped edge [2019-11-28 18:20:21,103 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [641] [641] P2ENTRY-->L4-3: Formula: (and (not (= 0 v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_10)) (= 2 v_~y$w_buff0~0_40) (= v_~y$w_buff0_used~0_161 1) (= v_~y$w_buff0~0_41 v_~y$w_buff1~0_32) (= v_P2Thread1of1ForFork0_~arg.base_6 |v_P2Thread1of1ForFork0_#in~arg.base_8|) (= v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_10 |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|) (= |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6| (ite (not (and (not (= (mod v_~y$w_buff1_used~0_89 256) 0)) (not (= 0 (mod v_~y$w_buff0_used~0_161 256))))) 1 0)) (= v_P2Thread1of1ForFork0_~arg.offset_6 |v_P2Thread1of1ForFork0_#in~arg.offset_8|) (= v_~y$w_buff1_used~0_89 v_~y$w_buff0_used~0_162)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_8|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_162, ~y$w_buff0~0=v_~y$w_buff0~0_41, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_8|} OutVars{P2Thread1of1ForFork0_~arg.base=v_P2Thread1of1ForFork0_~arg.base_6, P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_8|, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_161, ~y$w_buff1~0=v_~y$w_buff1~0_32, ~y$w_buff0~0=v_~y$w_buff0~0_40, P2Thread1of1ForFork0_~arg.offset=v_P2Thread1of1ForFork0_~arg.offset_6, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_8|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_10, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_89} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:20:21,104 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [704] [704] P0ENTRY-->P0EXIT: Formula: (and (= v_~z~0_35 1) (= 0 |v_P0Thread1of1ForFork1_#res.base_9|) (= 0 |v_P0Thread1of1ForFork1_#res.offset_9|) (= |v_P0Thread1of1ForFork1_#in~arg.base_21| v_P0Thread1of1ForFork1_~arg.base_19) (= v_P0Thread1of1ForFork1_~arg.offset_19 |v_P0Thread1of1ForFork1_#in~arg.offset_21|) (= v_~x~0_49 1) (= v_~__unbuffered_cnt~0_67 (+ v_~__unbuffered_cnt~0_68 1))) InVars {P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_21|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_68, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_21|} OutVars{P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_9|, P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_21|, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_9|, P0Thread1of1ForFork1_~arg.offset=v_P0Thread1of1ForFork1_~arg.offset_19, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_67, ~z~0=v_~z~0_35, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_21|, ~x~0=v_~x~0_49, P0Thread1of1ForFork1_~arg.base=v_P0Thread1of1ForFork1_~arg.base_19} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#res.offset, P0Thread1of1ForFork1_#res.base, P0Thread1of1ForFork1_~arg.offset, ~__unbuffered_cnt~0, ~z~0, ~x~0, P0Thread1of1ForFork1_~arg.base] because there is no mapped edge [2019-11-28 18:20:21,105 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [679] [679] L778-->L778-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-1527392779 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In-1527392779 256)))) (or (and (= ~y$w_buff0_used~0_In-1527392779 |P2Thread1of1ForFork0_#t~ite11_Out-1527392779|) (or .cse0 .cse1)) (and (= |P2Thread1of1ForFork0_#t~ite11_Out-1527392779| 0) (not .cse1) (not .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1527392779, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1527392779} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1527392779, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out-1527392779|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1527392779} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-11-28 18:20:21,106 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [694] [694] L748-2-->L748-4: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff1_thd2~0_In2036878197 256))) (.cse0 (= 0 (mod ~y$w_buff1_used~0_In2036878197 256)))) (or (and (= |P1Thread1of1ForFork2_#t~ite3_Out2036878197| ~y$w_buff1~0_In2036878197) (not .cse0) (not .cse1)) (and (= |P1Thread1of1ForFork2_#t~ite3_Out2036878197| ~y~0_In2036878197) (or .cse1 .cse0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In2036878197, ~y$w_buff1~0=~y$w_buff1~0_In2036878197, ~y~0=~y~0_In2036878197, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2036878197} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In2036878197, ~y$w_buff1~0=~y$w_buff1~0_In2036878197, ~y~0=~y~0_In2036878197, P1Thread1of1ForFork2_#t~ite3=|P1Thread1of1ForFork2_#t~ite3_Out2036878197|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2036878197} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-11-28 18:20:21,106 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [618] [618] L748-4-->L749: Formula: (= |v_P1Thread1of1ForFork2_#t~ite3_10| v_~y~0_21) InVars {P1Thread1of1ForFork2_#t~ite3=|v_P1Thread1of1ForFork2_#t~ite3_10|} OutVars{P1Thread1of1ForFork2_#t~ite4=|v_P1Thread1of1ForFork2_#t~ite4_11|, ~y~0=v_~y~0_21, P1Thread1of1ForFork2_#t~ite3=|v_P1Thread1of1ForFork2_#t~ite3_9|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite4, ~y~0, P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-11-28 18:20:21,106 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [677] [677] L749-->L749-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd2~0_In273667384 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In273667384 256)))) (or (and (not .cse0) (= 0 |P1Thread1of1ForFork2_#t~ite5_Out273667384|) (not .cse1)) (and (or .cse0 .cse1) (= |P1Thread1of1ForFork2_#t~ite5_Out273667384| ~y$w_buff0_used~0_In273667384)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In273667384, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In273667384} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In273667384, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In273667384, P1Thread1of1ForFork2_#t~ite5=|P1Thread1of1ForFork2_#t~ite5_Out273667384|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-11-28 18:20:21,107 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [689] [689] L750-->L750-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In-1361278008 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In-1361278008 256))) (.cse2 (= (mod ~y$r_buff1_thd2~0_In-1361278008 256) 0)) (.cse3 (= 0 (mod ~y$w_buff1_used~0_In-1361278008 256)))) (or (and (= |P1Thread1of1ForFork2_#t~ite6_Out-1361278008| ~y$w_buff1_used~0_In-1361278008) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P1Thread1of1ForFork2_#t~ite6_Out-1361278008|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1361278008, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1361278008, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1361278008, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1361278008} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1361278008, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1361278008, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1361278008, P1Thread1of1ForFork2_#t~ite6=|P1Thread1of1ForFork2_#t~ite6_Out-1361278008|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1361278008} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-11-28 18:20:21,107 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [688] [688] L751-->L751-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd2~0_In1285062482 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In1285062482 256)))) (or (and (not .cse0) (= 0 |P1Thread1of1ForFork2_#t~ite7_Out1285062482|) (not .cse1)) (and (or .cse0 .cse1) (= ~y$r_buff0_thd2~0_In1285062482 |P1Thread1of1ForFork2_#t~ite7_Out1285062482|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1285062482, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1285062482} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1285062482, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1285062482, P1Thread1of1ForFork2_#t~ite7=|P1Thread1of1ForFork2_#t~ite7_Out1285062482|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-11-28 18:20:21,108 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [690] [690] L779-->L779-2: Formula: (let ((.cse3 (= (mod ~y$r_buff0_thd3~0_In-1722087360 256) 0)) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In-1722087360 256))) (.cse0 (= 0 (mod ~y$w_buff1_used~0_In-1722087360 256))) (.cse1 (= (mod ~y$r_buff1_thd3~0_In-1722087360 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P2Thread1of1ForFork0_#t~ite12_Out-1722087360| ~y$w_buff1_used~0_In-1722087360)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1))) (= |P2Thread1of1ForFork0_#t~ite12_Out-1722087360| 0)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1722087360, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1722087360, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1722087360, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1722087360} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1722087360, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1722087360, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out-1722087360|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1722087360, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1722087360} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-11-28 18:20:21,108 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [686] [686] L752-->L752-2: Formula: (let ((.cse3 (= (mod ~y$w_buff0_used~0_In-2090380999 256) 0)) (.cse2 (= 0 (mod ~y$r_buff0_thd2~0_In-2090380999 256))) (.cse0 (= (mod ~y$w_buff1_used~0_In-2090380999 256) 0)) (.cse1 (= (mod ~y$r_buff1_thd2~0_In-2090380999 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork2_#t~ite8_Out-2090380999|)) (and (or .cse3 .cse2) (= ~y$r_buff1_thd2~0_In-2090380999 |P1Thread1of1ForFork2_#t~ite8_Out-2090380999|) (or .cse0 .cse1)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-2090380999, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2090380999, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-2090380999, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2090380999} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-2090380999, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2090380999, P1Thread1of1ForFork2_#t~ite8=|P1Thread1of1ForFork2_#t~ite8_Out-2090380999|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-2090380999, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2090380999} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-11-28 18:20:21,109 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L752-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= |v_P1Thread1of1ForFork2_#t~ite8_26| v_~y$r_buff1_thd2~0_56) (= (+ v_~__unbuffered_cnt~0_75 1) v_~__unbuffered_cnt~0_74)) InVars {P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_26|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_75} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_56, P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_25|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_74, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork2_#res.offset, P1Thread1of1ForFork2_#t~ite8, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-11-28 18:20:21,109 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L780-->L781: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In841071643 256))) (.cse2 (= (mod ~y$w_buff0_used~0_In841071643 256) 0)) (.cse0 (= ~y$r_buff0_thd3~0_In841071643 ~y$r_buff0_thd3~0_Out841071643))) (or (and .cse0 .cse1) (and (not .cse1) (= ~y$r_buff0_thd3~0_Out841071643 0) (not .cse2)) (and .cse2 .cse0))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In841071643, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In841071643} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In841071643, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out841071643, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out841071643|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-11-28 18:20:21,109 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [681] [681] L781-->L781-2: Formula: (let ((.cse2 (= 0 (mod ~y$r_buff0_thd3~0_In1375844735 256))) (.cse3 (= 0 (mod ~y$w_buff0_used~0_In1375844735 256))) (.cse0 (= (mod ~y$w_buff1_used~0_In1375844735 256) 0)) (.cse1 (= (mod ~y$r_buff1_thd3~0_In1375844735 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork0_#t~ite14_Out1375844735| 0)) (and (= |P2Thread1of1ForFork0_#t~ite14_Out1375844735| ~y$r_buff1_thd3~0_In1375844735) (or .cse2 .cse3) (or .cse0 .cse1)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1375844735, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1375844735, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1375844735, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1375844735} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out1375844735|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1375844735, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1375844735, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1375844735, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1375844735} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-11-28 18:20:21,109 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [722] [722] L781-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#t~ite14_38| v_~y$r_buff1_thd3~0_68) (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0) (= v_~__unbuffered_cnt~0_90 (+ v_~__unbuffered_cnt~0_91 1))) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_38|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_91} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_37|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_68, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_90, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-11-28 18:20:21,110 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [617] [617] L804-1-->L810: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_6 256))) (= v_~main$tmp_guard0~0_6 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_13) 1 0)) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_5|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet17, ~main$tmp_guard0~0] because there is no mapped edge [2019-11-28 18:20:21,110 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L810-2-->L810-4: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff1_used~0_In-607942364 256))) (.cse0 (= (mod ~y$r_buff1_thd0~0_In-607942364 256) 0))) (or (and (= ~y$w_buff1~0_In-607942364 |ULTIMATE.start_main_#t~ite18_Out-607942364|) (not .cse0) (not .cse1)) (and (= |ULTIMATE.start_main_#t~ite18_Out-607942364| ~y~0_In-607942364) (or .cse1 .cse0)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-607942364, ~y~0=~y~0_In-607942364, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-607942364, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-607942364} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-607942364, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out-607942364|, ~y~0=~y~0_In-607942364, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-607942364, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-607942364} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18] because there is no mapped edge [2019-11-28 18:20:21,110 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [636] [636] L810-4-->L811: Formula: (= v_~y~0_40 |v_ULTIMATE.start_main_#t~ite18_13|) InVars {ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_13|} OutVars{ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_12|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_12|, ~y~0=v_~y~0_40} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite19, ~y~0] because there is no mapped edge [2019-11-28 18:20:21,111 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [692] [692] L811-->L811-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In-1423681203 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In-1423681203 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite20_Out-1423681203| 0) (not .cse1)) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite20_Out-1423681203| ~y$w_buff0_used~0_In-1423681203)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1423681203, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1423681203} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1423681203, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1423681203, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out-1423681203|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-11-28 18:20:21,111 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [678] [678] L812-->L812-2: Formula: (let ((.cse3 (= (mod ~y$r_buff1_thd0~0_In713027833 256) 0)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In713027833 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In713027833 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In713027833 256)))) (or (and (= ~y$w_buff1_used~0_In713027833 |ULTIMATE.start_main_#t~ite21_Out713027833|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0))) (= 0 |ULTIMATE.start_main_#t~ite21_Out713027833|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In713027833, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In713027833, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In713027833, ~y$w_buff1_used~0=~y$w_buff1_used~0_In713027833} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In713027833, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In713027833, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out713027833|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In713027833, ~y$w_buff1_used~0=~y$w_buff1_used~0_In713027833} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-11-28 18:20:21,112 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [682] [682] L813-->L813-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In104154828 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In104154828 256) 0))) (or (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite22_Out104154828| 0)) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite22_Out104154828| ~y$r_buff0_thd0~0_In104154828)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In104154828, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In104154828} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In104154828, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In104154828, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out104154828|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-11-28 18:20:21,112 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [684] [684] L814-->L814-2: Formula: (let ((.cse3 (= (mod ~y$w_buff0_used~0_In-883137790 256) 0)) (.cse2 (= 0 (mod ~y$r_buff0_thd0~0_In-883137790 256))) (.cse0 (= (mod ~y$w_buff1_used~0_In-883137790 256) 0)) (.cse1 (= (mod ~y$r_buff1_thd0~0_In-883137790 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite23_Out-883137790| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite23_Out-883137790| ~y$r_buff1_thd0~0_In-883137790)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-883137790, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-883137790, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-883137790, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-883137790} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-883137790, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-883137790, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-883137790, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out-883137790|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-883137790} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-11-28 18:20:21,114 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L822-->L822-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In1224882351 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite29_In1224882351| |ULTIMATE.start_main_#t~ite29_Out1224882351|) (= |ULTIMATE.start_main_#t~ite30_Out1224882351| ~y$w_buff0~0_In1224882351) (not .cse0)) (and .cse0 (= |ULTIMATE.start_main_#t~ite30_Out1224882351| |ULTIMATE.start_main_#t~ite29_Out1224882351|) (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In1224882351 256) 0))) (or (and .cse1 (= 0 (mod ~y$r_buff1_thd0~0_In1224882351 256))) (= (mod ~y$w_buff0_used~0_In1224882351 256) 0) (and .cse1 (= (mod ~y$w_buff1_used~0_In1224882351 256) 0)))) (= ~y$w_buff0~0_In1224882351 |ULTIMATE.start_main_#t~ite29_Out1224882351|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1224882351, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_In1224882351|, ~y$w_buff0~0=~y$w_buff0~0_In1224882351, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1224882351, ~weak$$choice2~0=~weak$$choice2~0_In1224882351, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1224882351, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1224882351} OutVars{ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out1224882351|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1224882351, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out1224882351|, ~y$w_buff0~0=~y$w_buff0~0_In1224882351, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1224882351, ~weak$$choice2~0=~weak$$choice2~0_In1224882351, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1224882351, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1224882351} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-11-28 18:20:21,116 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [631] [631] L826-->L827: Formula: (and (not (= (mod v_~weak$$choice2~0_27 256) 0)) (= v_~y$r_buff0_thd0~0_86 v_~y$r_buff0_thd0~0_85)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_86, ~weak$$choice2~0=v_~weak$$choice2~0_27} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_6|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_10|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_85, ~weak$$choice2~0=v_~weak$$choice2~0_27, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-11-28 18:20:21,117 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [709] [709] L829-->L832-1: Formula: (and (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5| (mod v_~main$tmp_guard1~0_12 256)) (= v_~y~0_109 v_~y$mem_tmp~0_21) (not (= 0 (mod v_~y$flush_delayed~0_33 256))) (= 0 v_~y$flush_delayed~0_32)) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_21, ~y$flush_delayed~0=v_~y$flush_delayed~0_33, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_21, ~y$flush_delayed~0=v_~y$flush_delayed~0_32, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_24|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12, ~y~0=v_~y~0_109, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[~y$flush_delayed~0, ULTIMATE.start_main_#t~ite46, ~y~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-11-28 18:20:21,118 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] L832-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-11-28 18:20:21,254 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2019-11-28 18:20:21,255 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-28 18:20:21,256 INFO L168 Benchmark]: Toolchain (without parser) took 23162.39 ms. Allocated memory was 1.0 GB in the beginning and 2.1 GB in the end (delta: 1.1 GB). Free memory was 953.7 MB in the beginning and 1.3 GB in the end (delta: -310.0 MB). Peak memory consumption was 773.7 MB. Max. memory is 11.5 GB. [2019-11-28 18:20:21,257 INFO L168 Benchmark]: CDTParser took 0.32 ms. Allocated memory is still 1.0 GB. Free memory is still 981.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 18:20:21,257 INFO L168 Benchmark]: CACSL2BoogieTranslator took 953.92 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 135.8 MB). Free memory was 948.3 MB in the beginning and 1.1 GB in the end (delta: -148.8 MB). Peak memory consumption was 20.6 MB. Max. memory is 11.5 GB. [2019-11-28 18:20:21,258 INFO L168 Benchmark]: Boogie Procedure Inliner took 73.08 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. [2019-11-28 18:20:21,258 INFO L168 Benchmark]: Boogie Preprocessor took 47.13 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 18:20:21,258 INFO L168 Benchmark]: RCFGBuilder took 889.27 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 51.1 MB). Peak memory consumption was 51.1 MB. Max. memory is 11.5 GB. [2019-11-28 18:20:21,259 INFO L168 Benchmark]: TraceAbstraction took 21035.12 ms. Allocated memory was 1.2 GB in the beginning and 2.1 GB in the end (delta: 947.9 MB). Free memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: -243.9 MB). Peak memory consumption was 704.0 MB. Max. memory is 11.5 GB. [2019-11-28 18:20:21,259 INFO L168 Benchmark]: Witness Printer took 158.25 ms. Allocated memory is still 2.1 GB. Free memory was 1.3 GB in the beginning and 1.3 GB in the end (delta: 19.6 MB). Peak memory consumption was 19.6 MB. Max. memory is 11.5 GB. [2019-11-28 18:20:21,261 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.32 ms. Allocated memory is still 1.0 GB. Free memory is still 981.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 953.92 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 135.8 MB). Free memory was 948.3 MB in the beginning and 1.1 GB in the end (delta: -148.8 MB). Peak memory consumption was 20.6 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 73.08 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 47.13 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 889.27 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 51.1 MB). Peak memory consumption was 51.1 MB. Max. memory is 11.5 GB. * TraceAbstraction took 21035.12 ms. Allocated memory was 1.2 GB in the beginning and 2.1 GB in the end (delta: 947.9 MB). Free memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: -243.9 MB). Peak memory consumption was 704.0 MB. Max. memory is 11.5 GB. * Witness Printer took 158.25 ms. Allocated memory is still 2.1 GB. Free memory was 1.3 GB in the beginning and 1.3 GB in the end (delta: 19.6 MB). Peak memory consumption was 19.6 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 5.1s, 162 ProgramPointsBefore, 83 ProgramPointsAfterwards, 193 TransitionsBefore, 92 TransitionsAfterwards, 11490 CoEnabledTransitionPairs, 7 FixpointIterations, 31 TrivialSequentialCompositions, 44 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 34 ConcurrentYvCompositions, 26 ChoiceCompositions, 3955 VarBasedMoverChecksPositive, 193 VarBasedMoverChecksNegative, 45 SemBasedMoverChecksPositive, 196 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 1.3s, 0 MoverChecksTotal, 48383 CheckedPairsTotal, 109 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L800] FCALL, FORK 0 pthread_create(&t1492, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L802] FCALL, FORK 0 pthread_create(&t1493, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L804] FCALL, FORK 0 pthread_create(&t1494, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L767] 3 y$r_buff1_thd0 = y$r_buff0_thd0 [L768] 3 y$r_buff1_thd1 = y$r_buff0_thd1 [L769] 3 y$r_buff1_thd2 = y$r_buff0_thd2 [L770] 3 y$r_buff1_thd3 = y$r_buff0_thd3 [L771] 3 y$r_buff0_thd3 = (_Bool)1 [L774] 3 __unbuffered_p2_EAX = z VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=0] [L777] EXPR 3 y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L742] 2 x = 2 [L745] 2 y = 1 VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L777] 3 y = y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) [L748] 2 y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L749] 2 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$w_buff0_used [L750] 2 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used [L751] 2 y$r_buff0_thd2 = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$r_buff0_thd2 [L778] 3 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : y$w_buff0_used [L779] 3 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd3 || y$w_buff1_used && y$r_buff1_thd3 ? (_Bool)0 : y$w_buff1_used [L810] 0 y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L811] 0 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used [L812] 0 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$w_buff1_used [L813] 0 y$r_buff0_thd0 = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$r_buff0_thd0 [L814] 0 y$r_buff1_thd0 = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$r_buff1_thd0 [L817] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L818] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L819] 0 y$flush_delayed = weak$$choice2 [L820] 0 y$mem_tmp = y VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L821] EXPR 0 !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L821] 0 y = !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) [L822] 0 y$w_buff0 = weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) [L823] EXPR 0 weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L823] 0 y$w_buff1 = weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) [L824] EXPR 0 weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L824] 0 y$w_buff0_used = weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) [L825] EXPR 0 weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L825] 0 y$w_buff1_used = weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L827] EXPR 0 weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L827] 0 y$r_buff1_thd0 = weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L828] 0 main$tmp_guard1 = !(x == 2 && y == 2 && __unbuffered_p2_EAX == 0) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 153 locations, 2 error locations. Result: UNSAFE, OverallTime: 20.7s, OverallIterations: 18, TraceHistogramMax: 1, AutomataDifference: 6.1s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 1851 SDtfs, 1620 SDslu, 3936 SDs, 0 SdLazy, 1918 SolverSat, 118 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 2.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 136 GetRequests, 29 SyntacticMatches, 11 SemanticMatches, 96 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 151 ImplicationChecksByTransitivity, 1.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=28190occurred in iteration=5, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 4.7s AutomataMinimizationTime, 17 MinimizatonAttempts, 17291 StatesRemovedByMinimization, 13 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.5s SsaConstructionTime, 0.4s SatisfiabilityAnalysisTime, 1.6s InterpolantComputationTime, 733 NumberOfCodeBlocks, 733 NumberOfCodeBlocksAsserted, 18 NumberOfCheckSat, 659 ConstructedInterpolants, 0 QuantifiedInterpolants, 119775 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 17 InterpolantComputations, 17 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...