./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/pthread-wmm/mix056_rmo.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx12G -Xms1G -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/pthread-wmm/mix056_rmo.opt.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 43ce2500bbd191816156edc0be3de52055c93242 ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-11-28 18:20:01,774 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-28 18:20:01,777 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-28 18:20:01,793 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-28 18:20:01,793 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-28 18:20:01,794 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-28 18:20:01,796 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-28 18:20:01,798 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-28 18:20:01,800 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-28 18:20:01,801 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-28 18:20:01,802 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-28 18:20:01,804 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-28 18:20:01,804 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-28 18:20:01,805 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-28 18:20:01,807 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-28 18:20:01,808 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-28 18:20:01,809 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-28 18:20:01,811 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-28 18:20:01,813 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-28 18:20:01,815 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-28 18:20:01,817 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-28 18:20:01,819 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-28 18:20:01,820 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-28 18:20:01,822 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-28 18:20:01,824 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-28 18:20:01,825 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-28 18:20:01,825 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-28 18:20:01,826 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-28 18:20:01,827 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-28 18:20:01,828 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-28 18:20:01,829 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-28 18:20:01,830 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-28 18:20:01,831 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-28 18:20:01,832 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-28 18:20:01,833 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-28 18:20:01,833 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-28 18:20:01,834 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-28 18:20:01,835 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-28 18:20:01,835 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-28 18:20:01,836 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-28 18:20:01,837 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-28 18:20:01,838 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-28 18:20:01,854 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-28 18:20:01,855 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-28 18:20:01,856 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-28 18:20:01,856 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-28 18:20:01,857 INFO L138 SettingsManager]: * Use SBE=true [2019-11-28 18:20:01,857 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-28 18:20:01,857 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-28 18:20:01,858 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-28 18:20:01,858 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-28 18:20:01,858 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-28 18:20:01,858 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-28 18:20:01,859 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-28 18:20:01,859 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-28 18:20:01,859 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-28 18:20:01,860 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-28 18:20:01,860 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-28 18:20:01,860 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-28 18:20:01,860 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-28 18:20:01,861 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-28 18:20:01,861 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-28 18:20:01,861 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-28 18:20:01,862 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 18:20:01,862 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-28 18:20:01,862 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-28 18:20:01,863 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-28 18:20:01,863 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-28 18:20:01,863 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-28 18:20:01,863 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-28 18:20:01,864 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-11-28 18:20:01,864 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 43ce2500bbd191816156edc0be3de52055c93242 [2019-11-28 18:20:02,199 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-28 18:20:02,213 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-28 18:20:02,217 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-28 18:20:02,219 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-28 18:20:02,220 INFO L275 PluginConnector]: CDTParser initialized [2019-11-28 18:20:02,221 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/pthread-wmm/mix056_rmo.opt.i [2019-11-28 18:20:02,286 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7baed34a3/5c026f9fa08a4c52882855eeefd0c635/FLAG116eadb52 [2019-11-28 18:20:02,844 INFO L306 CDTParser]: Found 1 translation units. [2019-11-28 18:20:02,845 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/pthread-wmm/mix056_rmo.opt.i [2019-11-28 18:20:02,871 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7baed34a3/5c026f9fa08a4c52882855eeefd0c635/FLAG116eadb52 [2019-11-28 18:20:03,075 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7baed34a3/5c026f9fa08a4c52882855eeefd0c635 [2019-11-28 18:20:03,080 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-28 18:20:03,082 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-28 18:20:03,084 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-28 18:20:03,084 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-28 18:20:03,088 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-28 18:20:03,090 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 06:20:03" (1/1) ... [2019-11-28 18:20:03,093 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6ded1fde and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:03, skipping insertion in model container [2019-11-28 18:20:03,093 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 06:20:03" (1/1) ... [2019-11-28 18:20:03,102 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-11-28 18:20:03,150 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-11-28 18:20:03,706 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 18:20:03,719 INFO L203 MainTranslator]: Completed pre-run [2019-11-28 18:20:03,799 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 18:20:03,875 INFO L208 MainTranslator]: Completed translation [2019-11-28 18:20:03,875 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:03 WrapperNode [2019-11-28 18:20:03,876 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-28 18:20:03,877 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-28 18:20:03,877 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-28 18:20:03,877 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-28 18:20:03,884 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:03" (1/1) ... [2019-11-28 18:20:03,909 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:03" (1/1) ... [2019-11-28 18:20:03,948 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-28 18:20:03,948 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-28 18:20:03,949 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-28 18:20:03,949 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-28 18:20:03,960 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:03" (1/1) ... [2019-11-28 18:20:03,960 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:03" (1/1) ... [2019-11-28 18:20:03,970 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:03" (1/1) ... [2019-11-28 18:20:03,970 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:03" (1/1) ... [2019-11-28 18:20:03,984 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:03" (1/1) ... [2019-11-28 18:20:03,989 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:03" (1/1) ... [2019-11-28 18:20:03,996 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:03" (1/1) ... [2019-11-28 18:20:04,002 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-28 18:20:04,003 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-28 18:20:04,003 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-28 18:20:04,003 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-28 18:20:04,004 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:03" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 18:20:04,067 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-11-28 18:20:04,068 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-11-28 18:20:04,068 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-11-28 18:20:04,068 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-11-28 18:20:04,068 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-11-28 18:20:04,069 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-11-28 18:20:04,069 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-11-28 18:20:04,069 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-11-28 18:20:04,073 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-11-28 18:20:04,073 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-11-28 18:20:04,073 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-11-28 18:20:04,076 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-28 18:20:04,076 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-28 18:20:04,078 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-11-28 18:20:04,778 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-28 18:20:04,778 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-11-28 18:20:04,780 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:20:04 BoogieIcfgContainer [2019-11-28 18:20:04,780 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-28 18:20:04,781 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-28 18:20:04,781 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-28 18:20:04,785 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-28 18:20:04,785 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 06:20:03" (1/3) ... [2019-11-28 18:20:04,786 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@467e2062 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 06:20:04, skipping insertion in model container [2019-11-28 18:20:04,787 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:03" (2/3) ... [2019-11-28 18:20:04,787 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@467e2062 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 06:20:04, skipping insertion in model container [2019-11-28 18:20:04,788 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:20:04" (3/3) ... [2019-11-28 18:20:04,790 INFO L109 eAbstractionObserver]: Analyzing ICFG mix056_rmo.opt.i [2019-11-28 18:20:04,801 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-11-28 18:20:04,802 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-28 18:20:04,810 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-11-28 18:20:04,811 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-11-28 18:20:04,851 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,852 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,852 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,853 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,853 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,853 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,855 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,855 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,856 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,856 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,856 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,857 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,857 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,858 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,860 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,861 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,861 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,862 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,862 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,863 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,863 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,863 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,864 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,864 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,865 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,865 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,865 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,866 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,866 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,866 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,867 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,867 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,869 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,869 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,871 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,871 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,873 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,873 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,874 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,875 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,875 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,875 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,876 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,876 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,876 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,877 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,877 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,877 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,879 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,879 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,879 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,880 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,880 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,880 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,881 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,881 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,881 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,881 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,882 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,882 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,882 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,883 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,884 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,884 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,884 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,884 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,885 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,885 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,886 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,886 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:04,906 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-11-28 18:20:04,929 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-28 18:20:04,929 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-28 18:20:04,929 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-28 18:20:04,930 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-28 18:20:04,930 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-28 18:20:04,930 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-28 18:20:04,930 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-28 18:20:04,931 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-28 18:20:04,954 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 162 places, 193 transitions [2019-11-28 18:20:04,957 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 162 places, 193 transitions [2019-11-28 18:20:05,046 INFO L134 PetriNetUnfolder]: 41/190 cut-off events. [2019-11-28 18:20:05,047 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-11-28 18:20:05,063 INFO L76 FinitePrefix]: Finished finitePrefix Result has 200 conditions, 190 events. 41/190 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 465 event pairs. 9/156 useless extension candidates. Maximal degree in co-relation 161. Up to 2 conditions per place. [2019-11-28 18:20:05,085 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 162 places, 193 transitions [2019-11-28 18:20:05,134 INFO L134 PetriNetUnfolder]: 41/190 cut-off events. [2019-11-28 18:20:05,134 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-11-28 18:20:05,141 INFO L76 FinitePrefix]: Finished finitePrefix Result has 200 conditions, 190 events. 41/190 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 465 event pairs. 9/156 useless extension candidates. Maximal degree in co-relation 161. Up to 2 conditions per place. [2019-11-28 18:20:05,158 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 11490 [2019-11-28 18:20:05,160 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-11-28 18:20:09,808 WARN L192 SmtUtils]: Spent 264.00 ms on a formula simplification. DAG size of input: 87 DAG size of output: 85 [2019-11-28 18:20:09,956 WARN L192 SmtUtils]: Spent 145.00 ms on a formula simplification that was a NOOP. DAG size: 83 [2019-11-28 18:20:10,003 INFO L206 etLargeBlockEncoding]: Checked pairs total: 48383 [2019-11-28 18:20:10,004 INFO L214 etLargeBlockEncoding]: Total number of compositions: 109 [2019-11-28 18:20:10,008 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 83 places, 92 transitions [2019-11-28 18:20:11,539 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 16526 states. [2019-11-28 18:20:11,541 INFO L276 IsEmpty]: Start isEmpty. Operand 16526 states. [2019-11-28 18:20:11,549 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2019-11-28 18:20:11,549 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:11,550 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:11,551 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:11,557 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:11,557 INFO L82 PathProgramCache]: Analyzing trace with hash 2128093424, now seen corresponding path program 1 times [2019-11-28 18:20:11,567 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:11,567 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1237656668] [2019-11-28 18:20:11,568 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:11,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:11,865 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:11,865 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1237656668] [2019-11-28 18:20:11,867 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:11,867 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-11-28 18:20:11,868 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [790371922] [2019-11-28 18:20:11,875 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:20:11,875 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:11,890 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:20:11,891 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:11,893 INFO L87 Difference]: Start difference. First operand 16526 states. Second operand 3 states. [2019-11-28 18:20:12,321 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:12,322 INFO L93 Difference]: Finished difference Result 16398 states and 61580 transitions. [2019-11-28 18:20:12,322 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:20:12,324 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2019-11-28 18:20:12,324 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:12,510 INFO L225 Difference]: With dead ends: 16398 [2019-11-28 18:20:12,511 INFO L226 Difference]: Without dead ends: 16062 [2019-11-28 18:20:12,512 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:12,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16062 states. [2019-11-28 18:20:13,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16062 to 16062. [2019-11-28 18:20:13,380 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16062 states. [2019-11-28 18:20:13,473 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16062 states to 16062 states and 60376 transitions. [2019-11-28 18:20:13,475 INFO L78 Accepts]: Start accepts. Automaton has 16062 states and 60376 transitions. Word has length 7 [2019-11-28 18:20:13,476 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:13,476 INFO L462 AbstractCegarLoop]: Abstraction has 16062 states and 60376 transitions. [2019-11-28 18:20:13,476 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:20:13,477 INFO L276 IsEmpty]: Start isEmpty. Operand 16062 states and 60376 transitions. [2019-11-28 18:20:13,488 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-11-28 18:20:13,488 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:13,489 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:13,489 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:13,489 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:13,490 INFO L82 PathProgramCache]: Analyzing trace with hash -1390331573, now seen corresponding path program 1 times [2019-11-28 18:20:13,490 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:13,490 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1430179258] [2019-11-28 18:20:13,491 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:13,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:13,630 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:13,630 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1430179258] [2019-11-28 18:20:13,631 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:13,631 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:20:13,631 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1527467110] [2019-11-28 18:20:13,634 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:20:13,634 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:13,634 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:20:13,634 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:20:13,635 INFO L87 Difference]: Start difference. First operand 16062 states and 60376 transitions. Second operand 4 states. [2019-11-28 18:20:14,073 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:14,074 INFO L93 Difference]: Finished difference Result 24942 states and 90524 transitions. [2019-11-28 18:20:14,074 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:20:14,074 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-11-28 18:20:14,075 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:14,157 INFO L225 Difference]: With dead ends: 24942 [2019-11-28 18:20:14,158 INFO L226 Difference]: Without dead ends: 24928 [2019-11-28 18:20:14,161 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:20:14,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24928 states. [2019-11-28 18:20:15,202 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24928 to 22166. [2019-11-28 18:20:15,202 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22166 states. [2019-11-28 18:20:15,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22166 states to 22166 states and 81470 transitions. [2019-11-28 18:20:15,286 INFO L78 Accepts]: Start accepts. Automaton has 22166 states and 81470 transitions. Word has length 13 [2019-11-28 18:20:15,286 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:15,286 INFO L462 AbstractCegarLoop]: Abstraction has 22166 states and 81470 transitions. [2019-11-28 18:20:15,286 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:20:15,286 INFO L276 IsEmpty]: Start isEmpty. Operand 22166 states and 81470 transitions. [2019-11-28 18:20:15,288 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-11-28 18:20:15,288 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:15,288 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:15,289 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:15,289 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:15,289 INFO L82 PathProgramCache]: Analyzing trace with hash -1371832765, now seen corresponding path program 1 times [2019-11-28 18:20:15,290 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:15,290 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [939376929] [2019-11-28 18:20:15,290 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:15,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:15,386 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:15,387 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [939376929] [2019-11-28 18:20:15,387 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:15,387 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:20:15,387 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [162465814] [2019-11-28 18:20:15,388 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:20:15,388 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:15,388 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:20:15,389 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:20:15,389 INFO L87 Difference]: Start difference. First operand 22166 states and 81470 transitions. Second operand 4 states. [2019-11-28 18:20:15,678 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:15,679 INFO L93 Difference]: Finished difference Result 27782 states and 100994 transitions. [2019-11-28 18:20:15,679 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:20:15,679 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-11-28 18:20:15,679 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:15,801 INFO L225 Difference]: With dead ends: 27782 [2019-11-28 18:20:15,801 INFO L226 Difference]: Without dead ends: 27782 [2019-11-28 18:20:15,802 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:20:16,012 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27782 states. [2019-11-28 18:20:16,638 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27782 to 24630. [2019-11-28 18:20:16,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24630 states. [2019-11-28 18:20:16,786 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24630 states to 24630 states and 90262 transitions. [2019-11-28 18:20:16,787 INFO L78 Accepts]: Start accepts. Automaton has 24630 states and 90262 transitions. Word has length 13 [2019-11-28 18:20:16,787 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:16,788 INFO L462 AbstractCegarLoop]: Abstraction has 24630 states and 90262 transitions. [2019-11-28 18:20:16,788 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:20:16,790 INFO L276 IsEmpty]: Start isEmpty. Operand 24630 states and 90262 transitions. [2019-11-28 18:20:16,802 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-11-28 18:20:16,802 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:16,802 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:16,803 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:16,803 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:16,804 INFO L82 PathProgramCache]: Analyzing trace with hash -1003212910, now seen corresponding path program 1 times [2019-11-28 18:20:16,804 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:16,805 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [139787193] [2019-11-28 18:20:16,805 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:16,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:16,997 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:17,000 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [139787193] [2019-11-28 18:20:17,000 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:17,001 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:20:17,001 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1892594017] [2019-11-28 18:20:17,001 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:20:17,002 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:17,002 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:20:17,002 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:20:17,003 INFO L87 Difference]: Start difference. First operand 24630 states and 90262 transitions. Second operand 5 states. [2019-11-28 18:20:17,976 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:17,977 INFO L93 Difference]: Finished difference Result 33042 states and 118962 transitions. [2019-11-28 18:20:17,977 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-11-28 18:20:17,978 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-11-28 18:20:17,978 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:18,099 INFO L225 Difference]: With dead ends: 33042 [2019-11-28 18:20:18,100 INFO L226 Difference]: Without dead ends: 33028 [2019-11-28 18:20:18,101 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-11-28 18:20:18,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33028 states. [2019-11-28 18:20:18,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33028 to 24716. [2019-11-28 18:20:18,903 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24716 states. [2019-11-28 18:20:18,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24716 states to 24716 states and 90325 transitions. [2019-11-28 18:20:18,982 INFO L78 Accepts]: Start accepts. Automaton has 24716 states and 90325 transitions. Word has length 19 [2019-11-28 18:20:18,983 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:18,983 INFO L462 AbstractCegarLoop]: Abstraction has 24716 states and 90325 transitions. [2019-11-28 18:20:18,983 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:20:18,983 INFO L276 IsEmpty]: Start isEmpty. Operand 24716 states and 90325 transitions. [2019-11-28 18:20:19,012 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-11-28 18:20:19,013 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:19,013 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:19,013 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:19,013 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:19,014 INFO L82 PathProgramCache]: Analyzing trace with hash -1251036613, now seen corresponding path program 1 times [2019-11-28 18:20:19,014 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:19,014 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [570529840] [2019-11-28 18:20:19,014 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:19,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:19,077 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:19,077 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [570529840] [2019-11-28 18:20:19,078 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:19,078 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:20:19,078 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [164355915] [2019-11-28 18:20:19,078 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:20:19,079 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:19,079 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:20:19,079 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:19,079 INFO L87 Difference]: Start difference. First operand 24716 states and 90325 transitions. Second operand 3 states. [2019-11-28 18:20:19,308 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:19,308 INFO L93 Difference]: Finished difference Result 30008 states and 109703 transitions. [2019-11-28 18:20:19,309 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:20:19,309 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-11-28 18:20:19,309 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:19,900 INFO L225 Difference]: With dead ends: 30008 [2019-11-28 18:20:19,900 INFO L226 Difference]: Without dead ends: 30008 [2019-11-28 18:20:19,901 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:20,100 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30008 states. [2019-11-28 18:20:20,539 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30008 to 28190. [2019-11-28 18:20:20,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28190 states. [2019-11-28 18:20:20,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28190 states to 28190 states and 103378 transitions. [2019-11-28 18:20:20,610 INFO L78 Accepts]: Start accepts. Automaton has 28190 states and 103378 transitions. Word has length 27 [2019-11-28 18:20:20,610 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:20,610 INFO L462 AbstractCegarLoop]: Abstraction has 28190 states and 103378 transitions. [2019-11-28 18:20:20,610 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:20:20,611 INFO L276 IsEmpty]: Start isEmpty. Operand 28190 states and 103378 transitions. [2019-11-28 18:20:20,636 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-11-28 18:20:20,637 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:20,637 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:20,637 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:20,637 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:20,638 INFO L82 PathProgramCache]: Analyzing trace with hash -1250824263, now seen corresponding path program 1 times [2019-11-28 18:20:20,638 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:20,638 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1658211544] [2019-11-28 18:20:20,638 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:20,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:20,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:20,690 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1658211544] [2019-11-28 18:20:20,691 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:20,691 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:20:20,691 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1500474528] [2019-11-28 18:20:20,691 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:20:20,691 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:20,692 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:20:20,692 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:20,692 INFO L87 Difference]: Start difference. First operand 28190 states and 103378 transitions. Second operand 3 states. [2019-11-28 18:20:20,759 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:20,760 INFO L93 Difference]: Finished difference Result 16100 states and 51114 transitions. [2019-11-28 18:20:20,760 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:20:20,760 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-11-28 18:20:20,760 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:20,785 INFO L225 Difference]: With dead ends: 16100 [2019-11-28 18:20:20,786 INFO L226 Difference]: Without dead ends: 16100 [2019-11-28 18:20:20,786 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:20,851 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16100 states. [2019-11-28 18:20:21,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16100 to 16100. [2019-11-28 18:20:21,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16100 states. [2019-11-28 18:20:21,173 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16100 states to 16100 states and 51114 transitions. [2019-11-28 18:20:21,174 INFO L78 Accepts]: Start accepts. Automaton has 16100 states and 51114 transitions. Word has length 27 [2019-11-28 18:20:21,174 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:21,174 INFO L462 AbstractCegarLoop]: Abstraction has 16100 states and 51114 transitions. [2019-11-28 18:20:21,174 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:20:21,175 INFO L276 IsEmpty]: Start isEmpty. Operand 16100 states and 51114 transitions. [2019-11-28 18:20:21,188 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-11-28 18:20:21,189 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:21,189 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:21,189 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:21,189 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:21,190 INFO L82 PathProgramCache]: Analyzing trace with hash 411430761, now seen corresponding path program 1 times [2019-11-28 18:20:21,190 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:21,191 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [967029795] [2019-11-28 18:20:21,191 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:21,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:21,278 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:21,279 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [967029795] [2019-11-28 18:20:21,279 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:21,279 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:20:21,279 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2070165512] [2019-11-28 18:20:21,280 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:20:21,280 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:21,281 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:20:21,281 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:20:21,281 INFO L87 Difference]: Start difference. First operand 16100 states and 51114 transitions. Second operand 4 states. [2019-11-28 18:20:21,305 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:21,306 INFO L93 Difference]: Finished difference Result 2377 states and 5510 transitions. [2019-11-28 18:20:21,306 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-28 18:20:21,307 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 28 [2019-11-28 18:20:21,307 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:21,310 INFO L225 Difference]: With dead ends: 2377 [2019-11-28 18:20:21,311 INFO L226 Difference]: Without dead ends: 2377 [2019-11-28 18:20:21,312 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:20:21,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2377 states. [2019-11-28 18:20:21,341 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2377 to 2377. [2019-11-28 18:20:21,342 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2377 states. [2019-11-28 18:20:21,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2377 states to 2377 states and 5510 transitions. [2019-11-28 18:20:21,351 INFO L78 Accepts]: Start accepts. Automaton has 2377 states and 5510 transitions. Word has length 28 [2019-11-28 18:20:21,351 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:21,351 INFO L462 AbstractCegarLoop]: Abstraction has 2377 states and 5510 transitions. [2019-11-28 18:20:21,351 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:20:21,351 INFO L276 IsEmpty]: Start isEmpty. Operand 2377 states and 5510 transitions. [2019-11-28 18:20:21,358 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2019-11-28 18:20:21,358 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:21,359 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:21,359 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:21,359 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:21,359 INFO L82 PathProgramCache]: Analyzing trace with hash -1388136454, now seen corresponding path program 1 times [2019-11-28 18:20:21,362 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:21,363 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1022665461] [2019-11-28 18:20:21,363 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:21,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:21,483 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:21,484 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1022665461] [2019-11-28 18:20:21,484 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:21,484 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 18:20:21,484 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [945489708] [2019-11-28 18:20:21,484 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:20:21,485 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:21,485 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:20:21,486 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:20:21,486 INFO L87 Difference]: Start difference. First operand 2377 states and 5510 transitions. Second operand 5 states. [2019-11-28 18:20:21,509 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:21,509 INFO L93 Difference]: Finished difference Result 678 states and 1563 transitions. [2019-11-28 18:20:21,510 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:20:21,510 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 40 [2019-11-28 18:20:21,510 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:21,512 INFO L225 Difference]: With dead ends: 678 [2019-11-28 18:20:21,512 INFO L226 Difference]: Without dead ends: 678 [2019-11-28 18:20:21,512 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:20:21,515 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 678 states. [2019-11-28 18:20:21,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 678 to 622. [2019-11-28 18:20:21,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 622 states. [2019-11-28 18:20:21,523 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 622 states to 622 states and 1431 transitions. [2019-11-28 18:20:21,523 INFO L78 Accepts]: Start accepts. Automaton has 622 states and 1431 transitions. Word has length 40 [2019-11-28 18:20:21,525 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:21,525 INFO L462 AbstractCegarLoop]: Abstraction has 622 states and 1431 transitions. [2019-11-28 18:20:21,525 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:20:21,526 INFO L276 IsEmpty]: Start isEmpty. Operand 622 states and 1431 transitions. [2019-11-28 18:20:21,527 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-11-28 18:20:21,527 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:21,528 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:21,528 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:21,528 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:21,528 INFO L82 PathProgramCache]: Analyzing trace with hash -826083081, now seen corresponding path program 1 times [2019-11-28 18:20:21,529 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:21,529 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1325937398] [2019-11-28 18:20:21,529 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:21,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:21,637 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:21,638 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1325937398] [2019-11-28 18:20:21,638 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:21,638 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 18:20:21,638 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2069279590] [2019-11-28 18:20:21,639 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:20:21,639 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:21,639 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:20:21,640 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:20:21,640 INFO L87 Difference]: Start difference. First operand 622 states and 1431 transitions. Second operand 5 states. [2019-11-28 18:20:21,842 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:21,843 INFO L93 Difference]: Finished difference Result 911 states and 2103 transitions. [2019-11-28 18:20:21,843 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 18:20:21,843 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 55 [2019-11-28 18:20:21,843 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:21,844 INFO L225 Difference]: With dead ends: 911 [2019-11-28 18:20:21,844 INFO L226 Difference]: Without dead ends: 911 [2019-11-28 18:20:21,845 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-11-28 18:20:21,846 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 911 states. [2019-11-28 18:20:21,852 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 911 to 821. [2019-11-28 18:20:21,852 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 821 states. [2019-11-28 18:20:21,854 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 821 states to 821 states and 1898 transitions. [2019-11-28 18:20:21,854 INFO L78 Accepts]: Start accepts. Automaton has 821 states and 1898 transitions. Word has length 55 [2019-11-28 18:20:21,855 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:21,855 INFO L462 AbstractCegarLoop]: Abstraction has 821 states and 1898 transitions. [2019-11-28 18:20:21,855 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:20:21,855 INFO L276 IsEmpty]: Start isEmpty. Operand 821 states and 1898 transitions. [2019-11-28 18:20:21,857 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-11-28 18:20:21,857 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:21,857 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:21,858 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:21,858 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:21,858 INFO L82 PathProgramCache]: Analyzing trace with hash 297273929, now seen corresponding path program 2 times [2019-11-28 18:20:21,858 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:21,859 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1376355624] [2019-11-28 18:20:21,859 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:21,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:21,954 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:21,955 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1376355624] [2019-11-28 18:20:21,955 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:21,955 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-28 18:20:21,956 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1031660527] [2019-11-28 18:20:21,956 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-28 18:20:21,956 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:21,957 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-28 18:20:21,957 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-11-28 18:20:21,957 INFO L87 Difference]: Start difference. First operand 821 states and 1898 transitions. Second operand 6 states. [2019-11-28 18:20:22,270 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:22,271 INFO L93 Difference]: Finished difference Result 1208 states and 2794 transitions. [2019-11-28 18:20:22,271 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-11-28 18:20:22,271 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 55 [2019-11-28 18:20:22,271 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:22,273 INFO L225 Difference]: With dead ends: 1208 [2019-11-28 18:20:22,273 INFO L226 Difference]: Without dead ends: 1208 [2019-11-28 18:20:22,273 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2019-11-28 18:20:22,275 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1208 states. [2019-11-28 18:20:22,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1208 to 893. [2019-11-28 18:20:22,285 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 893 states. [2019-11-28 18:20:22,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 893 states to 893 states and 2076 transitions. [2019-11-28 18:20:22,287 INFO L78 Accepts]: Start accepts. Automaton has 893 states and 2076 transitions. Word has length 55 [2019-11-28 18:20:22,287 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:22,287 INFO L462 AbstractCegarLoop]: Abstraction has 893 states and 2076 transitions. [2019-11-28 18:20:22,288 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-28 18:20:22,288 INFO L276 IsEmpty]: Start isEmpty. Operand 893 states and 2076 transitions. [2019-11-28 18:20:22,290 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-11-28 18:20:22,290 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:22,290 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:22,290 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:22,291 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:22,291 INFO L82 PathProgramCache]: Analyzing trace with hash 1649215159, now seen corresponding path program 3 times [2019-11-28 18:20:22,291 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:22,292 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2143431017] [2019-11-28 18:20:22,292 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:22,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:22,365 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:22,366 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2143431017] [2019-11-28 18:20:22,366 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:22,367 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:20:22,367 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1916988933] [2019-11-28 18:20:22,368 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:20:22,368 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:22,369 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:20:22,369 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:22,369 INFO L87 Difference]: Start difference. First operand 893 states and 2076 transitions. Second operand 3 states. [2019-11-28 18:20:22,418 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:22,418 INFO L93 Difference]: Finished difference Result 892 states and 2074 transitions. [2019-11-28 18:20:22,419 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:20:22,419 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 55 [2019-11-28 18:20:22,419 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:22,421 INFO L225 Difference]: With dead ends: 892 [2019-11-28 18:20:22,422 INFO L226 Difference]: Without dead ends: 892 [2019-11-28 18:20:22,422 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:22,426 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 892 states. [2019-11-28 18:20:22,437 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 892 to 665. [2019-11-28 18:20:22,438 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 665 states. [2019-11-28 18:20:22,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 665 states to 665 states and 1545 transitions. [2019-11-28 18:20:22,440 INFO L78 Accepts]: Start accepts. Automaton has 665 states and 1545 transitions. Word has length 55 [2019-11-28 18:20:22,440 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:22,441 INFO L462 AbstractCegarLoop]: Abstraction has 665 states and 1545 transitions. [2019-11-28 18:20:22,441 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:20:22,441 INFO L276 IsEmpty]: Start isEmpty. Operand 665 states and 1545 transitions. [2019-11-28 18:20:22,443 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-11-28 18:20:22,443 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:22,443 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:22,443 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:22,444 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:22,444 INFO L82 PathProgramCache]: Analyzing trace with hash 1696047106, now seen corresponding path program 1 times [2019-11-28 18:20:22,444 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:22,445 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [373015159] [2019-11-28 18:20:22,445 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:22,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:22,504 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:22,505 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [373015159] [2019-11-28 18:20:22,505 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:22,506 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:20:22,506 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [893093889] [2019-11-28 18:20:22,506 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:20:22,507 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:22,507 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:20:22,507 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:22,508 INFO L87 Difference]: Start difference. First operand 665 states and 1545 transitions. Second operand 3 states. [2019-11-28 18:20:22,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:22,525 INFO L93 Difference]: Finished difference Result 633 states and 1431 transitions. [2019-11-28 18:20:22,526 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:20:22,526 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 56 [2019-11-28 18:20:22,527 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:22,527 INFO L225 Difference]: With dead ends: 633 [2019-11-28 18:20:22,528 INFO L226 Difference]: Without dead ends: 633 [2019-11-28 18:20:22,528 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:22,530 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 633 states. [2019-11-28 18:20:22,537 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 633 to 597. [2019-11-28 18:20:22,537 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 597 states. [2019-11-28 18:20:22,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 597 states to 597 states and 1345 transitions. [2019-11-28 18:20:22,539 INFO L78 Accepts]: Start accepts. Automaton has 597 states and 1345 transitions. Word has length 56 [2019-11-28 18:20:22,539 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:22,539 INFO L462 AbstractCegarLoop]: Abstraction has 597 states and 1345 transitions. [2019-11-28 18:20:22,540 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:20:22,540 INFO L276 IsEmpty]: Start isEmpty. Operand 597 states and 1345 transitions. [2019-11-28 18:20:22,541 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:20:22,541 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:22,542 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:22,542 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:22,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:22,542 INFO L82 PathProgramCache]: Analyzing trace with hash 816342703, now seen corresponding path program 1 times [2019-11-28 18:20:22,543 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:22,543 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1910792558] [2019-11-28 18:20:22,543 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:22,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:22,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:22,724 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1910792558] [2019-11-28 18:20:22,724 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:22,725 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-28 18:20:22,725 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [156399221] [2019-11-28 18:20:22,725 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-11-28 18:20:22,726 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:22,726 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-11-28 18:20:22,727 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-11-28 18:20:22,727 INFO L87 Difference]: Start difference. First operand 597 states and 1345 transitions. Second operand 7 states. [2019-11-28 18:20:22,882 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:22,882 INFO L93 Difference]: Finished difference Result 1128 states and 2330 transitions. [2019-11-28 18:20:22,883 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-11-28 18:20:22,883 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 57 [2019-11-28 18:20:22,884 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:22,885 INFO L225 Difference]: With dead ends: 1128 [2019-11-28 18:20:22,885 INFO L226 Difference]: Without dead ends: 755 [2019-11-28 18:20:22,885 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=40, Invalid=70, Unknown=0, NotChecked=0, Total=110 [2019-11-28 18:20:22,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 755 states. [2019-11-28 18:20:22,898 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 755 to 535. [2019-11-28 18:20:22,898 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 535 states. [2019-11-28 18:20:22,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 535 states to 535 states and 1166 transitions. [2019-11-28 18:20:22,900 INFO L78 Accepts]: Start accepts. Automaton has 535 states and 1166 transitions. Word has length 57 [2019-11-28 18:20:22,900 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:22,901 INFO L462 AbstractCegarLoop]: Abstraction has 535 states and 1166 transitions. [2019-11-28 18:20:22,901 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-11-28 18:20:22,901 INFO L276 IsEmpty]: Start isEmpty. Operand 535 states and 1166 transitions. [2019-11-28 18:20:22,902 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:20:22,903 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:22,903 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:22,903 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:22,904 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:22,904 INFO L82 PathProgramCache]: Analyzing trace with hash 729563135, now seen corresponding path program 2 times [2019-11-28 18:20:22,904 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:22,905 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [560830175] [2019-11-28 18:20:22,905 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:22,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:23,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:23,130 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [560830175] [2019-11-28 18:20:23,131 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:23,131 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 18:20:23,131 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [91190651] [2019-11-28 18:20:23,132 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-28 18:20:23,132 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:23,132 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-28 18:20:23,133 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-11-28 18:20:23,133 INFO L87 Difference]: Start difference. First operand 535 states and 1166 transitions. Second operand 6 states. [2019-11-28 18:20:23,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:23,231 INFO L93 Difference]: Finished difference Result 768 states and 1621 transitions. [2019-11-28 18:20:23,232 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 18:20:23,232 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 57 [2019-11-28 18:20:23,233 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:23,233 INFO L225 Difference]: With dead ends: 768 [2019-11-28 18:20:23,233 INFO L226 Difference]: Without dead ends: 231 [2019-11-28 18:20:23,234 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-11-28 18:20:23,235 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 231 states. [2019-11-28 18:20:23,239 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 231 to 207. [2019-11-28 18:20:23,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 207 states. [2019-11-28 18:20:23,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 364 transitions. [2019-11-28 18:20:23,240 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 364 transitions. Word has length 57 [2019-11-28 18:20:23,241 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:23,241 INFO L462 AbstractCegarLoop]: Abstraction has 207 states and 364 transitions. [2019-11-28 18:20:23,241 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-28 18:20:23,241 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 364 transitions. [2019-11-28 18:20:23,242 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:20:23,242 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:23,243 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:23,243 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:23,243 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:23,243 INFO L82 PathProgramCache]: Analyzing trace with hash -1516556909, now seen corresponding path program 3 times [2019-11-28 18:20:23,244 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:23,244 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1200982913] [2019-11-28 18:20:23,244 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:23,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:23,964 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:23,964 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1200982913] [2019-11-28 18:20:23,964 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:23,964 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-11-28 18:20:23,964 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1674807678] [2019-11-28 18:20:23,965 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-11-28 18:20:23,965 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:23,965 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-11-28 18:20:23,965 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=150, Unknown=0, NotChecked=0, Total=182 [2019-11-28 18:20:23,965 INFO L87 Difference]: Start difference. First operand 207 states and 364 transitions. Second operand 14 states. [2019-11-28 18:20:24,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:24,516 INFO L93 Difference]: Finished difference Result 363 states and 624 transitions. [2019-11-28 18:20:24,516 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-11-28 18:20:24,516 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 57 [2019-11-28 18:20:24,517 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:24,517 INFO L225 Difference]: With dead ends: 363 [2019-11-28 18:20:24,517 INFO L226 Difference]: Without dead ends: 333 [2019-11-28 18:20:24,518 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 86 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=130, Invalid=520, Unknown=0, NotChecked=0, Total=650 [2019-11-28 18:20:24,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 333 states. [2019-11-28 18:20:24,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 333 to 315. [2019-11-28 18:20:24,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 315 states. [2019-11-28 18:20:24,522 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 315 states to 315 states and 549 transitions. [2019-11-28 18:20:24,522 INFO L78 Accepts]: Start accepts. Automaton has 315 states and 549 transitions. Word has length 57 [2019-11-28 18:20:24,522 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:24,522 INFO L462 AbstractCegarLoop]: Abstraction has 315 states and 549 transitions. [2019-11-28 18:20:24,523 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-11-28 18:20:24,523 INFO L276 IsEmpty]: Start isEmpty. Operand 315 states and 549 transitions. [2019-11-28 18:20:24,523 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:20:24,524 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:24,524 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:24,524 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:24,524 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:24,524 INFO L82 PathProgramCache]: Analyzing trace with hash 731376245, now seen corresponding path program 4 times [2019-11-28 18:20:24,524 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:24,524 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1988086594] [2019-11-28 18:20:24,525 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:24,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 18:20:24,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 18:20:24,626 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-28 18:20:24,627 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-28 18:20:24,631 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [740] [740] ULTIMATE.startENTRY-->L800: Formula: (let ((.cse0 (store |v_#valid_62| 0 0))) (and (= |v_ULTIMATE.start_main_~#t1504~0.offset_19| 0) (= 0 v_~y$read_delayed_var~0.base_6) (= (store |v_#length_24| |v_ULTIMATE.start_main_~#t1504~0.base_26| 4) |v_#length_23|) (= 0 v_~weak$$choice0~0_25) (= 0 v_~y$r_buff0_thd3~0_151) (= v_~y$w_buff1~0_200 0) (= v_~y$w_buff0_used~0_650 0) (= v_~__unbuffered_cnt~0_109 0) (< 0 |v_#StackHeapBarrier_16|) (= 0 v_~y$w_buff0~0_308) (= 0 v_~y$r_buff1_thd3~0_122) (= v_~y$read_delayed~0_6 0) (= 0 v_~y$r_buff1_thd1~0_76) (= v_~z~0_51 0) (= v_~y$r_buff0_thd1~0_29 0) (= v_~main$tmp_guard1~0_28 0) (= v_~y$r_buff0_thd0~0_312 0) (= 0 v_~__unbuffered_p2_EAX~0_90) (= 0 v_~y$flush_delayed~0_45) (= v_~y$w_buff1_used~0_407 0) (< |v_#StackHeapBarrier_16| |v_ULTIMATE.start_main_~#t1504~0.base_26|) (= v_~y$r_buff0_thd2~0_88 0) (= |v_#NULL.offset_5| 0) (= 0 v_~y$r_buff1_thd2~0_131) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t1504~0.base_26|)) (= v_~y$mem_tmp~0_31 0) (= 0 v_~y$read_delayed_var~0.offset_6) (= v_~y~0_150 0) (= v_~weak$$choice2~0_131 0) (= v_~y$r_buff1_thd0~0_254 0) (= (store |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1504~0.base_26| (store (select |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1504~0.base_26|) |v_ULTIMATE.start_main_~#t1504~0.offset_19| 0)) |v_#memory_int_23|) (= v_~main$tmp_guard0~0_24 0) (= (store .cse0 |v_ULTIMATE.start_main_~#t1504~0.base_26| 1) |v_#valid_60|) (= 0 |v_#NULL.base_5|) (= v_~x~0_80 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_16|, #valid=|v_#valid_62|, #memory_int=|v_#memory_int_24|, #length=|v_#length_24|} OutVars{ULTIMATE.start_main_~#t1504~0.base=|v_ULTIMATE.start_main_~#t1504~0.base_26|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_28|, ULTIMATE.start_main_~#t1504~0.offset=|v_ULTIMATE.start_main_~#t1504~0.offset_19|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_26|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_104|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_52|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_26|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_38|, ~y$read_delayed~0=v_~y$read_delayed~0_6, ~y$mem_tmp~0=v_~y$mem_tmp~0_31, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_122, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_29, ~y$flush_delayed~0=v_~y$flush_delayed~0_45, #length=|v_#length_23|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_90, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_34|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_142|, ULTIMATE.start_main_~#t1506~0.offset=|v_ULTIMATE.start_main_~#t1506~0.offset_14|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_44|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_31|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_98|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_27|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_26|, ~weak$$choice0~0=v_~weak$$choice0~0_25, #StackHeapBarrier=|v_#StackHeapBarrier_16|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_28|, ~y$w_buff1~0=v_~y$w_buff1~0_200, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_6, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_88, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_8|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_22|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_109, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_254, ~x~0=v_~x~0_80, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_6, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_650, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_38|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_31|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_28, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_28|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_32|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_16|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_58|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_50|, ULTIMATE.start_main_~#t1505~0.offset=|v_ULTIMATE.start_main_~#t1505~0.offset_19|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_76, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_44|, ULTIMATE.start_main_~#t1506~0.base=|v_ULTIMATE.start_main_~#t1506~0.base_21|, ~y$w_buff0~0=v_~y$w_buff0~0_308, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_151, ~y~0=v_~y~0_150, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_30|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_44|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_26|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_96|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_24, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_31|, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_31|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_131, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_28|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_18|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_312, #valid=|v_#valid_60|, #memory_int=|v_#memory_int_23|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_8|, ULTIMATE.start_main_~#t1505~0.base=|v_ULTIMATE.start_main_~#t1505~0.base_26|, ~z~0=v_~z~0_51, ~weak$$choice2~0=v_~weak$$choice2~0_131, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_407} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1504~0.base, ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_~#t1504~0.offset, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~y$read_delayed~0, ~y$mem_tmp~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_~#t1506~0.offset, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_~#t1505~0.offset, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_~#t1506~0.base, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ULTIMATE.start_main_~#t1505~0.base, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:20:24,632 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [715] [715] L800-1-->L802: Formula: (and (not (= 0 |v_ULTIMATE.start_main_~#t1505~0.base_13|)) (= (store |v_#length_18| |v_ULTIMATE.start_main_~#t1505~0.base_13| 4) |v_#length_17|) (= (store |v_#valid_41| |v_ULTIMATE.start_main_~#t1505~0.base_13| 1) |v_#valid_40|) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1505~0.base_13|) (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1505~0.base_13| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1505~0.base_13|) |v_ULTIMATE.start_main_~#t1505~0.offset_11| 1)) |v_#memory_int_17|) (= (select |v_#valid_41| |v_ULTIMATE.start_main_~#t1505~0.base_13|) 0) (= |v_ULTIMATE.start_main_~#t1505~0.offset_11| 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_41|, #memory_int=|v_#memory_int_18|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t1505~0.offset=|v_ULTIMATE.start_main_~#t1505~0.offset_11|, #StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_17|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, ULTIMATE.start_main_~#t1505~0.base=|v_ULTIMATE.start_main_~#t1505~0.base_13|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1505~0.offset, #valid, #memory_int, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_~#t1505~0.base, #length] because there is no mapped edge [2019-11-28 18:20:24,633 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L802-1-->L804: Formula: (and (not (= 0 |v_ULTIMATE.start_main_~#t1506~0.base_12|)) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t1506~0.base_12|) (= (select |v_#valid_39| |v_ULTIMATE.start_main_~#t1506~0.base_12|) 0) (= |v_#valid_38| (store |v_#valid_39| |v_ULTIMATE.start_main_~#t1506~0.base_12| 1)) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1506~0.base_12| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1506~0.base_12|) |v_ULTIMATE.start_main_~#t1506~0.offset_10| 2)) |v_#memory_int_15|) (= 0 |v_ULTIMATE.start_main_~#t1506~0.offset_10|) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t1506~0.base_12| 4))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_39|, #memory_int=|v_#memory_int_16|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_~#t1506~0.base=|v_ULTIMATE.start_main_~#t1506~0.base_12|, ULTIMATE.start_main_~#t1506~0.offset=|v_ULTIMATE.start_main_~#t1506~0.offset_10|, #valid=|v_#valid_38|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, #length=|v_#length_15|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1506~0.base, ULTIMATE.start_main_~#t1506~0.offset, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, #length] because there is no mapped edge [2019-11-28 18:20:24,633 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [641] [641] P2ENTRY-->L4-3: Formula: (and (not (= 0 v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_10)) (= 2 v_~y$w_buff0~0_40) (= v_~y$w_buff0_used~0_161 1) (= v_~y$w_buff0~0_41 v_~y$w_buff1~0_32) (= v_P2Thread1of1ForFork0_~arg.base_6 |v_P2Thread1of1ForFork0_#in~arg.base_8|) (= v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_10 |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|) (= |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6| (ite (not (and (not (= (mod v_~y$w_buff1_used~0_89 256) 0)) (not (= 0 (mod v_~y$w_buff0_used~0_161 256))))) 1 0)) (= v_P2Thread1of1ForFork0_~arg.offset_6 |v_P2Thread1of1ForFork0_#in~arg.offset_8|) (= v_~y$w_buff1_used~0_89 v_~y$w_buff0_used~0_162)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_8|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_162, ~y$w_buff0~0=v_~y$w_buff0~0_41, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_8|} OutVars{P2Thread1of1ForFork0_~arg.base=v_P2Thread1of1ForFork0_~arg.base_6, P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_8|, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_161, ~y$w_buff1~0=v_~y$w_buff1~0_32, ~y$w_buff0~0=v_~y$w_buff0~0_40, P2Thread1of1ForFork0_~arg.offset=v_P2Thread1of1ForFork0_~arg.offset_6, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_8|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_10, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_89} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:20:24,634 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [704] [704] P0ENTRY-->P0EXIT: Formula: (and (= v_~z~0_35 1) (= 0 |v_P0Thread1of1ForFork1_#res.base_9|) (= 0 |v_P0Thread1of1ForFork1_#res.offset_9|) (= |v_P0Thread1of1ForFork1_#in~arg.base_21| v_P0Thread1of1ForFork1_~arg.base_19) (= v_P0Thread1of1ForFork1_~arg.offset_19 |v_P0Thread1of1ForFork1_#in~arg.offset_21|) (= v_~x~0_49 1) (= v_~__unbuffered_cnt~0_67 (+ v_~__unbuffered_cnt~0_68 1))) InVars {P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_21|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_68, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_21|} OutVars{P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_9|, P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_21|, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_9|, P0Thread1of1ForFork1_~arg.offset=v_P0Thread1of1ForFork1_~arg.offset_19, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_67, ~z~0=v_~z~0_35, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_21|, ~x~0=v_~x~0_49, P0Thread1of1ForFork1_~arg.base=v_P0Thread1of1ForFork1_~arg.base_19} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#res.offset, P0Thread1of1ForFork1_#res.base, P0Thread1of1ForFork1_~arg.offset, ~__unbuffered_cnt~0, ~z~0, ~x~0, P0Thread1of1ForFork1_~arg.base] because there is no mapped edge [2019-11-28 18:20:24,635 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [679] [679] L778-->L778-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd3~0_In-1904113297 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1904113297 256)))) (or (and (not .cse0) (= |P2Thread1of1ForFork0_#t~ite11_Out-1904113297| 0) (not .cse1)) (and (= |P2Thread1of1ForFork0_#t~ite11_Out-1904113297| ~y$w_buff0_used~0_In-1904113297) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1904113297, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1904113297} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1904113297, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out-1904113297|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1904113297} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-11-28 18:20:24,636 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [694] [694] L748-2-->L748-4: Formula: (let ((.cse1 (= (mod ~y$w_buff1_used~0_In1050405150 256) 0)) (.cse0 (= 0 (mod ~y$r_buff1_thd2~0_In1050405150 256)))) (or (and (= ~y~0_In1050405150 |P1Thread1of1ForFork2_#t~ite3_Out1050405150|) (or .cse0 .cse1)) (and (not .cse1) (= ~y$w_buff1~0_In1050405150 |P1Thread1of1ForFork2_#t~ite3_Out1050405150|) (not .cse0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1050405150, ~y$w_buff1~0=~y$w_buff1~0_In1050405150, ~y~0=~y~0_In1050405150, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1050405150} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1050405150, ~y$w_buff1~0=~y$w_buff1~0_In1050405150, ~y~0=~y~0_In1050405150, P1Thread1of1ForFork2_#t~ite3=|P1Thread1of1ForFork2_#t~ite3_Out1050405150|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1050405150} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-11-28 18:20:24,636 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [618] [618] L748-4-->L749: Formula: (= |v_P1Thread1of1ForFork2_#t~ite3_10| v_~y~0_21) InVars {P1Thread1of1ForFork2_#t~ite3=|v_P1Thread1of1ForFork2_#t~ite3_10|} OutVars{P1Thread1of1ForFork2_#t~ite4=|v_P1Thread1of1ForFork2_#t~ite4_11|, ~y~0=v_~y~0_21, P1Thread1of1ForFork2_#t~ite3=|v_P1Thread1of1ForFork2_#t~ite3_9|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite4, ~y~0, P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-11-28 18:20:24,636 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [677] [677] L749-->L749-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In2024711614 256) 0)) (.cse0 (= (mod ~y$r_buff0_thd2~0_In2024711614 256) 0))) (or (and (not .cse0) (not .cse1) (= |P1Thread1of1ForFork2_#t~ite5_Out2024711614| 0)) (and (= ~y$w_buff0_used~0_In2024711614 |P1Thread1of1ForFork2_#t~ite5_Out2024711614|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In2024711614, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2024711614} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In2024711614, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2024711614, P1Thread1of1ForFork2_#t~ite5=|P1Thread1of1ForFork2_#t~ite5_Out2024711614|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-11-28 18:20:24,637 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [689] [689] L750-->L750-2: Formula: (let ((.cse2 (= (mod ~y$r_buff1_thd2~0_In1731600886 256) 0)) (.cse3 (= (mod ~y$w_buff1_used~0_In1731600886 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In1731600886 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In1731600886 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork2_#t~ite6_Out1731600886| 0)) (and (or .cse2 .cse3) (or .cse0 .cse1) (= ~y$w_buff1_used~0_In1731600886 |P1Thread1of1ForFork2_#t~ite6_Out1731600886|)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1731600886, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1731600886, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1731600886, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1731600886} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1731600886, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1731600886, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1731600886, P1Thread1of1ForFork2_#t~ite6=|P1Thread1of1ForFork2_#t~ite6_Out1731600886|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1731600886} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-11-28 18:20:24,637 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [688] [688] L751-->L751-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In-107325694 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In-107325694 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork2_#t~ite7_Out-107325694|)) (and (= ~y$r_buff0_thd2~0_In-107325694 |P1Thread1of1ForFork2_#t~ite7_Out-107325694|) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-107325694, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-107325694} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-107325694, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-107325694, P1Thread1of1ForFork2_#t~ite7=|P1Thread1of1ForFork2_#t~ite7_Out-107325694|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-11-28 18:20:24,638 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [690] [690] L779-->L779-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In218932195 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In218932195 256))) (.cse2 (= (mod ~y$r_buff1_thd3~0_In218932195 256) 0)) (.cse3 (= (mod ~y$w_buff1_used~0_In218932195 256) 0))) (or (and (= |P2Thread1of1ForFork0_#t~ite12_Out218932195| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (= |P2Thread1of1ForFork0_#t~ite12_Out218932195| ~y$w_buff1_used~0_In218932195) (or .cse2 .cse3)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In218932195, ~y$w_buff0_used~0=~y$w_buff0_used~0_In218932195, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In218932195, ~y$w_buff1_used~0=~y$w_buff1_used~0_In218932195} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In218932195, ~y$w_buff0_used~0=~y$w_buff0_used~0_In218932195, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out218932195|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In218932195, ~y$w_buff1_used~0=~y$w_buff1_used~0_In218932195} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-11-28 18:20:24,638 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [686] [686] L752-->L752-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff1_used~0_In834809249 256))) (.cse1 (= 0 (mod ~y$r_buff1_thd2~0_In834809249 256))) (.cse2 (= (mod ~y$r_buff0_thd2~0_In834809249 256) 0)) (.cse3 (= 0 (mod ~y$w_buff0_used~0_In834809249 256)))) (or (and (= ~y$r_buff1_thd2~0_In834809249 |P1Thread1of1ForFork2_#t~ite8_Out834809249|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P1Thread1of1ForFork2_#t~ite8_Out834809249|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In834809249, ~y$w_buff0_used~0=~y$w_buff0_used~0_In834809249, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In834809249, ~y$w_buff1_used~0=~y$w_buff1_used~0_In834809249} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In834809249, ~y$w_buff0_used~0=~y$w_buff0_used~0_In834809249, P1Thread1of1ForFork2_#t~ite8=|P1Thread1of1ForFork2_#t~ite8_Out834809249|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In834809249, ~y$w_buff1_used~0=~y$w_buff1_used~0_In834809249} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-11-28 18:20:24,639 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L752-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= |v_P1Thread1of1ForFork2_#t~ite8_26| v_~y$r_buff1_thd2~0_56) (= (+ v_~__unbuffered_cnt~0_75 1) v_~__unbuffered_cnt~0_74)) InVars {P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_26|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_75} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_56, P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_25|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_74, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork2_#res.offset, P1Thread1of1ForFork2_#t~ite8, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-11-28 18:20:24,639 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L780-->L781: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-1358093944 256) 0)) (.cse2 (= ~y$r_buff0_thd3~0_In-1358093944 ~y$r_buff0_thd3~0_Out-1358093944)) (.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In-1358093944 256)))) (or (and (not .cse0) (= 0 ~y$r_buff0_thd3~0_Out-1358093944) (not .cse1)) (and .cse1 .cse2) (and .cse2 .cse0))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1358093944, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1358093944} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1358093944, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out-1358093944, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out-1358093944|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-11-28 18:20:24,639 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [681] [681] L781-->L781-2: Formula: (let ((.cse0 (= (mod ~y$w_buff1_used~0_In1524866939 256) 0)) (.cse1 (= (mod ~y$r_buff1_thd3~0_In1524866939 256) 0)) (.cse3 (= (mod ~y$r_buff0_thd3~0_In1524866939 256) 0)) (.cse2 (= (mod ~y$w_buff0_used~0_In1524866939 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P2Thread1of1ForFork0_#t~ite14_Out1524866939| ~y$r_buff1_thd3~0_In1524866939)) (and (= |P2Thread1of1ForFork0_#t~ite14_Out1524866939| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1524866939, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1524866939, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1524866939, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1524866939} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out1524866939|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1524866939, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1524866939, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1524866939, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1524866939} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-11-28 18:20:24,640 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [722] [722] L781-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#t~ite14_38| v_~y$r_buff1_thd3~0_68) (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0) (= v_~__unbuffered_cnt~0_90 (+ v_~__unbuffered_cnt~0_91 1))) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_38|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_91} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_37|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_68, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_90, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-11-28 18:20:24,640 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [617] [617] L804-1-->L810: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_6 256))) (= v_~main$tmp_guard0~0_6 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_13) 1 0)) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_5|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet17, ~main$tmp_guard0~0] because there is no mapped edge [2019-11-28 18:20:24,640 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L810-2-->L810-4: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In858870946 256))) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In858870946 256)))) (or (and (not .cse0) (not .cse1) (= ~y$w_buff1~0_In858870946 |ULTIMATE.start_main_#t~ite18_Out858870946|)) (and (or .cse0 .cse1) (= ~y~0_In858870946 |ULTIMATE.start_main_#t~ite18_Out858870946|)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In858870946, ~y~0=~y~0_In858870946, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In858870946, ~y$w_buff1_used~0=~y$w_buff1_used~0_In858870946} OutVars{~y$w_buff1~0=~y$w_buff1~0_In858870946, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out858870946|, ~y~0=~y~0_In858870946, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In858870946, ~y$w_buff1_used~0=~y$w_buff1_used~0_In858870946} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18] because there is no mapped edge [2019-11-28 18:20:24,641 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [636] [636] L810-4-->L811: Formula: (= v_~y~0_40 |v_ULTIMATE.start_main_#t~ite18_13|) InVars {ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_13|} OutVars{ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_12|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_12|, ~y~0=v_~y~0_40} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite19, ~y~0] because there is no mapped edge [2019-11-28 18:20:24,641 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [692] [692] L811-->L811-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In1594724547 256))) (.cse1 (= (mod ~y$r_buff0_thd0~0_In1594724547 256) 0))) (or (and (= ~y$w_buff0_used~0_In1594724547 |ULTIMATE.start_main_#t~ite20_Out1594724547|) (or .cse0 .cse1)) (and (= 0 |ULTIMATE.start_main_#t~ite20_Out1594724547|) (not .cse0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1594724547, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1594724547} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1594724547, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1594724547, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out1594724547|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-11-28 18:20:24,641 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [678] [678] L812-->L812-2: Formula: (let ((.cse2 (= (mod ~y$r_buff1_thd0~0_In-364540095 256) 0)) (.cse3 (= (mod ~y$w_buff1_used~0_In-364540095 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In-364540095 256))) (.cse0 (= (mod ~y$w_buff0_used~0_In-364540095 256) 0))) (or (and (= 0 |ULTIMATE.start_main_#t~ite21_Out-364540095|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse2 .cse3) (= ~y$w_buff1_used~0_In-364540095 |ULTIMATE.start_main_#t~ite21_Out-364540095|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-364540095, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-364540095, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-364540095, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-364540095} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-364540095, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-364540095, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out-364540095|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-364540095, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-364540095} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-11-28 18:20:24,642 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [682] [682] L813-->L813-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In1312338085 256))) (.cse1 (= (mod ~y$r_buff0_thd0~0_In1312338085 256) 0))) (or (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite22_Out1312338085|) (not .cse1)) (and (= |ULTIMATE.start_main_#t~ite22_Out1312338085| ~y$r_buff0_thd0~0_In1312338085) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1312338085, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1312338085} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1312338085, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1312338085, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out1312338085|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-11-28 18:20:24,643 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [684] [684] L814-->L814-2: Formula: (let ((.cse1 (= (mod ~y$r_buff1_thd0~0_In-1902227196 256) 0)) (.cse0 (= (mod ~y$w_buff1_used~0_In-1902227196 256) 0)) (.cse3 (= 0 (mod ~y$w_buff0_used~0_In-1902227196 256))) (.cse2 (= (mod ~y$r_buff0_thd0~0_In-1902227196 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~y$r_buff1_thd0~0_In-1902227196 |ULTIMATE.start_main_#t~ite23_Out-1902227196|)) (and (= 0 |ULTIMATE.start_main_#t~ite23_Out-1902227196|) (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1902227196, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1902227196, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1902227196, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1902227196} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1902227196, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1902227196, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1902227196, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out-1902227196|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1902227196} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-11-28 18:20:24,644 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L822-->L822-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In893464797 256)))) (or (and (= ~y$w_buff0~0_In893464797 |ULTIMATE.start_main_#t~ite29_Out893464797|) (= |ULTIMATE.start_main_#t~ite30_Out893464797| |ULTIMATE.start_main_#t~ite29_Out893464797|) .cse0 (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In893464797 256) 0))) (or (and .cse1 (= 0 (mod ~y$r_buff1_thd0~0_In893464797 256))) (= (mod ~y$w_buff0_used~0_In893464797 256) 0) (and (= (mod ~y$w_buff1_used~0_In893464797 256) 0) .cse1)))) (and (= |ULTIMATE.start_main_#t~ite29_In893464797| |ULTIMATE.start_main_#t~ite29_Out893464797|) (= |ULTIMATE.start_main_#t~ite30_Out893464797| ~y$w_buff0~0_In893464797) (not .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In893464797, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_In893464797|, ~y$w_buff0~0=~y$w_buff0~0_In893464797, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In893464797, ~weak$$choice2~0=~weak$$choice2~0_In893464797, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In893464797, ~y$w_buff1_used~0=~y$w_buff1_used~0_In893464797} OutVars{ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out893464797|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In893464797, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out893464797|, ~y$w_buff0~0=~y$w_buff0~0_In893464797, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In893464797, ~weak$$choice2~0=~weak$$choice2~0_In893464797, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In893464797, ~y$w_buff1_used~0=~y$w_buff1_used~0_In893464797} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-11-28 18:20:24,646 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [631] [631] L826-->L827: Formula: (and (not (= (mod v_~weak$$choice2~0_27 256) 0)) (= v_~y$r_buff0_thd0~0_86 v_~y$r_buff0_thd0~0_85)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_86, ~weak$$choice2~0=v_~weak$$choice2~0_27} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_6|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_10|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_85, ~weak$$choice2~0=v_~weak$$choice2~0_27, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-11-28 18:20:24,647 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [709] [709] L829-->L832-1: Formula: (and (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5| (mod v_~main$tmp_guard1~0_12 256)) (= v_~y~0_109 v_~y$mem_tmp~0_21) (not (= 0 (mod v_~y$flush_delayed~0_33 256))) (= 0 v_~y$flush_delayed~0_32)) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_21, ~y$flush_delayed~0=v_~y$flush_delayed~0_33, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_21, ~y$flush_delayed~0=v_~y$flush_delayed~0_32, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_24|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12, ~y~0=v_~y~0_109, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[~y$flush_delayed~0, ULTIMATE.start_main_#t~ite46, ~y~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-11-28 18:20:24,647 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] L832-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-11-28 18:20:24,753 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 06:20:24 BasicIcfg [2019-11-28 18:20:24,754 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-28 18:20:24,754 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-28 18:20:24,754 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-28 18:20:24,755 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-28 18:20:24,755 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:20:04" (3/4) ... [2019-11-28 18:20:24,759 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-28 18:20:24,760 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [740] [740] ULTIMATE.startENTRY-->L800: Formula: (let ((.cse0 (store |v_#valid_62| 0 0))) (and (= |v_ULTIMATE.start_main_~#t1504~0.offset_19| 0) (= 0 v_~y$read_delayed_var~0.base_6) (= (store |v_#length_24| |v_ULTIMATE.start_main_~#t1504~0.base_26| 4) |v_#length_23|) (= 0 v_~weak$$choice0~0_25) (= 0 v_~y$r_buff0_thd3~0_151) (= v_~y$w_buff1~0_200 0) (= v_~y$w_buff0_used~0_650 0) (= v_~__unbuffered_cnt~0_109 0) (< 0 |v_#StackHeapBarrier_16|) (= 0 v_~y$w_buff0~0_308) (= 0 v_~y$r_buff1_thd3~0_122) (= v_~y$read_delayed~0_6 0) (= 0 v_~y$r_buff1_thd1~0_76) (= v_~z~0_51 0) (= v_~y$r_buff0_thd1~0_29 0) (= v_~main$tmp_guard1~0_28 0) (= v_~y$r_buff0_thd0~0_312 0) (= 0 v_~__unbuffered_p2_EAX~0_90) (= 0 v_~y$flush_delayed~0_45) (= v_~y$w_buff1_used~0_407 0) (< |v_#StackHeapBarrier_16| |v_ULTIMATE.start_main_~#t1504~0.base_26|) (= v_~y$r_buff0_thd2~0_88 0) (= |v_#NULL.offset_5| 0) (= 0 v_~y$r_buff1_thd2~0_131) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t1504~0.base_26|)) (= v_~y$mem_tmp~0_31 0) (= 0 v_~y$read_delayed_var~0.offset_6) (= v_~y~0_150 0) (= v_~weak$$choice2~0_131 0) (= v_~y$r_buff1_thd0~0_254 0) (= (store |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1504~0.base_26| (store (select |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1504~0.base_26|) |v_ULTIMATE.start_main_~#t1504~0.offset_19| 0)) |v_#memory_int_23|) (= v_~main$tmp_guard0~0_24 0) (= (store .cse0 |v_ULTIMATE.start_main_~#t1504~0.base_26| 1) |v_#valid_60|) (= 0 |v_#NULL.base_5|) (= v_~x~0_80 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_16|, #valid=|v_#valid_62|, #memory_int=|v_#memory_int_24|, #length=|v_#length_24|} OutVars{ULTIMATE.start_main_~#t1504~0.base=|v_ULTIMATE.start_main_~#t1504~0.base_26|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_28|, ULTIMATE.start_main_~#t1504~0.offset=|v_ULTIMATE.start_main_~#t1504~0.offset_19|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_26|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_104|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_52|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_26|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_38|, ~y$read_delayed~0=v_~y$read_delayed~0_6, ~y$mem_tmp~0=v_~y$mem_tmp~0_31, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_122, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_29, ~y$flush_delayed~0=v_~y$flush_delayed~0_45, #length=|v_#length_23|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_90, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_34|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_142|, ULTIMATE.start_main_~#t1506~0.offset=|v_ULTIMATE.start_main_~#t1506~0.offset_14|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_44|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_31|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_98|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_27|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_26|, ~weak$$choice0~0=v_~weak$$choice0~0_25, #StackHeapBarrier=|v_#StackHeapBarrier_16|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_28|, ~y$w_buff1~0=v_~y$w_buff1~0_200, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_6, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_88, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_8|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_22|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_109, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_254, ~x~0=v_~x~0_80, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_6, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_650, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_38|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_31|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_28, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_28|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_32|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_16|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_58|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_50|, ULTIMATE.start_main_~#t1505~0.offset=|v_ULTIMATE.start_main_~#t1505~0.offset_19|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_76, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_44|, ULTIMATE.start_main_~#t1506~0.base=|v_ULTIMATE.start_main_~#t1506~0.base_21|, ~y$w_buff0~0=v_~y$w_buff0~0_308, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_151, ~y~0=v_~y~0_150, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_30|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_44|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_26|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_96|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_24, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_31|, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_31|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_131, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_28|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_18|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_312, #valid=|v_#valid_60|, #memory_int=|v_#memory_int_23|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_8|, ULTIMATE.start_main_~#t1505~0.base=|v_ULTIMATE.start_main_~#t1505~0.base_26|, ~z~0=v_~z~0_51, ~weak$$choice2~0=v_~weak$$choice2~0_131, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_407} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1504~0.base, ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_~#t1504~0.offset, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~y$read_delayed~0, ~y$mem_tmp~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_~#t1506~0.offset, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_~#t1505~0.offset, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_~#t1506~0.base, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ULTIMATE.start_main_~#t1505~0.base, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:20:24,760 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [715] [715] L800-1-->L802: Formula: (and (not (= 0 |v_ULTIMATE.start_main_~#t1505~0.base_13|)) (= (store |v_#length_18| |v_ULTIMATE.start_main_~#t1505~0.base_13| 4) |v_#length_17|) (= (store |v_#valid_41| |v_ULTIMATE.start_main_~#t1505~0.base_13| 1) |v_#valid_40|) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1505~0.base_13|) (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1505~0.base_13| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1505~0.base_13|) |v_ULTIMATE.start_main_~#t1505~0.offset_11| 1)) |v_#memory_int_17|) (= (select |v_#valid_41| |v_ULTIMATE.start_main_~#t1505~0.base_13|) 0) (= |v_ULTIMATE.start_main_~#t1505~0.offset_11| 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_41|, #memory_int=|v_#memory_int_18|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t1505~0.offset=|v_ULTIMATE.start_main_~#t1505~0.offset_11|, #StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_17|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, ULTIMATE.start_main_~#t1505~0.base=|v_ULTIMATE.start_main_~#t1505~0.base_13|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1505~0.offset, #valid, #memory_int, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_~#t1505~0.base, #length] because there is no mapped edge [2019-11-28 18:20:24,761 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L802-1-->L804: Formula: (and (not (= 0 |v_ULTIMATE.start_main_~#t1506~0.base_12|)) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t1506~0.base_12|) (= (select |v_#valid_39| |v_ULTIMATE.start_main_~#t1506~0.base_12|) 0) (= |v_#valid_38| (store |v_#valid_39| |v_ULTIMATE.start_main_~#t1506~0.base_12| 1)) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1506~0.base_12| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1506~0.base_12|) |v_ULTIMATE.start_main_~#t1506~0.offset_10| 2)) |v_#memory_int_15|) (= 0 |v_ULTIMATE.start_main_~#t1506~0.offset_10|) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t1506~0.base_12| 4))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_39|, #memory_int=|v_#memory_int_16|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_~#t1506~0.base=|v_ULTIMATE.start_main_~#t1506~0.base_12|, ULTIMATE.start_main_~#t1506~0.offset=|v_ULTIMATE.start_main_~#t1506~0.offset_10|, #valid=|v_#valid_38|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, #length=|v_#length_15|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1506~0.base, ULTIMATE.start_main_~#t1506~0.offset, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, #length] because there is no mapped edge [2019-11-28 18:20:24,761 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [641] [641] P2ENTRY-->L4-3: Formula: (and (not (= 0 v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_10)) (= 2 v_~y$w_buff0~0_40) (= v_~y$w_buff0_used~0_161 1) (= v_~y$w_buff0~0_41 v_~y$w_buff1~0_32) (= v_P2Thread1of1ForFork0_~arg.base_6 |v_P2Thread1of1ForFork0_#in~arg.base_8|) (= v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_10 |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|) (= |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6| (ite (not (and (not (= (mod v_~y$w_buff1_used~0_89 256) 0)) (not (= 0 (mod v_~y$w_buff0_used~0_161 256))))) 1 0)) (= v_P2Thread1of1ForFork0_~arg.offset_6 |v_P2Thread1of1ForFork0_#in~arg.offset_8|) (= v_~y$w_buff1_used~0_89 v_~y$w_buff0_used~0_162)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_8|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_162, ~y$w_buff0~0=v_~y$w_buff0~0_41, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_8|} OutVars{P2Thread1of1ForFork0_~arg.base=v_P2Thread1of1ForFork0_~arg.base_6, P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_8|, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_161, ~y$w_buff1~0=v_~y$w_buff1~0_32, ~y$w_buff0~0=v_~y$w_buff0~0_40, P2Thread1of1ForFork0_~arg.offset=v_P2Thread1of1ForFork0_~arg.offset_6, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_8|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_10, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_89} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:20:24,762 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [704] [704] P0ENTRY-->P0EXIT: Formula: (and (= v_~z~0_35 1) (= 0 |v_P0Thread1of1ForFork1_#res.base_9|) (= 0 |v_P0Thread1of1ForFork1_#res.offset_9|) (= |v_P0Thread1of1ForFork1_#in~arg.base_21| v_P0Thread1of1ForFork1_~arg.base_19) (= v_P0Thread1of1ForFork1_~arg.offset_19 |v_P0Thread1of1ForFork1_#in~arg.offset_21|) (= v_~x~0_49 1) (= v_~__unbuffered_cnt~0_67 (+ v_~__unbuffered_cnt~0_68 1))) InVars {P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_21|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_68, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_21|} OutVars{P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_9|, P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_21|, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_9|, P0Thread1of1ForFork1_~arg.offset=v_P0Thread1of1ForFork1_~arg.offset_19, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_67, ~z~0=v_~z~0_35, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_21|, ~x~0=v_~x~0_49, P0Thread1of1ForFork1_~arg.base=v_P0Thread1of1ForFork1_~arg.base_19} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#res.offset, P0Thread1of1ForFork1_#res.base, P0Thread1of1ForFork1_~arg.offset, ~__unbuffered_cnt~0, ~z~0, ~x~0, P0Thread1of1ForFork1_~arg.base] because there is no mapped edge [2019-11-28 18:20:24,763 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [679] [679] L778-->L778-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd3~0_In-1904113297 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1904113297 256)))) (or (and (not .cse0) (= |P2Thread1of1ForFork0_#t~ite11_Out-1904113297| 0) (not .cse1)) (and (= |P2Thread1of1ForFork0_#t~ite11_Out-1904113297| ~y$w_buff0_used~0_In-1904113297) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1904113297, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1904113297} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1904113297, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out-1904113297|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1904113297} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-11-28 18:20:24,764 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [694] [694] L748-2-->L748-4: Formula: (let ((.cse1 (= (mod ~y$w_buff1_used~0_In1050405150 256) 0)) (.cse0 (= 0 (mod ~y$r_buff1_thd2~0_In1050405150 256)))) (or (and (= ~y~0_In1050405150 |P1Thread1of1ForFork2_#t~ite3_Out1050405150|) (or .cse0 .cse1)) (and (not .cse1) (= ~y$w_buff1~0_In1050405150 |P1Thread1of1ForFork2_#t~ite3_Out1050405150|) (not .cse0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1050405150, ~y$w_buff1~0=~y$w_buff1~0_In1050405150, ~y~0=~y~0_In1050405150, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1050405150} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1050405150, ~y$w_buff1~0=~y$w_buff1~0_In1050405150, ~y~0=~y~0_In1050405150, P1Thread1of1ForFork2_#t~ite3=|P1Thread1of1ForFork2_#t~ite3_Out1050405150|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1050405150} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-11-28 18:20:24,764 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [618] [618] L748-4-->L749: Formula: (= |v_P1Thread1of1ForFork2_#t~ite3_10| v_~y~0_21) InVars {P1Thread1of1ForFork2_#t~ite3=|v_P1Thread1of1ForFork2_#t~ite3_10|} OutVars{P1Thread1of1ForFork2_#t~ite4=|v_P1Thread1of1ForFork2_#t~ite4_11|, ~y~0=v_~y~0_21, P1Thread1of1ForFork2_#t~ite3=|v_P1Thread1of1ForFork2_#t~ite3_9|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite4, ~y~0, P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-11-28 18:20:24,765 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [677] [677] L749-->L749-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In2024711614 256) 0)) (.cse0 (= (mod ~y$r_buff0_thd2~0_In2024711614 256) 0))) (or (and (not .cse0) (not .cse1) (= |P1Thread1of1ForFork2_#t~ite5_Out2024711614| 0)) (and (= ~y$w_buff0_used~0_In2024711614 |P1Thread1of1ForFork2_#t~ite5_Out2024711614|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In2024711614, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2024711614} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In2024711614, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2024711614, P1Thread1of1ForFork2_#t~ite5=|P1Thread1of1ForFork2_#t~ite5_Out2024711614|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-11-28 18:20:24,765 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [689] [689] L750-->L750-2: Formula: (let ((.cse2 (= (mod ~y$r_buff1_thd2~0_In1731600886 256) 0)) (.cse3 (= (mod ~y$w_buff1_used~0_In1731600886 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In1731600886 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In1731600886 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork2_#t~ite6_Out1731600886| 0)) (and (or .cse2 .cse3) (or .cse0 .cse1) (= ~y$w_buff1_used~0_In1731600886 |P1Thread1of1ForFork2_#t~ite6_Out1731600886|)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1731600886, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1731600886, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1731600886, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1731600886} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1731600886, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1731600886, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1731600886, P1Thread1of1ForFork2_#t~ite6=|P1Thread1of1ForFork2_#t~ite6_Out1731600886|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1731600886} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-11-28 18:20:24,766 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [688] [688] L751-->L751-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In-107325694 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In-107325694 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork2_#t~ite7_Out-107325694|)) (and (= ~y$r_buff0_thd2~0_In-107325694 |P1Thread1of1ForFork2_#t~ite7_Out-107325694|) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-107325694, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-107325694} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-107325694, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-107325694, P1Thread1of1ForFork2_#t~ite7=|P1Thread1of1ForFork2_#t~ite7_Out-107325694|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-11-28 18:20:24,766 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [690] [690] L779-->L779-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In218932195 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In218932195 256))) (.cse2 (= (mod ~y$r_buff1_thd3~0_In218932195 256) 0)) (.cse3 (= (mod ~y$w_buff1_used~0_In218932195 256) 0))) (or (and (= |P2Thread1of1ForFork0_#t~ite12_Out218932195| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (= |P2Thread1of1ForFork0_#t~ite12_Out218932195| ~y$w_buff1_used~0_In218932195) (or .cse2 .cse3)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In218932195, ~y$w_buff0_used~0=~y$w_buff0_used~0_In218932195, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In218932195, ~y$w_buff1_used~0=~y$w_buff1_used~0_In218932195} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In218932195, ~y$w_buff0_used~0=~y$w_buff0_used~0_In218932195, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out218932195|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In218932195, ~y$w_buff1_used~0=~y$w_buff1_used~0_In218932195} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-11-28 18:20:24,767 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [686] [686] L752-->L752-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff1_used~0_In834809249 256))) (.cse1 (= 0 (mod ~y$r_buff1_thd2~0_In834809249 256))) (.cse2 (= (mod ~y$r_buff0_thd2~0_In834809249 256) 0)) (.cse3 (= 0 (mod ~y$w_buff0_used~0_In834809249 256)))) (or (and (= ~y$r_buff1_thd2~0_In834809249 |P1Thread1of1ForFork2_#t~ite8_Out834809249|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P1Thread1of1ForFork2_#t~ite8_Out834809249|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In834809249, ~y$w_buff0_used~0=~y$w_buff0_used~0_In834809249, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In834809249, ~y$w_buff1_used~0=~y$w_buff1_used~0_In834809249} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In834809249, ~y$w_buff0_used~0=~y$w_buff0_used~0_In834809249, P1Thread1of1ForFork2_#t~ite8=|P1Thread1of1ForFork2_#t~ite8_Out834809249|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In834809249, ~y$w_buff1_used~0=~y$w_buff1_used~0_In834809249} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-11-28 18:20:24,767 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L752-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= |v_P1Thread1of1ForFork2_#t~ite8_26| v_~y$r_buff1_thd2~0_56) (= (+ v_~__unbuffered_cnt~0_75 1) v_~__unbuffered_cnt~0_74)) InVars {P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_26|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_75} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_56, P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_25|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_74, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork2_#res.offset, P1Thread1of1ForFork2_#t~ite8, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-11-28 18:20:24,767 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L780-->L781: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-1358093944 256) 0)) (.cse2 (= ~y$r_buff0_thd3~0_In-1358093944 ~y$r_buff0_thd3~0_Out-1358093944)) (.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In-1358093944 256)))) (or (and (not .cse0) (= 0 ~y$r_buff0_thd3~0_Out-1358093944) (not .cse1)) (and .cse1 .cse2) (and .cse2 .cse0))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1358093944, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1358093944} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1358093944, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out-1358093944, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out-1358093944|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-11-28 18:20:24,768 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [681] [681] L781-->L781-2: Formula: (let ((.cse0 (= (mod ~y$w_buff1_used~0_In1524866939 256) 0)) (.cse1 (= (mod ~y$r_buff1_thd3~0_In1524866939 256) 0)) (.cse3 (= (mod ~y$r_buff0_thd3~0_In1524866939 256) 0)) (.cse2 (= (mod ~y$w_buff0_used~0_In1524866939 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P2Thread1of1ForFork0_#t~ite14_Out1524866939| ~y$r_buff1_thd3~0_In1524866939)) (and (= |P2Thread1of1ForFork0_#t~ite14_Out1524866939| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1524866939, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1524866939, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1524866939, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1524866939} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out1524866939|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1524866939, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1524866939, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1524866939, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1524866939} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-11-28 18:20:24,768 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [722] [722] L781-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#t~ite14_38| v_~y$r_buff1_thd3~0_68) (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0) (= v_~__unbuffered_cnt~0_90 (+ v_~__unbuffered_cnt~0_91 1))) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_38|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_91} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_37|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_68, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_90, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-11-28 18:20:24,768 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [617] [617] L804-1-->L810: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_6 256))) (= v_~main$tmp_guard0~0_6 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_13) 1 0)) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_5|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet17, ~main$tmp_guard0~0] because there is no mapped edge [2019-11-28 18:20:24,769 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L810-2-->L810-4: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In858870946 256))) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In858870946 256)))) (or (and (not .cse0) (not .cse1) (= ~y$w_buff1~0_In858870946 |ULTIMATE.start_main_#t~ite18_Out858870946|)) (and (or .cse0 .cse1) (= ~y~0_In858870946 |ULTIMATE.start_main_#t~ite18_Out858870946|)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In858870946, ~y~0=~y~0_In858870946, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In858870946, ~y$w_buff1_used~0=~y$w_buff1_used~0_In858870946} OutVars{~y$w_buff1~0=~y$w_buff1~0_In858870946, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out858870946|, ~y~0=~y~0_In858870946, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In858870946, ~y$w_buff1_used~0=~y$w_buff1_used~0_In858870946} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18] because there is no mapped edge [2019-11-28 18:20:24,769 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [636] [636] L810-4-->L811: Formula: (= v_~y~0_40 |v_ULTIMATE.start_main_#t~ite18_13|) InVars {ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_13|} OutVars{ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_12|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_12|, ~y~0=v_~y~0_40} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite19, ~y~0] because there is no mapped edge [2019-11-28 18:20:24,769 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [692] [692] L811-->L811-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In1594724547 256))) (.cse1 (= (mod ~y$r_buff0_thd0~0_In1594724547 256) 0))) (or (and (= ~y$w_buff0_used~0_In1594724547 |ULTIMATE.start_main_#t~ite20_Out1594724547|) (or .cse0 .cse1)) (and (= 0 |ULTIMATE.start_main_#t~ite20_Out1594724547|) (not .cse0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1594724547, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1594724547} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1594724547, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1594724547, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out1594724547|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-11-28 18:20:24,770 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [678] [678] L812-->L812-2: Formula: (let ((.cse2 (= (mod ~y$r_buff1_thd0~0_In-364540095 256) 0)) (.cse3 (= (mod ~y$w_buff1_used~0_In-364540095 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In-364540095 256))) (.cse0 (= (mod ~y$w_buff0_used~0_In-364540095 256) 0))) (or (and (= 0 |ULTIMATE.start_main_#t~ite21_Out-364540095|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse2 .cse3) (= ~y$w_buff1_used~0_In-364540095 |ULTIMATE.start_main_#t~ite21_Out-364540095|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-364540095, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-364540095, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-364540095, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-364540095} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-364540095, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-364540095, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out-364540095|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-364540095, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-364540095} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-11-28 18:20:24,770 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [682] [682] L813-->L813-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In1312338085 256))) (.cse1 (= (mod ~y$r_buff0_thd0~0_In1312338085 256) 0))) (or (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite22_Out1312338085|) (not .cse1)) (and (= |ULTIMATE.start_main_#t~ite22_Out1312338085| ~y$r_buff0_thd0~0_In1312338085) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1312338085, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1312338085} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1312338085, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1312338085, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out1312338085|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-11-28 18:20:24,771 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [684] [684] L814-->L814-2: Formula: (let ((.cse1 (= (mod ~y$r_buff1_thd0~0_In-1902227196 256) 0)) (.cse0 (= (mod ~y$w_buff1_used~0_In-1902227196 256) 0)) (.cse3 (= 0 (mod ~y$w_buff0_used~0_In-1902227196 256))) (.cse2 (= (mod ~y$r_buff0_thd0~0_In-1902227196 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~y$r_buff1_thd0~0_In-1902227196 |ULTIMATE.start_main_#t~ite23_Out-1902227196|)) (and (= 0 |ULTIMATE.start_main_#t~ite23_Out-1902227196|) (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1902227196, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1902227196, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1902227196, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1902227196} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1902227196, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1902227196, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1902227196, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out-1902227196|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1902227196} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-11-28 18:20:24,772 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L822-->L822-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In893464797 256)))) (or (and (= ~y$w_buff0~0_In893464797 |ULTIMATE.start_main_#t~ite29_Out893464797|) (= |ULTIMATE.start_main_#t~ite30_Out893464797| |ULTIMATE.start_main_#t~ite29_Out893464797|) .cse0 (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In893464797 256) 0))) (or (and .cse1 (= 0 (mod ~y$r_buff1_thd0~0_In893464797 256))) (= (mod ~y$w_buff0_used~0_In893464797 256) 0) (and (= (mod ~y$w_buff1_used~0_In893464797 256) 0) .cse1)))) (and (= |ULTIMATE.start_main_#t~ite29_In893464797| |ULTIMATE.start_main_#t~ite29_Out893464797|) (= |ULTIMATE.start_main_#t~ite30_Out893464797| ~y$w_buff0~0_In893464797) (not .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In893464797, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_In893464797|, ~y$w_buff0~0=~y$w_buff0~0_In893464797, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In893464797, ~weak$$choice2~0=~weak$$choice2~0_In893464797, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In893464797, ~y$w_buff1_used~0=~y$w_buff1_used~0_In893464797} OutVars{ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out893464797|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In893464797, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out893464797|, ~y$w_buff0~0=~y$w_buff0~0_In893464797, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In893464797, ~weak$$choice2~0=~weak$$choice2~0_In893464797, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In893464797, ~y$w_buff1_used~0=~y$w_buff1_used~0_In893464797} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-11-28 18:20:24,774 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [631] [631] L826-->L827: Formula: (and (not (= (mod v_~weak$$choice2~0_27 256) 0)) (= v_~y$r_buff0_thd0~0_86 v_~y$r_buff0_thd0~0_85)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_86, ~weak$$choice2~0=v_~weak$$choice2~0_27} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_6|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_10|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_85, ~weak$$choice2~0=v_~weak$$choice2~0_27, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-11-28 18:20:24,775 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [709] [709] L829-->L832-1: Formula: (and (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5| (mod v_~main$tmp_guard1~0_12 256)) (= v_~y~0_109 v_~y$mem_tmp~0_21) (not (= 0 (mod v_~y$flush_delayed~0_33 256))) (= 0 v_~y$flush_delayed~0_32)) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_21, ~y$flush_delayed~0=v_~y$flush_delayed~0_33, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_21, ~y$flush_delayed~0=v_~y$flush_delayed~0_32, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_24|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12, ~y~0=v_~y~0_109, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[~y$flush_delayed~0, ULTIMATE.start_main_#t~ite46, ~y~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-11-28 18:20:24,776 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] L832-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-11-28 18:20:24,913 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2019-11-28 18:20:24,916 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-28 18:20:24,917 INFO L168 Benchmark]: Toolchain (without parser) took 21836.15 ms. Allocated memory was 1.0 GB in the beginning and 2.0 GB in the end (delta: 1.0 GB). Free memory was 951.0 MB in the beginning and 1.4 GB in the end (delta: -488.9 MB). Peak memory consumption was 528.2 MB. Max. memory is 11.5 GB. [2019-11-28 18:20:24,918 INFO L168 Benchmark]: CDTParser took 0.32 ms. Allocated memory is still 1.0 GB. Free memory is still 987.2 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 18:20:24,918 INFO L168 Benchmark]: CACSL2BoogieTranslator took 792.55 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 115.3 MB). Free memory was 951.0 MB in the beginning and 1.1 GB in the end (delta: -131.5 MB). Peak memory consumption was 25.9 MB. Max. memory is 11.5 GB. [2019-11-28 18:20:24,919 INFO L168 Benchmark]: Boogie Procedure Inliner took 71.41 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.8 MB). Peak memory consumption was 6.8 MB. Max. memory is 11.5 GB. [2019-11-28 18:20:24,919 INFO L168 Benchmark]: Boogie Preprocessor took 53.69 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 18:20:24,920 INFO L168 Benchmark]: RCFGBuilder took 777.44 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 45.4 MB). Peak memory consumption was 45.4 MB. Max. memory is 11.5 GB. [2019-11-28 18:20:24,920 INFO L168 Benchmark]: TraceAbstraction took 19972.79 ms. Allocated memory was 1.1 GB in the beginning and 2.0 GB in the end (delta: 901.8 MB). Free memory was 1.0 GB in the beginning and 1.5 GB in the end (delta: -436.1 MB). Peak memory consumption was 465.7 MB. Max. memory is 11.5 GB. [2019-11-28 18:20:24,921 INFO L168 Benchmark]: Witness Printer took 161.93 ms. Allocated memory is still 2.0 GB. Free memory was 1.5 GB in the beginning and 1.4 GB in the end (delta: 19.6 MB). Peak memory consumption was 19.6 MB. Max. memory is 11.5 GB. [2019-11-28 18:20:24,923 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.32 ms. Allocated memory is still 1.0 GB. Free memory is still 987.2 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 792.55 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 115.3 MB). Free memory was 951.0 MB in the beginning and 1.1 GB in the end (delta: -131.5 MB). Peak memory consumption was 25.9 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 71.41 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.8 MB). Peak memory consumption was 6.8 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 53.69 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 777.44 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 45.4 MB). Peak memory consumption was 45.4 MB. Max. memory is 11.5 GB. * TraceAbstraction took 19972.79 ms. Allocated memory was 1.1 GB in the beginning and 2.0 GB in the end (delta: 901.8 MB). Free memory was 1.0 GB in the beginning and 1.5 GB in the end (delta: -436.1 MB). Peak memory consumption was 465.7 MB. Max. memory is 11.5 GB. * Witness Printer took 161.93 ms. Allocated memory is still 2.0 GB. Free memory was 1.5 GB in the beginning and 1.4 GB in the end (delta: 19.6 MB). Peak memory consumption was 19.6 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 5.0s, 162 ProgramPointsBefore, 83 ProgramPointsAfterwards, 193 TransitionsBefore, 92 TransitionsAfterwards, 11490 CoEnabledTransitionPairs, 7 FixpointIterations, 31 TrivialSequentialCompositions, 44 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 34 ConcurrentYvCompositions, 26 ChoiceCompositions, 3955 VarBasedMoverChecksPositive, 193 VarBasedMoverChecksNegative, 45 SemBasedMoverChecksPositive, 196 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 1.3s, 0 MoverChecksTotal, 48383 CheckedPairsTotal, 109 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L800] FCALL, FORK 0 pthread_create(&t1504, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L802] FCALL, FORK 0 pthread_create(&t1505, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L804] FCALL, FORK 0 pthread_create(&t1506, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L767] 3 y$r_buff1_thd0 = y$r_buff0_thd0 [L768] 3 y$r_buff1_thd1 = y$r_buff0_thd1 [L769] 3 y$r_buff1_thd2 = y$r_buff0_thd2 [L770] 3 y$r_buff1_thd3 = y$r_buff0_thd3 [L771] 3 y$r_buff0_thd3 = (_Bool)1 [L774] 3 __unbuffered_p2_EAX = z VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=0] [L777] EXPR 3 y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L742] 2 x = 2 [L745] 2 y = 1 VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L777] 3 y = y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) [L748] 2 y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L749] 2 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$w_buff0_used [L750] 2 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used [L751] 2 y$r_buff0_thd2 = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$r_buff0_thd2 [L778] 3 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : y$w_buff0_used [L779] 3 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd3 || y$w_buff1_used && y$r_buff1_thd3 ? (_Bool)0 : y$w_buff1_used [L810] 0 y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L811] 0 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used [L812] 0 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$w_buff1_used [L813] 0 y$r_buff0_thd0 = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$r_buff0_thd0 [L814] 0 y$r_buff1_thd0 = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$r_buff1_thd0 [L817] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L818] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L819] 0 y$flush_delayed = weak$$choice2 [L820] 0 y$mem_tmp = y VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L821] EXPR 0 !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L821] 0 y = !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) [L822] 0 y$w_buff0 = weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) [L823] EXPR 0 weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L823] 0 y$w_buff1 = weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) [L824] EXPR 0 weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L824] 0 y$w_buff0_used = weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) [L825] EXPR 0 weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L825] 0 y$w_buff1_used = weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L827] EXPR 0 weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L827] 0 y$r_buff1_thd0 = weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L828] 0 main$tmp_guard1 = !(x == 2 && y == 2 && __unbuffered_p2_EAX == 0) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 153 locations, 2 error locations. Result: UNSAFE, OverallTime: 19.7s, OverallIterations: 16, TraceHistogramMax: 1, AutomataDifference: 5.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 1648 SDtfs, 1540 SDslu, 2977 SDs, 0 SdLazy, 1458 SolverSat, 108 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 2.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 101 GetRequests, 20 SyntacticMatches, 8 SemanticMatches, 73 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 101 ImplicationChecksByTransitivity, 0.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=28190occurred in iteration=5, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 5.1s AutomataMinimizationTime, 15 MinimizatonAttempts, 17030 StatesRemovedByMinimization, 12 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.5s SatisfiabilityAnalysisTime, 1.7s InterpolantComputationTime, 623 NumberOfCodeBlocks, 623 NumberOfCodeBlocksAsserted, 16 NumberOfCheckSat, 551 ConstructedInterpolants, 0 QuantifiedInterpolants, 95139 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 15 InterpolantComputations, 15 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...