./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/pthread-wmm/mix056_tso.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx12G -Xms1G -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/pthread-wmm/mix056_tso.opt.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 7df04869a813bcedcfd0bfe21f6b1fbea7b23d38 ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-11-28 18:20:23,688 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-28 18:20:23,690 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-28 18:20:23,703 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-28 18:20:23,704 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-28 18:20:23,705 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-28 18:20:23,707 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-28 18:20:23,709 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-28 18:20:23,711 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-28 18:20:23,712 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-28 18:20:23,713 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-28 18:20:23,714 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-28 18:20:23,714 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-28 18:20:23,716 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-28 18:20:23,717 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-28 18:20:23,718 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-28 18:20:23,719 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-28 18:20:23,720 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-28 18:20:23,722 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-28 18:20:23,724 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-28 18:20:23,726 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-28 18:20:23,727 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-28 18:20:23,728 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-28 18:20:23,729 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-28 18:20:23,732 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-28 18:20:23,732 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-28 18:20:23,732 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-28 18:20:23,734 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-28 18:20:23,734 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-28 18:20:23,735 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-28 18:20:23,735 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-28 18:20:23,736 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-28 18:20:23,737 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-28 18:20:23,738 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-28 18:20:23,739 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-28 18:20:23,740 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-28 18:20:23,740 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-28 18:20:23,741 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-28 18:20:23,741 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-28 18:20:23,742 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-28 18:20:23,743 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-28 18:20:23,744 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-28 18:20:23,759 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-28 18:20:23,759 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-28 18:20:23,761 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-28 18:20:23,761 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-28 18:20:23,761 INFO L138 SettingsManager]: * Use SBE=true [2019-11-28 18:20:23,762 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-28 18:20:23,762 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-28 18:20:23,762 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-28 18:20:23,763 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-28 18:20:23,763 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-28 18:20:23,763 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-28 18:20:23,763 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-28 18:20:23,764 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-28 18:20:23,764 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-28 18:20:23,764 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-28 18:20:23,764 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-28 18:20:23,765 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-28 18:20:23,765 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-28 18:20:23,765 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-28 18:20:23,766 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-28 18:20:23,766 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-28 18:20:23,766 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 18:20:23,766 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-28 18:20:23,767 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-28 18:20:23,767 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-28 18:20:23,767 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-28 18:20:23,768 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-28 18:20:23,768 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-28 18:20:23,768 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-11-28 18:20:23,768 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 7df04869a813bcedcfd0bfe21f6b1fbea7b23d38 [2019-11-28 18:20:24,107 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-28 18:20:24,120 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-28 18:20:24,124 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-28 18:20:24,126 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-28 18:20:24,127 INFO L275 PluginConnector]: CDTParser initialized [2019-11-28 18:20:24,127 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/pthread-wmm/mix056_tso.opt.i [2019-11-28 18:20:24,192 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c3cc4ae3e/865e0a118bbb49ea8e2bf086525f663e/FLAG640422877 [2019-11-28 18:20:24,743 INFO L306 CDTParser]: Found 1 translation units. [2019-11-28 18:20:24,745 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/pthread-wmm/mix056_tso.opt.i [2019-11-28 18:20:24,771 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c3cc4ae3e/865e0a118bbb49ea8e2bf086525f663e/FLAG640422877 [2019-11-28 18:20:24,972 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c3cc4ae3e/865e0a118bbb49ea8e2bf086525f663e [2019-11-28 18:20:24,976 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-28 18:20:24,978 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-28 18:20:24,979 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-28 18:20:24,980 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-28 18:20:24,983 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-28 18:20:24,984 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 06:20:24" (1/1) ... [2019-11-28 18:20:24,987 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@16abc7cd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:24, skipping insertion in model container [2019-11-28 18:20:24,987 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 06:20:24" (1/1) ... [2019-11-28 18:20:24,996 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-11-28 18:20:25,067 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-11-28 18:20:25,660 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 18:20:25,680 INFO L203 MainTranslator]: Completed pre-run [2019-11-28 18:20:25,774 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 18:20:25,888 INFO L208 MainTranslator]: Completed translation [2019-11-28 18:20:25,889 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:25 WrapperNode [2019-11-28 18:20:25,889 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-28 18:20:25,890 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-28 18:20:25,890 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-28 18:20:25,890 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-28 18:20:25,901 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:25" (1/1) ... [2019-11-28 18:20:25,952 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:25" (1/1) ... [2019-11-28 18:20:26,009 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-28 18:20:26,012 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-28 18:20:26,013 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-28 18:20:26,013 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-28 18:20:26,024 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:25" (1/1) ... [2019-11-28 18:20:26,025 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:25" (1/1) ... [2019-11-28 18:20:26,046 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:25" (1/1) ... [2019-11-28 18:20:26,047 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:25" (1/1) ... [2019-11-28 18:20:26,059 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:25" (1/1) ... [2019-11-28 18:20:26,063 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:25" (1/1) ... [2019-11-28 18:20:26,067 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:25" (1/1) ... [2019-11-28 18:20:26,072 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-28 18:20:26,072 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-28 18:20:26,072 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-28 18:20:26,073 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-28 18:20:26,074 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:25" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 18:20:26,158 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-11-28 18:20:26,159 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-11-28 18:20:26,159 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-11-28 18:20:26,160 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-11-28 18:20:26,160 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-11-28 18:20:26,160 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-11-28 18:20:26,160 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-11-28 18:20:26,160 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-11-28 18:20:26,161 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-11-28 18:20:26,161 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-11-28 18:20:26,162 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-11-28 18:20:26,162 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-28 18:20:26,162 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-28 18:20:26,165 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-11-28 18:20:26,964 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-28 18:20:26,964 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-11-28 18:20:26,965 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:20:26 BoogieIcfgContainer [2019-11-28 18:20:26,965 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-28 18:20:26,966 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-28 18:20:26,967 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-28 18:20:26,969 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-28 18:20:26,969 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 06:20:24" (1/3) ... [2019-11-28 18:20:26,970 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2663ee0e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 06:20:26, skipping insertion in model container [2019-11-28 18:20:26,970 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:25" (2/3) ... [2019-11-28 18:20:26,971 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2663ee0e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 06:20:26, skipping insertion in model container [2019-11-28 18:20:26,971 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:20:26" (3/3) ... [2019-11-28 18:20:26,973 INFO L109 eAbstractionObserver]: Analyzing ICFG mix056_tso.opt.i [2019-11-28 18:20:26,983 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-11-28 18:20:26,984 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-28 18:20:26,991 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-11-28 18:20:26,992 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-11-28 18:20:27,029 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,030 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,030 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,030 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,031 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,031 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,031 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,032 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,032 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,032 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,032 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,033 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,033 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,033 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,034 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,034 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,034 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,034 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,035 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,035 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,035 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,035 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,036 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,036 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,036 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,037 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,037 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,037 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,037 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,038 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,038 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,038 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,039 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,039 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,039 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,039 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,040 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,041 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,041 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,041 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,041 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,041 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,042 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,042 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,042 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,043 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,043 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,043 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,043 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,044 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,044 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,044 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,045 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,045 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,045 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,045 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,045 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,046 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,046 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,046 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,047 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,047 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,047 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,047 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,048 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,048 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,048 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,049 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,049 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,049 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:27,069 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-11-28 18:20:27,091 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-28 18:20:27,091 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-28 18:20:27,091 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-28 18:20:27,092 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-28 18:20:27,092 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-28 18:20:27,092 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-28 18:20:27,092 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-28 18:20:27,092 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-28 18:20:27,111 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 162 places, 193 transitions [2019-11-28 18:20:27,113 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 162 places, 193 transitions [2019-11-28 18:20:27,209 INFO L134 PetriNetUnfolder]: 41/190 cut-off events. [2019-11-28 18:20:27,210 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-11-28 18:20:27,226 INFO L76 FinitePrefix]: Finished finitePrefix Result has 200 conditions, 190 events. 41/190 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 465 event pairs. 9/156 useless extension candidates. Maximal degree in co-relation 161. Up to 2 conditions per place. [2019-11-28 18:20:27,249 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 162 places, 193 transitions [2019-11-28 18:20:27,298 INFO L134 PetriNetUnfolder]: 41/190 cut-off events. [2019-11-28 18:20:27,299 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-11-28 18:20:27,306 INFO L76 FinitePrefix]: Finished finitePrefix Result has 200 conditions, 190 events. 41/190 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 465 event pairs. 9/156 useless extension candidates. Maximal degree in co-relation 161. Up to 2 conditions per place. [2019-11-28 18:20:27,324 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 11490 [2019-11-28 18:20:27,325 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-11-28 18:20:32,266 WARN L192 SmtUtils]: Spent 261.00 ms on a formula simplification. DAG size of input: 87 DAG size of output: 85 [2019-11-28 18:20:32,421 WARN L192 SmtUtils]: Spent 153.00 ms on a formula simplification that was a NOOP. DAG size: 83 [2019-11-28 18:20:32,448 INFO L206 etLargeBlockEncoding]: Checked pairs total: 48383 [2019-11-28 18:20:32,449 INFO L214 etLargeBlockEncoding]: Total number of compositions: 109 [2019-11-28 18:20:32,453 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 83 places, 92 transitions [2019-11-28 18:20:34,169 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 16526 states. [2019-11-28 18:20:34,172 INFO L276 IsEmpty]: Start isEmpty. Operand 16526 states. [2019-11-28 18:20:34,184 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2019-11-28 18:20:34,184 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:34,186 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:34,186 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:34,193 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:34,193 INFO L82 PathProgramCache]: Analyzing trace with hash 2128093424, now seen corresponding path program 1 times [2019-11-28 18:20:34,202 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:34,203 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2114913477] [2019-11-28 18:20:34,204 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:34,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:34,491 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:34,492 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2114913477] [2019-11-28 18:20:34,492 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:34,493 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-11-28 18:20:34,494 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [750048377] [2019-11-28 18:20:34,499 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:20:34,499 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:34,514 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:20:34,515 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:34,517 INFO L87 Difference]: Start difference. First operand 16526 states. Second operand 3 states. [2019-11-28 18:20:34,875 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:34,876 INFO L93 Difference]: Finished difference Result 16398 states and 61580 transitions. [2019-11-28 18:20:34,877 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:20:34,878 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2019-11-28 18:20:34,879 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:35,067 INFO L225 Difference]: With dead ends: 16398 [2019-11-28 18:20:35,068 INFO L226 Difference]: Without dead ends: 16062 [2019-11-28 18:20:35,069 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:35,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16062 states. [2019-11-28 18:20:35,912 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16062 to 16062. [2019-11-28 18:20:35,913 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16062 states. [2019-11-28 18:20:36,050 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16062 states to 16062 states and 60376 transitions. [2019-11-28 18:20:36,052 INFO L78 Accepts]: Start accepts. Automaton has 16062 states and 60376 transitions. Word has length 7 [2019-11-28 18:20:36,053 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:36,053 INFO L462 AbstractCegarLoop]: Abstraction has 16062 states and 60376 transitions. [2019-11-28 18:20:36,053 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:20:36,053 INFO L276 IsEmpty]: Start isEmpty. Operand 16062 states and 60376 transitions. [2019-11-28 18:20:36,064 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-11-28 18:20:36,065 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:36,065 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:36,065 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:36,066 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:36,066 INFO L82 PathProgramCache]: Analyzing trace with hash -1390331573, now seen corresponding path program 1 times [2019-11-28 18:20:36,067 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:36,067 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1809444361] [2019-11-28 18:20:36,067 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:36,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:36,235 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:36,235 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1809444361] [2019-11-28 18:20:36,235 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:36,236 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:20:36,236 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [990446453] [2019-11-28 18:20:36,237 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:20:36,238 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:36,238 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:20:36,238 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:20:36,238 INFO L87 Difference]: Start difference. First operand 16062 states and 60376 transitions. Second operand 4 states. [2019-11-28 18:20:36,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:36,649 INFO L93 Difference]: Finished difference Result 24942 states and 90524 transitions. [2019-11-28 18:20:36,650 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:20:36,650 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-11-28 18:20:36,650 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:36,754 INFO L225 Difference]: With dead ends: 24942 [2019-11-28 18:20:36,755 INFO L226 Difference]: Without dead ends: 24928 [2019-11-28 18:20:36,756 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:20:36,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24928 states. [2019-11-28 18:20:37,825 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24928 to 22166. [2019-11-28 18:20:37,826 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22166 states. [2019-11-28 18:20:37,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22166 states to 22166 states and 81470 transitions. [2019-11-28 18:20:37,918 INFO L78 Accepts]: Start accepts. Automaton has 22166 states and 81470 transitions. Word has length 13 [2019-11-28 18:20:37,919 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:37,919 INFO L462 AbstractCegarLoop]: Abstraction has 22166 states and 81470 transitions. [2019-11-28 18:20:37,919 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:20:37,919 INFO L276 IsEmpty]: Start isEmpty. Operand 22166 states and 81470 transitions. [2019-11-28 18:20:37,921 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-11-28 18:20:37,921 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:37,922 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:37,922 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:37,922 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:37,923 INFO L82 PathProgramCache]: Analyzing trace with hash -1371832765, now seen corresponding path program 1 times [2019-11-28 18:20:37,923 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:37,923 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [678759779] [2019-11-28 18:20:37,924 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:37,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:37,986 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:37,986 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [678759779] [2019-11-28 18:20:37,986 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:37,987 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:20:37,987 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [989972233] [2019-11-28 18:20:37,987 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:20:37,987 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:37,988 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:20:37,988 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:20:37,989 INFO L87 Difference]: Start difference. First operand 22166 states and 81470 transitions. Second operand 4 states. [2019-11-28 18:20:38,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:38,333 INFO L93 Difference]: Finished difference Result 27782 states and 100994 transitions. [2019-11-28 18:20:38,333 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:20:38,333 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-11-28 18:20:38,333 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:38,404 INFO L225 Difference]: With dead ends: 27782 [2019-11-28 18:20:38,405 INFO L226 Difference]: Without dead ends: 27782 [2019-11-28 18:20:38,405 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:20:38,605 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27782 states. [2019-11-28 18:20:39,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27782 to 24630. [2019-11-28 18:20:39,152 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24630 states. [2019-11-28 18:20:39,847 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24630 states to 24630 states and 90262 transitions. [2019-11-28 18:20:39,848 INFO L78 Accepts]: Start accepts. Automaton has 24630 states and 90262 transitions. Word has length 13 [2019-11-28 18:20:39,848 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:39,848 INFO L462 AbstractCegarLoop]: Abstraction has 24630 states and 90262 transitions. [2019-11-28 18:20:39,848 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:20:39,848 INFO L276 IsEmpty]: Start isEmpty. Operand 24630 states and 90262 transitions. [2019-11-28 18:20:39,856 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-11-28 18:20:39,856 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:39,856 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:39,857 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:39,857 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:39,857 INFO L82 PathProgramCache]: Analyzing trace with hash -1003212910, now seen corresponding path program 1 times [2019-11-28 18:20:39,857 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:39,858 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [26439954] [2019-11-28 18:20:39,858 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:39,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:39,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:39,936 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [26439954] [2019-11-28 18:20:39,936 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:39,936 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:20:39,937 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1222008541] [2019-11-28 18:20:39,937 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:20:39,937 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:39,937 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:20:39,938 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:20:39,938 INFO L87 Difference]: Start difference. First operand 24630 states and 90262 transitions. Second operand 5 states. [2019-11-28 18:20:40,454 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:40,454 INFO L93 Difference]: Finished difference Result 33042 states and 118962 transitions. [2019-11-28 18:20:40,454 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-11-28 18:20:40,454 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-11-28 18:20:40,455 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:40,542 INFO L225 Difference]: With dead ends: 33042 [2019-11-28 18:20:40,542 INFO L226 Difference]: Without dead ends: 33028 [2019-11-28 18:20:40,542 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-11-28 18:20:40,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33028 states. [2019-11-28 18:20:41,329 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33028 to 24716. [2019-11-28 18:20:41,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24716 states. [2019-11-28 18:20:41,397 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24716 states to 24716 states and 90325 transitions. [2019-11-28 18:20:41,397 INFO L78 Accepts]: Start accepts. Automaton has 24716 states and 90325 transitions. Word has length 19 [2019-11-28 18:20:41,397 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:41,398 INFO L462 AbstractCegarLoop]: Abstraction has 24716 states and 90325 transitions. [2019-11-28 18:20:41,398 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:20:41,398 INFO L276 IsEmpty]: Start isEmpty. Operand 24716 states and 90325 transitions. [2019-11-28 18:20:41,429 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-11-28 18:20:41,429 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:41,429 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:41,429 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:41,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:41,430 INFO L82 PathProgramCache]: Analyzing trace with hash -1251036613, now seen corresponding path program 1 times [2019-11-28 18:20:41,430 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:41,430 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [595696230] [2019-11-28 18:20:41,430 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:41,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:41,483 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:41,484 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [595696230] [2019-11-28 18:20:41,484 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:41,484 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:20:41,484 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [600365159] [2019-11-28 18:20:41,485 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:20:41,485 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:41,485 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:20:41,486 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:41,486 INFO L87 Difference]: Start difference. First operand 24716 states and 90325 transitions. Second operand 3 states. [2019-11-28 18:20:42,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:42,253 INFO L93 Difference]: Finished difference Result 30008 states and 109703 transitions. [2019-11-28 18:20:42,253 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:20:42,254 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-11-28 18:20:42,254 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:42,321 INFO L225 Difference]: With dead ends: 30008 [2019-11-28 18:20:42,321 INFO L226 Difference]: Without dead ends: 30008 [2019-11-28 18:20:42,321 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:42,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30008 states. [2019-11-28 18:20:43,007 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30008 to 28190. [2019-11-28 18:20:43,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28190 states. [2019-11-28 18:20:43,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28190 states to 28190 states and 103378 transitions. [2019-11-28 18:20:43,091 INFO L78 Accepts]: Start accepts. Automaton has 28190 states and 103378 transitions. Word has length 27 [2019-11-28 18:20:43,092 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:43,092 INFO L462 AbstractCegarLoop]: Abstraction has 28190 states and 103378 transitions. [2019-11-28 18:20:43,092 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:20:43,092 INFO L276 IsEmpty]: Start isEmpty. Operand 28190 states and 103378 transitions. [2019-11-28 18:20:43,117 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-11-28 18:20:43,117 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:43,117 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:43,118 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:43,118 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:43,118 INFO L82 PathProgramCache]: Analyzing trace with hash -1250824263, now seen corresponding path program 1 times [2019-11-28 18:20:43,118 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:43,119 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1701750263] [2019-11-28 18:20:43,119 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:43,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:43,189 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:43,189 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1701750263] [2019-11-28 18:20:43,190 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:43,190 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:20:43,190 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [827253486] [2019-11-28 18:20:43,190 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:20:43,191 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:43,191 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:20:43,191 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:43,191 INFO L87 Difference]: Start difference. First operand 28190 states and 103378 transitions. Second operand 3 states. [2019-11-28 18:20:43,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:43,258 INFO L93 Difference]: Finished difference Result 16100 states and 51114 transitions. [2019-11-28 18:20:43,258 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:20:43,258 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-11-28 18:20:43,258 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:43,284 INFO L225 Difference]: With dead ends: 16100 [2019-11-28 18:20:43,284 INFO L226 Difference]: Without dead ends: 16100 [2019-11-28 18:20:43,284 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:43,351 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16100 states. [2019-11-28 18:20:43,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16100 to 16100. [2019-11-28 18:20:43,545 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16100 states. [2019-11-28 18:20:43,580 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16100 states to 16100 states and 51114 transitions. [2019-11-28 18:20:43,580 INFO L78 Accepts]: Start accepts. Automaton has 16100 states and 51114 transitions. Word has length 27 [2019-11-28 18:20:43,580 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:43,580 INFO L462 AbstractCegarLoop]: Abstraction has 16100 states and 51114 transitions. [2019-11-28 18:20:43,580 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:20:43,581 INFO L276 IsEmpty]: Start isEmpty. Operand 16100 states and 51114 transitions. [2019-11-28 18:20:43,589 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-11-28 18:20:43,589 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:43,589 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:43,589 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:43,590 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:43,590 INFO L82 PathProgramCache]: Analyzing trace with hash 411430761, now seen corresponding path program 1 times [2019-11-28 18:20:43,590 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:43,590 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1597834338] [2019-11-28 18:20:43,591 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:43,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:43,660 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:43,661 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1597834338] [2019-11-28 18:20:43,662 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:43,662 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:20:43,662 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1956447866] [2019-11-28 18:20:43,663 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:20:43,663 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:43,663 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:20:43,663 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:20:43,663 INFO L87 Difference]: Start difference. First operand 16100 states and 51114 transitions. Second operand 4 states. [2019-11-28 18:20:43,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:43,686 INFO L93 Difference]: Finished difference Result 2377 states and 5510 transitions. [2019-11-28 18:20:43,687 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-28 18:20:43,687 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 28 [2019-11-28 18:20:43,687 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:43,691 INFO L225 Difference]: With dead ends: 2377 [2019-11-28 18:20:43,692 INFO L226 Difference]: Without dead ends: 2377 [2019-11-28 18:20:43,693 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:20:43,698 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2377 states. [2019-11-28 18:20:43,718 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2377 to 2377. [2019-11-28 18:20:43,718 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2377 states. [2019-11-28 18:20:43,722 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2377 states to 2377 states and 5510 transitions. [2019-11-28 18:20:43,722 INFO L78 Accepts]: Start accepts. Automaton has 2377 states and 5510 transitions. Word has length 28 [2019-11-28 18:20:43,722 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:43,723 INFO L462 AbstractCegarLoop]: Abstraction has 2377 states and 5510 transitions. [2019-11-28 18:20:43,723 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:20:43,723 INFO L276 IsEmpty]: Start isEmpty. Operand 2377 states and 5510 transitions. [2019-11-28 18:20:43,726 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2019-11-28 18:20:43,726 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:43,726 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:43,727 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:43,727 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:43,727 INFO L82 PathProgramCache]: Analyzing trace with hash -1388136454, now seen corresponding path program 1 times [2019-11-28 18:20:43,727 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:43,727 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1739495400] [2019-11-28 18:20:43,727 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:43,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:43,830 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:43,830 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1739495400] [2019-11-28 18:20:43,830 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:43,830 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 18:20:43,831 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [396738525] [2019-11-28 18:20:43,831 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:20:43,831 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:43,831 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:20:43,831 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:20:43,832 INFO L87 Difference]: Start difference. First operand 2377 states and 5510 transitions. Second operand 5 states. [2019-11-28 18:20:43,853 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:43,853 INFO L93 Difference]: Finished difference Result 678 states and 1563 transitions. [2019-11-28 18:20:43,853 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:20:43,853 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 40 [2019-11-28 18:20:43,853 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:43,854 INFO L225 Difference]: With dead ends: 678 [2019-11-28 18:20:43,854 INFO L226 Difference]: Without dead ends: 678 [2019-11-28 18:20:43,855 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:20:43,856 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 678 states. [2019-11-28 18:20:43,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 678 to 622. [2019-11-28 18:20:43,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 622 states. [2019-11-28 18:20:43,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 622 states to 622 states and 1431 transitions. [2019-11-28 18:20:43,863 INFO L78 Accepts]: Start accepts. Automaton has 622 states and 1431 transitions. Word has length 40 [2019-11-28 18:20:43,863 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:43,863 INFO L462 AbstractCegarLoop]: Abstraction has 622 states and 1431 transitions. [2019-11-28 18:20:43,863 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:20:43,863 INFO L276 IsEmpty]: Start isEmpty. Operand 622 states and 1431 transitions. [2019-11-28 18:20:43,865 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-11-28 18:20:43,865 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:43,865 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:43,865 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:43,865 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:43,866 INFO L82 PathProgramCache]: Analyzing trace with hash -826083081, now seen corresponding path program 1 times [2019-11-28 18:20:43,866 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:43,866 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [287904020] [2019-11-28 18:20:43,866 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:43,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:43,992 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:43,992 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [287904020] [2019-11-28 18:20:43,993 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:43,993 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 18:20:43,993 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [301127452] [2019-11-28 18:20:43,993 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-28 18:20:43,994 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:43,995 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-28 18:20:43,995 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-28 18:20:43,995 INFO L87 Difference]: Start difference. First operand 622 states and 1431 transitions. Second operand 6 states. [2019-11-28 18:20:44,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:44,054 INFO L93 Difference]: Finished difference Result 901 states and 1928 transitions. [2019-11-28 18:20:44,054 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 18:20:44,054 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 55 [2019-11-28 18:20:44,055 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:44,056 INFO L225 Difference]: With dead ends: 901 [2019-11-28 18:20:44,056 INFO L226 Difference]: Without dead ends: 559 [2019-11-28 18:20:44,056 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-11-28 18:20:44,057 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 559 states. [2019-11-28 18:20:44,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 559 to 559. [2019-11-28 18:20:44,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 559 states. [2019-11-28 18:20:44,062 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 559 states to 559 states and 1248 transitions. [2019-11-28 18:20:44,063 INFO L78 Accepts]: Start accepts. Automaton has 559 states and 1248 transitions. Word has length 55 [2019-11-28 18:20:44,063 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:44,063 INFO L462 AbstractCegarLoop]: Abstraction has 559 states and 1248 transitions. [2019-11-28 18:20:44,063 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-28 18:20:44,063 INFO L276 IsEmpty]: Start isEmpty. Operand 559 states and 1248 transitions. [2019-11-28 18:20:44,064 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-11-28 18:20:44,064 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:44,065 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:44,065 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:44,065 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:44,065 INFO L82 PathProgramCache]: Analyzing trace with hash -933435833, now seen corresponding path program 2 times [2019-11-28 18:20:44,065 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:44,066 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [925154699] [2019-11-28 18:20:44,066 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:44,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:44,142 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:44,142 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [925154699] [2019-11-28 18:20:44,142 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:44,142 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:20:44,143 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [664680685] [2019-11-28 18:20:44,143 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:20:44,143 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:44,143 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:20:44,144 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:44,144 INFO L87 Difference]: Start difference. First operand 559 states and 1248 transitions. Second operand 3 states. [2019-11-28 18:20:44,194 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:44,194 INFO L93 Difference]: Finished difference Result 558 states and 1246 transitions. [2019-11-28 18:20:44,195 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:20:44,195 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 55 [2019-11-28 18:20:44,195 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:44,196 INFO L225 Difference]: With dead ends: 558 [2019-11-28 18:20:44,196 INFO L226 Difference]: Without dead ends: 558 [2019-11-28 18:20:44,197 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:44,198 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 558 states. [2019-11-28 18:20:44,206 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 558 to 558. [2019-11-28 18:20:44,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 558 states. [2019-11-28 18:20:44,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 558 states to 558 states and 1246 transitions. [2019-11-28 18:20:44,208 INFO L78 Accepts]: Start accepts. Automaton has 558 states and 1246 transitions. Word has length 55 [2019-11-28 18:20:44,208 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:44,208 INFO L462 AbstractCegarLoop]: Abstraction has 558 states and 1246 transitions. [2019-11-28 18:20:44,209 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:20:44,209 INFO L276 IsEmpty]: Start isEmpty. Operand 558 states and 1246 transitions. [2019-11-28 18:20:44,210 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-11-28 18:20:44,210 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:44,211 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:44,211 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:44,211 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:44,211 INFO L82 PathProgramCache]: Analyzing trace with hash -1631888206, now seen corresponding path program 1 times [2019-11-28 18:20:44,212 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:44,212 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [414781046] [2019-11-28 18:20:44,212 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:44,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:44,381 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:44,381 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [414781046] [2019-11-28 18:20:44,382 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:44,382 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 18:20:44,382 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [905103198] [2019-11-28 18:20:44,383 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-28 18:20:44,383 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:44,384 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-28 18:20:44,384 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-11-28 18:20:44,384 INFO L87 Difference]: Start difference. First operand 558 states and 1246 transitions. Second operand 6 states. [2019-11-28 18:20:44,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:44,478 INFO L93 Difference]: Finished difference Result 821 states and 1801 transitions. [2019-11-28 18:20:44,479 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 18:20:44,479 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 56 [2019-11-28 18:20:44,479 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:44,480 INFO L225 Difference]: With dead ends: 821 [2019-11-28 18:20:44,480 INFO L226 Difference]: Without dead ends: 250 [2019-11-28 18:20:44,481 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-11-28 18:20:44,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 250 states. [2019-11-28 18:20:44,485 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 250 to 218. [2019-11-28 18:20:44,485 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 218 states. [2019-11-28 18:20:44,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 218 states to 218 states and 397 transitions. [2019-11-28 18:20:44,486 INFO L78 Accepts]: Start accepts. Automaton has 218 states and 397 transitions. Word has length 56 [2019-11-28 18:20:44,486 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:44,486 INFO L462 AbstractCegarLoop]: Abstraction has 218 states and 397 transitions. [2019-11-28 18:20:44,487 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-28 18:20:44,487 INFO L276 IsEmpty]: Start isEmpty. Operand 218 states and 397 transitions. [2019-11-28 18:20:44,488 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-11-28 18:20:44,488 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:44,488 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:44,488 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:44,489 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:44,489 INFO L82 PathProgramCache]: Analyzing trace with hash -318870370, now seen corresponding path program 2 times [2019-11-28 18:20:44,489 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:44,489 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1677399142] [2019-11-28 18:20:44,490 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:44,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:44,552 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:44,553 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1677399142] [2019-11-28 18:20:44,553 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:44,554 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:20:44,554 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1902577127] [2019-11-28 18:20:44,555 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:20:44,555 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:44,555 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:20:44,555 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:44,556 INFO L87 Difference]: Start difference. First operand 218 states and 397 transitions. Second operand 3 states. [2019-11-28 18:20:44,569 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:44,569 INFO L93 Difference]: Finished difference Result 207 states and 364 transitions. [2019-11-28 18:20:44,570 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:20:44,570 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 56 [2019-11-28 18:20:44,571 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:44,571 INFO L225 Difference]: With dead ends: 207 [2019-11-28 18:20:44,571 INFO L226 Difference]: Without dead ends: 207 [2019-11-28 18:20:44,572 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:44,573 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 207 states. [2019-11-28 18:20:44,576 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 207 to 207. [2019-11-28 18:20:44,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 207 states. [2019-11-28 18:20:44,577 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 364 transitions. [2019-11-28 18:20:44,578 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 364 transitions. Word has length 56 [2019-11-28 18:20:44,578 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:44,578 INFO L462 AbstractCegarLoop]: Abstraction has 207 states and 364 transitions. [2019-11-28 18:20:44,578 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:20:44,579 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 364 transitions. [2019-11-28 18:20:44,580 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:20:44,580 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:44,580 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:44,581 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:44,581 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:44,581 INFO L82 PathProgramCache]: Analyzing trace with hash -1516556909, now seen corresponding path program 1 times [2019-11-28 18:20:44,582 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:44,582 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1842563272] [2019-11-28 18:20:44,582 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:44,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:44,944 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:44,945 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1842563272] [2019-11-28 18:20:44,945 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:44,945 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-11-28 18:20:44,946 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1224782492] [2019-11-28 18:20:44,946 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-11-28 18:20:44,946 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:44,947 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-11-28 18:20:44,947 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=128, Unknown=0, NotChecked=0, Total=156 [2019-11-28 18:20:44,947 INFO L87 Difference]: Start difference. First operand 207 states and 364 transitions. Second operand 13 states. [2019-11-28 18:20:45,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:45,498 INFO L93 Difference]: Finished difference Result 363 states and 623 transitions. [2019-11-28 18:20:45,499 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-11-28 18:20:45,499 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 57 [2019-11-28 18:20:45,499 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:45,500 INFO L225 Difference]: With dead ends: 363 [2019-11-28 18:20:45,500 INFO L226 Difference]: Without dead ends: 333 [2019-11-28 18:20:45,500 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 61 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=80, Invalid=382, Unknown=0, NotChecked=0, Total=462 [2019-11-28 18:20:45,501 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 333 states. [2019-11-28 18:20:45,506 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 333 to 303. [2019-11-28 18:20:45,506 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 303 states. [2019-11-28 18:20:45,507 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 303 states to 303 states and 528 transitions. [2019-11-28 18:20:45,507 INFO L78 Accepts]: Start accepts. Automaton has 303 states and 528 transitions. Word has length 57 [2019-11-28 18:20:45,508 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:45,508 INFO L462 AbstractCegarLoop]: Abstraction has 303 states and 528 transitions. [2019-11-28 18:20:45,508 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-11-28 18:20:45,508 INFO L276 IsEmpty]: Start isEmpty. Operand 303 states and 528 transitions. [2019-11-28 18:20:45,509 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:20:45,509 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:45,509 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:45,510 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:45,510 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:45,510 INFO L82 PathProgramCache]: Analyzing trace with hash 1886575453, now seen corresponding path program 2 times [2019-11-28 18:20:45,510 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:45,511 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1887325756] [2019-11-28 18:20:45,511 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:45,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:46,114 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:46,114 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1887325756] [2019-11-28 18:20:46,114 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:46,115 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-11-28 18:20:46,115 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1199173968] [2019-11-28 18:20:46,115 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-11-28 18:20:46,115 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:46,116 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-11-28 18:20:46,116 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=151, Unknown=0, NotChecked=0, Total=182 [2019-11-28 18:20:46,116 INFO L87 Difference]: Start difference. First operand 303 states and 528 transitions. Second operand 14 states. [2019-11-28 18:20:46,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:46,650 INFO L93 Difference]: Finished difference Result 419 states and 709 transitions. [2019-11-28 18:20:46,650 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-11-28 18:20:46,650 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 57 [2019-11-28 18:20:46,651 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:46,651 INFO L225 Difference]: With dead ends: 419 [2019-11-28 18:20:46,651 INFO L226 Difference]: Without dead ends: 389 [2019-11-28 18:20:46,652 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 81 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=91, Invalid=461, Unknown=0, NotChecked=0, Total=552 [2019-11-28 18:20:46,653 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 389 states. [2019-11-28 18:20:46,656 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 389 to 307. [2019-11-28 18:20:46,656 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 307 states. [2019-11-28 18:20:46,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 307 states to 307 states and 535 transitions. [2019-11-28 18:20:46,656 INFO L78 Accepts]: Start accepts. Automaton has 307 states and 535 transitions. Word has length 57 [2019-11-28 18:20:46,656 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:46,657 INFO L462 AbstractCegarLoop]: Abstraction has 307 states and 535 transitions. [2019-11-28 18:20:46,657 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-11-28 18:20:46,657 INFO L276 IsEmpty]: Start isEmpty. Operand 307 states and 535 transitions. [2019-11-28 18:20:46,657 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:20:46,658 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:46,658 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:46,658 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:46,658 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:46,658 INFO L82 PathProgramCache]: Analyzing trace with hash -1834190715, now seen corresponding path program 3 times [2019-11-28 18:20:46,658 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:46,659 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [618977597] [2019-11-28 18:20:46,659 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:46,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:46,960 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:46,961 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [618977597] [2019-11-28 18:20:46,961 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:46,961 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-11-28 18:20:46,961 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1303195700] [2019-11-28 18:20:46,961 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-11-28 18:20:46,962 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:46,962 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-11-28 18:20:46,962 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=170, Unknown=0, NotChecked=0, Total=210 [2019-11-28 18:20:46,962 INFO L87 Difference]: Start difference. First operand 307 states and 535 transitions. Second operand 15 states. [2019-11-28 18:20:47,490 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:47,490 INFO L93 Difference]: Finished difference Result 415 states and 703 transitions. [2019-11-28 18:20:47,490 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-11-28 18:20:47,490 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 57 [2019-11-28 18:20:47,491 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:47,491 INFO L225 Difference]: With dead ends: 415 [2019-11-28 18:20:47,491 INFO L226 Difference]: Without dead ends: 385 [2019-11-28 18:20:47,492 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 93 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=131, Invalid=519, Unknown=0, NotChecked=0, Total=650 [2019-11-28 18:20:47,493 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 385 states. [2019-11-28 18:20:47,499 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 385 to 315. [2019-11-28 18:20:47,499 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 315 states. [2019-11-28 18:20:47,500 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 315 states to 315 states and 549 transitions. [2019-11-28 18:20:47,500 INFO L78 Accepts]: Start accepts. Automaton has 315 states and 549 transitions. Word has length 57 [2019-11-28 18:20:47,502 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:47,502 INFO L462 AbstractCegarLoop]: Abstraction has 315 states and 549 transitions. [2019-11-28 18:20:47,502 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-11-28 18:20:47,502 INFO L276 IsEmpty]: Start isEmpty. Operand 315 states and 549 transitions. [2019-11-28 18:20:47,503 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:20:47,503 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:47,503 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:47,503 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:47,504 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:47,504 INFO L82 PathProgramCache]: Analyzing trace with hash 731376245, now seen corresponding path program 4 times [2019-11-28 18:20:47,504 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:47,504 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1746645254] [2019-11-28 18:20:47,504 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:47,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 18:20:47,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 18:20:47,676 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-28 18:20:47,678 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-28 18:20:47,683 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [740] [740] ULTIMATE.startENTRY-->L800: Formula: (let ((.cse0 (store |v_#valid_62| 0 0))) (and (= 0 v_~y$read_delayed_var~0.base_6) (= 0 v_~weak$$choice0~0_25) (= 0 v_~y$r_buff0_thd3~0_151) (= v_~y$w_buff1~0_200 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t1510~0.base_26|)) (= v_~y$w_buff0_used~0_650 0) (= v_~__unbuffered_cnt~0_109 0) (< 0 |v_#StackHeapBarrier_16|) (= 0 v_~y$w_buff0~0_308) (= 0 v_~y$r_buff1_thd3~0_122) (= v_~y$read_delayed~0_6 0) (= 0 v_~y$r_buff1_thd1~0_76) (= |v_#valid_60| (store .cse0 |v_ULTIMATE.start_main_~#t1510~0.base_26| 1)) (= (store |v_#length_24| |v_ULTIMATE.start_main_~#t1510~0.base_26| 4) |v_#length_23|) (= v_~z~0_51 0) (= v_~y$r_buff0_thd1~0_29 0) (= v_~main$tmp_guard1~0_28 0) (= v_~y$r_buff0_thd0~0_312 0) (= 0 v_~__unbuffered_p2_EAX~0_90) (= 0 v_~y$flush_delayed~0_45) (= v_~y$w_buff1_used~0_407 0) (= v_~y$r_buff0_thd2~0_88 0) (= (store |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1510~0.base_26| (store (select |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1510~0.base_26|) |v_ULTIMATE.start_main_~#t1510~0.offset_19| 0)) |v_#memory_int_23|) (= |v_#NULL.offset_5| 0) (= 0 v_~y$r_buff1_thd2~0_131) (= v_~y$mem_tmp~0_31 0) (= |v_ULTIMATE.start_main_~#t1510~0.offset_19| 0) (= 0 v_~y$read_delayed_var~0.offset_6) (= v_~y~0_150 0) (= v_~weak$$choice2~0_131 0) (= v_~y$r_buff1_thd0~0_254 0) (< |v_#StackHeapBarrier_16| |v_ULTIMATE.start_main_~#t1510~0.base_26|) (= v_~main$tmp_guard0~0_24 0) (= 0 |v_#NULL.base_5|) (= v_~x~0_80 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_16|, #valid=|v_#valid_62|, #memory_int=|v_#memory_int_24|, #length=|v_#length_24|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_28|, ULTIMATE.start_main_~#t1511~0.offset=|v_ULTIMATE.start_main_~#t1511~0.offset_19|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_26|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_104|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_52|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_26|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_38|, ~y$read_delayed~0=v_~y$read_delayed~0_6, ~y$mem_tmp~0=v_~y$mem_tmp~0_31, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_122, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_29, ~y$flush_delayed~0=v_~y$flush_delayed~0_45, ULTIMATE.start_main_~#t1510~0.base=|v_ULTIMATE.start_main_~#t1510~0.base_26|, #length=|v_#length_23|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_90, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_34|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_142|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_44|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_31|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_98|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_27|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_26|, ~weak$$choice0~0=v_~weak$$choice0~0_25, #StackHeapBarrier=|v_#StackHeapBarrier_16|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_28|, ~y$w_buff1~0=v_~y$w_buff1~0_200, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_6, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_88, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_8|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_22|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_109, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_254, ~x~0=v_~x~0_80, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_6, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_650, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_38|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_31|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_28, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_28|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_32|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_16|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_58|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_50|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_76, ULTIMATE.start_main_~#t1512~0.base=|v_ULTIMATE.start_main_~#t1512~0.base_21|, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_44|, ULTIMATE.start_main_~#t1510~0.offset=|v_ULTIMATE.start_main_~#t1510~0.offset_19|, ~y$w_buff0~0=v_~y$w_buff0~0_308, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_151, ~y~0=v_~y~0_150, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_30|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_44|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_26|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_96|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_24, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_31|, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_31|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_131, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_28|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_18|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_312, #valid=|v_#valid_60|, #memory_int=|v_#memory_int_23|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_8|, ULTIMATE.start_main_~#t1512~0.offset=|v_ULTIMATE.start_main_~#t1512~0.offset_14|, ~z~0=v_~z~0_51, ~weak$$choice2~0=v_~weak$$choice2~0_131, ULTIMATE.start_main_~#t1511~0.base=|v_ULTIMATE.start_main_~#t1511~0.base_26|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_407} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_~#t1511~0.offset, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~y$read_delayed~0, ~y$mem_tmp~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, ULTIMATE.start_main_~#t1510~0.base, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_~#t1512~0.base, ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_~#t1510~0.offset, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ULTIMATE.start_main_~#t1512~0.offset, ~z~0, ~weak$$choice2~0, ULTIMATE.start_main_~#t1511~0.base, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:20:47,685 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [715] [715] L800-1-->L802: Formula: (and (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t1511~0.base_13| 4)) (= |v_ULTIMATE.start_main_~#t1511~0.offset_11| 0) (= (select |v_#valid_41| |v_ULTIMATE.start_main_~#t1511~0.base_13|) 0) (= |v_#memory_int_17| (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1511~0.base_13| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1511~0.base_13|) |v_ULTIMATE.start_main_~#t1511~0.offset_11| 1))) (= |v_#valid_40| (store |v_#valid_41| |v_ULTIMATE.start_main_~#t1511~0.base_13| 1)) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1511~0.base_13|) (not (= 0 |v_ULTIMATE.start_main_~#t1511~0.base_13|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_41|, #memory_int=|v_#memory_int_18|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_17|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, ULTIMATE.start_main_~#t1511~0.offset=|v_ULTIMATE.start_main_~#t1511~0.offset_11|, #length=|v_#length_17|, ULTIMATE.start_main_~#t1511~0.base=|v_ULTIMATE.start_main_~#t1511~0.base_13|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_~#t1511~0.offset, #length, ULTIMATE.start_main_~#t1511~0.base] because there is no mapped edge [2019-11-28 18:20:47,686 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L802-1-->L804: Formula: (and (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1512~0.base_12| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1512~0.base_12|) |v_ULTIMATE.start_main_~#t1512~0.offset_10| 2)) |v_#memory_int_15|) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t1512~0.base_12|) (= (select |v_#valid_39| |v_ULTIMATE.start_main_~#t1512~0.base_12|) 0) (= (store |v_#valid_39| |v_ULTIMATE.start_main_~#t1512~0.base_12| 1) |v_#valid_38|) (not (= |v_ULTIMATE.start_main_~#t1512~0.base_12| 0)) (= |v_ULTIMATE.start_main_~#t1512~0.offset_10| 0) (= (store |v_#length_16| |v_ULTIMATE.start_main_~#t1512~0.base_12| 4) |v_#length_15|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_39|, #memory_int=|v_#memory_int_16|, #length=|v_#length_16|} OutVars{ULTIMATE.start_main_~#t1512~0.base=|v_ULTIMATE.start_main_~#t1512~0.base_12|, #StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_38|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, ULTIMATE.start_main_~#t1512~0.offset=|v_ULTIMATE.start_main_~#t1512~0.offset_10|, #length=|v_#length_15|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1512~0.base, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ULTIMATE.start_main_~#t1512~0.offset, #length] because there is no mapped edge [2019-11-28 18:20:47,687 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [641] [641] P2ENTRY-->L4-3: Formula: (and (not (= 0 v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_10)) (= 2 v_~y$w_buff0~0_40) (= v_~y$w_buff0_used~0_161 1) (= v_~y$w_buff0~0_41 v_~y$w_buff1~0_32) (= v_P2Thread1of1ForFork0_~arg.base_6 |v_P2Thread1of1ForFork0_#in~arg.base_8|) (= v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_10 |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|) (= |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6| (ite (not (and (not (= (mod v_~y$w_buff1_used~0_89 256) 0)) (not (= 0 (mod v_~y$w_buff0_used~0_161 256))))) 1 0)) (= v_P2Thread1of1ForFork0_~arg.offset_6 |v_P2Thread1of1ForFork0_#in~arg.offset_8|) (= v_~y$w_buff1_used~0_89 v_~y$w_buff0_used~0_162)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_8|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_162, ~y$w_buff0~0=v_~y$w_buff0~0_41, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_8|} OutVars{P2Thread1of1ForFork0_~arg.base=v_P2Thread1of1ForFork0_~arg.base_6, P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_8|, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_161, ~y$w_buff1~0=v_~y$w_buff1~0_32, ~y$w_buff0~0=v_~y$w_buff0~0_40, P2Thread1of1ForFork0_~arg.offset=v_P2Thread1of1ForFork0_~arg.offset_6, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_8|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_10, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_89} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:20:47,689 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [704] [704] P0ENTRY-->P0EXIT: Formula: (and (= v_~z~0_35 1) (= 0 |v_P0Thread1of1ForFork1_#res.base_9|) (= 0 |v_P0Thread1of1ForFork1_#res.offset_9|) (= |v_P0Thread1of1ForFork1_#in~arg.base_21| v_P0Thread1of1ForFork1_~arg.base_19) (= v_P0Thread1of1ForFork1_~arg.offset_19 |v_P0Thread1of1ForFork1_#in~arg.offset_21|) (= v_~x~0_49 1) (= v_~__unbuffered_cnt~0_67 (+ v_~__unbuffered_cnt~0_68 1))) InVars {P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_21|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_68, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_21|} OutVars{P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_9|, P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_21|, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_9|, P0Thread1of1ForFork1_~arg.offset=v_P0Thread1of1ForFork1_~arg.offset_19, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_67, ~z~0=v_~z~0_35, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_21|, ~x~0=v_~x~0_49, P0Thread1of1ForFork1_~arg.base=v_P0Thread1of1ForFork1_~arg.base_19} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#res.offset, P0Thread1of1ForFork1_#res.base, P0Thread1of1ForFork1_~arg.offset, ~__unbuffered_cnt~0, ~z~0, ~x~0, P0Thread1of1ForFork1_~arg.base] because there is no mapped edge [2019-11-28 18:20:47,690 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [679] [679] L778-->L778-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In963439051 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In963439051 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite11_Out963439051| ~y$w_buff0_used~0_In963439051) (or .cse0 .cse1)) (and (= |P2Thread1of1ForFork0_#t~ite11_Out963439051| 0) (not .cse0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In963439051, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In963439051} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In963439051, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out963439051|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In963439051} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-11-28 18:20:47,691 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [694] [694] L748-2-->L748-4: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff1_used~0_In1378897744 256))) (.cse0 (= 0 (mod ~y$r_buff1_thd2~0_In1378897744 256)))) (or (and (= |P1Thread1of1ForFork2_#t~ite3_Out1378897744| ~y~0_In1378897744) (or .cse0 .cse1)) (and (= |P1Thread1of1ForFork2_#t~ite3_Out1378897744| ~y$w_buff1~0_In1378897744) (not .cse1) (not .cse0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1378897744, ~y$w_buff1~0=~y$w_buff1~0_In1378897744, ~y~0=~y~0_In1378897744, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1378897744} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1378897744, ~y$w_buff1~0=~y$w_buff1~0_In1378897744, ~y~0=~y~0_In1378897744, P1Thread1of1ForFork2_#t~ite3=|P1Thread1of1ForFork2_#t~ite3_Out1378897744|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1378897744} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-11-28 18:20:47,691 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [618] [618] L748-4-->L749: Formula: (= |v_P1Thread1of1ForFork2_#t~ite3_10| v_~y~0_21) InVars {P1Thread1of1ForFork2_#t~ite3=|v_P1Thread1of1ForFork2_#t~ite3_10|} OutVars{P1Thread1of1ForFork2_#t~ite4=|v_P1Thread1of1ForFork2_#t~ite4_11|, ~y~0=v_~y~0_21, P1Thread1of1ForFork2_#t~ite3=|v_P1Thread1of1ForFork2_#t~ite3_9|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite4, ~y~0, P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-11-28 18:20:47,692 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [677] [677] L749-->L749-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In990952532 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In990952532 256)))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork2_#t~ite5_Out990952532| ~y$w_buff0_used~0_In990952532)) (and (not .cse1) (not .cse0) (= |P1Thread1of1ForFork2_#t~ite5_Out990952532| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In990952532, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In990952532} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In990952532, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In990952532, P1Thread1of1ForFork2_#t~ite5=|P1Thread1of1ForFork2_#t~ite5_Out990952532|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-11-28 18:20:47,692 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [689] [689] L750-->L750-2: Formula: (let ((.cse3 (= 0 (mod ~y$w_buff1_used~0_In834809249 256))) (.cse2 (= 0 (mod ~y$r_buff1_thd2~0_In834809249 256))) (.cse1 (= (mod ~y$r_buff0_thd2~0_In834809249 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In834809249 256)))) (or (and (= 0 |P1Thread1of1ForFork2_#t~ite6_Out834809249|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |P1Thread1of1ForFork2_#t~ite6_Out834809249| ~y$w_buff1_used~0_In834809249) (or .cse3 .cse2) (or .cse1 .cse0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In834809249, ~y$w_buff0_used~0=~y$w_buff0_used~0_In834809249, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In834809249, ~y$w_buff1_used~0=~y$w_buff1_used~0_In834809249} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In834809249, ~y$w_buff0_used~0=~y$w_buff0_used~0_In834809249, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In834809249, P1Thread1of1ForFork2_#t~ite6=|P1Thread1of1ForFork2_#t~ite6_Out834809249|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In834809249} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-11-28 18:20:47,693 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [688] [688] L751-->L751-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In858870946 256))) (.cse0 (= (mod ~y$w_buff0_used~0_In858870946 256) 0))) (or (and (= |P1Thread1of1ForFork2_#t~ite7_Out858870946| ~y$r_buff0_thd2~0_In858870946) (or .cse0 .cse1)) (and (not .cse1) (= |P1Thread1of1ForFork2_#t~ite7_Out858870946| 0) (not .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In858870946, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In858870946} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In858870946, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In858870946, P1Thread1of1ForFork2_#t~ite7=|P1Thread1of1ForFork2_#t~ite7_Out858870946|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-11-28 18:20:47,694 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [690] [690] L779-->L779-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff1_thd3~0_In1872928097 256))) (.cse0 (= 0 (mod ~y$w_buff1_used~0_In1872928097 256))) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In1872928097 256))) (.cse3 (= (mod ~y$r_buff0_thd3~0_In1872928097 256) 0))) (or (and (= 0 |P2Thread1of1ForFork0_#t~ite12_Out1872928097|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (= ~y$w_buff1_used~0_In1872928097 |P2Thread1of1ForFork0_#t~ite12_Out1872928097|) (or .cse2 .cse3)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1872928097, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1872928097, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1872928097, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1872928097} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1872928097, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1872928097, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out1872928097|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1872928097, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1872928097} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-11-28 18:20:47,694 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [686] [686] L752-->L752-2: Formula: (let ((.cse3 (= 0 (mod ~y$r_buff0_thd2~0_In525659827 256))) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In525659827 256))) (.cse1 (= (mod ~y$r_buff1_thd2~0_In525659827 256) 0)) (.cse0 (= (mod ~y$w_buff1_used~0_In525659827 256) 0))) (or (and (= ~y$r_buff1_thd2~0_In525659827 |P1Thread1of1ForFork2_#t~ite8_Out525659827|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P1Thread1of1ForFork2_#t~ite8_Out525659827|) (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0)))))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In525659827, ~y$w_buff0_used~0=~y$w_buff0_used~0_In525659827, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In525659827, ~y$w_buff1_used~0=~y$w_buff1_used~0_In525659827} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In525659827, ~y$w_buff0_used~0=~y$w_buff0_used~0_In525659827, P1Thread1of1ForFork2_#t~ite8=|P1Thread1of1ForFork2_#t~ite8_Out525659827|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In525659827, ~y$w_buff1_used~0=~y$w_buff1_used~0_In525659827} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-11-28 18:20:47,694 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L752-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= |v_P1Thread1of1ForFork2_#t~ite8_26| v_~y$r_buff1_thd2~0_56) (= (+ v_~__unbuffered_cnt~0_75 1) v_~__unbuffered_cnt~0_74)) InVars {P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_26|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_75} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_56, P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_25|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_74, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork2_#res.offset, P1Thread1of1ForFork2_#t~ite8, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-11-28 18:20:47,695 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L780-->L781: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In218932195 256) 0)) (.cse1 (= ~y$r_buff0_thd3~0_In218932195 ~y$r_buff0_thd3~0_Out218932195)) (.cse2 (= 0 (mod ~y$r_buff0_thd3~0_In218932195 256)))) (or (and .cse0 .cse1) (and (= ~y$r_buff0_thd3~0_Out218932195 0) (not .cse2) (not .cse0)) (and .cse1 .cse2))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In218932195, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In218932195} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In218932195, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out218932195, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out218932195|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-11-28 18:20:47,695 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [681] [681] L781-->L781-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In-364540095 256) 0)) (.cse1 (= (mod ~y$r_buff0_thd3~0_In-364540095 256) 0)) (.cse2 (= (mod ~y$r_buff1_thd3~0_In-364540095 256) 0)) (.cse3 (= (mod ~y$w_buff1_used~0_In-364540095 256) 0))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork0_#t~ite14_Out-364540095| ~y$r_buff1_thd3~0_In-364540095) (or .cse2 .cse3)) (and (= 0 |P2Thread1of1ForFork0_#t~ite14_Out-364540095|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-364540095, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-364540095, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-364540095, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-364540095} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out-364540095|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-364540095, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-364540095, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-364540095, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-364540095} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-11-28 18:20:47,695 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [722] [722] L781-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#t~ite14_38| v_~y$r_buff1_thd3~0_68) (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0) (= v_~__unbuffered_cnt~0_90 (+ v_~__unbuffered_cnt~0_91 1))) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_38|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_91} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_37|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_68, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_90, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-11-28 18:20:47,695 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [617] [617] L804-1-->L810: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_6 256))) (= v_~main$tmp_guard0~0_6 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_13) 1 0)) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_5|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet17, ~main$tmp_guard0~0] because there is no mapped edge [2019-11-28 18:20:47,696 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L810-2-->L810-4: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff1_used~0_In1312338085 256))) (.cse1 (= 0 (mod ~y$r_buff1_thd0~0_In1312338085 256)))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite18_Out1312338085| ~y~0_In1312338085)) (and (= ~y$w_buff1~0_In1312338085 |ULTIMATE.start_main_#t~ite18_Out1312338085|) (not .cse0) (not .cse1)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In1312338085, ~y~0=~y~0_In1312338085, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1312338085, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1312338085} OutVars{~y$w_buff1~0=~y$w_buff1~0_In1312338085, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out1312338085|, ~y~0=~y~0_In1312338085, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1312338085, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1312338085} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18] because there is no mapped edge [2019-11-28 18:20:47,696 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [636] [636] L810-4-->L811: Formula: (= v_~y~0_40 |v_ULTIMATE.start_main_#t~ite18_13|) InVars {ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_13|} OutVars{ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_12|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_12|, ~y~0=v_~y~0_40} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite19, ~y~0] because there is no mapped edge [2019-11-28 18:20:47,696 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [692] [692] L811-->L811-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In1731600886 256))) (.cse1 (= (mod ~y$r_buff0_thd0~0_In1731600886 256) 0))) (or (and (or .cse0 .cse1) (= ~y$w_buff0_used~0_In1731600886 |ULTIMATE.start_main_#t~ite20_Out1731600886|)) (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite20_Out1731600886|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1731600886, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1731600886} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1731600886, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1731600886, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out1731600886|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-11-28 18:20:47,697 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [678] [678] L812-->L812-2: Formula: (let ((.cse3 (= 0 (mod ~y$w_buff0_used~0_In-569360907 256))) (.cse2 (= 0 (mod ~y$r_buff0_thd0~0_In-569360907 256))) (.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In-569360907 256))) (.cse1 (= (mod ~y$w_buff1_used~0_In-569360907 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |ULTIMATE.start_main_#t~ite21_Out-569360907| 0)) (and (= ~y$w_buff1_used~0_In-569360907 |ULTIMATE.start_main_#t~ite21_Out-569360907|) (or .cse3 .cse2) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-569360907, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-569360907, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-569360907, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-569360907} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-569360907, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-569360907, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out-569360907|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-569360907, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-569360907} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-11-28 18:20:47,698 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [682] [682] L813-->L813-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd0~0_In-1904113297 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1904113297 256)))) (or (and (or .cse0 .cse1) (= ~y$r_buff0_thd0~0_In-1904113297 |ULTIMATE.start_main_#t~ite22_Out-1904113297|)) (and (= |ULTIMATE.start_main_#t~ite22_Out-1904113297| 0) (not .cse0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1904113297, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1904113297} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1904113297, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1904113297, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out-1904113297|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-11-28 18:20:47,698 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [684] [684] L814-->L814-2: Formula: (let ((.cse3 (= (mod ~y$w_buff0_used~0_In1524866939 256) 0)) (.cse2 (= 0 (mod ~y$r_buff0_thd0~0_In1524866939 256))) (.cse1 (= (mod ~y$w_buff1_used~0_In1524866939 256) 0)) (.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In1524866939 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite23_Out1524866939|)) (and (or .cse3 .cse2) (= ~y$r_buff1_thd0~0_In1524866939 |ULTIMATE.start_main_#t~ite23_Out1524866939|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1524866939, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1524866939, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1524866939, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1524866939} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1524866939, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1524866939, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1524866939, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out1524866939|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1524866939} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-11-28 18:20:47,699 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L822-->L822-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In1464932229 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite29_In1464932229| |ULTIMATE.start_main_#t~ite29_Out1464932229|) (= |ULTIMATE.start_main_#t~ite30_Out1464932229| ~y$w_buff0~0_In1464932229) (not .cse0)) (and .cse0 (= |ULTIMATE.start_main_#t~ite29_Out1464932229| ~y$w_buff0~0_In1464932229) (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In1464932229 256) 0))) (or (= (mod ~y$w_buff0_used~0_In1464932229 256) 0) (and .cse1 (= 0 (mod ~y$r_buff1_thd0~0_In1464932229 256))) (and (= (mod ~y$w_buff1_used~0_In1464932229 256) 0) .cse1))) (= |ULTIMATE.start_main_#t~ite29_Out1464932229| |ULTIMATE.start_main_#t~ite30_Out1464932229|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1464932229, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_In1464932229|, ~y$w_buff0~0=~y$w_buff0~0_In1464932229, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1464932229, ~weak$$choice2~0=~weak$$choice2~0_In1464932229, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1464932229, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1464932229} OutVars{ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out1464932229|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1464932229, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out1464932229|, ~y$w_buff0~0=~y$w_buff0~0_In1464932229, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1464932229, ~weak$$choice2~0=~weak$$choice2~0_In1464932229, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1464932229, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1464932229} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-11-28 18:20:47,702 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [631] [631] L826-->L827: Formula: (and (not (= (mod v_~weak$$choice2~0_27 256) 0)) (= v_~y$r_buff0_thd0~0_86 v_~y$r_buff0_thd0~0_85)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_86, ~weak$$choice2~0=v_~weak$$choice2~0_27} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_6|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_10|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_85, ~weak$$choice2~0=v_~weak$$choice2~0_27, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-11-28 18:20:47,703 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [709] [709] L829-->L832-1: Formula: (and (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5| (mod v_~main$tmp_guard1~0_12 256)) (= v_~y~0_109 v_~y$mem_tmp~0_21) (not (= 0 (mod v_~y$flush_delayed~0_33 256))) (= 0 v_~y$flush_delayed~0_32)) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_21, ~y$flush_delayed~0=v_~y$flush_delayed~0_33, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_21, ~y$flush_delayed~0=v_~y$flush_delayed~0_32, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_24|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12, ~y~0=v_~y~0_109, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[~y$flush_delayed~0, ULTIMATE.start_main_#t~ite46, ~y~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-11-28 18:20:47,703 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] L832-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-11-28 18:20:47,851 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 06:20:47 BasicIcfg [2019-11-28 18:20:47,851 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-28 18:20:47,852 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-28 18:20:47,852 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-28 18:20:47,852 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-28 18:20:47,853 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:20:26" (3/4) ... [2019-11-28 18:20:47,857 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-28 18:20:47,858 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [740] [740] ULTIMATE.startENTRY-->L800: Formula: (let ((.cse0 (store |v_#valid_62| 0 0))) (and (= 0 v_~y$read_delayed_var~0.base_6) (= 0 v_~weak$$choice0~0_25) (= 0 v_~y$r_buff0_thd3~0_151) (= v_~y$w_buff1~0_200 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t1510~0.base_26|)) (= v_~y$w_buff0_used~0_650 0) (= v_~__unbuffered_cnt~0_109 0) (< 0 |v_#StackHeapBarrier_16|) (= 0 v_~y$w_buff0~0_308) (= 0 v_~y$r_buff1_thd3~0_122) (= v_~y$read_delayed~0_6 0) (= 0 v_~y$r_buff1_thd1~0_76) (= |v_#valid_60| (store .cse0 |v_ULTIMATE.start_main_~#t1510~0.base_26| 1)) (= (store |v_#length_24| |v_ULTIMATE.start_main_~#t1510~0.base_26| 4) |v_#length_23|) (= v_~z~0_51 0) (= v_~y$r_buff0_thd1~0_29 0) (= v_~main$tmp_guard1~0_28 0) (= v_~y$r_buff0_thd0~0_312 0) (= 0 v_~__unbuffered_p2_EAX~0_90) (= 0 v_~y$flush_delayed~0_45) (= v_~y$w_buff1_used~0_407 0) (= v_~y$r_buff0_thd2~0_88 0) (= (store |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1510~0.base_26| (store (select |v_#memory_int_24| |v_ULTIMATE.start_main_~#t1510~0.base_26|) |v_ULTIMATE.start_main_~#t1510~0.offset_19| 0)) |v_#memory_int_23|) (= |v_#NULL.offset_5| 0) (= 0 v_~y$r_buff1_thd2~0_131) (= v_~y$mem_tmp~0_31 0) (= |v_ULTIMATE.start_main_~#t1510~0.offset_19| 0) (= 0 v_~y$read_delayed_var~0.offset_6) (= v_~y~0_150 0) (= v_~weak$$choice2~0_131 0) (= v_~y$r_buff1_thd0~0_254 0) (< |v_#StackHeapBarrier_16| |v_ULTIMATE.start_main_~#t1510~0.base_26|) (= v_~main$tmp_guard0~0_24 0) (= 0 |v_#NULL.base_5|) (= v_~x~0_80 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_16|, #valid=|v_#valid_62|, #memory_int=|v_#memory_int_24|, #length=|v_#length_24|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_28|, ULTIMATE.start_main_~#t1511~0.offset=|v_ULTIMATE.start_main_~#t1511~0.offset_19|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_26|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_104|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_52|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_26|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_38|, ~y$read_delayed~0=v_~y$read_delayed~0_6, ~y$mem_tmp~0=v_~y$mem_tmp~0_31, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_122, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_29, ~y$flush_delayed~0=v_~y$flush_delayed~0_45, ULTIMATE.start_main_~#t1510~0.base=|v_ULTIMATE.start_main_~#t1510~0.base_26|, #length=|v_#length_23|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_90, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_34|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_142|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_44|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_31|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_98|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_27|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_26|, ~weak$$choice0~0=v_~weak$$choice0~0_25, #StackHeapBarrier=|v_#StackHeapBarrier_16|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_28|, ~y$w_buff1~0=v_~y$w_buff1~0_200, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_6, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_88, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_8|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_22|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_109, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_254, ~x~0=v_~x~0_80, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_6, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_650, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_38|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_31|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_28, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_28|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_32|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_16|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_58|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_50|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_76, ULTIMATE.start_main_~#t1512~0.base=|v_ULTIMATE.start_main_~#t1512~0.base_21|, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_44|, ULTIMATE.start_main_~#t1510~0.offset=|v_ULTIMATE.start_main_~#t1510~0.offset_19|, ~y$w_buff0~0=v_~y$w_buff0~0_308, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_151, ~y~0=v_~y~0_150, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_30|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_44|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_26|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_96|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_24, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_31|, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_31|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_131, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_28|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_18|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_312, #valid=|v_#valid_60|, #memory_int=|v_#memory_int_23|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_8|, ULTIMATE.start_main_~#t1512~0.offset=|v_ULTIMATE.start_main_~#t1512~0.offset_14|, ~z~0=v_~z~0_51, ~weak$$choice2~0=v_~weak$$choice2~0_131, ULTIMATE.start_main_~#t1511~0.base=|v_ULTIMATE.start_main_~#t1511~0.base_26|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_407} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_~#t1511~0.offset, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~y$read_delayed~0, ~y$mem_tmp~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, ULTIMATE.start_main_~#t1510~0.base, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_~#t1512~0.base, ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_~#t1510~0.offset, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ULTIMATE.start_main_~#t1512~0.offset, ~z~0, ~weak$$choice2~0, ULTIMATE.start_main_~#t1511~0.base, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:20:47,859 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [715] [715] L800-1-->L802: Formula: (and (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t1511~0.base_13| 4)) (= |v_ULTIMATE.start_main_~#t1511~0.offset_11| 0) (= (select |v_#valid_41| |v_ULTIMATE.start_main_~#t1511~0.base_13|) 0) (= |v_#memory_int_17| (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1511~0.base_13| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1511~0.base_13|) |v_ULTIMATE.start_main_~#t1511~0.offset_11| 1))) (= |v_#valid_40| (store |v_#valid_41| |v_ULTIMATE.start_main_~#t1511~0.base_13| 1)) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1511~0.base_13|) (not (= 0 |v_ULTIMATE.start_main_~#t1511~0.base_13|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_41|, #memory_int=|v_#memory_int_18|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_17|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, ULTIMATE.start_main_~#t1511~0.offset=|v_ULTIMATE.start_main_~#t1511~0.offset_11|, #length=|v_#length_17|, ULTIMATE.start_main_~#t1511~0.base=|v_ULTIMATE.start_main_~#t1511~0.base_13|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_~#t1511~0.offset, #length, ULTIMATE.start_main_~#t1511~0.base] because there is no mapped edge [2019-11-28 18:20:47,859 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L802-1-->L804: Formula: (and (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1512~0.base_12| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1512~0.base_12|) |v_ULTIMATE.start_main_~#t1512~0.offset_10| 2)) |v_#memory_int_15|) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t1512~0.base_12|) (= (select |v_#valid_39| |v_ULTIMATE.start_main_~#t1512~0.base_12|) 0) (= (store |v_#valid_39| |v_ULTIMATE.start_main_~#t1512~0.base_12| 1) |v_#valid_38|) (not (= |v_ULTIMATE.start_main_~#t1512~0.base_12| 0)) (= |v_ULTIMATE.start_main_~#t1512~0.offset_10| 0) (= (store |v_#length_16| |v_ULTIMATE.start_main_~#t1512~0.base_12| 4) |v_#length_15|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_39|, #memory_int=|v_#memory_int_16|, #length=|v_#length_16|} OutVars{ULTIMATE.start_main_~#t1512~0.base=|v_ULTIMATE.start_main_~#t1512~0.base_12|, #StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_38|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, ULTIMATE.start_main_~#t1512~0.offset=|v_ULTIMATE.start_main_~#t1512~0.offset_10|, #length=|v_#length_15|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t1512~0.base, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ULTIMATE.start_main_~#t1512~0.offset, #length] because there is no mapped edge [2019-11-28 18:20:47,860 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [641] [641] P2ENTRY-->L4-3: Formula: (and (not (= 0 v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_10)) (= 2 v_~y$w_buff0~0_40) (= v_~y$w_buff0_used~0_161 1) (= v_~y$w_buff0~0_41 v_~y$w_buff1~0_32) (= v_P2Thread1of1ForFork0_~arg.base_6 |v_P2Thread1of1ForFork0_#in~arg.base_8|) (= v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_10 |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|) (= |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6| (ite (not (and (not (= (mod v_~y$w_buff1_used~0_89 256) 0)) (not (= 0 (mod v_~y$w_buff0_used~0_161 256))))) 1 0)) (= v_P2Thread1of1ForFork0_~arg.offset_6 |v_P2Thread1of1ForFork0_#in~arg.offset_8|) (= v_~y$w_buff1_used~0_89 v_~y$w_buff0_used~0_162)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_8|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_162, ~y$w_buff0~0=v_~y$w_buff0~0_41, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_8|} OutVars{P2Thread1of1ForFork0_~arg.base=v_P2Thread1of1ForFork0_~arg.base_6, P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_8|, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_161, ~y$w_buff1~0=v_~y$w_buff1~0_32, ~y$w_buff0~0=v_~y$w_buff0~0_40, P2Thread1of1ForFork0_~arg.offset=v_P2Thread1of1ForFork0_~arg.offset_6, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_8|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_10, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_89} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:20:47,861 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [704] [704] P0ENTRY-->P0EXIT: Formula: (and (= v_~z~0_35 1) (= 0 |v_P0Thread1of1ForFork1_#res.base_9|) (= 0 |v_P0Thread1of1ForFork1_#res.offset_9|) (= |v_P0Thread1of1ForFork1_#in~arg.base_21| v_P0Thread1of1ForFork1_~arg.base_19) (= v_P0Thread1of1ForFork1_~arg.offset_19 |v_P0Thread1of1ForFork1_#in~arg.offset_21|) (= v_~x~0_49 1) (= v_~__unbuffered_cnt~0_67 (+ v_~__unbuffered_cnt~0_68 1))) InVars {P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_21|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_68, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_21|} OutVars{P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_9|, P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_21|, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_9|, P0Thread1of1ForFork1_~arg.offset=v_P0Thread1of1ForFork1_~arg.offset_19, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_67, ~z~0=v_~z~0_35, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_21|, ~x~0=v_~x~0_49, P0Thread1of1ForFork1_~arg.base=v_P0Thread1of1ForFork1_~arg.base_19} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#res.offset, P0Thread1of1ForFork1_#res.base, P0Thread1of1ForFork1_~arg.offset, ~__unbuffered_cnt~0, ~z~0, ~x~0, P0Thread1of1ForFork1_~arg.base] because there is no mapped edge [2019-11-28 18:20:47,864 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [679] [679] L778-->L778-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In963439051 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In963439051 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite11_Out963439051| ~y$w_buff0_used~0_In963439051) (or .cse0 .cse1)) (and (= |P2Thread1of1ForFork0_#t~ite11_Out963439051| 0) (not .cse0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In963439051, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In963439051} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In963439051, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out963439051|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In963439051} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-11-28 18:20:47,865 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [694] [694] L748-2-->L748-4: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff1_used~0_In1378897744 256))) (.cse0 (= 0 (mod ~y$r_buff1_thd2~0_In1378897744 256)))) (or (and (= |P1Thread1of1ForFork2_#t~ite3_Out1378897744| ~y~0_In1378897744) (or .cse0 .cse1)) (and (= |P1Thread1of1ForFork2_#t~ite3_Out1378897744| ~y$w_buff1~0_In1378897744) (not .cse1) (not .cse0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1378897744, ~y$w_buff1~0=~y$w_buff1~0_In1378897744, ~y~0=~y~0_In1378897744, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1378897744} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1378897744, ~y$w_buff1~0=~y$w_buff1~0_In1378897744, ~y~0=~y~0_In1378897744, P1Thread1of1ForFork2_#t~ite3=|P1Thread1of1ForFork2_#t~ite3_Out1378897744|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1378897744} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-11-28 18:20:47,865 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [618] [618] L748-4-->L749: Formula: (= |v_P1Thread1of1ForFork2_#t~ite3_10| v_~y~0_21) InVars {P1Thread1of1ForFork2_#t~ite3=|v_P1Thread1of1ForFork2_#t~ite3_10|} OutVars{P1Thread1of1ForFork2_#t~ite4=|v_P1Thread1of1ForFork2_#t~ite4_11|, ~y~0=v_~y~0_21, P1Thread1of1ForFork2_#t~ite3=|v_P1Thread1of1ForFork2_#t~ite3_9|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite4, ~y~0, P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-11-28 18:20:47,866 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [677] [677] L749-->L749-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In990952532 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In990952532 256)))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork2_#t~ite5_Out990952532| ~y$w_buff0_used~0_In990952532)) (and (not .cse1) (not .cse0) (= |P1Thread1of1ForFork2_#t~ite5_Out990952532| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In990952532, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In990952532} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In990952532, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In990952532, P1Thread1of1ForFork2_#t~ite5=|P1Thread1of1ForFork2_#t~ite5_Out990952532|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-11-28 18:20:47,866 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [689] [689] L750-->L750-2: Formula: (let ((.cse3 (= 0 (mod ~y$w_buff1_used~0_In834809249 256))) (.cse2 (= 0 (mod ~y$r_buff1_thd2~0_In834809249 256))) (.cse1 (= (mod ~y$r_buff0_thd2~0_In834809249 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In834809249 256)))) (or (and (= 0 |P1Thread1of1ForFork2_#t~ite6_Out834809249|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |P1Thread1of1ForFork2_#t~ite6_Out834809249| ~y$w_buff1_used~0_In834809249) (or .cse3 .cse2) (or .cse1 .cse0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In834809249, ~y$w_buff0_used~0=~y$w_buff0_used~0_In834809249, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In834809249, ~y$w_buff1_used~0=~y$w_buff1_used~0_In834809249} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In834809249, ~y$w_buff0_used~0=~y$w_buff0_used~0_In834809249, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In834809249, P1Thread1of1ForFork2_#t~ite6=|P1Thread1of1ForFork2_#t~ite6_Out834809249|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In834809249} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-11-28 18:20:47,867 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [688] [688] L751-->L751-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In858870946 256))) (.cse0 (= (mod ~y$w_buff0_used~0_In858870946 256) 0))) (or (and (= |P1Thread1of1ForFork2_#t~ite7_Out858870946| ~y$r_buff0_thd2~0_In858870946) (or .cse0 .cse1)) (and (not .cse1) (= |P1Thread1of1ForFork2_#t~ite7_Out858870946| 0) (not .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In858870946, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In858870946} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In858870946, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In858870946, P1Thread1of1ForFork2_#t~ite7=|P1Thread1of1ForFork2_#t~ite7_Out858870946|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-11-28 18:20:47,868 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [690] [690] L779-->L779-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff1_thd3~0_In1872928097 256))) (.cse0 (= 0 (mod ~y$w_buff1_used~0_In1872928097 256))) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In1872928097 256))) (.cse3 (= (mod ~y$r_buff0_thd3~0_In1872928097 256) 0))) (or (and (= 0 |P2Thread1of1ForFork0_#t~ite12_Out1872928097|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (= ~y$w_buff1_used~0_In1872928097 |P2Thread1of1ForFork0_#t~ite12_Out1872928097|) (or .cse2 .cse3)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1872928097, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1872928097, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1872928097, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1872928097} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1872928097, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1872928097, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out1872928097|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1872928097, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1872928097} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-11-28 18:20:47,868 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [686] [686] L752-->L752-2: Formula: (let ((.cse3 (= 0 (mod ~y$r_buff0_thd2~0_In525659827 256))) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In525659827 256))) (.cse1 (= (mod ~y$r_buff1_thd2~0_In525659827 256) 0)) (.cse0 (= (mod ~y$w_buff1_used~0_In525659827 256) 0))) (or (and (= ~y$r_buff1_thd2~0_In525659827 |P1Thread1of1ForFork2_#t~ite8_Out525659827|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P1Thread1of1ForFork2_#t~ite8_Out525659827|) (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0)))))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In525659827, ~y$w_buff0_used~0=~y$w_buff0_used~0_In525659827, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In525659827, ~y$w_buff1_used~0=~y$w_buff1_used~0_In525659827} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In525659827, ~y$w_buff0_used~0=~y$w_buff0_used~0_In525659827, P1Thread1of1ForFork2_#t~ite8=|P1Thread1of1ForFork2_#t~ite8_Out525659827|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In525659827, ~y$w_buff1_used~0=~y$w_buff1_used~0_In525659827} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-11-28 18:20:47,869 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L752-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= |v_P1Thread1of1ForFork2_#t~ite8_26| v_~y$r_buff1_thd2~0_56) (= (+ v_~__unbuffered_cnt~0_75 1) v_~__unbuffered_cnt~0_74)) InVars {P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_26|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_75} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_56, P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_25|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_74, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork2_#res.offset, P1Thread1of1ForFork2_#t~ite8, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-11-28 18:20:47,869 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L780-->L781: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In218932195 256) 0)) (.cse1 (= ~y$r_buff0_thd3~0_In218932195 ~y$r_buff0_thd3~0_Out218932195)) (.cse2 (= 0 (mod ~y$r_buff0_thd3~0_In218932195 256)))) (or (and .cse0 .cse1) (and (= ~y$r_buff0_thd3~0_Out218932195 0) (not .cse2) (not .cse0)) (and .cse1 .cse2))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In218932195, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In218932195} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In218932195, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out218932195, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out218932195|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-11-28 18:20:47,869 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [681] [681] L781-->L781-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In-364540095 256) 0)) (.cse1 (= (mod ~y$r_buff0_thd3~0_In-364540095 256) 0)) (.cse2 (= (mod ~y$r_buff1_thd3~0_In-364540095 256) 0)) (.cse3 (= (mod ~y$w_buff1_used~0_In-364540095 256) 0))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork0_#t~ite14_Out-364540095| ~y$r_buff1_thd3~0_In-364540095) (or .cse2 .cse3)) (and (= 0 |P2Thread1of1ForFork0_#t~ite14_Out-364540095|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-364540095, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-364540095, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-364540095, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-364540095} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out-364540095|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-364540095, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-364540095, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-364540095, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-364540095} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-11-28 18:20:47,870 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [722] [722] L781-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#t~ite14_38| v_~y$r_buff1_thd3~0_68) (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0) (= v_~__unbuffered_cnt~0_90 (+ v_~__unbuffered_cnt~0_91 1))) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_38|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_91} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_37|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_68, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_90, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-11-28 18:20:47,870 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [617] [617] L804-1-->L810: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_6 256))) (= v_~main$tmp_guard0~0_6 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_13) 1 0)) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_5|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet17, ~main$tmp_guard0~0] because there is no mapped edge [2019-11-28 18:20:47,870 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L810-2-->L810-4: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff1_used~0_In1312338085 256))) (.cse1 (= 0 (mod ~y$r_buff1_thd0~0_In1312338085 256)))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite18_Out1312338085| ~y~0_In1312338085)) (and (= ~y$w_buff1~0_In1312338085 |ULTIMATE.start_main_#t~ite18_Out1312338085|) (not .cse0) (not .cse1)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In1312338085, ~y~0=~y~0_In1312338085, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1312338085, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1312338085} OutVars{~y$w_buff1~0=~y$w_buff1~0_In1312338085, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out1312338085|, ~y~0=~y~0_In1312338085, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1312338085, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1312338085} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18] because there is no mapped edge [2019-11-28 18:20:47,871 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [636] [636] L810-4-->L811: Formula: (= v_~y~0_40 |v_ULTIMATE.start_main_#t~ite18_13|) InVars {ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_13|} OutVars{ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_12|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_12|, ~y~0=v_~y~0_40} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite19, ~y~0] because there is no mapped edge [2019-11-28 18:20:47,871 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [692] [692] L811-->L811-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In1731600886 256))) (.cse1 (= (mod ~y$r_buff0_thd0~0_In1731600886 256) 0))) (or (and (or .cse0 .cse1) (= ~y$w_buff0_used~0_In1731600886 |ULTIMATE.start_main_#t~ite20_Out1731600886|)) (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite20_Out1731600886|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1731600886, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1731600886} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1731600886, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1731600886, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out1731600886|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-11-28 18:20:47,871 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [678] [678] L812-->L812-2: Formula: (let ((.cse3 (= 0 (mod ~y$w_buff0_used~0_In-569360907 256))) (.cse2 (= 0 (mod ~y$r_buff0_thd0~0_In-569360907 256))) (.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In-569360907 256))) (.cse1 (= (mod ~y$w_buff1_used~0_In-569360907 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |ULTIMATE.start_main_#t~ite21_Out-569360907| 0)) (and (= ~y$w_buff1_used~0_In-569360907 |ULTIMATE.start_main_#t~ite21_Out-569360907|) (or .cse3 .cse2) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-569360907, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-569360907, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-569360907, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-569360907} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-569360907, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-569360907, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out-569360907|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-569360907, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-569360907} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-11-28 18:20:47,872 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [682] [682] L813-->L813-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd0~0_In-1904113297 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1904113297 256)))) (or (and (or .cse0 .cse1) (= ~y$r_buff0_thd0~0_In-1904113297 |ULTIMATE.start_main_#t~ite22_Out-1904113297|)) (and (= |ULTIMATE.start_main_#t~ite22_Out-1904113297| 0) (not .cse0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1904113297, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1904113297} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1904113297, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1904113297, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out-1904113297|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-11-28 18:20:47,873 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [684] [684] L814-->L814-2: Formula: (let ((.cse3 (= (mod ~y$w_buff0_used~0_In1524866939 256) 0)) (.cse2 (= 0 (mod ~y$r_buff0_thd0~0_In1524866939 256))) (.cse1 (= (mod ~y$w_buff1_used~0_In1524866939 256) 0)) (.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In1524866939 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite23_Out1524866939|)) (and (or .cse3 .cse2) (= ~y$r_buff1_thd0~0_In1524866939 |ULTIMATE.start_main_#t~ite23_Out1524866939|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1524866939, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1524866939, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1524866939, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1524866939} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1524866939, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1524866939, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1524866939, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out1524866939|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1524866939} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-11-28 18:20:47,874 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L822-->L822-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In1464932229 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite29_In1464932229| |ULTIMATE.start_main_#t~ite29_Out1464932229|) (= |ULTIMATE.start_main_#t~ite30_Out1464932229| ~y$w_buff0~0_In1464932229) (not .cse0)) (and .cse0 (= |ULTIMATE.start_main_#t~ite29_Out1464932229| ~y$w_buff0~0_In1464932229) (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In1464932229 256) 0))) (or (= (mod ~y$w_buff0_used~0_In1464932229 256) 0) (and .cse1 (= 0 (mod ~y$r_buff1_thd0~0_In1464932229 256))) (and (= (mod ~y$w_buff1_used~0_In1464932229 256) 0) .cse1))) (= |ULTIMATE.start_main_#t~ite29_Out1464932229| |ULTIMATE.start_main_#t~ite30_Out1464932229|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1464932229, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_In1464932229|, ~y$w_buff0~0=~y$w_buff0~0_In1464932229, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1464932229, ~weak$$choice2~0=~weak$$choice2~0_In1464932229, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1464932229, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1464932229} OutVars{ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out1464932229|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1464932229, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out1464932229|, ~y$w_buff0~0=~y$w_buff0~0_In1464932229, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1464932229, ~weak$$choice2~0=~weak$$choice2~0_In1464932229, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1464932229, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1464932229} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-11-28 18:20:47,877 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [631] [631] L826-->L827: Formula: (and (not (= (mod v_~weak$$choice2~0_27 256) 0)) (= v_~y$r_buff0_thd0~0_86 v_~y$r_buff0_thd0~0_85)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_86, ~weak$$choice2~0=v_~weak$$choice2~0_27} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_6|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_10|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_85, ~weak$$choice2~0=v_~weak$$choice2~0_27, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-11-28 18:20:47,879 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [709] [709] L829-->L832-1: Formula: (and (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5| (mod v_~main$tmp_guard1~0_12 256)) (= v_~y~0_109 v_~y$mem_tmp~0_21) (not (= 0 (mod v_~y$flush_delayed~0_33 256))) (= 0 v_~y$flush_delayed~0_32)) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_21, ~y$flush_delayed~0=v_~y$flush_delayed~0_33, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_21, ~y$flush_delayed~0=v_~y$flush_delayed~0_32, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_24|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12, ~y~0=v_~y~0_109, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[~y$flush_delayed~0, ULTIMATE.start_main_#t~ite46, ~y~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-11-28 18:20:47,879 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] L832-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-11-28 18:20:48,041 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2019-11-28 18:20:48,044 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-28 18:20:48,046 INFO L168 Benchmark]: Toolchain (without parser) took 23068.24 ms. Allocated memory was 1.0 GB in the beginning and 2.1 GB in the end (delta: 1.1 GB). Free memory was 952.3 MB in the beginning and 1.4 GB in the end (delta: -408.2 MB). Peak memory consumption was 681.8 MB. Max. memory is 11.5 GB. [2019-11-28 18:20:48,049 INFO L168 Benchmark]: CDTParser took 0.32 ms. Allocated memory is still 1.0 GB. Free memory is still 987.2 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 18:20:48,050 INFO L168 Benchmark]: CACSL2BoogieTranslator took 909.87 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 130.5 MB). Free memory was 952.3 MB in the beginning and 1.1 GB in the end (delta: -140.6 MB). Peak memory consumption was 26.1 MB. Max. memory is 11.5 GB. [2019-11-28 18:20:48,050 INFO L168 Benchmark]: Boogie Procedure Inliner took 122.21 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. [2019-11-28 18:20:48,050 INFO L168 Benchmark]: Boogie Preprocessor took 59.46 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 18:20:48,051 INFO L168 Benchmark]: RCFGBuilder took 893.13 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 51.6 MB). Peak memory consumption was 51.6 MB. Max. memory is 11.5 GB. [2019-11-28 18:20:48,054 INFO L168 Benchmark]: TraceAbstraction took 20884.94 ms. Allocated memory was 1.2 GB in the beginning and 2.1 GB in the end (delta: 959.4 MB). Free memory was 1.0 GB in the beginning and 1.4 GB in the end (delta: -346.1 MB). Peak memory consumption was 613.4 MB. Max. memory is 11.5 GB. [2019-11-28 18:20:48,055 INFO L168 Benchmark]: Witness Printer took 192.25 ms. Allocated memory is still 2.1 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 20.1 MB). Peak memory consumption was 20.1 MB. Max. memory is 11.5 GB. [2019-11-28 18:20:48,057 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.32 ms. Allocated memory is still 1.0 GB. Free memory is still 987.2 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 909.87 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 130.5 MB). Free memory was 952.3 MB in the beginning and 1.1 GB in the end (delta: -140.6 MB). Peak memory consumption was 26.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 122.21 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 59.46 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 893.13 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 51.6 MB). Peak memory consumption was 51.6 MB. Max. memory is 11.5 GB. * TraceAbstraction took 20884.94 ms. Allocated memory was 1.2 GB in the beginning and 2.1 GB in the end (delta: 959.4 MB). Free memory was 1.0 GB in the beginning and 1.4 GB in the end (delta: -346.1 MB). Peak memory consumption was 613.4 MB. Max. memory is 11.5 GB. * Witness Printer took 192.25 ms. Allocated memory is still 2.1 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 20.1 MB). Peak memory consumption was 20.1 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 5.3s, 162 ProgramPointsBefore, 83 ProgramPointsAfterwards, 193 TransitionsBefore, 92 TransitionsAfterwards, 11490 CoEnabledTransitionPairs, 7 FixpointIterations, 31 TrivialSequentialCompositions, 44 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 34 ConcurrentYvCompositions, 26 ChoiceCompositions, 3955 VarBasedMoverChecksPositive, 193 VarBasedMoverChecksNegative, 45 SemBasedMoverChecksPositive, 196 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 1.4s, 0 MoverChecksTotal, 48383 CheckedPairsTotal, 109 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L800] FCALL, FORK 0 pthread_create(&t1510, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L802] FCALL, FORK 0 pthread_create(&t1511, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L804] FCALL, FORK 0 pthread_create(&t1512, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L767] 3 y$r_buff1_thd0 = y$r_buff0_thd0 [L768] 3 y$r_buff1_thd1 = y$r_buff0_thd1 [L769] 3 y$r_buff1_thd2 = y$r_buff0_thd2 [L770] 3 y$r_buff1_thd3 = y$r_buff0_thd3 [L771] 3 y$r_buff0_thd3 = (_Bool)1 [L774] 3 __unbuffered_p2_EAX = z VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=0] [L777] EXPR 3 y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L742] 2 x = 2 [L745] 2 y = 1 VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L777] 3 y = y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) [L748] 2 y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L749] 2 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$w_buff0_used [L750] 2 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used [L751] 2 y$r_buff0_thd2 = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$r_buff0_thd2 [L778] 3 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : y$w_buff0_used [L779] 3 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd3 || y$w_buff1_used && y$r_buff1_thd3 ? (_Bool)0 : y$w_buff1_used [L810] 0 y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L811] 0 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used [L812] 0 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$w_buff1_used [L813] 0 y$r_buff0_thd0 = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$r_buff0_thd0 [L814] 0 y$r_buff1_thd0 = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$r_buff1_thd0 [L817] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L818] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L819] 0 y$flush_delayed = weak$$choice2 [L820] 0 y$mem_tmp = y VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L821] EXPR 0 !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L821] 0 y = !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) [L822] 0 y$w_buff0 = weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) [L823] EXPR 0 weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L823] 0 y$w_buff1 = weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) [L824] EXPR 0 weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L824] 0 y$w_buff0_used = weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) [L825] EXPR 0 weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L825] 0 y$w_buff1_used = weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L827] EXPR 0 weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L827] 0 y$r_buff1_thd0 = weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L828] 0 main$tmp_guard1 = !(x == 2 && y == 2 && __unbuffered_p2_EAX == 0) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 153 locations, 2 error locations. Result: UNSAFE, OverallTime: 20.5s, OverallIterations: 16, TraceHistogramMax: 1, AutomataDifference: 4.9s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 1588 SDtfs, 1636 SDslu, 3714 SDs, 0 SdLazy, 1835 SolverSat, 136 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.7s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 123 GetRequests, 15 SyntacticMatches, 6 SemanticMatches, 102 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 241 ImplicationChecksByTransitivity, 1.4s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=28190occurred in iteration=5, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 5.5s AutomataMinimizationTime, 15 MinimizatonAttempts, 16314 StatesRemovedByMinimization, 9 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.4s SatisfiabilityAnalysisTime, 1.9s InterpolantComputationTime, 624 NumberOfCodeBlocks, 624 NumberOfCodeBlocksAsserted, 16 NumberOfCheckSat, 552 ConstructedInterpolants, 0 QuantifiedInterpolants, 115151 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 15 InterpolantComputations, 15 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...