./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/pthread-wmm/mix057_power.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx12G -Xms1G -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/pthread-wmm/mix057_power.opt.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 41b89180b23bede5465d1065a3c6e37c030463b4 ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-11-28 18:20:26,293 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-28 18:20:26,296 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-28 18:20:26,314 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-28 18:20:26,314 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-28 18:20:26,316 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-28 18:20:26,318 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-28 18:20:26,327 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-28 18:20:26,329 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-28 18:20:26,330 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-28 18:20:26,332 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-28 18:20:26,333 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-28 18:20:26,333 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-28 18:20:26,334 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-28 18:20:26,335 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-28 18:20:26,337 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-28 18:20:26,337 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-28 18:20:26,340 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-28 18:20:26,342 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-28 18:20:26,348 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-28 18:20:26,350 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-28 18:20:26,351 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-28 18:20:26,352 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-28 18:20:26,353 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-28 18:20:26,355 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-28 18:20:26,356 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-28 18:20:26,356 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-28 18:20:26,357 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-28 18:20:26,358 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-28 18:20:26,359 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-28 18:20:26,360 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-28 18:20:26,361 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-28 18:20:26,362 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-28 18:20:26,363 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-28 18:20:26,364 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-28 18:20:26,366 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-28 18:20:26,366 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-28 18:20:26,367 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-28 18:20:26,367 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-28 18:20:26,368 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-28 18:20:26,373 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-28 18:20:26,375 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-28 18:20:26,394 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-28 18:20:26,394 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-28 18:20:26,395 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-28 18:20:26,402 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-28 18:20:26,402 INFO L138 SettingsManager]: * Use SBE=true [2019-11-28 18:20:26,402 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-28 18:20:26,403 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-28 18:20:26,403 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-28 18:20:26,403 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-28 18:20:26,403 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-28 18:20:26,404 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-28 18:20:26,404 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-28 18:20:26,404 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-28 18:20:26,405 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-28 18:20:26,405 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-28 18:20:26,405 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-28 18:20:26,405 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-28 18:20:26,406 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-28 18:20:26,406 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-28 18:20:26,406 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-28 18:20:26,407 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-28 18:20:26,407 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 18:20:26,407 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-28 18:20:26,408 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-28 18:20:26,408 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-28 18:20:26,408 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-28 18:20:26,408 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-28 18:20:26,409 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-28 18:20:26,409 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-11-28 18:20:26,409 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 41b89180b23bede5465d1065a3c6e37c030463b4 [2019-11-28 18:20:26,719 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-28 18:20:26,732 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-28 18:20:26,736 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-28 18:20:26,737 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-28 18:20:26,738 INFO L275 PluginConnector]: CDTParser initialized [2019-11-28 18:20:26,738 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/pthread-wmm/mix057_power.opt.i [2019-11-28 18:20:26,796 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4f18e59aa/2bb18ed5c6584d81a5a46b9c35022c44/FLAG457dcf8b8 [2019-11-28 18:20:27,341 INFO L306 CDTParser]: Found 1 translation units. [2019-11-28 18:20:27,344 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/pthread-wmm/mix057_power.opt.i [2019-11-28 18:20:27,359 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4f18e59aa/2bb18ed5c6584d81a5a46b9c35022c44/FLAG457dcf8b8 [2019-11-28 18:20:27,572 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4f18e59aa/2bb18ed5c6584d81a5a46b9c35022c44 [2019-11-28 18:20:27,576 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-28 18:20:27,578 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-28 18:20:27,579 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-28 18:20:27,579 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-28 18:20:27,582 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-28 18:20:27,583 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 06:20:27" (1/1) ... [2019-11-28 18:20:27,586 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@46c20c6c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:27, skipping insertion in model container [2019-11-28 18:20:27,587 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 06:20:27" (1/1) ... [2019-11-28 18:20:27,595 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-11-28 18:20:27,654 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-11-28 18:20:28,132 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 18:20:28,153 INFO L203 MainTranslator]: Completed pre-run [2019-11-28 18:20:28,235 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 18:20:28,312 INFO L208 MainTranslator]: Completed translation [2019-11-28 18:20:28,313 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:28 WrapperNode [2019-11-28 18:20:28,313 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-28 18:20:28,314 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-28 18:20:28,315 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-28 18:20:28,315 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-28 18:20:28,324 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:28" (1/1) ... [2019-11-28 18:20:28,351 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:28" (1/1) ... [2019-11-28 18:20:28,399 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-28 18:20:28,400 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-28 18:20:28,400 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-28 18:20:28,400 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-28 18:20:28,410 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:28" (1/1) ... [2019-11-28 18:20:28,410 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:28" (1/1) ... [2019-11-28 18:20:28,415 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:28" (1/1) ... [2019-11-28 18:20:28,415 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:28" (1/1) ... [2019-11-28 18:20:28,426 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:28" (1/1) ... [2019-11-28 18:20:28,430 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:28" (1/1) ... [2019-11-28 18:20:28,434 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:28" (1/1) ... [2019-11-28 18:20:28,439 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-28 18:20:28,440 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-28 18:20:28,440 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-28 18:20:28,440 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-28 18:20:28,441 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:28" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 18:20:28,519 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-11-28 18:20:28,519 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-11-28 18:20:28,519 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-11-28 18:20:28,520 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-11-28 18:20:28,521 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-11-28 18:20:28,521 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-11-28 18:20:28,521 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-11-28 18:20:28,521 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-11-28 18:20:28,522 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-11-28 18:20:28,522 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-11-28 18:20:28,523 INFO L130 BoogieDeclarations]: Found specification of procedure P3 [2019-11-28 18:20:28,523 INFO L138 BoogieDeclarations]: Found implementation of procedure P3 [2019-11-28 18:20:28,523 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-11-28 18:20:28,523 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-28 18:20:28,524 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-28 18:20:28,526 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-11-28 18:20:29,308 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-28 18:20:29,309 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-11-28 18:20:29,312 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:20:29 BoogieIcfgContainer [2019-11-28 18:20:29,312 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-28 18:20:29,313 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-28 18:20:29,314 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-28 18:20:29,319 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-28 18:20:29,319 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 06:20:27" (1/3) ... [2019-11-28 18:20:29,320 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@70fc7d08 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 06:20:29, skipping insertion in model container [2019-11-28 18:20:29,321 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:20:28" (2/3) ... [2019-11-28 18:20:29,321 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@70fc7d08 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 06:20:29, skipping insertion in model container [2019-11-28 18:20:29,322 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:20:29" (3/3) ... [2019-11-28 18:20:29,325 INFO L109 eAbstractionObserver]: Analyzing ICFG mix057_power.opt.i [2019-11-28 18:20:29,337 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-11-28 18:20:29,338 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-28 18:20:29,352 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-11-28 18:20:29,353 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-11-28 18:20:29,419 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork3_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,420 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork3_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,420 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork3_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,421 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork3_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,421 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork3_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,421 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork3_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,422 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,423 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,423 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,423 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,423 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,424 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,425 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,425 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,425 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,425 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,426 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,426 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,426 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,427 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,427 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,427 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,428 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,429 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,429 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,429 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,430 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,430 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,430 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,431 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,431 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,431 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,432 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,432 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,433 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,433 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,433 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,434 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,435 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,435 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,435 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,435 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,438 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,439 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,439 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,439 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,439 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork2___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,439 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,440 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork2___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,440 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork2___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,441 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,441 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,441 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,441 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,442 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,442 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,442 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,442 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,443 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,443 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,443 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,443 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,443 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,444 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,444 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,445 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,445 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,445 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,445 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,446 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,446 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,446 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,446 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,447 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,447 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,447 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:20:29,471 INFO L249 AbstractCegarLoop]: Starting to check reachability of 7 error locations. [2019-11-28 18:20:29,488 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-28 18:20:29,488 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-28 18:20:29,488 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-28 18:20:29,488 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-28 18:20:29,488 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-28 18:20:29,489 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-28 18:20:29,489 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-28 18:20:29,489 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-28 18:20:29,507 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 178 places, 206 transitions [2019-11-28 18:20:29,510 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 178 places, 206 transitions [2019-11-28 18:20:29,636 INFO L134 PetriNetUnfolder]: 41/202 cut-off events. [2019-11-28 18:20:29,637 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-11-28 18:20:29,659 INFO L76 FinitePrefix]: Finished finitePrefix Result has 215 conditions, 202 events. 41/202 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 8. Compared 483 event pairs. 12/171 useless extension candidates. Maximal degree in co-relation 172. Up to 2 conditions per place. [2019-11-28 18:20:29,683 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 178 places, 206 transitions [2019-11-28 18:20:29,766 INFO L134 PetriNetUnfolder]: 41/202 cut-off events. [2019-11-28 18:20:29,766 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-11-28 18:20:29,777 INFO L76 FinitePrefix]: Finished finitePrefix Result has 215 conditions, 202 events. 41/202 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 8. Compared 483 event pairs. 12/171 useless extension candidates. Maximal degree in co-relation 172. Up to 2 conditions per place. [2019-11-28 18:20:29,799 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 12668 [2019-11-28 18:20:29,800 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-11-28 18:20:35,047 WARN L192 SmtUtils]: Spent 273.00 ms on a formula simplification. DAG size of input: 93 DAG size of output: 91 [2019-11-28 18:20:35,181 WARN L192 SmtUtils]: Spent 131.00 ms on a formula simplification that was a NOOP. DAG size: 89 [2019-11-28 18:20:35,206 INFO L206 etLargeBlockEncoding]: Checked pairs total: 56276 [2019-11-28 18:20:35,206 INFO L214 etLargeBlockEncoding]: Total number of compositions: 119 [2019-11-28 18:20:35,210 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 91 places, 100 transitions [2019-11-28 18:20:38,314 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 32878 states. [2019-11-28 18:20:38,315 INFO L276 IsEmpty]: Start isEmpty. Operand 32878 states. [2019-11-28 18:20:38,323 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 10 [2019-11-28 18:20:38,323 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:38,324 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:38,325 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:38,330 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:38,330 INFO L82 PathProgramCache]: Analyzing trace with hash -667351009, now seen corresponding path program 1 times [2019-11-28 18:20:38,337 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:38,338 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1889807180] [2019-11-28 18:20:38,338 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:38,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:38,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:38,629 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1889807180] [2019-11-28 18:20:38,630 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:38,630 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-11-28 18:20:38,631 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [228468238] [2019-11-28 18:20:38,636 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:20:38,637 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:38,652 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:20:38,653 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:38,656 INFO L87 Difference]: Start difference. First operand 32878 states. Second operand 3 states. [2019-11-28 18:20:39,439 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:39,439 INFO L93 Difference]: Finished difference Result 32686 states and 139960 transitions. [2019-11-28 18:20:39,440 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:20:39,441 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 9 [2019-11-28 18:20:39,442 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:39,746 INFO L225 Difference]: With dead ends: 32686 [2019-11-28 18:20:39,746 INFO L226 Difference]: Without dead ends: 32062 [2019-11-28 18:20:39,750 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:40,169 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32062 states. [2019-11-28 18:20:41,062 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32062 to 32062. [2019-11-28 18:20:41,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32062 states. [2019-11-28 18:20:41,833 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32062 states to 32062 states and 137412 transitions. [2019-11-28 18:20:41,835 INFO L78 Accepts]: Start accepts. Automaton has 32062 states and 137412 transitions. Word has length 9 [2019-11-28 18:20:41,836 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:41,836 INFO L462 AbstractCegarLoop]: Abstraction has 32062 states and 137412 transitions. [2019-11-28 18:20:41,836 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:20:41,837 INFO L276 IsEmpty]: Start isEmpty. Operand 32062 states and 137412 transitions. [2019-11-28 18:20:41,851 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-11-28 18:20:41,851 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:41,851 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:41,852 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:41,852 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:41,852 INFO L82 PathProgramCache]: Analyzing trace with hash -139405083, now seen corresponding path program 1 times [2019-11-28 18:20:41,853 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:41,853 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [585230028] [2019-11-28 18:20:41,853 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:41,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:41,997 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:41,999 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [585230028] [2019-11-28 18:20:41,999 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:41,999 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:20:42,000 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2068486029] [2019-11-28 18:20:42,001 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:20:42,002 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:42,002 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:20:42,002 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:20:42,002 INFO L87 Difference]: Start difference. First operand 32062 states and 137412 transitions. Second operand 4 states. [2019-11-28 18:20:42,621 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:42,621 INFO L93 Difference]: Finished difference Result 51166 states and 211740 transitions. [2019-11-28 18:20:42,622 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:20:42,622 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-11-28 18:20:42,622 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:42,864 INFO L225 Difference]: With dead ends: 51166 [2019-11-28 18:20:42,865 INFO L226 Difference]: Without dead ends: 51138 [2019-11-28 18:20:42,865 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:20:43,269 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51138 states. [2019-11-28 18:20:45,001 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51138 to 46670. [2019-11-28 18:20:45,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46670 states. [2019-11-28 18:20:45,230 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46670 states to 46670 states and 195108 transitions. [2019-11-28 18:20:45,230 INFO L78 Accepts]: Start accepts. Automaton has 46670 states and 195108 transitions. Word has length 15 [2019-11-28 18:20:45,231 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:45,231 INFO L462 AbstractCegarLoop]: Abstraction has 46670 states and 195108 transitions. [2019-11-28 18:20:45,231 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:20:45,232 INFO L276 IsEmpty]: Start isEmpty. Operand 46670 states and 195108 transitions. [2019-11-28 18:20:45,235 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-11-28 18:20:45,236 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:45,236 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:45,237 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:45,237 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:45,238 INFO L82 PathProgramCache]: Analyzing trace with hash 2113277815, now seen corresponding path program 1 times [2019-11-28 18:20:45,238 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:45,238 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1826166932] [2019-11-28 18:20:45,239 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:45,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:45,382 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:45,383 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1826166932] [2019-11-28 18:20:45,383 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:45,383 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:20:45,384 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1327201621] [2019-11-28 18:20:45,384 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:20:45,384 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:45,384 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:20:45,385 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:20:45,385 INFO L87 Difference]: Start difference. First operand 46670 states and 195108 transitions. Second operand 4 states. [2019-11-28 18:20:45,861 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:45,862 INFO L93 Difference]: Finished difference Result 57898 states and 240332 transitions. [2019-11-28 18:20:45,862 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:20:45,862 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-11-28 18:20:45,862 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:46,078 INFO L225 Difference]: With dead ends: 57898 [2019-11-28 18:20:46,079 INFO L226 Difference]: Without dead ends: 57898 [2019-11-28 18:20:46,079 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:20:46,437 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57898 states. [2019-11-28 18:20:48,332 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57898 to 51310. [2019-11-28 18:20:48,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51310 states. [2019-11-28 18:20:48,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51310 states to 51310 states and 214288 transitions. [2019-11-28 18:20:48,528 INFO L78 Accepts]: Start accepts. Automaton has 51310 states and 214288 transitions. Word has length 15 [2019-11-28 18:20:48,528 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:48,528 INFO L462 AbstractCegarLoop]: Abstraction has 51310 states and 214288 transitions. [2019-11-28 18:20:48,528 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:20:48,528 INFO L276 IsEmpty]: Start isEmpty. Operand 51310 states and 214288 transitions. [2019-11-28 18:20:48,541 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-11-28 18:20:48,541 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:48,541 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:48,541 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:48,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:48,542 INFO L82 PathProgramCache]: Analyzing trace with hash -942234691, now seen corresponding path program 1 times [2019-11-28 18:20:48,542 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:48,542 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [133495508] [2019-11-28 18:20:48,543 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:48,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:48,689 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:48,690 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [133495508] [2019-11-28 18:20:48,690 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:48,690 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:20:48,691 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1796572953] [2019-11-28 18:20:48,691 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:20:48,691 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:48,691 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:20:48,692 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:20:48,692 INFO L87 Difference]: Start difference. First operand 51310 states and 214288 transitions. Second operand 5 states. [2019-11-28 18:20:49,506 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:49,506 INFO L93 Difference]: Finished difference Result 69354 states and 284756 transitions. [2019-11-28 18:20:49,506 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-11-28 18:20:49,507 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 21 [2019-11-28 18:20:49,507 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:49,735 INFO L225 Difference]: With dead ends: 69354 [2019-11-28 18:20:49,735 INFO L226 Difference]: Without dead ends: 69326 [2019-11-28 18:20:49,736 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-11-28 18:20:51,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69326 states. [2019-11-28 18:20:51,808 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69326 to 51342. [2019-11-28 18:20:51,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51342 states. [2019-11-28 18:20:51,974 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51342 states to 51342 states and 213896 transitions. [2019-11-28 18:20:51,974 INFO L78 Accepts]: Start accepts. Automaton has 51342 states and 213896 transitions. Word has length 21 [2019-11-28 18:20:51,975 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:51,975 INFO L462 AbstractCegarLoop]: Abstraction has 51342 states and 213896 transitions. [2019-11-28 18:20:51,975 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:20:51,975 INFO L276 IsEmpty]: Start isEmpty. Operand 51342 states and 213896 transitions. [2019-11-28 18:20:52,017 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-11-28 18:20:52,018 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:52,018 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:52,018 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:52,018 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:52,018 INFO L82 PathProgramCache]: Analyzing trace with hash 1902768364, now seen corresponding path program 1 times [2019-11-28 18:20:52,019 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:52,019 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1896955739] [2019-11-28 18:20:52,019 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:52,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:52,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:52,075 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1896955739] [2019-11-28 18:20:52,076 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:52,076 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:20:52,076 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [377374967] [2019-11-28 18:20:52,076 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:20:52,077 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:52,077 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:20:52,077 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:52,077 INFO L87 Difference]: Start difference. First operand 51342 states and 213896 transitions. Second operand 3 states. [2019-11-28 18:20:52,277 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:52,278 INFO L93 Difference]: Finished difference Result 40388 states and 155545 transitions. [2019-11-28 18:20:52,278 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:20:52,278 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 29 [2019-11-28 18:20:52,279 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:52,387 INFO L225 Difference]: With dead ends: 40388 [2019-11-28 18:20:52,387 INFO L226 Difference]: Without dead ends: 40388 [2019-11-28 18:20:52,387 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:52,593 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40388 states. [2019-11-28 18:20:53,794 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40388 to 40388. [2019-11-28 18:20:53,795 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40388 states. [2019-11-28 18:20:53,928 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40388 states to 40388 states and 155545 transitions. [2019-11-28 18:20:53,929 INFO L78 Accepts]: Start accepts. Automaton has 40388 states and 155545 transitions. Word has length 29 [2019-11-28 18:20:53,929 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:53,929 INFO L462 AbstractCegarLoop]: Abstraction has 40388 states and 155545 transitions. [2019-11-28 18:20:53,929 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:20:53,929 INFO L276 IsEmpty]: Start isEmpty. Operand 40388 states and 155545 transitions. [2019-11-28 18:20:53,959 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2019-11-28 18:20:53,959 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:53,959 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:53,959 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:53,960 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:53,960 INFO L82 PathProgramCache]: Analyzing trace with hash 847829435, now seen corresponding path program 1 times [2019-11-28 18:20:53,960 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:53,960 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1293985957] [2019-11-28 18:20:53,960 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:53,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:54,026 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:54,027 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1293985957] [2019-11-28 18:20:54,027 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:54,027 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:20:54,027 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [535438488] [2019-11-28 18:20:54,028 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:20:54,028 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:54,028 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:20:54,028 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:20:54,029 INFO L87 Difference]: Start difference. First operand 40388 states and 155545 transitions. Second operand 4 states. [2019-11-28 18:20:54,131 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:54,131 INFO L93 Difference]: Finished difference Result 16956 states and 54151 transitions. [2019-11-28 18:20:54,131 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-28 18:20:54,131 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 30 [2019-11-28 18:20:54,132 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:54,162 INFO L225 Difference]: With dead ends: 16956 [2019-11-28 18:20:54,162 INFO L226 Difference]: Without dead ends: 16956 [2019-11-28 18:20:54,164 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:20:54,233 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16956 states. [2019-11-28 18:20:54,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16956 to 16956. [2019-11-28 18:20:54,403 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16956 states. [2019-11-28 18:20:54,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16956 states to 16956 states and 54151 transitions. [2019-11-28 18:20:54,441 INFO L78 Accepts]: Start accepts. Automaton has 16956 states and 54151 transitions. Word has length 30 [2019-11-28 18:20:54,441 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:54,441 INFO L462 AbstractCegarLoop]: Abstraction has 16956 states and 54151 transitions. [2019-11-28 18:20:54,441 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:20:54,441 INFO L276 IsEmpty]: Start isEmpty. Operand 16956 states and 54151 transitions. [2019-11-28 18:20:54,451 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-11-28 18:20:54,451 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:54,451 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:54,451 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:54,451 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:54,452 INFO L82 PathProgramCache]: Analyzing trace with hash 613602003, now seen corresponding path program 1 times [2019-11-28 18:20:54,452 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:54,452 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [842844256] [2019-11-28 18:20:54,452 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:54,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:54,517 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:54,517 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [842844256] [2019-11-28 18:20:54,518 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:54,519 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 18:20:54,519 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1670612128] [2019-11-28 18:20:54,519 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:20:54,519 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:54,520 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:20:54,521 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:20:54,521 INFO L87 Difference]: Start difference. First operand 16956 states and 54151 transitions. Second operand 5 states. [2019-11-28 18:20:54,558 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:54,559 INFO L93 Difference]: Finished difference Result 2891 states and 7349 transitions. [2019-11-28 18:20:54,559 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:20:54,561 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 31 [2019-11-28 18:20:54,562 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:54,566 INFO L225 Difference]: With dead ends: 2891 [2019-11-28 18:20:54,567 INFO L226 Difference]: Without dead ends: 2891 [2019-11-28 18:20:54,567 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:20:54,573 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2891 states. [2019-11-28 18:20:54,594 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2891 to 2891. [2019-11-28 18:20:54,594 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2891 states. [2019-11-28 18:20:54,599 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2891 states to 2891 states and 7349 transitions. [2019-11-28 18:20:54,599 INFO L78 Accepts]: Start accepts. Automaton has 2891 states and 7349 transitions. Word has length 31 [2019-11-28 18:20:54,599 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:54,600 INFO L462 AbstractCegarLoop]: Abstraction has 2891 states and 7349 transitions. [2019-11-28 18:20:54,600 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:20:54,600 INFO L276 IsEmpty]: Start isEmpty. Operand 2891 states and 7349 transitions. [2019-11-28 18:20:54,605 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2019-11-28 18:20:54,605 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:54,605 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:54,605 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:54,606 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:54,606 INFO L82 PathProgramCache]: Analyzing trace with hash 2131566482, now seen corresponding path program 1 times [2019-11-28 18:20:54,606 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:54,606 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1623449091] [2019-11-28 18:20:54,606 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:54,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:54,713 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:54,713 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1623449091] [2019-11-28 18:20:54,713 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:54,713 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 18:20:54,714 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1030594474] [2019-11-28 18:20:54,714 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-28 18:20:54,714 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:54,714 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-28 18:20:54,715 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2019-11-28 18:20:54,716 INFO L87 Difference]: Start difference. First operand 2891 states and 7349 transitions. Second operand 6 states. [2019-11-28 18:20:54,757 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:54,757 INFO L93 Difference]: Finished difference Result 1241 states and 3509 transitions. [2019-11-28 18:20:54,757 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 18:20:54,758 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 43 [2019-11-28 18:20:54,758 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:54,760 INFO L225 Difference]: With dead ends: 1241 [2019-11-28 18:20:54,760 INFO L226 Difference]: Without dead ends: 1241 [2019-11-28 18:20:54,763 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2019-11-28 18:20:54,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1241 states. [2019-11-28 18:20:54,781 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1241 to 1129. [2019-11-28 18:20:54,781 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1129 states. [2019-11-28 18:20:54,785 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1129 states to 1129 states and 3189 transitions. [2019-11-28 18:20:54,785 INFO L78 Accepts]: Start accepts. Automaton has 1129 states and 3189 transitions. Word has length 43 [2019-11-28 18:20:54,786 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:54,786 INFO L462 AbstractCegarLoop]: Abstraction has 1129 states and 3189 transitions. [2019-11-28 18:20:54,786 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-28 18:20:54,786 INFO L276 IsEmpty]: Start isEmpty. Operand 1129 states and 3189 transitions. [2019-11-28 18:20:54,789 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-11-28 18:20:54,789 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:54,789 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:54,789 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:54,790 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:54,790 INFO L82 PathProgramCache]: Analyzing trace with hash -275883304, now seen corresponding path program 1 times [2019-11-28 18:20:54,790 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:54,790 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [448454636] [2019-11-28 18:20:54,791 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:54,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:54,877 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:54,878 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [448454636] [2019-11-28 18:20:54,879 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:54,879 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:20:54,880 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2072366538] [2019-11-28 18:20:54,881 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:20:54,881 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:54,881 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:20:54,882 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:54,882 INFO L87 Difference]: Start difference. First operand 1129 states and 3189 transitions. Second operand 3 states. [2019-11-28 18:20:54,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:54,932 INFO L93 Difference]: Finished difference Result 1141 states and 3206 transitions. [2019-11-28 18:20:54,933 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:20:54,933 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 58 [2019-11-28 18:20:54,933 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:54,937 INFO L225 Difference]: With dead ends: 1141 [2019-11-28 18:20:54,937 INFO L226 Difference]: Without dead ends: 1141 [2019-11-28 18:20:54,937 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:54,941 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1141 states. [2019-11-28 18:20:54,952 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1141 to 1135. [2019-11-28 18:20:54,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1135 states. [2019-11-28 18:20:54,956 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1135 states to 1135 states and 3199 transitions. [2019-11-28 18:20:54,956 INFO L78 Accepts]: Start accepts. Automaton has 1135 states and 3199 transitions. Word has length 58 [2019-11-28 18:20:54,958 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:54,958 INFO L462 AbstractCegarLoop]: Abstraction has 1135 states and 3199 transitions. [2019-11-28 18:20:54,958 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:20:54,959 INFO L276 IsEmpty]: Start isEmpty. Operand 1135 states and 3199 transitions. [2019-11-28 18:20:54,962 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-11-28 18:20:54,962 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:54,963 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:54,963 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:54,963 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:54,964 INFO L82 PathProgramCache]: Analyzing trace with hash -791070951, now seen corresponding path program 1 times [2019-11-28 18:20:54,964 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:54,964 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1095754205] [2019-11-28 18:20:54,965 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:55,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:55,067 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:55,067 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1095754205] [2019-11-28 18:20:55,068 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:55,068 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 18:20:55,068 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [668875849] [2019-11-28 18:20:55,068 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:20:55,069 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:55,069 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:20:55,069 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:20:55,069 INFO L87 Difference]: Start difference. First operand 1135 states and 3199 transitions. Second operand 5 states. [2019-11-28 18:20:55,312 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:55,312 INFO L93 Difference]: Finished difference Result 1644 states and 4637 transitions. [2019-11-28 18:20:55,312 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-11-28 18:20:55,312 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 58 [2019-11-28 18:20:55,313 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:55,316 INFO L225 Difference]: With dead ends: 1644 [2019-11-28 18:20:55,316 INFO L226 Difference]: Without dead ends: 1644 [2019-11-28 18:20:55,317 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-11-28 18:20:55,321 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1644 states. [2019-11-28 18:20:55,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1644 to 1448. [2019-11-28 18:20:55,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1448 states. [2019-11-28 18:20:55,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1448 states to 1448 states and 4085 transitions. [2019-11-28 18:20:55,344 INFO L78 Accepts]: Start accepts. Automaton has 1448 states and 4085 transitions. Word has length 58 [2019-11-28 18:20:55,344 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:55,344 INFO L462 AbstractCegarLoop]: Abstraction has 1448 states and 4085 transitions. [2019-11-28 18:20:55,344 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:20:55,344 INFO L276 IsEmpty]: Start isEmpty. Operand 1448 states and 4085 transitions. [2019-11-28 18:20:55,348 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-11-28 18:20:55,348 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:55,348 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:55,348 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:55,348 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:55,349 INFO L82 PathProgramCache]: Analyzing trace with hash 867176459, now seen corresponding path program 2 times [2019-11-28 18:20:55,349 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:55,349 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [967122108] [2019-11-28 18:20:55,349 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:55,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:55,471 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:55,472 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [967122108] [2019-11-28 18:20:55,472 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:55,472 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-28 18:20:55,472 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [106975467] [2019-11-28 18:20:55,473 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-28 18:20:55,473 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:55,473 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-28 18:20:55,474 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-11-28 18:20:55,474 INFO L87 Difference]: Start difference. First operand 1448 states and 4085 transitions. Second operand 6 states. [2019-11-28 18:20:55,773 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:55,773 INFO L93 Difference]: Finished difference Result 1722 states and 4730 transitions. [2019-11-28 18:20:55,774 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-11-28 18:20:55,774 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 58 [2019-11-28 18:20:55,774 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:55,777 INFO L225 Difference]: With dead ends: 1722 [2019-11-28 18:20:55,777 INFO L226 Difference]: Without dead ends: 1722 [2019-11-28 18:20:55,778 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-11-28 18:20:55,782 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1722 states. [2019-11-28 18:20:55,794 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1722 to 1500. [2019-11-28 18:20:55,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1500 states. [2019-11-28 18:20:55,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1500 states to 1500 states and 4161 transitions. [2019-11-28 18:20:55,797 INFO L78 Accepts]: Start accepts. Automaton has 1500 states and 4161 transitions. Word has length 58 [2019-11-28 18:20:55,797 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:55,797 INFO L462 AbstractCegarLoop]: Abstraction has 1500 states and 4161 transitions. [2019-11-28 18:20:55,797 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-28 18:20:55,797 INFO L276 IsEmpty]: Start isEmpty. Operand 1500 states and 4161 transitions. [2019-11-28 18:20:55,799 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-11-28 18:20:55,800 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:55,800 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:55,800 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:55,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:55,800 INFO L82 PathProgramCache]: Analyzing trace with hash -2105802411, now seen corresponding path program 3 times [2019-11-28 18:20:55,800 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:55,801 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1653215130] [2019-11-28 18:20:55,801 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:55,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:55,907 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:55,907 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1653215130] [2019-11-28 18:20:55,908 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:55,908 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:20:55,908 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [215424203] [2019-11-28 18:20:55,909 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:20:55,909 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:55,909 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:20:55,909 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:55,910 INFO L87 Difference]: Start difference. First operand 1500 states and 4161 transitions. Second operand 3 states. [2019-11-28 18:20:55,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:55,958 INFO L93 Difference]: Finished difference Result 1499 states and 4159 transitions. [2019-11-28 18:20:55,958 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:20:55,958 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 58 [2019-11-28 18:20:55,959 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:55,962 INFO L225 Difference]: With dead ends: 1499 [2019-11-28 18:20:55,962 INFO L226 Difference]: Without dead ends: 1499 [2019-11-28 18:20:55,963 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:55,966 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1499 states. [2019-11-28 18:20:55,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1499 to 1186. [2019-11-28 18:20:55,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1186 states. [2019-11-28 18:20:55,980 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1186 states to 1186 states and 3289 transitions. [2019-11-28 18:20:55,980 INFO L78 Accepts]: Start accepts. Automaton has 1186 states and 3289 transitions. Word has length 58 [2019-11-28 18:20:55,980 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:55,981 INFO L462 AbstractCegarLoop]: Abstraction has 1186 states and 3289 transitions. [2019-11-28 18:20:55,981 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:20:55,981 INFO L276 IsEmpty]: Start isEmpty. Operand 1186 states and 3289 transitions. [2019-11-28 18:20:55,983 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-11-28 18:20:55,983 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:55,984 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:55,984 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:55,984 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:55,984 INFO L82 PathProgramCache]: Analyzing trace with hash 654382096, now seen corresponding path program 1 times [2019-11-28 18:20:55,984 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:55,985 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2108408983] [2019-11-28 18:20:55,985 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:56,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:56,127 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:56,127 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2108408983] [2019-11-28 18:20:56,128 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:56,128 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 18:20:56,128 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [753480589] [2019-11-28 18:20:56,129 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-28 18:20:56,129 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:56,130 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-28 18:20:56,130 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-11-28 18:20:56,130 INFO L87 Difference]: Start difference. First operand 1186 states and 3289 transitions. Second operand 6 states. [2019-11-28 18:20:56,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:56,244 INFO L93 Difference]: Finished difference Result 2353 states and 6054 transitions. [2019-11-28 18:20:56,244 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 18:20:56,245 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 59 [2019-11-28 18:20:56,245 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:56,247 INFO L225 Difference]: With dead ends: 2353 [2019-11-28 18:20:56,247 INFO L226 Difference]: Without dead ends: 958 [2019-11-28 18:20:56,248 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-11-28 18:20:56,250 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 958 states. [2019-11-28 18:20:56,261 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 958 to 662. [2019-11-28 18:20:56,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 662 states. [2019-11-28 18:20:56,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 662 states to 662 states and 1493 transitions. [2019-11-28 18:20:56,264 INFO L78 Accepts]: Start accepts. Automaton has 662 states and 1493 transitions. Word has length 59 [2019-11-28 18:20:56,264 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:56,265 INFO L462 AbstractCegarLoop]: Abstraction has 662 states and 1493 transitions. [2019-11-28 18:20:56,265 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-28 18:20:56,265 INFO L276 IsEmpty]: Start isEmpty. Operand 662 states and 1493 transitions. [2019-11-28 18:20:56,267 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-11-28 18:20:56,267 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:56,267 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:56,267 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:56,268 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:56,268 INFO L82 PathProgramCache]: Analyzing trace with hash 1334298476, now seen corresponding path program 2 times [2019-11-28 18:20:56,268 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:56,269 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1073427368] [2019-11-28 18:20:56,269 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:56,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:56,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:56,335 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1073427368] [2019-11-28 18:20:56,336 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:56,336 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:20:56,336 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [163884031] [2019-11-28 18:20:56,336 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:20:56,337 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:56,337 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:20:56,337 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:56,337 INFO L87 Difference]: Start difference. First operand 662 states and 1493 transitions. Second operand 3 states. [2019-11-28 18:20:56,355 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:56,356 INFO L93 Difference]: Finished difference Result 650 states and 1453 transitions. [2019-11-28 18:20:56,356 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:20:56,357 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 59 [2019-11-28 18:20:56,357 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:56,358 INFO L225 Difference]: With dead ends: 650 [2019-11-28 18:20:56,358 INFO L226 Difference]: Without dead ends: 650 [2019-11-28 18:20:56,359 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:20:56,362 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 650 states. [2019-11-28 18:20:56,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 650 to 650. [2019-11-28 18:20:56,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 650 states. [2019-11-28 18:20:56,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 650 states to 650 states and 1453 transitions. [2019-11-28 18:20:56,373 INFO L78 Accepts]: Start accepts. Automaton has 650 states and 1453 transitions. Word has length 59 [2019-11-28 18:20:56,374 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:56,374 INFO L462 AbstractCegarLoop]: Abstraction has 650 states and 1453 transitions. [2019-11-28 18:20:56,374 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:20:56,374 INFO L276 IsEmpty]: Start isEmpty. Operand 650 states and 1453 transitions. [2019-11-28 18:20:56,376 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-11-28 18:20:56,377 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:56,377 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:56,378 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:56,378 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:56,378 INFO L82 PathProgramCache]: Analyzing trace with hash 2055807341, now seen corresponding path program 1 times [2019-11-28 18:20:56,379 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:56,379 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2111313719] [2019-11-28 18:20:56,379 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:56,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:56,699 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:56,700 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2111313719] [2019-11-28 18:20:56,700 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:56,700 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-11-28 18:20:56,701 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [138538139] [2019-11-28 18:20:56,701 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-11-28 18:20:56,701 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:56,701 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-11-28 18:20:56,702 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=103, Unknown=0, NotChecked=0, Total=132 [2019-11-28 18:20:56,702 INFO L87 Difference]: Start difference. First operand 650 states and 1453 transitions. Second operand 12 states. [2019-11-28 18:20:57,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:57,441 INFO L93 Difference]: Finished difference Result 1340 states and 2732 transitions. [2019-11-28 18:20:57,442 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-11-28 18:20:57,442 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 60 [2019-11-28 18:20:57,442 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:57,443 INFO L225 Difference]: With dead ends: 1340 [2019-11-28 18:20:57,444 INFO L226 Difference]: Without dead ends: 817 [2019-11-28 18:20:57,444 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 84 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=143, Invalid=457, Unknown=0, NotChecked=0, Total=600 [2019-11-28 18:20:57,446 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 817 states. [2019-11-28 18:20:57,453 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 817 to 573. [2019-11-28 18:20:57,453 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 573 states. [2019-11-28 18:20:57,455 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 573 states to 573 states and 1232 transitions. [2019-11-28 18:20:57,455 INFO L78 Accepts]: Start accepts. Automaton has 573 states and 1232 transitions. Word has length 60 [2019-11-28 18:20:57,455 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:57,455 INFO L462 AbstractCegarLoop]: Abstraction has 573 states and 1232 transitions. [2019-11-28 18:20:57,456 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-11-28 18:20:57,456 INFO L276 IsEmpty]: Start isEmpty. Operand 573 states and 1232 transitions. [2019-11-28 18:20:57,457 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-11-28 18:20:57,457 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:57,458 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:57,458 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:57,458 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:57,458 INFO L82 PathProgramCache]: Analyzing trace with hash -837634653, now seen corresponding path program 2 times [2019-11-28 18:20:57,459 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:57,459 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [282784955] [2019-11-28 18:20:57,459 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:57,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:20:57,549 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:20:57,550 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [282784955] [2019-11-28 18:20:57,550 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:20:57,550 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 18:20:57,550 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [505713959] [2019-11-28 18:20:57,551 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:20:57,551 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:20:57,552 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:20:57,552 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:20:57,552 INFO L87 Difference]: Start difference. First operand 573 states and 1232 transitions. Second operand 5 states. [2019-11-28 18:20:57,595 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:20:57,595 INFO L93 Difference]: Finished difference Result 755 states and 1551 transitions. [2019-11-28 18:20:57,595 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:20:57,595 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 60 [2019-11-28 18:20:57,596 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:20:57,596 INFO L225 Difference]: With dead ends: 755 [2019-11-28 18:20:57,596 INFO L226 Difference]: Without dead ends: 213 [2019-11-28 18:20:57,597 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-28 18:20:57,598 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 213 states. [2019-11-28 18:20:57,599 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 213 to 213. [2019-11-28 18:20:57,599 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 213 states. [2019-11-28 18:20:57,599 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 213 states to 213 states and 368 transitions. [2019-11-28 18:20:57,600 INFO L78 Accepts]: Start accepts. Automaton has 213 states and 368 transitions. Word has length 60 [2019-11-28 18:20:57,603 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:20:57,603 INFO L462 AbstractCegarLoop]: Abstraction has 213 states and 368 transitions. [2019-11-28 18:20:57,603 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:20:57,603 INFO L276 IsEmpty]: Start isEmpty. Operand 213 states and 368 transitions. [2019-11-28 18:20:57,604 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2019-11-28 18:20:57,604 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:20:57,604 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:20:57,605 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P3Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P3Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:20:57,605 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:20:57,605 INFO L82 PathProgramCache]: Analyzing trace with hash -524819563, now seen corresponding path program 3 times [2019-11-28 18:20:57,606 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:20:57,606 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [156324996] [2019-11-28 18:20:57,606 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:20:57,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 18:20:57,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 18:20:57,737 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-28 18:20:57,737 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-28 18:20:57,741 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [777] [777] ULTIMATE.startENTRY-->L821: Formula: (let ((.cse0 (store |v_#valid_75| 0 0))) (and (= v_~weak$$choice2~0_146 0) (= v_~z$w_buff0_used~0_885 0) (= v_~z$mem_tmp~0_22 0) (= (select .cse0 |v_ULTIMATE.start_main_~#t1517~0.base_24|) 0) (= v_~z$r_buff1_thd0~0_298 0) (= 0 v_~z$r_buff1_thd2~0_83) (= 0 v_~z$r_buff1_thd4~0_140) (= 0 v_~z$r_buff1_thd1~0_83) (= 0 v_~z$flush_delayed~0_36) (= |v_#memory_int_25| (store |v_#memory_int_26| |v_ULTIMATE.start_main_~#t1517~0.base_24| (store (select |v_#memory_int_26| |v_ULTIMATE.start_main_~#t1517~0.base_24|) |v_ULTIMATE.start_main_~#t1517~0.offset_18| 0))) (= 0 |v_ULTIMATE.start_main_~#t1517~0.offset_18|) (= v_~z$r_buff0_thd3~0_92 0) (= v_~z$read_delayed_var~0.offset_7 0) (< 0 |v_#StackHeapBarrier_18|) (= v_~__unbuffered_p3_EAX~0_100 0) (= v_~z$w_buff0~0_503 0) (= v_~z$w_buff1_used~0_515 0) (= v_~a~0_48 0) (= v_~x~0_57 0) (= v_~z$read_delayed_var~0.base_7 0) (= v_~z$read_delayed~0_7 0) (= v_~z~0_155 0) (= v_~main$tmp_guard1~0_32 0) (= |v_#length_29| (store |v_#length_30| |v_ULTIMATE.start_main_~#t1517~0.base_24| 4)) (= |v_#valid_73| (store .cse0 |v_ULTIMATE.start_main_~#t1517~0.base_24| 1)) (= 0 v_~weak$$choice0~0_16) (= v_~__unbuffered_cnt~0_141 0) (= 0 v_~z$r_buff1_thd3~0_146) (= v_~z$w_buff1~0_306 0) (= v_~z$r_buff0_thd0~0_394 0) (= |v_#NULL.offset_5| 0) (= v_~z$r_buff0_thd2~0_32 0) (= v_~main$tmp_guard0~0_22 0) (= 0 v_~z$r_buff0_thd4~0_161) (= v_~y~0_76 0) (= v_~z$r_buff0_thd1~0_32 0) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t1517~0.base_24|) (= 0 |v_#NULL.base_5|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_75|, #memory_int=|v_#memory_int_26|, #length=|v_#length_30|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_59|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_83, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_41|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_32|, ULTIMATE.start_main_~#t1517~0.offset=|v_ULTIMATE.start_main_~#t1517~0.offset_18|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_35|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_30|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_45|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_60|, ~a~0=v_~a~0_48, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_394, ~z$r_buff0_thd4~0=v_~z$r_buff0_thd4~0_161, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_100, #length=|v_#length_29|, ~z$mem_tmp~0=v_~z$mem_tmp~0_22, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_48|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_114|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_515, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_191|, ~z$flush_delayed~0=v_~z$flush_delayed~0_36, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_35|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_44|, ~weak$$choice0~0=v_~weak$$choice0~0_16, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_38|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_83, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_10|, ULTIMATE.start_main_~#t1519~0.base=|v_ULTIMATE.start_main_~#t1519~0.base_20|, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_7, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_92, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_10|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_141, ~x~0=v_~x~0_57, ULTIMATE.start_main_~#t1520~0.base=|v_ULTIMATE.start_main_~#t1520~0.base_21|, ~z$r_buff1_thd4~0=v_~z$r_buff1_thd4~0_140, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_40|, ~z$read_delayed~0=v_~z$read_delayed~0_7, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_57|, ~z$w_buff1~0=v_~z$w_buff1~0_306, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_43|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_31|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_29|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_31|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_51|, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_44|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_298, ULTIMATE.start_main_#t~nondet26=|v_ULTIMATE.start_main_#t~nondet26_25|, ULTIMATE.start_main_~#t1520~0.offset=|v_ULTIMATE.start_main_~#t1520~0.offset_17|, ULTIMATE.start_main_~#t1518~0.base=|v_ULTIMATE.start_main_~#t1518~0.base_22|, ~y~0=v_~y~0_76, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_32, ULTIMATE.start_main_~#t1518~0.offset=|v_ULTIMATE.start_main_~#t1518~0.offset_17|, ULTIMATE.start_main_~#t1517~0.base=|v_ULTIMATE.start_main_~#t1517~0.base_24|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_885, ~z$w_buff0~0=v_~z$w_buff0~0_503, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_39|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_25|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_146, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_122|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_44|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_22, ULTIMATE.start_main_~#t1519~0.offset=|v_ULTIMATE.start_main_~#t1519~0.offset_16|, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_36|, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_35|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_31|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, #valid=|v_#valid_73|, #memory_int=|v_#memory_int_25|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_9|, ULTIMATE.start_main_#t~nondet18=|v_ULTIMATE.start_main_#t~nondet18_23|, ~z~0=v_~z~0_155, ~weak$$choice2~0=v_~weak$$choice2~0_146, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_32} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_~#t1517~0.offset, #NULL.offset, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~a~0, ~z$r_buff0_thd0~0, ~z$r_buff0_thd4~0, ~__unbuffered_p3_EAX~0, #length, ~z$mem_tmp~0, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ~z$flush_delayed~0, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~z$r_buff1_thd1~0, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_~#t1519~0.base, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~x~0, ULTIMATE.start_main_~#t1520~0.base, ~z$r_buff1_thd4~0, ULTIMATE.start_main_#t~ite29, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite30, ~z$r_buff1_thd0~0, ULTIMATE.start_main_#t~nondet26, ULTIMATE.start_main_~#t1520~0.offset, ULTIMATE.start_main_~#t1518~0.base, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_~#t1518~0.offset, ULTIMATE.start_main_~#t1517~0.base, ~z$w_buff0_used~0, ~z$w_buff0~0, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_~#t1519~0.offset, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ULTIMATE.start_main_#t~nondet18, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-11-28 18:20:57,742 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [732] [732] L821-1-->L823: Formula: (and (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1518~0.base_10| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1518~0.base_10|) |v_ULTIMATE.start_main_~#t1518~0.offset_9| 1)) |v_#memory_int_13|) (= (select |v_#valid_36| |v_ULTIMATE.start_main_~#t1518~0.base_10|) 0) (= |v_#valid_35| (store |v_#valid_36| |v_ULTIMATE.start_main_~#t1518~0.base_10| 1)) (not (= 0 |v_ULTIMATE.start_main_~#t1518~0.base_10|)) (= 0 |v_ULTIMATE.start_main_~#t1518~0.offset_9|) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t1518~0.base_10| 4)) (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t1518~0.base_10|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_36|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, #length=|v_#length_17|, ULTIMATE.start_main_~#t1518~0.base=|v_ULTIMATE.start_main_~#t1518~0.base_10|, ULTIMATE.start_main_~#t1518~0.offset=|v_ULTIMATE.start_main_~#t1518~0.offset_9|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_#t~nondet15, #length, ULTIMATE.start_main_~#t1518~0.base, ULTIMATE.start_main_~#t1518~0.offset] because there is no mapped edge [2019-11-28 18:20:57,743 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [753] [753] L823-1-->L825: Formula: (and (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1519~0.base_12|) (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t1519~0.base_12| 4)) (= (select |v_#valid_46| |v_ULTIMATE.start_main_~#t1519~0.base_12|) 0) (not (= |v_ULTIMATE.start_main_~#t1519~0.base_12| 0)) (= |v_#memory_int_17| (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1519~0.base_12| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1519~0.base_12|) |v_ULTIMATE.start_main_~#t1519~0.offset_10| 2))) (= |v_#valid_45| (store |v_#valid_46| |v_ULTIMATE.start_main_~#t1519~0.base_12| 1)) (= 0 |v_ULTIMATE.start_main_~#t1519~0.offset_10|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_46|, #memory_int=|v_#memory_int_18|, #length=|v_#length_22|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_45|, #memory_int=|v_#memory_int_17|, ULTIMATE.start_main_~#t1519~0.base=|v_ULTIMATE.start_main_~#t1519~0.base_12|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, #length=|v_#length_21|, ULTIMATE.start_main_~#t1519~0.offset=|v_ULTIMATE.start_main_~#t1519~0.offset_10|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_~#t1519~0.base, ULTIMATE.start_main_#t~nondet16, #length, ULTIMATE.start_main_~#t1519~0.offset] because there is no mapped edge [2019-11-28 18:20:57,743 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [743] [743] L825-1-->L827: Formula: (and (= (select |v_#valid_40| |v_ULTIMATE.start_main_~#t1520~0.base_11|) 0) (= (store |v_#valid_40| |v_ULTIMATE.start_main_~#t1520~0.base_11| 1) |v_#valid_39|) (= |v_ULTIMATE.start_main_~#t1520~0.offset_10| 0) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t1520~0.base_11|) (not (= |v_ULTIMATE.start_main_~#t1520~0.base_11| 0)) (= |v_#length_19| (store |v_#length_20| |v_ULTIMATE.start_main_~#t1520~0.base_11| 4)) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1520~0.base_11| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1520~0.base_11|) |v_ULTIMATE.start_main_~#t1520~0.offset_10| 3)) |v_#memory_int_15|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_16|, #length=|v_#length_20|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_39|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_~#t1520~0.offset=|v_ULTIMATE.start_main_~#t1520~0.offset_10|, #length=|v_#length_19|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_6|, ULTIMATE.start_main_~#t1520~0.base=|v_ULTIMATE.start_main_~#t1520~0.base_11|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_~#t1520~0.offset, #length, ULTIMATE.start_main_#t~nondet17, ULTIMATE.start_main_~#t1520~0.base] because there is no mapped edge [2019-11-28 18:20:57,744 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [691] [691] P3ENTRY-->L4-3: Formula: (and (not (= v_P3Thread1of1ForFork2___VERIFIER_assert_~expression_11 0)) (= v_P3Thread1of1ForFork2_~arg.base_9 |v_P3Thread1of1ForFork2_#in~arg.base_11|) (= v_P3Thread1of1ForFork2___VERIFIER_assert_~expression_11 |v_P3Thread1of1ForFork2___VERIFIER_assert_#in~expression_9|) (= (ite (not (and (not (= (mod v_~z$w_buff0_used~0_218 256) 0)) (not (= (mod v_~z$w_buff1_used~0_99 256) 0)))) 1 0) |v_P3Thread1of1ForFork2___VERIFIER_assert_#in~expression_9|) (= |v_P3Thread1of1ForFork2_#in~arg.offset_11| v_P3Thread1of1ForFork2_~arg.offset_9) (= v_~z$w_buff0_used~0_218 1) (= v_~z$w_buff0~0_48 v_~z$w_buff1~0_32) (= 2 v_~z$w_buff0~0_47) (= v_~z$w_buff0_used~0_219 v_~z$w_buff1_used~0_99)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_219, ~z$w_buff0~0=v_~z$w_buff0~0_48, P3Thread1of1ForFork2_#in~arg.offset=|v_P3Thread1of1ForFork2_#in~arg.offset_11|, P3Thread1of1ForFork2_#in~arg.base=|v_P3Thread1of1ForFork2_#in~arg.base_11|} OutVars{P3Thread1of1ForFork2___VERIFIER_assert_~expression=v_P3Thread1of1ForFork2___VERIFIER_assert_~expression_11, P3Thread1of1ForFork2_~arg.offset=v_P3Thread1of1ForFork2_~arg.offset_9, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_218, ~z$w_buff0~0=v_~z$w_buff0~0_47, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_99, P3Thread1of1ForFork2_#in~arg.offset=|v_P3Thread1of1ForFork2_#in~arg.offset_11|, ~z$w_buff1~0=v_~z$w_buff1~0_32, P3Thread1of1ForFork2___VERIFIER_assert_#in~expression=|v_P3Thread1of1ForFork2___VERIFIER_assert_#in~expression_9|, P3Thread1of1ForFork2_~arg.base=v_P3Thread1of1ForFork2_~arg.base_9, P3Thread1of1ForFork2_#in~arg.base=|v_P3Thread1of1ForFork2_#in~arg.base_11|} AuxVars[] AssignedVars[P3Thread1of1ForFork2___VERIFIER_assert_~expression, P3Thread1of1ForFork2_~arg.offset, ~z$w_buff0_used~0, ~z$w_buff0~0, ~z$w_buff1_used~0, ~z$w_buff1~0, P3Thread1of1ForFork2___VERIFIER_assert_#in~expression, P3Thread1of1ForFork2_~arg.base] because there is no mapped edge [2019-11-28 18:20:57,745 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [757] [757] P0ENTRY-->P0EXIT: Formula: (and (= v_~x~0_44 1) (= v_~__unbuffered_cnt~0_102 (+ v_~__unbuffered_cnt~0_103 1)) (= v_P0Thread1of1ForFork3_~arg.base_17 |v_P0Thread1of1ForFork3_#in~arg.base_19|) (= v_~a~0_40 1) (= |v_P0Thread1of1ForFork3_#res.offset_9| 0) (= |v_P0Thread1of1ForFork3_#in~arg.offset_19| v_P0Thread1of1ForFork3_~arg.offset_17) (= 0 |v_P0Thread1of1ForFork3_#res.base_9|)) InVars {P0Thread1of1ForFork3_#in~arg.offset=|v_P0Thread1of1ForFork3_#in~arg.offset_19|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_103, P0Thread1of1ForFork3_#in~arg.base=|v_P0Thread1of1ForFork3_#in~arg.base_19|} OutVars{~a~0=v_~a~0_40, P0Thread1of1ForFork3_#in~arg.offset=|v_P0Thread1of1ForFork3_#in~arg.offset_19|, P0Thread1of1ForFork3_~arg.base=v_P0Thread1of1ForFork3_~arg.base_17, P0Thread1of1ForFork3_#res.base=|v_P0Thread1of1ForFork3_#res.base_9|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_102, P0Thread1of1ForFork3_#res.offset=|v_P0Thread1of1ForFork3_#res.offset_9|, P0Thread1of1ForFork3_~arg.offset=v_P0Thread1of1ForFork3_~arg.offset_17, P0Thread1of1ForFork3_#in~arg.base=|v_P0Thread1of1ForFork3_#in~arg.base_19|, ~x~0=v_~x~0_44} AuxVars[] AssignedVars[~a~0, P0Thread1of1ForFork3_~arg.base, P0Thread1of1ForFork3_#res.base, ~__unbuffered_cnt~0, P0Thread1of1ForFork3_#res.offset, P0Thread1of1ForFork3_~arg.offset, ~x~0] because there is no mapped edge [2019-11-28 18:20:57,745 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [746] [746] P1ENTRY-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork0_#res.offset_3|) (= v_~x~0_39 2) (= v_~__unbuffered_cnt~0_78 (+ v_~__unbuffered_cnt~0_79 1)) (= v_~y~0_50 1) (= 0 |v_P1Thread1of1ForFork0_#res.base_3|) (= |v_P1Thread1of1ForFork0_#in~arg.base_10| v_P1Thread1of1ForFork0_~arg.base_8) (= |v_P1Thread1of1ForFork0_#in~arg.offset_10| v_P1Thread1of1ForFork0_~arg.offset_8)) InVars {P1Thread1of1ForFork0_#in~arg.base=|v_P1Thread1of1ForFork0_#in~arg.base_10|, P1Thread1of1ForFork0_#in~arg.offset=|v_P1Thread1of1ForFork0_#in~arg.offset_10|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_79} OutVars{P1Thread1of1ForFork0_~arg.offset=v_P1Thread1of1ForFork0_~arg.offset_8, P1Thread1of1ForFork0_~arg.base=v_P1Thread1of1ForFork0_~arg.base_8, P1Thread1of1ForFork0_#in~arg.base=|v_P1Thread1of1ForFork0_#in~arg.base_10|, P1Thread1of1ForFork0_#in~arg.offset=|v_P1Thread1of1ForFork0_#in~arg.offset_10|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_78, P1Thread1of1ForFork0_#res.offset=|v_P1Thread1of1ForFork0_#res.offset_3|, ~y~0=v_~y~0_50, P1Thread1of1ForFork0_#res.base=|v_P1Thread1of1ForFork0_#res.base_3|, ~x~0=v_~x~0_39} AuxVars[] AssignedVars[P1Thread1of1ForFork0_~arg.offset, P1Thread1of1ForFork0_~arg.base, ~__unbuffered_cnt~0, P1Thread1of1ForFork0_#res.offset, ~y~0, P1Thread1of1ForFork0_#res.base, ~x~0] because there is no mapped edge [2019-11-28 18:20:57,746 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L768-2-->L768-5: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff1_thd3~0_In1745659752 256))) (.cse1 (= (mod ~z$w_buff1_used~0_In1745659752 256) 0)) (.cse2 (= |P2Thread1of1ForFork1_#t~ite4_Out1745659752| |P2Thread1of1ForFork1_#t~ite3_Out1745659752|))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork1_#t~ite3_Out1745659752| ~z~0_In1745659752) .cse2) (and (= ~z$w_buff1~0_In1745659752 |P2Thread1of1ForFork1_#t~ite3_Out1745659752|) (not .cse0) (not .cse1) .cse2))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1745659752, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1745659752, ~z$w_buff1~0=~z$w_buff1~0_In1745659752, ~z~0=~z~0_In1745659752} OutVars{P2Thread1of1ForFork1_#t~ite4=|P2Thread1of1ForFork1_#t~ite4_Out1745659752|, P2Thread1of1ForFork1_#t~ite3=|P2Thread1of1ForFork1_#t~ite3_Out1745659752|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1745659752, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1745659752, ~z$w_buff1~0=~z$w_buff1~0_In1745659752, ~z~0=~z~0_In1745659752} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite4, P2Thread1of1ForFork1_#t~ite3] because there is no mapped edge [2019-11-28 18:20:57,747 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [722] [722] L769-->L769-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In305584938 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In305584938 256)))) (or (and (= |P2Thread1of1ForFork1_#t~ite5_Out305584938| ~z$w_buff0_used~0_In305584938) (or .cse0 .cse1)) (and (= 0 |P2Thread1of1ForFork1_#t~ite5_Out305584938|) (not .cse1) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In305584938, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In305584938} OutVars{P2Thread1of1ForFork1_#t~ite5=|P2Thread1of1ForFork1_#t~ite5_Out305584938|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In305584938, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In305584938} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite5] because there is no mapped edge [2019-11-28 18:20:57,748 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [724] [724] L770-->L770-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff1_used~0_In-858612910 256))) (.cse1 (= 0 (mod ~z$r_buff1_thd3~0_In-858612910 256))) (.cse2 (= (mod ~z$r_buff0_thd3~0_In-858612910 256) 0)) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In-858612910 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork1_#t~ite6_Out-858612910|)) (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~z$w_buff1_used~0_In-858612910 |P2Thread1of1ForFork1_#t~ite6_Out-858612910|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-858612910, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-858612910, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-858612910, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-858612910} OutVars{P2Thread1of1ForFork1_#t~ite6=|P2Thread1of1ForFork1_#t~ite6_Out-858612910|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-858612910, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-858612910, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-858612910, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-858612910} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite6] because there is no mapped edge [2019-11-28 18:20:57,748 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [710] [710] L771-->L771-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd3~0_In1252880533 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In1252880533 256) 0))) (or (and (= |P2Thread1of1ForFork1_#t~ite7_Out1252880533| ~z$r_buff0_thd3~0_In1252880533) (or .cse0 .cse1)) (and (= |P2Thread1of1ForFork1_#t~ite7_Out1252880533| 0) (not .cse0) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1252880533, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1252880533} OutVars{P2Thread1of1ForFork1_#t~ite7=|P2Thread1of1ForFork1_#t~ite7_Out1252880533|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1252880533, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1252880533} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite7] because there is no mapped edge [2019-11-28 18:20:57,749 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [708] [708] L772-->L772-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff1_used~0_In886166393 256))) (.cse1 (= 0 (mod ~z$r_buff1_thd3~0_In886166393 256))) (.cse3 (= 0 (mod ~z$r_buff0_thd3~0_In886166393 256))) (.cse2 (= (mod ~z$w_buff0_used~0_In886166393 256) 0))) (or (and (= 0 |P2Thread1of1ForFork1_#t~ite8_Out886166393|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (or .cse3 .cse2) (= |P2Thread1of1ForFork1_#t~ite8_Out886166393| ~z$r_buff1_thd3~0_In886166393)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In886166393, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In886166393, ~z$w_buff1_used~0=~z$w_buff1_used~0_In886166393, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In886166393} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In886166393, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In886166393, ~z$w_buff1_used~0=~z$w_buff1_used~0_In886166393, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In886166393, P2Thread1of1ForFork1_#t~ite8=|P2Thread1of1ForFork1_#t~ite8_Out886166393|} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite8] because there is no mapped edge [2019-11-28 18:20:57,749 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [752] [752] L772-2-->P2EXIT: Formula: (and (= 0 |v_P2Thread1of1ForFork1_#res.offset_3|) (= v_~z$r_buff1_thd3~0_127 |v_P2Thread1of1ForFork1_#t~ite8_44|) (= v_~__unbuffered_cnt~0_100 (+ v_~__unbuffered_cnt~0_101 1)) (= 0 |v_P2Thread1of1ForFork1_#res.base_3|)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_101, P2Thread1of1ForFork1_#t~ite8=|v_P2Thread1of1ForFork1_#t~ite8_44|} OutVars{P2Thread1of1ForFork1_#res.base=|v_P2Thread1of1ForFork1_#res.base_3|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_127, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_100, P2Thread1of1ForFork1_#res.offset=|v_P2Thread1of1ForFork1_#res.offset_3|, P2Thread1of1ForFork1_#t~ite8=|v_P2Thread1of1ForFork1_#t~ite8_43|} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#res.base, ~z$r_buff1_thd3~0, ~__unbuffered_cnt~0, P2Thread1of1ForFork1_#res.offset, P2Thread1of1ForFork1_#t~ite8] because there is no mapped edge [2019-11-28 18:20:57,750 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [727] [727] L799-->L799-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd4~0_In-1673649629 256) 0)) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1673649629 256)))) (or (and (= |P3Thread1of1ForFork2_#t~ite11_Out-1673649629| 0) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= |P3Thread1of1ForFork2_#t~ite11_Out-1673649629| ~z$w_buff0_used~0_In-1673649629)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1673649629, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-1673649629} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1673649629, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-1673649629, P3Thread1of1ForFork2_#t~ite11=|P3Thread1of1ForFork2_#t~ite11_Out-1673649629|} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite11] because there is no mapped edge [2019-11-28 18:20:57,751 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [712] [712] L800-->L800-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff1_thd4~0_In1850039452 256))) (.cse1 (= (mod ~z$w_buff1_used~0_In1850039452 256) 0)) (.cse2 (= (mod ~z$r_buff0_thd4~0_In1850039452 256) 0)) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In1850039452 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P3Thread1of1ForFork2_#t~ite12_Out1850039452|)) (and (or .cse0 .cse1) (= ~z$w_buff1_used~0_In1850039452 |P3Thread1of1ForFork2_#t~ite12_Out1850039452|) (or .cse2 .cse3)))) InVars {~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In1850039452, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1850039452, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In1850039452, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1850039452} OutVars{~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In1850039452, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1850039452, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In1850039452, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1850039452, P3Thread1of1ForFork2_#t~ite12=|P3Thread1of1ForFork2_#t~ite12_Out1850039452|} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite12] because there is no mapped edge [2019-11-28 18:20:57,752 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L801-->L802: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In599803640 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd4~0_In599803640 256))) (.cse2 (= ~z$r_buff0_thd4~0_Out599803640 ~z$r_buff0_thd4~0_In599803640))) (or (and (not .cse0) (= ~z$r_buff0_thd4~0_Out599803640 0) (not .cse1)) (and .cse2 .cse1) (and .cse0 .cse2))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In599803640, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In599803640} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In599803640, P3Thread1of1ForFork2_#t~ite13=|P3Thread1of1ForFork2_#t~ite13_Out599803640|, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_Out599803640} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite13, ~z$r_buff0_thd4~0] because there is no mapped edge [2019-11-28 18:20:57,752 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L802-->L802-2: Formula: (let ((.cse2 (= (mod ~z$w_buff1_used~0_In387116641 256) 0)) (.cse3 (= 0 (mod ~z$r_buff1_thd4~0_In387116641 256))) (.cse0 (= (mod ~z$w_buff0_used~0_In387116641 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd4~0_In387116641 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P3Thread1of1ForFork2_#t~ite14_Out387116641| 0)) (and (= |P3Thread1of1ForFork2_#t~ite14_Out387116641| ~z$r_buff1_thd4~0_In387116641) (or .cse2 .cse3) (or .cse0 .cse1)))) InVars {~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In387116641, ~z$w_buff0_used~0=~z$w_buff0_used~0_In387116641, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In387116641, ~z$w_buff1_used~0=~z$w_buff1_used~0_In387116641} OutVars{~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In387116641, ~z$w_buff0_used~0=~z$w_buff0_used~0_In387116641, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In387116641, ~z$w_buff1_used~0=~z$w_buff1_used~0_In387116641, P3Thread1of1ForFork2_#t~ite14=|P3Thread1of1ForFork2_#t~ite14_Out387116641|} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite14] because there is no mapped edge [2019-11-28 18:20:57,752 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L802-2-->P3EXIT: Formula: (and (= |v_P3Thread1of1ForFork2_#t~ite14_54| v_~z$r_buff1_thd4~0_130) (= 0 |v_P3Thread1of1ForFork2_#res.base_3|) (= v_~__unbuffered_cnt~0_126 (+ v_~__unbuffered_cnt~0_127 1)) (= 0 |v_P3Thread1of1ForFork2_#res.offset_3|)) InVars {P3Thread1of1ForFork2_#t~ite14=|v_P3Thread1of1ForFork2_#t~ite14_54|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_127} OutVars{P3Thread1of1ForFork2_#res.base=|v_P3Thread1of1ForFork2_#res.base_3|, ~z$r_buff1_thd4~0=v_~z$r_buff1_thd4~0_130, P3Thread1of1ForFork2_#t~ite14=|v_P3Thread1of1ForFork2_#t~ite14_53|, P3Thread1of1ForFork2_#res.offset=|v_P3Thread1of1ForFork2_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_126} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#res.base, ~z$r_buff1_thd4~0, P3Thread1of1ForFork2_#t~ite14, P3Thread1of1ForFork2_#res.offset, ~__unbuffered_cnt~0] because there is no mapped edge [2019-11-28 18:20:57,752 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [673] [673] L827-1-->L833: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_6 256))) (= v_~main$tmp_guard0~0_6 (ite (= (ite (= 4 v_~__unbuffered_cnt~0_21) 1 0) 0) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_21} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_21, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6, ULTIMATE.start_main_#t~nondet18=|v_ULTIMATE.start_main_#t~nondet18_6|} AuxVars[] AssignedVars[~main$tmp_guard0~0, ULTIMATE.start_main_#t~nondet18] because there is no mapped edge [2019-11-28 18:20:57,753 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [721] [721] L833-2-->L833-4: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff1_thd0~0_In126385134 256))) (.cse0 (= (mod ~z$w_buff1_used~0_In126385134 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite19_Out126385134| ~z$w_buff1~0_In126385134) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= |ULTIMATE.start_main_#t~ite19_Out126385134| ~z~0_In126385134)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In126385134, ~z$w_buff1_used~0=~z$w_buff1_used~0_In126385134, ~z$w_buff1~0=~z$w_buff1~0_In126385134, ~z~0=~z~0_In126385134} OutVars{ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out126385134|, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In126385134, ~z$w_buff1_used~0=~z$w_buff1_used~0_In126385134, ~z$w_buff1~0=~z$w_buff1~0_In126385134, ~z~0=~z~0_In126385134} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-11-28 18:20:57,753 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [658] [658] L833-4-->L834: Formula: (= v_~z~0_31 |v_ULTIMATE.start_main_#t~ite19_8|) InVars {ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_8|} OutVars{ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_7|, ~z~0=v_~z~0_31, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_7|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19, ~z~0, ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-11-28 18:20:57,754 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [715] [715] L834-->L834-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In878369281 256))) (.cse0 (= (mod ~z$r_buff0_thd0~0_In878369281 256) 0))) (or (and (= ~z$w_buff0_used~0_In878369281 |ULTIMATE.start_main_#t~ite21_Out878369281|) (or .cse0 .cse1)) (and (= 0 |ULTIMATE.start_main_#t~ite21_Out878369281|) (not .cse1) (not .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In878369281, ~z$w_buff0_used~0=~z$w_buff0_used~0_In878369281} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In878369281, ~z$w_buff0_used~0=~z$w_buff0_used~0_In878369281, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out878369281|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-11-28 18:20:57,754 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [725] [725] L835-->L835-2: Formula: (let ((.cse3 (= (mod ~z$r_buff0_thd0~0_In1326642456 256) 0)) (.cse2 (= (mod ~z$w_buff0_used~0_In1326642456 256) 0)) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In1326642456 256))) (.cse1 (= 0 (mod ~z$r_buff1_thd0~0_In1326642456 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~z$w_buff1_used~0_In1326642456 |ULTIMATE.start_main_#t~ite22_Out1326642456|)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1))) (= 0 |ULTIMATE.start_main_#t~ite22_Out1326642456|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1326642456, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1326642456, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1326642456, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1326642456} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1326642456, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1326642456, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1326642456, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1326642456, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out1326642456|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-11-28 18:20:57,755 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [718] [718] L836-->L836-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd0~0_In-776016827 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In-776016827 256) 0))) (or (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite23_Out-776016827|) (not .cse1)) (and (or .cse0 .cse1) (= ~z$r_buff0_thd0~0_In-776016827 |ULTIMATE.start_main_#t~ite23_Out-776016827|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-776016827, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-776016827} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-776016827, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-776016827, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out-776016827|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-11-28 18:20:57,756 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [711] [711] L837-->L837-2: Formula: (let ((.cse1 (= (mod ~z$w_buff1_used~0_In1068039251 256) 0)) (.cse0 (= (mod ~z$r_buff1_thd0~0_In1068039251 256) 0)) (.cse3 (= (mod ~z$r_buff0_thd0~0_In1068039251 256) 0)) (.cse2 (= (mod ~z$w_buff0_used~0_In1068039251 256) 0))) (or (and (= ~z$r_buff1_thd0~0_In1068039251 |ULTIMATE.start_main_#t~ite24_Out1068039251|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |ULTIMATE.start_main_#t~ite24_Out1068039251|) (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2)))))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1068039251, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1068039251, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1068039251, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1068039251} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1068039251, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1068039251, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1068039251, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out1068039251|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1068039251} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24] because there is no mapped edge [2019-11-28 18:20:57,760 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L849-->L850: Formula: (and (= v_~z$r_buff0_thd0~0_119 v_~z$r_buff0_thd0~0_120) (not (= 0 (mod v_~weak$$choice2~0_29 256)))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_120, ~weak$$choice2~0=v_~weak$$choice2~0_29} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_8|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_119, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_9|, ~weak$$choice2~0=v_~weak$$choice2~0_29, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-11-28 18:20:57,761 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [760] [760] L850-->L850-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-1050911323 256)))) (or (and (= |ULTIMATE.start_main_#t~ite46_Out-1050911323| |ULTIMATE.start_main_#t~ite45_Out-1050911323|) (= |ULTIMATE.start_main_#t~ite45_Out-1050911323| ~z$r_buff1_thd0~0_In-1050911323) .cse0 (let ((.cse1 (= 0 (mod ~z$r_buff0_thd0~0_In-1050911323 256)))) (or (and .cse1 (= (mod ~z$r_buff1_thd0~0_In-1050911323 256) 0)) (and .cse1 (= 0 (mod ~z$w_buff1_used~0_In-1050911323 256))) (= (mod ~z$w_buff0_used~0_In-1050911323 256) 0)))) (and (= |ULTIMATE.start_main_#t~ite46_Out-1050911323| ~z$r_buff1_thd0~0_In-1050911323) (= |ULTIMATE.start_main_#t~ite45_In-1050911323| |ULTIMATE.start_main_#t~ite45_Out-1050911323|) (not .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1050911323, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1050911323, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1050911323, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1050911323, ~weak$$choice2~0=~weak$$choice2~0_In-1050911323, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_In-1050911323|} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1050911323, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1050911323, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1050911323, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1050911323, ULTIMATE.start_main_#t~ite46=|ULTIMATE.start_main_#t~ite46_Out-1050911323|, ~weak$$choice2~0=~weak$$choice2~0_In-1050911323, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_Out-1050911323|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite45] because there is no mapped edge [2019-11-28 18:20:57,761 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [755] [755] L852-->L855-1: Formula: (and (= v_~z$mem_tmp~0_13 v_~z~0_120) (= 0 v_~z$flush_delayed~0_24) (= (mod v_~main$tmp_guard1~0_23 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|) (not (= 0 (mod v_~z$flush_delayed~0_25 256)))) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_13, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_23, ~z$flush_delayed~0=v_~z$flush_delayed~0_25} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_13, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_24|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_23, ~z$flush_delayed~0=v_~z$flush_delayed~0_24, ~z~0=v_~z~0_120, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-11-28 18:20:57,762 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [729] [729] L855-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-11-28 18:20:57,851 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 06:20:57 BasicIcfg [2019-11-28 18:20:57,851 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-28 18:20:57,852 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-28 18:20:57,852 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-28 18:20:57,852 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-28 18:20:57,853 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:20:29" (3/4) ... [2019-11-28 18:20:57,858 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-28 18:20:57,858 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [777] [777] ULTIMATE.startENTRY-->L821: Formula: (let ((.cse0 (store |v_#valid_75| 0 0))) (and (= v_~weak$$choice2~0_146 0) (= v_~z$w_buff0_used~0_885 0) (= v_~z$mem_tmp~0_22 0) (= (select .cse0 |v_ULTIMATE.start_main_~#t1517~0.base_24|) 0) (= v_~z$r_buff1_thd0~0_298 0) (= 0 v_~z$r_buff1_thd2~0_83) (= 0 v_~z$r_buff1_thd4~0_140) (= 0 v_~z$r_buff1_thd1~0_83) (= 0 v_~z$flush_delayed~0_36) (= |v_#memory_int_25| (store |v_#memory_int_26| |v_ULTIMATE.start_main_~#t1517~0.base_24| (store (select |v_#memory_int_26| |v_ULTIMATE.start_main_~#t1517~0.base_24|) |v_ULTIMATE.start_main_~#t1517~0.offset_18| 0))) (= 0 |v_ULTIMATE.start_main_~#t1517~0.offset_18|) (= v_~z$r_buff0_thd3~0_92 0) (= v_~z$read_delayed_var~0.offset_7 0) (< 0 |v_#StackHeapBarrier_18|) (= v_~__unbuffered_p3_EAX~0_100 0) (= v_~z$w_buff0~0_503 0) (= v_~z$w_buff1_used~0_515 0) (= v_~a~0_48 0) (= v_~x~0_57 0) (= v_~z$read_delayed_var~0.base_7 0) (= v_~z$read_delayed~0_7 0) (= v_~z~0_155 0) (= v_~main$tmp_guard1~0_32 0) (= |v_#length_29| (store |v_#length_30| |v_ULTIMATE.start_main_~#t1517~0.base_24| 4)) (= |v_#valid_73| (store .cse0 |v_ULTIMATE.start_main_~#t1517~0.base_24| 1)) (= 0 v_~weak$$choice0~0_16) (= v_~__unbuffered_cnt~0_141 0) (= 0 v_~z$r_buff1_thd3~0_146) (= v_~z$w_buff1~0_306 0) (= v_~z$r_buff0_thd0~0_394 0) (= |v_#NULL.offset_5| 0) (= v_~z$r_buff0_thd2~0_32 0) (= v_~main$tmp_guard0~0_22 0) (= 0 v_~z$r_buff0_thd4~0_161) (= v_~y~0_76 0) (= v_~z$r_buff0_thd1~0_32 0) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t1517~0.base_24|) (= 0 |v_#NULL.base_5|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_75|, #memory_int=|v_#memory_int_26|, #length=|v_#length_30|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_59|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_83, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_41|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_32|, ULTIMATE.start_main_~#t1517~0.offset=|v_ULTIMATE.start_main_~#t1517~0.offset_18|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_35|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_30|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_45|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_60|, ~a~0=v_~a~0_48, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_394, ~z$r_buff0_thd4~0=v_~z$r_buff0_thd4~0_161, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_100, #length=|v_#length_29|, ~z$mem_tmp~0=v_~z$mem_tmp~0_22, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_48|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_114|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_515, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_191|, ~z$flush_delayed~0=v_~z$flush_delayed~0_36, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_35|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_44|, ~weak$$choice0~0=v_~weak$$choice0~0_16, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_38|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_83, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_10|, ULTIMATE.start_main_~#t1519~0.base=|v_ULTIMATE.start_main_~#t1519~0.base_20|, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_7, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_92, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_10|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_141, ~x~0=v_~x~0_57, ULTIMATE.start_main_~#t1520~0.base=|v_ULTIMATE.start_main_~#t1520~0.base_21|, ~z$r_buff1_thd4~0=v_~z$r_buff1_thd4~0_140, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_40|, ~z$read_delayed~0=v_~z$read_delayed~0_7, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_57|, ~z$w_buff1~0=v_~z$w_buff1~0_306, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_32, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_43|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_7, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_31|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_29|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_31|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_51|, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_44|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_298, ULTIMATE.start_main_#t~nondet26=|v_ULTIMATE.start_main_#t~nondet26_25|, ULTIMATE.start_main_~#t1520~0.offset=|v_ULTIMATE.start_main_~#t1520~0.offset_17|, ULTIMATE.start_main_~#t1518~0.base=|v_ULTIMATE.start_main_~#t1518~0.base_22|, ~y~0=v_~y~0_76, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_32, ULTIMATE.start_main_~#t1518~0.offset=|v_ULTIMATE.start_main_~#t1518~0.offset_17|, ULTIMATE.start_main_~#t1517~0.base=|v_ULTIMATE.start_main_~#t1517~0.base_24|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_885, ~z$w_buff0~0=v_~z$w_buff0~0_503, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_39|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_25|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_146, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_122|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_44|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_22, ULTIMATE.start_main_~#t1519~0.offset=|v_ULTIMATE.start_main_~#t1519~0.offset_16|, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_36|, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_35|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_31|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, #valid=|v_#valid_73|, #memory_int=|v_#memory_int_25|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_9|, ULTIMATE.start_main_#t~nondet18=|v_ULTIMATE.start_main_#t~nondet18_23|, ~z~0=v_~z~0_155, ~weak$$choice2~0=v_~weak$$choice2~0_146, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_32} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_~#t1517~0.offset, #NULL.offset, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~a~0, ~z$r_buff0_thd0~0, ~z$r_buff0_thd4~0, ~__unbuffered_p3_EAX~0, #length, ~z$mem_tmp~0, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite35, ~z$w_buff1_used~0, ULTIMATE.start_main_#t~ite37, ~z$flush_delayed~0, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~z$r_buff1_thd1~0, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_~#t1519~0.base, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~x~0, ULTIMATE.start_main_~#t1520~0.base, ~z$r_buff1_thd4~0, ULTIMATE.start_main_#t~ite29, ~z$read_delayed~0, ULTIMATE.start_main_#t~ite46, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite30, ~z$r_buff1_thd0~0, ULTIMATE.start_main_#t~nondet26, ULTIMATE.start_main_~#t1520~0.offset, ULTIMATE.start_main_~#t1518~0.base, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_~#t1518~0.offset, ULTIMATE.start_main_~#t1517~0.base, ~z$w_buff0_used~0, ~z$w_buff0~0, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_~#t1519~0.offset, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ULTIMATE.start_main_#t~nondet18, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-11-28 18:20:57,860 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [732] [732] L821-1-->L823: Formula: (and (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1518~0.base_10| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t1518~0.base_10|) |v_ULTIMATE.start_main_~#t1518~0.offset_9| 1)) |v_#memory_int_13|) (= (select |v_#valid_36| |v_ULTIMATE.start_main_~#t1518~0.base_10|) 0) (= |v_#valid_35| (store |v_#valid_36| |v_ULTIMATE.start_main_~#t1518~0.base_10| 1)) (not (= 0 |v_ULTIMATE.start_main_~#t1518~0.base_10|)) (= 0 |v_ULTIMATE.start_main_~#t1518~0.offset_9|) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t1518~0.base_10| 4)) (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t1518~0.base_10|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_36|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, #length=|v_#length_17|, ULTIMATE.start_main_~#t1518~0.base=|v_ULTIMATE.start_main_~#t1518~0.base_10|, ULTIMATE.start_main_~#t1518~0.offset=|v_ULTIMATE.start_main_~#t1518~0.offset_9|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_#t~nondet15, #length, ULTIMATE.start_main_~#t1518~0.base, ULTIMATE.start_main_~#t1518~0.offset] because there is no mapped edge [2019-11-28 18:20:57,861 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [753] [753] L823-1-->L825: Formula: (and (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t1519~0.base_12|) (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t1519~0.base_12| 4)) (= (select |v_#valid_46| |v_ULTIMATE.start_main_~#t1519~0.base_12|) 0) (not (= |v_ULTIMATE.start_main_~#t1519~0.base_12| 0)) (= |v_#memory_int_17| (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1519~0.base_12| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t1519~0.base_12|) |v_ULTIMATE.start_main_~#t1519~0.offset_10| 2))) (= |v_#valid_45| (store |v_#valid_46| |v_ULTIMATE.start_main_~#t1519~0.base_12| 1)) (= 0 |v_ULTIMATE.start_main_~#t1519~0.offset_10|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_46|, #memory_int=|v_#memory_int_18|, #length=|v_#length_22|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_45|, #memory_int=|v_#memory_int_17|, ULTIMATE.start_main_~#t1519~0.base=|v_ULTIMATE.start_main_~#t1519~0.base_12|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_5|, #length=|v_#length_21|, ULTIMATE.start_main_~#t1519~0.offset=|v_ULTIMATE.start_main_~#t1519~0.offset_10|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_~#t1519~0.base, ULTIMATE.start_main_#t~nondet16, #length, ULTIMATE.start_main_~#t1519~0.offset] because there is no mapped edge [2019-11-28 18:20:57,862 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [743] [743] L825-1-->L827: Formula: (and (= (select |v_#valid_40| |v_ULTIMATE.start_main_~#t1520~0.base_11|) 0) (= (store |v_#valid_40| |v_ULTIMATE.start_main_~#t1520~0.base_11| 1) |v_#valid_39|) (= |v_ULTIMATE.start_main_~#t1520~0.offset_10| 0) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t1520~0.base_11|) (not (= |v_ULTIMATE.start_main_~#t1520~0.base_11| 0)) (= |v_#length_19| (store |v_#length_20| |v_ULTIMATE.start_main_~#t1520~0.base_11| 4)) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1520~0.base_11| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t1520~0.base_11|) |v_ULTIMATE.start_main_~#t1520~0.offset_10| 3)) |v_#memory_int_15|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_16|, #length=|v_#length_20|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_39|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_~#t1520~0.offset=|v_ULTIMATE.start_main_~#t1520~0.offset_10|, #length=|v_#length_19|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_6|, ULTIMATE.start_main_~#t1520~0.base=|v_ULTIMATE.start_main_~#t1520~0.base_11|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_~#t1520~0.offset, #length, ULTIMATE.start_main_#t~nondet17, ULTIMATE.start_main_~#t1520~0.base] because there is no mapped edge [2019-11-28 18:20:57,862 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [691] [691] P3ENTRY-->L4-3: Formula: (and (not (= v_P3Thread1of1ForFork2___VERIFIER_assert_~expression_11 0)) (= v_P3Thread1of1ForFork2_~arg.base_9 |v_P3Thread1of1ForFork2_#in~arg.base_11|) (= v_P3Thread1of1ForFork2___VERIFIER_assert_~expression_11 |v_P3Thread1of1ForFork2___VERIFIER_assert_#in~expression_9|) (= (ite (not (and (not (= (mod v_~z$w_buff0_used~0_218 256) 0)) (not (= (mod v_~z$w_buff1_used~0_99 256) 0)))) 1 0) |v_P3Thread1of1ForFork2___VERIFIER_assert_#in~expression_9|) (= |v_P3Thread1of1ForFork2_#in~arg.offset_11| v_P3Thread1of1ForFork2_~arg.offset_9) (= v_~z$w_buff0_used~0_218 1) (= v_~z$w_buff0~0_48 v_~z$w_buff1~0_32) (= 2 v_~z$w_buff0~0_47) (= v_~z$w_buff0_used~0_219 v_~z$w_buff1_used~0_99)) InVars {~z$w_buff0_used~0=v_~z$w_buff0_used~0_219, ~z$w_buff0~0=v_~z$w_buff0~0_48, P3Thread1of1ForFork2_#in~arg.offset=|v_P3Thread1of1ForFork2_#in~arg.offset_11|, P3Thread1of1ForFork2_#in~arg.base=|v_P3Thread1of1ForFork2_#in~arg.base_11|} OutVars{P3Thread1of1ForFork2___VERIFIER_assert_~expression=v_P3Thread1of1ForFork2___VERIFIER_assert_~expression_11, P3Thread1of1ForFork2_~arg.offset=v_P3Thread1of1ForFork2_~arg.offset_9, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_218, ~z$w_buff0~0=v_~z$w_buff0~0_47, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_99, P3Thread1of1ForFork2_#in~arg.offset=|v_P3Thread1of1ForFork2_#in~arg.offset_11|, ~z$w_buff1~0=v_~z$w_buff1~0_32, P3Thread1of1ForFork2___VERIFIER_assert_#in~expression=|v_P3Thread1of1ForFork2___VERIFIER_assert_#in~expression_9|, P3Thread1of1ForFork2_~arg.base=v_P3Thread1of1ForFork2_~arg.base_9, P3Thread1of1ForFork2_#in~arg.base=|v_P3Thread1of1ForFork2_#in~arg.base_11|} AuxVars[] AssignedVars[P3Thread1of1ForFork2___VERIFIER_assert_~expression, P3Thread1of1ForFork2_~arg.offset, ~z$w_buff0_used~0, ~z$w_buff0~0, ~z$w_buff1_used~0, ~z$w_buff1~0, P3Thread1of1ForFork2___VERIFIER_assert_#in~expression, P3Thread1of1ForFork2_~arg.base] because there is no mapped edge [2019-11-28 18:20:57,863 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [757] [757] P0ENTRY-->P0EXIT: Formula: (and (= v_~x~0_44 1) (= v_~__unbuffered_cnt~0_102 (+ v_~__unbuffered_cnt~0_103 1)) (= v_P0Thread1of1ForFork3_~arg.base_17 |v_P0Thread1of1ForFork3_#in~arg.base_19|) (= v_~a~0_40 1) (= |v_P0Thread1of1ForFork3_#res.offset_9| 0) (= |v_P0Thread1of1ForFork3_#in~arg.offset_19| v_P0Thread1of1ForFork3_~arg.offset_17) (= 0 |v_P0Thread1of1ForFork3_#res.base_9|)) InVars {P0Thread1of1ForFork3_#in~arg.offset=|v_P0Thread1of1ForFork3_#in~arg.offset_19|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_103, P0Thread1of1ForFork3_#in~arg.base=|v_P0Thread1of1ForFork3_#in~arg.base_19|} OutVars{~a~0=v_~a~0_40, P0Thread1of1ForFork3_#in~arg.offset=|v_P0Thread1of1ForFork3_#in~arg.offset_19|, P0Thread1of1ForFork3_~arg.base=v_P0Thread1of1ForFork3_~arg.base_17, P0Thread1of1ForFork3_#res.base=|v_P0Thread1of1ForFork3_#res.base_9|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_102, P0Thread1of1ForFork3_#res.offset=|v_P0Thread1of1ForFork3_#res.offset_9|, P0Thread1of1ForFork3_~arg.offset=v_P0Thread1of1ForFork3_~arg.offset_17, P0Thread1of1ForFork3_#in~arg.base=|v_P0Thread1of1ForFork3_#in~arg.base_19|, ~x~0=v_~x~0_44} AuxVars[] AssignedVars[~a~0, P0Thread1of1ForFork3_~arg.base, P0Thread1of1ForFork3_#res.base, ~__unbuffered_cnt~0, P0Thread1of1ForFork3_#res.offset, P0Thread1of1ForFork3_~arg.offset, ~x~0] because there is no mapped edge [2019-11-28 18:20:57,863 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [746] [746] P1ENTRY-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork0_#res.offset_3|) (= v_~x~0_39 2) (= v_~__unbuffered_cnt~0_78 (+ v_~__unbuffered_cnt~0_79 1)) (= v_~y~0_50 1) (= 0 |v_P1Thread1of1ForFork0_#res.base_3|) (= |v_P1Thread1of1ForFork0_#in~arg.base_10| v_P1Thread1of1ForFork0_~arg.base_8) (= |v_P1Thread1of1ForFork0_#in~arg.offset_10| v_P1Thread1of1ForFork0_~arg.offset_8)) InVars {P1Thread1of1ForFork0_#in~arg.base=|v_P1Thread1of1ForFork0_#in~arg.base_10|, P1Thread1of1ForFork0_#in~arg.offset=|v_P1Thread1of1ForFork0_#in~arg.offset_10|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_79} OutVars{P1Thread1of1ForFork0_~arg.offset=v_P1Thread1of1ForFork0_~arg.offset_8, P1Thread1of1ForFork0_~arg.base=v_P1Thread1of1ForFork0_~arg.base_8, P1Thread1of1ForFork0_#in~arg.base=|v_P1Thread1of1ForFork0_#in~arg.base_10|, P1Thread1of1ForFork0_#in~arg.offset=|v_P1Thread1of1ForFork0_#in~arg.offset_10|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_78, P1Thread1of1ForFork0_#res.offset=|v_P1Thread1of1ForFork0_#res.offset_3|, ~y~0=v_~y~0_50, P1Thread1of1ForFork0_#res.base=|v_P1Thread1of1ForFork0_#res.base_3|, ~x~0=v_~x~0_39} AuxVars[] AssignedVars[P1Thread1of1ForFork0_~arg.offset, P1Thread1of1ForFork0_~arg.base, ~__unbuffered_cnt~0, P1Thread1of1ForFork0_#res.offset, ~y~0, P1Thread1of1ForFork0_#res.base, ~x~0] because there is no mapped edge [2019-11-28 18:20:57,864 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [714] [714] L768-2-->L768-5: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff1_thd3~0_In1745659752 256))) (.cse1 (= (mod ~z$w_buff1_used~0_In1745659752 256) 0)) (.cse2 (= |P2Thread1of1ForFork1_#t~ite4_Out1745659752| |P2Thread1of1ForFork1_#t~ite3_Out1745659752|))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork1_#t~ite3_Out1745659752| ~z~0_In1745659752) .cse2) (and (= ~z$w_buff1~0_In1745659752 |P2Thread1of1ForFork1_#t~ite3_Out1745659752|) (not .cse0) (not .cse1) .cse2))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1745659752, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1745659752, ~z$w_buff1~0=~z$w_buff1~0_In1745659752, ~z~0=~z~0_In1745659752} OutVars{P2Thread1of1ForFork1_#t~ite4=|P2Thread1of1ForFork1_#t~ite4_Out1745659752|, P2Thread1of1ForFork1_#t~ite3=|P2Thread1of1ForFork1_#t~ite3_Out1745659752|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1745659752, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1745659752, ~z$w_buff1~0=~z$w_buff1~0_In1745659752, ~z~0=~z~0_In1745659752} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite4, P2Thread1of1ForFork1_#t~ite3] because there is no mapped edge [2019-11-28 18:20:57,865 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [722] [722] L769-->L769-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In305584938 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In305584938 256)))) (or (and (= |P2Thread1of1ForFork1_#t~ite5_Out305584938| ~z$w_buff0_used~0_In305584938) (or .cse0 .cse1)) (and (= 0 |P2Thread1of1ForFork1_#t~ite5_Out305584938|) (not .cse1) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In305584938, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In305584938} OutVars{P2Thread1of1ForFork1_#t~ite5=|P2Thread1of1ForFork1_#t~ite5_Out305584938|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In305584938, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In305584938} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite5] because there is no mapped edge [2019-11-28 18:20:57,866 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [724] [724] L770-->L770-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff1_used~0_In-858612910 256))) (.cse1 (= 0 (mod ~z$r_buff1_thd3~0_In-858612910 256))) (.cse2 (= (mod ~z$r_buff0_thd3~0_In-858612910 256) 0)) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In-858612910 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork1_#t~ite6_Out-858612910|)) (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~z$w_buff1_used~0_In-858612910 |P2Thread1of1ForFork1_#t~ite6_Out-858612910|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-858612910, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-858612910, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-858612910, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-858612910} OutVars{P2Thread1of1ForFork1_#t~ite6=|P2Thread1of1ForFork1_#t~ite6_Out-858612910|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-858612910, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-858612910, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-858612910, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-858612910} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite6] because there is no mapped edge [2019-11-28 18:20:57,866 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [710] [710] L771-->L771-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd3~0_In1252880533 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In1252880533 256) 0))) (or (and (= |P2Thread1of1ForFork1_#t~ite7_Out1252880533| ~z$r_buff0_thd3~0_In1252880533) (or .cse0 .cse1)) (and (= |P2Thread1of1ForFork1_#t~ite7_Out1252880533| 0) (not .cse0) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1252880533, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1252880533} OutVars{P2Thread1of1ForFork1_#t~ite7=|P2Thread1of1ForFork1_#t~ite7_Out1252880533|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1252880533, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1252880533} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite7] because there is no mapped edge [2019-11-28 18:20:57,868 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [708] [708] L772-->L772-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff1_used~0_In886166393 256))) (.cse1 (= 0 (mod ~z$r_buff1_thd3~0_In886166393 256))) (.cse3 (= 0 (mod ~z$r_buff0_thd3~0_In886166393 256))) (.cse2 (= (mod ~z$w_buff0_used~0_In886166393 256) 0))) (or (and (= 0 |P2Thread1of1ForFork1_#t~ite8_Out886166393|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (or .cse3 .cse2) (= |P2Thread1of1ForFork1_#t~ite8_Out886166393| ~z$r_buff1_thd3~0_In886166393)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In886166393, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In886166393, ~z$w_buff1_used~0=~z$w_buff1_used~0_In886166393, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In886166393} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In886166393, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In886166393, ~z$w_buff1_used~0=~z$w_buff1_used~0_In886166393, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In886166393, P2Thread1of1ForFork1_#t~ite8=|P2Thread1of1ForFork1_#t~ite8_Out886166393|} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#t~ite8] because there is no mapped edge [2019-11-28 18:20:57,868 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [752] [752] L772-2-->P2EXIT: Formula: (and (= 0 |v_P2Thread1of1ForFork1_#res.offset_3|) (= v_~z$r_buff1_thd3~0_127 |v_P2Thread1of1ForFork1_#t~ite8_44|) (= v_~__unbuffered_cnt~0_100 (+ v_~__unbuffered_cnt~0_101 1)) (= 0 |v_P2Thread1of1ForFork1_#res.base_3|)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_101, P2Thread1of1ForFork1_#t~ite8=|v_P2Thread1of1ForFork1_#t~ite8_44|} OutVars{P2Thread1of1ForFork1_#res.base=|v_P2Thread1of1ForFork1_#res.base_3|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_127, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_100, P2Thread1of1ForFork1_#res.offset=|v_P2Thread1of1ForFork1_#res.offset_3|, P2Thread1of1ForFork1_#t~ite8=|v_P2Thread1of1ForFork1_#t~ite8_43|} AuxVars[] AssignedVars[P2Thread1of1ForFork1_#res.base, ~z$r_buff1_thd3~0, ~__unbuffered_cnt~0, P2Thread1of1ForFork1_#res.offset, P2Thread1of1ForFork1_#t~ite8] because there is no mapped edge [2019-11-28 18:20:57,869 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [727] [727] L799-->L799-2: Formula: (let ((.cse1 (= (mod ~z$r_buff0_thd4~0_In-1673649629 256) 0)) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1673649629 256)))) (or (and (= |P3Thread1of1ForFork2_#t~ite11_Out-1673649629| 0) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= |P3Thread1of1ForFork2_#t~ite11_Out-1673649629| ~z$w_buff0_used~0_In-1673649629)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1673649629, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-1673649629} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1673649629, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In-1673649629, P3Thread1of1ForFork2_#t~ite11=|P3Thread1of1ForFork2_#t~ite11_Out-1673649629|} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite11] because there is no mapped edge [2019-11-28 18:20:57,870 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [712] [712] L800-->L800-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff1_thd4~0_In1850039452 256))) (.cse1 (= (mod ~z$w_buff1_used~0_In1850039452 256) 0)) (.cse2 (= (mod ~z$r_buff0_thd4~0_In1850039452 256) 0)) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In1850039452 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P3Thread1of1ForFork2_#t~ite12_Out1850039452|)) (and (or .cse0 .cse1) (= ~z$w_buff1_used~0_In1850039452 |P3Thread1of1ForFork2_#t~ite12_Out1850039452|) (or .cse2 .cse3)))) InVars {~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In1850039452, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1850039452, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In1850039452, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1850039452} OutVars{~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In1850039452, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1850039452, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In1850039452, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1850039452, P3Thread1of1ForFork2_#t~ite12=|P3Thread1of1ForFork2_#t~ite12_Out1850039452|} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite12] because there is no mapped edge [2019-11-28 18:20:57,871 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L801-->L802: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In599803640 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd4~0_In599803640 256))) (.cse2 (= ~z$r_buff0_thd4~0_Out599803640 ~z$r_buff0_thd4~0_In599803640))) (or (and (not .cse0) (= ~z$r_buff0_thd4~0_Out599803640 0) (not .cse1)) (and .cse2 .cse1) (and .cse0 .cse2))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In599803640, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In599803640} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In599803640, P3Thread1of1ForFork2_#t~ite13=|P3Thread1of1ForFork2_#t~ite13_Out599803640|, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_Out599803640} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite13, ~z$r_buff0_thd4~0] because there is no mapped edge [2019-11-28 18:20:57,871 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L802-->L802-2: Formula: (let ((.cse2 (= (mod ~z$w_buff1_used~0_In387116641 256) 0)) (.cse3 (= 0 (mod ~z$r_buff1_thd4~0_In387116641 256))) (.cse0 (= (mod ~z$w_buff0_used~0_In387116641 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd4~0_In387116641 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P3Thread1of1ForFork2_#t~ite14_Out387116641| 0)) (and (= |P3Thread1of1ForFork2_#t~ite14_Out387116641| ~z$r_buff1_thd4~0_In387116641) (or .cse2 .cse3) (or .cse0 .cse1)))) InVars {~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In387116641, ~z$w_buff0_used~0=~z$w_buff0_used~0_In387116641, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In387116641, ~z$w_buff1_used~0=~z$w_buff1_used~0_In387116641} OutVars{~z$r_buff1_thd4~0=~z$r_buff1_thd4~0_In387116641, ~z$w_buff0_used~0=~z$w_buff0_used~0_In387116641, ~z$r_buff0_thd4~0=~z$r_buff0_thd4~0_In387116641, ~z$w_buff1_used~0=~z$w_buff1_used~0_In387116641, P3Thread1of1ForFork2_#t~ite14=|P3Thread1of1ForFork2_#t~ite14_Out387116641|} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#t~ite14] because there is no mapped edge [2019-11-28 18:20:57,871 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L802-2-->P3EXIT: Formula: (and (= |v_P3Thread1of1ForFork2_#t~ite14_54| v_~z$r_buff1_thd4~0_130) (= 0 |v_P3Thread1of1ForFork2_#res.base_3|) (= v_~__unbuffered_cnt~0_126 (+ v_~__unbuffered_cnt~0_127 1)) (= 0 |v_P3Thread1of1ForFork2_#res.offset_3|)) InVars {P3Thread1of1ForFork2_#t~ite14=|v_P3Thread1of1ForFork2_#t~ite14_54|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_127} OutVars{P3Thread1of1ForFork2_#res.base=|v_P3Thread1of1ForFork2_#res.base_3|, ~z$r_buff1_thd4~0=v_~z$r_buff1_thd4~0_130, P3Thread1of1ForFork2_#t~ite14=|v_P3Thread1of1ForFork2_#t~ite14_53|, P3Thread1of1ForFork2_#res.offset=|v_P3Thread1of1ForFork2_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_126} AuxVars[] AssignedVars[P3Thread1of1ForFork2_#res.base, ~z$r_buff1_thd4~0, P3Thread1of1ForFork2_#t~ite14, P3Thread1of1ForFork2_#res.offset, ~__unbuffered_cnt~0] because there is no mapped edge [2019-11-28 18:20:57,871 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [673] [673] L827-1-->L833: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_6 256))) (= v_~main$tmp_guard0~0_6 (ite (= (ite (= 4 v_~__unbuffered_cnt~0_21) 1 0) 0) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_21} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_21, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6, ULTIMATE.start_main_#t~nondet18=|v_ULTIMATE.start_main_#t~nondet18_6|} AuxVars[] AssignedVars[~main$tmp_guard0~0, ULTIMATE.start_main_#t~nondet18] because there is no mapped edge [2019-11-28 18:20:57,872 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [721] [721] L833-2-->L833-4: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff1_thd0~0_In126385134 256))) (.cse0 (= (mod ~z$w_buff1_used~0_In126385134 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite19_Out126385134| ~z$w_buff1~0_In126385134) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= |ULTIMATE.start_main_#t~ite19_Out126385134| ~z~0_In126385134)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In126385134, ~z$w_buff1_used~0=~z$w_buff1_used~0_In126385134, ~z$w_buff1~0=~z$w_buff1~0_In126385134, ~z~0=~z~0_In126385134} OutVars{ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out126385134|, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In126385134, ~z$w_buff1_used~0=~z$w_buff1_used~0_In126385134, ~z$w_buff1~0=~z$w_buff1~0_In126385134, ~z~0=~z~0_In126385134} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-11-28 18:20:57,872 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [658] [658] L833-4-->L834: Formula: (= v_~z~0_31 |v_ULTIMATE.start_main_#t~ite19_8|) InVars {ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_8|} OutVars{ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_7|, ~z~0=v_~z~0_31, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_7|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19, ~z~0, ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-11-28 18:20:57,872 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [715] [715] L834-->L834-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In878369281 256))) (.cse0 (= (mod ~z$r_buff0_thd0~0_In878369281 256) 0))) (or (and (= ~z$w_buff0_used~0_In878369281 |ULTIMATE.start_main_#t~ite21_Out878369281|) (or .cse0 .cse1)) (and (= 0 |ULTIMATE.start_main_#t~ite21_Out878369281|) (not .cse1) (not .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In878369281, ~z$w_buff0_used~0=~z$w_buff0_used~0_In878369281} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In878369281, ~z$w_buff0_used~0=~z$w_buff0_used~0_In878369281, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out878369281|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-11-28 18:20:57,873 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [725] [725] L835-->L835-2: Formula: (let ((.cse3 (= (mod ~z$r_buff0_thd0~0_In1326642456 256) 0)) (.cse2 (= (mod ~z$w_buff0_used~0_In1326642456 256) 0)) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In1326642456 256))) (.cse1 (= 0 (mod ~z$r_buff1_thd0~0_In1326642456 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~z$w_buff1_used~0_In1326642456 |ULTIMATE.start_main_#t~ite22_Out1326642456|)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1))) (= 0 |ULTIMATE.start_main_#t~ite22_Out1326642456|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1326642456, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1326642456, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1326642456, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1326642456} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1326642456, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1326642456, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1326642456, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1326642456, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out1326642456|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-11-28 18:20:57,874 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [718] [718] L836-->L836-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd0~0_In-776016827 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In-776016827 256) 0))) (or (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite23_Out-776016827|) (not .cse1)) (and (or .cse0 .cse1) (= ~z$r_buff0_thd0~0_In-776016827 |ULTIMATE.start_main_#t~ite23_Out-776016827|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-776016827, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-776016827} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-776016827, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-776016827, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out-776016827|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-11-28 18:20:57,875 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [711] [711] L837-->L837-2: Formula: (let ((.cse1 (= (mod ~z$w_buff1_used~0_In1068039251 256) 0)) (.cse0 (= (mod ~z$r_buff1_thd0~0_In1068039251 256) 0)) (.cse3 (= (mod ~z$r_buff0_thd0~0_In1068039251 256) 0)) (.cse2 (= (mod ~z$w_buff0_used~0_In1068039251 256) 0))) (or (and (= ~z$r_buff1_thd0~0_In1068039251 |ULTIMATE.start_main_#t~ite24_Out1068039251|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |ULTIMATE.start_main_#t~ite24_Out1068039251|) (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2)))))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1068039251, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1068039251, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1068039251, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1068039251} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1068039251, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1068039251, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1068039251, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out1068039251|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1068039251} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24] because there is no mapped edge [2019-11-28 18:20:57,880 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L849-->L850: Formula: (and (= v_~z$r_buff0_thd0~0_119 v_~z$r_buff0_thd0~0_120) (not (= 0 (mod v_~weak$$choice2~0_29 256)))) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_120, ~weak$$choice2~0=v_~weak$$choice2~0_29} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_8|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_119, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_9|, ~weak$$choice2~0=v_~weak$$choice2~0_29, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-11-28 18:20:57,881 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [760] [760] L850-->L850-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-1050911323 256)))) (or (and (= |ULTIMATE.start_main_#t~ite46_Out-1050911323| |ULTIMATE.start_main_#t~ite45_Out-1050911323|) (= |ULTIMATE.start_main_#t~ite45_Out-1050911323| ~z$r_buff1_thd0~0_In-1050911323) .cse0 (let ((.cse1 (= 0 (mod ~z$r_buff0_thd0~0_In-1050911323 256)))) (or (and .cse1 (= (mod ~z$r_buff1_thd0~0_In-1050911323 256) 0)) (and .cse1 (= 0 (mod ~z$w_buff1_used~0_In-1050911323 256))) (= (mod ~z$w_buff0_used~0_In-1050911323 256) 0)))) (and (= |ULTIMATE.start_main_#t~ite46_Out-1050911323| ~z$r_buff1_thd0~0_In-1050911323) (= |ULTIMATE.start_main_#t~ite45_In-1050911323| |ULTIMATE.start_main_#t~ite45_Out-1050911323|) (not .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1050911323, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1050911323, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1050911323, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1050911323, ~weak$$choice2~0=~weak$$choice2~0_In-1050911323, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_In-1050911323|} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1050911323, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1050911323, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1050911323, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1050911323, ULTIMATE.start_main_#t~ite46=|ULTIMATE.start_main_#t~ite46_Out-1050911323|, ~weak$$choice2~0=~weak$$choice2~0_In-1050911323, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_Out-1050911323|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite45] because there is no mapped edge [2019-11-28 18:20:57,882 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [755] [755] L852-->L855-1: Formula: (and (= v_~z$mem_tmp~0_13 v_~z~0_120) (= 0 v_~z$flush_delayed~0_24) (= (mod v_~main$tmp_guard1~0_23 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|) (not (= 0 (mod v_~z$flush_delayed~0_25 256)))) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_13, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_23, ~z$flush_delayed~0=v_~z$flush_delayed~0_25} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_13, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_24|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_23, ~z$flush_delayed~0=v_~z$flush_delayed~0_24, ~z~0=v_~z~0_120, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47, ~z$flush_delayed~0, ~z~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-11-28 18:20:57,882 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [729] [729] L855-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-11-28 18:20:58,002 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2019-11-28 18:20:58,003 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-28 18:20:58,005 INFO L168 Benchmark]: Toolchain (without parser) took 30427.42 ms. Allocated memory was 1.0 GB in the beginning and 2.6 GB in the end (delta: 1.6 GB). Free memory was 949.6 MB in the beginning and 568.7 MB in the end (delta: 381.0 MB). Peak memory consumption was 2.0 GB. Max. memory is 11.5 GB. [2019-11-28 18:20:58,005 INFO L168 Benchmark]: CDTParser took 0.29 ms. Allocated memory is still 1.0 GB. Free memory is still 981.8 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 18:20:58,006 INFO L168 Benchmark]: CACSL2BoogieTranslator took 735.05 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 134.7 MB). Free memory was 949.6 MB in the beginning and 1.1 GB in the end (delta: -147.6 MB). Peak memory consumption was 20.6 MB. Max. memory is 11.5 GB. [2019-11-28 18:20:58,006 INFO L168 Benchmark]: Boogie Procedure Inliner took 85.08 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. [2019-11-28 18:20:58,007 INFO L168 Benchmark]: Boogie Preprocessor took 39.76 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 18:20:58,007 INFO L168 Benchmark]: RCFGBuilder took 872.52 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 51.7 MB). Peak memory consumption was 51.7 MB. Max. memory is 11.5 GB. [2019-11-28 18:20:58,008 INFO L168 Benchmark]: TraceAbstraction took 28538.07 ms. Allocated memory was 1.2 GB in the beginning and 2.6 GB in the end (delta: 1.5 GB). Free memory was 1.0 GB in the beginning and 595.7 MB in the end (delta: 443.0 MB). Peak memory consumption was 1.9 GB. Max. memory is 11.5 GB. [2019-11-28 18:20:58,009 INFO L168 Benchmark]: Witness Printer took 151.15 ms. Allocated memory is still 2.6 GB. Free memory was 595.7 MB in the beginning and 568.7 MB in the end (delta: 27.0 MB). Peak memory consumption was 27.0 MB. Max. memory is 11.5 GB. [2019-11-28 18:20:58,012 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.29 ms. Allocated memory is still 1.0 GB. Free memory is still 981.8 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 735.05 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 134.7 MB). Free memory was 949.6 MB in the beginning and 1.1 GB in the end (delta: -147.6 MB). Peak memory consumption was 20.6 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 85.08 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 39.76 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 872.52 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 51.7 MB). Peak memory consumption was 51.7 MB. Max. memory is 11.5 GB. * TraceAbstraction took 28538.07 ms. Allocated memory was 1.2 GB in the beginning and 2.6 GB in the end (delta: 1.5 GB). Free memory was 1.0 GB in the beginning and 595.7 MB in the end (delta: 443.0 MB). Peak memory consumption was 1.9 GB. Max. memory is 11.5 GB. * Witness Printer took 151.15 ms. Allocated memory is still 2.6 GB. Free memory was 595.7 MB in the beginning and 568.7 MB in the end (delta: 27.0 MB). Peak memory consumption was 27.0 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 5.6s, 178 ProgramPointsBefore, 91 ProgramPointsAfterwards, 206 TransitionsBefore, 100 TransitionsAfterwards, 12668 CoEnabledTransitionPairs, 8 FixpointIterations, 34 TrivialSequentialCompositions, 49 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 36 ConcurrentYvCompositions, 24 ChoiceCompositions, 4617 VarBasedMoverChecksPositive, 237 VarBasedMoverChecksNegative, 66 SemBasedMoverChecksPositive, 231 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 1.6s, 0 MoverChecksTotal, 56276 CheckedPairsTotal, 119 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L821] FCALL, FORK 0 pthread_create(&t1517, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L823] FCALL, FORK 0 pthread_create(&t1518, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L825] FCALL, FORK 0 pthread_create(&t1519, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L827] FCALL, FORK 0 pthread_create(&t1520, ((void *)0), P3, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L787] 4 z$r_buff1_thd0 = z$r_buff0_thd0 [L788] 4 z$r_buff1_thd1 = z$r_buff0_thd1 [L789] 4 z$r_buff1_thd2 = z$r_buff0_thd2 [L790] 4 z$r_buff1_thd3 = z$r_buff0_thd3 [L791] 4 z$r_buff1_thd4 = z$r_buff0_thd4 [L792] 4 z$r_buff0_thd4 = (_Bool)1 [L795] 4 __unbuffered_p3_EAX = a VAL [__unbuffered_cnt=0, __unbuffered_p3_EAX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L762] 3 y = 2 [L765] 3 z = 1 VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=2, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, z=1, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L768] EXPR 3 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=2, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, z=1, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L768] 3 z = z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) [L769] 3 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used [L770] 3 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used [L771] 3 z$r_buff0_thd3 = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 [L798] EXPR 4 z$w_buff0_used && z$r_buff0_thd4 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd4 ? z$w_buff1 : z) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, z=1, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L798] 4 z = z$w_buff0_used && z$r_buff0_thd4 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd4 ? z$w_buff1 : z) [L799] 4 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd4 ? (_Bool)0 : z$w_buff0_used [L800] 4 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd4 || z$w_buff1_used && z$r_buff1_thd4 ? (_Bool)0 : z$w_buff1_used [L833] 0 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, z=2, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L834] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L835] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L836] 0 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 [L837] 0 z$r_buff1_thd0 = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 [L840] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L841] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L842] 0 z$flush_delayed = weak$$choice2 [L843] 0 z$mem_tmp = z VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L844] EXPR 0 !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L844] 0 z = !z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff1) [L845] EXPR 0 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L845] 0 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : z$w_buff0)) [L846] EXPR 0 weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff1 : z$w_buff1)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L846] 0 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff1 : z$w_buff1)) [L847] EXPR 0 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L847] 0 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used)) [L848] EXPR 0 weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L848] 0 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L850] 0 z$r_buff1_thd0 = weak$$choice2 ? z$r_buff1_thd0 : (!z$w_buff0_used || !z$r_buff0_thd0 && !z$w_buff1_used || !z$r_buff0_thd0 && !z$r_buff1_thd0 ? z$r_buff1_thd0 : (z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L851] 0 main$tmp_guard1 = !(x == 2 && y == 2 && z == 2 && __unbuffered_p3_EAX == 0) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p3_EAX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, z=2, z$flush_delayed=1, z$mem_tmp=2, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff0_thd4=1, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$r_buff1_thd4=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=2, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 5 procedures, 166 locations, 2 error locations. Result: UNSAFE, OverallTime: 28.2s, OverallIterations: 17, TraceHistogramMax: 1, AutomataDifference: 5.8s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 1898 SDtfs, 1675 SDslu, 3505 SDs, 0 SdLazy, 1631 SolverSat, 132 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.7s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 99 GetRequests, 20 SyntacticMatches, 8 SemanticMatches, 71 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 94 ImplicationChecksByTransitivity, 0.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=51342occurred in iteration=4, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 11.1s AutomataMinimizationTime, 16 MinimizatonAttempts, 30429 StatesRemovedByMinimization, 10 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.4s SatisfiabilityAnalysisTime, 1.3s InterpolantComputationTime, 723 NumberOfCodeBlocks, 723 NumberOfCodeBlocksAsserted, 17 NumberOfCheckSat, 647 ConstructedInterpolants, 0 QuantifiedInterpolants, 119938 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 16 InterpolantComputations, 16 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...