./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.1.ufo.UNBOUNDED.pals.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx12G -Xms1G -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.1.ufo.UNBOUNDED.pals.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 41aeb4b3eafc96a3464e4411965bc0b5575f7ae7 .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-11-28 17:33:14,499 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-28 17:33:14,502 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-28 17:33:14,519 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-28 17:33:14,519 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-28 17:33:14,521 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-28 17:33:14,522 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-28 17:33:14,524 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-28 17:33:14,526 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-28 17:33:14,527 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-28 17:33:14,528 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-28 17:33:14,530 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-28 17:33:14,530 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-28 17:33:14,531 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-28 17:33:14,532 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-28 17:33:14,533 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-28 17:33:14,534 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-28 17:33:14,535 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-28 17:33:14,537 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-28 17:33:14,539 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-28 17:33:14,541 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-28 17:33:14,542 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-28 17:33:14,543 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-28 17:33:14,544 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-28 17:33:14,546 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-28 17:33:14,547 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-28 17:33:14,547 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-28 17:33:14,548 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-28 17:33:14,548 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-28 17:33:14,550 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-28 17:33:14,550 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-28 17:33:14,551 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-28 17:33:14,551 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-28 17:33:14,552 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-28 17:33:14,553 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-28 17:33:14,554 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-28 17:33:14,555 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-28 17:33:14,555 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-28 17:33:14,555 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-28 17:33:14,556 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-28 17:33:14,557 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-28 17:33:14,558 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-28 17:33:14,575 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-28 17:33:14,576 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-28 17:33:14,578 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-28 17:33:14,579 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-28 17:33:14,579 INFO L138 SettingsManager]: * Use SBE=true [2019-11-28 17:33:14,579 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-28 17:33:14,580 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-28 17:33:14,580 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-28 17:33:14,580 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-28 17:33:14,580 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-28 17:33:14,581 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-28 17:33:14,582 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-28 17:33:14,582 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-28 17:33:14,583 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-28 17:33:14,583 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-28 17:33:14,583 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-28 17:33:14,583 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-28 17:33:14,584 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-28 17:33:14,584 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-28 17:33:14,584 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-28 17:33:14,585 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-28 17:33:14,585 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 17:33:14,586 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-28 17:33:14,586 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-28 17:33:14,586 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-28 17:33:14,587 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-28 17:33:14,587 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-28 17:33:14,587 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-28 17:33:14,587 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-11-28 17:33:14,588 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 41aeb4b3eafc96a3464e4411965bc0b5575f7ae7 [2019-11-28 17:33:14,997 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-28 17:33:15,013 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-28 17:33:15,017 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-28 17:33:15,020 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-28 17:33:15,021 INFO L275 PluginConnector]: CDTParser initialized [2019-11-28 17:33:15,022 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.1.ufo.UNBOUNDED.pals.c [2019-11-28 17:33:15,095 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/263b2fb55/cf57df356d524ec9ad9db7bc6e391447/FLAG446b4fb2c [2019-11-28 17:33:15,644 INFO L306 CDTParser]: Found 1 translation units. [2019-11-28 17:33:15,645 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.1.ufo.UNBOUNDED.pals.c [2019-11-28 17:33:15,658 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/263b2fb55/cf57df356d524ec9ad9db7bc6e391447/FLAG446b4fb2c [2019-11-28 17:33:15,912 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/263b2fb55/cf57df356d524ec9ad9db7bc6e391447 [2019-11-28 17:33:15,915 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-28 17:33:15,917 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-28 17:33:15,918 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-28 17:33:15,919 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-28 17:33:15,921 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-28 17:33:15,922 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 05:33:15" (1/1) ... [2019-11-28 17:33:15,925 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5596f513 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:33:15, skipping insertion in model container [2019-11-28 17:33:15,926 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 05:33:15" (1/1) ... [2019-11-28 17:33:15,934 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-11-28 17:33:15,985 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-11-28 17:33:16,426 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 17:33:16,435 INFO L203 MainTranslator]: Completed pre-run [2019-11-28 17:33:16,522 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 17:33:16,546 INFO L208 MainTranslator]: Completed translation [2019-11-28 17:33:16,547 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:33:16 WrapperNode [2019-11-28 17:33:16,548 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-28 17:33:16,549 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-28 17:33:16,550 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-28 17:33:16,550 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-28 17:33:16,557 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:33:16" (1/1) ... [2019-11-28 17:33:16,570 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:33:16" (1/1) ... [2019-11-28 17:33:16,643 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-28 17:33:16,644 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-28 17:33:16,644 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-28 17:33:16,644 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-28 17:33:16,655 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:33:16" (1/1) ... [2019-11-28 17:33:16,656 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:33:16" (1/1) ... [2019-11-28 17:33:16,664 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:33:16" (1/1) ... [2019-11-28 17:33:16,664 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:33:16" (1/1) ... [2019-11-28 17:33:16,682 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:33:16" (1/1) ... [2019-11-28 17:33:16,708 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:33:16" (1/1) ... [2019-11-28 17:33:16,718 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:33:16" (1/1) ... [2019-11-28 17:33:16,733 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-28 17:33:16,734 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-28 17:33:16,734 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-28 17:33:16,734 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-28 17:33:16,735 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:33:16" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 17:33:16,810 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-28 17:33:16,811 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-28 17:33:18,281 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-28 17:33:18,282 INFO L287 CfgBuilder]: Removed 119 assume(true) statements. [2019-11-28 17:33:18,283 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 05:33:18 BoogieIcfgContainer [2019-11-28 17:33:18,283 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-28 17:33:18,285 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-28 17:33:18,285 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-28 17:33:18,288 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-28 17:33:18,289 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 05:33:15" (1/3) ... [2019-11-28 17:33:18,291 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@b119ac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 05:33:18, skipping insertion in model container [2019-11-28 17:33:18,291 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:33:16" (2/3) ... [2019-11-28 17:33:18,292 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@b119ac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 05:33:18, skipping insertion in model container [2019-11-28 17:33:18,292 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 05:33:18" (3/3) ... [2019-11-28 17:33:18,295 INFO L109 eAbstractionObserver]: Analyzing ICFG pals_STARTPALS_ActiveStandby.1.ufo.UNBOUNDED.pals.c [2019-11-28 17:33:18,306 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-28 17:33:18,318 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 23 error locations. [2019-11-28 17:33:18,338 INFO L249 AbstractCegarLoop]: Starting to check reachability of 23 error locations. [2019-11-28 17:33:18,376 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-28 17:33:18,376 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-28 17:33:18,376 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-28 17:33:18,377 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-28 17:33:18,377 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-28 17:33:18,377 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-28 17:33:18,378 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-28 17:33:18,378 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-28 17:33:18,406 INFO L276 IsEmpty]: Start isEmpty. Operand 292 states. [2019-11-28 17:33:18,414 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-11-28 17:33:18,414 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:33:18,415 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:33:18,416 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:33:18,423 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:33:18,424 INFO L82 PathProgramCache]: Analyzing trace with hash 211735483, now seen corresponding path program 1 times [2019-11-28 17:33:18,434 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:33:18,435 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1020796650] [2019-11-28 17:33:18,435 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:33:18,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:33:18,699 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:33:18,700 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1020796650] [2019-11-28 17:33:18,701 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:33:18,702 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:33:18,704 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1574617895] [2019-11-28 17:33:18,714 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:33:18,715 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:33:18,737 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:33:18,738 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:33:18,741 INFO L87 Difference]: Start difference. First operand 292 states. Second operand 3 states. [2019-11-28 17:33:18,876 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:33:18,877 INFO L93 Difference]: Finished difference Result 566 states and 887 transitions. [2019-11-28 17:33:18,880 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:33:18,881 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 31 [2019-11-28 17:33:18,882 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:33:18,896 INFO L225 Difference]: With dead ends: 566 [2019-11-28 17:33:18,897 INFO L226 Difference]: Without dead ends: 288 [2019-11-28 17:33:18,902 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:33:18,921 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states. [2019-11-28 17:33:18,961 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 288. [2019-11-28 17:33:18,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 288 states. [2019-11-28 17:33:18,965 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 288 states to 288 states and 412 transitions. [2019-11-28 17:33:18,967 INFO L78 Accepts]: Start accepts. Automaton has 288 states and 412 transitions. Word has length 31 [2019-11-28 17:33:18,967 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:33:18,968 INFO L462 AbstractCegarLoop]: Abstraction has 288 states and 412 transitions. [2019-11-28 17:33:18,968 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:33:18,968 INFO L276 IsEmpty]: Start isEmpty. Operand 288 states and 412 transitions. [2019-11-28 17:33:18,970 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-11-28 17:33:18,970 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:33:18,970 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:33:18,971 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:33:18,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:33:18,972 INFO L82 PathProgramCache]: Analyzing trace with hash -1187444686, now seen corresponding path program 1 times [2019-11-28 17:33:18,973 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:33:18,973 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [841664944] [2019-11-28 17:33:18,973 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:33:19,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:33:19,222 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:33:19,223 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [841664944] [2019-11-28 17:33:19,223 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:33:19,223 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:33:19,224 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [912899200] [2019-11-28 17:33:19,225 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:33:19,226 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:33:19,226 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:33:19,227 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:33:19,227 INFO L87 Difference]: Start difference. First operand 288 states and 412 transitions. Second operand 3 states. [2019-11-28 17:33:19,298 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:33:19,298 INFO L93 Difference]: Finished difference Result 594 states and 858 transitions. [2019-11-28 17:33:19,299 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:33:19,299 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 42 [2019-11-28 17:33:19,300 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:33:19,303 INFO L225 Difference]: With dead ends: 594 [2019-11-28 17:33:19,304 INFO L226 Difference]: Without dead ends: 321 [2019-11-28 17:33:19,307 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:33:19,309 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 321 states. [2019-11-28 17:33:19,329 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 321 to 264. [2019-11-28 17:33:19,329 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 264 states. [2019-11-28 17:33:19,331 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 264 states to 264 states and 376 transitions. [2019-11-28 17:33:19,331 INFO L78 Accepts]: Start accepts. Automaton has 264 states and 376 transitions. Word has length 42 [2019-11-28 17:33:19,332 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:33:19,332 INFO L462 AbstractCegarLoop]: Abstraction has 264 states and 376 transitions. [2019-11-28 17:33:19,332 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:33:19,333 INFO L276 IsEmpty]: Start isEmpty. Operand 264 states and 376 transitions. [2019-11-28 17:33:19,334 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-11-28 17:33:19,335 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:33:19,335 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:33:19,336 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:33:19,336 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:33:19,336 INFO L82 PathProgramCache]: Analyzing trace with hash 1273755287, now seen corresponding path program 1 times [2019-11-28 17:33:19,337 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:33:19,337 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2118347519] [2019-11-28 17:33:19,337 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:33:19,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:33:19,527 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:33:19,528 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2118347519] [2019-11-28 17:33:19,528 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:33:19,529 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:33:19,530 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [747396689] [2019-11-28 17:33:19,531 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:33:19,532 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:33:19,532 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:33:19,533 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:33:19,533 INFO L87 Difference]: Start difference. First operand 264 states and 376 transitions. Second operand 3 states. [2019-11-28 17:33:19,599 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:33:19,599 INFO L93 Difference]: Finished difference Result 739 states and 1063 transitions. [2019-11-28 17:33:19,603 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:33:19,604 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 49 [2019-11-28 17:33:19,604 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:33:19,609 INFO L225 Difference]: With dead ends: 739 [2019-11-28 17:33:19,609 INFO L226 Difference]: Without dead ends: 490 [2019-11-28 17:33:19,611 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:33:19,614 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 490 states. [2019-11-28 17:33:19,661 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 490 to 299. [2019-11-28 17:33:19,664 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 299 states. [2019-11-28 17:33:19,666 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 299 states to 299 states and 428 transitions. [2019-11-28 17:33:19,666 INFO L78 Accepts]: Start accepts. Automaton has 299 states and 428 transitions. Word has length 49 [2019-11-28 17:33:19,670 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:33:19,671 INFO L462 AbstractCegarLoop]: Abstraction has 299 states and 428 transitions. [2019-11-28 17:33:19,671 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:33:19,671 INFO L276 IsEmpty]: Start isEmpty. Operand 299 states and 428 transitions. [2019-11-28 17:33:19,674 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2019-11-28 17:33:19,674 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:33:19,674 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:33:19,678 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:33:19,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:33:19,680 INFO L82 PathProgramCache]: Analyzing trace with hash -1910840580, now seen corresponding path program 1 times [2019-11-28 17:33:19,680 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:33:19,681 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1796731309] [2019-11-28 17:33:19,681 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:33:19,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:33:19,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:33:19,853 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1796731309] [2019-11-28 17:33:19,853 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:33:19,854 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 17:33:19,854 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2090738627] [2019-11-28 17:33:19,854 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 17:33:19,855 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:33:19,855 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 17:33:19,855 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:33:19,856 INFO L87 Difference]: Start difference. First operand 299 states and 428 transitions. Second operand 5 states. [2019-11-28 17:33:20,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:33:20,209 INFO L93 Difference]: Finished difference Result 939 states and 1357 transitions. [2019-11-28 17:33:20,210 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 17:33:20,210 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 50 [2019-11-28 17:33:20,211 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:33:20,215 INFO L225 Difference]: With dead ends: 939 [2019-11-28 17:33:20,215 INFO L226 Difference]: Without dead ends: 655 [2019-11-28 17:33:20,217 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-11-28 17:33:20,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 655 states. [2019-11-28 17:33:20,241 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 655 to 385. [2019-11-28 17:33:20,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 385 states. [2019-11-28 17:33:20,243 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 385 states to 385 states and 551 transitions. [2019-11-28 17:33:20,244 INFO L78 Accepts]: Start accepts. Automaton has 385 states and 551 transitions. Word has length 50 [2019-11-28 17:33:20,244 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:33:20,244 INFO L462 AbstractCegarLoop]: Abstraction has 385 states and 551 transitions. [2019-11-28 17:33:20,245 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 17:33:20,245 INFO L276 IsEmpty]: Start isEmpty. Operand 385 states and 551 transitions. [2019-11-28 17:33:20,247 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-11-28 17:33:20,247 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:33:20,247 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:33:20,248 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:33:20,248 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:33:20,248 INFO L82 PathProgramCache]: Analyzing trace with hash -1041102253, now seen corresponding path program 1 times [2019-11-28 17:33:20,249 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:33:20,249 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [294659233] [2019-11-28 17:33:20,249 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:33:20,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:33:20,346 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:33:20,346 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [294659233] [2019-11-28 17:33:20,347 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:33:20,347 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 17:33:20,347 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [149415275] [2019-11-28 17:33:20,348 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 17:33:20,348 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:33:20,348 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 17:33:20,349 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:33:20,349 INFO L87 Difference]: Start difference. First operand 385 states and 551 transitions. Second operand 5 states. [2019-11-28 17:33:20,638 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:33:20,639 INFO L93 Difference]: Finished difference Result 941 states and 1357 transitions. [2019-11-28 17:33:20,639 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 17:33:20,640 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 51 [2019-11-28 17:33:20,641 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:33:20,645 INFO L225 Difference]: With dead ends: 941 [2019-11-28 17:33:20,646 INFO L226 Difference]: Without dead ends: 657 [2019-11-28 17:33:20,647 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-11-28 17:33:20,649 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 657 states. [2019-11-28 17:33:20,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 657 to 389. [2019-11-28 17:33:20,674 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 389 states. [2019-11-28 17:33:20,676 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 555 transitions. [2019-11-28 17:33:20,676 INFO L78 Accepts]: Start accepts. Automaton has 389 states and 555 transitions. Word has length 51 [2019-11-28 17:33:20,677 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:33:20,677 INFO L462 AbstractCegarLoop]: Abstraction has 389 states and 555 transitions. [2019-11-28 17:33:20,677 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 17:33:20,677 INFO L276 IsEmpty]: Start isEmpty. Operand 389 states and 555 transitions. [2019-11-28 17:33:20,679 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2019-11-28 17:33:20,680 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:33:20,680 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:33:20,681 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:33:20,681 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:33:20,681 INFO L82 PathProgramCache]: Analyzing trace with hash -458607163, now seen corresponding path program 1 times [2019-11-28 17:33:20,682 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:33:20,682 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1688666226] [2019-11-28 17:33:20,682 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:33:20,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:33:20,842 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:33:20,843 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1688666226] [2019-11-28 17:33:20,844 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:33:20,844 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 17:33:20,844 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [55466206] [2019-11-28 17:33:20,846 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 17:33:20,846 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:33:20,847 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 17:33:20,847 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 17:33:20,848 INFO L87 Difference]: Start difference. First operand 389 states and 555 transitions. Second operand 4 states. [2019-11-28 17:33:21,104 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:33:21,104 INFO L93 Difference]: Finished difference Result 941 states and 1353 transitions. [2019-11-28 17:33:21,104 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 17:33:21,105 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 53 [2019-11-28 17:33:21,106 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:33:21,110 INFO L225 Difference]: With dead ends: 941 [2019-11-28 17:33:21,111 INFO L226 Difference]: Without dead ends: 657 [2019-11-28 17:33:21,113 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:33:21,114 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 657 states. [2019-11-28 17:33:21,143 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 657 to 389. [2019-11-28 17:33:21,144 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 389 states. [2019-11-28 17:33:21,146 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 553 transitions. [2019-11-28 17:33:21,146 INFO L78 Accepts]: Start accepts. Automaton has 389 states and 553 transitions. Word has length 53 [2019-11-28 17:33:21,146 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:33:21,147 INFO L462 AbstractCegarLoop]: Abstraction has 389 states and 553 transitions. [2019-11-28 17:33:21,147 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 17:33:21,147 INFO L276 IsEmpty]: Start isEmpty. Operand 389 states and 553 transitions. [2019-11-28 17:33:21,148 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-11-28 17:33:21,148 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:33:21,148 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:33:21,148 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:33:21,152 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:33:21,153 INFO L82 PathProgramCache]: Analyzing trace with hash 1789775306, now seen corresponding path program 1 times [2019-11-28 17:33:21,153 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:33:21,155 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1023968926] [2019-11-28 17:33:21,155 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:33:21,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:33:21,334 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:33:21,335 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1023968926] [2019-11-28 17:33:21,335 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:33:21,336 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 17:33:21,336 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [124635430] [2019-11-28 17:33:21,336 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 17:33:21,336 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:33:21,337 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 17:33:21,337 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:33:21,337 INFO L87 Difference]: Start difference. First operand 389 states and 553 transitions. Second operand 5 states. [2019-11-28 17:33:21,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:33:21,409 INFO L93 Difference]: Finished difference Result 773 states and 1114 transitions. [2019-11-28 17:33:21,409 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-28 17:33:21,409 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 54 [2019-11-28 17:33:21,410 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:33:21,413 INFO L225 Difference]: With dead ends: 773 [2019-11-28 17:33:21,413 INFO L226 Difference]: Without dead ends: 489 [2019-11-28 17:33:21,415 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2019-11-28 17:33:21,416 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 489 states. [2019-11-28 17:33:21,434 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 489 to 384. [2019-11-28 17:33:21,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 384 states. [2019-11-28 17:33:21,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 545 transitions. [2019-11-28 17:33:21,437 INFO L78 Accepts]: Start accepts. Automaton has 384 states and 545 transitions. Word has length 54 [2019-11-28 17:33:21,438 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:33:21,438 INFO L462 AbstractCegarLoop]: Abstraction has 384 states and 545 transitions. [2019-11-28 17:33:21,438 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 17:33:21,438 INFO L276 IsEmpty]: Start isEmpty. Operand 384 states and 545 transitions. [2019-11-28 17:33:21,439 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-11-28 17:33:21,439 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:33:21,440 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:33:21,440 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:33:21,440 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:33:21,440 INFO L82 PathProgramCache]: Analyzing trace with hash 1630366882, now seen corresponding path program 1 times [2019-11-28 17:33:21,441 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:33:21,441 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [611357816] [2019-11-28 17:33:21,441 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:33:21,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:33:21,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:33:21,618 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [611357816] [2019-11-28 17:33:21,619 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:33:21,619 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 17:33:21,619 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [157499103] [2019-11-28 17:33:21,620 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 17:33:21,620 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:33:21,621 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 17:33:21,621 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:33:21,621 INFO L87 Difference]: Start difference. First operand 384 states and 545 transitions. Second operand 5 states. [2019-11-28 17:33:21,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:33:21,749 INFO L93 Difference]: Finished difference Result 804 states and 1163 transitions. [2019-11-28 17:33:21,749 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 17:33:21,750 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 58 [2019-11-28 17:33:21,750 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:33:21,753 INFO L225 Difference]: With dead ends: 804 [2019-11-28 17:33:21,753 INFO L226 Difference]: Without dead ends: 525 [2019-11-28 17:33:21,754 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-11-28 17:33:21,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 525 states. [2019-11-28 17:33:21,776 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 525 to 354. [2019-11-28 17:33:21,776 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 354 states. [2019-11-28 17:33:21,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 354 states to 354 states and 499 transitions. [2019-11-28 17:33:21,778 INFO L78 Accepts]: Start accepts. Automaton has 354 states and 499 transitions. Word has length 58 [2019-11-28 17:33:21,779 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:33:21,779 INFO L462 AbstractCegarLoop]: Abstraction has 354 states and 499 transitions. [2019-11-28 17:33:21,779 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 17:33:21,779 INFO L276 IsEmpty]: Start isEmpty. Operand 354 states and 499 transitions. [2019-11-28 17:33:21,780 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-11-28 17:33:21,780 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:33:21,780 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:33:21,781 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:33:21,782 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:33:21,782 INFO L82 PathProgramCache]: Analyzing trace with hash 644191382, now seen corresponding path program 1 times [2019-11-28 17:33:21,782 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:33:21,783 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1572230682] [2019-11-28 17:33:21,783 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:33:21,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:33:21,912 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:33:21,912 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1572230682] [2019-11-28 17:33:21,912 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:33:21,912 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 17:33:21,913 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2040336765] [2019-11-28 17:33:21,913 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 17:33:21,913 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:33:21,914 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 17:33:21,915 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:33:21,916 INFO L87 Difference]: Start difference. First operand 354 states and 499 transitions. Second operand 5 states. [2019-11-28 17:33:22,055 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:33:22,056 INFO L93 Difference]: Finished difference Result 900 states and 1292 transitions. [2019-11-28 17:33:22,056 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 17:33:22,056 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 63 [2019-11-28 17:33:22,057 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:33:22,060 INFO L225 Difference]: With dead ends: 900 [2019-11-28 17:33:22,061 INFO L226 Difference]: Without dead ends: 651 [2019-11-28 17:33:22,062 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-11-28 17:33:22,063 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 651 states. [2019-11-28 17:33:22,085 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 651 to 324. [2019-11-28 17:33:22,086 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 324 states. [2019-11-28 17:33:22,087 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 324 states to 324 states and 453 transitions. [2019-11-28 17:33:22,088 INFO L78 Accepts]: Start accepts. Automaton has 324 states and 453 transitions. Word has length 63 [2019-11-28 17:33:22,088 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:33:22,088 INFO L462 AbstractCegarLoop]: Abstraction has 324 states and 453 transitions. [2019-11-28 17:33:22,088 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 17:33:22,089 INFO L276 IsEmpty]: Start isEmpty. Operand 324 states and 453 transitions. [2019-11-28 17:33:22,089 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-11-28 17:33:22,090 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:33:22,090 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:33:22,091 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:33:22,091 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:33:22,092 INFO L82 PathProgramCache]: Analyzing trace with hash 157991886, now seen corresponding path program 1 times [2019-11-28 17:33:22,092 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:33:22,092 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [690153085] [2019-11-28 17:33:22,092 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:33:22,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:33:22,276 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:33:22,277 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [690153085] [2019-11-28 17:33:22,277 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:33:22,278 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-28 17:33:22,278 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1376639429] [2019-11-28 17:33:22,278 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-28 17:33:22,279 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:33:22,279 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-28 17:33:22,279 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-28 17:33:22,279 INFO L87 Difference]: Start difference. First operand 324 states and 453 transitions. Second operand 6 states. [2019-11-28 17:33:22,521 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:33:22,521 INFO L93 Difference]: Finished difference Result 1098 states and 1557 transitions. [2019-11-28 17:33:22,522 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-28 17:33:22,522 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 68 [2019-11-28 17:33:22,522 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:33:22,526 INFO L225 Difference]: With dead ends: 1098 [2019-11-28 17:33:22,526 INFO L226 Difference]: Without dead ends: 879 [2019-11-28 17:33:22,527 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2019-11-28 17:33:22,528 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 879 states. [2019-11-28 17:33:22,556 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 879 to 363. [2019-11-28 17:33:22,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 363 states. [2019-11-28 17:33:22,558 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 363 states to 363 states and 507 transitions. [2019-11-28 17:33:22,558 INFO L78 Accepts]: Start accepts. Automaton has 363 states and 507 transitions. Word has length 68 [2019-11-28 17:33:22,560 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:33:22,560 INFO L462 AbstractCegarLoop]: Abstraction has 363 states and 507 transitions. [2019-11-28 17:33:22,561 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-28 17:33:22,561 INFO L276 IsEmpty]: Start isEmpty. Operand 363 states and 507 transitions. [2019-11-28 17:33:22,567 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2019-11-28 17:33:22,567 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:33:22,567 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:33:22,568 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:33:22,568 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:33:22,568 INFO L82 PathProgramCache]: Analyzing trace with hash -2134355609, now seen corresponding path program 1 times [2019-11-28 17:33:22,568 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:33:22,568 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [373517480] [2019-11-28 17:33:22,569 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:33:22,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:33:22,663 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:33:22,664 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [373517480] [2019-11-28 17:33:22,664 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:33:22,664 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:33:22,665 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1449865238] [2019-11-28 17:33:22,665 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:33:22,666 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:33:22,666 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:33:22,666 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:33:22,666 INFO L87 Difference]: Start difference. First operand 363 states and 507 transitions. Second operand 3 states. [2019-11-28 17:33:22,737 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:33:22,738 INFO L93 Difference]: Finished difference Result 659 states and 932 transitions. [2019-11-28 17:33:22,738 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:33:22,738 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 69 [2019-11-28 17:33:22,739 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:33:22,742 INFO L225 Difference]: With dead ends: 659 [2019-11-28 17:33:22,742 INFO L226 Difference]: Without dead ends: 440 [2019-11-28 17:33:22,743 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:33:22,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 440 states. [2019-11-28 17:33:22,774 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 440 to 359. [2019-11-28 17:33:22,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 359 states. [2019-11-28 17:33:22,776 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 359 states to 359 states and 500 transitions. [2019-11-28 17:33:22,776 INFO L78 Accepts]: Start accepts. Automaton has 359 states and 500 transitions. Word has length 69 [2019-11-28 17:33:22,776 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:33:22,776 INFO L462 AbstractCegarLoop]: Abstraction has 359 states and 500 transitions. [2019-11-28 17:33:22,777 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:33:22,777 INFO L276 IsEmpty]: Start isEmpty. Operand 359 states and 500 transitions. [2019-11-28 17:33:22,778 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-28 17:33:22,778 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:33:22,778 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:33:22,780 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:33:22,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:33:22,780 INFO L82 PathProgramCache]: Analyzing trace with hash 1585943340, now seen corresponding path program 1 times [2019-11-28 17:33:22,781 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:33:22,781 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2053167692] [2019-11-28 17:33:22,781 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:33:22,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:33:22,877 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:33:22,878 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2053167692] [2019-11-28 17:33:22,878 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:33:22,878 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 17:33:22,879 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [326837169] [2019-11-28 17:33:22,879 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 17:33:22,880 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:33:22,880 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 17:33:22,880 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 17:33:22,880 INFO L87 Difference]: Start difference. First operand 359 states and 500 transitions. Second operand 4 states. [2019-11-28 17:33:23,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:33:23,077 INFO L93 Difference]: Finished difference Result 949 states and 1326 transitions. [2019-11-28 17:33:23,077 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 17:33:23,078 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 72 [2019-11-28 17:33:23,078 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:33:23,082 INFO L225 Difference]: With dead ends: 949 [2019-11-28 17:33:23,082 INFO L226 Difference]: Without dead ends: 724 [2019-11-28 17:33:23,083 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:33:23,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 724 states. [2019-11-28 17:33:23,123 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 724 to 529. [2019-11-28 17:33:23,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 529 states. [2019-11-28 17:33:23,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 529 states to 529 states and 733 transitions. [2019-11-28 17:33:23,126 INFO L78 Accepts]: Start accepts. Automaton has 529 states and 733 transitions. Word has length 72 [2019-11-28 17:33:23,126 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:33:23,126 INFO L462 AbstractCegarLoop]: Abstraction has 529 states and 733 transitions. [2019-11-28 17:33:23,127 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 17:33:23,127 INFO L276 IsEmpty]: Start isEmpty. Operand 529 states and 733 transitions. [2019-11-28 17:33:23,128 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-28 17:33:23,128 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:33:23,128 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:33:23,129 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:33:23,129 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:33:23,129 INFO L82 PathProgramCache]: Analyzing trace with hash -2083950892, now seen corresponding path program 1 times [2019-11-28 17:33:23,130 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:33:23,130 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1037178026] [2019-11-28 17:33:23,130 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:33:23,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:33:23,182 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:33:23,182 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1037178026] [2019-11-28 17:33:23,182 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:33:23,183 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:33:23,183 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [489210977] [2019-11-28 17:33:23,183 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:33:23,183 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:33:23,185 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:33:23,185 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:33:23,185 INFO L87 Difference]: Start difference. First operand 529 states and 733 transitions. Second operand 3 states. [2019-11-28 17:33:23,232 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:33:23,233 INFO L93 Difference]: Finished difference Result 907 states and 1262 transitions. [2019-11-28 17:33:23,233 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:33:23,234 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-11-28 17:33:23,234 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:33:23,238 INFO L225 Difference]: With dead ends: 907 [2019-11-28 17:33:23,238 INFO L226 Difference]: Without dead ends: 529 [2019-11-28 17:33:23,239 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:33:23,241 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 529 states. [2019-11-28 17:33:23,297 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 529 to 529. [2019-11-28 17:33:23,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 529 states. [2019-11-28 17:33:23,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 529 states to 529 states and 729 transitions. [2019-11-28 17:33:23,301 INFO L78 Accepts]: Start accepts. Automaton has 529 states and 729 transitions. Word has length 72 [2019-11-28 17:33:23,301 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:33:23,301 INFO L462 AbstractCegarLoop]: Abstraction has 529 states and 729 transitions. [2019-11-28 17:33:23,301 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:33:23,302 INFO L276 IsEmpty]: Start isEmpty. Operand 529 states and 729 transitions. [2019-11-28 17:33:23,303 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2019-11-28 17:33:23,303 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:33:23,304 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:33:23,304 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:33:23,304 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:33:23,305 INFO L82 PathProgramCache]: Analyzing trace with hash 2070467794, now seen corresponding path program 1 times [2019-11-28 17:33:23,305 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:33:23,311 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1617125537] [2019-11-28 17:33:23,311 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:33:23,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:33:23,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:33:23,379 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1617125537] [2019-11-28 17:33:23,380 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:33:23,380 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:33:23,380 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [566763413] [2019-11-28 17:33:23,381 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:33:23,381 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:33:23,381 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:33:23,382 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:33:23,382 INFO L87 Difference]: Start difference. First operand 529 states and 729 transitions. Second operand 3 states. [2019-11-28 17:33:23,480 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:33:23,481 INFO L93 Difference]: Finished difference Result 1250 states and 1717 transitions. [2019-11-28 17:33:23,481 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:33:23,481 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 72 [2019-11-28 17:33:23,481 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:33:23,486 INFO L225 Difference]: With dead ends: 1250 [2019-11-28 17:33:23,486 INFO L226 Difference]: Without dead ends: 835 [2019-11-28 17:33:23,488 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:33:23,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states. [2019-11-28 17:33:23,540 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 563. [2019-11-28 17:33:23,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 563 states. [2019-11-28 17:33:23,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 563 states and 773 transitions. [2019-11-28 17:33:23,543 INFO L78 Accepts]: Start accepts. Automaton has 563 states and 773 transitions. Word has length 72 [2019-11-28 17:33:23,544 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:33:23,544 INFO L462 AbstractCegarLoop]: Abstraction has 563 states and 773 transitions. [2019-11-28 17:33:23,544 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:33:23,544 INFO L276 IsEmpty]: Start isEmpty. Operand 563 states and 773 transitions. [2019-11-28 17:33:23,545 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-28 17:33:23,545 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:33:23,546 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:33:23,546 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:33:23,546 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:33:23,547 INFO L82 PathProgramCache]: Analyzing trace with hash -1917205063, now seen corresponding path program 1 times [2019-11-28 17:33:23,547 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:33:23,547 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [671355615] [2019-11-28 17:33:23,547 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:33:23,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:33:23,703 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:33:23,704 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [671355615] [2019-11-28 17:33:23,704 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:33:23,704 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-28 17:33:23,704 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [485959395] [2019-11-28 17:33:23,705 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-28 17:33:23,705 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:33:23,705 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-28 17:33:23,705 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-28 17:33:23,705 INFO L87 Difference]: Start difference. First operand 563 states and 773 transitions. Second operand 6 states. [2019-11-28 17:33:24,031 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:33:24,031 INFO L93 Difference]: Finished difference Result 1763 states and 2476 transitions. [2019-11-28 17:33:24,031 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-28 17:33:24,032 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 73 [2019-11-28 17:33:24,032 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:33:24,039 INFO L225 Difference]: With dead ends: 1763 [2019-11-28 17:33:24,039 INFO L226 Difference]: Without dead ends: 1430 [2019-11-28 17:33:24,040 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2019-11-28 17:33:24,042 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1430 states. [2019-11-28 17:33:24,101 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1430 to 567. [2019-11-28 17:33:24,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 567 states. [2019-11-28 17:33:24,105 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 567 states to 567 states and 778 transitions. [2019-11-28 17:33:24,105 INFO L78 Accepts]: Start accepts. Automaton has 567 states and 778 transitions. Word has length 73 [2019-11-28 17:33:24,105 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:33:24,106 INFO L462 AbstractCegarLoop]: Abstraction has 567 states and 778 transitions. [2019-11-28 17:33:24,106 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-28 17:33:24,106 INFO L276 IsEmpty]: Start isEmpty. Operand 567 states and 778 transitions. [2019-11-28 17:33:24,107 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-28 17:33:24,108 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:33:24,108 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:33:24,108 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:33:24,109 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:33:24,109 INFO L82 PathProgramCache]: Analyzing trace with hash 197100160, now seen corresponding path program 1 times [2019-11-28 17:33:24,109 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:33:24,109 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [189960043] [2019-11-28 17:33:24,110 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:33:24,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:33:24,218 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:33:24,219 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [189960043] [2019-11-28 17:33:24,219 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:33:24,219 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 17:33:24,220 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [210627] [2019-11-28 17:33:24,220 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 17:33:24,220 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:33:24,220 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 17:33:24,221 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:33:24,221 INFO L87 Difference]: Start difference. First operand 567 states and 778 transitions. Second operand 5 states. [2019-11-28 17:33:24,432 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:33:24,433 INFO L93 Difference]: Finished difference Result 886 states and 1237 transitions. [2019-11-28 17:33:24,433 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 17:33:24,433 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 73 [2019-11-28 17:33:24,434 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:33:24,440 INFO L225 Difference]: With dead ends: 886 [2019-11-28 17:33:24,440 INFO L226 Difference]: Without dead ends: 884 [2019-11-28 17:33:24,441 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-11-28 17:33:24,443 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 884 states. [2019-11-28 17:33:24,496 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 884 to 569. [2019-11-28 17:33:24,496 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 569 states. [2019-11-28 17:33:24,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 569 states to 569 states and 780 transitions. [2019-11-28 17:33:24,499 INFO L78 Accepts]: Start accepts. Automaton has 569 states and 780 transitions. Word has length 73 [2019-11-28 17:33:24,499 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:33:24,499 INFO L462 AbstractCegarLoop]: Abstraction has 569 states and 780 transitions. [2019-11-28 17:33:24,499 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 17:33:24,499 INFO L276 IsEmpty]: Start isEmpty. Operand 569 states and 780 transitions. [2019-11-28 17:33:24,500 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-11-28 17:33:24,500 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:33:24,501 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:33:24,501 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:33:24,501 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:33:24,501 INFO L82 PathProgramCache]: Analyzing trace with hash 2083582807, now seen corresponding path program 1 times [2019-11-28 17:33:24,502 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:33:24,502 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [791506607] [2019-11-28 17:33:24,502 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:33:24,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:33:24,610 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:33:24,611 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [791506607] [2019-11-28 17:33:24,611 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:33:24,611 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-28 17:33:24,612 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1182388883] [2019-11-28 17:33:24,612 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-28 17:33:24,612 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:33:24,613 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-28 17:33:24,613 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-28 17:33:24,613 INFO L87 Difference]: Start difference. First operand 569 states and 780 transitions. Second operand 6 states. [2019-11-28 17:33:25,317 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:33:25,318 INFO L93 Difference]: Finished difference Result 2030 states and 2821 transitions. [2019-11-28 17:33:25,318 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-28 17:33:25,318 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 73 [2019-11-28 17:33:25,319 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:33:25,327 INFO L225 Difference]: With dead ends: 2030 [2019-11-28 17:33:25,327 INFO L226 Difference]: Without dead ends: 1656 [2019-11-28 17:33:25,329 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-11-28 17:33:25,331 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1656 states. [2019-11-28 17:33:25,395 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1656 to 615. [2019-11-28 17:33:25,395 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 615 states. [2019-11-28 17:33:25,398 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 615 states to 615 states and 838 transitions. [2019-11-28 17:33:25,398 INFO L78 Accepts]: Start accepts. Automaton has 615 states and 838 transitions. Word has length 73 [2019-11-28 17:33:25,398 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:33:25,398 INFO L462 AbstractCegarLoop]: Abstraction has 615 states and 838 transitions. [2019-11-28 17:33:25,398 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-28 17:33:25,398 INFO L276 IsEmpty]: Start isEmpty. Operand 615 states and 838 transitions. [2019-11-28 17:33:25,399 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2019-11-28 17:33:25,400 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:33:25,400 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:33:25,400 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:33:25,400 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:33:25,400 INFO L82 PathProgramCache]: Analyzing trace with hash 1204676769, now seen corresponding path program 1 times [2019-11-28 17:33:25,401 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:33:25,401 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1550912795] [2019-11-28 17:33:25,401 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:33:25,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:33:25,510 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:33:25,511 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1550912795] [2019-11-28 17:33:25,511 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:33:25,511 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-28 17:33:25,511 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2064013324] [2019-11-28 17:33:25,512 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-28 17:33:25,512 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:33:25,512 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-28 17:33:25,512 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-28 17:33:25,513 INFO L87 Difference]: Start difference. First operand 615 states and 838 transitions. Second operand 6 states. [2019-11-28 17:33:26,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:33:26,023 INFO L93 Difference]: Finished difference Result 2356 states and 3253 transitions. [2019-11-28 17:33:26,023 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-28 17:33:26,023 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 74 [2019-11-28 17:33:26,024 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:33:26,034 INFO L225 Difference]: With dead ends: 2356 [2019-11-28 17:33:26,034 INFO L226 Difference]: Without dead ends: 1974 [2019-11-28 17:33:26,036 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2019-11-28 17:33:26,038 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1974 states. [2019-11-28 17:33:26,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1974 to 693. [2019-11-28 17:33:26,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 693 states. [2019-11-28 17:33:26,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 940 transitions. [2019-11-28 17:33:26,113 INFO L78 Accepts]: Start accepts. Automaton has 693 states and 940 transitions. Word has length 74 [2019-11-28 17:33:26,114 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:33:26,114 INFO L462 AbstractCegarLoop]: Abstraction has 693 states and 940 transitions. [2019-11-28 17:33:26,114 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-28 17:33:26,114 INFO L276 IsEmpty]: Start isEmpty. Operand 693 states and 940 transitions. [2019-11-28 17:33:26,115 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2019-11-28 17:33:26,115 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:33:26,115 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:33:26,116 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:33:26,116 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:33:26,116 INFO L82 PathProgramCache]: Analyzing trace with hash -217796256, now seen corresponding path program 1 times [2019-11-28 17:33:26,116 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:33:26,117 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [112133385] [2019-11-28 17:33:26,117 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:33:26,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:33:26,201 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:33:26,202 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [112133385] [2019-11-28 17:33:26,202 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:33:26,202 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-28 17:33:26,202 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1627200030] [2019-11-28 17:33:26,203 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-28 17:33:26,203 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:33:26,203 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-28 17:33:26,203 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-28 17:33:26,203 INFO L87 Difference]: Start difference. First operand 693 states and 940 transitions. Second operand 6 states. [2019-11-28 17:33:26,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:33:26,428 INFO L93 Difference]: Finished difference Result 1555 states and 2195 transitions. [2019-11-28 17:33:26,428 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-28 17:33:26,429 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 74 [2019-11-28 17:33:26,429 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:33:26,435 INFO L225 Difference]: With dead ends: 1555 [2019-11-28 17:33:26,435 INFO L226 Difference]: Without dead ends: 1156 [2019-11-28 17:33:26,437 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2019-11-28 17:33:26,439 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1156 states. [2019-11-28 17:33:26,514 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1156 to 699. [2019-11-28 17:33:26,514 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 699 states. [2019-11-28 17:33:26,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 699 states to 699 states and 946 transitions. [2019-11-28 17:33:26,517 INFO L78 Accepts]: Start accepts. Automaton has 699 states and 946 transitions. Word has length 74 [2019-11-28 17:33:26,517 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:33:26,517 INFO L462 AbstractCegarLoop]: Abstraction has 699 states and 946 transitions. [2019-11-28 17:33:26,517 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-28 17:33:26,518 INFO L276 IsEmpty]: Start isEmpty. Operand 699 states and 946 transitions. [2019-11-28 17:33:26,519 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2019-11-28 17:33:26,519 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:33:26,519 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:33:26,519 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:33:26,519 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:33:26,520 INFO L82 PathProgramCache]: Analyzing trace with hash -1278252476, now seen corresponding path program 1 times [2019-11-28 17:33:26,520 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:33:26,520 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [801376735] [2019-11-28 17:33:26,520 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:33:26,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:33:26,572 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:33:26,572 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [801376735] [2019-11-28 17:33:26,572 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:33:26,572 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:33:26,573 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1339117530] [2019-11-28 17:33:26,573 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:33:26,573 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:33:26,573 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:33:26,574 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:33:26,574 INFO L87 Difference]: Start difference. First operand 699 states and 946 transitions. Second operand 3 states. [2019-11-28 17:33:26,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:33:26,695 INFO L93 Difference]: Finished difference Result 1371 states and 1888 transitions. [2019-11-28 17:33:26,696 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:33:26,696 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 74 [2019-11-28 17:33:26,696 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:33:26,700 INFO L225 Difference]: With dead ends: 1371 [2019-11-28 17:33:26,700 INFO L226 Difference]: Without dead ends: 903 [2019-11-28 17:33:26,702 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:33:26,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 903 states. [2019-11-28 17:33:26,795 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 903 to 678. [2019-11-28 17:33:26,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 678 states. [2019-11-28 17:33:26,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 678 states to 678 states and 909 transitions. [2019-11-28 17:33:26,798 INFO L78 Accepts]: Start accepts. Automaton has 678 states and 909 transitions. Word has length 74 [2019-11-28 17:33:26,798 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:33:26,798 INFO L462 AbstractCegarLoop]: Abstraction has 678 states and 909 transitions. [2019-11-28 17:33:26,799 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:33:26,799 INFO L276 IsEmpty]: Start isEmpty. Operand 678 states and 909 transitions. [2019-11-28 17:33:26,800 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2019-11-28 17:33:26,800 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:33:26,800 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:33:26,801 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr8ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr7ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr16ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr15ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr21ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr17ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr18ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr22ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr20ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr12ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr19ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr4ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr5ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr6ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr10ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr14ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr13ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr11ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr9ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:33:26,801 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:33:26,801 INFO L82 PathProgramCache]: Analyzing trace with hash -1698648942, now seen corresponding path program 1 times [2019-11-28 17:33:26,801 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:33:26,802 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [459519592] [2019-11-28 17:33:26,802 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:33:26,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 17:33:26,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 17:33:26,973 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-28 17:33:26,973 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-28 17:33:27,136 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 05:33:27 BoogieIcfgContainer [2019-11-28 17:33:27,136 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-28 17:33:27,136 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-28 17:33:27,137 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-28 17:33:27,137 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-28 17:33:27,138 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 05:33:18" (3/4) ... [2019-11-28 17:33:27,140 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-28 17:33:27,293 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2019-11-28 17:33:27,293 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-28 17:33:27,297 INFO L168 Benchmark]: Toolchain (without parser) took 11377.98 ms. Allocated memory was 1.0 GB in the beginning and 1.4 GB in the end (delta: 394.3 MB). Free memory was 960.4 MB in the beginning and 1.3 GB in the end (delta: -364.8 MB). Peak memory consumption was 29.5 MB. Max. memory is 11.5 GB. [2019-11-28 17:33:27,297 INFO L168 Benchmark]: CDTParser took 0.76 ms. Allocated memory is still 1.0 GB. Free memory is still 987.2 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 17:33:27,297 INFO L168 Benchmark]: CACSL2BoogieTranslator took 630.49 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 145.8 MB). Free memory was 960.4 MB in the beginning and 1.1 GB in the end (delta: -175.7 MB). Peak memory consumption was 26.0 MB. Max. memory is 11.5 GB. [2019-11-28 17:33:27,298 INFO L168 Benchmark]: Boogie Procedure Inliner took 94.31 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 8.0 MB). Peak memory consumption was 8.0 MB. Max. memory is 11.5 GB. [2019-11-28 17:33:27,298 INFO L168 Benchmark]: Boogie Preprocessor took 89.46 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.4 MB). Peak memory consumption was 6.4 MB. Max. memory is 11.5 GB. [2019-11-28 17:33:27,298 INFO L168 Benchmark]: RCFGBuilder took 1549.76 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 95.0 MB). Peak memory consumption was 95.0 MB. Max. memory is 11.5 GB. [2019-11-28 17:33:27,299 INFO L168 Benchmark]: TraceAbstraction took 8851.36 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 248.5 MB). Free memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: -320.4 MB). There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 17:33:27,299 INFO L168 Benchmark]: Witness Printer took 156.73 ms. Allocated memory is still 1.4 GB. Free memory was 1.3 GB in the beginning and 1.3 GB in the end (delta: 21.9 MB). Peak memory consumption was 21.9 MB. Max. memory is 11.5 GB. [2019-11-28 17:33:27,301 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.76 ms. Allocated memory is still 1.0 GB. Free memory is still 987.2 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 630.49 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 145.8 MB). Free memory was 960.4 MB in the beginning and 1.1 GB in the end (delta: -175.7 MB). Peak memory consumption was 26.0 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 94.31 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 8.0 MB). Peak memory consumption was 8.0 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 89.46 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.4 MB). Peak memory consumption was 6.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1549.76 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 95.0 MB). Peak memory consumption was 95.0 MB. Max. memory is 11.5 GB. * TraceAbstraction took 8851.36 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 248.5 MB). Free memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: -320.4 MB). There was no memory consumed. Max. memory is 11.5 GB. * Witness Printer took 156.73 ms. Allocated memory is still 1.4 GB. Free memory was 1.3 GB in the beginning and 1.3 GB in the end (delta: 21.9 MB). Peak memory consumption was 21.9 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 661]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L69] msg_t nomsg = (msg_t )-1; [L70] port_t cs1 ; [L71] int8_t cs1_old ; [L72] int8_t cs1_new ; [L73] port_t cs2 ; [L74] int8_t cs2_old ; [L75] int8_t cs2_new ; [L76] port_t s1s2 ; [L77] int8_t s1s2_old ; [L78] int8_t s1s2_new ; [L79] port_t s1s1 ; [L80] int8_t s1s1_old ; [L81] int8_t s1s1_new ; [L82] port_t s2s1 ; [L83] int8_t s2s1_old ; [L84] int8_t s2s1_new ; [L85] port_t s2s2 ; [L86] int8_t s2s2_old ; [L87] int8_t s2s2_new ; [L88] port_t s1p ; [L89] int8_t s1p_old ; [L90] int8_t s1p_new ; [L91] port_t s2p ; [L92] int8_t s2p_old ; [L93] int8_t s2p_new ; [L96] _Bool side1Failed ; [L97] _Bool side2Failed ; [L98] msg_t side1_written ; [L99] msg_t side2_written ; [L102] static _Bool side1Failed_History_0 ; [L103] static _Bool side1Failed_History_1 ; [L104] static _Bool side1Failed_History_2 ; [L105] static _Bool side2Failed_History_0 ; [L106] static _Bool side2Failed_History_1 ; [L107] static _Bool side2Failed_History_2 ; [L108] static int8_t active_side_History_0 ; [L109] static int8_t active_side_History_1 ; [L110] static int8_t active_side_History_2 ; [L111] static msg_t manual_selection_History_0 ; [L112] static msg_t manual_selection_History_1 ; [L113] static msg_t manual_selection_History_2 ; [L463] void (*nodes[4])(void) = { & Console_task_each_pals_period, & Side1_activestandby_task_each_pals_period, & Side2_activestandby_task_each_pals_period, & Pendulum_prism_task_each_pals_period}; VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=0, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L585] int c1 ; [L586] int i2 ; [L589] c1 = 0 [L590] side1Failed = __VERIFIER_nondet_bool() [L591] side2Failed = __VERIFIER_nondet_bool() [L592] side1_written = __VERIFIER_nondet_char() [L593] side2_written = __VERIFIER_nondet_char() [L594] side1Failed_History_0 = __VERIFIER_nondet_bool() [L595] side1Failed_History_1 = __VERIFIER_nondet_bool() [L596] side1Failed_History_2 = __VERIFIER_nondet_bool() [L597] side2Failed_History_0 = __VERIFIER_nondet_bool() [L598] side2Failed_History_1 = __VERIFIER_nondet_bool() [L599] side2Failed_History_2 = __VERIFIER_nondet_bool() [L600] active_side_History_0 = __VERIFIER_nondet_char() [L601] active_side_History_1 = __VERIFIER_nondet_char() [L602] active_side_History_2 = __VERIFIER_nondet_char() [L603] manual_selection_History_0 = __VERIFIER_nondet_char() [L604] manual_selection_History_1 = __VERIFIER_nondet_char() [L605] manual_selection_History_2 = __VERIFIER_nondet_char() [L239] COND FALSE !((int )side1Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=129, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=128, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L242] COND FALSE !((int )side2Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=129, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=128, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L245] COND FALSE !((int )active_side_History_0 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=129, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=128, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L248] COND FALSE !((int )manual_selection_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=129, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=128, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L251] COND FALSE !((int )side1Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=129, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=128, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L254] COND FALSE !((int )side2Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=129, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=128, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L257] COND FALSE !((int )active_side_History_1 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=129, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=128, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L260] COND FALSE !((int )manual_selection_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=129, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=128, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L263] COND FALSE !((int )side1Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=129, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=128, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L266] COND FALSE !((int )side2Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=129, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=128, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L269] COND FALSE !((int )active_side_History_2 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=129, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=128, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L272] COND FALSE !((int )manual_selection_History_2 != 0) [L275] return (1); VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1_written=0, side1Failed=129, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=128, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L606] i2 = init() [L608] cs1_old = nomsg [L609] cs1_new = nomsg [L610] cs2_old = nomsg [L611] cs2_new = nomsg [L612] s1s2_old = nomsg [L613] s1s2_new = nomsg [L614] s1s1_old = nomsg [L615] s1s1_new = nomsg [L616] s2s1_old = nomsg [L617] s2s1_new = nomsg [L618] s2s2_old = nomsg [L619] s2s2_new = nomsg [L620] s1p_old = nomsg [L621] s1p_new = nomsg [L622] s2p_old = nomsg [L623] s2p_new = nomsg [L624] i2 = 0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=129, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=128, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L625] COND TRUE 1 [L293] msg_t manual_selection ; [L294] char tmp ; [L297] tmp = __VERIFIER_nondet_char() [L298] manual_selection = tmp [L209] manual_selection_History_2 = manual_selection_History_1 [L210] manual_selection_History_1 = manual_selection_History_0 [L211] manual_selection_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=129, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=128, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] EXPR manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=129, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=128, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L300] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L301] EXPR manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=129, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=128, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L301] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L302] manual_selection = (msg_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=129, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=128, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L308] int8_t side1 ; [L309] int8_t side2 ; [L310] msg_t manual_selection ; [L311] int8_t next_state ; [L314] side1 = nomsg [L315] side2 = nomsg [L316] manual_selection = (msg_t )0 [L317] side1Failed = __VERIFIER_nondet_bool() [L119] side1Failed_History_2 = side1Failed_History_1 [L120] side1Failed_History_1 = side1Failed_History_0 [L121] side1Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=128, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L319] COND FALSE !(\read(side1Failed)) [L326] side1 = s1s1_old [L327] s1s1_old = nomsg [L328] side2 = s2s1_old [L329] s2s1_old = nomsg [L330] manual_selection = cs1_old [L331] cs1_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=128, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L332] COND TRUE (int )side1 == (int )side2 [L333] next_state = (int8_t )1 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=128, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L356] EXPR next_state != nomsg && s1s1_new == nomsg ? next_state : s1s1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=128, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L356] s1s1_new = next_state != nomsg && s1s1_new == nomsg ? next_state : s1s1_new [L357] EXPR next_state != nomsg && s1s2_new == nomsg ? next_state : s1s2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=128, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L357] s1s2_new = next_state != nomsg && s1s2_new == nomsg ? next_state : s1s2_new [L358] EXPR next_state != nomsg && s1p_new == nomsg ? next_state : s1p_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=128, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L358] s1p_new = next_state != nomsg && s1p_new == nomsg ? next_state : s1p_new [L359] side1_written = next_state VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=128, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L365] int8_t side1 ; [L366] int8_t side2 ; [L367] msg_t manual_selection ; [L368] int8_t next_state ; [L371] side1 = nomsg [L372] side2 = nomsg [L373] manual_selection = (msg_t )0 [L374] side2Failed = __VERIFIER_nondet_bool() [L149] side2Failed_History_2 = side2Failed_History_1 [L150] side2Failed_History_1 = side2Failed_History_0 [L151] side2Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L376] COND FALSE !(\read(side2Failed)) [L383] side1 = s1s2_old [L384] s1s2_old = nomsg [L385] side2 = s2s2_old [L386] s2s2_old = nomsg [L387] manual_selection = cs2_old [L388] cs2_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L389] COND TRUE (int )side1 == (int )side2 [L390] next_state = (int8_t )1 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] EXPR next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L413] s2s1_new = next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new [L414] EXPR next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L414] s2s2_new = next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new [L415] EXPR next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=1, s2s1_old=-1, s2s2=0, s2s2_new=1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L415] s2p_new = next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new [L416] side2_written = next_state VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=1, s2p_old=-1, s2s1=0, s2s1_new=1, s2s1_old=-1, s2s2=0, s2s2_new=1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L422] int8_t active_side ; [L423] int8_t tmp ; [L424] int8_t side1 ; [L425] int8_t side2 ; [L190] COND TRUE (int )index == 0 [L191] return (active_side_History_0); VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=1, s2p_old=-1, s2s1=0, s2s1_new=1, s2s1_old=-1, s2s2=0, s2s2_new=1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L428] tmp = read_active_side_history((unsigned char)0) [L429] active_side = tmp [L430] side1 = nomsg [L431] side2 = nomsg [L432] side1 = s1p_old [L433] s1p_old = nomsg [L434] side2 = s2p_old [L435] s2p_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=1, s2p_old=-1, s2s1=0, s2s1_new=1, s2s1_old=-1, s2s2=0, s2s2_new=1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L436] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=1, s2p_old=-1, s2s1=0, s2s1_new=1, s2s1_old=-1, s2s2=0, s2s2_new=1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L439] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=1, s2p_old=-1, s2s1=0, s2s1_new=1, s2s1_old=-1, s2s2=0, s2s2_new=1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L442] COND FALSE !((int )side1 == 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=1, s2p_old=-1, s2s1=0, s2s1_new=1, s2s1_old=-1, s2s2=0, s2s2_new=1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L450] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=1, s2p_old=-1, s2s1=0, s2s1_new=1, s2s1_old=-1, s2s2=0, s2s2_new=1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L451] COND FALSE !((int )side2 == 0) [L454] active_side = (int8_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=1, s2p_old=-1, s2s1=0, s2s1_new=1, s2s1_old=-1, s2s2=0, s2s2_new=1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L179] active_side_History_2 = active_side_History_1 [L180] active_side_History_1 = active_side_History_0 [L181] active_side_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=1, s1p_old=-1, s1s1=0, s1s1_new=1, s1s1_old=-1, s1s2=0, s1s2_new=1, s1s2_old=-1, s2p=0, s2p_new=1, s2p_old=-1, s2s1=0, s2s1_new=1, s2s1_old=-1, s2s2=0, s2s2_new=1, s2s2_old=-1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L631] cs1_old = cs1_new [L632] cs1_new = nomsg [L633] cs2_old = cs2_new [L634] cs2_new = nomsg [L635] s1s2_old = s1s2_new [L636] s1s2_new = nomsg [L637] s1s1_old = s1s1_new [L638] s1s1_new = nomsg [L639] s2s1_old = s2s1_new [L640] s2s1_new = nomsg [L641] s2s2_old = s2s2_new [L642] s2s2_new = nomsg [L643] s1p_old = s1p_new [L644] s1p_new = nomsg [L645] s2p_old = s2p_new [L646] s2p_new = nomsg [L466] int tmp ; [L467] msg_t tmp___0 ; [L468] _Bool tmp___1 ; [L469] _Bool tmp___2 ; [L470] _Bool tmp___3 ; [L471] _Bool tmp___4 ; [L472] int8_t tmp___5 ; [L473] _Bool tmp___6 ; [L474] _Bool tmp___7 ; [L475] _Bool tmp___8 ; [L476] int8_t tmp___9 ; [L477] _Bool tmp___10 ; [L478] _Bool tmp___11 ; [L479] _Bool tmp___12 ; [L480] msg_t tmp___13 ; [L481] _Bool tmp___14 ; [L482] _Bool tmp___15 ; [L483] _Bool tmp___16 ; [L484] _Bool tmp___17 ; [L485] int8_t tmp___18 ; [L486] int8_t tmp___19 ; [L487] int8_t tmp___20 ; VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L490] COND TRUE ! side1Failed [L491] tmp = 1 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L220] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L223] COND TRUE (int )index == 1 [L224] return (manual_selection_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L499] tmp___0 = read_manual_selection_history((unsigned char)1) [L500] COND TRUE ! tmp___0 [L130] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L133] COND TRUE (int )index == 1 [L134] return (side1Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L501] tmp___1 = read_side1_failed_history((unsigned char)1) [L502] COND TRUE ! tmp___1 [L130] COND TRUE (int )index == 0 [L131] return (side1Failed_History_0); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L503] tmp___2 = read_side1_failed_history((unsigned char)0) [L504] COND TRUE ! tmp___2 [L160] COND FALSE !((int )index == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L163] COND TRUE (int )index == 1 [L164] return (side2Failed_History_1); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L505] tmp___3 = read_side2_failed_history((unsigned char)1) [L506] COND TRUE ! tmp___3 [L160] COND TRUE (int )index == 0 [L161] return (side2Failed_History_0); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L507] tmp___4 = read_side2_failed_history((unsigned char)0) [L508] COND TRUE ! tmp___4 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L509] COND FALSE !(! ((int )side1_written == 1)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L514] COND FALSE !(! (! ((int )side1_written == 0))) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L519] COND TRUE ! (! ((int )side1_written == 1)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L520] COND TRUE ! ((int )side2_written == 0) [L521] return (0); VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L647] c1 = check() [L659] COND TRUE ! arg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] [L661] __VERIFIER_error() VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=1, s1s1=0, s1s1_new=-1, s1s1_old=1, s1s2=0, s1s2_new=-1, s1s2_old=1, s2p=0, s2p_new=-1, s2p_old=1, s2s1=0, s2s1_new=-1, s2s1_old=1, s2s2=0, s2s2_new=-1, s2s2_old=1, side1_written=1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side2_written=1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 292 locations, 23 error locations. Result: UNSAFE, OverallTime: 8.6s, OverallIterations: 21, TraceHistogramMax: 1, AutomataDifference: 4.4s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 8997 SDtfs, 12932 SDslu, 14123 SDs, 0 SdLazy, 1323 SolverSat, 146 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.6s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 164 GetRequests, 63 SyntacticMatches, 8 SemanticMatches, 93 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 61 ImplicationChecksByTransitivity, 1.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=699occurred in iteration=19, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.9s AutomataMinimizationTime, 20 MinimizatonAttempts, 6903 StatesRemovedByMinimization, 18 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 0.7s SatisfiabilityAnalysisTime, 1.5s InterpolantComputationTime, 1320 NumberOfCodeBlocks, 1320 NumberOfCodeBlocksAsserted, 21 NumberOfCheckSat, 1225 ConstructedInterpolants, 0 QuantifiedInterpolants, 255377 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 20 InterpolantComputations, 20 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...