./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/pthread-wmm/safe010_rmo.oepc.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx12G -Xms1G -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/pthread-wmm/safe010_rmo.oepc.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ad7a03e4ce6743566424918d18fa966b8d8855df ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-11-28 18:27:35,982 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-28 18:27:35,984 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-28 18:27:36,001 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-28 18:27:36,002 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-28 18:27:36,004 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-28 18:27:36,006 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-28 18:27:36,014 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-28 18:27:36,016 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-28 18:27:36,019 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-28 18:27:36,021 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-28 18:27:36,023 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-28 18:27:36,024 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-28 18:27:36,027 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-28 18:27:36,028 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-28 18:27:36,030 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-28 18:27:36,032 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-28 18:27:36,036 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-28 18:27:36,038 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-28 18:27:36,042 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-28 18:27:36,045 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-28 18:27:36,048 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-28 18:27:36,051 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-28 18:27:36,052 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-28 18:27:36,056 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-28 18:27:36,056 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-28 18:27:36,057 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-28 18:27:36,058 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-28 18:27:36,058 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-28 18:27:36,059 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-28 18:27:36,060 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-28 18:27:36,060 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-28 18:27:36,061 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-28 18:27:36,062 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-28 18:27:36,063 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-28 18:27:36,063 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-28 18:27:36,064 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-28 18:27:36,064 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-28 18:27:36,065 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-28 18:27:36,066 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-28 18:27:36,067 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-28 18:27:36,067 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-28 18:27:36,084 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-28 18:27:36,085 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-28 18:27:36,087 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-28 18:27:36,087 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-28 18:27:36,087 INFO L138 SettingsManager]: * Use SBE=true [2019-11-28 18:27:36,088 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-28 18:27:36,088 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-28 18:27:36,088 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-28 18:27:36,088 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-28 18:27:36,089 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-28 18:27:36,090 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-28 18:27:36,090 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-28 18:27:36,090 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-28 18:27:36,091 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-28 18:27:36,091 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-28 18:27:36,091 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-28 18:27:36,092 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-28 18:27:36,092 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-28 18:27:36,092 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-28 18:27:36,093 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-28 18:27:36,093 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-28 18:27:36,093 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 18:27:36,094 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-28 18:27:36,094 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-28 18:27:36,094 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-28 18:27:36,094 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-28 18:27:36,095 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-28 18:27:36,095 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-28 18:27:36,095 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-11-28 18:27:36,096 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ad7a03e4ce6743566424918d18fa966b8d8855df [2019-11-28 18:27:36,401 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-28 18:27:36,420 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-28 18:27:36,424 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-28 18:27:36,426 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-28 18:27:36,427 INFO L275 PluginConnector]: CDTParser initialized [2019-11-28 18:27:36,428 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/pthread-wmm/safe010_rmo.oepc.i [2019-11-28 18:27:36,508 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/54bd2911e/55a4650d7d1b4032baf13effac7493d7/FLAG6c367c2b3 [2019-11-28 18:27:37,118 INFO L306 CDTParser]: Found 1 translation units. [2019-11-28 18:27:37,121 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/pthread-wmm/safe010_rmo.oepc.i [2019-11-28 18:27:37,141 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/54bd2911e/55a4650d7d1b4032baf13effac7493d7/FLAG6c367c2b3 [2019-11-28 18:27:37,345 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/54bd2911e/55a4650d7d1b4032baf13effac7493d7 [2019-11-28 18:27:37,348 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-28 18:27:37,350 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-28 18:27:37,351 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-28 18:27:37,351 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-28 18:27:37,354 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-28 18:27:37,355 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 06:27:37" (1/1) ... [2019-11-28 18:27:37,358 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3bd431ac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:27:37, skipping insertion in model container [2019-11-28 18:27:37,358 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 06:27:37" (1/1) ... [2019-11-28 18:27:37,366 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-11-28 18:27:37,412 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-11-28 18:27:37,855 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 18:27:37,867 INFO L203 MainTranslator]: Completed pre-run [2019-11-28 18:27:37,954 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 18:27:38,023 INFO L208 MainTranslator]: Completed translation [2019-11-28 18:27:38,023 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:27:38 WrapperNode [2019-11-28 18:27:38,024 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-28 18:27:38,025 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-28 18:27:38,025 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-28 18:27:38,025 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-28 18:27:38,034 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:27:38" (1/1) ... [2019-11-28 18:27:38,053 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:27:38" (1/1) ... [2019-11-28 18:27:38,091 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-28 18:27:38,092 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-28 18:27:38,092 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-28 18:27:38,092 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-28 18:27:38,102 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:27:38" (1/1) ... [2019-11-28 18:27:38,103 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:27:38" (1/1) ... [2019-11-28 18:27:38,108 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:27:38" (1/1) ... [2019-11-28 18:27:38,108 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:27:38" (1/1) ... [2019-11-28 18:27:38,118 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:27:38" (1/1) ... [2019-11-28 18:27:38,122 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:27:38" (1/1) ... [2019-11-28 18:27:38,125 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:27:38" (1/1) ... [2019-11-28 18:27:38,130 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-28 18:27:38,131 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-28 18:27:38,131 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-28 18:27:38,131 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-28 18:27:38,132 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:27:38" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 18:27:38,208 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-11-28 18:27:38,209 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-11-28 18:27:38,209 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-11-28 18:27:38,210 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-11-28 18:27:38,210 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-11-28 18:27:38,210 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-11-28 18:27:38,210 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-11-28 18:27:38,211 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-11-28 18:27:38,211 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-11-28 18:27:38,212 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-28 18:27:38,212 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-28 18:27:38,214 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-11-28 18:27:38,898 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-28 18:27:38,898 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-11-28 18:27:38,900 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:27:38 BoogieIcfgContainer [2019-11-28 18:27:38,900 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-28 18:27:38,902 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-28 18:27:38,902 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-28 18:27:38,904 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-28 18:27:38,905 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 06:27:37" (1/3) ... [2019-11-28 18:27:38,905 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@31efd924 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 06:27:38, skipping insertion in model container [2019-11-28 18:27:38,906 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:27:38" (2/3) ... [2019-11-28 18:27:38,906 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@31efd924 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 06:27:38, skipping insertion in model container [2019-11-28 18:27:38,906 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:27:38" (3/3) ... [2019-11-28 18:27:38,909 INFO L109 eAbstractionObserver]: Analyzing ICFG safe010_rmo.oepc.i [2019-11-28 18:27:38,919 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-11-28 18:27:38,920 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-28 18:27:38,927 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-11-28 18:27:38,928 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-11-28 18:27:38,963 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,963 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,964 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,964 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,964 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,964 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,965 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,965 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,966 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,966 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,966 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,967 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,967 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,967 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,967 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,968 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,968 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,968 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,968 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,968 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,969 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,969 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,969 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,970 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,970 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,970 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,971 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,971 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,971 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,971 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,972 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,972 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,972 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,972 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,973 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,973 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,973 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,973 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,974 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,974 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,974 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,974 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,975 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,975 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,975 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,975 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,976 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,976 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,976 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,976 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,977 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,977 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,977 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,977 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,978 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,978 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,978 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,978 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,979 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,979 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,979 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,979 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,980 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:38,980 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:27:39,001 INFO L249 AbstractCegarLoop]: Starting to check reachability of 5 error locations. [2019-11-28 18:27:39,018 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-28 18:27:39,018 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-28 18:27:39,018 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-28 18:27:39,019 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-28 18:27:39,019 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-28 18:27:39,019 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-28 18:27:39,019 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-28 18:27:39,019 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-28 18:27:39,037 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 146 places, 180 transitions [2019-11-28 18:27:39,039 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 146 places, 180 transitions [2019-11-28 18:27:39,125 INFO L134 PetriNetUnfolder]: 41/178 cut-off events. [2019-11-28 18:27:39,125 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-11-28 18:27:39,140 INFO L76 FinitePrefix]: Finished finitePrefix Result has 185 conditions, 178 events. 41/178 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 8. Compared 460 event pairs. 6/141 useless extension candidates. Maximal degree in co-relation 150. Up to 2 conditions per place. [2019-11-28 18:27:39,161 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 146 places, 180 transitions [2019-11-28 18:27:39,236 INFO L134 PetriNetUnfolder]: 41/178 cut-off events. [2019-11-28 18:27:39,236 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-11-28 18:27:39,245 INFO L76 FinitePrefix]: Finished finitePrefix Result has 185 conditions, 178 events. 41/178 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 8. Compared 460 event pairs. 6/141 useless extension candidates. Maximal degree in co-relation 150. Up to 2 conditions per place. [2019-11-28 18:27:39,264 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 10418 [2019-11-28 18:27:39,266 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-11-28 18:27:42,265 WARN L192 SmtUtils]: Spent 107.00 ms on a formula simplification. DAG size of input: 36 DAG size of output: 24 [2019-11-28 18:27:44,098 WARN L192 SmtUtils]: Spent 271.00 ms on a formula simplification. DAG size of input: 81 DAG size of output: 79 [2019-11-28 18:27:44,208 WARN L192 SmtUtils]: Spent 104.00 ms on a formula simplification that was a NOOP. DAG size: 77 [2019-11-28 18:27:44,237 INFO L206 etLargeBlockEncoding]: Checked pairs total: 46090 [2019-11-28 18:27:44,237 INFO L214 etLargeBlockEncoding]: Total number of compositions: 101 [2019-11-28 18:27:44,241 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 79 places, 91 transitions [2019-11-28 18:27:44,893 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 8654 states. [2019-11-28 18:27:44,896 INFO L276 IsEmpty]: Start isEmpty. Operand 8654 states. [2019-11-28 18:27:44,903 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-11-28 18:27:44,903 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:27:44,904 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-11-28 18:27:44,905 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:27:44,912 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:27:44,913 INFO L82 PathProgramCache]: Analyzing trace with hash 722891, now seen corresponding path program 1 times [2019-11-28 18:27:44,926 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:27:44,926 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1029914562] [2019-11-28 18:27:44,927 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:27:45,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:27:45,227 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:27:45,228 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1029914562] [2019-11-28 18:27:45,231 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:27:45,232 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-11-28 18:27:45,234 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1415749180] [2019-11-28 18:27:45,241 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:27:45,252 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:27:45,278 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:27:45,279 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:27:45,283 INFO L87 Difference]: Start difference. First operand 8654 states. Second operand 3 states. [2019-11-28 18:27:45,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:27:45,700 INFO L93 Difference]: Finished difference Result 8604 states and 28108 transitions. [2019-11-28 18:27:45,701 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:27:45,703 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2019-11-28 18:27:45,704 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:27:45,861 INFO L225 Difference]: With dead ends: 8604 [2019-11-28 18:27:45,866 INFO L226 Difference]: Without dead ends: 8436 [2019-11-28 18:27:45,868 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:27:46,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8436 states. [2019-11-28 18:27:46,343 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8436 to 8436. [2019-11-28 18:27:46,345 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8436 states. [2019-11-28 18:27:46,400 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8436 states to 8436 states and 27590 transitions. [2019-11-28 18:27:46,402 INFO L78 Accepts]: Start accepts. Automaton has 8436 states and 27590 transitions. Word has length 3 [2019-11-28 18:27:46,402 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:27:46,402 INFO L462 AbstractCegarLoop]: Abstraction has 8436 states and 27590 transitions. [2019-11-28 18:27:46,402 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:27:46,403 INFO L276 IsEmpty]: Start isEmpty. Operand 8436 states and 27590 transitions. [2019-11-28 18:27:46,406 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-11-28 18:27:46,407 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:27:46,407 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:27:46,408 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:27:46,408 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:27:46,408 INFO L82 PathProgramCache]: Analyzing trace with hash -1596153002, now seen corresponding path program 1 times [2019-11-28 18:27:46,409 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:27:46,409 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1652633393] [2019-11-28 18:27:46,409 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:27:46,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:27:46,565 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:27:46,565 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1652633393] [2019-11-28 18:27:46,565 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:27:46,565 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:27:46,566 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1927087796] [2019-11-28 18:27:46,568 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:27:46,568 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:27:46,569 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:27:46,569 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:27:46,569 INFO L87 Difference]: Start difference. First operand 8436 states and 27590 transitions. Second operand 4 states. [2019-11-28 18:27:47,006 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:27:47,007 INFO L93 Difference]: Finished difference Result 13130 states and 41153 transitions. [2019-11-28 18:27:47,007 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:27:47,007 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-11-28 18:27:47,008 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:27:47,108 INFO L225 Difference]: With dead ends: 13130 [2019-11-28 18:27:47,109 INFO L226 Difference]: Without dead ends: 13123 [2019-11-28 18:27:47,109 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:27:47,226 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13123 states. [2019-11-28 18:27:47,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13123 to 11988. [2019-11-28 18:27:47,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11988 states. [2019-11-28 18:27:47,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11988 states to 11988 states and 38075 transitions. [2019-11-28 18:27:47,731 INFO L78 Accepts]: Start accepts. Automaton has 11988 states and 38075 transitions. Word has length 11 [2019-11-28 18:27:47,732 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:27:47,732 INFO L462 AbstractCegarLoop]: Abstraction has 11988 states and 38075 transitions. [2019-11-28 18:27:47,732 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:27:47,732 INFO L276 IsEmpty]: Start isEmpty. Operand 11988 states and 38075 transitions. [2019-11-28 18:27:47,744 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-11-28 18:27:47,744 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:27:47,744 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:27:47,745 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:27:47,745 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:27:47,745 INFO L82 PathProgramCache]: Analyzing trace with hash 1194917716, now seen corresponding path program 1 times [2019-11-28 18:27:47,745 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:27:47,746 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1501720208] [2019-11-28 18:27:47,746 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:27:47,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:27:47,859 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:27:47,860 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1501720208] [2019-11-28 18:27:47,860 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:27:47,860 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:27:47,860 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1881516721] [2019-11-28 18:27:47,862 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:27:47,862 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:27:47,863 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:27:47,863 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:27:47,863 INFO L87 Difference]: Start difference. First operand 11988 states and 38075 transitions. Second operand 4 states. [2019-11-28 18:27:48,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:27:48,142 INFO L93 Difference]: Finished difference Result 14736 states and 46267 transitions. [2019-11-28 18:27:48,142 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:27:48,142 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-11-28 18:27:48,143 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:27:48,199 INFO L225 Difference]: With dead ends: 14736 [2019-11-28 18:27:48,199 INFO L226 Difference]: Without dead ends: 14736 [2019-11-28 18:27:48,200 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:27:48,300 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14736 states. [2019-11-28 18:27:48,608 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14736 to 13160. [2019-11-28 18:27:48,609 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13160 states. [2019-11-28 18:27:48,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13160 states to 13160 states and 41689 transitions. [2019-11-28 18:27:48,671 INFO L78 Accepts]: Start accepts. Automaton has 13160 states and 41689 transitions. Word has length 11 [2019-11-28 18:27:48,671 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:27:48,671 INFO L462 AbstractCegarLoop]: Abstraction has 13160 states and 41689 transitions. [2019-11-28 18:27:48,671 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:27:48,672 INFO L276 IsEmpty]: Start isEmpty. Operand 13160 states and 41689 transitions. [2019-11-28 18:27:48,677 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2019-11-28 18:27:48,678 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:27:48,678 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:27:48,679 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:27:48,679 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:27:48,680 INFO L82 PathProgramCache]: Analyzing trace with hash -1502155024, now seen corresponding path program 1 times [2019-11-28 18:27:48,680 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:27:48,682 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1004868740] [2019-11-28 18:27:48,682 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:27:48,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:27:48,764 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:27:48,764 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1004868740] [2019-11-28 18:27:48,765 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:27:48,765 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:27:48,765 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [839285748] [2019-11-28 18:27:48,765 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:27:48,766 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:27:48,766 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:27:48,766 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:27:48,766 INFO L87 Difference]: Start difference. First operand 13160 states and 41689 transitions. Second operand 5 states. [2019-11-28 18:27:49,259 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:27:49,259 INFO L93 Difference]: Finished difference Result 17572 states and 54523 transitions. [2019-11-28 18:27:49,260 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-11-28 18:27:49,260 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2019-11-28 18:27:49,261 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:27:49,324 INFO L225 Difference]: With dead ends: 17572 [2019-11-28 18:27:49,324 INFO L226 Difference]: Without dead ends: 17565 [2019-11-28 18:27:49,325 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-11-28 18:27:49,437 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17565 states. [2019-11-28 18:27:49,918 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17565 to 13105. [2019-11-28 18:27:49,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13105 states. [2019-11-28 18:27:49,964 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13105 states to 13105 states and 41426 transitions. [2019-11-28 18:27:49,964 INFO L78 Accepts]: Start accepts. Automaton has 13105 states and 41426 transitions. Word has length 17 [2019-11-28 18:27:49,964 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:27:49,965 INFO L462 AbstractCegarLoop]: Abstraction has 13105 states and 41426 transitions. [2019-11-28 18:27:49,965 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:27:49,965 INFO L276 IsEmpty]: Start isEmpty. Operand 13105 states and 41426 transitions. [2019-11-28 18:27:49,977 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-11-28 18:27:49,978 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:27:49,978 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:27:49,978 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:27:49,978 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:27:49,979 INFO L82 PathProgramCache]: Analyzing trace with hash 933350131, now seen corresponding path program 1 times [2019-11-28 18:27:49,979 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:27:49,979 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [610985346] [2019-11-28 18:27:49,980 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:27:49,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:27:50,045 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:27:50,045 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [610985346] [2019-11-28 18:27:50,046 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:27:50,046 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:27:50,046 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1924195954] [2019-11-28 18:27:50,046 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:27:50,047 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:27:50,047 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:27:50,047 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:27:50,047 INFO L87 Difference]: Start difference. First operand 13105 states and 41426 transitions. Second operand 3 states. [2019-11-28 18:27:50,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:27:50,171 INFO L93 Difference]: Finished difference Result 16057 states and 50095 transitions. [2019-11-28 18:27:50,171 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:27:50,172 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2019-11-28 18:27:50,172 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:27:50,213 INFO L225 Difference]: With dead ends: 16057 [2019-11-28 18:27:50,214 INFO L226 Difference]: Without dead ends: 16057 [2019-11-28 18:27:50,215 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:27:50,310 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16057 states. [2019-11-28 18:27:50,600 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16057 to 14186. [2019-11-28 18:27:50,601 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14186 states. [2019-11-28 18:27:50,664 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14186 states to 14186 states and 44710 transitions. [2019-11-28 18:27:50,664 INFO L78 Accepts]: Start accepts. Automaton has 14186 states and 44710 transitions. Word has length 25 [2019-11-28 18:27:50,666 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:27:50,667 INFO L462 AbstractCegarLoop]: Abstraction has 14186 states and 44710 transitions. [2019-11-28 18:27:50,667 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:27:50,667 INFO L276 IsEmpty]: Start isEmpty. Operand 14186 states and 44710 transitions. [2019-11-28 18:27:50,687 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-11-28 18:27:50,688 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:27:50,688 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:27:50,688 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:27:50,689 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:27:50,689 INFO L82 PathProgramCache]: Analyzing trace with hash 933194542, now seen corresponding path program 1 times [2019-11-28 18:27:50,690 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:27:50,690 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [709643004] [2019-11-28 18:27:50,690 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:27:50,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:27:50,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:27:50,819 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [709643004] [2019-11-28 18:27:50,820 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:27:50,820 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:27:50,820 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [494706908] [2019-11-28 18:27:50,821 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:27:50,821 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:27:50,821 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:27:50,821 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:27:50,821 INFO L87 Difference]: Start difference. First operand 14186 states and 44710 transitions. Second operand 4 states. [2019-11-28 18:27:50,872 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:27:50,873 INFO L93 Difference]: Finished difference Result 2296 states and 5226 transitions. [2019-11-28 18:27:50,873 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-28 18:27:50,873 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 25 [2019-11-28 18:27:50,874 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:27:50,877 INFO L225 Difference]: With dead ends: 2296 [2019-11-28 18:27:50,878 INFO L226 Difference]: Without dead ends: 2019 [2019-11-28 18:27:50,878 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:27:50,885 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2019 states. [2019-11-28 18:27:50,920 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2019 to 2019. [2019-11-28 18:27:50,920 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2019 states. [2019-11-28 18:27:50,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2019 states to 2019 states and 4460 transitions. [2019-11-28 18:27:50,927 INFO L78 Accepts]: Start accepts. Automaton has 2019 states and 4460 transitions. Word has length 25 [2019-11-28 18:27:50,927 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:27:50,927 INFO L462 AbstractCegarLoop]: Abstraction has 2019 states and 4460 transitions. [2019-11-28 18:27:50,928 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:27:50,928 INFO L276 IsEmpty]: Start isEmpty. Operand 2019 states and 4460 transitions. [2019-11-28 18:27:50,931 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-11-28 18:27:50,931 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:27:50,932 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:27:50,932 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:27:50,932 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:27:50,932 INFO L82 PathProgramCache]: Analyzing trace with hash -568804126, now seen corresponding path program 1 times [2019-11-28 18:27:50,933 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:27:50,933 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1635452581] [2019-11-28 18:27:50,933 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:27:50,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:27:51,043 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:27:51,043 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1635452581] [2019-11-28 18:27:51,043 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:27:51,044 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 18:27:51,044 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [395692573] [2019-11-28 18:27:51,044 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:27:51,044 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:27:51,045 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:27:51,045 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:27:51,045 INFO L87 Difference]: Start difference. First operand 2019 states and 4460 transitions. Second operand 5 states. [2019-11-28 18:27:51,090 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:27:51,090 INFO L93 Difference]: Finished difference Result 416 states and 758 transitions. [2019-11-28 18:27:51,091 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:27:51,091 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 37 [2019-11-28 18:27:51,092 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:27:51,092 INFO L225 Difference]: With dead ends: 416 [2019-11-28 18:27:51,092 INFO L226 Difference]: Without dead ends: 371 [2019-11-28 18:27:51,093 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-11-28 18:27:51,095 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 371 states. [2019-11-28 18:27:51,098 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 371 to 343. [2019-11-28 18:27:51,098 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 343 states. [2019-11-28 18:27:51,099 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 343 states to 343 states and 618 transitions. [2019-11-28 18:27:51,100 INFO L78 Accepts]: Start accepts. Automaton has 343 states and 618 transitions. Word has length 37 [2019-11-28 18:27:51,100 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:27:51,101 INFO L462 AbstractCegarLoop]: Abstraction has 343 states and 618 transitions. [2019-11-28 18:27:51,101 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:27:51,101 INFO L276 IsEmpty]: Start isEmpty. Operand 343 states and 618 transitions. [2019-11-28 18:27:51,105 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2019-11-28 18:27:51,105 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:27:51,106 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:27:51,106 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:27:51,106 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:27:51,108 INFO L82 PathProgramCache]: Analyzing trace with hash -506418728, now seen corresponding path program 1 times [2019-11-28 18:27:51,108 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:27:51,109 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1065852797] [2019-11-28 18:27:51,109 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:27:51,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:27:51,241 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:27:51,242 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1065852797] [2019-11-28 18:27:51,242 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:27:51,242 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-11-28 18:27:51,242 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2093371136] [2019-11-28 18:27:51,243 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-11-28 18:27:51,243 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:27:51,243 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-11-28 18:27:51,244 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-11-28 18:27:51,244 INFO L87 Difference]: Start difference. First operand 343 states and 618 transitions. Second operand 7 states. [2019-11-28 18:27:51,675 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:27:51,676 INFO L93 Difference]: Finished difference Result 539 states and 970 transitions. [2019-11-28 18:27:51,676 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-11-28 18:27:51,676 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 52 [2019-11-28 18:27:51,677 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:27:51,678 INFO L225 Difference]: With dead ends: 539 [2019-11-28 18:27:51,678 INFO L226 Difference]: Without dead ends: 539 [2019-11-28 18:27:51,678 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=80, Unknown=0, NotChecked=0, Total=110 [2019-11-28 18:27:51,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 539 states. [2019-11-28 18:27:51,687 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 539 to 444. [2019-11-28 18:27:51,687 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 444 states. [2019-11-28 18:27:51,688 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 444 states to 444 states and 802 transitions. [2019-11-28 18:27:51,688 INFO L78 Accepts]: Start accepts. Automaton has 444 states and 802 transitions. Word has length 52 [2019-11-28 18:27:51,691 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:27:51,691 INFO L462 AbstractCegarLoop]: Abstraction has 444 states and 802 transitions. [2019-11-28 18:27:51,691 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-11-28 18:27:51,692 INFO L276 IsEmpty]: Start isEmpty. Operand 444 states and 802 transitions. [2019-11-28 18:27:51,693 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2019-11-28 18:27:51,693 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:27:51,693 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:27:51,693 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:27:51,694 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:27:51,694 INFO L82 PathProgramCache]: Analyzing trace with hash 22285210, now seen corresponding path program 2 times [2019-11-28 18:27:51,694 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:27:51,701 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [832831783] [2019-11-28 18:27:51,702 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:27:51,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:27:51,847 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:27:51,847 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [832831783] [2019-11-28 18:27:51,849 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:27:51,850 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 18:27:51,851 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [93136889] [2019-11-28 18:27:51,851 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:27:51,851 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:27:51,852 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:27:51,852 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:27:51,852 INFO L87 Difference]: Start difference. First operand 444 states and 802 transitions. Second operand 5 states. [2019-11-28 18:27:52,040 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:27:52,040 INFO L93 Difference]: Finished difference Result 621 states and 1127 transitions. [2019-11-28 18:27:52,041 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 18:27:52,041 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 52 [2019-11-28 18:27:52,041 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:27:52,042 INFO L225 Difference]: With dead ends: 621 [2019-11-28 18:27:52,042 INFO L226 Difference]: Without dead ends: 621 [2019-11-28 18:27:52,043 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-11-28 18:27:52,044 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 621 states. [2019-11-28 18:27:52,054 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 621 to 504. [2019-11-28 18:27:52,054 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 504 states. [2019-11-28 18:27:52,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 504 states to 504 states and 921 transitions. [2019-11-28 18:27:52,055 INFO L78 Accepts]: Start accepts. Automaton has 504 states and 921 transitions. Word has length 52 [2019-11-28 18:27:52,056 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:27:52,056 INFO L462 AbstractCegarLoop]: Abstraction has 504 states and 921 transitions. [2019-11-28 18:27:52,056 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:27:52,056 INFO L276 IsEmpty]: Start isEmpty. Operand 504 states and 921 transitions. [2019-11-28 18:27:52,057 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2019-11-28 18:27:52,058 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:27:52,058 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:27:52,058 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:27:52,058 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:27:52,058 INFO L82 PathProgramCache]: Analyzing trace with hash 260455414, now seen corresponding path program 3 times [2019-11-28 18:27:52,061 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:27:52,061 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1548915287] [2019-11-28 18:27:52,061 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:27:52,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:27:52,210 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:27:52,211 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1548915287] [2019-11-28 18:27:52,211 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:27:52,211 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-28 18:27:52,212 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1771229783] [2019-11-28 18:27:52,212 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-28 18:27:52,213 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:27:52,213 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-28 18:27:52,213 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-28 18:27:52,214 INFO L87 Difference]: Start difference. First operand 504 states and 921 transitions. Second operand 6 states. [2019-11-28 18:27:52,541 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:27:52,541 INFO L93 Difference]: Finished difference Result 719 states and 1302 transitions. [2019-11-28 18:27:52,542 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-28 18:27:52,542 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 52 [2019-11-28 18:27:52,543 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:27:52,544 INFO L225 Difference]: With dead ends: 719 [2019-11-28 18:27:52,544 INFO L226 Difference]: Without dead ends: 719 [2019-11-28 18:27:52,544 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=32, Invalid=78, Unknown=0, NotChecked=0, Total=110 [2019-11-28 18:27:52,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 719 states. [2019-11-28 18:27:52,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 719 to 516. [2019-11-28 18:27:52,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 516 states. [2019-11-28 18:27:52,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 516 states to 516 states and 943 transitions. [2019-11-28 18:27:52,554 INFO L78 Accepts]: Start accepts. Automaton has 516 states and 943 transitions. Word has length 52 [2019-11-28 18:27:52,554 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:27:52,554 INFO L462 AbstractCegarLoop]: Abstraction has 516 states and 943 transitions. [2019-11-28 18:27:52,555 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-28 18:27:52,555 INFO L276 IsEmpty]: Start isEmpty. Operand 516 states and 943 transitions. [2019-11-28 18:27:52,557 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2019-11-28 18:27:52,557 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:27:52,557 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:27:52,558 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:27:52,558 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:27:52,558 INFO L82 PathProgramCache]: Analyzing trace with hash -681731879, now seen corresponding path program 1 times [2019-11-28 18:27:52,558 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:27:52,559 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [613790653] [2019-11-28 18:27:52,559 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:27:52,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:27:52,974 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:27:52,974 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [613790653] [2019-11-28 18:27:52,974 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:27:52,974 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-11-28 18:27:52,975 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [642246847] [2019-11-28 18:27:52,975 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-11-28 18:27:52,975 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:27:52,976 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-11-28 18:27:52,976 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2019-11-28 18:27:52,976 INFO L87 Difference]: Start difference. First operand 516 states and 943 transitions. Second operand 12 states. [2019-11-28 18:27:53,539 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:27:53,540 INFO L93 Difference]: Finished difference Result 978 states and 1768 transitions. [2019-11-28 18:27:53,540 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-11-28 18:27:53,540 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 53 [2019-11-28 18:27:53,541 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:27:53,541 INFO L225 Difference]: With dead ends: 978 [2019-11-28 18:27:53,542 INFO L226 Difference]: Without dead ends: 471 [2019-11-28 18:27:53,542 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 52 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=104, Invalid=276, Unknown=0, NotChecked=0, Total=380 [2019-11-28 18:27:53,544 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 471 states. [2019-11-28 18:27:53,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 471 to 407. [2019-11-28 18:27:53,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 407 states. [2019-11-28 18:27:53,549 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 407 states to 407 states and 753 transitions. [2019-11-28 18:27:53,549 INFO L78 Accepts]: Start accepts. Automaton has 407 states and 753 transitions. Word has length 53 [2019-11-28 18:27:53,549 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:27:53,549 INFO L462 AbstractCegarLoop]: Abstraction has 407 states and 753 transitions. [2019-11-28 18:27:53,549 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-11-28 18:27:53,549 INFO L276 IsEmpty]: Start isEmpty. Operand 407 states and 753 transitions. [2019-11-28 18:27:53,550 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2019-11-28 18:27:53,551 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:27:53,551 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:27:53,551 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:27:53,551 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:27:53,551 INFO L82 PathProgramCache]: Analyzing trace with hash -983517111, now seen corresponding path program 1 times [2019-11-28 18:27:53,552 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:27:53,552 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [678034611] [2019-11-28 18:27:53,552 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:27:53,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:27:53,615 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:27:53,616 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [678034611] [2019-11-28 18:27:53,616 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:27:53,616 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:27:53,616 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [560115662] [2019-11-28 18:27:53,617 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:27:53,617 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:27:53,617 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:27:53,617 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:27:53,617 INFO L87 Difference]: Start difference. First operand 407 states and 753 transitions. Second operand 3 states. [2019-11-28 18:27:53,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:27:53,627 INFO L93 Difference]: Finished difference Result 357 states and 640 transitions. [2019-11-28 18:27:53,628 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:27:53,628 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 53 [2019-11-28 18:27:53,628 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:27:53,629 INFO L225 Difference]: With dead ends: 357 [2019-11-28 18:27:53,629 INFO L226 Difference]: Without dead ends: 357 [2019-11-28 18:27:53,629 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:27:53,630 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 357 states. [2019-11-28 18:27:53,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 357 to 357. [2019-11-28 18:27:53,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 357 states. [2019-11-28 18:27:53,634 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 357 states to 357 states and 640 transitions. [2019-11-28 18:27:53,635 INFO L78 Accepts]: Start accepts. Automaton has 357 states and 640 transitions. Word has length 53 [2019-11-28 18:27:53,635 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:27:53,635 INFO L462 AbstractCegarLoop]: Abstraction has 357 states and 640 transitions. [2019-11-28 18:27:53,635 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:27:53,636 INFO L276 IsEmpty]: Start isEmpty. Operand 357 states and 640 transitions. [2019-11-28 18:27:53,637 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2019-11-28 18:27:53,637 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:27:53,638 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:27:53,638 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:27:53,638 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:27:53,638 INFO L82 PathProgramCache]: Analyzing trace with hash -1828454951, now seen corresponding path program 2 times [2019-11-28 18:27:53,638 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:27:53,639 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1457372853] [2019-11-28 18:27:53,639 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:27:53,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:27:53,726 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:27:53,727 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1457372853] [2019-11-28 18:27:53,727 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:27:53,727 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:27:53,727 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2076684946] [2019-11-28 18:27:53,728 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:27:53,728 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:27:53,728 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:27:53,729 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:27:53,729 INFO L87 Difference]: Start difference. First operand 357 states and 640 transitions. Second operand 3 states. [2019-11-28 18:27:53,765 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:27:53,765 INFO L93 Difference]: Finished difference Result 357 states and 639 transitions. [2019-11-28 18:27:53,765 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:27:53,766 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 53 [2019-11-28 18:27:53,766 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:27:53,766 INFO L225 Difference]: With dead ends: 357 [2019-11-28 18:27:53,766 INFO L226 Difference]: Without dead ends: 357 [2019-11-28 18:27:53,768 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:27:53,769 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 357 states. [2019-11-28 18:27:53,772 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 357 to 221. [2019-11-28 18:27:53,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 221 states. [2019-11-28 18:27:53,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 221 states to 221 states and 391 transitions. [2019-11-28 18:27:53,773 INFO L78 Accepts]: Start accepts. Automaton has 221 states and 391 transitions. Word has length 53 [2019-11-28 18:27:53,774 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:27:53,774 INFO L462 AbstractCegarLoop]: Abstraction has 221 states and 391 transitions. [2019-11-28 18:27:53,774 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:27:53,774 INFO L276 IsEmpty]: Start isEmpty. Operand 221 states and 391 transitions. [2019-11-28 18:27:53,775 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-11-28 18:27:53,775 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:27:53,775 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:27:53,775 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:27:53,776 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:27:53,776 INFO L82 PathProgramCache]: Analyzing trace with hash -1034362442, now seen corresponding path program 1 times [2019-11-28 18:27:53,776 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:27:53,777 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1850679526] [2019-11-28 18:27:53,777 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:27:53,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:27:54,103 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:27:54,103 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1850679526] [2019-11-28 18:27:54,104 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:27:54,104 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-11-28 18:27:54,104 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [249505204] [2019-11-28 18:27:54,105 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-11-28 18:27:54,105 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:27:54,105 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-11-28 18:27:54,106 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=149, Unknown=0, NotChecked=0, Total=182 [2019-11-28 18:27:54,106 INFO L87 Difference]: Start difference. First operand 221 states and 391 transitions. Second operand 14 states. [2019-11-28 18:27:54,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:27:54,780 INFO L93 Difference]: Finished difference Result 382 states and 654 transitions. [2019-11-28 18:27:54,780 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-11-28 18:27:54,781 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 54 [2019-11-28 18:27:54,781 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:27:54,782 INFO L225 Difference]: With dead ends: 382 [2019-11-28 18:27:54,782 INFO L226 Difference]: Without dead ends: 347 [2019-11-28 18:27:54,783 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 85 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=107, Invalid=493, Unknown=0, NotChecked=0, Total=600 [2019-11-28 18:27:54,784 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 347 states. [2019-11-28 18:27:54,787 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 347 to 317. [2019-11-28 18:27:54,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 317 states. [2019-11-28 18:27:54,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 317 states to 317 states and 555 transitions. [2019-11-28 18:27:54,788 INFO L78 Accepts]: Start accepts. Automaton has 317 states and 555 transitions. Word has length 54 [2019-11-28 18:27:54,788 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:27:54,788 INFO L462 AbstractCegarLoop]: Abstraction has 317 states and 555 transitions. [2019-11-28 18:27:54,788 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-11-28 18:27:54,788 INFO L276 IsEmpty]: Start isEmpty. Operand 317 states and 555 transitions. [2019-11-28 18:27:54,789 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-11-28 18:27:54,789 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:27:54,789 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:27:54,789 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:27:54,790 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:27:54,790 INFO L82 PathProgramCache]: Analyzing trace with hash -1623394108, now seen corresponding path program 2 times [2019-11-28 18:27:54,790 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:27:54,790 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2052039270] [2019-11-28 18:27:54,790 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:27:54,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:27:55,490 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:27:55,490 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2052039270] [2019-11-28 18:27:55,490 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:27:55,490 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [19] imperfect sequences [] total 19 [2019-11-28 18:27:55,491 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [244650379] [2019-11-28 18:27:55,491 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-11-28 18:27:55,491 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:27:55,491 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-11-28 18:27:55,492 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=345, Unknown=0, NotChecked=0, Total=420 [2019-11-28 18:27:55,492 INFO L87 Difference]: Start difference. First operand 317 states and 555 transitions. Second operand 21 states. [2019-11-28 18:27:56,729 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:27:56,730 INFO L93 Difference]: Finished difference Result 631 states and 1083 transitions. [2019-11-28 18:27:56,730 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2019-11-28 18:27:56,730 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 54 [2019-11-28 18:27:56,731 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:27:56,731 INFO L225 Difference]: With dead ends: 631 [2019-11-28 18:27:56,732 INFO L226 Difference]: Without dead ends: 598 [2019-11-28 18:27:56,733 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 0 SyntacticMatches, 4 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 318 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=206, Invalid=1054, Unknown=0, NotChecked=0, Total=1260 [2019-11-28 18:27:56,735 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 598 states. [2019-11-28 18:27:56,741 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 598 to 336. [2019-11-28 18:27:56,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 336 states. [2019-11-28 18:27:56,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 336 states to 336 states and 592 transitions. [2019-11-28 18:27:56,742 INFO L78 Accepts]: Start accepts. Automaton has 336 states and 592 transitions. Word has length 54 [2019-11-28 18:27:56,744 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:27:56,744 INFO L462 AbstractCegarLoop]: Abstraction has 336 states and 592 transitions. [2019-11-28 18:27:56,744 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-11-28 18:27:56,744 INFO L276 IsEmpty]: Start isEmpty. Operand 336 states and 592 transitions. [2019-11-28 18:27:56,745 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-11-28 18:27:56,745 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:27:56,745 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:27:56,745 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:27:56,745 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:27:56,746 INFO L82 PathProgramCache]: Analyzing trace with hash -521424182, now seen corresponding path program 3 times [2019-11-28 18:27:56,746 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:27:56,746 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1090301672] [2019-11-28 18:27:56,746 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:27:56,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:27:56,991 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:27:56,992 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1090301672] [2019-11-28 18:27:56,995 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:27:56,995 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-11-28 18:27:56,995 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1735582347] [2019-11-28 18:27:56,996 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-11-28 18:27:56,996 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:27:56,997 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-11-28 18:27:56,997 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=148, Unknown=0, NotChecked=0, Total=182 [2019-11-28 18:27:56,997 INFO L87 Difference]: Start difference. First operand 336 states and 592 transitions. Second operand 14 states. [2019-11-28 18:27:57,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:27:57,436 INFO L93 Difference]: Finished difference Result 463 states and 789 transitions. [2019-11-28 18:27:57,437 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-11-28 18:27:57,437 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 54 [2019-11-28 18:27:57,437 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:27:57,438 INFO L225 Difference]: With dead ends: 463 [2019-11-28 18:27:57,438 INFO L226 Difference]: Without dead ends: 430 [2019-11-28 18:27:57,439 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 69 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=84, Invalid=378, Unknown=0, NotChecked=0, Total=462 [2019-11-28 18:27:57,439 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states. [2019-11-28 18:27:57,442 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 321. [2019-11-28 18:27:57,443 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 321 states. [2019-11-28 18:27:57,443 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 321 states to 321 states and 562 transitions. [2019-11-28 18:27:57,444 INFO L78 Accepts]: Start accepts. Automaton has 321 states and 562 transitions. Word has length 54 [2019-11-28 18:27:57,444 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:27:57,444 INFO L462 AbstractCegarLoop]: Abstraction has 321 states and 562 transitions. [2019-11-28 18:27:57,445 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-11-28 18:27:57,445 INFO L276 IsEmpty]: Start isEmpty. Operand 321 states and 562 transitions. [2019-11-28 18:27:57,448 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-11-28 18:27:57,448 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:27:57,448 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:27:57,448 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:27:57,449 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:27:57,449 INFO L82 PathProgramCache]: Analyzing trace with hash 1326135034, now seen corresponding path program 4 times [2019-11-28 18:27:57,449 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:27:57,449 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1732013300] [2019-11-28 18:27:57,450 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:27:57,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:27:57,894 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:27:57,895 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1732013300] [2019-11-28 18:27:57,896 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:27:57,896 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-11-28 18:27:57,896 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2030007578] [2019-11-28 18:27:57,897 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-11-28 18:27:57,897 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:27:57,897 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-11-28 18:27:57,898 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=125, Unknown=0, NotChecked=0, Total=156 [2019-11-28 18:27:57,898 INFO L87 Difference]: Start difference. First operand 321 states and 562 transitions. Second operand 13 states. [2019-11-28 18:27:58,319 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:27:58,319 INFO L93 Difference]: Finished difference Result 426 states and 719 transitions. [2019-11-28 18:27:58,320 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-11-28 18:27:58,320 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 54 [2019-11-28 18:27:58,320 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:27:58,321 INFO L225 Difference]: With dead ends: 426 [2019-11-28 18:27:58,321 INFO L226 Difference]: Without dead ends: 391 [2019-11-28 18:27:58,321 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 75 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=97, Invalid=409, Unknown=0, NotChecked=0, Total=506 [2019-11-28 18:27:58,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 391 states. [2019-11-28 18:27:58,327 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 391 to 329. [2019-11-28 18:27:58,327 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 329 states. [2019-11-28 18:27:58,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 329 states to 329 states and 576 transitions. [2019-11-28 18:27:58,328 INFO L78 Accepts]: Start accepts. Automaton has 329 states and 576 transitions. Word has length 54 [2019-11-28 18:27:58,329 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:27:58,329 INFO L462 AbstractCegarLoop]: Abstraction has 329 states and 576 transitions. [2019-11-28 18:27:58,329 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-11-28 18:27:58,329 INFO L276 IsEmpty]: Start isEmpty. Operand 329 states and 576 transitions. [2019-11-28 18:27:58,333 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-11-28 18:27:58,333 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:27:58,334 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:27:58,334 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:27:58,334 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:27:58,334 INFO L82 PathProgramCache]: Analyzing trace with hash -91775718, now seen corresponding path program 5 times [2019-11-28 18:27:58,334 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:27:58,335 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1604633422] [2019-11-28 18:27:58,335 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:27:58,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 18:27:58,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 18:27:58,467 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-28 18:27:58,467 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-28 18:27:58,471 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [702] [702] ULTIMATE.startENTRY-->L779: Formula: (let ((.cse0 (store |v_#valid_47| 0 0))) (and (= 0 v_~y$read_delayed_var~0.base_6) (= v_~y$r_buff1_thd0~0_329 0) (= v_~y$w_buff0_used~0_834 0) (= 0 |v_ULTIMATE.start_main_~#t2017~0.offset_19|) (= 0 v_~__unbuffered_cnt~0_61) (= |v_#valid_45| (store .cse0 |v_ULTIMATE.start_main_~#t2017~0.base_24| 1)) (= 0 v_~weak$$choice0~0_14) (= v_~y$r_buff1_thd1~0_200 0) (= 0 v_~x~0_147) (= |v_#NULL.offset_3| 0) (= v_~main$tmp_guard1~0_27 0) (= v_~y$read_delayed~0_6 0) (= 0 v_~__unbuffered_p1_EAX~0_29) (< |v_#StackHeapBarrier_13| |v_ULTIMATE.start_main_~#t2017~0.base_24|) (= 0 v_~y$r_buff1_thd2~0_208) (= 0 v_~y$r_buff0_thd2~0_162) (= v_~y$mem_tmp~0_19 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t2017~0.base_24|)) (= v_~weak$$choice2~0_141 0) (= v_~y$w_buff1_used~0_547 0) (= (store |v_#length_14| |v_ULTIMATE.start_main_~#t2017~0.base_24| 4) |v_#length_13|) (= v_~y$r_buff0_thd1~0_297 0) (= 0 v_~y$flush_delayed~0_36) (= v_~main$tmp_guard0~0_33 0) (= 0 |v_#NULL.base_3|) (= 0 v_~y$w_buff0~0_485) (= 0 v_~y$read_delayed_var~0.offset_6) (= v_~y$r_buff0_thd0~0_416 0) (= v_~y~0_146 0) (< 0 |v_#StackHeapBarrier_13|) (= (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t2017~0.base_24| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t2017~0.base_24|) |v_ULTIMATE.start_main_~#t2017~0.offset_19| 0)) |v_#memory_int_11|) (= v_~y$w_buff1~0_308 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_47|, #memory_int=|v_#memory_int_12|, #length=|v_#length_14|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_41|, #NULL.offset=|v_#NULL.offset_3|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_35|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_145|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_48|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_37|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_36|, ~y$read_delayed~0=v_~y$read_delayed~0_6, ~y$mem_tmp~0=v_~y$mem_tmp~0_19, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_29, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_297, ~y$flush_delayed~0=v_~y$flush_delayed~0_36, ULTIMATE.start_main_~#t2017~0.base=|v_ULTIMATE.start_main_~#t2017~0.base_24|, #length=|v_#length_13|, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_36|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_38|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_21|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_27|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_41|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_44|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_38|, ~weak$$choice0~0=v_~weak$$choice0~0_14, #StackHeapBarrier=|v_#StackHeapBarrier_13|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_36|, ~y$w_buff1~0=v_~y$w_buff1~0_308, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_6, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_162, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_10|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_61, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_329, ~x~0=v_~x~0_147, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_6, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_834, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_36|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_33|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_27, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_43|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_33|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_42|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_34|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_200, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_34|, ~y$w_buff0~0=v_~y$w_buff0~0_485, ~y~0=v_~y~0_146, ULTIMATE.start_main_#t~ite17=|v_ULTIMATE.start_main_#t~ite17_29|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_21|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_33|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_53|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_27|, ULTIMATE.start_main_~#t2018~0.offset=|v_ULTIMATE.start_main_~#t2018~0.offset_16|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_33, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_35|, #NULL.base=|v_#NULL.base_3|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_40|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_208, ULTIMATE.start_main_~#t2018~0.base=|v_ULTIMATE.start_main_~#t2018~0.base_19|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_37|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_18|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_416, #valid=|v_#valid_45|, #memory_int=|v_#memory_int_11|, ULTIMATE.start_main_~#t2017~0.offset=|v_ULTIMATE.start_main_~#t2017~0.offset_19|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_14|, ~weak$$choice2~0=v_~weak$$choice2~0_141, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_547} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~y$read_delayed~0, ~y$mem_tmp~0, ~__unbuffered_p1_EAX~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, ULTIMATE.start_main_~#t2017~0.base, #length, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ~y$w_buff0~0, ~y~0, ULTIMATE.start_main_#t~ite17, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ULTIMATE.start_main_~#t2018~0.offset, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_~#t2018~0.base, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_~#t2017~0.offset, ULTIMATE.start_main_#t~nondet16, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:27:58,472 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [675] [675] L779-1-->L781: Formula: (and (not (= 0 |v_ULTIMATE.start_main_~#t2018~0.base_11|)) (< |v_#StackHeapBarrier_8| |v_ULTIMATE.start_main_~#t2018~0.base_11|) (= 0 (select |v_#valid_28| |v_ULTIMATE.start_main_~#t2018~0.base_11|)) (= |v_#memory_int_7| (store |v_#memory_int_8| |v_ULTIMATE.start_main_~#t2018~0.base_11| (store (select |v_#memory_int_8| |v_ULTIMATE.start_main_~#t2018~0.base_11|) |v_ULTIMATE.start_main_~#t2018~0.offset_10| 1))) (= |v_#length_9| (store |v_#length_10| |v_ULTIMATE.start_main_~#t2018~0.base_11| 4)) (= (store |v_#valid_28| |v_ULTIMATE.start_main_~#t2018~0.base_11| 1) |v_#valid_27|) (= 0 |v_ULTIMATE.start_main_~#t2018~0.offset_10|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_8|, #valid=|v_#valid_28|, #memory_int=|v_#memory_int_8|, #length=|v_#length_10|} OutVars{ULTIMATE.start_main_~#t2018~0.base=|v_ULTIMATE.start_main_~#t2018~0.base_11|, #StackHeapBarrier=|v_#StackHeapBarrier_8|, #valid=|v_#valid_27|, #memory_int=|v_#memory_int_7|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_6|, ULTIMATE.start_main_~#t2018~0.offset=|v_ULTIMATE.start_main_~#t2018~0.offset_10|, #length=|v_#length_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2018~0.base, #valid, #memory_int, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_~#t2018~0.offset, #length] because there is no mapped edge [2019-11-28 18:27:58,472 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [638] [638] P0ENTRY-->L4-3: Formula: (and (= v_~y$w_buff1~0_121 v_~y$w_buff0~0_204) (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_98 0)) (= v_P0Thread1of1ForFork0_~arg.base_94 |v_P0Thread1of1ForFork0_#in~arg.base_96|) (= 2 v_~y$w_buff0~0_203) (= |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_94| (ite (not (and (not (= 0 (mod v_~y$w_buff0_used~0_349 256))) (not (= 0 (mod v_~y$w_buff1_used~0_210 256))))) 1 0)) (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_98 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_94|) (= v_P0Thread1of1ForFork0_~arg.offset_94 |v_P0Thread1of1ForFork0_#in~arg.offset_96|) (= v_~y$w_buff0_used~0_350 v_~y$w_buff1_used~0_210) (= v_~y$w_buff0_used~0_349 1)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_96|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_350, ~y$w_buff0~0=v_~y$w_buff0~0_204, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_96|} OutVars{P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_96|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_349, ~y$w_buff1~0=v_~y$w_buff1~0_121, ~y$w_buff0~0=v_~y$w_buff0~0_203, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_98, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_96|, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_94, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_94|, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_94, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_210} AuxVars[] AssignedVars[~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P0Thread1of1ForFork0___VERIFIER_assert_~expression, P0Thread1of1ForFork0_~arg.base, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression, P0Thread1of1ForFork0_~arg.offset, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:27:58,475 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [642] [642] L756-2-->L756-4: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff1_thd2~0_In751410806 256))) (.cse1 (= (mod ~y$w_buff1_used~0_In751410806 256) 0))) (or (and (= ~y~0_In751410806 |P1Thread1of1ForFork1_#t~ite9_Out751410806|) (or .cse0 .cse1)) (and (= ~y$w_buff1~0_In751410806 |P1Thread1of1ForFork1_#t~ite9_Out751410806|) (not .cse0) (not .cse1)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In751410806, ~y$w_buff1~0=~y$w_buff1~0_In751410806, ~y~0=~y~0_In751410806, ~y$w_buff1_used~0=~y$w_buff1_used~0_In751410806} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In751410806, ~y$w_buff1~0=~y$w_buff1~0_In751410806, P1Thread1of1ForFork1_#t~ite9=|P1Thread1of1ForFork1_#t~ite9_Out751410806|, ~y~0=~y~0_In751410806, ~y$w_buff1_used~0=~y$w_buff1_used~0_In751410806} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9] because there is no mapped edge [2019-11-28 18:27:58,475 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [621] [621] L756-4-->L757: Formula: (= |v_P1Thread1of1ForFork1_#t~ite9_8| v_~y~0_41) InVars {P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_8|} OutVars{P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_7|, P1Thread1of1ForFork1_#t~ite10=|v_P1Thread1of1ForFork1_#t~ite10_13|, ~y~0=v_~y~0_41} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9, P1Thread1of1ForFork1_#t~ite10, ~y~0] because there is no mapped edge [2019-11-28 18:27:58,476 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [646] [646] L757-->L757-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In1111595850 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In1111595850 256)))) (or (and (= 0 |P1Thread1of1ForFork1_#t~ite11_Out1111595850|) (not .cse0) (not .cse1)) (and (= ~y$w_buff0_used~0_In1111595850 |P1Thread1of1ForFork1_#t~ite11_Out1111595850|) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1111595850, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1111595850} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1111595850, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1111595850, P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out1111595850|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-11-28 18:27:58,476 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [659] [659] L758-->L758-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff1_used~0_In-170886724 256))) (.cse1 (= (mod ~y$r_buff1_thd2~0_In-170886724 256) 0)) (.cse2 (= (mod ~y$r_buff0_thd2~0_In-170886724 256) 0)) (.cse3 (= (mod ~y$w_buff0_used~0_In-170886724 256) 0))) (or (and (= 0 |P1Thread1of1ForFork1_#t~ite12_Out-170886724|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~y$w_buff1_used~0_In-170886724 |P1Thread1of1ForFork1_#t~ite12_Out-170886724|) (or .cse0 .cse1) (or .cse2 .cse3)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-170886724, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-170886724, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-170886724, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-170886724} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-170886724, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-170886724, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-170886724, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out-170886724|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-170886724} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-11-28 18:27:58,476 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [645] [645] L759-->L759-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In-552784531 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In-552784531 256)))) (or (and (not .cse0) (= 0 |P1Thread1of1ForFork1_#t~ite13_Out-552784531|) (not .cse1)) (and (or .cse1 .cse0) (= ~y$r_buff0_thd2~0_In-552784531 |P1Thread1of1ForFork1_#t~ite13_Out-552784531|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-552784531, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-552784531} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-552784531, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-552784531, P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out-552784531|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13] because there is no mapped edge [2019-11-28 18:27:58,477 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [652] [652] L760-->L760-2: Formula: (let ((.cse2 (= 0 (mod ~y$w_buff1_used~0_In438094370 256))) (.cse3 (= 0 (mod ~y$r_buff1_thd2~0_In438094370 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In438094370 256))) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In438094370 256)))) (or (and (= |P1Thread1of1ForFork1_#t~ite14_Out438094370| ~y$r_buff1_thd2~0_In438094370) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1))) (= |P1Thread1of1ForFork1_#t~ite14_Out438094370| 0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In438094370, ~y$w_buff0_used~0=~y$w_buff0_used~0_In438094370, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In438094370, ~y$w_buff1_used~0=~y$w_buff1_used~0_In438094370} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In438094370, ~y$w_buff0_used~0=~y$w_buff0_used~0_In438094370, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In438094370, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out438094370|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In438094370} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-11-28 18:27:58,477 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L760-2-->P1EXIT: Formula: (and (= |v_P1Thread1of1ForFork1_#t~ite14_28| v_~y$r_buff1_thd2~0_91) (= (+ v_~__unbuffered_cnt~0_39 1) v_~__unbuffered_cnt~0_38) (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_39, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_28|} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_91, P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_38, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_27|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork1_#res.offset, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-11-28 18:27:58,477 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [655] [655] L737-->L737-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In1051564462 256) 0)) (.cse1 (= (mod ~y$r_buff0_thd1~0_In1051564462 256) 0))) (or (and (= 0 |P0Thread1of1ForFork0_#t~ite5_Out1051564462|) (not .cse0) (not .cse1)) (and (= |P0Thread1of1ForFork0_#t~ite5_Out1051564462| ~y$w_buff0_used~0_In1051564462) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1051564462, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In1051564462} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out1051564462|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1051564462, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In1051564462} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-11-28 18:27:58,478 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [641] [641] L738-->L738-2: Formula: (let ((.cse1 (= (mod ~y$w_buff1_used~0_In340754628 256) 0)) (.cse0 (= 0 (mod ~y$r_buff1_thd1~0_In340754628 256))) (.cse3 (= 0 (mod ~y$w_buff0_used~0_In340754628 256))) (.cse2 (= 0 (mod ~y$r_buff0_thd1~0_In340754628 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P0Thread1of1ForFork0_#t~ite6_Out340754628| ~y$w_buff1_used~0_In340754628)) (and (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2))) (= |P0Thread1of1ForFork0_#t~ite6_Out340754628| 0)))) InVars {~y$r_buff1_thd1~0=~y$r_buff1_thd1~0_In340754628, ~y$w_buff0_used~0=~y$w_buff0_used~0_In340754628, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In340754628, ~y$w_buff1_used~0=~y$w_buff1_used~0_In340754628} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out340754628|, ~y$r_buff1_thd1~0=~y$r_buff1_thd1~0_In340754628, ~y$w_buff0_used~0=~y$w_buff0_used~0_In340754628, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In340754628, ~y$w_buff1_used~0=~y$w_buff1_used~0_In340754628} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-11-28 18:27:58,478 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [643] [643] L739-->L740: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd1~0_In1095409174 256) 0)) (.cse0 (= ~y$r_buff0_thd1~0_Out1095409174 ~y$r_buff0_thd1~0_In1095409174)) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In1095409174 256)))) (or (and .cse0 .cse1) (and (not .cse1) (= ~y$r_buff0_thd1~0_Out1095409174 0) (not .cse2)) (and .cse0 .cse2))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1095409174, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In1095409174} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1095409174, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out1095409174|, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_Out1095409174} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7, ~y$r_buff0_thd1~0] because there is no mapped edge [2019-11-28 18:27:58,478 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [657] [657] L740-->L740-2: Formula: (let ((.cse2 (= 0 (mod ~y$w_buff0_used~0_In479357156 256))) (.cse3 (= 0 (mod ~y$r_buff0_thd1~0_In479357156 256))) (.cse0 (= 0 (mod ~y$w_buff1_used~0_In479357156 256))) (.cse1 (= 0 (mod ~y$r_buff1_thd1~0_In479357156 256)))) (or (and (= ~y$r_buff1_thd1~0_In479357156 |P0Thread1of1ForFork0_#t~ite8_Out479357156|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |P0Thread1of1ForFork0_#t~ite8_Out479357156| 0) (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1)))))) InVars {~y$r_buff1_thd1~0=~y$r_buff1_thd1~0_In479357156, ~y$w_buff0_used~0=~y$w_buff0_used~0_In479357156, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In479357156, ~y$w_buff1_used~0=~y$w_buff1_used~0_In479357156} OutVars{~y$r_buff1_thd1~0=~y$r_buff1_thd1~0_In479357156, ~y$w_buff0_used~0=~y$w_buff0_used~0_In479357156, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out479357156|, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In479357156, ~y$w_buff1_used~0=~y$w_buff1_used~0_In479357156} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-11-28 18:27:58,478 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [668] [668] L740-2-->P0EXIT: Formula: (and (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~y$r_buff1_thd1~0_80 |v_P0Thread1of1ForFork0_#t~ite8_28|) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|) (= v_~__unbuffered_cnt~0_31 (+ v_~__unbuffered_cnt~0_32 1))) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_28|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_32} OutVars{~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_80, P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_27|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_31} AuxVars[] AssignedVars[~y$r_buff1_thd1~0, P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-11-28 18:27:58,479 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [577] [577] L785-->L787-2: Formula: (and (not (= (mod v_~main$tmp_guard0~0_4 256) 0)) (or (= (mod v_~y$w_buff0_used~0_67 256) 0) (= 0 (mod v_~y$r_buff0_thd0~0_44 256)))) InVars {~y$w_buff0_used~0=v_~y$w_buff0_used~0_67, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_44, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_4} OutVars{~y$w_buff0_used~0=v_~y$w_buff0_used~0_67, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_44, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_4} AuxVars[] AssignedVars[] because there is no mapped edge [2019-11-28 18:27:58,479 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [656] [656] L787-2-->L787-5: Formula: (let ((.cse2 (= (mod ~y$r_buff1_thd0~0_In-1282646055 256) 0)) (.cse0 (= |ULTIMATE.start_main_#t~ite18_Out-1282646055| |ULTIMATE.start_main_#t~ite17_Out-1282646055|)) (.cse1 (= (mod ~y$w_buff1_used~0_In-1282646055 256) 0))) (or (and .cse0 (or .cse1 .cse2) (= |ULTIMATE.start_main_#t~ite17_Out-1282646055| ~y~0_In-1282646055)) (and (not .cse2) .cse0 (= |ULTIMATE.start_main_#t~ite17_Out-1282646055| ~y$w_buff1~0_In-1282646055) (not .cse1)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-1282646055, ~y~0=~y~0_In-1282646055, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1282646055, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1282646055} OutVars{ULTIMATE.start_main_#t~ite17=|ULTIMATE.start_main_#t~ite17_Out-1282646055|, ~y$w_buff1~0=~y$w_buff1~0_In-1282646055, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out-1282646055|, ~y~0=~y~0_In-1282646055, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1282646055, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1282646055} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite17, ULTIMATE.start_main_#t~ite18] because there is no mapped edge [2019-11-28 18:27:58,479 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [644] [644] L788-->L788-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In-1586782825 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In-1586782825 256)))) (or (and (or .cse0 .cse1) (= ~y$w_buff0_used~0_In-1586782825 |ULTIMATE.start_main_#t~ite19_Out-1586782825|)) (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite19_Out-1586782825|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1586782825, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1586782825} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1586782825, ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out-1586782825|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1586782825} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-11-28 18:27:58,480 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [648] [648] L789-->L789-2: Formula: (let ((.cse2 (= (mod ~y$w_buff0_used~0_In-1575932751 256) 0)) (.cse3 (= (mod ~y$r_buff0_thd0~0_In-1575932751 256) 0)) (.cse0 (= 0 (mod ~y$w_buff1_used~0_In-1575932751 256))) (.cse1 (= 0 (mod ~y$r_buff1_thd0~0_In-1575932751 256)))) (or (and (= 0 |ULTIMATE.start_main_#t~ite20_Out-1575932751|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~y$w_buff1_used~0_In-1575932751 |ULTIMATE.start_main_#t~ite20_Out-1575932751|) (or .cse2 .cse3) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1575932751, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1575932751, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1575932751, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1575932751} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1575932751, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1575932751, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out-1575932751|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1575932751, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1575932751} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-11-28 18:27:58,480 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [639] [639] L790-->L790-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In-784309596 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In-784309596 256)))) (or (and (= |ULTIMATE.start_main_#t~ite21_Out-784309596| ~y$r_buff0_thd0~0_In-784309596) (or .cse0 .cse1)) (and (not .cse0) (= |ULTIMATE.start_main_#t~ite21_Out-784309596| 0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-784309596, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-784309596} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-784309596, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-784309596, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out-784309596|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-11-28 18:27:58,481 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [651] [651] L791-->L791-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In420519582 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In420519582 256))) (.cse2 (= (mod ~y$r_buff1_thd0~0_In420519582 256) 0)) (.cse3 (= (mod ~y$w_buff1_used~0_In420519582 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite22_Out420519582|)) (and (or .cse0 .cse1) (or .cse2 .cse3) (= |ULTIMATE.start_main_#t~ite22_Out420519582| ~y$r_buff1_thd0~0_In420519582)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In420519582, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In420519582, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In420519582, ~y$w_buff1_used~0=~y$w_buff1_used~0_In420519582} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In420519582, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In420519582, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In420519582, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out420519582|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In420519582} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-11-28 18:27:58,482 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [689] [689] L800-->L800-8: Formula: (let ((.cse1 (= (mod ~weak$$choice2~0_In-631527573 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite32_Out-631527573| |ULTIMATE.start_main_#t~ite31_Out-631527573|) (let ((.cse0 (= (mod ~y$r_buff0_thd0~0_In-631527573 256) 0))) (or (and .cse0 (= (mod ~y$w_buff1_used~0_In-631527573 256) 0)) (and .cse0 (= (mod ~y$r_buff1_thd0~0_In-631527573 256) 0)) (= (mod ~y$w_buff0_used~0_In-631527573 256) 0))) (= ~y$w_buff1~0_In-631527573 |ULTIMATE.start_main_#t~ite31_Out-631527573|) .cse1) (and (= |ULTIMATE.start_main_#t~ite32_Out-631527573| ~y$w_buff1~0_In-631527573) (not .cse1) (= |ULTIMATE.start_main_#t~ite31_In-631527573| |ULTIMATE.start_main_#t~ite31_Out-631527573|)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-631527573, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-631527573, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-631527573, ~weak$$choice2~0=~weak$$choice2~0_In-631527573, ULTIMATE.start_main_#t~ite31=|ULTIMATE.start_main_#t~ite31_In-631527573|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-631527573, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-631527573} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-631527573, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-631527573, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-631527573, ULTIMATE.start_main_#t~ite31=|ULTIMATE.start_main_#t~ite31_Out-631527573|, ~weak$$choice2~0=~weak$$choice2~0_In-631527573, ULTIMATE.start_main_#t~ite32=|ULTIMATE.start_main_#t~ite32_Out-631527573|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-631527573, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-631527573} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite32] because there is no mapped edge [2019-11-28 18:27:58,484 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [637] [637] L803-->L804: Formula: (and (= v_~y$r_buff0_thd0~0_162 v_~y$r_buff0_thd0~0_163) (not (= (mod v_~weak$$choice2~0_39 256) 0))) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_163, ~weak$$choice2~0=v_~weak$$choice2~0_39} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_9|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_11|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_18|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_162, ~weak$$choice2~0=v_~weak$$choice2~0_39} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~ite39, ~y$r_buff0_thd0~0] because there is no mapped edge [2019-11-28 18:27:58,485 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [686] [686] L806-->L809-1: Formula: (and (= 0 v_~y$flush_delayed~0_24) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6| (mod v_~main$tmp_guard1~0_12 256)) (not (= 0 (mod v_~y$flush_delayed~0_25 256))) (= v_~y~0_106 v_~y$mem_tmp~0_13)) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_13, ~y$flush_delayed~0=v_~y$flush_delayed~0_25, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_13, ~y$flush_delayed~0=v_~y$flush_delayed~0_24, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12, ~y~0=v_~y~0_106, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_22|, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[~y$flush_delayed~0, ~y~0, ULTIMATE.start_main_#t~ite45, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-11-28 18:27:58,485 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [680] [680] L809-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-11-28 18:27:58,599 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 06:27:58 BasicIcfg [2019-11-28 18:27:58,599 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-28 18:27:58,599 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-28 18:27:58,599 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-28 18:27:58,600 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-28 18:27:58,600 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:27:38" (3/4) ... [2019-11-28 18:27:58,604 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-28 18:27:58,604 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [702] [702] ULTIMATE.startENTRY-->L779: Formula: (let ((.cse0 (store |v_#valid_47| 0 0))) (and (= 0 v_~y$read_delayed_var~0.base_6) (= v_~y$r_buff1_thd0~0_329 0) (= v_~y$w_buff0_used~0_834 0) (= 0 |v_ULTIMATE.start_main_~#t2017~0.offset_19|) (= 0 v_~__unbuffered_cnt~0_61) (= |v_#valid_45| (store .cse0 |v_ULTIMATE.start_main_~#t2017~0.base_24| 1)) (= 0 v_~weak$$choice0~0_14) (= v_~y$r_buff1_thd1~0_200 0) (= 0 v_~x~0_147) (= |v_#NULL.offset_3| 0) (= v_~main$tmp_guard1~0_27 0) (= v_~y$read_delayed~0_6 0) (= 0 v_~__unbuffered_p1_EAX~0_29) (< |v_#StackHeapBarrier_13| |v_ULTIMATE.start_main_~#t2017~0.base_24|) (= 0 v_~y$r_buff1_thd2~0_208) (= 0 v_~y$r_buff0_thd2~0_162) (= v_~y$mem_tmp~0_19 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t2017~0.base_24|)) (= v_~weak$$choice2~0_141 0) (= v_~y$w_buff1_used~0_547 0) (= (store |v_#length_14| |v_ULTIMATE.start_main_~#t2017~0.base_24| 4) |v_#length_13|) (= v_~y$r_buff0_thd1~0_297 0) (= 0 v_~y$flush_delayed~0_36) (= v_~main$tmp_guard0~0_33 0) (= 0 |v_#NULL.base_3|) (= 0 v_~y$w_buff0~0_485) (= 0 v_~y$read_delayed_var~0.offset_6) (= v_~y$r_buff0_thd0~0_416 0) (= v_~y~0_146 0) (< 0 |v_#StackHeapBarrier_13|) (= (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t2017~0.base_24| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t2017~0.base_24|) |v_ULTIMATE.start_main_~#t2017~0.offset_19| 0)) |v_#memory_int_11|) (= v_~y$w_buff1~0_308 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_47|, #memory_int=|v_#memory_int_12|, #length=|v_#length_14|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_41|, #NULL.offset=|v_#NULL.offset_3|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_35|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_145|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_48|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_37|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_36|, ~y$read_delayed~0=v_~y$read_delayed~0_6, ~y$mem_tmp~0=v_~y$mem_tmp~0_19, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_29, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_297, ~y$flush_delayed~0=v_~y$flush_delayed~0_36, ULTIMATE.start_main_~#t2017~0.base=|v_ULTIMATE.start_main_~#t2017~0.base_24|, #length=|v_#length_13|, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_36|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_38|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_21|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_27|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_41|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_44|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_38|, ~weak$$choice0~0=v_~weak$$choice0~0_14, #StackHeapBarrier=|v_#StackHeapBarrier_13|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_36|, ~y$w_buff1~0=v_~y$w_buff1~0_308, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_6, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_162, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_10|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_61, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_329, ~x~0=v_~x~0_147, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_6, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_834, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_36|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_33|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_27, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_43|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_33|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_42|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_34|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_200, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_34|, ~y$w_buff0~0=v_~y$w_buff0~0_485, ~y~0=v_~y~0_146, ULTIMATE.start_main_#t~ite17=|v_ULTIMATE.start_main_#t~ite17_29|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_21|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_33|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_53|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_27|, ULTIMATE.start_main_~#t2018~0.offset=|v_ULTIMATE.start_main_~#t2018~0.offset_16|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_33, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_35|, #NULL.base=|v_#NULL.base_3|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_40|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_208, ULTIMATE.start_main_~#t2018~0.base=|v_ULTIMATE.start_main_~#t2018~0.base_19|, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_37|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_18|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_416, #valid=|v_#valid_45|, #memory_int=|v_#memory_int_11|, ULTIMATE.start_main_~#t2017~0.offset=|v_ULTIMATE.start_main_~#t2017~0.offset_19|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_14|, ~weak$$choice2~0=v_~weak$$choice2~0_141, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_547} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~y$read_delayed~0, ~y$mem_tmp~0, ~__unbuffered_p1_EAX~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, ULTIMATE.start_main_~#t2017~0.base, #length, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ~y$w_buff0~0, ~y~0, ULTIMATE.start_main_#t~ite17, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ULTIMATE.start_main_~#t2018~0.offset, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_~#t2018~0.base, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_~#t2017~0.offset, ULTIMATE.start_main_#t~nondet16, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:27:58,605 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [675] [675] L779-1-->L781: Formula: (and (not (= 0 |v_ULTIMATE.start_main_~#t2018~0.base_11|)) (< |v_#StackHeapBarrier_8| |v_ULTIMATE.start_main_~#t2018~0.base_11|) (= 0 (select |v_#valid_28| |v_ULTIMATE.start_main_~#t2018~0.base_11|)) (= |v_#memory_int_7| (store |v_#memory_int_8| |v_ULTIMATE.start_main_~#t2018~0.base_11| (store (select |v_#memory_int_8| |v_ULTIMATE.start_main_~#t2018~0.base_11|) |v_ULTIMATE.start_main_~#t2018~0.offset_10| 1))) (= |v_#length_9| (store |v_#length_10| |v_ULTIMATE.start_main_~#t2018~0.base_11| 4)) (= (store |v_#valid_28| |v_ULTIMATE.start_main_~#t2018~0.base_11| 1) |v_#valid_27|) (= 0 |v_ULTIMATE.start_main_~#t2018~0.offset_10|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_8|, #valid=|v_#valid_28|, #memory_int=|v_#memory_int_8|, #length=|v_#length_10|} OutVars{ULTIMATE.start_main_~#t2018~0.base=|v_ULTIMATE.start_main_~#t2018~0.base_11|, #StackHeapBarrier=|v_#StackHeapBarrier_8|, #valid=|v_#valid_27|, #memory_int=|v_#memory_int_7|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_6|, ULTIMATE.start_main_~#t2018~0.offset=|v_ULTIMATE.start_main_~#t2018~0.offset_10|, #length=|v_#length_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2018~0.base, #valid, #memory_int, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_~#t2018~0.offset, #length] because there is no mapped edge [2019-11-28 18:27:58,605 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [638] [638] P0ENTRY-->L4-3: Formula: (and (= v_~y$w_buff1~0_121 v_~y$w_buff0~0_204) (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_98 0)) (= v_P0Thread1of1ForFork0_~arg.base_94 |v_P0Thread1of1ForFork0_#in~arg.base_96|) (= 2 v_~y$w_buff0~0_203) (= |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_94| (ite (not (and (not (= 0 (mod v_~y$w_buff0_used~0_349 256))) (not (= 0 (mod v_~y$w_buff1_used~0_210 256))))) 1 0)) (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_98 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_94|) (= v_P0Thread1of1ForFork0_~arg.offset_94 |v_P0Thread1of1ForFork0_#in~arg.offset_96|) (= v_~y$w_buff0_used~0_350 v_~y$w_buff1_used~0_210) (= v_~y$w_buff0_used~0_349 1)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_96|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_350, ~y$w_buff0~0=v_~y$w_buff0~0_204, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_96|} OutVars{P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_96|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_349, ~y$w_buff1~0=v_~y$w_buff1~0_121, ~y$w_buff0~0=v_~y$w_buff0~0_203, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_98, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_96|, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_94, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_94|, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_94, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_210} AuxVars[] AssignedVars[~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P0Thread1of1ForFork0___VERIFIER_assert_~expression, P0Thread1of1ForFork0_~arg.base, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression, P0Thread1of1ForFork0_~arg.offset, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:27:58,606 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [642] [642] L756-2-->L756-4: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff1_thd2~0_In751410806 256))) (.cse1 (= (mod ~y$w_buff1_used~0_In751410806 256) 0))) (or (and (= ~y~0_In751410806 |P1Thread1of1ForFork1_#t~ite9_Out751410806|) (or .cse0 .cse1)) (and (= ~y$w_buff1~0_In751410806 |P1Thread1of1ForFork1_#t~ite9_Out751410806|) (not .cse0) (not .cse1)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In751410806, ~y$w_buff1~0=~y$w_buff1~0_In751410806, ~y~0=~y~0_In751410806, ~y$w_buff1_used~0=~y$w_buff1_used~0_In751410806} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In751410806, ~y$w_buff1~0=~y$w_buff1~0_In751410806, P1Thread1of1ForFork1_#t~ite9=|P1Thread1of1ForFork1_#t~ite9_Out751410806|, ~y~0=~y~0_In751410806, ~y$w_buff1_used~0=~y$w_buff1_used~0_In751410806} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9] because there is no mapped edge [2019-11-28 18:27:58,607 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [621] [621] L756-4-->L757: Formula: (= |v_P1Thread1of1ForFork1_#t~ite9_8| v_~y~0_41) InVars {P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_8|} OutVars{P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_7|, P1Thread1of1ForFork1_#t~ite10=|v_P1Thread1of1ForFork1_#t~ite10_13|, ~y~0=v_~y~0_41} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9, P1Thread1of1ForFork1_#t~ite10, ~y~0] because there is no mapped edge [2019-11-28 18:27:58,607 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [646] [646] L757-->L757-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In1111595850 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In1111595850 256)))) (or (and (= 0 |P1Thread1of1ForFork1_#t~ite11_Out1111595850|) (not .cse0) (not .cse1)) (and (= ~y$w_buff0_used~0_In1111595850 |P1Thread1of1ForFork1_#t~ite11_Out1111595850|) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1111595850, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1111595850} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1111595850, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1111595850, P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out1111595850|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-11-28 18:27:58,607 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [659] [659] L758-->L758-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff1_used~0_In-170886724 256))) (.cse1 (= (mod ~y$r_buff1_thd2~0_In-170886724 256) 0)) (.cse2 (= (mod ~y$r_buff0_thd2~0_In-170886724 256) 0)) (.cse3 (= (mod ~y$w_buff0_used~0_In-170886724 256) 0))) (or (and (= 0 |P1Thread1of1ForFork1_#t~ite12_Out-170886724|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~y$w_buff1_used~0_In-170886724 |P1Thread1of1ForFork1_#t~ite12_Out-170886724|) (or .cse0 .cse1) (or .cse2 .cse3)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-170886724, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-170886724, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-170886724, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-170886724} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-170886724, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-170886724, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-170886724, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out-170886724|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-170886724} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-11-28 18:27:58,608 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [645] [645] L759-->L759-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In-552784531 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In-552784531 256)))) (or (and (not .cse0) (= 0 |P1Thread1of1ForFork1_#t~ite13_Out-552784531|) (not .cse1)) (and (or .cse1 .cse0) (= ~y$r_buff0_thd2~0_In-552784531 |P1Thread1of1ForFork1_#t~ite13_Out-552784531|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-552784531, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-552784531} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-552784531, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-552784531, P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out-552784531|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13] because there is no mapped edge [2019-11-28 18:27:58,609 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [652] [652] L760-->L760-2: Formula: (let ((.cse2 (= 0 (mod ~y$w_buff1_used~0_In438094370 256))) (.cse3 (= 0 (mod ~y$r_buff1_thd2~0_In438094370 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In438094370 256))) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In438094370 256)))) (or (and (= |P1Thread1of1ForFork1_#t~ite14_Out438094370| ~y$r_buff1_thd2~0_In438094370) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1))) (= |P1Thread1of1ForFork1_#t~ite14_Out438094370| 0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In438094370, ~y$w_buff0_used~0=~y$w_buff0_used~0_In438094370, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In438094370, ~y$w_buff1_used~0=~y$w_buff1_used~0_In438094370} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In438094370, ~y$w_buff0_used~0=~y$w_buff0_used~0_In438094370, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In438094370, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out438094370|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In438094370} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-11-28 18:27:58,609 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L760-2-->P1EXIT: Formula: (and (= |v_P1Thread1of1ForFork1_#t~ite14_28| v_~y$r_buff1_thd2~0_91) (= (+ v_~__unbuffered_cnt~0_39 1) v_~__unbuffered_cnt~0_38) (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_39, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_28|} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_91, P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_38, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_27|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork1_#res.offset, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-11-28 18:27:58,609 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [655] [655] L737-->L737-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In1051564462 256) 0)) (.cse1 (= (mod ~y$r_buff0_thd1~0_In1051564462 256) 0))) (or (and (= 0 |P0Thread1of1ForFork0_#t~ite5_Out1051564462|) (not .cse0) (not .cse1)) (and (= |P0Thread1of1ForFork0_#t~ite5_Out1051564462| ~y$w_buff0_used~0_In1051564462) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1051564462, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In1051564462} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out1051564462|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1051564462, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In1051564462} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-11-28 18:27:58,609 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [641] [641] L738-->L738-2: Formula: (let ((.cse1 (= (mod ~y$w_buff1_used~0_In340754628 256) 0)) (.cse0 (= 0 (mod ~y$r_buff1_thd1~0_In340754628 256))) (.cse3 (= 0 (mod ~y$w_buff0_used~0_In340754628 256))) (.cse2 (= 0 (mod ~y$r_buff0_thd1~0_In340754628 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P0Thread1of1ForFork0_#t~ite6_Out340754628| ~y$w_buff1_used~0_In340754628)) (and (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2))) (= |P0Thread1of1ForFork0_#t~ite6_Out340754628| 0)))) InVars {~y$r_buff1_thd1~0=~y$r_buff1_thd1~0_In340754628, ~y$w_buff0_used~0=~y$w_buff0_used~0_In340754628, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In340754628, ~y$w_buff1_used~0=~y$w_buff1_used~0_In340754628} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out340754628|, ~y$r_buff1_thd1~0=~y$r_buff1_thd1~0_In340754628, ~y$w_buff0_used~0=~y$w_buff0_used~0_In340754628, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In340754628, ~y$w_buff1_used~0=~y$w_buff1_used~0_In340754628} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-11-28 18:27:58,610 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [643] [643] L739-->L740: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd1~0_In1095409174 256) 0)) (.cse0 (= ~y$r_buff0_thd1~0_Out1095409174 ~y$r_buff0_thd1~0_In1095409174)) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In1095409174 256)))) (or (and .cse0 .cse1) (and (not .cse1) (= ~y$r_buff0_thd1~0_Out1095409174 0) (not .cse2)) (and .cse0 .cse2))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1095409174, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In1095409174} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1095409174, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out1095409174|, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_Out1095409174} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7, ~y$r_buff0_thd1~0] because there is no mapped edge [2019-11-28 18:27:58,610 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [657] [657] L740-->L740-2: Formula: (let ((.cse2 (= 0 (mod ~y$w_buff0_used~0_In479357156 256))) (.cse3 (= 0 (mod ~y$r_buff0_thd1~0_In479357156 256))) (.cse0 (= 0 (mod ~y$w_buff1_used~0_In479357156 256))) (.cse1 (= 0 (mod ~y$r_buff1_thd1~0_In479357156 256)))) (or (and (= ~y$r_buff1_thd1~0_In479357156 |P0Thread1of1ForFork0_#t~ite8_Out479357156|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |P0Thread1of1ForFork0_#t~ite8_Out479357156| 0) (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1)))))) InVars {~y$r_buff1_thd1~0=~y$r_buff1_thd1~0_In479357156, ~y$w_buff0_used~0=~y$w_buff0_used~0_In479357156, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In479357156, ~y$w_buff1_used~0=~y$w_buff1_used~0_In479357156} OutVars{~y$r_buff1_thd1~0=~y$r_buff1_thd1~0_In479357156, ~y$w_buff0_used~0=~y$w_buff0_used~0_In479357156, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out479357156|, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In479357156, ~y$w_buff1_used~0=~y$w_buff1_used~0_In479357156} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-11-28 18:27:58,610 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [668] [668] L740-2-->P0EXIT: Formula: (and (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~y$r_buff1_thd1~0_80 |v_P0Thread1of1ForFork0_#t~ite8_28|) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|) (= v_~__unbuffered_cnt~0_31 (+ v_~__unbuffered_cnt~0_32 1))) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_28|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_32} OutVars{~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_80, P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_27|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_31} AuxVars[] AssignedVars[~y$r_buff1_thd1~0, P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-11-28 18:27:58,610 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [577] [577] L785-->L787-2: Formula: (and (not (= (mod v_~main$tmp_guard0~0_4 256) 0)) (or (= (mod v_~y$w_buff0_used~0_67 256) 0) (= 0 (mod v_~y$r_buff0_thd0~0_44 256)))) InVars {~y$w_buff0_used~0=v_~y$w_buff0_used~0_67, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_44, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_4} OutVars{~y$w_buff0_used~0=v_~y$w_buff0_used~0_67, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_44, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_4} AuxVars[] AssignedVars[] because there is no mapped edge [2019-11-28 18:27:58,610 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [656] [656] L787-2-->L787-5: Formula: (let ((.cse2 (= (mod ~y$r_buff1_thd0~0_In-1282646055 256) 0)) (.cse0 (= |ULTIMATE.start_main_#t~ite18_Out-1282646055| |ULTIMATE.start_main_#t~ite17_Out-1282646055|)) (.cse1 (= (mod ~y$w_buff1_used~0_In-1282646055 256) 0))) (or (and .cse0 (or .cse1 .cse2) (= |ULTIMATE.start_main_#t~ite17_Out-1282646055| ~y~0_In-1282646055)) (and (not .cse2) .cse0 (= |ULTIMATE.start_main_#t~ite17_Out-1282646055| ~y$w_buff1~0_In-1282646055) (not .cse1)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-1282646055, ~y~0=~y~0_In-1282646055, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1282646055, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1282646055} OutVars{ULTIMATE.start_main_#t~ite17=|ULTIMATE.start_main_#t~ite17_Out-1282646055|, ~y$w_buff1~0=~y$w_buff1~0_In-1282646055, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out-1282646055|, ~y~0=~y~0_In-1282646055, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1282646055, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1282646055} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite17, ULTIMATE.start_main_#t~ite18] because there is no mapped edge [2019-11-28 18:27:58,611 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [644] [644] L788-->L788-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In-1586782825 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In-1586782825 256)))) (or (and (or .cse0 .cse1) (= ~y$w_buff0_used~0_In-1586782825 |ULTIMATE.start_main_#t~ite19_Out-1586782825|)) (and (not .cse0) (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite19_Out-1586782825|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1586782825, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1586782825} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1586782825, ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out-1586782825|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1586782825} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-11-28 18:27:58,611 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [648] [648] L789-->L789-2: Formula: (let ((.cse2 (= (mod ~y$w_buff0_used~0_In-1575932751 256) 0)) (.cse3 (= (mod ~y$r_buff0_thd0~0_In-1575932751 256) 0)) (.cse0 (= 0 (mod ~y$w_buff1_used~0_In-1575932751 256))) (.cse1 (= 0 (mod ~y$r_buff1_thd0~0_In-1575932751 256)))) (or (and (= 0 |ULTIMATE.start_main_#t~ite20_Out-1575932751|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~y$w_buff1_used~0_In-1575932751 |ULTIMATE.start_main_#t~ite20_Out-1575932751|) (or .cse2 .cse3) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1575932751, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1575932751, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1575932751, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1575932751} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1575932751, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1575932751, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out-1575932751|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1575932751, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1575932751} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-11-28 18:27:58,612 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [639] [639] L790-->L790-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In-784309596 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In-784309596 256)))) (or (and (= |ULTIMATE.start_main_#t~ite21_Out-784309596| ~y$r_buff0_thd0~0_In-784309596) (or .cse0 .cse1)) (and (not .cse0) (= |ULTIMATE.start_main_#t~ite21_Out-784309596| 0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-784309596, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-784309596} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-784309596, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-784309596, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out-784309596|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-11-28 18:27:58,612 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [651] [651] L791-->L791-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In420519582 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In420519582 256))) (.cse2 (= (mod ~y$r_buff1_thd0~0_In420519582 256) 0)) (.cse3 (= (mod ~y$w_buff1_used~0_In420519582 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite22_Out420519582|)) (and (or .cse0 .cse1) (or .cse2 .cse3) (= |ULTIMATE.start_main_#t~ite22_Out420519582| ~y$r_buff1_thd0~0_In420519582)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In420519582, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In420519582, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In420519582, ~y$w_buff1_used~0=~y$w_buff1_used~0_In420519582} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In420519582, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In420519582, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In420519582, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out420519582|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In420519582} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-11-28 18:27:58,613 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [689] [689] L800-->L800-8: Formula: (let ((.cse1 (= (mod ~weak$$choice2~0_In-631527573 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite32_Out-631527573| |ULTIMATE.start_main_#t~ite31_Out-631527573|) (let ((.cse0 (= (mod ~y$r_buff0_thd0~0_In-631527573 256) 0))) (or (and .cse0 (= (mod ~y$w_buff1_used~0_In-631527573 256) 0)) (and .cse0 (= (mod ~y$r_buff1_thd0~0_In-631527573 256) 0)) (= (mod ~y$w_buff0_used~0_In-631527573 256) 0))) (= ~y$w_buff1~0_In-631527573 |ULTIMATE.start_main_#t~ite31_Out-631527573|) .cse1) (and (= |ULTIMATE.start_main_#t~ite32_Out-631527573| ~y$w_buff1~0_In-631527573) (not .cse1) (= |ULTIMATE.start_main_#t~ite31_In-631527573| |ULTIMATE.start_main_#t~ite31_Out-631527573|)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-631527573, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-631527573, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-631527573, ~weak$$choice2~0=~weak$$choice2~0_In-631527573, ULTIMATE.start_main_#t~ite31=|ULTIMATE.start_main_#t~ite31_In-631527573|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-631527573, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-631527573} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-631527573, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-631527573, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-631527573, ULTIMATE.start_main_#t~ite31=|ULTIMATE.start_main_#t~ite31_Out-631527573|, ~weak$$choice2~0=~weak$$choice2~0_In-631527573, ULTIMATE.start_main_#t~ite32=|ULTIMATE.start_main_#t~ite32_Out-631527573|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-631527573, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-631527573} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite32] because there is no mapped edge [2019-11-28 18:27:58,615 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [637] [637] L803-->L804: Formula: (and (= v_~y$r_buff0_thd0~0_162 v_~y$r_buff0_thd0~0_163) (not (= (mod v_~weak$$choice2~0_39 256) 0))) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_163, ~weak$$choice2~0=v_~weak$$choice2~0_39} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_9|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_11|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_18|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_162, ~weak$$choice2~0=v_~weak$$choice2~0_39} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~ite39, ~y$r_buff0_thd0~0] because there is no mapped edge [2019-11-28 18:27:58,616 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [686] [686] L806-->L809-1: Formula: (and (= 0 v_~y$flush_delayed~0_24) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6| (mod v_~main$tmp_guard1~0_12 256)) (not (= 0 (mod v_~y$flush_delayed~0_25 256))) (= v_~y~0_106 v_~y$mem_tmp~0_13)) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_13, ~y$flush_delayed~0=v_~y$flush_delayed~0_25, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_13, ~y$flush_delayed~0=v_~y$flush_delayed~0_24, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12, ~y~0=v_~y~0_106, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_22|, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[~y$flush_delayed~0, ~y~0, ULTIMATE.start_main_#t~ite45, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-11-28 18:27:58,616 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [680] [680] L809-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-11-28 18:27:58,732 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2019-11-28 18:27:58,732 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-28 18:27:58,735 INFO L168 Benchmark]: Toolchain (without parser) took 21383.93 ms. Allocated memory was 1.0 GB in the beginning and 1.9 GB in the end (delta: 859.3 MB). Free memory was 952.3 MB in the beginning and 1.6 GB in the end (delta: -622.4 MB). Peak memory consumption was 237.0 MB. Max. memory is 11.5 GB. [2019-11-28 18:27:58,735 INFO L168 Benchmark]: CDTParser took 0.90 ms. Allocated memory is still 1.0 GB. Free memory is still 987.2 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 18:27:58,736 INFO L168 Benchmark]: CACSL2BoogieTranslator took 673.63 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 150.5 MB). Free memory was 952.3 MB in the beginning and 1.1 GB in the end (delta: -160.2 MB). Peak memory consumption was 20.6 MB. Max. memory is 11.5 GB. [2019-11-28 18:27:58,736 INFO L168 Benchmark]: Boogie Procedure Inliner took 67.02 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.6 MB). Peak memory consumption was 6.6 MB. Max. memory is 11.5 GB. [2019-11-28 18:27:58,736 INFO L168 Benchmark]: Boogie Preprocessor took 38.63 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 18:27:58,737 INFO L168 Benchmark]: RCFGBuilder took 769.37 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 43.8 MB). Peak memory consumption was 43.8 MB. Max. memory is 11.5 GB. [2019-11-28 18:27:58,737 INFO L168 Benchmark]: TraceAbstraction took 19697.50 ms. Allocated memory was 1.2 GB in the beginning and 1.9 GB in the end (delta: 708.8 MB). Free memory was 1.1 GB in the beginning and 1.6 GB in the end (delta: -538.0 MB). Peak memory consumption was 170.9 MB. Max. memory is 11.5 GB. [2019-11-28 18:27:58,738 INFO L168 Benchmark]: Witness Printer took 132.56 ms. Allocated memory is still 1.9 GB. Free memory was 1.6 GB in the beginning and 1.6 GB in the end (delta: 19.0 MB). Peak memory consumption was 19.0 MB. Max. memory is 11.5 GB. [2019-11-28 18:27:58,741 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.90 ms. Allocated memory is still 1.0 GB. Free memory is still 987.2 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 673.63 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 150.5 MB). Free memory was 952.3 MB in the beginning and 1.1 GB in the end (delta: -160.2 MB). Peak memory consumption was 20.6 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 67.02 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.6 MB). Peak memory consumption was 6.6 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 38.63 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 769.37 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 43.8 MB). Peak memory consumption was 43.8 MB. Max. memory is 11.5 GB. * TraceAbstraction took 19697.50 ms. Allocated memory was 1.2 GB in the beginning and 1.9 GB in the end (delta: 708.8 MB). Free memory was 1.1 GB in the beginning and 1.6 GB in the end (delta: -538.0 MB). Peak memory consumption was 170.9 MB. Max. memory is 11.5 GB. * Witness Printer took 132.56 ms. Allocated memory is still 1.9 GB. Free memory was 1.6 GB in the beginning and 1.6 GB in the end (delta: 19.0 MB). Peak memory consumption was 19.0 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 5.2s, 146 ProgramPointsBefore, 79 ProgramPointsAfterwards, 180 TransitionsBefore, 91 TransitionsAfterwards, 10418 CoEnabledTransitionPairs, 7 FixpointIterations, 28 TrivialSequentialCompositions, 39 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 34 ConcurrentYvCompositions, 25 ChoiceCompositions, 3678 VarBasedMoverChecksPositive, 231 VarBasedMoverChecksNegative, 69 SemBasedMoverChecksPositive, 221 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 1.6s, 0 MoverChecksTotal, 46090 CheckedPairsTotal, 101 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L779] FCALL, FORK 0 pthread_create(&t2017, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0] [L781] FCALL, FORK 0 pthread_create(&t2018, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0] [L727] 1 y$r_buff1_thd0 = y$r_buff0_thd0 [L728] 1 y$r_buff1_thd1 = y$r_buff0_thd1 [L729] 1 y$r_buff1_thd2 = y$r_buff0_thd2 [L730] 1 y$r_buff0_thd1 = (_Bool)1 [L733] 1 x = 1 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0] [L736] EXPR 1 y$w_buff0_used && y$r_buff0_thd1 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd1 ? y$w_buff1 : y) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0] [L750] 2 __unbuffered_p1_EAX = x [L753] 2 y = 1 VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0] [L736] 1 y = y$w_buff0_used && y$r_buff0_thd1 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd1 ? y$w_buff1 : y) [L756] 2 y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=1, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0] [L757] 2 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$w_buff0_used [L758] 2 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used [L759] 2 y$r_buff0_thd2 = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$r_buff0_thd2 [L737] 1 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd1 ? (_Bool)0 : y$w_buff0_used [L738] 1 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd1 || y$w_buff1_used && y$r_buff1_thd1 ? (_Bool)0 : y$w_buff1_used [L783] 0 main$tmp_guard0 = __unbuffered_cnt == 2 VAL [\result={0:0}, __unbuffered_cnt=2, __unbuffered_p1_EAX=1, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0] [L787] 0 y = y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) [L788] 0 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used [L789] 0 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$w_buff1_used [L790] 0 y$r_buff0_thd0 = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$r_buff0_thd0 [L791] 0 y$r_buff1_thd0 = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$r_buff1_thd0 [L794] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L795] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L796] 0 y$flush_delayed = weak$$choice2 [L797] 0 y$mem_tmp = y VAL [\result={0:0}, __unbuffered_cnt=2, __unbuffered_p1_EAX=1, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=6, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0] [L798] EXPR 0 !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) VAL [\result={0:0}, __unbuffered_cnt=2, __unbuffered_p1_EAX=1, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=6, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0] [L798] 0 y = !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) [L799] EXPR 0 weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) VAL [\result={0:0}, __unbuffered_cnt=2, __unbuffered_p1_EAX=1, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=6, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0] [L799] 0 y$w_buff0 = weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) [L800] 0 y$w_buff1 = weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) [L801] EXPR 0 weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) VAL [\result={0:0}, __unbuffered_cnt=2, __unbuffered_p1_EAX=1, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=6, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0] [L801] 0 y$w_buff0_used = weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) [L802] EXPR 0 weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, __unbuffered_cnt=2, __unbuffered_p1_EAX=1, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=6, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0] [L802] 0 y$w_buff1_used = weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L804] EXPR 0 weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, __unbuffered_cnt=2, __unbuffered_p1_EAX=1, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=6, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0] [L804] 0 y$r_buff1_thd0 = weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L805] 0 main$tmp_guard1 = !(y == 2 && __unbuffered_p1_EAX == 1) VAL [\result={0:0}, __unbuffered_cnt=2, __unbuffered_p1_EAX=1, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=6, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 3 procedures, 140 locations, 2 error locations. Result: UNSAFE, OverallTime: 19.4s, OverallIterations: 18, TraceHistogramMax: 1, AutomataDifference: 6.6s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 1796 SDtfs, 2158 SDslu, 5274 SDs, 0 SdLazy, 3821 SolverSat, 246 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 3.6s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 203 GetRequests, 22 SyntacticMatches, 18 SemanticMatches, 163 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 626 ImplicationChecksByTransitivity, 2.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=14186occurred in iteration=5, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 2.8s AutomataMinimizationTime, 17 MinimizatonAttempts, 10148 StatesRemovedByMinimization, 14 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 0.5s SatisfiabilityAnalysisTime, 2.5s InterpolantComputationTime, 714 NumberOfCodeBlocks, 714 NumberOfCodeBlocksAsserted, 18 NumberOfCheckSat, 643 ConstructedInterpolants, 0 QuantifiedInterpolants, 150193 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 17 InterpolantComputations, 17 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...