./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/pthread-wmm/safe029_rmo.oepc.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx12G -Xms1G -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/pthread-wmm/safe029_rmo.oepc.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash eff86fe4110cf0b56af359bea2f58358a83b929a ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-11-28 18:32:33,051 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-28 18:32:33,053 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-28 18:32:33,069 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-28 18:32:33,069 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-28 18:32:33,071 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-28 18:32:33,072 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-28 18:32:33,074 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-28 18:32:33,076 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-28 18:32:33,077 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-28 18:32:33,078 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-28 18:32:33,080 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-28 18:32:33,080 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-28 18:32:33,081 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-28 18:32:33,082 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-28 18:32:33,084 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-28 18:32:33,084 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-28 18:32:33,086 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-28 18:32:33,088 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-28 18:32:33,090 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-28 18:32:33,092 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-28 18:32:33,094 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-28 18:32:33,095 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-28 18:32:33,096 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-28 18:32:33,099 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-28 18:32:33,100 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-28 18:32:33,100 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-28 18:32:33,101 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-28 18:32:33,102 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-28 18:32:33,103 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-28 18:32:33,103 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-28 18:32:33,104 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-28 18:32:33,105 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-28 18:32:33,106 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-28 18:32:33,107 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-28 18:32:33,107 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-28 18:32:33,108 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-28 18:32:33,109 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-28 18:32:33,109 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-28 18:32:33,110 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-28 18:32:33,111 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-28 18:32:33,112 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-28 18:32:33,128 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-28 18:32:33,128 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-28 18:32:33,130 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-28 18:32:33,130 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-28 18:32:33,131 INFO L138 SettingsManager]: * Use SBE=true [2019-11-28 18:32:33,131 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-28 18:32:33,131 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-28 18:32:33,131 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-28 18:32:33,132 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-28 18:32:33,132 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-28 18:32:33,132 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-28 18:32:33,133 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-28 18:32:33,133 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-28 18:32:33,133 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-28 18:32:33,133 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-28 18:32:33,134 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-28 18:32:33,134 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-28 18:32:33,134 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-28 18:32:33,135 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-28 18:32:33,135 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-28 18:32:33,135 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-28 18:32:33,135 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 18:32:33,136 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-28 18:32:33,136 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-28 18:32:33,136 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-28 18:32:33,137 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-28 18:32:33,137 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-28 18:32:33,137 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-28 18:32:33,138 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-11-28 18:32:33,138 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> eff86fe4110cf0b56af359bea2f58358a83b929a [2019-11-28 18:32:33,460 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-28 18:32:33,473 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-28 18:32:33,477 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-28 18:32:33,478 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-28 18:32:33,479 INFO L275 PluginConnector]: CDTParser initialized [2019-11-28 18:32:33,480 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/pthread-wmm/safe029_rmo.oepc.i [2019-11-28 18:32:33,543 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/45316cfec/dcbc902e6650429ab8024da22b97d837/FLAG9163b35fd [2019-11-28 18:32:34,131 INFO L306 CDTParser]: Found 1 translation units. [2019-11-28 18:32:34,131 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/pthread-wmm/safe029_rmo.oepc.i [2019-11-28 18:32:34,158 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/45316cfec/dcbc902e6650429ab8024da22b97d837/FLAG9163b35fd [2019-11-28 18:32:34,391 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/45316cfec/dcbc902e6650429ab8024da22b97d837 [2019-11-28 18:32:34,394 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-28 18:32:34,395 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-28 18:32:34,396 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-28 18:32:34,397 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-28 18:32:34,402 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-28 18:32:34,403 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 06:32:34" (1/1) ... [2019-11-28 18:32:34,407 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6822e6d4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:32:34, skipping insertion in model container [2019-11-28 18:32:34,407 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 06:32:34" (1/1) ... [2019-11-28 18:32:34,416 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-11-28 18:32:34,471 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-11-28 18:32:34,985 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 18:32:34,998 INFO L203 MainTranslator]: Completed pre-run [2019-11-28 18:32:35,088 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 18:32:35,167 INFO L208 MainTranslator]: Completed translation [2019-11-28 18:32:35,168 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:32:35 WrapperNode [2019-11-28 18:32:35,168 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-28 18:32:35,169 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-28 18:32:35,170 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-28 18:32:35,170 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-28 18:32:35,179 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:32:35" (1/1) ... [2019-11-28 18:32:35,199 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:32:35" (1/1) ... [2019-11-28 18:32:35,238 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-28 18:32:35,238 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-28 18:32:35,239 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-28 18:32:35,239 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-28 18:32:35,252 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:32:35" (1/1) ... [2019-11-28 18:32:35,252 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:32:35" (1/1) ... [2019-11-28 18:32:35,260 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:32:35" (1/1) ... [2019-11-28 18:32:35,260 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:32:35" (1/1) ... [2019-11-28 18:32:35,287 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:32:35" (1/1) ... [2019-11-28 18:32:35,292 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:32:35" (1/1) ... [2019-11-28 18:32:35,299 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:32:35" (1/1) ... [2019-11-28 18:32:35,306 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-28 18:32:35,307 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-28 18:32:35,307 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-28 18:32:35,307 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-28 18:32:35,308 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:32:35" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 18:32:35,377 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-11-28 18:32:35,378 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-11-28 18:32:35,378 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-11-28 18:32:35,379 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-11-28 18:32:35,380 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-11-28 18:32:35,380 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-11-28 18:32:35,380 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-11-28 18:32:35,380 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-11-28 18:32:35,381 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-11-28 18:32:35,381 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-28 18:32:35,381 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-28 18:32:35,384 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-11-28 18:32:36,082 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-28 18:32:36,082 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-11-28 18:32:36,084 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:32:36 BoogieIcfgContainer [2019-11-28 18:32:36,084 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-28 18:32:36,085 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-28 18:32:36,085 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-28 18:32:36,089 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-28 18:32:36,089 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 06:32:34" (1/3) ... [2019-11-28 18:32:36,090 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@24eb342b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 06:32:36, skipping insertion in model container [2019-11-28 18:32:36,091 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:32:35" (2/3) ... [2019-11-28 18:32:36,091 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@24eb342b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 06:32:36, skipping insertion in model container [2019-11-28 18:32:36,091 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:32:36" (3/3) ... [2019-11-28 18:32:36,093 INFO L109 eAbstractionObserver]: Analyzing ICFG safe029_rmo.oepc.i [2019-11-28 18:32:36,104 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-11-28 18:32:36,105 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-28 18:32:36,113 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-11-28 18:32:36,114 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-11-28 18:32:36,149 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,150 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,151 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,151 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,151 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,151 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,152 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,152 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,153 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,153 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,154 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,154 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,154 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,155 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,155 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,156 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,156 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,156 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,157 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,157 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,157 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,158 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,158 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,158 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,159 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,159 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,159 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,159 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,160 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,160 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,160 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,160 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,161 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,161 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,161 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,162 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,162 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,162 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,162 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,163 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,163 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,163 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,163 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,164 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,164 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,164 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,164 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,165 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,165 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,165 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,165 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,166 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,166 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,166 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,166 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,167 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,167 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,167 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,167 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,168 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,168 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,168 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,168 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,168 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:36,191 INFO L249 AbstractCegarLoop]: Starting to check reachability of 5 error locations. [2019-11-28 18:32:36,213 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-28 18:32:36,213 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-28 18:32:36,213 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-28 18:32:36,214 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-28 18:32:36,214 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-28 18:32:36,214 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-28 18:32:36,214 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-28 18:32:36,215 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-28 18:32:36,232 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 145 places, 179 transitions [2019-11-28 18:32:36,234 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 145 places, 179 transitions [2019-11-28 18:32:36,320 INFO L134 PetriNetUnfolder]: 41/177 cut-off events. [2019-11-28 18:32:36,320 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-11-28 18:32:36,334 INFO L76 FinitePrefix]: Finished finitePrefix Result has 184 conditions, 177 events. 41/177 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 466 event pairs. 6/140 useless extension candidates. Maximal degree in co-relation 150. Up to 2 conditions per place. [2019-11-28 18:32:36,356 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 145 places, 179 transitions [2019-11-28 18:32:36,403 INFO L134 PetriNetUnfolder]: 41/177 cut-off events. [2019-11-28 18:32:36,404 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-11-28 18:32:36,416 INFO L76 FinitePrefix]: Finished finitePrefix Result has 184 conditions, 177 events. 41/177 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 466 event pairs. 6/140 useless extension candidates. Maximal degree in co-relation 150. Up to 2 conditions per place. [2019-11-28 18:32:36,431 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 10418 [2019-11-28 18:32:36,433 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-11-28 18:32:40,895 WARN L192 SmtUtils]: Spent 258.00 ms on a formula simplification. DAG size of input: 79 DAG size of output: 77 [2019-11-28 18:32:41,010 WARN L192 SmtUtils]: Spent 113.00 ms on a formula simplification that was a NOOP. DAG size: 75 [2019-11-28 18:32:41,044 INFO L206 etLargeBlockEncoding]: Checked pairs total: 46212 [2019-11-28 18:32:41,044 INFO L214 etLargeBlockEncoding]: Total number of compositions: 97 [2019-11-28 18:32:41,047 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 78 places, 90 transitions [2019-11-28 18:32:41,692 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 8458 states. [2019-11-28 18:32:41,695 INFO L276 IsEmpty]: Start isEmpty. Operand 8458 states. [2019-11-28 18:32:41,704 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-11-28 18:32:41,705 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:32:41,706 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-11-28 18:32:41,707 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:32:41,718 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:32:41,723 INFO L82 PathProgramCache]: Analyzing trace with hash 717058, now seen corresponding path program 1 times [2019-11-28 18:32:41,738 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:32:41,739 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1236415264] [2019-11-28 18:32:41,739 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:32:41,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:32:42,160 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:32:42,161 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1236415264] [2019-11-28 18:32:42,164 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:32:42,165 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-11-28 18:32:42,167 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [123297544] [2019-11-28 18:32:42,175 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:32:42,176 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:32:42,211 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:32:42,212 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:32:42,216 INFO L87 Difference]: Start difference. First operand 8458 states. Second operand 3 states. [2019-11-28 18:32:42,548 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:32:42,548 INFO L93 Difference]: Finished difference Result 8394 states and 27476 transitions. [2019-11-28 18:32:42,549 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:32:42,551 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2019-11-28 18:32:42,551 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:32:42,667 INFO L225 Difference]: With dead ends: 8394 [2019-11-28 18:32:42,672 INFO L226 Difference]: Without dead ends: 8226 [2019-11-28 18:32:42,674 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:32:42,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8226 states. [2019-11-28 18:32:43,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8226 to 8226. [2019-11-28 18:32:43,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8226 states. [2019-11-28 18:32:43,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8226 states to 8226 states and 26958 transitions. [2019-11-28 18:32:43,167 INFO L78 Accepts]: Start accepts. Automaton has 8226 states and 26958 transitions. Word has length 3 [2019-11-28 18:32:43,167 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:32:43,168 INFO L462 AbstractCegarLoop]: Abstraction has 8226 states and 26958 transitions. [2019-11-28 18:32:43,168 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:32:43,168 INFO L276 IsEmpty]: Start isEmpty. Operand 8226 states and 26958 transitions. [2019-11-28 18:32:43,172 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-11-28 18:32:43,173 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:32:43,173 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:32:43,173 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:32:43,174 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:32:43,174 INFO L82 PathProgramCache]: Analyzing trace with hash 651590314, now seen corresponding path program 1 times [2019-11-28 18:32:43,174 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:32:43,175 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [22612744] [2019-11-28 18:32:43,175 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:32:43,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:32:43,314 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:32:43,314 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [22612744] [2019-11-28 18:32:43,314 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:32:43,315 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:32:43,315 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [683195886] [2019-11-28 18:32:43,317 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:32:43,317 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:32:43,318 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:32:43,318 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:32:43,318 INFO L87 Difference]: Start difference. First operand 8226 states and 26958 transitions. Second operand 4 states. [2019-11-28 18:32:43,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:32:43,727 INFO L93 Difference]: Finished difference Result 12778 states and 40134 transitions. [2019-11-28 18:32:43,728 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:32:43,728 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-11-28 18:32:43,728 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:32:43,821 INFO L225 Difference]: With dead ends: 12778 [2019-11-28 18:32:43,822 INFO L226 Difference]: Without dead ends: 12771 [2019-11-28 18:32:43,822 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:32:43,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12771 states. [2019-11-28 18:32:44,416 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12771 to 11467. [2019-11-28 18:32:44,416 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11467 states. [2019-11-28 18:32:44,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11467 states to 11467 states and 36507 transitions. [2019-11-28 18:32:44,469 INFO L78 Accepts]: Start accepts. Automaton has 11467 states and 36507 transitions. Word has length 11 [2019-11-28 18:32:44,469 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:32:44,470 INFO L462 AbstractCegarLoop]: Abstraction has 11467 states and 36507 transitions. [2019-11-28 18:32:44,470 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:32:44,470 INFO L276 IsEmpty]: Start isEmpty. Operand 11467 states and 36507 transitions. [2019-11-28 18:32:44,473 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-11-28 18:32:44,473 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:32:44,473 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:32:44,474 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:32:44,474 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:32:44,474 INFO L82 PathProgramCache]: Analyzing trace with hash -1968692504, now seen corresponding path program 1 times [2019-11-28 18:32:44,475 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:32:44,475 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [60528482] [2019-11-28 18:32:44,475 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:32:44,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:32:44,546 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:32:44,547 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [60528482] [2019-11-28 18:32:44,548 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:32:44,548 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:32:44,548 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1072708231] [2019-11-28 18:32:44,549 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:32:44,549 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:32:44,549 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:32:44,549 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:32:44,549 INFO L87 Difference]: Start difference. First operand 11467 states and 36507 transitions. Second operand 4 states. [2019-11-28 18:32:44,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:32:44,800 INFO L93 Difference]: Finished difference Result 14268 states and 44852 transitions. [2019-11-28 18:32:44,800 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:32:44,801 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-11-28 18:32:44,801 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:32:44,850 INFO L225 Difference]: With dead ends: 14268 [2019-11-28 18:32:44,850 INFO L226 Difference]: Without dead ends: 14268 [2019-11-28 18:32:44,852 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:32:44,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14268 states. [2019-11-28 18:32:45,217 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14268 to 12752. [2019-11-28 18:32:45,218 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12752 states. [2019-11-28 18:32:45,265 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12752 states to 12752 states and 40448 transitions. [2019-11-28 18:32:45,265 INFO L78 Accepts]: Start accepts. Automaton has 12752 states and 40448 transitions. Word has length 11 [2019-11-28 18:32:45,266 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:32:45,266 INFO L462 AbstractCegarLoop]: Abstraction has 12752 states and 40448 transitions. [2019-11-28 18:32:45,266 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:32:45,266 INFO L276 IsEmpty]: Start isEmpty. Operand 12752 states and 40448 transitions. [2019-11-28 18:32:45,271 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2019-11-28 18:32:45,272 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:32:45,272 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:32:45,272 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:32:45,273 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:32:45,273 INFO L82 PathProgramCache]: Analyzing trace with hash -1372508181, now seen corresponding path program 1 times [2019-11-28 18:32:45,273 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:32:45,274 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1615412322] [2019-11-28 18:32:45,274 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:32:45,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:32:45,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:32:45,350 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1615412322] [2019-11-28 18:32:45,350 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:32:45,351 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:32:45,351 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1807880684] [2019-11-28 18:32:45,351 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:32:45,352 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:32:45,352 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:32:45,352 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:32:45,352 INFO L87 Difference]: Start difference. First operand 12752 states and 40448 transitions. Second operand 5 states. [2019-11-28 18:32:45,820 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:32:45,825 INFO L93 Difference]: Finished difference Result 17010 states and 52843 transitions. [2019-11-28 18:32:45,826 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-11-28 18:32:45,826 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2019-11-28 18:32:45,826 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:32:45,884 INFO L225 Difference]: With dead ends: 17010 [2019-11-28 18:32:45,884 INFO L226 Difference]: Without dead ends: 17003 [2019-11-28 18:32:45,884 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-11-28 18:32:45,991 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17003 states. [2019-11-28 18:32:46,460 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17003 to 12755. [2019-11-28 18:32:46,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12755 states. [2019-11-28 18:32:46,499 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12755 states to 12755 states and 40342 transitions. [2019-11-28 18:32:46,500 INFO L78 Accepts]: Start accepts. Automaton has 12755 states and 40342 transitions. Word has length 17 [2019-11-28 18:32:46,500 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:32:46,503 INFO L462 AbstractCegarLoop]: Abstraction has 12755 states and 40342 transitions. [2019-11-28 18:32:46,503 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:32:46,503 INFO L276 IsEmpty]: Start isEmpty. Operand 12755 states and 40342 transitions. [2019-11-28 18:32:46,518 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-11-28 18:32:46,519 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:32:46,519 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:32:46,519 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:32:46,519 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:32:46,520 INFO L82 PathProgramCache]: Analyzing trace with hash -1155459573, now seen corresponding path program 1 times [2019-11-28 18:32:46,520 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:32:46,520 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1656081276] [2019-11-28 18:32:46,521 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:32:46,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:32:46,616 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:32:46,617 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1656081276] [2019-11-28 18:32:46,617 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:32:46,617 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:32:46,618 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [374880495] [2019-11-28 18:32:46,618 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:32:46,620 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:32:46,621 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:32:46,621 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:32:46,621 INFO L87 Difference]: Start difference. First operand 12755 states and 40342 transitions. Second operand 3 states. [2019-11-28 18:32:46,737 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:32:46,737 INFO L93 Difference]: Finished difference Result 15529 states and 48523 transitions. [2019-11-28 18:32:46,738 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:32:46,738 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2019-11-28 18:32:46,738 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:32:46,776 INFO L225 Difference]: With dead ends: 15529 [2019-11-28 18:32:46,776 INFO L226 Difference]: Without dead ends: 15529 [2019-11-28 18:32:46,777 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:32:46,873 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15529 states. [2019-11-28 18:32:47,122 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15529 to 13746. [2019-11-28 18:32:47,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13746 states. [2019-11-28 18:32:47,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13746 states to 13746 states and 43375 transitions. [2019-11-28 18:32:47,165 INFO L78 Accepts]: Start accepts. Automaton has 13746 states and 43375 transitions. Word has length 25 [2019-11-28 18:32:47,166 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:32:47,167 INFO L462 AbstractCegarLoop]: Abstraction has 13746 states and 43375 transitions. [2019-11-28 18:32:47,167 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:32:47,167 INFO L276 IsEmpty]: Start isEmpty. Operand 13746 states and 43375 transitions. [2019-11-28 18:32:47,187 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-11-28 18:32:47,187 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:32:47,188 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:32:47,188 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:32:47,188 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:32:47,189 INFO L82 PathProgramCache]: Analyzing trace with hash -1248228747, now seen corresponding path program 1 times [2019-11-28 18:32:47,189 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:32:47,189 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [920218327] [2019-11-28 18:32:47,189 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:32:47,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:32:47,311 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:32:47,311 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [920218327] [2019-11-28 18:32:47,311 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:32:47,311 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 18:32:47,313 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [72287807] [2019-11-28 18:32:47,313 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-28 18:32:47,313 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:32:47,314 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-28 18:32:47,314 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-11-28 18:32:47,314 INFO L87 Difference]: Start difference. First operand 13746 states and 43375 transitions. Second operand 6 states. [2019-11-28 18:32:47,788 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:32:47,789 INFO L93 Difference]: Finished difference Result 19657 states and 60760 transitions. [2019-11-28 18:32:47,789 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-11-28 18:32:47,789 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 25 [2019-11-28 18:32:47,790 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:32:47,828 INFO L225 Difference]: With dead ends: 19657 [2019-11-28 18:32:47,828 INFO L226 Difference]: Without dead ends: 19641 [2019-11-28 18:32:47,828 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2019-11-28 18:32:47,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19641 states. [2019-11-28 18:32:48,232 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19641 to 15905. [2019-11-28 18:32:48,232 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15905 states. [2019-11-28 18:32:48,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15905 states to 15905 states and 49859 transitions. [2019-11-28 18:32:48,282 INFO L78 Accepts]: Start accepts. Automaton has 15905 states and 49859 transitions. Word has length 25 [2019-11-28 18:32:48,282 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:32:48,282 INFO L462 AbstractCegarLoop]: Abstraction has 15905 states and 49859 transitions. [2019-11-28 18:32:48,283 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-28 18:32:48,283 INFO L276 IsEmpty]: Start isEmpty. Operand 15905 states and 49859 transitions. [2019-11-28 18:32:48,306 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-11-28 18:32:48,307 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:32:48,307 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:32:48,307 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:32:48,308 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:32:48,308 INFO L82 PathProgramCache]: Analyzing trace with hash 279625016, now seen corresponding path program 1 times [2019-11-28 18:32:48,308 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:32:48,309 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1612617460] [2019-11-28 18:32:48,309 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:32:48,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:32:48,436 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:32:48,437 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1612617460] [2019-11-28 18:32:48,437 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:32:48,438 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:32:48,438 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1585471960] [2019-11-28 18:32:48,439 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:32:48,439 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:32:48,439 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:32:48,439 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:32:48,439 INFO L87 Difference]: Start difference. First operand 15905 states and 49859 transitions. Second operand 4 states. [2019-11-28 18:32:48,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:32:48,481 INFO L93 Difference]: Finished difference Result 2247 states and 5122 transitions. [2019-11-28 18:32:48,482 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-28 18:32:48,482 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 31 [2019-11-28 18:32:48,482 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:32:48,485 INFO L225 Difference]: With dead ends: 2247 [2019-11-28 18:32:48,485 INFO L226 Difference]: Without dead ends: 1970 [2019-11-28 18:32:48,486 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:32:48,490 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1970 states. [2019-11-28 18:32:48,520 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1970 to 1970. [2019-11-28 18:32:48,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1970 states. [2019-11-28 18:32:48,525 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1970 states to 1970 states and 4356 transitions. [2019-11-28 18:32:48,526 INFO L78 Accepts]: Start accepts. Automaton has 1970 states and 4356 transitions. Word has length 31 [2019-11-28 18:32:48,526 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:32:48,526 INFO L462 AbstractCegarLoop]: Abstraction has 1970 states and 4356 transitions. [2019-11-28 18:32:48,527 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:32:48,527 INFO L276 IsEmpty]: Start isEmpty. Operand 1970 states and 4356 transitions. [2019-11-28 18:32:48,530 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2019-11-28 18:32:48,530 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:32:48,531 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:32:48,531 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:32:48,531 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:32:48,532 INFO L82 PathProgramCache]: Analyzing trace with hash -1011623832, now seen corresponding path program 1 times [2019-11-28 18:32:48,532 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:32:48,532 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1978955722] [2019-11-28 18:32:48,532 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:32:48,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:32:48,921 WARN L192 SmtUtils]: Spent 265.00 ms on a formula simplification that was a NOOP. DAG size: 6 [2019-11-28 18:32:49,019 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:32:49,020 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1978955722] [2019-11-28 18:32:49,021 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:32:49,022 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-28 18:32:49,022 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1144468560] [2019-11-28 18:32:49,023 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-11-28 18:32:49,023 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:32:49,024 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-11-28 18:32:49,024 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2019-11-28 18:32:49,024 INFO L87 Difference]: Start difference. First operand 1970 states and 4356 transitions. Second operand 8 states. [2019-11-28 18:32:49,825 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:32:49,825 INFO L93 Difference]: Finished difference Result 2561 states and 5544 transitions. [2019-11-28 18:32:49,825 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-11-28 18:32:49,826 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 37 [2019-11-28 18:32:49,826 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:32:49,831 INFO L225 Difference]: With dead ends: 2561 [2019-11-28 18:32:49,831 INFO L226 Difference]: Without dead ends: 2559 [2019-11-28 18:32:49,832 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=61, Invalid=179, Unknown=0, NotChecked=0, Total=240 [2019-11-28 18:32:49,837 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2559 states. [2019-11-28 18:32:49,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2559 to 2033. [2019-11-28 18:32:49,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2033 states. [2019-11-28 18:32:49,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2033 states to 2033 states and 4500 transitions. [2019-11-28 18:32:49,865 INFO L78 Accepts]: Start accepts. Automaton has 2033 states and 4500 transitions. Word has length 37 [2019-11-28 18:32:49,866 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:32:49,867 INFO L462 AbstractCegarLoop]: Abstraction has 2033 states and 4500 transitions. [2019-11-28 18:32:49,867 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-11-28 18:32:49,867 INFO L276 IsEmpty]: Start isEmpty. Operand 2033 states and 4500 transitions. [2019-11-28 18:32:49,871 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2019-11-28 18:32:49,872 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:32:49,872 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:32:49,872 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:32:49,872 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:32:49,873 INFO L82 PathProgramCache]: Analyzing trace with hash -669150451, now seen corresponding path program 1 times [2019-11-28 18:32:49,873 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:32:49,878 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1987333718] [2019-11-28 18:32:49,878 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:32:49,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:32:49,983 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:32:49,984 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1987333718] [2019-11-28 18:32:49,984 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:32:49,984 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 18:32:49,984 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2088406479] [2019-11-28 18:32:49,985 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:32:49,985 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:32:49,985 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:32:49,985 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:32:49,985 INFO L87 Difference]: Start difference. First operand 2033 states and 4500 transitions. Second operand 5 states. [2019-11-28 18:32:50,505 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:32:50,506 INFO L93 Difference]: Finished difference Result 2780 states and 6027 transitions. [2019-11-28 18:32:50,507 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 18:32:50,507 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 41 [2019-11-28 18:32:50,507 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:32:50,510 INFO L225 Difference]: With dead ends: 2780 [2019-11-28 18:32:50,510 INFO L226 Difference]: Without dead ends: 2780 [2019-11-28 18:32:50,510 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-11-28 18:32:50,516 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2780 states. [2019-11-28 18:32:50,543 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2780 to 2441. [2019-11-28 18:32:50,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2441 states. [2019-11-28 18:32:50,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2441 states to 2441 states and 5347 transitions. [2019-11-28 18:32:50,548 INFO L78 Accepts]: Start accepts. Automaton has 2441 states and 5347 transitions. Word has length 41 [2019-11-28 18:32:50,548 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:32:50,548 INFO L462 AbstractCegarLoop]: Abstraction has 2441 states and 5347 transitions. [2019-11-28 18:32:50,548 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:32:50,549 INFO L276 IsEmpty]: Start isEmpty. Operand 2441 states and 5347 transitions. [2019-11-28 18:32:50,552 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-11-28 18:32:50,553 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:32:50,553 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:32:50,553 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:32:50,554 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:32:50,554 INFO L82 PathProgramCache]: Analyzing trace with hash -1265386816, now seen corresponding path program 1 times [2019-11-28 18:32:50,554 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:32:50,554 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1481821631] [2019-11-28 18:32:50,555 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:32:50,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:32:50,637 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:32:50,637 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1481821631] [2019-11-28 18:32:50,638 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:32:50,638 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 18:32:50,638 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1205128795] [2019-11-28 18:32:50,638 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:32:50,639 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:32:50,639 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:32:50,639 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:32:50,639 INFO L87 Difference]: Start difference. First operand 2441 states and 5347 transitions. Second operand 5 states. [2019-11-28 18:32:51,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:32:51,191 INFO L93 Difference]: Finished difference Result 3289 states and 7089 transitions. [2019-11-28 18:32:51,191 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-11-28 18:32:51,191 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 42 [2019-11-28 18:32:51,192 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:32:51,195 INFO L225 Difference]: With dead ends: 3289 [2019-11-28 18:32:51,195 INFO L226 Difference]: Without dead ends: 3289 [2019-11-28 18:32:51,195 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-11-28 18:32:51,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3289 states. [2019-11-28 18:32:51,233 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3289 to 2732. [2019-11-28 18:32:51,233 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2732 states. [2019-11-28 18:32:51,239 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2732 states to 2732 states and 5972 transitions. [2019-11-28 18:32:51,239 INFO L78 Accepts]: Start accepts. Automaton has 2732 states and 5972 transitions. Word has length 42 [2019-11-28 18:32:51,239 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:32:51,239 INFO L462 AbstractCegarLoop]: Abstraction has 2732 states and 5972 transitions. [2019-11-28 18:32:51,240 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:32:51,240 INFO L276 IsEmpty]: Start isEmpty. Operand 2732 states and 5972 transitions. [2019-11-28 18:32:51,245 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-11-28 18:32:51,245 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:32:51,245 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:32:51,246 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:32:51,246 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:32:51,246 INFO L82 PathProgramCache]: Analyzing trace with hash 1349071825, now seen corresponding path program 1 times [2019-11-28 18:32:51,247 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:32:51,247 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1158582206] [2019-11-28 18:32:51,247 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:32:51,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:32:51,318 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:32:51,319 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1158582206] [2019-11-28 18:32:51,319 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:32:51,319 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 18:32:51,319 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [484033718] [2019-11-28 18:32:51,320 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:32:51,320 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:32:51,320 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:32:51,320 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:32:51,321 INFO L87 Difference]: Start difference. First operand 2732 states and 5972 transitions. Second operand 5 states. [2019-11-28 18:32:51,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:32:51,365 INFO L93 Difference]: Finished difference Result 706 states and 1302 transitions. [2019-11-28 18:32:51,365 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:32:51,365 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 42 [2019-11-28 18:32:51,366 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:32:51,366 INFO L225 Difference]: With dead ends: 706 [2019-11-28 18:32:51,367 INFO L226 Difference]: Without dead ends: 626 [2019-11-28 18:32:51,367 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-11-28 18:32:51,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states. [2019-11-28 18:32:51,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 500. [2019-11-28 18:32:51,375 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 500 states. [2019-11-28 18:32:51,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 500 states to 500 states and 913 transitions. [2019-11-28 18:32:51,376 INFO L78 Accepts]: Start accepts. Automaton has 500 states and 913 transitions. Word has length 42 [2019-11-28 18:32:51,376 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:32:51,377 INFO L462 AbstractCegarLoop]: Abstraction has 500 states and 913 transitions. [2019-11-28 18:32:51,377 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:32:51,377 INFO L276 IsEmpty]: Start isEmpty. Operand 500 states and 913 transitions. [2019-11-28 18:32:51,378 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2019-11-28 18:32:51,378 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:32:51,379 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:32:51,379 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:32:51,379 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:32:51,379 INFO L82 PathProgramCache]: Analyzing trace with hash -1583281740, now seen corresponding path program 1 times [2019-11-28 18:32:51,380 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:32:51,380 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [247446201] [2019-11-28 18:32:51,380 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:32:51,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:32:51,532 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:32:51,532 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [247446201] [2019-11-28 18:32:51,533 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:32:51,533 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-28 18:32:51,534 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1251282792] [2019-11-28 18:32:51,534 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-28 18:32:51,535 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:32:51,535 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-28 18:32:51,536 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-28 18:32:51,536 INFO L87 Difference]: Start difference. First operand 500 states and 913 transitions. Second operand 6 states. [2019-11-28 18:32:51,841 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:32:51,842 INFO L93 Difference]: Finished difference Result 701 states and 1268 transitions. [2019-11-28 18:32:51,842 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-28 18:32:51,842 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 52 [2019-11-28 18:32:51,843 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:32:51,844 INFO L225 Difference]: With dead ends: 701 [2019-11-28 18:32:51,844 INFO L226 Difference]: Without dead ends: 701 [2019-11-28 18:32:51,844 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=32, Invalid=78, Unknown=0, NotChecked=0, Total=110 [2019-11-28 18:32:51,845 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 701 states. [2019-11-28 18:32:51,849 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 701 to 533. [2019-11-28 18:32:51,849 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 533 states. [2019-11-28 18:32:51,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 533 states to 533 states and 974 transitions. [2019-11-28 18:32:51,850 INFO L78 Accepts]: Start accepts. Automaton has 533 states and 974 transitions. Word has length 52 [2019-11-28 18:32:51,850 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:32:51,850 INFO L462 AbstractCegarLoop]: Abstraction has 533 states and 974 transitions. [2019-11-28 18:32:51,850 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-28 18:32:51,851 INFO L276 IsEmpty]: Start isEmpty. Operand 533 states and 974 transitions. [2019-11-28 18:32:51,852 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2019-11-28 18:32:51,852 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:32:51,852 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:32:51,852 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:32:51,852 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:32:51,853 INFO L82 PathProgramCache]: Analyzing trace with hash 1092311168, now seen corresponding path program 2 times [2019-11-28 18:32:51,853 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:32:51,853 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1123054891] [2019-11-28 18:32:51,854 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:32:51,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:32:51,997 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:32:51,997 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1123054891] [2019-11-28 18:32:51,998 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:32:51,998 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 18:32:51,998 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1915011740] [2019-11-28 18:32:51,999 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-28 18:32:51,999 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:32:52,001 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-28 18:32:52,004 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-11-28 18:32:52,009 INFO L87 Difference]: Start difference. First operand 533 states and 974 transitions. Second operand 6 states. [2019-11-28 18:32:52,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:32:52,092 INFO L93 Difference]: Finished difference Result 927 states and 1713 transitions. [2019-11-28 18:32:52,093 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 18:32:52,093 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 52 [2019-11-28 18:32:52,094 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:32:52,095 INFO L225 Difference]: With dead ends: 927 [2019-11-28 18:32:52,095 INFO L226 Difference]: Without dead ends: 463 [2019-11-28 18:32:52,095 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-11-28 18:32:52,098 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 463 states. [2019-11-28 18:32:52,104 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 463 to 399. [2019-11-28 18:32:52,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 399 states. [2019-11-28 18:32:52,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 399 states and 739 transitions. [2019-11-28 18:32:52,106 INFO L78 Accepts]: Start accepts. Automaton has 399 states and 739 transitions. Word has length 52 [2019-11-28 18:32:52,106 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:32:52,106 INFO L462 AbstractCegarLoop]: Abstraction has 399 states and 739 transitions. [2019-11-28 18:32:52,107 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-28 18:32:52,107 INFO L276 IsEmpty]: Start isEmpty. Operand 399 states and 739 transitions. [2019-11-28 18:32:52,108 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2019-11-28 18:32:52,108 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:32:52,109 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:32:52,109 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:32:52,109 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:32:52,110 INFO L82 PathProgramCache]: Analyzing trace with hash 1013051528, now seen corresponding path program 3 times [2019-11-28 18:32:52,110 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:32:52,111 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1336769527] [2019-11-28 18:32:52,111 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:32:52,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:32:52,254 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:32:52,255 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1336769527] [2019-11-28 18:32:52,255 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:32:52,255 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-11-28 18:32:52,256 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [945328195] [2019-11-28 18:32:52,256 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-11-28 18:32:52,257 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:32:52,257 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-11-28 18:32:52,257 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-11-28 18:32:52,258 INFO L87 Difference]: Start difference. First operand 399 states and 739 transitions. Second operand 7 states. [2019-11-28 18:32:52,573 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:32:52,574 INFO L93 Difference]: Finished difference Result 585 states and 1055 transitions. [2019-11-28 18:32:52,574 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-11-28 18:32:52,574 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 52 [2019-11-28 18:32:52,575 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:32:52,575 INFO L225 Difference]: With dead ends: 585 [2019-11-28 18:32:52,575 INFO L226 Difference]: Without dead ends: 585 [2019-11-28 18:32:52,576 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2019-11-28 18:32:52,578 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 585 states. [2019-11-28 18:32:52,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 585 to 406. [2019-11-28 18:32:52,583 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 406 states. [2019-11-28 18:32:52,584 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 406 states to 406 states and 752 transitions. [2019-11-28 18:32:52,584 INFO L78 Accepts]: Start accepts. Automaton has 406 states and 752 transitions. Word has length 52 [2019-11-28 18:32:52,585 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:32:52,585 INFO L462 AbstractCegarLoop]: Abstraction has 406 states and 752 transitions. [2019-11-28 18:32:52,585 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-11-28 18:32:52,585 INFO L276 IsEmpty]: Start isEmpty. Operand 406 states and 752 transitions. [2019-11-28 18:32:52,586 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2019-11-28 18:32:52,586 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:32:52,586 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:32:52,587 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:32:52,587 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:32:52,587 INFO L82 PathProgramCache]: Analyzing trace with hash -948892510, now seen corresponding path program 1 times [2019-11-28 18:32:52,587 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:32:52,588 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [417030878] [2019-11-28 18:32:52,588 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:32:52,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:32:52,714 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:32:52,715 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [417030878] [2019-11-28 18:32:52,715 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:32:52,715 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:32:52,715 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1481723260] [2019-11-28 18:32:52,715 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:32:52,716 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:32:52,716 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:32:52,716 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:32:52,716 INFO L87 Difference]: Start difference. First operand 406 states and 752 transitions. Second operand 3 states. [2019-11-28 18:32:52,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:32:52,727 INFO L93 Difference]: Finished difference Result 356 states and 639 transitions. [2019-11-28 18:32:52,727 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:32:52,727 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 53 [2019-11-28 18:32:52,728 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:32:52,728 INFO L225 Difference]: With dead ends: 356 [2019-11-28 18:32:52,728 INFO L226 Difference]: Without dead ends: 356 [2019-11-28 18:32:52,728 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:32:52,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 356 states. [2019-11-28 18:32:52,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 356 to 356. [2019-11-28 18:32:52,736 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 356 states. [2019-11-28 18:32:52,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 356 states to 356 states and 639 transitions. [2019-11-28 18:32:52,737 INFO L78 Accepts]: Start accepts. Automaton has 356 states and 639 transitions. Word has length 53 [2019-11-28 18:32:52,738 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:32:52,738 INFO L462 AbstractCegarLoop]: Abstraction has 356 states and 639 transitions. [2019-11-28 18:32:52,738 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:32:52,738 INFO L276 IsEmpty]: Start isEmpty. Operand 356 states and 639 transitions. [2019-11-28 18:32:52,739 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2019-11-28 18:32:52,739 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:32:52,740 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:32:52,740 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:32:52,740 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:32:52,740 INFO L82 PathProgramCache]: Analyzing trace with hash 2062591520, now seen corresponding path program 1 times [2019-11-28 18:32:52,741 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:32:52,741 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1804672448] [2019-11-28 18:32:52,741 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:32:52,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:32:52,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:32:52,819 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1804672448] [2019-11-28 18:32:52,819 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:32:52,820 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:32:52,820 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [206700395] [2019-11-28 18:32:52,820 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:32:52,820 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:32:52,821 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:32:52,824 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:32:52,824 INFO L87 Difference]: Start difference. First operand 356 states and 639 transitions. Second operand 3 states. [2019-11-28 18:32:52,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:32:52,871 INFO L93 Difference]: Finished difference Result 355 states and 637 transitions. [2019-11-28 18:32:52,872 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:32:52,872 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 53 [2019-11-28 18:32:52,872 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:32:52,873 INFO L225 Difference]: With dead ends: 355 [2019-11-28 18:32:52,873 INFO L226 Difference]: Without dead ends: 355 [2019-11-28 18:32:52,874 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:32:52,875 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 355 states. [2019-11-28 18:32:52,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 355 to 219. [2019-11-28 18:32:52,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 219 states. [2019-11-28 18:32:52,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 219 states to 219 states and 389 transitions. [2019-11-28 18:32:52,879 INFO L78 Accepts]: Start accepts. Automaton has 219 states and 389 transitions. Word has length 53 [2019-11-28 18:32:52,879 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:32:52,879 INFO L462 AbstractCegarLoop]: Abstraction has 219 states and 389 transitions. [2019-11-28 18:32:52,880 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:32:52,880 INFO L276 IsEmpty]: Start isEmpty. Operand 219 states and 389 transitions. [2019-11-28 18:32:52,880 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-11-28 18:32:52,881 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:32:52,881 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:32:52,881 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:32:52,881 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:32:52,882 INFO L82 PathProgramCache]: Analyzing trace with hash 133727006, now seen corresponding path program 1 times [2019-11-28 18:32:52,882 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:32:52,882 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [583173289] [2019-11-28 18:32:52,883 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:32:52,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:32:53,491 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:32:53,491 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [583173289] [2019-11-28 18:32:53,492 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:32:53,492 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2019-11-28 18:32:53,492 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1685167845] [2019-11-28 18:32:53,492 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-11-28 18:32:53,493 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:32:53,493 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-11-28 18:32:53,493 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=197, Unknown=0, NotChecked=0, Total=240 [2019-11-28 18:32:53,493 INFO L87 Difference]: Start difference. First operand 219 states and 389 transitions. Second operand 16 states. [2019-11-28 18:32:54,876 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:32:54,877 INFO L93 Difference]: Finished difference Result 510 states and 863 transitions. [2019-11-28 18:32:54,877 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2019-11-28 18:32:54,877 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 54 [2019-11-28 18:32:54,878 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:32:54,878 INFO L225 Difference]: With dead ends: 510 [2019-11-28 18:32:54,879 INFO L226 Difference]: Without dead ends: 462 [2019-11-28 18:32:54,880 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 213 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=173, Invalid=949, Unknown=0, NotChecked=0, Total=1122 [2019-11-28 18:32:54,881 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 462 states. [2019-11-28 18:32:54,884 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 462 to 317. [2019-11-28 18:32:54,884 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 317 states. [2019-11-28 18:32:54,884 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 317 states to 317 states and 559 transitions. [2019-11-28 18:32:54,885 INFO L78 Accepts]: Start accepts. Automaton has 317 states and 559 transitions. Word has length 54 [2019-11-28 18:32:54,885 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:32:54,885 INFO L462 AbstractCegarLoop]: Abstraction has 317 states and 559 transitions. [2019-11-28 18:32:54,885 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-11-28 18:32:54,885 INFO L276 IsEmpty]: Start isEmpty. Operand 317 states and 559 transitions. [2019-11-28 18:32:54,886 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-11-28 18:32:54,886 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:32:54,886 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:32:54,886 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:32:54,886 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:32:54,886 INFO L82 PathProgramCache]: Analyzing trace with hash -224039150, now seen corresponding path program 2 times [2019-11-28 18:32:54,887 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:32:54,887 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1883349161] [2019-11-28 18:32:54,887 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:32:54,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:32:55,154 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:32:55,156 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1883349161] [2019-11-28 18:32:55,157 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:32:55,157 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-11-28 18:32:55,158 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [355989588] [2019-11-28 18:32:55,158 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-11-28 18:32:55,158 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:32:55,159 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-11-28 18:32:55,160 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=128, Unknown=0, NotChecked=0, Total=156 [2019-11-28 18:32:55,161 INFO L87 Difference]: Start difference. First operand 317 states and 559 transitions. Second operand 13 states. [2019-11-28 18:32:55,667 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:32:55,667 INFO L93 Difference]: Finished difference Result 500 states and 845 transitions. [2019-11-28 18:32:55,667 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-11-28 18:32:55,668 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 54 [2019-11-28 18:32:55,668 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:32:55,669 INFO L225 Difference]: With dead ends: 500 [2019-11-28 18:32:55,669 INFO L226 Difference]: Without dead ends: 469 [2019-11-28 18:32:55,670 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 61 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=80, Invalid=382, Unknown=0, NotChecked=0, Total=462 [2019-11-28 18:32:55,670 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 469 states. [2019-11-28 18:32:55,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 469 to 329. [2019-11-28 18:32:55,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 329 states. [2019-11-28 18:32:55,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 329 states to 329 states and 579 transitions. [2019-11-28 18:32:55,673 INFO L78 Accepts]: Start accepts. Automaton has 329 states and 579 transitions. Word has length 54 [2019-11-28 18:32:55,674 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:32:55,674 INFO L462 AbstractCegarLoop]: Abstraction has 329 states and 579 transitions. [2019-11-28 18:32:55,674 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-11-28 18:32:55,674 INFO L276 IsEmpty]: Start isEmpty. Operand 329 states and 579 transitions. [2019-11-28 18:32:55,674 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-11-28 18:32:55,675 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:32:55,675 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:32:55,675 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:32:55,675 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:32:55,676 INFO L82 PathProgramCache]: Analyzing trace with hash 881857310, now seen corresponding path program 3 times [2019-11-28 18:32:55,676 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:32:55,676 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1772459143] [2019-11-28 18:32:55,676 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:32:55,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:32:55,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:32:55,920 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1772459143] [2019-11-28 18:32:55,920 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:32:55,920 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-11-28 18:32:55,921 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1016328050] [2019-11-28 18:32:55,921 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-11-28 18:32:55,921 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:32:55,921 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-11-28 18:32:55,922 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=173, Unknown=0, NotChecked=0, Total=210 [2019-11-28 18:32:55,922 INFO L87 Difference]: Start difference. First operand 329 states and 579 transitions. Second operand 15 states. [2019-11-28 18:32:56,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:32:56,682 INFO L93 Difference]: Finished difference Result 545 states and 913 transitions. [2019-11-28 18:32:56,682 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2019-11-28 18:32:56,683 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 54 [2019-11-28 18:32:56,683 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:32:56,684 INFO L225 Difference]: With dead ends: 545 [2019-11-28 18:32:56,684 INFO L226 Difference]: Without dead ends: 504 [2019-11-28 18:32:56,685 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 107 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=113, Invalid=589, Unknown=0, NotChecked=0, Total=702 [2019-11-28 18:32:56,686 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states. [2019-11-28 18:32:56,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 330. [2019-11-28 18:32:56,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 330 states. [2019-11-28 18:32:56,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 330 states to 330 states and 580 transitions. [2019-11-28 18:32:56,689 INFO L78 Accepts]: Start accepts. Automaton has 330 states and 580 transitions. Word has length 54 [2019-11-28 18:32:56,689 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:32:56,689 INFO L462 AbstractCegarLoop]: Abstraction has 330 states and 580 transitions. [2019-11-28 18:32:56,689 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-11-28 18:32:56,689 INFO L276 IsEmpty]: Start isEmpty. Operand 330 states and 580 transitions. [2019-11-28 18:32:56,690 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-11-28 18:32:56,690 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:32:56,690 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:32:56,691 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:32:56,691 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:32:56,691 INFO L82 PathProgramCache]: Analyzing trace with hash -1097685616, now seen corresponding path program 4 times [2019-11-28 18:32:56,691 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:32:56,692 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [483386888] [2019-11-28 18:32:56,692 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:32:56,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:32:56,909 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:32:56,910 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [483386888] [2019-11-28 18:32:56,910 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:32:56,910 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-11-28 18:32:56,910 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [869317695] [2019-11-28 18:32:56,911 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-11-28 18:32:56,911 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:32:56,911 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-11-28 18:32:56,912 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=126, Unknown=0, NotChecked=0, Total=156 [2019-11-28 18:32:56,912 INFO L87 Difference]: Start difference. First operand 330 states and 580 transitions. Second operand 13 states. [2019-11-28 18:32:57,415 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:32:57,415 INFO L93 Difference]: Finished difference Result 499 states and 839 transitions. [2019-11-28 18:32:57,416 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-11-28 18:32:57,416 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 54 [2019-11-28 18:32:57,417 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:32:57,418 INFO L225 Difference]: With dead ends: 499 [2019-11-28 18:32:57,418 INFO L226 Difference]: Without dead ends: 468 [2019-11-28 18:32:57,418 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 57 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=84, Invalid=378, Unknown=0, NotChecked=0, Total=462 [2019-11-28 18:32:57,420 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 468 states. [2019-11-28 18:32:57,425 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 468 to 329. [2019-11-28 18:32:57,425 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 329 states. [2019-11-28 18:32:57,426 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 329 states to 329 states and 578 transitions. [2019-11-28 18:32:57,427 INFO L78 Accepts]: Start accepts. Automaton has 329 states and 578 transitions. Word has length 54 [2019-11-28 18:32:57,427 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:32:57,427 INFO L462 AbstractCegarLoop]: Abstraction has 329 states and 578 transitions. [2019-11-28 18:32:57,428 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-11-28 18:32:57,428 INFO L276 IsEmpty]: Start isEmpty. Operand 329 states and 578 transitions. [2019-11-28 18:32:57,429 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-11-28 18:32:57,429 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:32:57,429 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:32:57,430 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:32:57,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:32:57,430 INFO L82 PathProgramCache]: Analyzing trace with hash -1701611196, now seen corresponding path program 5 times [2019-11-28 18:32:57,431 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:32:57,431 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [921912247] [2019-11-28 18:32:57,431 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:32:57,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:32:57,720 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:32:57,721 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [921912247] [2019-11-28 18:32:57,721 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:32:57,721 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-11-28 18:32:57,722 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [263234069] [2019-11-28 18:32:57,722 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-11-28 18:32:57,722 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:32:57,723 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-11-28 18:32:57,723 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=128, Unknown=0, NotChecked=0, Total=156 [2019-11-28 18:32:57,723 INFO L87 Difference]: Start difference. First operand 329 states and 578 transitions. Second operand 13 states. [2019-11-28 18:32:58,120 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:32:58,120 INFO L93 Difference]: Finished difference Result 430 states and 730 transitions. [2019-11-28 18:32:58,121 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-11-28 18:32:58,121 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 54 [2019-11-28 18:32:58,121 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:32:58,122 INFO L225 Difference]: With dead ends: 430 [2019-11-28 18:32:58,122 INFO L226 Difference]: Without dead ends: 399 [2019-11-28 18:32:58,123 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 68 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=90, Invalid=416, Unknown=0, NotChecked=0, Total=506 [2019-11-28 18:32:58,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 399 states. [2019-11-28 18:32:58,128 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 399 to 327. [2019-11-28 18:32:58,128 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 327 states. [2019-11-28 18:32:58,129 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 327 states to 327 states and 574 transitions. [2019-11-28 18:32:58,129 INFO L78 Accepts]: Start accepts. Automaton has 327 states and 574 transitions. Word has length 54 [2019-11-28 18:32:58,129 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:32:58,130 INFO L462 AbstractCegarLoop]: Abstraction has 327 states and 574 transitions. [2019-11-28 18:32:58,130 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-11-28 18:32:58,130 INFO L276 IsEmpty]: Start isEmpty. Operand 327 states and 574 transitions. [2019-11-28 18:32:58,131 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-11-28 18:32:58,131 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:32:58,131 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:32:58,131 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:32:58,132 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:32:58,132 INFO L82 PathProgramCache]: Analyzing trace with hash 2067211286, now seen corresponding path program 6 times [2019-11-28 18:32:58,132 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:32:58,132 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [176949316] [2019-11-28 18:32:58,132 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:32:58,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 18:32:58,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 18:32:58,227 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-28 18:32:58,227 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-28 18:32:58,231 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [696] [696] ULTIMATE.startENTRY-->L777: Formula: (let ((.cse0 (store |v_#valid_40| 0 0))) (and (= 0 v_~y$read_delayed_var~0.base_6) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t2481~0.base_19| 4)) (= 0 |v_ULTIMATE.start_main_~#t2481~0.offset_16|) (= 0 v_~__unbuffered_cnt~0_61) (= v_~weak$$choice2~0_132 0) (= |v_#NULL.offset_6| 0) (= v_~y$read_delayed~0_7 0) (= v_~y$w_buff1_used~0_444 0) (= v_~y$r_buff1_thd0~0_304 0) (= v_~main$tmp_guard0~0_23 0) (= v_~y$r_buff0_thd0~0_394 0) (= (select .cse0 |v_ULTIMATE.start_main_~#t2481~0.base_19|) 0) (= 0 v_~y$w_buff0~0_376) (= 0 |v_#NULL.base_6|) (< |v_#StackHeapBarrier_13| |v_ULTIMATE.start_main_~#t2481~0.base_19|) (= v_~y$r_buff1_thd1~0_220 0) (= v_~y~0_141 0) (= v_~y$r_buff0_thd1~0_301 0) (= 0 v_~weak$$choice0~0_24) (= 0 v_~y$flush_delayed~0_48) (= 0 v_~y$r_buff0_thd2~0_175) (= v_~y$w_buff1~0_254 0) (= |v_#valid_38| (store .cse0 |v_ULTIMATE.start_main_~#t2481~0.base_19| 1)) (= v_~y$mem_tmp~0_31 0) (= v_~y$w_buff0_used~0_753 0) (= 0 v_~y$read_delayed_var~0.offset_6) (= 0 v_~y$r_buff1_thd2~0_205) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t2481~0.base_19| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t2481~0.base_19|) |v_ULTIMATE.start_main_~#t2481~0.offset_16| 0)) |v_#memory_int_15|) (= 0 v_~x~0_168) (< 0 |v_#StackHeapBarrier_13|) (= v_~main$tmp_guard1~0_22 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_16|, #length=|v_#length_16|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_45|, #NULL.offset=|v_#NULL.offset_6|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_32|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_32|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_42|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_56|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_35|, ~y$read_delayed~0=v_~y$read_delayed~0_7, ULTIMATE.start_main_~#t2481~0.offset=|v_ULTIMATE.start_main_~#t2481~0.offset_16|, ~y$mem_tmp~0=v_~y$mem_tmp~0_31, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_301, ~y$flush_delayed~0=v_~y$flush_delayed~0_48, ULTIMATE.start_main_~#t2482~0.base=|v_ULTIMATE.start_main_~#t2482~0.base_19|, #length=|v_#length_15|, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_29|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_32|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_44|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_35|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_51|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_45|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_31|, ~weak$$choice0~0=v_~weak$$choice0~0_24, #StackHeapBarrier=|v_#StackHeapBarrier_13|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_30|, ~y$w_buff1~0=v_~y$w_buff1~0_254, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_6, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_175, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_8|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_61, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_304, ~x~0=v_~x~0_168, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_6, ULTIMATE.start_main_~#t2482~0.offset=|v_ULTIMATE.start_main_~#t2482~0.offset_15|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_753, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_28|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_28|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_22, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_43|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_28|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_46|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_28|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_220, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_39|, ~y$w_buff0~0=v_~y$w_buff0~0_376, ~y~0=v_~y~0_141, ULTIMATE.start_main_#t~ite17=|v_ULTIMATE.start_main_#t~ite17_30|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_44|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_26|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_37|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_29|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_23, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_28|, #NULL.base=|v_#NULL.base_6|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_39|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_205, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_16|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_15|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_394, #valid=|v_#valid_38|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_13|, ~weak$$choice2~0=v_~weak$$choice2~0_132, ULTIMATE.start_main_~#t2481~0.base=|v_ULTIMATE.start_main_~#t2481~0.base_19|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_444} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~y$read_delayed~0, ULTIMATE.start_main_~#t2481~0.offset, ~y$mem_tmp~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, ULTIMATE.start_main_~#t2482~0.base, #length, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ~y$read_delayed_var~0.offset, ULTIMATE.start_main_~#t2482~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ~y$w_buff0~0, ~y~0, ULTIMATE.start_main_#t~ite17, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ~weak$$choice2~0, ULTIMATE.start_main_~#t2481~0.base, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:32:58,232 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [677] [677] L777-1-->L779: Formula: (and (not (= |v_ULTIMATE.start_main_~#t2482~0.base_11| 0)) (= |v_#memory_int_9| (store |v_#memory_int_10| |v_ULTIMATE.start_main_~#t2482~0.base_11| (store (select |v_#memory_int_10| |v_ULTIMATE.start_main_~#t2482~0.base_11|) |v_ULTIMATE.start_main_~#t2482~0.offset_10| 1))) (< |v_#StackHeapBarrier_8| |v_ULTIMATE.start_main_~#t2482~0.base_11|) (= |v_#valid_21| (store |v_#valid_22| |v_ULTIMATE.start_main_~#t2482~0.base_11| 1)) (= 0 |v_ULTIMATE.start_main_~#t2482~0.offset_10|) (= (store |v_#length_10| |v_ULTIMATE.start_main_~#t2482~0.base_11| 4) |v_#length_9|) (= 0 (select |v_#valid_22| |v_ULTIMATE.start_main_~#t2482~0.base_11|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_8|, #valid=|v_#valid_22|, #memory_int=|v_#memory_int_10|, #length=|v_#length_10|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_8|, ULTIMATE.start_main_~#t2482~0.offset=|v_ULTIMATE.start_main_~#t2482~0.offset_10|, #valid=|v_#valid_21|, #memory_int=|v_#memory_int_9|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, ULTIMATE.start_main_~#t2482~0.base=|v_ULTIMATE.start_main_~#t2482~0.base_11|, #length=|v_#length_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2482~0.offset, #valid, #memory_int, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_~#t2482~0.base, #length] because there is no mapped edge [2019-11-28 18:32:58,233 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [623] [623] P0ENTRY-->L4-3: Formula: (and (= 2 v_~y$w_buff0~0_172) (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_79 0)) (= (ite (not (and (not (= (mod v_~y$w_buff0_used~0_290 256) 0)) (not (= 0 (mod v_~y$w_buff1_used~0_162 256))))) 1 0) |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_77|) (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_79 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_77|) (= v_~y$w_buff0_used~0_290 1) (= v_P0Thread1of1ForFork0_~arg.offset_77 |v_P0Thread1of1ForFork0_#in~arg.offset_79|) (= v_P0Thread1of1ForFork0_~arg.base_77 |v_P0Thread1of1ForFork0_#in~arg.base_79|) (= v_~y$w_buff0_used~0_291 v_~y$w_buff1_used~0_162) (= v_~y$w_buff1~0_100 v_~y$w_buff0~0_173)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_79|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_291, ~y$w_buff0~0=v_~y$w_buff0~0_173, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_79|} OutVars{P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_79|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_290, ~y$w_buff1~0=v_~y$w_buff1~0_100, ~y$w_buff0~0=v_~y$w_buff0~0_172, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_79, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_79|, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_77, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_77|, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_77, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_162} AuxVars[] AssignedVars[~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P0Thread1of1ForFork0___VERIFIER_assert_~expression, P0Thread1of1ForFork0_~arg.base, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression, P0Thread1of1ForFork0_~arg.offset, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:32:58,234 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [656] [656] L735-->L735-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd1~0_In-1575932751 256))) (.cse0 (= (mod ~y$w_buff0_used~0_In-1575932751 256) 0))) (or (and (not .cse0) (not .cse1) (= |P0Thread1of1ForFork0_#t~ite5_Out-1575932751| 0)) (and (or .cse1 .cse0) (= |P0Thread1of1ForFork0_#t~ite5_Out-1575932751| ~y$w_buff0_used~0_In-1575932751)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1575932751, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In-1575932751} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out-1575932751|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1575932751, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In-1575932751} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-11-28 18:32:58,235 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [648] [648] L754-2-->L754-4: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff1_used~0_In-330043530 256))) (.cse1 (= (mod ~y$r_buff1_thd2~0_In-330043530 256) 0))) (or (and (= ~y~0_In-330043530 |P1Thread1of1ForFork1_#t~ite9_Out-330043530|) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= ~y$w_buff1~0_In-330043530 |P1Thread1of1ForFork1_#t~ite9_Out-330043530|)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-330043530, ~y$w_buff1~0=~y$w_buff1~0_In-330043530, ~y~0=~y~0_In-330043530, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-330043530} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-330043530, ~y$w_buff1~0=~y$w_buff1~0_In-330043530, P1Thread1of1ForFork1_#t~ite9=|P1Thread1of1ForFork1_#t~ite9_Out-330043530|, ~y~0=~y~0_In-330043530, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-330043530} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9] because there is no mapped edge [2019-11-28 18:32:58,235 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [630] [630] L754-4-->L755: Formula: (= v_~y~0_50 |v_P1Thread1of1ForFork1_#t~ite9_12|) InVars {P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_12|} OutVars{P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_11|, P1Thread1of1ForFork1_#t~ite10=|v_P1Thread1of1ForFork1_#t~ite10_13|, ~y~0=v_~y~0_50} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9, P1Thread1of1ForFork1_#t~ite10, ~y~0] because there is no mapped edge [2019-11-28 18:32:58,236 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [640] [640] L755-->L755-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In502986957 256))) (.cse0 (= (mod ~y$w_buff0_used~0_In502986957 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork1_#t~ite11_Out502986957|)) (and (= ~y$w_buff0_used~0_In502986957 |P1Thread1of1ForFork1_#t~ite11_Out502986957|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In502986957, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In502986957} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In502986957, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In502986957, P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out502986957|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-11-28 18:32:58,236 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [657] [657] L736-->L736-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In439924727 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd1~0_In439924727 256))) (.cse2 (= 0 (mod ~y$r_buff1_thd1~0_In439924727 256))) (.cse3 (= 0 (mod ~y$w_buff1_used~0_In439924727 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P0Thread1of1ForFork0_#t~ite6_Out439924727| 0)) (and (or .cse1 .cse0) (= |P0Thread1of1ForFork0_#t~ite6_Out439924727| ~y$w_buff1_used~0_In439924727) (or .cse2 .cse3)))) InVars {~y$r_buff1_thd1~0=~y$r_buff1_thd1~0_In439924727, ~y$w_buff0_used~0=~y$w_buff0_used~0_In439924727, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In439924727, ~y$w_buff1_used~0=~y$w_buff1_used~0_In439924727} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out439924727|, ~y$r_buff1_thd1~0=~y$r_buff1_thd1~0_In439924727, ~y$w_buff0_used~0=~y$w_buff0_used~0_In439924727, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In439924727, ~y$w_buff1_used~0=~y$w_buff1_used~0_In439924727} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-11-28 18:32:58,237 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [643] [643] L737-->L738: Formula: (let ((.cse0 (= ~y$r_buff0_thd1~0_In-1937141926 ~y$r_buff0_thd1~0_Out-1937141926)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1937141926 256))) (.cse2 (= (mod ~y$r_buff0_thd1~0_In-1937141926 256) 0))) (or (and .cse0 .cse1) (and .cse2 .cse0) (and (not .cse1) (= 0 ~y$r_buff0_thd1~0_Out-1937141926) (not .cse2)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1937141926, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In-1937141926} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1937141926, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out-1937141926|, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_Out-1937141926} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7, ~y$r_buff0_thd1~0] because there is no mapped edge [2019-11-28 18:32:58,237 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [638] [638] L756-->L756-2: Formula: (let ((.cse3 (= (mod ~y$r_buff1_thd2~0_In1278367555 256) 0)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In1278367555 256))) (.cse0 (= (mod ~y$r_buff0_thd2~0_In1278367555 256) 0)) (.cse1 (= (mod ~y$w_buff0_used~0_In1278367555 256) 0))) (or (and (= 0 |P1Thread1of1ForFork1_#t~ite12_Out1278367555|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (or .cse0 .cse1) (= ~y$w_buff1_used~0_In1278367555 |P1Thread1of1ForFork1_#t~ite12_Out1278367555|)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1278367555, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1278367555, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1278367555, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1278367555} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1278367555, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1278367555, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1278367555, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out1278367555|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1278367555} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-11-28 18:32:58,237 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [659] [659] L757-->L757-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd2~0_In420519582 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In420519582 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork1_#t~ite13_Out420519582|)) (and (= |P1Thread1of1ForFork1_#t~ite13_Out420519582| ~y$r_buff0_thd2~0_In420519582) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In420519582, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In420519582} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In420519582, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In420519582, P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out420519582|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13] because there is no mapped edge [2019-11-28 18:32:58,238 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [644] [644] L758-->L758-2: Formula: (let ((.cse2 (= 0 (mod ~y$w_buff1_used~0_In-1521563323 256))) (.cse3 (= (mod ~y$r_buff1_thd2~0_In-1521563323 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-1521563323 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In-1521563323 256)))) (or (and (or .cse0 .cse1) (= ~y$r_buff1_thd2~0_In-1521563323 |P1Thread1of1ForFork1_#t~ite14_Out-1521563323|) (or .cse2 .cse3)) (and (= |P1Thread1of1ForFork1_#t~ite14_Out-1521563323| 0) (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1)))))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1521563323, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1521563323, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1521563323, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1521563323} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1521563323, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1521563323, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1521563323, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out-1521563323|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1521563323} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-11-28 18:32:58,238 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [668] [668] L758-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_40 1) v_~__unbuffered_cnt~0_39) (= |v_P1Thread1of1ForFork1_#t~ite14_32| v_~y$r_buff1_thd2~0_85)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_40, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_32|} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_85, P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_39, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_31|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork1_#res.offset, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-11-28 18:32:58,238 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [655] [655] L738-->L738-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In470297281 256))) (.cse0 (= (mod ~y$r_buff0_thd1~0_In470297281 256) 0)) (.cse3 (= (mod ~y$r_buff1_thd1~0_In470297281 256) 0)) (.cse2 (= (mod ~y$w_buff1_used~0_In470297281 256) 0))) (or (and (= 0 |P0Thread1of1ForFork0_#t~ite8_Out470297281|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (or .cse3 .cse2) (= ~y$r_buff1_thd1~0_In470297281 |P0Thread1of1ForFork0_#t~ite8_Out470297281|)))) InVars {~y$r_buff1_thd1~0=~y$r_buff1_thd1~0_In470297281, ~y$w_buff0_used~0=~y$w_buff0_used~0_In470297281, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In470297281, ~y$w_buff1_used~0=~y$w_buff1_used~0_In470297281} OutVars{~y$r_buff1_thd1~0=~y$r_buff1_thd1~0_In470297281, ~y$w_buff0_used~0=~y$w_buff0_used~0_In470297281, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out470297281|, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In470297281, ~y$w_buff1_used~0=~y$w_buff1_used~0_In470297281} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-11-28 18:32:58,239 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [663] [663] L738-2-->P0EXIT: Formula: (and (= v_~__unbuffered_cnt~0_32 (+ v_~__unbuffered_cnt~0_33 1)) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~y$r_buff1_thd1~0_63 |v_P0Thread1of1ForFork0_#t~ite8_26|) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_26|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_33} OutVars{~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_63, P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_25|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_32} AuxVars[] AssignedVars[~y$r_buff1_thd1~0, P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-11-28 18:32:58,239 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [592] [592] L783-->L785-2: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_6 256))) (or (= (mod v_~y$w_buff0_used~0_159 256) 0) (= (mod v_~y$r_buff0_thd0~0_61 256) 0))) InVars {~y$w_buff0_used~0=v_~y$w_buff0_used~0_159, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_61, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} OutVars{~y$w_buff0_used~0=v_~y$w_buff0_used~0_159, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_61, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[] because there is no mapped edge [2019-11-28 18:32:58,239 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [654] [654] L785-2-->L785-4: Formula: (let ((.cse0 (= (mod ~y$r_buff1_thd0~0_In1111595850 256) 0)) (.cse1 (= (mod ~y$w_buff1_used~0_In1111595850 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite17_Out1111595850| ~y~0_In1111595850) (or .cse0 .cse1)) (and (= |ULTIMATE.start_main_#t~ite17_Out1111595850| ~y$w_buff1~0_In1111595850) (not .cse0) (not .cse1)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In1111595850, ~y~0=~y~0_In1111595850, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1111595850, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1111595850} OutVars{ULTIMATE.start_main_#t~ite17=|ULTIMATE.start_main_#t~ite17_Out1111595850|, ~y$w_buff1~0=~y$w_buff1~0_In1111595850, ~y~0=~y~0_In1111595850, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1111595850, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1111595850} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite17] because there is no mapped edge [2019-11-28 18:32:58,240 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [621] [621] L785-4-->L786: Formula: (= v_~y~0_46 |v_ULTIMATE.start_main_#t~ite17_8|) InVars {ULTIMATE.start_main_#t~ite17=|v_ULTIMATE.start_main_#t~ite17_8|} OutVars{ULTIMATE.start_main_#t~ite17=|v_ULTIMATE.start_main_#t~ite17_7|, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_8|, ~y~0=v_~y~0_46} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite17, ULTIMATE.start_main_#t~ite18, ~y~0] because there is no mapped edge [2019-11-28 18:32:58,240 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [647] [647] L786-->L786-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In-784309596 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In-784309596 256)))) (or (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite19_Out-784309596|) (not .cse1)) (and (or .cse0 .cse1) (= ~y$w_buff0_used~0_In-784309596 |ULTIMATE.start_main_#t~ite19_Out-784309596|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-784309596, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-784309596} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-784309596, ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out-784309596|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-784309596} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-11-28 18:32:58,240 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [641] [641] L787-->L787-2: Formula: (let ((.cse2 (= (mod ~y$w_buff1_used~0_In291869625 256) 0)) (.cse3 (= 0 (mod ~y$r_buff1_thd0~0_In291869625 256))) (.cse1 (= (mod ~y$r_buff0_thd0~0_In291869625 256) 0)) (.cse0 (= (mod ~y$w_buff0_used~0_In291869625 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite20_Out291869625|)) (and (= ~y$w_buff1_used~0_In291869625 |ULTIMATE.start_main_#t~ite20_Out291869625|) (or .cse2 .cse3) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In291869625, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In291869625, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In291869625, ~y$w_buff1_used~0=~y$w_buff1_used~0_In291869625} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In291869625, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In291869625, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out291869625|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In291869625, ~y$w_buff1_used~0=~y$w_buff1_used~0_In291869625} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-11-28 18:32:58,241 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [650] [650] L788-->L788-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In751410806 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In751410806 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite21_Out751410806| ~y$r_buff0_thd0~0_In751410806)) (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite21_Out751410806| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In751410806, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In751410806} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In751410806, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In751410806, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out751410806|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-11-28 18:32:58,242 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [642] [642] L789-->L789-2: Formula: (let ((.cse2 (= (mod ~y$w_buff0_used~0_In806292319 256) 0)) (.cse3 (= (mod ~y$r_buff0_thd0~0_In806292319 256) 0)) (.cse0 (= (mod ~y$r_buff1_thd0~0_In806292319 256) 0)) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In806292319 256)))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite22_Out806292319| ~y$r_buff1_thd0~0_In806292319) (or .cse2 .cse3)) (and (= 0 |ULTIMATE.start_main_#t~ite22_Out806292319|) (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In806292319, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In806292319, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In806292319, ~y$w_buff1_used~0=~y$w_buff1_used~0_In806292319} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In806292319, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In806292319, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In806292319, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out806292319|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In806292319} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-11-28 18:32:58,243 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [683] [683] L799-->L799-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In1051564462 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite35_Out1051564462| |ULTIMATE.start_main_#t~ite34_Out1051564462|) .cse0 (= ~y$w_buff0_used~0_In1051564462 |ULTIMATE.start_main_#t~ite34_Out1051564462|) (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In1051564462 256)))) (or (and (= 0 (mod ~y$r_buff1_thd0~0_In1051564462 256)) .cse1) (and .cse1 (= 0 (mod ~y$w_buff1_used~0_In1051564462 256))) (= (mod ~y$w_buff0_used~0_In1051564462 256) 0)))) (and (= |ULTIMATE.start_main_#t~ite35_Out1051564462| ~y$w_buff0_used~0_In1051564462) (not .cse0) (= |ULTIMATE.start_main_#t~ite34_In1051564462| |ULTIMATE.start_main_#t~ite34_Out1051564462|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1051564462, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1051564462, ~weak$$choice2~0=~weak$$choice2~0_In1051564462, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1051564462, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1051564462, ULTIMATE.start_main_#t~ite34=|ULTIMATE.start_main_#t~ite34_In1051564462|} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1051564462, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1051564462, ULTIMATE.start_main_#t~ite35=|ULTIMATE.start_main_#t~ite35_Out1051564462|, ~weak$$choice2~0=~weak$$choice2~0_In1051564462, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1051564462, ULTIMATE.start_main_#t~ite34=|ULTIMATE.start_main_#t~ite34_Out1051564462|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1051564462} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite34] because there is no mapped edge [2019-11-28 18:32:58,244 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [597] [597] L801-->L802: Formula: (and (= v_~y$r_buff0_thd0~0_72 v_~y$r_buff0_thd0~0_71) (not (= (mod v_~weak$$choice2~0_23 256) 0))) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_72, ~weak$$choice2~0=v_~weak$$choice2~0_23} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_7|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_7|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_7|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_71, ~weak$$choice2~0=v_~weak$$choice2~0_23} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~ite39, ~y$r_buff0_thd0~0] because there is no mapped edge [2019-11-28 18:32:58,245 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [676] [676] L804-->L4: Formula: (and (= v_~y~0_99 v_~y$mem_tmp~0_21) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_10| (mod v_~main$tmp_guard1~0_10 256)) (not (= 0 (mod v_~y$flush_delayed~0_36 256))) (= 0 v_~y$flush_delayed~0_35)) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_21, ~y$flush_delayed~0=v_~y$flush_delayed~0_36, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_10} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_21, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_12, ~y$flush_delayed~0=v_~y$flush_delayed~0_35, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_10, ~y~0=v_~y~0_99, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_28|, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_10|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ~y$flush_delayed~0, ~y~0, ULTIMATE.start_main_#t~ite45, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-11-28 18:32:58,246 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [671] [671] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-11-28 18:32:58,311 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 06:32:58 BasicIcfg [2019-11-28 18:32:58,311 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-28 18:32:58,312 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-28 18:32:58,312 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-28 18:32:58,313 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-28 18:32:58,313 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:32:36" (3/4) ... [2019-11-28 18:32:58,316 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-28 18:32:58,316 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [696] [696] ULTIMATE.startENTRY-->L777: Formula: (let ((.cse0 (store |v_#valid_40| 0 0))) (and (= 0 v_~y$read_delayed_var~0.base_6) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t2481~0.base_19| 4)) (= 0 |v_ULTIMATE.start_main_~#t2481~0.offset_16|) (= 0 v_~__unbuffered_cnt~0_61) (= v_~weak$$choice2~0_132 0) (= |v_#NULL.offset_6| 0) (= v_~y$read_delayed~0_7 0) (= v_~y$w_buff1_used~0_444 0) (= v_~y$r_buff1_thd0~0_304 0) (= v_~main$tmp_guard0~0_23 0) (= v_~y$r_buff0_thd0~0_394 0) (= (select .cse0 |v_ULTIMATE.start_main_~#t2481~0.base_19|) 0) (= 0 v_~y$w_buff0~0_376) (= 0 |v_#NULL.base_6|) (< |v_#StackHeapBarrier_13| |v_ULTIMATE.start_main_~#t2481~0.base_19|) (= v_~y$r_buff1_thd1~0_220 0) (= v_~y~0_141 0) (= v_~y$r_buff0_thd1~0_301 0) (= 0 v_~weak$$choice0~0_24) (= 0 v_~y$flush_delayed~0_48) (= 0 v_~y$r_buff0_thd2~0_175) (= v_~y$w_buff1~0_254 0) (= |v_#valid_38| (store .cse0 |v_ULTIMATE.start_main_~#t2481~0.base_19| 1)) (= v_~y$mem_tmp~0_31 0) (= v_~y$w_buff0_used~0_753 0) (= 0 v_~y$read_delayed_var~0.offset_6) (= 0 v_~y$r_buff1_thd2~0_205) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t2481~0.base_19| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t2481~0.base_19|) |v_ULTIMATE.start_main_~#t2481~0.offset_16| 0)) |v_#memory_int_15|) (= 0 v_~x~0_168) (< 0 |v_#StackHeapBarrier_13|) (= v_~main$tmp_guard1~0_22 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_40|, #memory_int=|v_#memory_int_16|, #length=|v_#length_16|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_45|, #NULL.offset=|v_#NULL.offset_6|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_32|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_32|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_42|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_56|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_35|, ~y$read_delayed~0=v_~y$read_delayed~0_7, ULTIMATE.start_main_~#t2481~0.offset=|v_ULTIMATE.start_main_~#t2481~0.offset_16|, ~y$mem_tmp~0=v_~y$mem_tmp~0_31, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_301, ~y$flush_delayed~0=v_~y$flush_delayed~0_48, ULTIMATE.start_main_~#t2482~0.base=|v_ULTIMATE.start_main_~#t2482~0.base_19|, #length=|v_#length_15|, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_29|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_32|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_44|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_35|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_51|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_45|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_31|, ~weak$$choice0~0=v_~weak$$choice0~0_24, #StackHeapBarrier=|v_#StackHeapBarrier_13|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_30|, ~y$w_buff1~0=v_~y$w_buff1~0_254, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_6, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_175, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_8|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_61, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_304, ~x~0=v_~x~0_168, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_6, ULTIMATE.start_main_~#t2482~0.offset=|v_ULTIMATE.start_main_~#t2482~0.offset_15|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_753, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_28|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_28|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_22, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_43|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_28|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_46|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_28|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_220, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_39|, ~y$w_buff0~0=v_~y$w_buff0~0_376, ~y~0=v_~y~0_141, ULTIMATE.start_main_#t~ite17=|v_ULTIMATE.start_main_#t~ite17_30|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_44|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_26|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_37|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_29|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_23, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_28|, #NULL.base=|v_#NULL.base_6|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_39|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_205, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_16|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_15|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_394, #valid=|v_#valid_38|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_13|, ~weak$$choice2~0=v_~weak$$choice2~0_132, ULTIMATE.start_main_~#t2481~0.base=|v_ULTIMATE.start_main_~#t2481~0.base_19|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_444} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~y$read_delayed~0, ULTIMATE.start_main_~#t2481~0.offset, ~y$mem_tmp~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, ULTIMATE.start_main_~#t2482~0.base, #length, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ~y$read_delayed_var~0.offset, ULTIMATE.start_main_~#t2482~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ~y$w_buff0~0, ~y~0, ULTIMATE.start_main_#t~ite17, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ~weak$$choice2~0, ULTIMATE.start_main_~#t2481~0.base, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:32:58,317 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [677] [677] L777-1-->L779: Formula: (and (not (= |v_ULTIMATE.start_main_~#t2482~0.base_11| 0)) (= |v_#memory_int_9| (store |v_#memory_int_10| |v_ULTIMATE.start_main_~#t2482~0.base_11| (store (select |v_#memory_int_10| |v_ULTIMATE.start_main_~#t2482~0.base_11|) |v_ULTIMATE.start_main_~#t2482~0.offset_10| 1))) (< |v_#StackHeapBarrier_8| |v_ULTIMATE.start_main_~#t2482~0.base_11|) (= |v_#valid_21| (store |v_#valid_22| |v_ULTIMATE.start_main_~#t2482~0.base_11| 1)) (= 0 |v_ULTIMATE.start_main_~#t2482~0.offset_10|) (= (store |v_#length_10| |v_ULTIMATE.start_main_~#t2482~0.base_11| 4) |v_#length_9|) (= 0 (select |v_#valid_22| |v_ULTIMATE.start_main_~#t2482~0.base_11|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_8|, #valid=|v_#valid_22|, #memory_int=|v_#memory_int_10|, #length=|v_#length_10|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_8|, ULTIMATE.start_main_~#t2482~0.offset=|v_ULTIMATE.start_main_~#t2482~0.offset_10|, #valid=|v_#valid_21|, #memory_int=|v_#memory_int_9|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, ULTIMATE.start_main_~#t2482~0.base=|v_ULTIMATE.start_main_~#t2482~0.base_11|, #length=|v_#length_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2482~0.offset, #valid, #memory_int, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_~#t2482~0.base, #length] because there is no mapped edge [2019-11-28 18:32:58,317 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [623] [623] P0ENTRY-->L4-3: Formula: (and (= 2 v_~y$w_buff0~0_172) (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_79 0)) (= (ite (not (and (not (= (mod v_~y$w_buff0_used~0_290 256) 0)) (not (= 0 (mod v_~y$w_buff1_used~0_162 256))))) 1 0) |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_77|) (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_79 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_77|) (= v_~y$w_buff0_used~0_290 1) (= v_P0Thread1of1ForFork0_~arg.offset_77 |v_P0Thread1of1ForFork0_#in~arg.offset_79|) (= v_P0Thread1of1ForFork0_~arg.base_77 |v_P0Thread1of1ForFork0_#in~arg.base_79|) (= v_~y$w_buff0_used~0_291 v_~y$w_buff1_used~0_162) (= v_~y$w_buff1~0_100 v_~y$w_buff0~0_173)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_79|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_291, ~y$w_buff0~0=v_~y$w_buff0~0_173, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_79|} OutVars{P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_79|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_290, ~y$w_buff1~0=v_~y$w_buff1~0_100, ~y$w_buff0~0=v_~y$w_buff0~0_172, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_79, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_79|, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_77, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_77|, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_77, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_162} AuxVars[] AssignedVars[~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P0Thread1of1ForFork0___VERIFIER_assert_~expression, P0Thread1of1ForFork0_~arg.base, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression, P0Thread1of1ForFork0_~arg.offset, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:32:58,318 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [656] [656] L735-->L735-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd1~0_In-1575932751 256))) (.cse0 (= (mod ~y$w_buff0_used~0_In-1575932751 256) 0))) (or (and (not .cse0) (not .cse1) (= |P0Thread1of1ForFork0_#t~ite5_Out-1575932751| 0)) (and (or .cse1 .cse0) (= |P0Thread1of1ForFork0_#t~ite5_Out-1575932751| ~y$w_buff0_used~0_In-1575932751)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1575932751, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In-1575932751} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out-1575932751|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1575932751, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In-1575932751} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-11-28 18:32:58,319 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [648] [648] L754-2-->L754-4: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff1_used~0_In-330043530 256))) (.cse1 (= (mod ~y$r_buff1_thd2~0_In-330043530 256) 0))) (or (and (= ~y~0_In-330043530 |P1Thread1of1ForFork1_#t~ite9_Out-330043530|) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= ~y$w_buff1~0_In-330043530 |P1Thread1of1ForFork1_#t~ite9_Out-330043530|)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-330043530, ~y$w_buff1~0=~y$w_buff1~0_In-330043530, ~y~0=~y~0_In-330043530, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-330043530} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-330043530, ~y$w_buff1~0=~y$w_buff1~0_In-330043530, P1Thread1of1ForFork1_#t~ite9=|P1Thread1of1ForFork1_#t~ite9_Out-330043530|, ~y~0=~y~0_In-330043530, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-330043530} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9] because there is no mapped edge [2019-11-28 18:32:58,319 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [630] [630] L754-4-->L755: Formula: (= v_~y~0_50 |v_P1Thread1of1ForFork1_#t~ite9_12|) InVars {P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_12|} OutVars{P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_11|, P1Thread1of1ForFork1_#t~ite10=|v_P1Thread1of1ForFork1_#t~ite10_13|, ~y~0=v_~y~0_50} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9, P1Thread1of1ForFork1_#t~ite10, ~y~0] because there is no mapped edge [2019-11-28 18:32:58,320 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [640] [640] L755-->L755-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In502986957 256))) (.cse0 (= (mod ~y$w_buff0_used~0_In502986957 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork1_#t~ite11_Out502986957|)) (and (= ~y$w_buff0_used~0_In502986957 |P1Thread1of1ForFork1_#t~ite11_Out502986957|) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In502986957, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In502986957} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In502986957, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In502986957, P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out502986957|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-11-28 18:32:58,320 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [657] [657] L736-->L736-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In439924727 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd1~0_In439924727 256))) (.cse2 (= 0 (mod ~y$r_buff1_thd1~0_In439924727 256))) (.cse3 (= 0 (mod ~y$w_buff1_used~0_In439924727 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P0Thread1of1ForFork0_#t~ite6_Out439924727| 0)) (and (or .cse1 .cse0) (= |P0Thread1of1ForFork0_#t~ite6_Out439924727| ~y$w_buff1_used~0_In439924727) (or .cse2 .cse3)))) InVars {~y$r_buff1_thd1~0=~y$r_buff1_thd1~0_In439924727, ~y$w_buff0_used~0=~y$w_buff0_used~0_In439924727, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In439924727, ~y$w_buff1_used~0=~y$w_buff1_used~0_In439924727} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out439924727|, ~y$r_buff1_thd1~0=~y$r_buff1_thd1~0_In439924727, ~y$w_buff0_used~0=~y$w_buff0_used~0_In439924727, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In439924727, ~y$w_buff1_used~0=~y$w_buff1_used~0_In439924727} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-11-28 18:32:58,321 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [643] [643] L737-->L738: Formula: (let ((.cse0 (= ~y$r_buff0_thd1~0_In-1937141926 ~y$r_buff0_thd1~0_Out-1937141926)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1937141926 256))) (.cse2 (= (mod ~y$r_buff0_thd1~0_In-1937141926 256) 0))) (or (and .cse0 .cse1) (and .cse2 .cse0) (and (not .cse1) (= 0 ~y$r_buff0_thd1~0_Out-1937141926) (not .cse2)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1937141926, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In-1937141926} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1937141926, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out-1937141926|, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_Out-1937141926} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7, ~y$r_buff0_thd1~0] because there is no mapped edge [2019-11-28 18:32:58,321 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [638] [638] L756-->L756-2: Formula: (let ((.cse3 (= (mod ~y$r_buff1_thd2~0_In1278367555 256) 0)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In1278367555 256))) (.cse0 (= (mod ~y$r_buff0_thd2~0_In1278367555 256) 0)) (.cse1 (= (mod ~y$w_buff0_used~0_In1278367555 256) 0))) (or (and (= 0 |P1Thread1of1ForFork1_#t~ite12_Out1278367555|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (or .cse0 .cse1) (= ~y$w_buff1_used~0_In1278367555 |P1Thread1of1ForFork1_#t~ite12_Out1278367555|)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1278367555, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1278367555, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1278367555, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1278367555} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1278367555, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1278367555, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1278367555, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out1278367555|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1278367555} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-11-28 18:32:58,322 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [659] [659] L757-->L757-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd2~0_In420519582 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In420519582 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork1_#t~ite13_Out420519582|)) (and (= |P1Thread1of1ForFork1_#t~ite13_Out420519582| ~y$r_buff0_thd2~0_In420519582) (or .cse0 .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In420519582, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In420519582} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In420519582, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In420519582, P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out420519582|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13] because there is no mapped edge [2019-11-28 18:32:58,322 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [644] [644] L758-->L758-2: Formula: (let ((.cse2 (= 0 (mod ~y$w_buff1_used~0_In-1521563323 256))) (.cse3 (= (mod ~y$r_buff1_thd2~0_In-1521563323 256) 0)) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-1521563323 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In-1521563323 256)))) (or (and (or .cse0 .cse1) (= ~y$r_buff1_thd2~0_In-1521563323 |P1Thread1of1ForFork1_#t~ite14_Out-1521563323|) (or .cse2 .cse3)) (and (= |P1Thread1of1ForFork1_#t~ite14_Out-1521563323| 0) (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1)))))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1521563323, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1521563323, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1521563323, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1521563323} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1521563323, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1521563323, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1521563323, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out-1521563323|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1521563323} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-11-28 18:32:58,322 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [668] [668] L758-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_40 1) v_~__unbuffered_cnt~0_39) (= |v_P1Thread1of1ForFork1_#t~ite14_32| v_~y$r_buff1_thd2~0_85)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_40, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_32|} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_85, P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_39, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_31|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork1_#res.offset, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-11-28 18:32:58,323 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [655] [655] L738-->L738-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In470297281 256))) (.cse0 (= (mod ~y$r_buff0_thd1~0_In470297281 256) 0)) (.cse3 (= (mod ~y$r_buff1_thd1~0_In470297281 256) 0)) (.cse2 (= (mod ~y$w_buff1_used~0_In470297281 256) 0))) (or (and (= 0 |P0Thread1of1ForFork0_#t~ite8_Out470297281|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (or .cse3 .cse2) (= ~y$r_buff1_thd1~0_In470297281 |P0Thread1of1ForFork0_#t~ite8_Out470297281|)))) InVars {~y$r_buff1_thd1~0=~y$r_buff1_thd1~0_In470297281, ~y$w_buff0_used~0=~y$w_buff0_used~0_In470297281, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In470297281, ~y$w_buff1_used~0=~y$w_buff1_used~0_In470297281} OutVars{~y$r_buff1_thd1~0=~y$r_buff1_thd1~0_In470297281, ~y$w_buff0_used~0=~y$w_buff0_used~0_In470297281, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out470297281|, ~y$r_buff0_thd1~0=~y$r_buff0_thd1~0_In470297281, ~y$w_buff1_used~0=~y$w_buff1_used~0_In470297281} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-11-28 18:32:58,323 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [663] [663] L738-2-->P0EXIT: Formula: (and (= v_~__unbuffered_cnt~0_32 (+ v_~__unbuffered_cnt~0_33 1)) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~y$r_buff1_thd1~0_63 |v_P0Thread1of1ForFork0_#t~ite8_26|) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_26|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_33} OutVars{~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_63, P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_25|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_32} AuxVars[] AssignedVars[~y$r_buff1_thd1~0, P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-11-28 18:32:58,323 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [592] [592] L783-->L785-2: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_6 256))) (or (= (mod v_~y$w_buff0_used~0_159 256) 0) (= (mod v_~y$r_buff0_thd0~0_61 256) 0))) InVars {~y$w_buff0_used~0=v_~y$w_buff0_used~0_159, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_61, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} OutVars{~y$w_buff0_used~0=v_~y$w_buff0_used~0_159, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_61, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[] because there is no mapped edge [2019-11-28 18:32:58,324 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [654] [654] L785-2-->L785-4: Formula: (let ((.cse0 (= (mod ~y$r_buff1_thd0~0_In1111595850 256) 0)) (.cse1 (= (mod ~y$w_buff1_used~0_In1111595850 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite17_Out1111595850| ~y~0_In1111595850) (or .cse0 .cse1)) (and (= |ULTIMATE.start_main_#t~ite17_Out1111595850| ~y$w_buff1~0_In1111595850) (not .cse0) (not .cse1)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In1111595850, ~y~0=~y~0_In1111595850, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1111595850, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1111595850} OutVars{ULTIMATE.start_main_#t~ite17=|ULTIMATE.start_main_#t~ite17_Out1111595850|, ~y$w_buff1~0=~y$w_buff1~0_In1111595850, ~y~0=~y~0_In1111595850, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1111595850, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1111595850} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite17] because there is no mapped edge [2019-11-28 18:32:58,324 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [621] [621] L785-4-->L786: Formula: (= v_~y~0_46 |v_ULTIMATE.start_main_#t~ite17_8|) InVars {ULTIMATE.start_main_#t~ite17=|v_ULTIMATE.start_main_#t~ite17_8|} OutVars{ULTIMATE.start_main_#t~ite17=|v_ULTIMATE.start_main_#t~ite17_7|, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_8|, ~y~0=v_~y~0_46} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite17, ULTIMATE.start_main_#t~ite18, ~y~0] because there is no mapped edge [2019-11-28 18:32:58,324 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [647] [647] L786-->L786-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In-784309596 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In-784309596 256)))) (or (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite19_Out-784309596|) (not .cse1)) (and (or .cse0 .cse1) (= ~y$w_buff0_used~0_In-784309596 |ULTIMATE.start_main_#t~ite19_Out-784309596|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-784309596, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-784309596} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-784309596, ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out-784309596|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-784309596} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-11-28 18:32:58,325 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [641] [641] L787-->L787-2: Formula: (let ((.cse2 (= (mod ~y$w_buff1_used~0_In291869625 256) 0)) (.cse3 (= 0 (mod ~y$r_buff1_thd0~0_In291869625 256))) (.cse1 (= (mod ~y$r_buff0_thd0~0_In291869625 256) 0)) (.cse0 (= (mod ~y$w_buff0_used~0_In291869625 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite20_Out291869625|)) (and (= ~y$w_buff1_used~0_In291869625 |ULTIMATE.start_main_#t~ite20_Out291869625|) (or .cse2 .cse3) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In291869625, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In291869625, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In291869625, ~y$w_buff1_used~0=~y$w_buff1_used~0_In291869625} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In291869625, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In291869625, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out291869625|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In291869625, ~y$w_buff1_used~0=~y$w_buff1_used~0_In291869625} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-11-28 18:32:58,325 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [650] [650] L788-->L788-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In751410806 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In751410806 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite21_Out751410806| ~y$r_buff0_thd0~0_In751410806)) (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite21_Out751410806| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In751410806, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In751410806} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In751410806, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In751410806, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out751410806|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-11-28 18:32:58,326 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [642] [642] L789-->L789-2: Formula: (let ((.cse2 (= (mod ~y$w_buff0_used~0_In806292319 256) 0)) (.cse3 (= (mod ~y$r_buff0_thd0~0_In806292319 256) 0)) (.cse0 (= (mod ~y$r_buff1_thd0~0_In806292319 256) 0)) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In806292319 256)))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite22_Out806292319| ~y$r_buff1_thd0~0_In806292319) (or .cse2 .cse3)) (and (= 0 |ULTIMATE.start_main_#t~ite22_Out806292319|) (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In806292319, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In806292319, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In806292319, ~y$w_buff1_used~0=~y$w_buff1_used~0_In806292319} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In806292319, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In806292319, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In806292319, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out806292319|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In806292319} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-11-28 18:32:58,328 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [683] [683] L799-->L799-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In1051564462 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite35_Out1051564462| |ULTIMATE.start_main_#t~ite34_Out1051564462|) .cse0 (= ~y$w_buff0_used~0_In1051564462 |ULTIMATE.start_main_#t~ite34_Out1051564462|) (let ((.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In1051564462 256)))) (or (and (= 0 (mod ~y$r_buff1_thd0~0_In1051564462 256)) .cse1) (and .cse1 (= 0 (mod ~y$w_buff1_used~0_In1051564462 256))) (= (mod ~y$w_buff0_used~0_In1051564462 256) 0)))) (and (= |ULTIMATE.start_main_#t~ite35_Out1051564462| ~y$w_buff0_used~0_In1051564462) (not .cse0) (= |ULTIMATE.start_main_#t~ite34_In1051564462| |ULTIMATE.start_main_#t~ite34_Out1051564462|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1051564462, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1051564462, ~weak$$choice2~0=~weak$$choice2~0_In1051564462, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1051564462, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1051564462, ULTIMATE.start_main_#t~ite34=|ULTIMATE.start_main_#t~ite34_In1051564462|} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1051564462, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1051564462, ULTIMATE.start_main_#t~ite35=|ULTIMATE.start_main_#t~ite35_Out1051564462|, ~weak$$choice2~0=~weak$$choice2~0_In1051564462, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1051564462, ULTIMATE.start_main_#t~ite34=|ULTIMATE.start_main_#t~ite34_Out1051564462|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1051564462} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite34] because there is no mapped edge [2019-11-28 18:32:58,329 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [597] [597] L801-->L802: Formula: (and (= v_~y$r_buff0_thd0~0_72 v_~y$r_buff0_thd0~0_71) (not (= (mod v_~weak$$choice2~0_23 256) 0))) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_72, ~weak$$choice2~0=v_~weak$$choice2~0_23} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_7|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_7|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_7|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_71, ~weak$$choice2~0=v_~weak$$choice2~0_23} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~ite39, ~y$r_buff0_thd0~0] because there is no mapped edge [2019-11-28 18:32:58,330 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [676] [676] L804-->L4: Formula: (and (= v_~y~0_99 v_~y$mem_tmp~0_21) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_10| (mod v_~main$tmp_guard1~0_10 256)) (not (= 0 (mod v_~y$flush_delayed~0_36 256))) (= 0 v_~y$flush_delayed~0_35)) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_21, ~y$flush_delayed~0=v_~y$flush_delayed~0_36, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_10} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_21, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_12, ~y$flush_delayed~0=v_~y$flush_delayed~0_35, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_10, ~y~0=v_~y~0_99, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_28|, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_10|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ~y$flush_delayed~0, ~y~0, ULTIMATE.start_main_#t~ite45, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-11-28 18:32:58,330 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [671] [671] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-11-28 18:32:58,413 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2019-11-28 18:32:58,414 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-28 18:32:58,415 INFO L168 Benchmark]: Toolchain (without parser) took 24020.41 ms. Allocated memory was 1.0 GB in the beginning and 2.0 GB in the end (delta: 954.7 MB). Free memory was 952.3 MB in the beginning and 1.0 GB in the end (delta: -77.5 MB). Peak memory consumption was 877.2 MB. Max. memory is 11.5 GB. [2019-11-28 18:32:58,416 INFO L168 Benchmark]: CDTParser took 0.32 ms. Allocated memory is still 1.0 GB. Free memory is still 987.2 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 18:32:58,417 INFO L168 Benchmark]: CACSL2BoogieTranslator took 772.61 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 143.7 MB). Free memory was 952.3 MB in the beginning and 1.1 GB in the end (delta: -153.1 MB). Peak memory consumption was 20.9 MB. Max. memory is 11.5 GB. [2019-11-28 18:32:58,417 INFO L168 Benchmark]: Boogie Procedure Inliner took 68.76 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.6 MB). Peak memory consumption was 6.6 MB. Max. memory is 11.5 GB. [2019-11-28 18:32:58,417 INFO L168 Benchmark]: Boogie Preprocessor took 67.81 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 18:32:58,418 INFO L168 Benchmark]: RCFGBuilder took 777.49 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 44.0 MB). Peak memory consumption was 44.0 MB. Max. memory is 11.5 GB. [2019-11-28 18:32:58,419 INFO L168 Benchmark]: TraceAbstraction took 22226.46 ms. Allocated memory was 1.2 GB in the beginning and 2.0 GB in the end (delta: 811.1 MB). Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 5.1 MB). Peak memory consumption was 816.2 MB. Max. memory is 11.5 GB. [2019-11-28 18:32:58,419 INFO L168 Benchmark]: Witness Printer took 101.69 ms. Allocated memory is still 2.0 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 19.8 MB). Peak memory consumption was 19.8 MB. Max. memory is 11.5 GB. [2019-11-28 18:32:58,424 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.32 ms. Allocated memory is still 1.0 GB. Free memory is still 987.2 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 772.61 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 143.7 MB). Free memory was 952.3 MB in the beginning and 1.1 GB in the end (delta: -153.1 MB). Peak memory consumption was 20.9 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 68.76 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.6 MB). Peak memory consumption was 6.6 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 67.81 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 777.49 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 44.0 MB). Peak memory consumption was 44.0 MB. Max. memory is 11.5 GB. * TraceAbstraction took 22226.46 ms. Allocated memory was 1.2 GB in the beginning and 2.0 GB in the end (delta: 811.1 MB). Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 5.1 MB). Peak memory consumption was 816.2 MB. Max. memory is 11.5 GB. * Witness Printer took 101.69 ms. Allocated memory is still 2.0 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 19.8 MB). Peak memory consumption was 19.8 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 4.8s, 145 ProgramPointsBefore, 78 ProgramPointsAfterwards, 179 TransitionsBefore, 90 TransitionsAfterwards, 10418 CoEnabledTransitionPairs, 7 FixpointIterations, 27 TrivialSequentialCompositions, 38 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 32 ConcurrentYvCompositions, 25 ChoiceCompositions, 3579 VarBasedMoverChecksPositive, 213 VarBasedMoverChecksNegative, 67 SemBasedMoverChecksPositive, 198 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 1.4s, 0 MoverChecksTotal, 46212 CheckedPairsTotal, 97 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L777] FCALL, FORK 0 pthread_create(&t2481, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0] [L779] FCALL, FORK 0 pthread_create(&t2482, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0] [L725] 1 y$r_buff1_thd0 = y$r_buff0_thd0 [L726] 1 y$r_buff1_thd1 = y$r_buff0_thd1 [L727] 1 y$r_buff1_thd2 = y$r_buff0_thd2 [L728] 1 y$r_buff0_thd1 = (_Bool)1 [L731] 1 x = 1 VAL [__unbuffered_cnt=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0] [L734] EXPR 1 y$w_buff0_used && y$r_buff0_thd1 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd1 ? y$w_buff1 : y) VAL [__unbuffered_cnt=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0] [L748] 2 x = 2 [L751] 2 y = 1 VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0] [L734] 1 y = y$w_buff0_used && y$r_buff0_thd1 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd1 ? y$w_buff1 : y) [L754] 2 y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) VAL [__unbuffered_cnt=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0] [L735] 1 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd1 ? (_Bool)0 : y$w_buff0_used [L736] 1 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd1 || y$w_buff1_used && y$r_buff1_thd1 ? (_Bool)0 : y$w_buff1_used [L755] 2 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$w_buff0_used [L756] 2 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used [L757] 2 y$r_buff0_thd2 = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$r_buff0_thd2 [L781] 0 main$tmp_guard0 = __unbuffered_cnt == 2 VAL [\result={0:0}, __unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0] [L786] 0 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used [L787] 0 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$w_buff1_used [L788] 0 y$r_buff0_thd0 = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$r_buff0_thd0 [L789] 0 y$r_buff1_thd0 = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$r_buff1_thd0 [L792] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L793] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L794] 0 y$flush_delayed = weak$$choice2 [L795] 0 y$mem_tmp = y VAL [\result={0:0}, __unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=6, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0] [L796] EXPR 0 !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) VAL [\result={0:0}, __unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=6, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0] [L796] 0 y = !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) [L797] EXPR 0 weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) VAL [\result={0:0}, __unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=6, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0] [L797] 0 y$w_buff0 = weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) [L798] EXPR 0 weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) VAL [\result={0:0}, __unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=6, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0] [L798] 0 y$w_buff1 = weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) [L799] 0 y$w_buff0_used = weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) [L800] EXPR 0 weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, __unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=6, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0] [L800] 0 y$w_buff1_used = weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L802] EXPR 0 weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, __unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=6, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0] [L802] 0 y$r_buff1_thd0 = weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L803] 0 main$tmp_guard1 = !(x == 2 && y == 2) VAL [\result={0:0}, __unbuffered_cnt=2, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=6, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=1, y$r_buff0_thd2=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 3 procedures, 139 locations, 2 error locations. Result: UNSAFE, OverallTime: 22.0s, OverallIterations: 22, TraceHistogramMax: 1, AutomataDifference: 8.8s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 2627 SDtfs, 2742 SDslu, 7572 SDs, 0 SdLazy, 5463 SolverSat, 265 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 5.2s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 248 GetRequests, 35 SyntacticMatches, 18 SemanticMatches, 195 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 560 ImplicationChecksByTransitivity, 3.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=15905occurred in iteration=6, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 3.2s AutomataMinimizationTime, 21 MinimizatonAttempts, 15352 StatesRemovedByMinimization, 18 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.5s SatisfiabilityAnalysisTime, 3.1s InterpolantComputationTime, 871 NumberOfCodeBlocks, 871 NumberOfCodeBlocksAsserted, 22 NumberOfCheckSat, 796 ConstructedInterpolants, 0 QuantifiedInterpolants, 151621 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 21 InterpolantComputations, 21 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...