./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/pthread-wmm/safe031_power.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx12G -Xms1G -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/pthread-wmm/safe031_power.opt.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash b4d1a2938d6ae8a9b01acdb4953c59ea95e54f7d ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-11-28 18:32:56,688 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-28 18:32:56,691 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-28 18:32:56,711 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-28 18:32:56,711 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-28 18:32:56,714 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-28 18:32:56,717 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-28 18:32:56,727 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-28 18:32:56,732 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-28 18:32:56,736 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-28 18:32:56,738 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-28 18:32:56,740 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-28 18:32:56,741 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-28 18:32:56,743 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-28 18:32:56,745 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-28 18:32:56,747 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-28 18:32:56,748 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-28 18:32:56,750 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-28 18:32:56,753 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-28 18:32:56,757 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-28 18:32:56,762 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-28 18:32:56,768 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-28 18:32:56,769 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-28 18:32:56,771 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-28 18:32:56,774 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-28 18:32:56,774 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-28 18:32:56,774 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-28 18:32:56,776 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-28 18:32:56,777 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-28 18:32:56,778 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-28 18:32:56,778 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-28 18:32:56,779 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-28 18:32:56,780 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-28 18:32:56,782 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-28 18:32:56,783 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-28 18:32:56,783 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-28 18:32:56,784 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-28 18:32:56,785 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-28 18:32:56,785 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-28 18:32:56,786 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-28 18:32:56,787 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-28 18:32:56,788 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-28 18:32:56,822 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-28 18:32:56,826 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-28 18:32:56,827 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-28 18:32:56,828 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-28 18:32:56,831 INFO L138 SettingsManager]: * Use SBE=true [2019-11-28 18:32:56,831 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-28 18:32:56,831 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-28 18:32:56,832 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-28 18:32:56,832 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-28 18:32:56,832 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-28 18:32:56,833 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-28 18:32:56,833 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-28 18:32:56,833 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-28 18:32:56,833 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-28 18:32:56,835 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-28 18:32:56,835 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-28 18:32:56,835 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-28 18:32:56,836 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-28 18:32:56,836 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-28 18:32:56,836 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-28 18:32:56,836 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-28 18:32:56,837 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 18:32:56,837 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-28 18:32:56,838 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-28 18:32:56,838 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-28 18:32:56,838 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-28 18:32:56,838 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-28 18:32:56,839 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-28 18:32:56,839 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-11-28 18:32:56,839 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> b4d1a2938d6ae8a9b01acdb4953c59ea95e54f7d [2019-11-28 18:32:57,151 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-28 18:32:57,170 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-28 18:32:57,173 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-28 18:32:57,175 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-28 18:32:57,176 INFO L275 PluginConnector]: CDTParser initialized [2019-11-28 18:32:57,177 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/pthread-wmm/safe031_power.opt.i [2019-11-28 18:32:57,248 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7868738d9/ae2c6e93580e472593fef2d3e82d27ec/FLAGbac9b7e1a [2019-11-28 18:32:57,858 INFO L306 CDTParser]: Found 1 translation units. [2019-11-28 18:32:57,859 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/pthread-wmm/safe031_power.opt.i [2019-11-28 18:32:57,887 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7868738d9/ae2c6e93580e472593fef2d3e82d27ec/FLAGbac9b7e1a [2019-11-28 18:32:58,095 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7868738d9/ae2c6e93580e472593fef2d3e82d27ec [2019-11-28 18:32:58,099 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-28 18:32:58,100 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-28 18:32:58,101 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-28 18:32:58,101 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-28 18:32:58,106 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-28 18:32:58,107 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 06:32:58" (1/1) ... [2019-11-28 18:32:58,110 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@553315ca and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:32:58, skipping insertion in model container [2019-11-28 18:32:58,110 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 06:32:58" (1/1) ... [2019-11-28 18:32:58,119 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-11-28 18:32:58,177 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-11-28 18:32:58,684 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 18:32:58,703 INFO L203 MainTranslator]: Completed pre-run [2019-11-28 18:32:58,769 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 18:32:58,844 INFO L208 MainTranslator]: Completed translation [2019-11-28 18:32:58,844 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:32:58 WrapperNode [2019-11-28 18:32:58,845 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-28 18:32:58,846 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-28 18:32:58,846 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-28 18:32:58,846 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-28 18:32:58,855 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:32:58" (1/1) ... [2019-11-28 18:32:58,874 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:32:58" (1/1) ... [2019-11-28 18:32:58,919 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-28 18:32:58,919 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-28 18:32:58,920 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-28 18:32:58,920 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-28 18:32:58,930 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:32:58" (1/1) ... [2019-11-28 18:32:58,930 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:32:58" (1/1) ... [2019-11-28 18:32:58,935 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:32:58" (1/1) ... [2019-11-28 18:32:58,935 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:32:58" (1/1) ... [2019-11-28 18:32:58,946 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:32:58" (1/1) ... [2019-11-28 18:32:58,951 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:32:58" (1/1) ... [2019-11-28 18:32:58,957 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:32:58" (1/1) ... [2019-11-28 18:32:58,962 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-28 18:32:58,963 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-28 18:32:58,963 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-28 18:32:58,963 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-28 18:32:58,964 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:32:58" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 18:32:59,029 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-11-28 18:32:59,029 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-11-28 18:32:59,029 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-11-28 18:32:59,029 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-11-28 18:32:59,030 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-11-28 18:32:59,031 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-11-28 18:32:59,031 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-11-28 18:32:59,031 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-11-28 18:32:59,031 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-11-28 18:32:59,032 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-11-28 18:32:59,033 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-11-28 18:32:59,033 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-28 18:32:59,033 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-28 18:32:59,035 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-11-28 18:32:59,693 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-28 18:32:59,693 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-11-28 18:32:59,695 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:32:59 BoogieIcfgContainer [2019-11-28 18:32:59,695 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-28 18:32:59,697 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-28 18:32:59,697 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-28 18:32:59,700 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-28 18:32:59,701 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 06:32:58" (1/3) ... [2019-11-28 18:32:59,702 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7abe24ff and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 06:32:59, skipping insertion in model container [2019-11-28 18:32:59,702 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:32:58" (2/3) ... [2019-11-28 18:32:59,703 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7abe24ff and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 06:32:59, skipping insertion in model container [2019-11-28 18:32:59,703 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:32:59" (3/3) ... [2019-11-28 18:32:59,705 INFO L109 eAbstractionObserver]: Analyzing ICFG safe031_power.opt.i [2019-11-28 18:32:59,716 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-11-28 18:32:59,717 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-28 18:32:59,725 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-11-28 18:32:59,726 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-11-28 18:32:59,763 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,764 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,764 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,765 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,765 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,765 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,766 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,766 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,767 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,767 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,767 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,768 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,768 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,768 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,769 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,769 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,769 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,770 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,770 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,770 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,771 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,771 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,771 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,772 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,772 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,772 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,773 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,773 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,773 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,774 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,774 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,775 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,775 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,775 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,776 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,776 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,777 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,777 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,778 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,778 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,778 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,778 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,779 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,779 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,780 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,780 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,780 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,781 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,781 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,781 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,782 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,782 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,782 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,783 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,783 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,783 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,784 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,784 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,784 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,785 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,785 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,785 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,786 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,786 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,786 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,787 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,787 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,787 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,787 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,788 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:32:59,807 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-11-28 18:32:59,830 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-28 18:32:59,831 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-28 18:32:59,831 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-28 18:32:59,831 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-28 18:32:59,832 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-28 18:32:59,832 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-28 18:32:59,832 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-28 18:32:59,832 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-28 18:32:59,851 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 162 places, 193 transitions [2019-11-28 18:32:59,853 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 162 places, 193 transitions [2019-11-28 18:32:59,942 INFO L134 PetriNetUnfolder]: 41/190 cut-off events. [2019-11-28 18:32:59,942 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-11-28 18:32:59,964 INFO L76 FinitePrefix]: Finished finitePrefix Result has 200 conditions, 190 events. 41/190 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 476 event pairs. 9/156 useless extension candidates. Maximal degree in co-relation 161. Up to 2 conditions per place. [2019-11-28 18:32:59,993 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 162 places, 193 transitions [2019-11-28 18:33:00,048 INFO L134 PetriNetUnfolder]: 41/190 cut-off events. [2019-11-28 18:33:00,049 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-11-28 18:33:00,061 INFO L76 FinitePrefix]: Finished finitePrefix Result has 200 conditions, 190 events. 41/190 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 476 event pairs. 9/156 useless extension candidates. Maximal degree in co-relation 161. Up to 2 conditions per place. [2019-11-28 18:33:00,086 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 11490 [2019-11-28 18:33:00,087 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-11-28 18:33:04,825 WARN L192 SmtUtils]: Spent 318.00 ms on a formula simplification. DAG size of input: 87 DAG size of output: 85 [2019-11-28 18:33:04,938 WARN L192 SmtUtils]: Spent 110.00 ms on a formula simplification that was a NOOP. DAG size: 83 [2019-11-28 18:33:04,958 INFO L206 etLargeBlockEncoding]: Checked pairs total: 48124 [2019-11-28 18:33:04,959 INFO L214 etLargeBlockEncoding]: Total number of compositions: 111 [2019-11-28 18:33:04,963 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 83 places, 94 transitions [2019-11-28 18:33:06,447 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 15710 states. [2019-11-28 18:33:06,450 INFO L276 IsEmpty]: Start isEmpty. Operand 15710 states. [2019-11-28 18:33:06,457 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2019-11-28 18:33:06,457 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:06,458 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:06,459 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:06,465 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:06,466 INFO L82 PathProgramCache]: Analyzing trace with hash 2126234855, now seen corresponding path program 1 times [2019-11-28 18:33:06,476 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:06,477 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [398051844] [2019-11-28 18:33:06,478 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:06,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:06,779 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:06,779 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [398051844] [2019-11-28 18:33:06,780 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:06,780 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-11-28 18:33:06,781 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1640915816] [2019-11-28 18:33:06,786 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:33:06,787 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:06,801 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:33:06,802 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:33:06,805 INFO L87 Difference]: Start difference. First operand 15710 states. Second operand 3 states. [2019-11-28 18:33:07,221 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:07,222 INFO L93 Difference]: Finished difference Result 15638 states and 59348 transitions. [2019-11-28 18:33:07,222 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:33:07,224 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2019-11-28 18:33:07,224 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:07,409 INFO L225 Difference]: With dead ends: 15638 [2019-11-28 18:33:07,409 INFO L226 Difference]: Without dead ends: 15326 [2019-11-28 18:33:07,411 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:33:07,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15326 states. [2019-11-28 18:33:08,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15326 to 15326. [2019-11-28 18:33:08,285 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15326 states. [2019-11-28 18:33:08,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15326 states to 15326 states and 58230 transitions. [2019-11-28 18:33:08,371 INFO L78 Accepts]: Start accepts. Automaton has 15326 states and 58230 transitions. Word has length 7 [2019-11-28 18:33:08,374 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:08,375 INFO L462 AbstractCegarLoop]: Abstraction has 15326 states and 58230 transitions. [2019-11-28 18:33:08,375 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:33:08,375 INFO L276 IsEmpty]: Start isEmpty. Operand 15326 states and 58230 transitions. [2019-11-28 18:33:08,386 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-11-28 18:33:08,386 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:08,386 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:08,387 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:08,387 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:08,387 INFO L82 PathProgramCache]: Analyzing trace with hash -380072381, now seen corresponding path program 1 times [2019-11-28 18:33:08,388 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:08,388 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1745482254] [2019-11-28 18:33:08,388 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:08,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:08,553 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:08,554 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1745482254] [2019-11-28 18:33:08,554 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:08,554 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:33:08,556 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1132802761] [2019-11-28 18:33:08,557 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:33:08,557 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:08,558 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:33:08,558 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:33:08,558 INFO L87 Difference]: Start difference. First operand 15326 states and 58230 transitions. Second operand 4 states. [2019-11-28 18:33:09,128 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:09,129 INFO L93 Difference]: Finished difference Result 24490 states and 89350 transitions. [2019-11-28 18:33:09,129 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:33:09,129 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-11-28 18:33:09,129 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:09,224 INFO L225 Difference]: With dead ends: 24490 [2019-11-28 18:33:09,224 INFO L226 Difference]: Without dead ends: 24476 [2019-11-28 18:33:09,225 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:33:09,392 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24476 states. [2019-11-28 18:33:10,202 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24476 to 22206. [2019-11-28 18:33:10,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22206 states. [2019-11-28 18:33:10,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22206 states to 22206 states and 82052 transitions. [2019-11-28 18:33:10,293 INFO L78 Accepts]: Start accepts. Automaton has 22206 states and 82052 transitions. Word has length 13 [2019-11-28 18:33:10,293 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:10,293 INFO L462 AbstractCegarLoop]: Abstraction has 22206 states and 82052 transitions. [2019-11-28 18:33:10,293 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:33:10,294 INFO L276 IsEmpty]: Start isEmpty. Operand 22206 states and 82052 transitions. [2019-11-28 18:33:10,295 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-11-28 18:33:10,295 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:10,295 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:10,296 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:10,296 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:10,296 INFO L82 PathProgramCache]: Analyzing trace with hash 691839138, now seen corresponding path program 1 times [2019-11-28 18:33:10,296 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:10,297 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [459255434] [2019-11-28 18:33:10,297 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:10,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:10,382 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:10,382 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [459255434] [2019-11-28 18:33:10,383 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:10,384 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:33:10,384 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1496114402] [2019-11-28 18:33:10,384 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:33:10,385 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:10,385 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:33:10,385 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:33:10,385 INFO L87 Difference]: Start difference. First operand 22206 states and 82052 transitions. Second operand 4 states. [2019-11-28 18:33:10,718 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:10,718 INFO L93 Difference]: Finished difference Result 27876 states and 102039 transitions. [2019-11-28 18:33:10,718 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:33:10,719 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-11-28 18:33:10,719 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:10,841 INFO L225 Difference]: With dead ends: 27876 [2019-11-28 18:33:10,841 INFO L226 Difference]: Without dead ends: 27876 [2019-11-28 18:33:10,841 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:33:10,998 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27876 states. [2019-11-28 18:33:11,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27876 to 24582. [2019-11-28 18:33:11,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24582 states. [2019-11-28 18:33:12,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24582 states to 24582 states and 90664 transitions. [2019-11-28 18:33:12,163 INFO L78 Accepts]: Start accepts. Automaton has 24582 states and 90664 transitions. Word has length 13 [2019-11-28 18:33:12,163 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:12,163 INFO L462 AbstractCegarLoop]: Abstraction has 24582 states and 90664 transitions. [2019-11-28 18:33:12,163 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:33:12,164 INFO L276 IsEmpty]: Start isEmpty. Operand 24582 states and 90664 transitions. [2019-11-28 18:33:12,170 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-11-28 18:33:12,170 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:12,170 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:12,170 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:12,171 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:12,171 INFO L82 PathProgramCache]: Analyzing trace with hash -165939970, now seen corresponding path program 1 times [2019-11-28 18:33:12,171 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:12,171 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [643165387] [2019-11-28 18:33:12,172 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:12,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:12,249 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:12,249 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [643165387] [2019-11-28 18:33:12,249 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:12,250 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:33:12,250 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [337766926] [2019-11-28 18:33:12,250 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:33:12,250 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:12,251 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:33:12,251 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:33:12,251 INFO L87 Difference]: Start difference. First operand 24582 states and 90664 transitions. Second operand 5 states. [2019-11-28 18:33:12,813 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:12,814 INFO L93 Difference]: Finished difference Result 33300 states and 120391 transitions. [2019-11-28 18:33:12,814 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-11-28 18:33:12,814 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-11-28 18:33:12,815 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:12,955 INFO L225 Difference]: With dead ends: 33300 [2019-11-28 18:33:12,956 INFO L226 Difference]: Without dead ends: 33286 [2019-11-28 18:33:12,956 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-11-28 18:33:13,138 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33286 states. [2019-11-28 18:33:13,722 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33286 to 24486. [2019-11-28 18:33:13,723 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24486 states. [2019-11-28 18:33:13,800 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24486 states to 24486 states and 90098 transitions. [2019-11-28 18:33:13,800 INFO L78 Accepts]: Start accepts. Automaton has 24486 states and 90098 transitions. Word has length 19 [2019-11-28 18:33:13,800 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:13,800 INFO L462 AbstractCegarLoop]: Abstraction has 24486 states and 90098 transitions. [2019-11-28 18:33:13,801 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:33:13,801 INFO L276 IsEmpty]: Start isEmpty. Operand 24486 states and 90098 transitions. [2019-11-28 18:33:13,827 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-11-28 18:33:13,827 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:13,827 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:13,827 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:13,828 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:13,828 INFO L82 PathProgramCache]: Analyzing trace with hash -1278693284, now seen corresponding path program 1 times [2019-11-28 18:33:13,828 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:13,828 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1048871705] [2019-11-28 18:33:13,828 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:13,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:13,878 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:13,879 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1048871705] [2019-11-28 18:33:13,879 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:13,879 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:33:13,879 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1304981949] [2019-11-28 18:33:13,880 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:33:13,880 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:13,880 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:33:13,880 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:33:13,880 INFO L87 Difference]: Start difference. First operand 24486 states and 90098 transitions. Second operand 3 states. [2019-11-28 18:33:14,580 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:14,580 INFO L93 Difference]: Finished difference Result 29936 states and 108805 transitions. [2019-11-28 18:33:14,580 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:33:14,580 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-11-28 18:33:14,581 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:14,697 INFO L225 Difference]: With dead ends: 29936 [2019-11-28 18:33:14,697 INFO L226 Difference]: Without dead ends: 29936 [2019-11-28 18:33:14,698 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:33:14,876 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29936 states. [2019-11-28 18:33:15,437 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29936 to 26410. [2019-11-28 18:33:15,437 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26410 states. [2019-11-28 18:33:15,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26410 states to 26410 states and 96908 transitions. [2019-11-28 18:33:15,520 INFO L78 Accepts]: Start accepts. Automaton has 26410 states and 96908 transitions. Word has length 27 [2019-11-28 18:33:15,521 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:15,522 INFO L462 AbstractCegarLoop]: Abstraction has 26410 states and 96908 transitions. [2019-11-28 18:33:15,522 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:33:15,522 INFO L276 IsEmpty]: Start isEmpty. Operand 26410 states and 96908 transitions. [2019-11-28 18:33:15,547 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-11-28 18:33:15,547 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:15,547 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:15,548 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:15,548 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:15,548 INFO L82 PathProgramCache]: Analyzing trace with hash -1374888423, now seen corresponding path program 1 times [2019-11-28 18:33:15,548 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:15,550 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [359271040] [2019-11-28 18:33:15,550 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:15,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:15,645 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:15,646 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [359271040] [2019-11-28 18:33:15,646 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:15,646 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:33:15,647 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [793476530] [2019-11-28 18:33:15,647 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:33:15,647 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:15,647 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:33:15,647 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:33:15,649 INFO L87 Difference]: Start difference. First operand 26410 states and 96908 transitions. Second operand 3 states. [2019-11-28 18:33:15,709 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:15,709 INFO L93 Difference]: Finished difference Result 15137 states and 48090 transitions. [2019-11-28 18:33:15,710 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:33:15,710 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-11-28 18:33:15,710 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:15,734 INFO L225 Difference]: With dead ends: 15137 [2019-11-28 18:33:15,735 INFO L226 Difference]: Without dead ends: 15137 [2019-11-28 18:33:15,735 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:33:15,801 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15137 states. [2019-11-28 18:33:15,985 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15137 to 15137. [2019-11-28 18:33:15,986 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15137 states. [2019-11-28 18:33:16,021 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15137 states to 15137 states and 48090 transitions. [2019-11-28 18:33:16,022 INFO L78 Accepts]: Start accepts. Automaton has 15137 states and 48090 transitions. Word has length 27 [2019-11-28 18:33:16,022 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:16,022 INFO L462 AbstractCegarLoop]: Abstraction has 15137 states and 48090 transitions. [2019-11-28 18:33:16,022 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:33:16,022 INFO L276 IsEmpty]: Start isEmpty. Operand 15137 states and 48090 transitions. [2019-11-28 18:33:16,029 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-11-28 18:33:16,030 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:16,030 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:16,030 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:16,030 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:16,030 INFO L82 PathProgramCache]: Analyzing trace with hash 783683513, now seen corresponding path program 1 times [2019-11-28 18:33:16,031 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:16,031 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [764587664] [2019-11-28 18:33:16,031 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:16,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:16,081 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:16,081 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [764587664] [2019-11-28 18:33:16,082 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:16,083 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:33:16,083 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1035438769] [2019-11-28 18:33:16,083 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:33:16,083 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:16,084 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:33:16,084 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:33:16,084 INFO L87 Difference]: Start difference. First operand 15137 states and 48090 transitions. Second operand 4 states. [2019-11-28 18:33:16,108 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:16,108 INFO L93 Difference]: Finished difference Result 2291 states and 5311 transitions. [2019-11-28 18:33:16,108 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-28 18:33:16,108 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 28 [2019-11-28 18:33:16,109 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:16,112 INFO L225 Difference]: With dead ends: 2291 [2019-11-28 18:33:16,112 INFO L226 Difference]: Without dead ends: 2291 [2019-11-28 18:33:16,112 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:33:16,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2291 states. [2019-11-28 18:33:16,136 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2291 to 2291. [2019-11-28 18:33:16,137 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2291 states. [2019-11-28 18:33:16,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2291 states to 2291 states and 5311 transitions. [2019-11-28 18:33:16,142 INFO L78 Accepts]: Start accepts. Automaton has 2291 states and 5311 transitions. Word has length 28 [2019-11-28 18:33:16,142 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:16,142 INFO L462 AbstractCegarLoop]: Abstraction has 2291 states and 5311 transitions. [2019-11-28 18:33:16,142 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:33:16,142 INFO L276 IsEmpty]: Start isEmpty. Operand 2291 states and 5311 transitions. [2019-11-28 18:33:16,145 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2019-11-28 18:33:16,146 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:16,146 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:16,146 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:16,146 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:16,146 INFO L82 PathProgramCache]: Analyzing trace with hash 1644769556, now seen corresponding path program 1 times [2019-11-28 18:33:16,147 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:16,147 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1870202721] [2019-11-28 18:33:16,147 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:16,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:16,284 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:16,285 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1870202721] [2019-11-28 18:33:16,285 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:16,285 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 18:33:16,285 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [70788296] [2019-11-28 18:33:16,286 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:33:16,286 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:16,286 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:33:16,286 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:33:16,287 INFO L87 Difference]: Start difference. First operand 2291 states and 5311 transitions. Second operand 5 states. [2019-11-28 18:33:16,309 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:16,309 INFO L93 Difference]: Finished difference Result 653 states and 1502 transitions. [2019-11-28 18:33:16,310 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:33:16,310 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 40 [2019-11-28 18:33:16,310 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:16,312 INFO L225 Difference]: With dead ends: 653 [2019-11-28 18:33:16,312 INFO L226 Difference]: Without dead ends: 653 [2019-11-28 18:33:16,312 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:33:16,315 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 653 states. [2019-11-28 18:33:16,321 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 653 to 597. [2019-11-28 18:33:16,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 597 states. [2019-11-28 18:33:16,322 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 597 states to 597 states and 1370 transitions. [2019-11-28 18:33:16,322 INFO L78 Accepts]: Start accepts. Automaton has 597 states and 1370 transitions. Word has length 40 [2019-11-28 18:33:16,324 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:16,325 INFO L462 AbstractCegarLoop]: Abstraction has 597 states and 1370 transitions. [2019-11-28 18:33:16,325 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:33:16,325 INFO L276 IsEmpty]: Start isEmpty. Operand 597 states and 1370 transitions. [2019-11-28 18:33:16,326 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-11-28 18:33:16,327 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:16,327 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:16,327 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:16,327 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:16,328 INFO L82 PathProgramCache]: Analyzing trace with hash -922835002, now seen corresponding path program 1 times [2019-11-28 18:33:16,328 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:16,328 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1994814918] [2019-11-28 18:33:16,328 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:16,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:16,484 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:16,484 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1994814918] [2019-11-28 18:33:16,485 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:16,486 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-28 18:33:16,486 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1340782007] [2019-11-28 18:33:16,487 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-28 18:33:16,487 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:16,487 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-28 18:33:16,488 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-11-28 18:33:16,488 INFO L87 Difference]: Start difference. First operand 597 states and 1370 transitions. Second operand 6 states. [2019-11-28 18:33:16,822 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:16,822 INFO L93 Difference]: Finished difference Result 950 states and 2192 transitions. [2019-11-28 18:33:16,823 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-11-28 18:33:16,823 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 55 [2019-11-28 18:33:16,823 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:16,825 INFO L225 Difference]: With dead ends: 950 [2019-11-28 18:33:16,825 INFO L226 Difference]: Without dead ends: 950 [2019-11-28 18:33:16,825 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 8 SyntacticMatches, 2 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=32, Invalid=78, Unknown=0, NotChecked=0, Total=110 [2019-11-28 18:33:16,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 950 states. [2019-11-28 18:33:16,836 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 950 to 852. [2019-11-28 18:33:16,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 852 states. [2019-11-28 18:33:16,838 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 852 states to 852 states and 1967 transitions. [2019-11-28 18:33:16,838 INFO L78 Accepts]: Start accepts. Automaton has 852 states and 1967 transitions. Word has length 55 [2019-11-28 18:33:16,839 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:16,839 INFO L462 AbstractCegarLoop]: Abstraction has 852 states and 1967 transitions. [2019-11-28 18:33:16,839 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-28 18:33:16,839 INFO L276 IsEmpty]: Start isEmpty. Operand 852 states and 1967 transitions. [2019-11-28 18:33:16,841 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-11-28 18:33:16,841 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:16,841 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:16,842 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:16,842 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:16,842 INFO L82 PathProgramCache]: Analyzing trace with hash -256459022, now seen corresponding path program 2 times [2019-11-28 18:33:16,842 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:16,843 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1699080183] [2019-11-28 18:33:16,843 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:16,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:16,956 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:16,957 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1699080183] [2019-11-28 18:33:16,957 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:16,958 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-28 18:33:16,958 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1318105047] [2019-11-28 18:33:16,960 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-11-28 18:33:16,960 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:16,960 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-11-28 18:33:16,961 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-11-28 18:33:16,961 INFO L87 Difference]: Start difference. First operand 852 states and 1967 transitions. Second operand 6 states. [2019-11-28 18:33:17,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:17,310 INFO L93 Difference]: Finished difference Result 1292 states and 2987 transitions. [2019-11-28 18:33:17,310 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-11-28 18:33:17,311 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 55 [2019-11-28 18:33:17,311 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:17,313 INFO L225 Difference]: With dead ends: 1292 [2019-11-28 18:33:17,314 INFO L226 Difference]: Without dead ends: 1292 [2019-11-28 18:33:17,314 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2019-11-28 18:33:17,316 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1292 states. [2019-11-28 18:33:17,327 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1292 to 934. [2019-11-28 18:33:17,327 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 934 states. [2019-11-28 18:33:17,329 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 934 states to 934 states and 2174 transitions. [2019-11-28 18:33:17,329 INFO L78 Accepts]: Start accepts. Automaton has 934 states and 2174 transitions. Word has length 55 [2019-11-28 18:33:17,329 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:17,329 INFO L462 AbstractCegarLoop]: Abstraction has 934 states and 2174 transitions. [2019-11-28 18:33:17,329 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-11-28 18:33:17,330 INFO L276 IsEmpty]: Start isEmpty. Operand 934 states and 2174 transitions. [2019-11-28 18:33:17,332 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-11-28 18:33:17,332 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:17,332 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:17,332 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:17,332 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:17,333 INFO L82 PathProgramCache]: Analyzing trace with hash -198491454, now seen corresponding path program 3 times [2019-11-28 18:33:17,333 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:17,333 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1814596546] [2019-11-28 18:33:17,333 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:17,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:17,443 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:17,443 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1814596546] [2019-11-28 18:33:17,443 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:17,444 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 18:33:17,444 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [280035037] [2019-11-28 18:33:17,444 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:33:17,444 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:17,445 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:33:17,445 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:33:17,445 INFO L87 Difference]: Start difference. First operand 934 states and 2174 transitions. Second operand 5 states. [2019-11-28 18:33:17,501 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:17,501 INFO L93 Difference]: Finished difference Result 1360 states and 2948 transitions. [2019-11-28 18:33:17,502 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:33:17,502 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 55 [2019-11-28 18:33:17,502 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:17,504 INFO L225 Difference]: With dead ends: 1360 [2019-11-28 18:33:17,504 INFO L226 Difference]: Without dead ends: 862 [2019-11-28 18:33:17,504 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-28 18:33:17,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 862 states. [2019-11-28 18:33:17,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 862 to 862. [2019-11-28 18:33:17,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 862 states. [2019-11-28 18:33:17,522 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 862 states to 862 states and 1965 transitions. [2019-11-28 18:33:17,522 INFO L78 Accepts]: Start accepts. Automaton has 862 states and 1965 transitions. Word has length 55 [2019-11-28 18:33:17,522 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:17,523 INFO L462 AbstractCegarLoop]: Abstraction has 862 states and 1965 transitions. [2019-11-28 18:33:17,523 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:33:17,523 INFO L276 IsEmpty]: Start isEmpty. Operand 862 states and 1965 transitions. [2019-11-28 18:33:17,525 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-11-28 18:33:17,525 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:17,525 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:17,525 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:17,526 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:17,526 INFO L82 PathProgramCache]: Analyzing trace with hash 1836195800, now seen corresponding path program 4 times [2019-11-28 18:33:17,526 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:17,527 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1781938573] [2019-11-28 18:33:17,527 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:17,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:17,601 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:17,601 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1781938573] [2019-11-28 18:33:17,602 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:17,602 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:33:17,602 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [851183249] [2019-11-28 18:33:17,603 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:33:17,603 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:17,603 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:33:17,604 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:33:17,604 INFO L87 Difference]: Start difference. First operand 862 states and 1965 transitions. Second operand 3 states. [2019-11-28 18:33:17,663 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:17,663 INFO L93 Difference]: Finished difference Result 862 states and 1964 transitions. [2019-11-28 18:33:17,664 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:33:17,664 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 55 [2019-11-28 18:33:17,664 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:17,666 INFO L225 Difference]: With dead ends: 862 [2019-11-28 18:33:17,666 INFO L226 Difference]: Without dead ends: 862 [2019-11-28 18:33:17,666 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:33:17,669 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 862 states. [2019-11-28 18:33:17,678 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 862 to 580. [2019-11-28 18:33:17,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 580 states. [2019-11-28 18:33:17,680 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 580 states to 580 states and 1308 transitions. [2019-11-28 18:33:17,680 INFO L78 Accepts]: Start accepts. Automaton has 580 states and 1308 transitions. Word has length 55 [2019-11-28 18:33:17,681 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:17,681 INFO L462 AbstractCegarLoop]: Abstraction has 580 states and 1308 transitions. [2019-11-28 18:33:17,681 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:33:17,681 INFO L276 IsEmpty]: Start isEmpty. Operand 580 states and 1308 transitions. [2019-11-28 18:33:17,683 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-11-28 18:33:17,683 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:17,684 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:17,684 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:17,684 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:17,684 INFO L82 PathProgramCache]: Analyzing trace with hash 89701865, now seen corresponding path program 1 times [2019-11-28 18:33:17,685 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:17,685 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [848709452] [2019-11-28 18:33:17,685 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:17,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:18,280 WARN L192 SmtUtils]: Spent 414.00 ms on a formula simplification. DAG size of input: 14 DAG size of output: 9 [2019-11-28 18:33:18,445 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:18,445 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [848709452] [2019-11-28 18:33:18,446 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:18,446 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-11-28 18:33:18,446 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2087751998] [2019-11-28 18:33:18,446 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-11-28 18:33:18,446 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:18,447 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-11-28 18:33:18,447 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=138, Unknown=0, NotChecked=0, Total=182 [2019-11-28 18:33:18,447 INFO L87 Difference]: Start difference. First operand 580 states and 1308 transitions. Second operand 14 states. [2019-11-28 18:33:19,348 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:19,348 INFO L93 Difference]: Finished difference Result 1381 states and 3011 transitions. [2019-11-28 18:33:19,349 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2019-11-28 18:33:19,349 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 56 [2019-11-28 18:33:19,350 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:19,350 INFO L225 Difference]: With dead ends: 1381 [2019-11-28 18:33:19,350 INFO L226 Difference]: Without dead ends: 278 [2019-11-28 18:33:19,352 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 132 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=220, Invalid=592, Unknown=0, NotChecked=0, Total=812 [2019-11-28 18:33:19,353 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 278 states. [2019-11-28 18:33:19,355 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 278 to 246. [2019-11-28 18:33:19,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 246 states. [2019-11-28 18:33:19,356 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 246 states to 246 states and 452 transitions. [2019-11-28 18:33:19,356 INFO L78 Accepts]: Start accepts. Automaton has 246 states and 452 transitions. Word has length 56 [2019-11-28 18:33:19,357 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:19,357 INFO L462 AbstractCegarLoop]: Abstraction has 246 states and 452 transitions. [2019-11-28 18:33:19,357 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-11-28 18:33:19,357 INFO L276 IsEmpty]: Start isEmpty. Operand 246 states and 452 transitions. [2019-11-28 18:33:19,358 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-11-28 18:33:19,358 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:19,358 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:19,358 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:19,358 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:19,358 INFO L82 PathProgramCache]: Analyzing trace with hash 341094135, now seen corresponding path program 2 times [2019-11-28 18:33:19,359 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:19,359 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1912832257] [2019-11-28 18:33:19,359 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:19,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:19,421 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:19,421 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1912832257] [2019-11-28 18:33:19,421 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:19,422 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:33:19,422 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [330119746] [2019-11-28 18:33:19,422 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:33:19,422 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:19,422 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:33:19,423 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:33:19,423 INFO L87 Difference]: Start difference. First operand 246 states and 452 transitions. Second operand 3 states. [2019-11-28 18:33:19,433 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:19,433 INFO L93 Difference]: Finished difference Result 236 states and 416 transitions. [2019-11-28 18:33:19,434 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:33:19,434 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 56 [2019-11-28 18:33:19,434 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:19,434 INFO L225 Difference]: With dead ends: 236 [2019-11-28 18:33:19,434 INFO L226 Difference]: Without dead ends: 236 [2019-11-28 18:33:19,435 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:33:19,436 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 236 states. [2019-11-28 18:33:19,437 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 236 to 209. [2019-11-28 18:33:19,438 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 209 states. [2019-11-28 18:33:19,438 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 209 states to 209 states and 365 transitions. [2019-11-28 18:33:19,438 INFO L78 Accepts]: Start accepts. Automaton has 209 states and 365 transitions. Word has length 56 [2019-11-28 18:33:19,438 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:19,439 INFO L462 AbstractCegarLoop]: Abstraction has 209 states and 365 transitions. [2019-11-28 18:33:19,439 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:33:19,439 INFO L276 IsEmpty]: Start isEmpty. Operand 209 states and 365 transitions. [2019-11-28 18:33:19,439 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:33:19,439 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:19,440 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:19,440 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:19,440 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:19,440 INFO L82 PathProgramCache]: Analyzing trace with hash -431408076, now seen corresponding path program 1 times [2019-11-28 18:33:19,441 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:19,441 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1615650195] [2019-11-28 18:33:19,441 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:19,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:19,779 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:19,780 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1615650195] [2019-11-28 18:33:19,780 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:19,780 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-11-28 18:33:19,780 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [156228354] [2019-11-28 18:33:19,781 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-11-28 18:33:19,781 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:19,781 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-11-28 18:33:19,781 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=128, Unknown=0, NotChecked=0, Total=156 [2019-11-28 18:33:19,781 INFO L87 Difference]: Start difference. First operand 209 states and 365 transitions. Second operand 13 states. [2019-11-28 18:33:20,393 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:20,393 INFO L93 Difference]: Finished difference Result 370 states and 629 transitions. [2019-11-28 18:33:20,393 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-11-28 18:33:20,394 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 57 [2019-11-28 18:33:20,394 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:20,395 INFO L225 Difference]: With dead ends: 370 [2019-11-28 18:33:20,395 INFO L226 Difference]: Without dead ends: 335 [2019-11-28 18:33:20,396 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=86, Invalid=420, Unknown=0, NotChecked=0, Total=506 [2019-11-28 18:33:20,397 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 335 states. [2019-11-28 18:33:20,400 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 335 to 305. [2019-11-28 18:33:20,400 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 305 states. [2019-11-28 18:33:20,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 305 states to 305 states and 529 transitions. [2019-11-28 18:33:20,401 INFO L78 Accepts]: Start accepts. Automaton has 305 states and 529 transitions. Word has length 57 [2019-11-28 18:33:20,401 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:20,401 INFO L462 AbstractCegarLoop]: Abstraction has 305 states and 529 transitions. [2019-11-28 18:33:20,401 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-11-28 18:33:20,401 INFO L276 IsEmpty]: Start isEmpty. Operand 305 states and 529 transitions. [2019-11-28 18:33:20,402 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:33:20,402 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:20,402 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:20,403 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:20,403 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:20,403 INFO L82 PathProgramCache]: Analyzing trace with hash 42803636, now seen corresponding path program 2 times [2019-11-28 18:33:20,403 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:20,403 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [752685627] [2019-11-28 18:33:20,404 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:20,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:20,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:20,651 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [752685627] [2019-11-28 18:33:20,654 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:20,654 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-11-28 18:33:20,656 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [32898173] [2019-11-28 18:33:20,656 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-11-28 18:33:20,657 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:20,657 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-11-28 18:33:20,657 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2019-11-28 18:33:20,657 INFO L87 Difference]: Start difference. First operand 305 states and 529 transitions. Second operand 13 states. [2019-11-28 18:33:21,134 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:21,135 INFO L93 Difference]: Finished difference Result 424 states and 712 transitions. [2019-11-28 18:33:21,135 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-11-28 18:33:21,135 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 57 [2019-11-28 18:33:21,136 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:21,136 INFO L225 Difference]: With dead ends: 424 [2019-11-28 18:33:21,136 INFO L226 Difference]: Without dead ends: 391 [2019-11-28 18:33:21,137 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 64 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=72, Invalid=348, Unknown=0, NotChecked=0, Total=420 [2019-11-28 18:33:21,138 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 391 states. [2019-11-28 18:33:21,141 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 391 to 309. [2019-11-28 18:33:21,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 309 states. [2019-11-28 18:33:21,142 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 309 states to 309 states and 536 transitions. [2019-11-28 18:33:21,142 INFO L78 Accepts]: Start accepts. Automaton has 309 states and 536 transitions. Word has length 57 [2019-11-28 18:33:21,142 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:21,142 INFO L462 AbstractCegarLoop]: Abstraction has 309 states and 536 transitions. [2019-11-28 18:33:21,142 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-11-28 18:33:21,143 INFO L276 IsEmpty]: Start isEmpty. Operand 309 states and 536 transitions. [2019-11-28 18:33:21,143 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:33:21,143 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:21,144 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:21,144 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:21,144 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:21,144 INFO L82 PathProgramCache]: Analyzing trace with hash -1239613688, now seen corresponding path program 3 times [2019-11-28 18:33:21,145 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:21,145 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2012350058] [2019-11-28 18:33:21,145 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:21,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:21,878 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:21,879 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2012350058] [2019-11-28 18:33:21,879 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:21,879 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [19] imperfect sequences [] total 19 [2019-11-28 18:33:21,879 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1408724825] [2019-11-28 18:33:21,880 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-11-28 18:33:21,880 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:21,880 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-11-28 18:33:21,881 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=79, Invalid=341, Unknown=0, NotChecked=0, Total=420 [2019-11-28 18:33:21,881 INFO L87 Difference]: Start difference. First operand 309 states and 536 transitions. Second operand 21 states. [2019-11-28 18:33:23,147 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:23,147 INFO L93 Difference]: Finished difference Result 729 states and 1244 transitions. [2019-11-28 18:33:23,148 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2019-11-28 18:33:23,148 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 57 [2019-11-28 18:33:23,148 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:23,149 INFO L225 Difference]: With dead ends: 729 [2019-11-28 18:33:23,149 INFO L226 Difference]: Without dead ends: 696 [2019-11-28 18:33:23,150 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 42 GetRequests, 1 SyntacticMatches, 3 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 320 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=271, Invalid=1289, Unknown=0, NotChecked=0, Total=1560 [2019-11-28 18:33:23,151 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 696 states. [2019-11-28 18:33:23,155 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 696 to 325. [2019-11-28 18:33:23,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 325 states. [2019-11-28 18:33:23,156 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 325 states to 325 states and 567 transitions. [2019-11-28 18:33:23,156 INFO L78 Accepts]: Start accepts. Automaton has 325 states and 567 transitions. Word has length 57 [2019-11-28 18:33:23,156 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:23,156 INFO L462 AbstractCegarLoop]: Abstraction has 325 states and 567 transitions. [2019-11-28 18:33:23,156 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-11-28 18:33:23,157 INFO L276 IsEmpty]: Start isEmpty. Operand 325 states and 567 transitions. [2019-11-28 18:33:23,157 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:33:23,158 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:23,158 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:23,158 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:23,158 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:23,159 INFO L82 PathProgramCache]: Analyzing trace with hash 1227312486, now seen corresponding path program 4 times [2019-11-28 18:33:23,159 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:23,159 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [979885585] [2019-11-28 18:33:23,159 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:23,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:23,488 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:23,489 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [979885585] [2019-11-28 18:33:23,489 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:23,489 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-11-28 18:33:23,490 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1547441096] [2019-11-28 18:33:23,490 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-11-28 18:33:23,490 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:23,491 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-11-28 18:33:23,491 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=174, Unknown=0, NotChecked=0, Total=210 [2019-11-28 18:33:23,491 INFO L87 Difference]: Start difference. First operand 325 states and 567 transitions. Second operand 15 states. [2019-11-28 18:33:24,224 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:24,224 INFO L93 Difference]: Finished difference Result 513 states and 864 transitions. [2019-11-28 18:33:24,224 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-11-28 18:33:24,224 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 57 [2019-11-28 18:33:24,225 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:24,226 INFO L225 Difference]: With dead ends: 513 [2019-11-28 18:33:24,226 INFO L226 Difference]: Without dead ends: 478 [2019-11-28 18:33:24,227 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 109 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=138, Invalid=674, Unknown=0, NotChecked=0, Total=812 [2019-11-28 18:33:24,227 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 478 states. [2019-11-28 18:33:24,230 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 478 to 319. [2019-11-28 18:33:24,230 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 319 states. [2019-11-28 18:33:24,230 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 319 states to 319 states and 554 transitions. [2019-11-28 18:33:24,230 INFO L78 Accepts]: Start accepts. Automaton has 319 states and 554 transitions. Word has length 57 [2019-11-28 18:33:24,230 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:24,231 INFO L462 AbstractCegarLoop]: Abstraction has 319 states and 554 transitions. [2019-11-28 18:33:24,231 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-11-28 18:33:24,231 INFO L276 IsEmpty]: Start isEmpty. Operand 319 states and 554 transitions. [2019-11-28 18:33:24,231 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:33:24,231 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:24,231 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:24,232 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:24,232 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:24,232 INFO L82 PathProgramCache]: Analyzing trace with hash 21415560, now seen corresponding path program 5 times [2019-11-28 18:33:24,232 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:24,232 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [350837834] [2019-11-28 18:33:24,232 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:24,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:24,444 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:24,445 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [350837834] [2019-11-28 18:33:24,445 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:24,445 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-11-28 18:33:24,445 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [851871452] [2019-11-28 18:33:24,446 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-11-28 18:33:24,446 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:24,446 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-11-28 18:33:24,446 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=128, Unknown=0, NotChecked=0, Total=156 [2019-11-28 18:33:24,447 INFO L87 Difference]: Start difference. First operand 319 states and 554 transitions. Second operand 13 states. [2019-11-28 18:33:24,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:24,857 INFO L93 Difference]: Finished difference Result 422 states and 709 transitions. [2019-11-28 18:33:24,858 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-11-28 18:33:24,858 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 57 [2019-11-28 18:33:24,858 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:24,859 INFO L225 Difference]: With dead ends: 422 [2019-11-28 18:33:24,859 INFO L226 Difference]: Without dead ends: 389 [2019-11-28 18:33:24,860 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 69 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=90, Invalid=416, Unknown=0, NotChecked=0, Total=506 [2019-11-28 18:33:24,860 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 389 states. [2019-11-28 18:33:24,862 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 389 to 317. [2019-11-28 18:33:24,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 317 states. [2019-11-28 18:33:24,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 317 states to 317 states and 550 transitions. [2019-11-28 18:33:24,863 INFO L78 Accepts]: Start accepts. Automaton has 317 states and 550 transitions. Word has length 57 [2019-11-28 18:33:24,863 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:24,863 INFO L462 AbstractCegarLoop]: Abstraction has 317 states and 550 transitions. [2019-11-28 18:33:24,863 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-11-28 18:33:24,863 INFO L276 IsEmpty]: Start isEmpty. Operand 317 states and 550 transitions. [2019-11-28 18:33:24,864 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:33:24,864 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:24,864 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:24,864 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:24,865 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:24,865 INFO L82 PathProgramCache]: Analyzing trace with hash -97225810, now seen corresponding path program 6 times [2019-11-28 18:33:24,865 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:24,865 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [137211379] [2019-11-28 18:33:24,865 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:24,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 18:33:24,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 18:33:25,022 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-28 18:33:25,022 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-28 18:33:25,026 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [740] [740] ULTIMATE.startENTRY-->L802: Formula: (let ((.cse0 (store |v_#valid_55| 0 0))) (and (= v_~y$w_buff1~0_198 0) (= v_~x~0_55 0) (= |v_#valid_53| (store .cse0 |v_ULTIMATE.start_main_~#t2516~0.base_22| 1)) (= 0 v_~y$read_delayed_var~0.offset_7) (= v_~weak$$choice2~0_120 0) (= v_~main$tmp_guard1~0_31 0) (= v_~y$r_buff1_thd0~0_279 0) (= 0 v_~y$r_buff1_thd2~0_191) (= v_~y$read_delayed~0_7 0) (= 0 v_~y$w_buff0~0_215) (= (select .cse0 |v_ULTIMATE.start_main_~#t2516~0.base_22|) 0) (= 0 v_~y$r_buff0_thd3~0_201) (< 0 |v_#StackHeapBarrier_17|) (= v_~y$r_buff0_thd0~0_331 0) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t2516~0.base_22|) (= v_~y$r_buff0_thd1~0_37 0) (= v_~y$w_buff0_used~0_623 0) (= 0 |v_#NULL.base_4|) (= v_~y~0_147 0) (= 0 v_~__unbuffered_p0_EAX~0_42) (= 0 v_~y$read_delayed_var~0.base_7) (= v_~y$mem_tmp~0_20 0) (= 0 v_~weak$$choice0~0_16) (= 0 v_~y$flush_delayed~0_42) (= 0 v_~y$r_buff0_thd2~0_116) (= v_~y$w_buff1_used~0_397 0) (= |v_#NULL.offset_4| 0) (= 0 |v_ULTIMATE.start_main_~#t2516~0.offset_17|) (= v_~main$tmp_guard0~0_26 0) (= (store |v_#memory_int_20| |v_ULTIMATE.start_main_~#t2516~0.base_22| (store (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#t2516~0.base_22|) |v_ULTIMATE.start_main_~#t2516~0.offset_17| 0)) |v_#memory_int_19|) (= (store |v_#length_22| |v_ULTIMATE.start_main_~#t2516~0.base_22| 4) |v_#length_21|) (= 0 v_~y$r_buff1_thd3~0_162) (= v_~z~0_148 0) (= 0 v_~__unbuffered_cnt~0_97) (= v_~y$r_buff1_thd1~0_116 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_55|, #memory_int=|v_#memory_int_20|, #length=|v_#length_22|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_40|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_23|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_23|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_46|, ULTIMATE.start_main_~#t2516~0.base=|v_ULTIMATE.start_main_~#t2516~0.base_22|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_25|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_40|, ~y$read_delayed~0=v_~y$read_delayed~0_7, ULTIMATE.start_main_~#t2517~0.offset=|v_ULTIMATE.start_main_~#t2517~0.offset_15|, ~y$mem_tmp~0=v_~y$mem_tmp~0_20, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_42, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_162, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_37, ~y$flush_delayed~0=v_~y$flush_delayed~0_42, #length=|v_#length_21|, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_27|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_31|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_23|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_28|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_35|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_60|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_65|, ~weak$$choice0~0=v_~weak$$choice0~0_16, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_27|, ~y$w_buff1~0=v_~y$w_buff1~0_198, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_7, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_116, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_7|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_23|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_97, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_279, ~x~0=v_~x~0_55, ULTIMATE.start_main_~#t2516~0.offset=|v_ULTIMATE.start_main_~#t2516~0.offset_17|, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_7, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_623, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_44|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_36|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_31, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_31|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_129|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_28|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_37|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_50|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_116, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_25|, ~y$w_buff0~0=v_~y$w_buff0~0_215, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_201, ~y~0=v_~y~0_147, ULTIMATE.start_main_~#t2518~0.base=|v_ULTIMATE.start_main_~#t2518~0.base_18|, ULTIMATE.start_main_~#t2517~0.base=|v_ULTIMATE.start_main_~#t2517~0.base_19|, ULTIMATE.start_main_~#t2518~0.offset=|v_ULTIMATE.start_main_~#t2518~0.offset_15|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_31|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_23|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_19|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_34|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_26, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_64|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_24|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_191, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_33|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_331, #valid=|v_#valid_53|, #memory_int=|v_#memory_int_19|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_8|, ~z~0=v_~z~0_148, ~weak$$choice2~0=v_~weak$$choice2~0_120, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_397} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_~#t2516~0.base, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~y$read_delayed~0, ULTIMATE.start_main_~#t2517~0.offset, ~y$mem_tmp~0, ~__unbuffered_p0_EAX~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, #length, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ULTIMATE.start_main_~#t2516~0.offset, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_~#t2518~0.base, ULTIMATE.start_main_~#t2517~0.base, ULTIMATE.start_main_~#t2518~0.offset, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:33:25,027 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [713] [713] L802-1-->L804: Formula: (and (= 0 |v_ULTIMATE.start_main_~#t2517~0.offset_10|) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t2517~0.base_11|) (= 0 (select |v_#valid_34| |v_ULTIMATE.start_main_~#t2517~0.base_11|)) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t2517~0.base_11| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t2517~0.base_11|) |v_ULTIMATE.start_main_~#t2517~0.offset_10| 1)) |v_#memory_int_15|) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t2517~0.base_11| 4)) (not (= |v_ULTIMATE.start_main_~#t2517~0.base_11| 0)) (= |v_#valid_33| (store |v_#valid_34| |v_ULTIMATE.start_main_~#t2517~0.base_11| 1))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_16|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t2517~0.offset=|v_ULTIMATE.start_main_~#t2517~0.offset_10|, #StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_~#t2517~0.base=|v_ULTIMATE.start_main_~#t2517~0.base_11|, #valid=|v_#valid_33|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2517~0.offset, ULTIMATE.start_main_~#t2517~0.base, #valid, #memory_int, ULTIMATE.start_main_#t~nondet15, #length] because there is no mapped edge [2019-11-28 18:33:25,028 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [702] [702] L804-1-->L806: Formula: (and (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t2518~0.base_10| 4)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2518~0.base_10| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2518~0.base_10|) |v_ULTIMATE.start_main_~#t2518~0.offset_10| 2)) |v_#memory_int_13|) (not (= 0 |v_ULTIMATE.start_main_~#t2518~0.base_10|)) (= (select |v_#valid_30| |v_ULTIMATE.start_main_~#t2518~0.base_10|) 0) (= |v_#valid_29| (store |v_#valid_30| |v_ULTIMATE.start_main_~#t2518~0.base_10| 1)) (= 0 |v_ULTIMATE.start_main_~#t2518~0.offset_10|) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t2518~0.base_10|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_30|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_~#t2518~0.offset=|v_ULTIMATE.start_main_~#t2518~0.offset_10|, #valid=|v_#valid_29|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_6|, #length=|v_#length_15|, ULTIMATE.start_main_~#t2518~0.base=|v_ULTIMATE.start_main_~#t2518~0.base_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2518~0.offset, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, #length, ULTIMATE.start_main_~#t2518~0.base] because there is no mapped edge [2019-11-28 18:33:25,029 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [616] [616] P2ENTRY-->L4-3: Formula: (and (= v_~y$w_buff0~0_29 v_~y$w_buff1~0_24) (= v_P2Thread1of1ForFork0_~arg.base_9 |v_P2Thread1of1ForFork0_#in~arg.base_11|) (= 2 v_~y$w_buff0~0_28) (= (ite (not (and (not (= 0 (mod v_~y$w_buff1_used~0_54 256))) (not (= (mod v_~y$w_buff0_used~0_103 256) 0)))) 1 0) |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_9|) (= v_~y$w_buff0_used~0_103 1) (= v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_11 |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_9|) (not (= 0 v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_11)) (= v_~y$w_buff1_used~0_54 v_~y$w_buff0_used~0_104) (= |v_P2Thread1of1ForFork0_#in~arg.offset_11| v_P2Thread1of1ForFork0_~arg.offset_9)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_11|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_104, ~y$w_buff0~0=v_~y$w_buff0~0_29, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_11|} OutVars{P2Thread1of1ForFork0_~arg.base=v_P2Thread1of1ForFork0_~arg.base_9, P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_11|, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_9|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_103, ~y$w_buff1~0=v_~y$w_buff1~0_24, ~y$w_buff0~0=v_~y$w_buff0~0_28, P2Thread1of1ForFork0_~arg.offset=v_P2Thread1of1ForFork0_~arg.offset_9, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_11|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_11, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_54} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:33:25,030 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] P0ENTRY-->P0EXIT: Formula: (and (= v_~x~0_47 v_~__unbuffered_p0_EAX~0_32) (= 0 |v_P0Thread1of1ForFork1_#res.offset_13|) (= (+ v_~__unbuffered_cnt~0_81 1) v_~__unbuffered_cnt~0_80) (= v_~z~0_109 2) (= v_P0Thread1of1ForFork1_~arg.offset_19 |v_P0Thread1of1ForFork1_#in~arg.offset_21|) (= |v_P0Thread1of1ForFork1_#in~arg.base_21| v_P0Thread1of1ForFork1_~arg.base_19) (= |v_P0Thread1of1ForFork1_#res.base_13| 0)) InVars {P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_21|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_81, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_21|, ~x~0=v_~x~0_47} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_32, P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_13|, P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_21|, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_13|, P0Thread1of1ForFork1_~arg.offset=v_P0Thread1of1ForFork1_~arg.offset_19, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_80, ~z~0=v_~z~0_109, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_21|, ~x~0=v_~x~0_47, P0Thread1of1ForFork1_~arg.base=v_P0Thread1of1ForFork1_~arg.base_19} AuxVars[] AssignedVars[~__unbuffered_p0_EAX~0, P0Thread1of1ForFork1_#res.offset, P0Thread1of1ForFork1_#res.base, P0Thread1of1ForFork1_~arg.offset, ~__unbuffered_cnt~0, ~z~0, P0Thread1of1ForFork1_~arg.base] because there is no mapped edge [2019-11-28 18:33:25,032 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [691] [691] L780-->L780-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In124302548 256) 0)) (.cse0 (= (mod ~y$r_buff0_thd3~0_In124302548 256) 0))) (or (and (not .cse0) (= |P2Thread1of1ForFork0_#t~ite11_Out124302548| 0) (not .cse1)) (and (= |P2Thread1of1ForFork0_#t~ite11_Out124302548| ~y$w_buff0_used~0_In124302548) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In124302548, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In124302548} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In124302548, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out124302548|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In124302548} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-11-28 18:33:25,033 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [678] [678] L750-2-->L750-5: Formula: (let ((.cse2 (= 0 (mod ~y$w_buff1_used~0_In270759896 256))) (.cse1 (= (mod ~y$r_buff1_thd2~0_In270759896 256) 0)) (.cse0 (= |P1Thread1of1ForFork2_#t~ite4_Out270759896| |P1Thread1of1ForFork2_#t~ite3_Out270759896|))) (or (and .cse0 (not .cse1) (not .cse2) (= |P1Thread1of1ForFork2_#t~ite3_Out270759896| ~y$w_buff1~0_In270759896)) (and (or .cse2 .cse1) .cse0 (= |P1Thread1of1ForFork2_#t~ite3_Out270759896| ~y~0_In270759896)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In270759896, ~y$w_buff1~0=~y$w_buff1~0_In270759896, ~y~0=~y~0_In270759896, ~y$w_buff1_used~0=~y$w_buff1_used~0_In270759896} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In270759896, ~y$w_buff1~0=~y$w_buff1~0_In270759896, P1Thread1of1ForFork2_#t~ite4=|P1Thread1of1ForFork2_#t~ite4_Out270759896|, ~y~0=~y~0_In270759896, P1Thread1of1ForFork2_#t~ite3=|P1Thread1of1ForFork2_#t~ite3_Out270759896|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In270759896} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite4, P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-11-28 18:33:25,034 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [694] [694] L751-->L751-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In-1594041317 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In-1594041317 256) 0))) (or (and (or .cse0 .cse1) (= ~y$w_buff0_used~0_In-1594041317 |P1Thread1of1ForFork2_#t~ite5_Out-1594041317|)) (and (not .cse0) (= 0 |P1Thread1of1ForFork2_#t~ite5_Out-1594041317|) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1594041317, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1594041317} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1594041317, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1594041317, P1Thread1of1ForFork2_#t~ite5=|P1Thread1of1ForFork2_#t~ite5_Out-1594041317|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-11-28 18:33:25,034 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [684] [684] L781-->L781-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In-1720038812 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In-1720038812 256) 0)) (.cse2 (= 0 (mod ~y$r_buff1_thd3~0_In-1720038812 256))) (.cse3 (= (mod ~y$w_buff1_used~0_In-1720038812 256) 0))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork0_#t~ite12_Out-1720038812| ~y$w_buff1_used~0_In-1720038812) (or .cse2 .cse3)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork0_#t~ite12_Out-1720038812| 0)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1720038812, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1720038812, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1720038812, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1720038812} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1720038812, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1720038812, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out-1720038812|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1720038812, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1720038812} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-11-28 18:33:25,035 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L752-->L752-2: Formula: (let ((.cse1 (= (mod ~y$r_buff1_thd2~0_In-646146690 256) 0)) (.cse0 (= (mod ~y$w_buff1_used~0_In-646146690 256) 0)) (.cse2 (= (mod ~y$r_buff0_thd2~0_In-646146690 256) 0)) (.cse3 (= 0 (mod ~y$w_buff0_used~0_In-646146690 256)))) (or (and (or .cse0 .cse1) (= ~y$w_buff1_used~0_In-646146690 |P1Thread1of1ForFork2_#t~ite6_Out-646146690|) (or .cse2 .cse3)) (and (= |P1Thread1of1ForFork2_#t~ite6_Out-646146690| 0) (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3)))))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-646146690, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-646146690, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-646146690, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-646146690} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-646146690, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-646146690, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-646146690, P1Thread1of1ForFork2_#t~ite6=|P1Thread1of1ForFork2_#t~ite6_Out-646146690|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-646146690} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-11-28 18:33:25,035 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L753-->L753-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In2139767393 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In2139767393 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork2_#t~ite7_Out2139767393|)) (and (or .cse1 .cse0) (= ~y$r_buff0_thd2~0_In2139767393 |P1Thread1of1ForFork2_#t~ite7_Out2139767393|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In2139767393, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2139767393} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In2139767393, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2139767393, P1Thread1of1ForFork2_#t~ite7=|P1Thread1of1ForFork2_#t~ite7_Out2139767393|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-11-28 18:33:25,036 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [690] [690] L754-->L754-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff1_used~0_In1509560354 256))) (.cse1 (= (mod ~y$r_buff1_thd2~0_In1509560354 256) 0)) (.cse2 (= 0 (mod ~y$r_buff0_thd2~0_In1509560354 256))) (.cse3 (= 0 (mod ~y$w_buff0_used~0_In1509560354 256)))) (or (and (= |P1Thread1of1ForFork2_#t~ite8_Out1509560354| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P1Thread1of1ForFork2_#t~ite8_Out1509560354| ~y$r_buff1_thd2~0_In1509560354)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1509560354, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1509560354, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1509560354, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1509560354} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1509560354, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1509560354, P1Thread1of1ForFork2_#t~ite8=|P1Thread1of1ForFork2_#t~ite8_Out1509560354|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1509560354, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1509560354} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-11-28 18:33:25,036 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [712] [712] L754-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= |v_P1Thread1of1ForFork2_#t~ite8_24| v_~y$r_buff1_thd2~0_103) (= v_~__unbuffered_cnt~0_54 (+ v_~__unbuffered_cnt~0_55 1))) InVars {P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_24|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_103, P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_23|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_54, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork2_#res.offset, P1Thread1of1ForFork2_#t~ite8, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-11-28 18:33:25,036 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [688] [688] L782-->L783: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In-467430696 256))) (.cse0 (= (mod ~y$w_buff0_used~0_In-467430696 256) 0)) (.cse2 (= ~y$r_buff0_thd3~0_In-467430696 ~y$r_buff0_thd3~0_Out-467430696))) (or (and (not .cse0) (= 0 ~y$r_buff0_thd3~0_Out-467430696) (not .cse1)) (and .cse1 .cse2) (and .cse0 .cse2))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-467430696, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-467430696} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-467430696, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out-467430696, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out-467430696|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-11-28 18:33:25,037 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [689] [689] L783-->L783-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In2122659476 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In2122659476 256))) (.cse3 (= 0 (mod ~y$w_buff1_used~0_In2122659476 256))) (.cse2 (= (mod ~y$r_buff1_thd3~0_In2122659476 256) 0))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork0_#t~ite14_Out2122659476| ~y$r_buff1_thd3~0_In2122659476) (or .cse2 .cse3)) (and (= 0 |P2Thread1of1ForFork0_#t~ite14_Out2122659476|) (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In2122659476, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2122659476, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In2122659476, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2122659476} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out2122659476|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In2122659476, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2122659476, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In2122659476, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2122659476} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-11-28 18:33:25,037 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L783-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= |v_P2Thread1of1ForFork0_#t~ite14_24| v_~y$r_buff1_thd3~0_99) (= (+ v_~__unbuffered_cnt~0_67 1) v_~__unbuffered_cnt~0_66) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_24|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_67} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_23|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_99, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_66, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-11-28 18:33:25,037 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [614] [614] L806-1-->L812: Formula: (and (= v_~main$tmp_guard0~0_7 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_14) 1 0) 0) 0 1)) (not (= (mod v_~main$tmp_guard0~0_7 256) 0))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_5|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet17, ~main$tmp_guard0~0] because there is no mapped edge [2019-11-28 18:33:25,038 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [692] [692] L812-2-->L812-5: Formula: (let ((.cse0 (= |ULTIMATE.start_main_#t~ite19_Out-2084326289| |ULTIMATE.start_main_#t~ite18_Out-2084326289|)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In-2084326289 256))) (.cse1 (= 0 (mod ~y$r_buff1_thd0~0_In-2084326289 256)))) (or (and .cse0 (or .cse1 .cse2) (= |ULTIMATE.start_main_#t~ite18_Out-2084326289| ~y~0_In-2084326289)) (and .cse0 (not .cse2) (not .cse1) (= |ULTIMATE.start_main_#t~ite18_Out-2084326289| ~y$w_buff1~0_In-2084326289)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-2084326289, ~y~0=~y~0_In-2084326289, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-2084326289, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2084326289} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-2084326289, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out-2084326289|, ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out-2084326289|, ~y~0=~y~0_In-2084326289, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-2084326289, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2084326289} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-11-28 18:33:25,038 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [676] [676] L813-->L813-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In-2044043605 256) 0)) (.cse1 (= (mod ~y$r_buff0_thd0~0_In-2044043605 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite20_Out-2044043605| ~y$w_buff0_used~0_In-2044043605) (or .cse0 .cse1)) (and (= |ULTIMATE.start_main_#t~ite20_Out-2044043605| 0) (not .cse0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-2044043605, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-2044043605} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-2044043605, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-2044043605, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out-2044043605|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-11-28 18:33:25,039 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [683] [683] L814-->L814-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In1717428532 256))) (.cse0 (= (mod ~y$r_buff0_thd0~0_In1717428532 256) 0)) (.cse2 (= 0 (mod ~y$r_buff1_thd0~0_In1717428532 256))) (.cse3 (= (mod ~y$w_buff1_used~0_In1717428532 256) 0))) (or (and (or .cse0 .cse1) (= ~y$w_buff1_used~0_In1717428532 |ULTIMATE.start_main_#t~ite21_Out1717428532|) (or .cse2 .cse3)) (and (= 0 |ULTIMATE.start_main_#t~ite21_Out1717428532|) (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1717428532, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1717428532, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1717428532, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1717428532} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1717428532, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1717428532, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out1717428532|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1717428532, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1717428532} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-11-28 18:33:25,039 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [680] [680] L815-->L815-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In1244165971 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In1244165971 256)))) (or (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite22_Out1244165971|) (not .cse1)) (and (= |ULTIMATE.start_main_#t~ite22_Out1244165971| ~y$r_buff0_thd0~0_In1244165971) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1244165971, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1244165971} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1244165971, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1244165971, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out1244165971|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-11-28 18:33:25,040 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [686] [686] L816-->L816-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In-1057205023 256))) (.cse1 (= (mod ~y$w_buff1_used~0_In-1057205023 256) 0)) (.cse3 (= (mod ~y$w_buff0_used~0_In-1057205023 256) 0)) (.cse2 (= (mod ~y$r_buff0_thd0~0_In-1057205023 256) 0))) (or (and (= 0 |ULTIMATE.start_main_#t~ite23_Out-1057205023|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (= ~y$r_buff1_thd0~0_In-1057205023 |ULTIMATE.start_main_#t~ite23_Out-1057205023|) (or .cse3 .cse2)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1057205023, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1057205023, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1057205023, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1057205023} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1057205023, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1057205023, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1057205023, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out-1057205023|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1057205023} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-11-28 18:33:25,043 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L827-->L827-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In2065715451 256) 0))) (or (and (not .cse0) (= ~y$w_buff1_used~0_In2065715451 |ULTIMATE.start_main_#t~ite39_Out2065715451|) (= |ULTIMATE.start_main_#t~ite38_In2065715451| |ULTIMATE.start_main_#t~ite38_Out2065715451|)) (and (= ~y$w_buff1_used~0_In2065715451 |ULTIMATE.start_main_#t~ite38_Out2065715451|) .cse0 (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In2065715451 256) 0))) (or (and (= (mod ~y$r_buff1_thd0~0_In2065715451 256) 0) .cse1) (= 0 (mod ~y$w_buff0_used~0_In2065715451 256)) (and (= 0 (mod ~y$w_buff1_used~0_In2065715451 256)) .cse1))) (= |ULTIMATE.start_main_#t~ite38_Out2065715451| |ULTIMATE.start_main_#t~ite39_Out2065715451|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In2065715451, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In2065715451, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_In2065715451|, ~weak$$choice2~0=~weak$$choice2~0_In2065715451, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In2065715451, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2065715451} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In2065715451, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out2065715451|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In2065715451, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_Out2065715451|, ~weak$$choice2~0=~weak$$choice2~0_In2065715451, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In2065715451, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2065715451} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite38] because there is no mapped edge [2019-11-28 18:33:25,044 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [649] [649] L828-->L829: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_25 256))) (= v_~y$r_buff0_thd0~0_98 v_~y$r_buff0_thd0~0_97)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_98, ~weak$$choice2~0=v_~weak$$choice2~0_25} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_13|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_8|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_97, ~weak$$choice2~0=v_~weak$$choice2~0_25, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-11-28 18:33:25,045 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [706] [706] L831-->L4: Formula: (and (= v_~y~0_99 v_~y$mem_tmp~0_10) (not (= (mod v_~y$flush_delayed~0_27 256) 0)) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4| (mod v_~main$tmp_guard1~0_12 256)) (= 0 v_~y$flush_delayed~0_26)) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_10, ~y$flush_delayed~0=v_~y$flush_delayed~0_27, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_10, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_9, ~y$flush_delayed~0=v_~y$flush_delayed~0_26, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_24|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12, ~y~0=v_~y~0_99, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ~y$flush_delayed~0, ULTIMATE.start_main_#t~ite46, ~y~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-11-28 18:33:25,045 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [709] [709] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-11-28 18:33:25,143 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 06:33:25 BasicIcfg [2019-11-28 18:33:25,144 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-28 18:33:25,144 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-28 18:33:25,144 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-28 18:33:25,144 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-28 18:33:25,145 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:32:59" (3/4) ... [2019-11-28 18:33:25,147 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-28 18:33:25,148 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [740] [740] ULTIMATE.startENTRY-->L802: Formula: (let ((.cse0 (store |v_#valid_55| 0 0))) (and (= v_~y$w_buff1~0_198 0) (= v_~x~0_55 0) (= |v_#valid_53| (store .cse0 |v_ULTIMATE.start_main_~#t2516~0.base_22| 1)) (= 0 v_~y$read_delayed_var~0.offset_7) (= v_~weak$$choice2~0_120 0) (= v_~main$tmp_guard1~0_31 0) (= v_~y$r_buff1_thd0~0_279 0) (= 0 v_~y$r_buff1_thd2~0_191) (= v_~y$read_delayed~0_7 0) (= 0 v_~y$w_buff0~0_215) (= (select .cse0 |v_ULTIMATE.start_main_~#t2516~0.base_22|) 0) (= 0 v_~y$r_buff0_thd3~0_201) (< 0 |v_#StackHeapBarrier_17|) (= v_~y$r_buff0_thd0~0_331 0) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t2516~0.base_22|) (= v_~y$r_buff0_thd1~0_37 0) (= v_~y$w_buff0_used~0_623 0) (= 0 |v_#NULL.base_4|) (= v_~y~0_147 0) (= 0 v_~__unbuffered_p0_EAX~0_42) (= 0 v_~y$read_delayed_var~0.base_7) (= v_~y$mem_tmp~0_20 0) (= 0 v_~weak$$choice0~0_16) (= 0 v_~y$flush_delayed~0_42) (= 0 v_~y$r_buff0_thd2~0_116) (= v_~y$w_buff1_used~0_397 0) (= |v_#NULL.offset_4| 0) (= 0 |v_ULTIMATE.start_main_~#t2516~0.offset_17|) (= v_~main$tmp_guard0~0_26 0) (= (store |v_#memory_int_20| |v_ULTIMATE.start_main_~#t2516~0.base_22| (store (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#t2516~0.base_22|) |v_ULTIMATE.start_main_~#t2516~0.offset_17| 0)) |v_#memory_int_19|) (= (store |v_#length_22| |v_ULTIMATE.start_main_~#t2516~0.base_22| 4) |v_#length_21|) (= 0 v_~y$r_buff1_thd3~0_162) (= v_~z~0_148 0) (= 0 v_~__unbuffered_cnt~0_97) (= v_~y$r_buff1_thd1~0_116 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_55|, #memory_int=|v_#memory_int_20|, #length=|v_#length_22|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_40|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_23|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_23|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_46|, ULTIMATE.start_main_~#t2516~0.base=|v_ULTIMATE.start_main_~#t2516~0.base_22|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_25|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_40|, ~y$read_delayed~0=v_~y$read_delayed~0_7, ULTIMATE.start_main_~#t2517~0.offset=|v_ULTIMATE.start_main_~#t2517~0.offset_15|, ~y$mem_tmp~0=v_~y$mem_tmp~0_20, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_42, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_162, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_37, ~y$flush_delayed~0=v_~y$flush_delayed~0_42, #length=|v_#length_21|, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_27|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_31|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_23|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_28|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_35|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_60|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_65|, ~weak$$choice0~0=v_~weak$$choice0~0_16, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_27|, ~y$w_buff1~0=v_~y$w_buff1~0_198, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_7, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_116, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_7|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_23|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_97, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_279, ~x~0=v_~x~0_55, ULTIMATE.start_main_~#t2516~0.offset=|v_ULTIMATE.start_main_~#t2516~0.offset_17|, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_7, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_623, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_44|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_36|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_31, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_31|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_129|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_28|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_37|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_50|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_116, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_25|, ~y$w_buff0~0=v_~y$w_buff0~0_215, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_201, ~y~0=v_~y~0_147, ULTIMATE.start_main_~#t2518~0.base=|v_ULTIMATE.start_main_~#t2518~0.base_18|, ULTIMATE.start_main_~#t2517~0.base=|v_ULTIMATE.start_main_~#t2517~0.base_19|, ULTIMATE.start_main_~#t2518~0.offset=|v_ULTIMATE.start_main_~#t2518~0.offset_15|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_31|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_23|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_19|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_34|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_26, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_64|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_24|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_191, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_33|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_331, #valid=|v_#valid_53|, #memory_int=|v_#memory_int_19|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_8|, ~z~0=v_~z~0_148, ~weak$$choice2~0=v_~weak$$choice2~0_120, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_397} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_~#t2516~0.base, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~y$read_delayed~0, ULTIMATE.start_main_~#t2517~0.offset, ~y$mem_tmp~0, ~__unbuffered_p0_EAX~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, #length, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ULTIMATE.start_main_~#t2516~0.offset, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_~#t2518~0.base, ULTIMATE.start_main_~#t2517~0.base, ULTIMATE.start_main_~#t2518~0.offset, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:33:25,148 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [713] [713] L802-1-->L804: Formula: (and (= 0 |v_ULTIMATE.start_main_~#t2517~0.offset_10|) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t2517~0.base_11|) (= 0 (select |v_#valid_34| |v_ULTIMATE.start_main_~#t2517~0.base_11|)) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t2517~0.base_11| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t2517~0.base_11|) |v_ULTIMATE.start_main_~#t2517~0.offset_10| 1)) |v_#memory_int_15|) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t2517~0.base_11| 4)) (not (= |v_ULTIMATE.start_main_~#t2517~0.base_11| 0)) (= |v_#valid_33| (store |v_#valid_34| |v_ULTIMATE.start_main_~#t2517~0.base_11| 1))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_16|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t2517~0.offset=|v_ULTIMATE.start_main_~#t2517~0.offset_10|, #StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_~#t2517~0.base=|v_ULTIMATE.start_main_~#t2517~0.base_11|, #valid=|v_#valid_33|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2517~0.offset, ULTIMATE.start_main_~#t2517~0.base, #valid, #memory_int, ULTIMATE.start_main_#t~nondet15, #length] because there is no mapped edge [2019-11-28 18:33:25,149 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [702] [702] L804-1-->L806: Formula: (and (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t2518~0.base_10| 4)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2518~0.base_10| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2518~0.base_10|) |v_ULTIMATE.start_main_~#t2518~0.offset_10| 2)) |v_#memory_int_13|) (not (= 0 |v_ULTIMATE.start_main_~#t2518~0.base_10|)) (= (select |v_#valid_30| |v_ULTIMATE.start_main_~#t2518~0.base_10|) 0) (= |v_#valid_29| (store |v_#valid_30| |v_ULTIMATE.start_main_~#t2518~0.base_10| 1)) (= 0 |v_ULTIMATE.start_main_~#t2518~0.offset_10|) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t2518~0.base_10|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_30|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_~#t2518~0.offset=|v_ULTIMATE.start_main_~#t2518~0.offset_10|, #valid=|v_#valid_29|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_6|, #length=|v_#length_15|, ULTIMATE.start_main_~#t2518~0.base=|v_ULTIMATE.start_main_~#t2518~0.base_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2518~0.offset, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, #length, ULTIMATE.start_main_~#t2518~0.base] because there is no mapped edge [2019-11-28 18:33:25,149 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [616] [616] P2ENTRY-->L4-3: Formula: (and (= v_~y$w_buff0~0_29 v_~y$w_buff1~0_24) (= v_P2Thread1of1ForFork0_~arg.base_9 |v_P2Thread1of1ForFork0_#in~arg.base_11|) (= 2 v_~y$w_buff0~0_28) (= (ite (not (and (not (= 0 (mod v_~y$w_buff1_used~0_54 256))) (not (= (mod v_~y$w_buff0_used~0_103 256) 0)))) 1 0) |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_9|) (= v_~y$w_buff0_used~0_103 1) (= v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_11 |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_9|) (not (= 0 v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_11)) (= v_~y$w_buff1_used~0_54 v_~y$w_buff0_used~0_104) (= |v_P2Thread1of1ForFork0_#in~arg.offset_11| v_P2Thread1of1ForFork0_~arg.offset_9)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_11|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_104, ~y$w_buff0~0=v_~y$w_buff0~0_29, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_11|} OutVars{P2Thread1of1ForFork0_~arg.base=v_P2Thread1of1ForFork0_~arg.base_9, P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_11|, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_9|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_103, ~y$w_buff1~0=v_~y$w_buff1~0_24, ~y$w_buff0~0=v_~y$w_buff0~0_28, P2Thread1of1ForFork0_~arg.offset=v_P2Thread1of1ForFork0_~arg.offset_9, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_11|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_11, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_54} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:33:25,150 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] P0ENTRY-->P0EXIT: Formula: (and (= v_~x~0_47 v_~__unbuffered_p0_EAX~0_32) (= 0 |v_P0Thread1of1ForFork1_#res.offset_13|) (= (+ v_~__unbuffered_cnt~0_81 1) v_~__unbuffered_cnt~0_80) (= v_~z~0_109 2) (= v_P0Thread1of1ForFork1_~arg.offset_19 |v_P0Thread1of1ForFork1_#in~arg.offset_21|) (= |v_P0Thread1of1ForFork1_#in~arg.base_21| v_P0Thread1of1ForFork1_~arg.base_19) (= |v_P0Thread1of1ForFork1_#res.base_13| 0)) InVars {P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_21|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_81, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_21|, ~x~0=v_~x~0_47} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_32, P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_13|, P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_21|, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_13|, P0Thread1of1ForFork1_~arg.offset=v_P0Thread1of1ForFork1_~arg.offset_19, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_80, ~z~0=v_~z~0_109, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_21|, ~x~0=v_~x~0_47, P0Thread1of1ForFork1_~arg.base=v_P0Thread1of1ForFork1_~arg.base_19} AuxVars[] AssignedVars[~__unbuffered_p0_EAX~0, P0Thread1of1ForFork1_#res.offset, P0Thread1of1ForFork1_#res.base, P0Thread1of1ForFork1_~arg.offset, ~__unbuffered_cnt~0, ~z~0, P0Thread1of1ForFork1_~arg.base] because there is no mapped edge [2019-11-28 18:33:25,151 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [691] [691] L780-->L780-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In124302548 256) 0)) (.cse0 (= (mod ~y$r_buff0_thd3~0_In124302548 256) 0))) (or (and (not .cse0) (= |P2Thread1of1ForFork0_#t~ite11_Out124302548| 0) (not .cse1)) (and (= |P2Thread1of1ForFork0_#t~ite11_Out124302548| ~y$w_buff0_used~0_In124302548) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In124302548, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In124302548} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In124302548, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out124302548|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In124302548} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-11-28 18:33:25,151 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [678] [678] L750-2-->L750-5: Formula: (let ((.cse2 (= 0 (mod ~y$w_buff1_used~0_In270759896 256))) (.cse1 (= (mod ~y$r_buff1_thd2~0_In270759896 256) 0)) (.cse0 (= |P1Thread1of1ForFork2_#t~ite4_Out270759896| |P1Thread1of1ForFork2_#t~ite3_Out270759896|))) (or (and .cse0 (not .cse1) (not .cse2) (= |P1Thread1of1ForFork2_#t~ite3_Out270759896| ~y$w_buff1~0_In270759896)) (and (or .cse2 .cse1) .cse0 (= |P1Thread1of1ForFork2_#t~ite3_Out270759896| ~y~0_In270759896)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In270759896, ~y$w_buff1~0=~y$w_buff1~0_In270759896, ~y~0=~y~0_In270759896, ~y$w_buff1_used~0=~y$w_buff1_used~0_In270759896} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In270759896, ~y$w_buff1~0=~y$w_buff1~0_In270759896, P1Thread1of1ForFork2_#t~ite4=|P1Thread1of1ForFork2_#t~ite4_Out270759896|, ~y~0=~y~0_In270759896, P1Thread1of1ForFork2_#t~ite3=|P1Thread1of1ForFork2_#t~ite3_Out270759896|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In270759896} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite4, P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-11-28 18:33:25,152 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [694] [694] L751-->L751-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In-1594041317 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In-1594041317 256) 0))) (or (and (or .cse0 .cse1) (= ~y$w_buff0_used~0_In-1594041317 |P1Thread1of1ForFork2_#t~ite5_Out-1594041317|)) (and (not .cse0) (= 0 |P1Thread1of1ForFork2_#t~ite5_Out-1594041317|) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1594041317, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1594041317} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1594041317, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-1594041317, P1Thread1of1ForFork2_#t~ite5=|P1Thread1of1ForFork2_#t~ite5_Out-1594041317|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-11-28 18:33:25,152 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [684] [684] L781-->L781-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In-1720038812 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In-1720038812 256) 0)) (.cse2 (= 0 (mod ~y$r_buff1_thd3~0_In-1720038812 256))) (.cse3 (= (mod ~y$w_buff1_used~0_In-1720038812 256) 0))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork0_#t~ite12_Out-1720038812| ~y$w_buff1_used~0_In-1720038812) (or .cse2 .cse3)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork0_#t~ite12_Out-1720038812| 0)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1720038812, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1720038812, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1720038812, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1720038812} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-1720038812, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1720038812, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out-1720038812|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1720038812, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1720038812} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-11-28 18:33:25,153 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L752-->L752-2: Formula: (let ((.cse1 (= (mod ~y$r_buff1_thd2~0_In-646146690 256) 0)) (.cse0 (= (mod ~y$w_buff1_used~0_In-646146690 256) 0)) (.cse2 (= (mod ~y$r_buff0_thd2~0_In-646146690 256) 0)) (.cse3 (= 0 (mod ~y$w_buff0_used~0_In-646146690 256)))) (or (and (or .cse0 .cse1) (= ~y$w_buff1_used~0_In-646146690 |P1Thread1of1ForFork2_#t~ite6_Out-646146690|) (or .cse2 .cse3)) (and (= |P1Thread1of1ForFork2_#t~ite6_Out-646146690| 0) (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3)))))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-646146690, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-646146690, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-646146690, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-646146690} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-646146690, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-646146690, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-646146690, P1Thread1of1ForFork2_#t~ite6=|P1Thread1of1ForFork2_#t~ite6_Out-646146690|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-646146690} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-11-28 18:33:25,153 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L753-->L753-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In2139767393 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In2139767393 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork2_#t~ite7_Out2139767393|)) (and (or .cse1 .cse0) (= ~y$r_buff0_thd2~0_In2139767393 |P1Thread1of1ForFork2_#t~ite7_Out2139767393|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In2139767393, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2139767393} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In2139767393, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In2139767393, P1Thread1of1ForFork2_#t~ite7=|P1Thread1of1ForFork2_#t~ite7_Out2139767393|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-11-28 18:33:25,153 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [690] [690] L754-->L754-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff1_used~0_In1509560354 256))) (.cse1 (= (mod ~y$r_buff1_thd2~0_In1509560354 256) 0)) (.cse2 (= 0 (mod ~y$r_buff0_thd2~0_In1509560354 256))) (.cse3 (= 0 (mod ~y$w_buff0_used~0_In1509560354 256)))) (or (and (= |P1Thread1of1ForFork2_#t~ite8_Out1509560354| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P1Thread1of1ForFork2_#t~ite8_Out1509560354| ~y$r_buff1_thd2~0_In1509560354)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1509560354, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1509560354, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1509560354, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1509560354} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1509560354, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1509560354, P1Thread1of1ForFork2_#t~ite8=|P1Thread1of1ForFork2_#t~ite8_Out1509560354|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1509560354, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1509560354} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-11-28 18:33:25,154 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [712] [712] L754-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= |v_P1Thread1of1ForFork2_#t~ite8_24| v_~y$r_buff1_thd2~0_103) (= v_~__unbuffered_cnt~0_54 (+ v_~__unbuffered_cnt~0_55 1))) InVars {P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_24|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_103, P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_23|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_54, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork2_#res.offset, P1Thread1of1ForFork2_#t~ite8, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-11-28 18:33:25,154 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [688] [688] L782-->L783: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In-467430696 256))) (.cse0 (= (mod ~y$w_buff0_used~0_In-467430696 256) 0)) (.cse2 (= ~y$r_buff0_thd3~0_In-467430696 ~y$r_buff0_thd3~0_Out-467430696))) (or (and (not .cse0) (= 0 ~y$r_buff0_thd3~0_Out-467430696) (not .cse1)) (and .cse1 .cse2) (and .cse0 .cse2))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-467430696, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-467430696} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-467430696, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out-467430696, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out-467430696|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-11-28 18:33:25,154 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [689] [689] L783-->L783-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In2122659476 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In2122659476 256))) (.cse3 (= 0 (mod ~y$w_buff1_used~0_In2122659476 256))) (.cse2 (= (mod ~y$r_buff1_thd3~0_In2122659476 256) 0))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork0_#t~ite14_Out2122659476| ~y$r_buff1_thd3~0_In2122659476) (or .cse2 .cse3)) (and (= 0 |P2Thread1of1ForFork0_#t~ite14_Out2122659476|) (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In2122659476, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2122659476, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In2122659476, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2122659476} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out2122659476|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In2122659476, ~y$w_buff0_used~0=~y$w_buff0_used~0_In2122659476, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In2122659476, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2122659476} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-11-28 18:33:25,154 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L783-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= |v_P2Thread1of1ForFork0_#t~ite14_24| v_~y$r_buff1_thd3~0_99) (= (+ v_~__unbuffered_cnt~0_67 1) v_~__unbuffered_cnt~0_66) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_24|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_67} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_23|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_99, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_66, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-11-28 18:33:25,154 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [614] [614] L806-1-->L812: Formula: (and (= v_~main$tmp_guard0~0_7 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_14) 1 0) 0) 0 1)) (not (= (mod v_~main$tmp_guard0~0_7 256) 0))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_5|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet17, ~main$tmp_guard0~0] because there is no mapped edge [2019-11-28 18:33:25,155 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [692] [692] L812-2-->L812-5: Formula: (let ((.cse0 (= |ULTIMATE.start_main_#t~ite19_Out-2084326289| |ULTIMATE.start_main_#t~ite18_Out-2084326289|)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In-2084326289 256))) (.cse1 (= 0 (mod ~y$r_buff1_thd0~0_In-2084326289 256)))) (or (and .cse0 (or .cse1 .cse2) (= |ULTIMATE.start_main_#t~ite18_Out-2084326289| ~y~0_In-2084326289)) (and .cse0 (not .cse2) (not .cse1) (= |ULTIMATE.start_main_#t~ite18_Out-2084326289| ~y$w_buff1~0_In-2084326289)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-2084326289, ~y~0=~y~0_In-2084326289, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-2084326289, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2084326289} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-2084326289, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out-2084326289|, ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out-2084326289|, ~y~0=~y~0_In-2084326289, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-2084326289, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2084326289} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-11-28 18:33:25,155 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [676] [676] L813-->L813-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In-2044043605 256) 0)) (.cse1 (= (mod ~y$r_buff0_thd0~0_In-2044043605 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite20_Out-2044043605| ~y$w_buff0_used~0_In-2044043605) (or .cse0 .cse1)) (and (= |ULTIMATE.start_main_#t~ite20_Out-2044043605| 0) (not .cse0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-2044043605, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-2044043605} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-2044043605, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-2044043605, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out-2044043605|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-11-28 18:33:25,156 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [683] [683] L814-->L814-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In1717428532 256))) (.cse0 (= (mod ~y$r_buff0_thd0~0_In1717428532 256) 0)) (.cse2 (= 0 (mod ~y$r_buff1_thd0~0_In1717428532 256))) (.cse3 (= (mod ~y$w_buff1_used~0_In1717428532 256) 0))) (or (and (or .cse0 .cse1) (= ~y$w_buff1_used~0_In1717428532 |ULTIMATE.start_main_#t~ite21_Out1717428532|) (or .cse2 .cse3)) (and (= 0 |ULTIMATE.start_main_#t~ite21_Out1717428532|) (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3)))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1717428532, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1717428532, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1717428532, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1717428532} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1717428532, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1717428532, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out1717428532|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1717428532, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1717428532} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-11-28 18:33:25,156 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [680] [680] L815-->L815-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In1244165971 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In1244165971 256)))) (or (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite22_Out1244165971|) (not .cse1)) (and (= |ULTIMATE.start_main_#t~ite22_Out1244165971| ~y$r_buff0_thd0~0_In1244165971) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1244165971, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1244165971} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1244165971, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1244165971, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out1244165971|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-11-28 18:33:25,157 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [686] [686] L816-->L816-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In-1057205023 256))) (.cse1 (= (mod ~y$w_buff1_used~0_In-1057205023 256) 0)) (.cse3 (= (mod ~y$w_buff0_used~0_In-1057205023 256) 0)) (.cse2 (= (mod ~y$r_buff0_thd0~0_In-1057205023 256) 0))) (or (and (= 0 |ULTIMATE.start_main_#t~ite23_Out-1057205023|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (= ~y$r_buff1_thd0~0_In-1057205023 |ULTIMATE.start_main_#t~ite23_Out-1057205023|) (or .cse3 .cse2)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1057205023, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1057205023, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1057205023, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1057205023} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1057205023, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1057205023, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1057205023, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out-1057205023|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1057205023} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-11-28 18:33:25,160 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L827-->L827-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In2065715451 256) 0))) (or (and (not .cse0) (= ~y$w_buff1_used~0_In2065715451 |ULTIMATE.start_main_#t~ite39_Out2065715451|) (= |ULTIMATE.start_main_#t~ite38_In2065715451| |ULTIMATE.start_main_#t~ite38_Out2065715451|)) (and (= ~y$w_buff1_used~0_In2065715451 |ULTIMATE.start_main_#t~ite38_Out2065715451|) .cse0 (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In2065715451 256) 0))) (or (and (= (mod ~y$r_buff1_thd0~0_In2065715451 256) 0) .cse1) (= 0 (mod ~y$w_buff0_used~0_In2065715451 256)) (and (= 0 (mod ~y$w_buff1_used~0_In2065715451 256)) .cse1))) (= |ULTIMATE.start_main_#t~ite38_Out2065715451| |ULTIMATE.start_main_#t~ite39_Out2065715451|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In2065715451, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In2065715451, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_In2065715451|, ~weak$$choice2~0=~weak$$choice2~0_In2065715451, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In2065715451, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2065715451} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In2065715451, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out2065715451|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In2065715451, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_Out2065715451|, ~weak$$choice2~0=~weak$$choice2~0_In2065715451, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In2065715451, ~y$w_buff1_used~0=~y$w_buff1_used~0_In2065715451} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite38] because there is no mapped edge [2019-11-28 18:33:25,160 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [649] [649] L828-->L829: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_25 256))) (= v_~y$r_buff0_thd0~0_98 v_~y$r_buff0_thd0~0_97)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_98, ~weak$$choice2~0=v_~weak$$choice2~0_25} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_13|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_8|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_97, ~weak$$choice2~0=v_~weak$$choice2~0_25, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-11-28 18:33:25,161 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [706] [706] L831-->L4: Formula: (and (= v_~y~0_99 v_~y$mem_tmp~0_10) (not (= (mod v_~y$flush_delayed~0_27 256) 0)) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4| (mod v_~main$tmp_guard1~0_12 256)) (= 0 v_~y$flush_delayed~0_26)) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_10, ~y$flush_delayed~0=v_~y$flush_delayed~0_27, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_10, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_9, ~y$flush_delayed~0=v_~y$flush_delayed~0_26, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_24|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12, ~y~0=v_~y~0_99, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ~y$flush_delayed~0, ULTIMATE.start_main_#t~ite46, ~y~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-11-28 18:33:25,161 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [709] [709] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-11-28 18:33:25,273 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2019-11-28 18:33:25,273 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-28 18:33:25,278 INFO L168 Benchmark]: Toolchain (without parser) took 27174.98 ms. Allocated memory was 1.0 GB in the beginning and 2.1 GB in the end (delta: 1.1 GB). Free memory was 960.4 MB in the beginning and 686.8 MB in the end (delta: 273.6 MB). Peak memory consumption was 1.4 GB. Max. memory is 11.5 GB. [2019-11-28 18:33:25,278 INFO L168 Benchmark]: CDTParser took 0.86 ms. Allocated memory is still 1.0 GB. Free memory is still 987.2 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 18:33:25,279 INFO L168 Benchmark]: CACSL2BoogieTranslator took 743.90 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 152.6 MB). Free memory was 955.0 MB in the beginning and 1.1 GB in the end (delta: -159.4 MB). Peak memory consumption was 20.5 MB. Max. memory is 11.5 GB. [2019-11-28 18:33:25,279 INFO L168 Benchmark]: Boogie Procedure Inliner took 73.63 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.6 MB). Peak memory consumption was 6.6 MB. Max. memory is 11.5 GB. [2019-11-28 18:33:25,283 INFO L168 Benchmark]: Boogie Preprocessor took 42.83 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 18:33:25,286 INFO L168 Benchmark]: RCFGBuilder took 732.65 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 51.5 MB). Peak memory consumption was 51.5 MB. Max. memory is 11.5 GB. [2019-11-28 18:33:25,287 INFO L168 Benchmark]: TraceAbstraction took 25447.20 ms. Allocated memory was 1.2 GB in the beginning and 2.1 GB in the end (delta: 952.6 MB). Free memory was 1.1 GB in the beginning and 706.6 MB in the end (delta: 349.7 MB). Peak memory consumption was 1.3 GB. Max. memory is 11.5 GB. [2019-11-28 18:33:25,287 INFO L168 Benchmark]: Witness Printer took 129.28 ms. Allocated memory is still 2.1 GB. Free memory was 706.6 MB in the beginning and 686.8 MB in the end (delta: 19.8 MB). Peak memory consumption was 19.8 MB. Max. memory is 11.5 GB. [2019-11-28 18:33:25,293 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.86 ms. Allocated memory is still 1.0 GB. Free memory is still 987.2 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 743.90 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 152.6 MB). Free memory was 955.0 MB in the beginning and 1.1 GB in the end (delta: -159.4 MB). Peak memory consumption was 20.5 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 73.63 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.6 MB). Peak memory consumption was 6.6 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 42.83 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 732.65 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 51.5 MB). Peak memory consumption was 51.5 MB. Max. memory is 11.5 GB. * TraceAbstraction took 25447.20 ms. Allocated memory was 1.2 GB in the beginning and 2.1 GB in the end (delta: 952.6 MB). Free memory was 1.1 GB in the beginning and 706.6 MB in the end (delta: 349.7 MB). Peak memory consumption was 1.3 GB. Max. memory is 11.5 GB. * Witness Printer took 129.28 ms. Allocated memory is still 2.1 GB. Free memory was 706.6 MB in the beginning and 686.8 MB in the end (delta: 19.8 MB). Peak memory consumption was 19.8 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 5.1s, 162 ProgramPointsBefore, 83 ProgramPointsAfterwards, 193 TransitionsBefore, 94 TransitionsAfterwards, 11490 CoEnabledTransitionPairs, 7 FixpointIterations, 31 TrivialSequentialCompositions, 43 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 37 ConcurrentYvCompositions, 24 ChoiceCompositions, 4225 VarBasedMoverChecksPositive, 199 VarBasedMoverChecksNegative, 61 SemBasedMoverChecksPositive, 194 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 1.2s, 0 MoverChecksTotal, 48124 CheckedPairsTotal, 111 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L802] FCALL, FORK 0 pthread_create(&t2516, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L804] FCALL, FORK 0 pthread_create(&t2517, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L806] FCALL, FORK 0 pthread_create(&t2518, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L769] 3 y$r_buff1_thd0 = y$r_buff0_thd0 [L770] 3 y$r_buff1_thd1 = y$r_buff0_thd1 [L771] 3 y$r_buff1_thd2 = y$r_buff0_thd2 [L772] 3 y$r_buff1_thd3 = y$r_buff0_thd3 [L773] 3 y$r_buff0_thd3 = (_Bool)1 [L776] 3 z = 1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L779] EXPR 3 y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L744] 2 x = 1 [L747] 2 y = 1 VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L779] 3 y = y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) [L750] EXPR 2 y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L780] 3 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : y$w_buff0_used [L750] 2 y = y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) [L751] 2 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$w_buff0_used [L752] 2 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used [L753] 2 y$r_buff0_thd2 = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$r_buff0_thd2 [L781] 3 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd3 || y$w_buff1_used && y$r_buff1_thd3 ? (_Bool)0 : y$w_buff1_used [L812] EXPR 0 y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L812] 0 y = y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) [L813] 0 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used [L814] 0 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$w_buff1_used [L815] 0 y$r_buff0_thd0 = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$r_buff0_thd0 [L816] 0 y$r_buff1_thd0 = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$r_buff1_thd0 [L819] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L820] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L821] 0 y$flush_delayed = weak$$choice2 [L822] 0 y$mem_tmp = y VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L823] EXPR 0 !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L823] 0 y = !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) [L824] EXPR 0 weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L824] 0 y$w_buff0 = weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) [L825] EXPR 0 weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L825] 0 y$w_buff1 = weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) [L826] EXPR 0 weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L826] 0 y$w_buff0_used = weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) [L827] 0 y$w_buff1_used = weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L829] EXPR 0 weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L829] 0 y$r_buff1_thd0 = weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L830] 0 main$tmp_guard1 = !(y == 2 && z == 2 && __unbuffered_p0_EAX == 0) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 153 locations, 2 error locations. Result: UNSAFE, OverallTime: 25.1s, OverallIterations: 20, TraceHistogramMax: 1, AutomataDifference: 8.6s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 2077 SDtfs, 2551 SDslu, 6538 SDs, 0 SdLazy, 4295 SolverSat, 261 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 3.9s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 246 GetRequests, 33 SyntacticMatches, 16 SemanticMatches, 197 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 784 ImplicationChecksByTransitivity, 3.4s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=26410occurred in iteration=5, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 5.4s AutomataMinimizationTime, 19 MinimizatonAttempts, 19457 StatesRemovedByMinimization, 15 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.5s SatisfiabilityAnalysisTime, 3.2s InterpolantComputationTime, 848 NumberOfCodeBlocks, 848 NumberOfCodeBlocksAsserted, 20 NumberOfCheckSat, 772 ConstructedInterpolants, 0 QuantifiedInterpolants, 182977 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 19 InterpolantComputations, 19 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...