./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/pthread-wmm/safe031_pso.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx12G -Xms1G -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/pthread-wmm/safe031_pso.opt.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e9c308ebb550e1fb0f7b53d2bde00a7623abfa26 .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-11-28 18:32:58,076 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-28 18:32:58,078 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-28 18:32:58,091 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-28 18:32:58,092 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-28 18:32:58,093 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-28 18:32:58,095 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-28 18:32:58,097 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-28 18:32:58,099 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-28 18:32:58,100 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-28 18:32:58,101 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-28 18:32:58,103 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-28 18:32:58,103 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-28 18:32:58,104 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-28 18:32:58,105 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-28 18:32:58,107 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-28 18:32:58,108 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-28 18:32:58,109 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-28 18:32:58,111 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-28 18:32:58,113 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-28 18:32:58,115 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-28 18:32:58,116 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-28 18:32:58,118 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-28 18:32:58,119 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-28 18:32:58,121 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-28 18:32:58,121 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-28 18:32:58,122 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-28 18:32:58,123 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-28 18:32:58,123 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-28 18:32:58,125 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-28 18:32:58,125 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-28 18:32:58,126 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-28 18:32:58,127 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-28 18:32:58,128 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-28 18:32:58,129 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-28 18:32:58,129 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-28 18:32:58,130 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-28 18:32:58,130 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-28 18:32:58,131 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-28 18:32:58,132 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-28 18:32:58,132 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-28 18:32:58,133 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-28 18:32:58,160 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-28 18:32:58,161 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-28 18:32:58,163 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-28 18:32:58,164 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-28 18:32:58,164 INFO L138 SettingsManager]: * Use SBE=true [2019-11-28 18:32:58,164 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-28 18:32:58,165 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-28 18:32:58,165 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-28 18:32:58,165 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-28 18:32:58,165 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-28 18:32:58,167 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-28 18:32:58,167 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-28 18:32:58,167 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-28 18:32:58,168 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-28 18:32:58,168 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-28 18:32:58,168 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-28 18:32:58,169 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-28 18:32:58,169 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-28 18:32:58,169 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-28 18:32:58,169 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-28 18:32:58,170 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-28 18:32:58,170 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 18:32:58,171 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-28 18:32:58,171 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-28 18:32:58,171 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-28 18:32:58,171 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-28 18:32:58,172 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-28 18:32:58,172 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-28 18:32:58,172 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-11-28 18:32:58,172 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e9c308ebb550e1fb0f7b53d2bde00a7623abfa26 [2019-11-28 18:32:58,463 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-28 18:32:58,482 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-28 18:32:58,486 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-28 18:32:58,488 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-28 18:32:58,488 INFO L275 PluginConnector]: CDTParser initialized [2019-11-28 18:32:58,490 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/pthread-wmm/safe031_pso.opt.i [2019-11-28 18:32:58,565 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/22bac37cf/47606706d45b4995b93353713c20f903/FLAGc17bfe1d9 [2019-11-28 18:32:59,203 INFO L306 CDTParser]: Found 1 translation units. [2019-11-28 18:32:59,204 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/pthread-wmm/safe031_pso.opt.i [2019-11-28 18:32:59,222 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/22bac37cf/47606706d45b4995b93353713c20f903/FLAGc17bfe1d9 [2019-11-28 18:32:59,416 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/22bac37cf/47606706d45b4995b93353713c20f903 [2019-11-28 18:32:59,420 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-28 18:32:59,421 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-28 18:32:59,423 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-28 18:32:59,423 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-28 18:32:59,427 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-28 18:32:59,428 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 06:32:59" (1/1) ... [2019-11-28 18:32:59,431 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@38a57ec0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:32:59, skipping insertion in model container [2019-11-28 18:32:59,431 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 06:32:59" (1/1) ... [2019-11-28 18:32:59,439 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-11-28 18:32:59,508 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-11-28 18:33:00,032 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 18:33:00,053 INFO L203 MainTranslator]: Completed pre-run [2019-11-28 18:33:00,114 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 18:33:00,186 INFO L208 MainTranslator]: Completed translation [2019-11-28 18:33:00,186 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:33:00 WrapperNode [2019-11-28 18:33:00,187 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-28 18:33:00,188 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-28 18:33:00,188 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-28 18:33:00,188 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-28 18:33:00,197 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:33:00" (1/1) ... [2019-11-28 18:33:00,224 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:33:00" (1/1) ... [2019-11-28 18:33:00,272 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-28 18:33:00,272 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-28 18:33:00,272 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-28 18:33:00,273 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-28 18:33:00,283 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:33:00" (1/1) ... [2019-11-28 18:33:00,283 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:33:00" (1/1) ... [2019-11-28 18:33:00,288 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:33:00" (1/1) ... [2019-11-28 18:33:00,289 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:33:00" (1/1) ... [2019-11-28 18:33:00,299 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:33:00" (1/1) ... [2019-11-28 18:33:00,304 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:33:00" (1/1) ... [2019-11-28 18:33:00,307 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:33:00" (1/1) ... [2019-11-28 18:33:00,312 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-28 18:33:00,313 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-28 18:33:00,313 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-28 18:33:00,313 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-28 18:33:00,314 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:33:00" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 18:33:00,395 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-11-28 18:33:00,396 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-11-28 18:33:00,396 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-11-28 18:33:00,396 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-11-28 18:33:00,396 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-11-28 18:33:00,396 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-11-28 18:33:00,397 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-11-28 18:33:00,397 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-11-28 18:33:00,397 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-11-28 18:33:00,397 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-11-28 18:33:00,398 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-11-28 18:33:00,398 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-28 18:33:00,398 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-28 18:33:00,400 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-11-28 18:33:01,135 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-28 18:33:01,136 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-11-28 18:33:01,137 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:33:01 BoogieIcfgContainer [2019-11-28 18:33:01,137 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-28 18:33:01,138 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-28 18:33:01,138 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-28 18:33:01,142 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-28 18:33:01,142 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 06:32:59" (1/3) ... [2019-11-28 18:33:01,143 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@30bc29d2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 06:33:01, skipping insertion in model container [2019-11-28 18:33:01,143 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 06:33:00" (2/3) ... [2019-11-28 18:33:01,144 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@30bc29d2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 06:33:01, skipping insertion in model container [2019-11-28 18:33:01,144 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:33:01" (3/3) ... [2019-11-28 18:33:01,146 INFO L109 eAbstractionObserver]: Analyzing ICFG safe031_pso.opt.i [2019-11-28 18:33:01,156 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-11-28 18:33:01,157 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-28 18:33:01,169 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-11-28 18:33:01,170 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-11-28 18:33:01,210 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,210 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,210 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,211 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,211 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,211 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,212 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,212 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,212 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,212 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,213 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,213 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,213 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,214 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,214 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,214 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,215 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,215 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,215 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,215 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,216 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,216 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,216 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,218 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,218 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,219 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,219 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,219 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,219 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,220 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,223 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,223 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,224 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,224 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,225 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,225 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,227 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,227 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,228 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,229 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,229 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,229 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,230 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,232 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,233 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,233 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,233 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,234 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,235 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,235 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,236 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,236 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,236 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,237 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,237 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,237 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,237 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,238 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,238 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,238 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,239 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,239 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,239 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,240 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,240 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,240 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,241 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,241 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,242 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,242 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-11-28 18:33:01,260 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-11-28 18:33:01,277 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-28 18:33:01,277 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-28 18:33:01,277 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-28 18:33:01,278 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-28 18:33:01,278 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-28 18:33:01,278 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-28 18:33:01,278 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-28 18:33:01,278 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-28 18:33:01,298 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 162 places, 193 transitions [2019-11-28 18:33:01,301 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 162 places, 193 transitions [2019-11-28 18:33:01,397 INFO L134 PetriNetUnfolder]: 41/190 cut-off events. [2019-11-28 18:33:01,397 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-11-28 18:33:01,414 INFO L76 FinitePrefix]: Finished finitePrefix Result has 200 conditions, 190 events. 41/190 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 476 event pairs. 9/156 useless extension candidates. Maximal degree in co-relation 161. Up to 2 conditions per place. [2019-11-28 18:33:01,437 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 162 places, 193 transitions [2019-11-28 18:33:01,487 INFO L134 PetriNetUnfolder]: 41/190 cut-off events. [2019-11-28 18:33:01,488 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-11-28 18:33:01,496 INFO L76 FinitePrefix]: Finished finitePrefix Result has 200 conditions, 190 events. 41/190 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 476 event pairs. 9/156 useless extension candidates. Maximal degree in co-relation 161. Up to 2 conditions per place. [2019-11-28 18:33:01,514 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 11490 [2019-11-28 18:33:01,515 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-11-28 18:33:06,442 WARN L192 SmtUtils]: Spent 284.00 ms on a formula simplification. DAG size of input: 87 DAG size of output: 85 [2019-11-28 18:33:06,572 WARN L192 SmtUtils]: Spent 126.00 ms on a formula simplification that was a NOOP. DAG size: 83 [2019-11-28 18:33:06,608 INFO L206 etLargeBlockEncoding]: Checked pairs total: 48124 [2019-11-28 18:33:06,610 INFO L214 etLargeBlockEncoding]: Total number of compositions: 111 [2019-11-28 18:33:06,621 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 83 places, 94 transitions [2019-11-28 18:33:08,390 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 15710 states. [2019-11-28 18:33:08,393 INFO L276 IsEmpty]: Start isEmpty. Operand 15710 states. [2019-11-28 18:33:08,402 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2019-11-28 18:33:08,403 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:08,404 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:08,405 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:08,412 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:08,413 INFO L82 PathProgramCache]: Analyzing trace with hash 2126234855, now seen corresponding path program 1 times [2019-11-28 18:33:08,423 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:08,424 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [609686737] [2019-11-28 18:33:08,424 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:08,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:08,761 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:08,762 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [609686737] [2019-11-28 18:33:08,763 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:08,763 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-11-28 18:33:08,764 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1786124745] [2019-11-28 18:33:08,768 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:33:08,768 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:08,779 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:33:08,780 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:33:08,782 INFO L87 Difference]: Start difference. First operand 15710 states. Second operand 3 states. [2019-11-28 18:33:09,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:09,224 INFO L93 Difference]: Finished difference Result 15638 states and 59348 transitions. [2019-11-28 18:33:09,225 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:33:09,226 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2019-11-28 18:33:09,227 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:09,409 INFO L225 Difference]: With dead ends: 15638 [2019-11-28 18:33:09,410 INFO L226 Difference]: Without dead ends: 15326 [2019-11-28 18:33:09,411 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:33:09,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15326 states. [2019-11-28 18:33:10,325 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15326 to 15326. [2019-11-28 18:33:10,327 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15326 states. [2019-11-28 18:33:10,412 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15326 states to 15326 states and 58230 transitions. [2019-11-28 18:33:10,414 INFO L78 Accepts]: Start accepts. Automaton has 15326 states and 58230 transitions. Word has length 7 [2019-11-28 18:33:10,416 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:10,416 INFO L462 AbstractCegarLoop]: Abstraction has 15326 states and 58230 transitions. [2019-11-28 18:33:10,417 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:33:10,417 INFO L276 IsEmpty]: Start isEmpty. Operand 15326 states and 58230 transitions. [2019-11-28 18:33:10,427 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-11-28 18:33:10,428 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:10,428 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:10,429 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:10,429 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:10,429 INFO L82 PathProgramCache]: Analyzing trace with hash -380072381, now seen corresponding path program 1 times [2019-11-28 18:33:10,429 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:10,430 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2092708328] [2019-11-28 18:33:10,430 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:10,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:10,595 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:10,595 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2092708328] [2019-11-28 18:33:10,596 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:10,596 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:33:10,596 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1591859499] [2019-11-28 18:33:10,599 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:33:10,599 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:10,599 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:33:10,599 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:33:10,600 INFO L87 Difference]: Start difference. First operand 15326 states and 58230 transitions. Second operand 4 states. [2019-11-28 18:33:11,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:11,110 INFO L93 Difference]: Finished difference Result 24490 states and 89350 transitions. [2019-11-28 18:33:11,111 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:33:11,111 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-11-28 18:33:11,112 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:11,231 INFO L225 Difference]: With dead ends: 24490 [2019-11-28 18:33:11,232 INFO L226 Difference]: Without dead ends: 24476 [2019-11-28 18:33:11,233 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:33:11,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24476 states. [2019-11-28 18:33:12,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24476 to 22206. [2019-11-28 18:33:12,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22206 states. [2019-11-28 18:33:12,477 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22206 states to 22206 states and 82052 transitions. [2019-11-28 18:33:12,478 INFO L78 Accepts]: Start accepts. Automaton has 22206 states and 82052 transitions. Word has length 13 [2019-11-28 18:33:12,478 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:12,479 INFO L462 AbstractCegarLoop]: Abstraction has 22206 states and 82052 transitions. [2019-11-28 18:33:12,479 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:33:12,479 INFO L276 IsEmpty]: Start isEmpty. Operand 22206 states and 82052 transitions. [2019-11-28 18:33:12,481 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-11-28 18:33:12,481 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:12,481 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:12,482 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:12,482 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:12,483 INFO L82 PathProgramCache]: Analyzing trace with hash 691839138, now seen corresponding path program 1 times [2019-11-28 18:33:12,483 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:12,483 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2097796807] [2019-11-28 18:33:12,484 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:12,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:12,551 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:12,551 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2097796807] [2019-11-28 18:33:12,551 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:12,552 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:33:12,553 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1650357017] [2019-11-28 18:33:12,553 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:33:12,554 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:12,554 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:33:12,555 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:33:12,555 INFO L87 Difference]: Start difference. First operand 22206 states and 82052 transitions. Second operand 4 states. [2019-11-28 18:33:12,883 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:12,883 INFO L93 Difference]: Finished difference Result 27876 states and 102039 transitions. [2019-11-28 18:33:12,884 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:33:12,884 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-11-28 18:33:12,884 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:12,990 INFO L225 Difference]: With dead ends: 27876 [2019-11-28 18:33:12,990 INFO L226 Difference]: Without dead ends: 27876 [2019-11-28 18:33:12,991 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:33:13,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27876 states. [2019-11-28 18:33:13,808 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27876 to 24582. [2019-11-28 18:33:13,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24582 states. [2019-11-28 18:33:13,929 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24582 states to 24582 states and 90664 transitions. [2019-11-28 18:33:13,929 INFO L78 Accepts]: Start accepts. Automaton has 24582 states and 90664 transitions. Word has length 13 [2019-11-28 18:33:13,930 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:13,930 INFO L462 AbstractCegarLoop]: Abstraction has 24582 states and 90664 transitions. [2019-11-28 18:33:13,930 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:33:13,932 INFO L276 IsEmpty]: Start isEmpty. Operand 24582 states and 90664 transitions. [2019-11-28 18:33:14,391 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-11-28 18:33:14,391 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:14,391 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:14,391 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:14,392 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:14,392 INFO L82 PathProgramCache]: Analyzing trace with hash -165939970, now seen corresponding path program 1 times [2019-11-28 18:33:14,392 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:14,393 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [348395501] [2019-11-28 18:33:14,393 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:14,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:14,541 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:14,542 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [348395501] [2019-11-28 18:33:14,544 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:14,544 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:33:14,545 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [327029776] [2019-11-28 18:33:14,545 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:33:14,545 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:14,545 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:33:14,546 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:33:14,546 INFO L87 Difference]: Start difference. First operand 24582 states and 90664 transitions. Second operand 5 states. [2019-11-28 18:33:15,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:15,079 INFO L93 Difference]: Finished difference Result 33300 states and 120391 transitions. [2019-11-28 18:33:15,080 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-11-28 18:33:15,081 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-11-28 18:33:15,081 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:15,215 INFO L225 Difference]: With dead ends: 33300 [2019-11-28 18:33:15,215 INFO L226 Difference]: Without dead ends: 33286 [2019-11-28 18:33:15,216 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-11-28 18:33:15,424 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33286 states. [2019-11-28 18:33:15,927 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33286 to 24486. [2019-11-28 18:33:15,928 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24486 states. [2019-11-28 18:33:16,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24486 states to 24486 states and 90098 transitions. [2019-11-28 18:33:16,014 INFO L78 Accepts]: Start accepts. Automaton has 24486 states and 90098 transitions. Word has length 19 [2019-11-28 18:33:16,015 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:16,015 INFO L462 AbstractCegarLoop]: Abstraction has 24486 states and 90098 transitions. [2019-11-28 18:33:16,015 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:33:16,015 INFO L276 IsEmpty]: Start isEmpty. Operand 24486 states and 90098 transitions. [2019-11-28 18:33:16,045 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-11-28 18:33:16,046 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:16,046 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:16,047 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:16,047 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:16,047 INFO L82 PathProgramCache]: Analyzing trace with hash -1278693284, now seen corresponding path program 1 times [2019-11-28 18:33:16,047 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:16,048 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1337146541] [2019-11-28 18:33:16,048 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:16,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:16,088 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:16,088 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1337146541] [2019-11-28 18:33:16,089 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:16,089 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:33:16,089 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1985334829] [2019-11-28 18:33:16,090 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:33:16,090 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:16,091 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:33:16,091 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:33:16,091 INFO L87 Difference]: Start difference. First operand 24486 states and 90098 transitions. Second operand 3 states. [2019-11-28 18:33:16,788 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:16,789 INFO L93 Difference]: Finished difference Result 29936 states and 108805 transitions. [2019-11-28 18:33:16,789 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:33:16,789 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-11-28 18:33:16,789 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:16,890 INFO L225 Difference]: With dead ends: 29936 [2019-11-28 18:33:16,891 INFO L226 Difference]: Without dead ends: 29936 [2019-11-28 18:33:16,891 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:33:17,040 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29936 states. [2019-11-28 18:33:17,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29936 to 26410. [2019-11-28 18:33:17,532 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26410 states. [2019-11-28 18:33:17,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26410 states to 26410 states and 96908 transitions. [2019-11-28 18:33:17,604 INFO L78 Accepts]: Start accepts. Automaton has 26410 states and 96908 transitions. Word has length 27 [2019-11-28 18:33:17,604 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:17,605 INFO L462 AbstractCegarLoop]: Abstraction has 26410 states and 96908 transitions. [2019-11-28 18:33:17,605 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:33:17,605 INFO L276 IsEmpty]: Start isEmpty. Operand 26410 states and 96908 transitions. [2019-11-28 18:33:17,627 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-11-28 18:33:17,628 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:17,628 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:17,628 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:17,629 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:17,629 INFO L82 PathProgramCache]: Analyzing trace with hash -1374888423, now seen corresponding path program 1 times [2019-11-28 18:33:17,629 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:17,630 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [80851912] [2019-11-28 18:33:17,630 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:17,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:17,680 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:17,680 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [80851912] [2019-11-28 18:33:17,680 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:17,681 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:33:17,681 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1235023466] [2019-11-28 18:33:17,681 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:33:17,681 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:17,682 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:33:17,682 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:33:17,682 INFO L87 Difference]: Start difference. First operand 26410 states and 96908 transitions. Second operand 3 states. [2019-11-28 18:33:17,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:17,739 INFO L93 Difference]: Finished difference Result 15137 states and 48090 transitions. [2019-11-28 18:33:17,739 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:33:17,739 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-11-28 18:33:17,739 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:17,762 INFO L225 Difference]: With dead ends: 15137 [2019-11-28 18:33:17,763 INFO L226 Difference]: Without dead ends: 15137 [2019-11-28 18:33:17,763 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:33:17,821 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15137 states. [2019-11-28 18:33:18,036 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15137 to 15137. [2019-11-28 18:33:18,036 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15137 states. [2019-11-28 18:33:18,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15137 states to 15137 states and 48090 transitions. [2019-11-28 18:33:18,070 INFO L78 Accepts]: Start accepts. Automaton has 15137 states and 48090 transitions. Word has length 27 [2019-11-28 18:33:18,070 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:18,070 INFO L462 AbstractCegarLoop]: Abstraction has 15137 states and 48090 transitions. [2019-11-28 18:33:18,070 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:33:18,070 INFO L276 IsEmpty]: Start isEmpty. Operand 15137 states and 48090 transitions. [2019-11-28 18:33:18,078 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-11-28 18:33:18,078 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:18,078 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:18,079 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:18,079 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:18,079 INFO L82 PathProgramCache]: Analyzing trace with hash 783683513, now seen corresponding path program 1 times [2019-11-28 18:33:18,079 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:18,079 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [795356667] [2019-11-28 18:33:18,080 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:18,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:18,135 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:18,136 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [795356667] [2019-11-28 18:33:18,136 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:18,136 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 18:33:18,136 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1562031223] [2019-11-28 18:33:18,137 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 18:33:18,137 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:18,137 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 18:33:18,137 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:33:18,137 INFO L87 Difference]: Start difference. First operand 15137 states and 48090 transitions. Second operand 4 states. [2019-11-28 18:33:18,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:18,160 INFO L93 Difference]: Finished difference Result 2291 states and 5311 transitions. [2019-11-28 18:33:18,160 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-28 18:33:18,160 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 28 [2019-11-28 18:33:18,161 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:18,164 INFO L225 Difference]: With dead ends: 2291 [2019-11-28 18:33:18,164 INFO L226 Difference]: Without dead ends: 2291 [2019-11-28 18:33:18,164 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-11-28 18:33:18,170 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2291 states. [2019-11-28 18:33:18,187 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2291 to 2291. [2019-11-28 18:33:18,188 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2291 states. [2019-11-28 18:33:18,192 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2291 states to 2291 states and 5311 transitions. [2019-11-28 18:33:18,192 INFO L78 Accepts]: Start accepts. Automaton has 2291 states and 5311 transitions. Word has length 28 [2019-11-28 18:33:18,192 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:18,192 INFO L462 AbstractCegarLoop]: Abstraction has 2291 states and 5311 transitions. [2019-11-28 18:33:18,192 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 18:33:18,193 INFO L276 IsEmpty]: Start isEmpty. Operand 2291 states and 5311 transitions. [2019-11-28 18:33:18,195 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2019-11-28 18:33:18,195 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:18,195 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:18,196 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:18,196 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:18,196 INFO L82 PathProgramCache]: Analyzing trace with hash 1644769556, now seen corresponding path program 1 times [2019-11-28 18:33:18,196 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:18,196 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [500963237] [2019-11-28 18:33:18,197 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:18,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:18,299 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:18,300 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [500963237] [2019-11-28 18:33:18,300 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:18,300 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 18:33:18,300 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [719262115] [2019-11-28 18:33:18,301 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:33:18,301 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:18,301 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:33:18,301 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:33:18,301 INFO L87 Difference]: Start difference. First operand 2291 states and 5311 transitions. Second operand 5 states. [2019-11-28 18:33:18,322 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:18,323 INFO L93 Difference]: Finished difference Result 653 states and 1502 transitions. [2019-11-28 18:33:18,323 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:33:18,323 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 40 [2019-11-28 18:33:18,323 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:18,324 INFO L225 Difference]: With dead ends: 653 [2019-11-28 18:33:18,324 INFO L226 Difference]: Without dead ends: 653 [2019-11-28 18:33:18,325 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:33:18,327 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 653 states. [2019-11-28 18:33:18,333 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 653 to 597. [2019-11-28 18:33:18,333 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 597 states. [2019-11-28 18:33:18,334 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 597 states to 597 states and 1370 transitions. [2019-11-28 18:33:18,334 INFO L78 Accepts]: Start accepts. Automaton has 597 states and 1370 transitions. Word has length 40 [2019-11-28 18:33:18,336 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:18,336 INFO L462 AbstractCegarLoop]: Abstraction has 597 states and 1370 transitions. [2019-11-28 18:33:18,336 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:33:18,336 INFO L276 IsEmpty]: Start isEmpty. Operand 597 states and 1370 transitions. [2019-11-28 18:33:18,339 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-11-28 18:33:18,339 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:18,339 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:18,340 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:18,340 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:18,340 INFO L82 PathProgramCache]: Analyzing trace with hash -922835002, now seen corresponding path program 1 times [2019-11-28 18:33:18,340 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:18,341 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [300202759] [2019-11-28 18:33:18,341 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:18,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:18,441 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:18,441 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [300202759] [2019-11-28 18:33:18,442 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:18,442 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:33:18,442 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1684797537] [2019-11-28 18:33:18,443 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:33:18,443 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:18,443 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:33:18,443 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:33:18,443 INFO L87 Difference]: Start difference. First operand 597 states and 1370 transitions. Second operand 3 states. [2019-11-28 18:33:18,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:18,457 INFO L93 Difference]: Finished difference Result 597 states and 1346 transitions. [2019-11-28 18:33:18,458 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:33:18,458 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 55 [2019-11-28 18:33:18,458 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:18,459 INFO L225 Difference]: With dead ends: 597 [2019-11-28 18:33:18,459 INFO L226 Difference]: Without dead ends: 597 [2019-11-28 18:33:18,459 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:33:18,461 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 597 states. [2019-11-28 18:33:18,466 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 597 to 597. [2019-11-28 18:33:18,467 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 597 states. [2019-11-28 18:33:18,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 597 states to 597 states and 1346 transitions. [2019-11-28 18:33:18,468 INFO L78 Accepts]: Start accepts. Automaton has 597 states and 1346 transitions. Word has length 55 [2019-11-28 18:33:18,468 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:18,468 INFO L462 AbstractCegarLoop]: Abstraction has 597 states and 1346 transitions. [2019-11-28 18:33:18,468 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:33:18,468 INFO L276 IsEmpty]: Start isEmpty. Operand 597 states and 1346 transitions. [2019-11-28 18:33:18,469 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-11-28 18:33:18,469 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:18,470 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:18,470 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:18,470 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:18,470 INFO L82 PathProgramCache]: Analyzing trace with hash -1916501781, now seen corresponding path program 1 times [2019-11-28 18:33:18,470 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:18,471 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1458330160] [2019-11-28 18:33:18,471 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:18,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:18,552 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:18,552 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1458330160] [2019-11-28 18:33:18,552 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:18,552 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 18:33:18,553 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [963290583] [2019-11-28 18:33:18,553 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:33:18,553 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:18,554 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:33:18,554 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:33:18,554 INFO L87 Difference]: Start difference. First operand 597 states and 1346 transitions. Second operand 5 states. [2019-11-28 18:33:18,739 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:18,740 INFO L93 Difference]: Finished difference Result 868 states and 1969 transitions. [2019-11-28 18:33:18,740 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 18:33:18,740 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 56 [2019-11-28 18:33:18,741 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:18,742 INFO L225 Difference]: With dead ends: 868 [2019-11-28 18:33:18,742 INFO L226 Difference]: Without dead ends: 868 [2019-11-28 18:33:18,743 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-11-28 18:33:18,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 868 states. [2019-11-28 18:33:18,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 868 to 766. [2019-11-28 18:33:18,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 766 states. [2019-11-28 18:33:18,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 766 states to 766 states and 1736 transitions. [2019-11-28 18:33:18,753 INFO L78 Accepts]: Start accepts. Automaton has 766 states and 1736 transitions. Word has length 56 [2019-11-28 18:33:18,753 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:18,753 INFO L462 AbstractCegarLoop]: Abstraction has 766 states and 1736 transitions. [2019-11-28 18:33:18,753 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:33:18,753 INFO L276 IsEmpty]: Start isEmpty. Operand 766 states and 1736 transitions. [2019-11-28 18:33:18,754 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-11-28 18:33:18,755 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:18,755 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:18,755 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:18,755 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:18,755 INFO L82 PathProgramCache]: Analyzing trace with hash 510672277, now seen corresponding path program 2 times [2019-11-28 18:33:18,755 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:18,756 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [385816017] [2019-11-28 18:33:18,756 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:18,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:18,847 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:18,847 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [385816017] [2019-11-28 18:33:18,848 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:18,848 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 18:33:18,848 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1507787328] [2019-11-28 18:33:18,849 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:33:18,849 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:18,850 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:33:18,851 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:33:18,851 INFO L87 Difference]: Start difference. First operand 766 states and 1736 transitions. Second operand 5 states. [2019-11-28 18:33:18,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:18,989 INFO L93 Difference]: Finished difference Result 939 states and 2124 transitions. [2019-11-28 18:33:18,989 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 18:33:18,989 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 56 [2019-11-28 18:33:18,990 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:18,993 INFO L225 Difference]: With dead ends: 939 [2019-11-28 18:33:18,993 INFO L226 Difference]: Without dead ends: 939 [2019-11-28 18:33:18,994 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-11-28 18:33:18,997 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 939 states. [2019-11-28 18:33:19,006 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 939 to 780. [2019-11-28 18:33:19,007 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 780 states. [2019-11-28 18:33:19,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 780 states to 780 states and 1769 transitions. [2019-11-28 18:33:19,010 INFO L78 Accepts]: Start accepts. Automaton has 780 states and 1769 transitions. Word has length 56 [2019-11-28 18:33:19,010 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:19,011 INFO L462 AbstractCegarLoop]: Abstraction has 780 states and 1769 transitions. [2019-11-28 18:33:19,011 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:33:19,011 INFO L276 IsEmpty]: Start isEmpty. Operand 780 states and 1769 transitions. [2019-11-28 18:33:19,014 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-11-28 18:33:19,015 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:19,015 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:19,015 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:19,016 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:19,016 INFO L82 PathProgramCache]: Analyzing trace with hash -1314270907, now seen corresponding path program 3 times [2019-11-28 18:33:19,016 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:19,017 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [629351054] [2019-11-28 18:33:19,017 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:19,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:19,285 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:19,286 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [629351054] [2019-11-28 18:33:19,286 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:19,286 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-11-28 18:33:19,287 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1301480992] [2019-11-28 18:33:19,287 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-11-28 18:33:19,287 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:19,288 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-11-28 18:33:19,288 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2019-11-28 18:33:19,288 INFO L87 Difference]: Start difference. First operand 780 states and 1769 transitions. Second operand 8 states. [2019-11-28 18:33:19,839 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:19,839 INFO L93 Difference]: Finished difference Result 1309 states and 2932 transitions. [2019-11-28 18:33:19,839 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-11-28 18:33:19,840 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 56 [2019-11-28 18:33:19,840 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:19,842 INFO L225 Difference]: With dead ends: 1309 [2019-11-28 18:33:19,842 INFO L226 Difference]: Without dead ends: 1309 [2019-11-28 18:33:19,843 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 9 SyntacticMatches, 2 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 29 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=59, Invalid=151, Unknown=0, NotChecked=0, Total=210 [2019-11-28 18:33:19,845 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1309 states. [2019-11-28 18:33:19,854 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1309 to 772. [2019-11-28 18:33:19,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 772 states. [2019-11-28 18:33:19,856 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 772 states to 772 states and 1743 transitions. [2019-11-28 18:33:19,856 INFO L78 Accepts]: Start accepts. Automaton has 772 states and 1743 transitions. Word has length 56 [2019-11-28 18:33:19,856 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:19,856 INFO L462 AbstractCegarLoop]: Abstraction has 772 states and 1743 transitions. [2019-11-28 18:33:19,856 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-11-28 18:33:19,856 INFO L276 IsEmpty]: Start isEmpty. Operand 772 states and 1743 transitions. [2019-11-28 18:33:19,858 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-11-28 18:33:19,858 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:19,858 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:19,858 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:19,858 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:19,858 INFO L82 PathProgramCache]: Analyzing trace with hash 69556479, now seen corresponding path program 4 times [2019-11-28 18:33:19,859 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:19,859 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [593021826] [2019-11-28 18:33:19,859 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:19,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:19,987 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:19,988 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [593021826] [2019-11-28 18:33:19,988 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:19,988 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 18:33:19,989 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [883786477] [2019-11-28 18:33:19,990 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 18:33:19,990 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:19,990 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 18:33:19,991 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 18:33:19,991 INFO L87 Difference]: Start difference. First operand 772 states and 1743 transitions. Second operand 5 states. [2019-11-28 18:33:20,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:20,048 INFO L93 Difference]: Finished difference Result 1120 states and 2349 transitions. [2019-11-28 18:33:20,049 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 18:33:20,049 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 56 [2019-11-28 18:33:20,050 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:20,051 INFO L225 Difference]: With dead ends: 1120 [2019-11-28 18:33:20,051 INFO L226 Difference]: Without dead ends: 703 [2019-11-28 18:33:20,051 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-28 18:33:20,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 703 states. [2019-11-28 18:33:20,066 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 703 to 703. [2019-11-28 18:33:20,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 703 states. [2019-11-28 18:33:20,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 703 states to 703 states and 1544 transitions. [2019-11-28 18:33:20,069 INFO L78 Accepts]: Start accepts. Automaton has 703 states and 1544 transitions. Word has length 56 [2019-11-28 18:33:20,069 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:20,070 INFO L462 AbstractCegarLoop]: Abstraction has 703 states and 1544 transitions. [2019-11-28 18:33:20,070 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 18:33:20,070 INFO L276 IsEmpty]: Start isEmpty. Operand 703 states and 1544 transitions. [2019-11-28 18:33:20,072 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2019-11-28 18:33:20,072 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:20,073 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:20,073 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:20,073 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:20,073 INFO L82 PathProgramCache]: Analyzing trace with hash -1040007325, now seen corresponding path program 5 times [2019-11-28 18:33:20,074 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:20,074 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1747272410] [2019-11-28 18:33:20,074 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:20,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:20,199 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:20,200 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1747272410] [2019-11-28 18:33:20,201 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:20,201 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 18:33:20,201 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1090848936] [2019-11-28 18:33:20,202 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 18:33:20,202 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:20,202 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 18:33:20,202 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:33:20,203 INFO L87 Difference]: Start difference. First operand 703 states and 1544 transitions. Second operand 3 states. [2019-11-28 18:33:20,247 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:20,247 INFO L93 Difference]: Finished difference Result 703 states and 1543 transitions. [2019-11-28 18:33:20,247 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 18:33:20,248 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 56 [2019-11-28 18:33:20,248 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:20,249 INFO L225 Difference]: With dead ends: 703 [2019-11-28 18:33:20,249 INFO L226 Difference]: Without dead ends: 703 [2019-11-28 18:33:20,250 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 18:33:20,252 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 703 states. [2019-11-28 18:33:20,260 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 703 to 542. [2019-11-28 18:33:20,260 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 542 states. [2019-11-28 18:33:20,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 542 states to 542 states and 1163 transitions. [2019-11-28 18:33:20,262 INFO L78 Accepts]: Start accepts. Automaton has 542 states and 1163 transitions. Word has length 56 [2019-11-28 18:33:20,262 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:20,262 INFO L462 AbstractCegarLoop]: Abstraction has 542 states and 1163 transitions. [2019-11-28 18:33:20,263 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 18:33:20,263 INFO L276 IsEmpty]: Start isEmpty. Operand 542 states and 1163 transitions. [2019-11-28 18:33:20,264 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:33:20,264 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:20,265 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:20,265 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:20,265 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:20,265 INFO L82 PathProgramCache]: Analyzing trace with hash 574299964, now seen corresponding path program 1 times [2019-11-28 18:33:20,266 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:20,266 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1070946498] [2019-11-28 18:33:20,266 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:20,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:20,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:20,686 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1070946498] [2019-11-28 18:33:20,686 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:20,686 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-11-28 18:33:20,687 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1214899619] [2019-11-28 18:33:20,687 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-11-28 18:33:20,687 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:20,687 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-11-28 18:33:20,688 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-11-28 18:33:20,688 INFO L87 Difference]: Start difference. First operand 542 states and 1163 transitions. Second operand 7 states. [2019-11-28 18:33:20,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:20,798 INFO L93 Difference]: Finished difference Result 788 states and 1653 transitions. [2019-11-28 18:33:20,799 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-11-28 18:33:20,799 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 57 [2019-11-28 18:33:20,799 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:20,800 INFO L225 Difference]: With dead ends: 788 [2019-11-28 18:33:20,800 INFO L226 Difference]: Without dead ends: 226 [2019-11-28 18:33:20,800 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=40, Invalid=70, Unknown=0, NotChecked=0, Total=110 [2019-11-28 18:33:20,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 226 states. [2019-11-28 18:33:20,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 226 to 202. [2019-11-28 18:33:20,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 202 states. [2019-11-28 18:33:20,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 202 states to 202 states and 344 transitions. [2019-11-28 18:33:20,807 INFO L78 Accepts]: Start accepts. Automaton has 202 states and 344 transitions. Word has length 57 [2019-11-28 18:33:20,807 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:20,807 INFO L462 AbstractCegarLoop]: Abstraction has 202 states and 344 transitions. [2019-11-28 18:33:20,807 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-11-28 18:33:20,807 INFO L276 IsEmpty]: Start isEmpty. Operand 202 states and 344 transitions. [2019-11-28 18:33:20,809 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:33:20,809 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:20,809 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:20,810 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:20,810 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:20,810 INFO L82 PathProgramCache]: Analyzing trace with hash -431408076, now seen corresponding path program 2 times [2019-11-28 18:33:20,810 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:20,810 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1147888657] [2019-11-28 18:33:20,811 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:20,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:21,117 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:21,118 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1147888657] [2019-11-28 18:33:21,118 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:21,118 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-11-28 18:33:21,119 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1224322493] [2019-11-28 18:33:21,119 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-11-28 18:33:21,119 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:21,119 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-11-28 18:33:21,120 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=149, Unknown=0, NotChecked=0, Total=182 [2019-11-28 18:33:21,120 INFO L87 Difference]: Start difference. First operand 202 states and 344 transitions. Second operand 14 states. [2019-11-28 18:33:21,719 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:21,720 INFO L93 Difference]: Finished difference Result 363 states and 608 transitions. [2019-11-28 18:33:21,720 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-11-28 18:33:21,720 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 57 [2019-11-28 18:33:21,721 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:21,721 INFO L225 Difference]: With dead ends: 363 [2019-11-28 18:33:21,721 INFO L226 Difference]: Without dead ends: 328 [2019-11-28 18:33:21,722 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 85 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=107, Invalid=493, Unknown=0, NotChecked=0, Total=600 [2019-11-28 18:33:21,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 328 states. [2019-11-28 18:33:21,726 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 328 to 298. [2019-11-28 18:33:21,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 298 states. [2019-11-28 18:33:21,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 298 states to 298 states and 508 transitions. [2019-11-28 18:33:21,727 INFO L78 Accepts]: Start accepts. Automaton has 298 states and 508 transitions. Word has length 57 [2019-11-28 18:33:21,728 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:21,728 INFO L462 AbstractCegarLoop]: Abstraction has 298 states and 508 transitions. [2019-11-28 18:33:21,728 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-11-28 18:33:21,728 INFO L276 IsEmpty]: Start isEmpty. Operand 298 states and 508 transitions. [2019-11-28 18:33:21,733 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:33:21,733 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:21,733 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:21,733 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:21,734 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:21,734 INFO L82 PathProgramCache]: Analyzing trace with hash 42803636, now seen corresponding path program 3 times [2019-11-28 18:33:21,734 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:21,735 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [738158465] [2019-11-28 18:33:21,735 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:21,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:22,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:22,056 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [738158465] [2019-11-28 18:33:22,056 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:22,056 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-11-28 18:33:22,056 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2110718927] [2019-11-28 18:33:22,058 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-11-28 18:33:22,058 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:22,058 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-11-28 18:33:22,059 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=151, Unknown=0, NotChecked=0, Total=182 [2019-11-28 18:33:22,059 INFO L87 Difference]: Start difference. First operand 298 states and 508 transitions. Second operand 14 states. [2019-11-28 18:33:22,660 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:22,660 INFO L93 Difference]: Finished difference Result 419 states and 694 transitions. [2019-11-28 18:33:22,661 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-11-28 18:33:22,661 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 57 [2019-11-28 18:33:22,661 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:22,662 INFO L225 Difference]: With dead ends: 419 [2019-11-28 18:33:22,662 INFO L226 Difference]: Without dead ends: 384 [2019-11-28 18:33:22,663 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 92 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=97, Invalid=503, Unknown=0, NotChecked=0, Total=600 [2019-11-28 18:33:22,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384 states. [2019-11-28 18:33:22,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384 to 302. [2019-11-28 18:33:22,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 302 states. [2019-11-28 18:33:22,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 302 states to 302 states and 515 transitions. [2019-11-28 18:33:22,667 INFO L78 Accepts]: Start accepts. Automaton has 302 states and 515 transitions. Word has length 57 [2019-11-28 18:33:22,668 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:22,668 INFO L462 AbstractCegarLoop]: Abstraction has 302 states and 515 transitions. [2019-11-28 18:33:22,668 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-11-28 18:33:22,668 INFO L276 IsEmpty]: Start isEmpty. Operand 302 states and 515 transitions. [2019-11-28 18:33:22,669 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:33:22,669 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:22,669 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:22,669 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:22,669 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:22,669 INFO L82 PathProgramCache]: Analyzing trace with hash -1239613688, now seen corresponding path program 4 times [2019-11-28 18:33:22,670 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:22,670 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [345584282] [2019-11-28 18:33:22,670 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:22,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 18:33:22,928 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 18:33:22,928 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [345584282] [2019-11-28 18:33:22,929 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 18:33:22,929 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-11-28 18:33:22,929 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [866747785] [2019-11-28 18:33:22,929 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-11-28 18:33:22,930 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 18:33:22,930 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-11-28 18:33:22,930 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=125, Unknown=0, NotChecked=0, Total=156 [2019-11-28 18:33:22,930 INFO L87 Difference]: Start difference. First operand 302 states and 515 transitions. Second operand 13 states. [2019-11-28 18:33:23,406 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 18:33:23,406 INFO L93 Difference]: Finished difference Result 407 states and 673 transitions. [2019-11-28 18:33:23,406 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-11-28 18:33:23,407 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 57 [2019-11-28 18:33:23,407 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 18:33:23,407 INFO L225 Difference]: With dead ends: 407 [2019-11-28 18:33:23,407 INFO L226 Difference]: Without dead ends: 372 [2019-11-28 18:33:23,408 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 75 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=97, Invalid=409, Unknown=0, NotChecked=0, Total=506 [2019-11-28 18:33:23,410 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 372 states. [2019-11-28 18:33:23,414 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 372 to 310. [2019-11-28 18:33:23,414 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 310 states. [2019-11-28 18:33:23,415 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 310 states to 310 states and 529 transitions. [2019-11-28 18:33:23,416 INFO L78 Accepts]: Start accepts. Automaton has 310 states and 529 transitions. Word has length 57 [2019-11-28 18:33:23,417 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 18:33:23,417 INFO L462 AbstractCegarLoop]: Abstraction has 310 states and 529 transitions. [2019-11-28 18:33:23,418 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-11-28 18:33:23,418 INFO L276 IsEmpty]: Start isEmpty. Operand 310 states and 529 transitions. [2019-11-28 18:33:23,419 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-11-28 18:33:23,419 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 18:33:23,419 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 18:33:23,419 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 18:33:23,420 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 18:33:23,420 INFO L82 PathProgramCache]: Analyzing trace with hash -97225810, now seen corresponding path program 5 times [2019-11-28 18:33:23,420 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 18:33:23,421 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1421743973] [2019-11-28 18:33:23,421 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 18:33:23,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 18:33:23,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 18:33:23,522 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-28 18:33:23,522 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-28 18:33:23,526 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [740] [740] ULTIMATE.startENTRY-->L802: Formula: (let ((.cse0 (store |v_#valid_55| 0 0))) (and (= v_~y$w_buff1~0_198 0) (= v_~x~0_55 0) (= 0 v_~y$read_delayed_var~0.offset_7) (= v_~weak$$choice2~0_120 0) (= v_~main$tmp_guard1~0_31 0) (= v_~y$r_buff1_thd0~0_279 0) (= 0 v_~y$r_buff1_thd2~0_191) (= v_~y$read_delayed~0_7 0) (= 0 v_~y$w_buff0~0_215) (= 0 |v_ULTIMATE.start_main_~#t2522~0.offset_17|) (= 0 v_~y$r_buff0_thd3~0_201) (< 0 |v_#StackHeapBarrier_17|) (= v_~y$r_buff0_thd0~0_331 0) (= v_~y$r_buff0_thd1~0_37 0) (= v_~y$w_buff0_used~0_623 0) (= |v_#valid_53| (store .cse0 |v_ULTIMATE.start_main_~#t2522~0.base_22| 1)) (= 0 |v_#NULL.base_4|) (= v_~y~0_147 0) (= 0 v_~__unbuffered_p0_EAX~0_42) (= 0 v_~y$read_delayed_var~0.base_7) (= v_~y$mem_tmp~0_20 0) (= 0 v_~weak$$choice0~0_16) (= 0 v_~y$flush_delayed~0_42) (= 0 v_~y$r_buff0_thd2~0_116) (= v_~y$w_buff1_used~0_397 0) (= |v_#NULL.offset_4| 0) (= v_~main$tmp_guard0~0_26 0) (= (store |v_#length_22| |v_ULTIMATE.start_main_~#t2522~0.base_22| 4) |v_#length_21|) (= 0 v_~y$r_buff1_thd3~0_162) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t2522~0.base_22|)) (= v_~z~0_148 0) (= 0 v_~__unbuffered_cnt~0_97) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t2522~0.base_22|) (= (store |v_#memory_int_20| |v_ULTIMATE.start_main_~#t2522~0.base_22| (store (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#t2522~0.base_22|) |v_ULTIMATE.start_main_~#t2522~0.offset_17| 0)) |v_#memory_int_19|) (= v_~y$r_buff1_thd1~0_116 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_55|, #memory_int=|v_#memory_int_20|, #length=|v_#length_22|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_40|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_23|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_23|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_46|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_25|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_40|, ~y$read_delayed~0=v_~y$read_delayed~0_7, ~y$mem_tmp~0=v_~y$mem_tmp~0_20, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_42, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_162, ULTIMATE.start_main_~#t2522~0.base=|v_ULTIMATE.start_main_~#t2522~0.base_22|, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_37, ~y$flush_delayed~0=v_~y$flush_delayed~0_42, ULTIMATE.start_main_~#t2522~0.offset=|v_ULTIMATE.start_main_~#t2522~0.offset_17|, #length=|v_#length_21|, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_27|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_31|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_23|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_28|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_35|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_60|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_65|, ~weak$$choice0~0=v_~weak$$choice0~0_16, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_27|, ~y$w_buff1~0=v_~y$w_buff1~0_198, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_7, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_116, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_7|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_23|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_97, ULTIMATE.start_main_~#t2524~0.offset=|v_ULTIMATE.start_main_~#t2524~0.offset_15|, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_279, ~x~0=v_~x~0_55, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_7, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_623, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_44|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_36|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_31, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_31|, ULTIMATE.start_main_~#t2523~0.offset=|v_ULTIMATE.start_main_~#t2523~0.offset_15|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_129|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_28|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_37|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_50|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_116, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_25|, ~y$w_buff0~0=v_~y$w_buff0~0_215, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_201, ULTIMATE.start_main_~#t2524~0.base=|v_ULTIMATE.start_main_~#t2524~0.base_18|, ~y~0=v_~y~0_147, ULTIMATE.start_main_~#t2523~0.base=|v_ULTIMATE.start_main_~#t2523~0.base_19|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_31|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_23|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_19|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_34|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_26, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_64|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_24|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_191, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_33|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_331, #valid=|v_#valid_53|, #memory_int=|v_#memory_int_19|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_8|, ~z~0=v_~z~0_148, ~weak$$choice2~0=v_~weak$$choice2~0_120, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_397} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~y$read_delayed~0, ~y$mem_tmp~0, ~__unbuffered_p0_EAX~0, ~y$r_buff1_thd3~0, ULTIMATE.start_main_~#t2522~0.base, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, ULTIMATE.start_main_~#t2522~0.offset, #length, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ULTIMATE.start_main_~#t2524~0.offset, ~y$r_buff1_thd0~0, ~x~0, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_~#t2523~0.offset, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ULTIMATE.start_main_~#t2524~0.base, ~y~0, ULTIMATE.start_main_~#t2523~0.base, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:33:23,527 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [713] [713] L802-1-->L804: Formula: (and (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t2523~0.base_11|) (= (store |v_#valid_34| |v_ULTIMATE.start_main_~#t2523~0.base_11| 1) |v_#valid_33|) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t2523~0.base_11| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t2523~0.base_11|) |v_ULTIMATE.start_main_~#t2523~0.offset_10| 1)) |v_#memory_int_15|) (= (select |v_#valid_34| |v_ULTIMATE.start_main_~#t2523~0.base_11|) 0) (= 0 |v_ULTIMATE.start_main_~#t2523~0.offset_10|) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t2523~0.base_11| 4)) (not (= 0 |v_ULTIMATE.start_main_~#t2523~0.base_11|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_16|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t2523~0.base=|v_ULTIMATE.start_main_~#t2523~0.base_11|, #StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_33|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, #length=|v_#length_17|, ULTIMATE.start_main_~#t2523~0.offset=|v_ULTIMATE.start_main_~#t2523~0.offset_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2523~0.base, #valid, #memory_int, ULTIMATE.start_main_#t~nondet15, #length, ULTIMATE.start_main_~#t2523~0.offset] because there is no mapped edge [2019-11-28 18:33:23,527 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [702] [702] L804-1-->L806: Formula: (and (= 0 |v_ULTIMATE.start_main_~#t2524~0.offset_10|) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t2524~0.base_10| 4)) (= (store |v_#valid_30| |v_ULTIMATE.start_main_~#t2524~0.base_10| 1) |v_#valid_29|) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t2524~0.base_10|) (= 0 (select |v_#valid_30| |v_ULTIMATE.start_main_~#t2524~0.base_10|)) (not (= |v_ULTIMATE.start_main_~#t2524~0.base_10| 0)) (= |v_#memory_int_13| (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2524~0.base_10| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2524~0.base_10|) |v_ULTIMATE.start_main_~#t2524~0.offset_10| 2)))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_30|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_29|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_~#t2524~0.base=|v_ULTIMATE.start_main_~#t2524~0.base_10|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_6|, #length=|v_#length_15|, ULTIMATE.start_main_~#t2524~0.offset=|v_ULTIMATE.start_main_~#t2524~0.offset_10|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_~#t2524~0.base, ULTIMATE.start_main_#t~nondet16, #length, ULTIMATE.start_main_~#t2524~0.offset] because there is no mapped edge [2019-11-28 18:33:23,528 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [616] [616] P2ENTRY-->L4-3: Formula: (and (= v_~y$w_buff0~0_29 v_~y$w_buff1~0_24) (= v_P2Thread1of1ForFork0_~arg.base_9 |v_P2Thread1of1ForFork0_#in~arg.base_11|) (= 2 v_~y$w_buff0~0_28) (= (ite (not (and (not (= 0 (mod v_~y$w_buff1_used~0_54 256))) (not (= (mod v_~y$w_buff0_used~0_103 256) 0)))) 1 0) |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_9|) (= v_~y$w_buff0_used~0_103 1) (= v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_11 |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_9|) (not (= 0 v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_11)) (= v_~y$w_buff1_used~0_54 v_~y$w_buff0_used~0_104) (= |v_P2Thread1of1ForFork0_#in~arg.offset_11| v_P2Thread1of1ForFork0_~arg.offset_9)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_11|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_104, ~y$w_buff0~0=v_~y$w_buff0~0_29, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_11|} OutVars{P2Thread1of1ForFork0_~arg.base=v_P2Thread1of1ForFork0_~arg.base_9, P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_11|, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_9|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_103, ~y$w_buff1~0=v_~y$w_buff1~0_24, ~y$w_buff0~0=v_~y$w_buff0~0_28, P2Thread1of1ForFork0_~arg.offset=v_P2Thread1of1ForFork0_~arg.offset_9, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_11|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_11, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_54} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:33:23,528 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] P0ENTRY-->P0EXIT: Formula: (and (= v_~x~0_47 v_~__unbuffered_p0_EAX~0_32) (= 0 |v_P0Thread1of1ForFork1_#res.offset_13|) (= (+ v_~__unbuffered_cnt~0_81 1) v_~__unbuffered_cnt~0_80) (= v_~z~0_109 2) (= v_P0Thread1of1ForFork1_~arg.offset_19 |v_P0Thread1of1ForFork1_#in~arg.offset_21|) (= |v_P0Thread1of1ForFork1_#in~arg.base_21| v_P0Thread1of1ForFork1_~arg.base_19) (= |v_P0Thread1of1ForFork1_#res.base_13| 0)) InVars {P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_21|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_81, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_21|, ~x~0=v_~x~0_47} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_32, P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_13|, P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_21|, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_13|, P0Thread1of1ForFork1_~arg.offset=v_P0Thread1of1ForFork1_~arg.offset_19, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_80, ~z~0=v_~z~0_109, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_21|, ~x~0=v_~x~0_47, P0Thread1of1ForFork1_~arg.base=v_P0Thread1of1ForFork1_~arg.base_19} AuxVars[] AssignedVars[~__unbuffered_p0_EAX~0, P0Thread1of1ForFork1_#res.offset, P0Thread1of1ForFork1_#res.base, P0Thread1of1ForFork1_~arg.offset, ~__unbuffered_cnt~0, ~z~0, P0Thread1of1ForFork1_~arg.base] because there is no mapped edge [2019-11-28 18:33:23,530 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [691] [691] L780-->L780-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-1611046035 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In-1611046035 256)))) (or (and (not .cse0) (= |P2Thread1of1ForFork0_#t~ite11_Out-1611046035| 0) (not .cse1)) (and (= |P2Thread1of1ForFork0_#t~ite11_Out-1611046035| ~y$w_buff0_used~0_In-1611046035) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1611046035, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1611046035} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1611046035, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out-1611046035|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1611046035} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-11-28 18:33:23,530 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [678] [678] L750-2-->L750-5: Formula: (let ((.cse1 (= |P1Thread1of1ForFork2_#t~ite4_Out-1363482218| |P1Thread1of1ForFork2_#t~ite3_Out-1363482218|)) (.cse0 (= 0 (mod ~y$w_buff1_used~0_In-1363482218 256))) (.cse2 (= (mod ~y$r_buff1_thd2~0_In-1363482218 256) 0))) (or (and (= |P1Thread1of1ForFork2_#t~ite3_Out-1363482218| ~y$w_buff1~0_In-1363482218) (not .cse0) .cse1 (not .cse2)) (and .cse1 (or .cse0 .cse2) (= |P1Thread1of1ForFork2_#t~ite3_Out-1363482218| ~y~0_In-1363482218)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1363482218, ~y$w_buff1~0=~y$w_buff1~0_In-1363482218, ~y~0=~y~0_In-1363482218, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1363482218} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1363482218, ~y$w_buff1~0=~y$w_buff1~0_In-1363482218, P1Thread1of1ForFork2_#t~ite4=|P1Thread1of1ForFork2_#t~ite4_Out-1363482218|, ~y~0=~y~0_In-1363482218, P1Thread1of1ForFork2_#t~ite3=|P1Thread1of1ForFork2_#t~ite3_Out-1363482218|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1363482218} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite4, P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-11-28 18:33:23,531 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [694] [694] L751-->L751-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In-467953725 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In-467953725 256)))) (or (and (= ~y$w_buff0_used~0_In-467953725 |P1Thread1of1ForFork2_#t~ite5_Out-467953725|) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= |P1Thread1of1ForFork2_#t~ite5_Out-467953725| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-467953725, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-467953725} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-467953725, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-467953725, P1Thread1of1ForFork2_#t~ite5=|P1Thread1of1ForFork2_#t~ite5_Out-467953725|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-11-28 18:33:23,531 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [684] [684] L781-->L781-2: Formula: (let ((.cse2 (= 0 (mod ~y$r_buff1_thd3~0_In-807219425 256))) (.cse3 (= 0 (mod ~y$w_buff1_used~0_In-807219425 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-807219425 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In-807219425 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite12_Out-807219425| ~y$w_buff1_used~0_In-807219425) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |P2Thread1of1ForFork0_#t~ite12_Out-807219425| 0) (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-807219425, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-807219425, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-807219425, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-807219425} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-807219425, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-807219425, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out-807219425|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-807219425, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-807219425} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-11-28 18:33:23,532 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L752-->L752-2: Formula: (let ((.cse3 (= 0 (mod ~y$w_buff1_used~0_In-167094018 256))) (.cse2 (= (mod ~y$r_buff1_thd2~0_In-167094018 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In-167094018 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-167094018 256)))) (or (and (= 0 |P1Thread1of1ForFork2_#t~ite6_Out-167094018|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (= ~y$w_buff1_used~0_In-167094018 |P1Thread1of1ForFork2_#t~ite6_Out-167094018|) (or .cse1 .cse0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-167094018, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-167094018, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-167094018, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-167094018} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-167094018, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-167094018, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-167094018, P1Thread1of1ForFork2_#t~ite6=|P1Thread1of1ForFork2_#t~ite6_Out-167094018|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-167094018} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-11-28 18:33:23,532 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L753-->L753-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In1324152761 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In1324152761 256)))) (or (and (= ~y$r_buff0_thd2~0_In1324152761 |P1Thread1of1ForFork2_#t~ite7_Out1324152761|) (or .cse0 .cse1)) (and (= 0 |P1Thread1of1ForFork2_#t~ite7_Out1324152761|) (not .cse0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1324152761, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1324152761} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1324152761, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1324152761, P1Thread1of1ForFork2_#t~ite7=|P1Thread1of1ForFork2_#t~ite7_Out1324152761|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-11-28 18:33:23,533 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [690] [690] L754-->L754-2: Formula: (let ((.cse3 (= 0 (mod ~y$r_buff0_thd2~0_In1619644640 256))) (.cse2 (= (mod ~y$w_buff0_used~0_In1619644640 256) 0)) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In1619644640 256))) (.cse0 (= 0 (mod ~y$r_buff1_thd2~0_In1619644640 256)))) (or (and (= |P1Thread1of1ForFork2_#t~ite8_Out1619644640| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (or .cse1 .cse0) (= |P1Thread1of1ForFork2_#t~ite8_Out1619644640| ~y$r_buff1_thd2~0_In1619644640)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1619644640, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1619644640, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1619644640, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1619644640} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1619644640, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1619644640, P1Thread1of1ForFork2_#t~ite8=|P1Thread1of1ForFork2_#t~ite8_Out1619644640|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1619644640, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1619644640} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-11-28 18:33:23,533 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [712] [712] L754-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= |v_P1Thread1of1ForFork2_#t~ite8_24| v_~y$r_buff1_thd2~0_103) (= v_~__unbuffered_cnt~0_54 (+ v_~__unbuffered_cnt~0_55 1))) InVars {P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_24|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_103, P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_23|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_54, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork2_#res.offset, P1Thread1of1ForFork2_#t~ite8, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-11-28 18:33:23,533 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [688] [688] L782-->L783: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In796242937 256))) (.cse2 (= (mod ~y$r_buff0_thd3~0_In796242937 256) 0)) (.cse0 (= ~y$r_buff0_thd3~0_In796242937 ~y$r_buff0_thd3~0_Out796242937))) (or (and .cse0 .cse1) (and (= 0 ~y$r_buff0_thd3~0_Out796242937) (not .cse2) (not .cse1)) (and .cse2 .cse0))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In796242937, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In796242937} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In796242937, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out796242937, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out796242937|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-11-28 18:33:23,533 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [689] [689] L783-->L783-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff1_used~0_In357477073 256))) (.cse0 (= (mod ~y$r_buff1_thd3~0_In357477073 256) 0)) (.cse3 (= 0 (mod ~y$r_buff0_thd3~0_In357477073 256))) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In357477073 256)))) (or (and (or .cse0 .cse1) (= ~y$r_buff1_thd3~0_In357477073 |P2Thread1of1ForFork0_#t~ite14_Out357477073|) (or .cse2 .cse3)) (and (= 0 |P2Thread1of1ForFork0_#t~ite14_Out357477073|) (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In357477073, ~y$w_buff0_used~0=~y$w_buff0_used~0_In357477073, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In357477073, ~y$w_buff1_used~0=~y$w_buff1_used~0_In357477073} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out357477073|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In357477073, ~y$w_buff0_used~0=~y$w_buff0_used~0_In357477073, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In357477073, ~y$w_buff1_used~0=~y$w_buff1_used~0_In357477073} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-11-28 18:33:23,534 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L783-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= |v_P2Thread1of1ForFork0_#t~ite14_24| v_~y$r_buff1_thd3~0_99) (= (+ v_~__unbuffered_cnt~0_67 1) v_~__unbuffered_cnt~0_66) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_24|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_67} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_23|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_99, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_66, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-11-28 18:33:23,534 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [614] [614] L806-1-->L812: Formula: (and (= v_~main$tmp_guard0~0_7 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_14) 1 0) 0) 0 1)) (not (= (mod v_~main$tmp_guard0~0_7 256) 0))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_5|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet17, ~main$tmp_guard0~0] because there is no mapped edge [2019-11-28 18:33:23,534 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [692] [692] L812-2-->L812-5: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In-1376643054 256))) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In-1376643054 256))) (.cse1 (= |ULTIMATE.start_main_#t~ite19_Out-1376643054| |ULTIMATE.start_main_#t~ite18_Out-1376643054|))) (or (and (= |ULTIMATE.start_main_#t~ite18_Out-1376643054| ~y$w_buff1~0_In-1376643054) (not .cse0) .cse1 (not .cse2)) (and (or .cse0 .cse2) (= |ULTIMATE.start_main_#t~ite18_Out-1376643054| ~y~0_In-1376643054) .cse1))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-1376643054, ~y~0=~y~0_In-1376643054, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1376643054, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1376643054} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-1376643054, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out-1376643054|, ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out-1376643054|, ~y~0=~y~0_In-1376643054, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1376643054, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1376643054} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-11-28 18:33:23,535 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [676] [676] L813-->L813-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In-1358340014 256))) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1358340014 256)))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite20_Out-1358340014| ~y$w_buff0_used~0_In-1358340014)) (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite20_Out-1358340014| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1358340014, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1358340014} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1358340014, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1358340014, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out-1358340014|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-11-28 18:33:23,535 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [683] [683] L814-->L814-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In85907139 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In85907139 256))) (.cse2 (= 0 (mod ~y$r_buff1_thd0~0_In85907139 256))) (.cse3 (= 0 (mod ~y$w_buff1_used~0_In85907139 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite21_Out85907139|)) (and (or .cse0 .cse1) (= ~y$w_buff1_used~0_In85907139 |ULTIMATE.start_main_#t~ite21_Out85907139|) (or .cse2 .cse3)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In85907139, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In85907139, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In85907139, ~y$w_buff1_used~0=~y$w_buff1_used~0_In85907139} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In85907139, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In85907139, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out85907139|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In85907139, ~y$w_buff1_used~0=~y$w_buff1_used~0_In85907139} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-11-28 18:33:23,536 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [680] [680] L815-->L815-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In213564249 256))) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In213564249 256)))) (or (and (= ~y$r_buff0_thd0~0_In213564249 |ULTIMATE.start_main_#t~ite22_Out213564249|) (or .cse0 .cse1)) (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite22_Out213564249|) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In213564249, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In213564249} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In213564249, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In213564249, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out213564249|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-11-28 18:33:23,536 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [686] [686] L816-->L816-2: Formula: (let ((.cse3 (= 0 (mod ~y$w_buff0_used~0_In1539316582 256))) (.cse2 (= 0 (mod ~y$r_buff0_thd0~0_In1539316582 256))) (.cse0 (= (mod ~y$r_buff1_thd0~0_In1539316582 256) 0)) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In1539316582 256)))) (or (and (= ~y$r_buff1_thd0~0_In1539316582 |ULTIMATE.start_main_#t~ite23_Out1539316582|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1))) (= |ULTIMATE.start_main_#t~ite23_Out1539316582| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1539316582, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1539316582, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1539316582, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1539316582} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1539316582, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1539316582, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1539316582, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out1539316582|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1539316582} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-11-28 18:33:23,539 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L827-->L827-8: Formula: (let ((.cse1 (= 0 (mod ~weak$$choice2~0_In1144169944 256)))) (or (and (let ((.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In1144169944 256)))) (or (= 0 (mod ~y$w_buff0_used~0_In1144169944 256)) (and .cse0 (= (mod ~y$w_buff1_used~0_In1144169944 256) 0)) (and (= 0 (mod ~y$r_buff1_thd0~0_In1144169944 256)) .cse0))) (= |ULTIMATE.start_main_#t~ite38_Out1144169944| ~y$w_buff1_used~0_In1144169944) (= |ULTIMATE.start_main_#t~ite38_Out1144169944| |ULTIMATE.start_main_#t~ite39_Out1144169944|) .cse1) (and (= |ULTIMATE.start_main_#t~ite39_Out1144169944| ~y$w_buff1_used~0_In1144169944) (= |ULTIMATE.start_main_#t~ite38_In1144169944| |ULTIMATE.start_main_#t~ite38_Out1144169944|) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1144169944, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1144169944, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_In1144169944|, ~weak$$choice2~0=~weak$$choice2~0_In1144169944, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1144169944, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1144169944} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1144169944, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out1144169944|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1144169944, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_Out1144169944|, ~weak$$choice2~0=~weak$$choice2~0_In1144169944, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1144169944, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1144169944} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite38] because there is no mapped edge [2019-11-28 18:33:23,540 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [649] [649] L828-->L829: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_25 256))) (= v_~y$r_buff0_thd0~0_98 v_~y$r_buff0_thd0~0_97)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_98, ~weak$$choice2~0=v_~weak$$choice2~0_25} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_13|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_8|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_97, ~weak$$choice2~0=v_~weak$$choice2~0_25, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-11-28 18:33:23,541 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [706] [706] L831-->L4: Formula: (and (= v_~y~0_99 v_~y$mem_tmp~0_10) (not (= (mod v_~y$flush_delayed~0_27 256) 0)) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4| (mod v_~main$tmp_guard1~0_12 256)) (= 0 v_~y$flush_delayed~0_26)) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_10, ~y$flush_delayed~0=v_~y$flush_delayed~0_27, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_10, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_9, ~y$flush_delayed~0=v_~y$flush_delayed~0_26, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_24|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12, ~y~0=v_~y~0_99, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ~y$flush_delayed~0, ULTIMATE.start_main_#t~ite46, ~y~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-11-28 18:33:23,541 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [709] [709] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-11-28 18:33:23,627 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 06:33:23 BasicIcfg [2019-11-28 18:33:23,628 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-28 18:33:23,628 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-28 18:33:23,628 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-28 18:33:23,629 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-28 18:33:23,629 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 06:33:01" (3/4) ... [2019-11-28 18:33:23,632 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-28 18:33:23,633 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [740] [740] ULTIMATE.startENTRY-->L802: Formula: (let ((.cse0 (store |v_#valid_55| 0 0))) (and (= v_~y$w_buff1~0_198 0) (= v_~x~0_55 0) (= 0 v_~y$read_delayed_var~0.offset_7) (= v_~weak$$choice2~0_120 0) (= v_~main$tmp_guard1~0_31 0) (= v_~y$r_buff1_thd0~0_279 0) (= 0 v_~y$r_buff1_thd2~0_191) (= v_~y$read_delayed~0_7 0) (= 0 v_~y$w_buff0~0_215) (= 0 |v_ULTIMATE.start_main_~#t2522~0.offset_17|) (= 0 v_~y$r_buff0_thd3~0_201) (< 0 |v_#StackHeapBarrier_17|) (= v_~y$r_buff0_thd0~0_331 0) (= v_~y$r_buff0_thd1~0_37 0) (= v_~y$w_buff0_used~0_623 0) (= |v_#valid_53| (store .cse0 |v_ULTIMATE.start_main_~#t2522~0.base_22| 1)) (= 0 |v_#NULL.base_4|) (= v_~y~0_147 0) (= 0 v_~__unbuffered_p0_EAX~0_42) (= 0 v_~y$read_delayed_var~0.base_7) (= v_~y$mem_tmp~0_20 0) (= 0 v_~weak$$choice0~0_16) (= 0 v_~y$flush_delayed~0_42) (= 0 v_~y$r_buff0_thd2~0_116) (= v_~y$w_buff1_used~0_397 0) (= |v_#NULL.offset_4| 0) (= v_~main$tmp_guard0~0_26 0) (= (store |v_#length_22| |v_ULTIMATE.start_main_~#t2522~0.base_22| 4) |v_#length_21|) (= 0 v_~y$r_buff1_thd3~0_162) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t2522~0.base_22|)) (= v_~z~0_148 0) (= 0 v_~__unbuffered_cnt~0_97) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t2522~0.base_22|) (= (store |v_#memory_int_20| |v_ULTIMATE.start_main_~#t2522~0.base_22| (store (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#t2522~0.base_22|) |v_ULTIMATE.start_main_~#t2522~0.offset_17| 0)) |v_#memory_int_19|) (= v_~y$r_buff1_thd1~0_116 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_55|, #memory_int=|v_#memory_int_20|, #length=|v_#length_22|} OutVars{ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_40|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_23|, ULTIMATE.start_main_#t~ite20=|v_ULTIMATE.start_main_#t~ite20_23|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_46|, ULTIMATE.start_main_#t~ite22=|v_ULTIMATE.start_main_#t~ite22_25|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_40|, ~y$read_delayed~0=v_~y$read_delayed~0_7, ~y$mem_tmp~0=v_~y$mem_tmp~0_20, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_42, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_162, ULTIMATE.start_main_~#t2522~0.base=|v_ULTIMATE.start_main_~#t2522~0.base_22|, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_37, ~y$flush_delayed~0=v_~y$flush_delayed~0_42, ULTIMATE.start_main_~#t2522~0.offset=|v_ULTIMATE.start_main_~#t2522~0.offset_17|, #length=|v_#length_21|, ULTIMATE.start_main_#t~ite18=|v_ULTIMATE.start_main_#t~ite18_27|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_31|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_23|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_28|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_35|, ULTIMATE.start_main_#t~ite31=|v_ULTIMATE.start_main_#t~ite31_60|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_65|, ~weak$$choice0~0=v_~weak$$choice0~0_16, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_27|, ~y$w_buff1~0=v_~y$w_buff1~0_198, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_7, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_116, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_7|, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_23|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_97, ULTIMATE.start_main_~#t2524~0.offset=|v_ULTIMATE.start_main_~#t2524~0.offset_15|, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_279, ~x~0=v_~x~0_55, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_7, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_623, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_44|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_36|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_31, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_31|, ULTIMATE.start_main_~#t2523~0.offset=|v_ULTIMATE.start_main_~#t2523~0.offset_15|, ULTIMATE.start_main_#t~ite21=|v_ULTIMATE.start_main_#t~ite21_129|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_28|, ULTIMATE.start_main_#t~ite23=|v_ULTIMATE.start_main_#t~ite23_37|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_50|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_116, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_25|, ~y$w_buff0~0=v_~y$w_buff0~0_215, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_201, ULTIMATE.start_main_~#t2524~0.base=|v_ULTIMATE.start_main_~#t2524~0.base_18|, ~y~0=v_~y~0_147, ULTIMATE.start_main_~#t2523~0.base=|v_ULTIMATE.start_main_~#t2523~0.base_19|, ULTIMATE.start_main_#t~ite19=|v_ULTIMATE.start_main_#t~ite19_31|, ULTIMATE.start_main_#t~nondet25=|v_ULTIMATE.start_main_#t~nondet25_23|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_19|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_34|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_26, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_64|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_24|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_191, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_33|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_331, #valid=|v_#valid_53|, #memory_int=|v_#memory_int_19|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_8|, ~z~0=v_~z~0_148, ~weak$$choice2~0=v_~weak$$choice2~0_120, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_397} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite20, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite22, ULTIMATE.start_main_#t~ite45, ~y$read_delayed~0, ~y$mem_tmp~0, ~__unbuffered_p0_EAX~0, ~y$r_buff1_thd3~0, ULTIMATE.start_main_~#t2522~0.base, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, ULTIMATE.start_main_~#t2522~0.offset, #length, ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite31, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet15, ULTIMATE.start_main_#t~nondet17, ~__unbuffered_cnt~0, ULTIMATE.start_main_~#t2524~0.offset, ~y$r_buff1_thd0~0, ~x~0, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_~#t2523~0.offset, ULTIMATE.start_main_#t~ite21, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite23, ULTIMATE.start_main_#t~ite44, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ULTIMATE.start_main_~#t2524~0.base, ~y~0, ULTIMATE.start_main_~#t2523~0.base, ULTIMATE.start_main_#t~ite19, ULTIMATE.start_main_#t~nondet25, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ULTIMATE.start_main_#t~nondet16, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:33:23,633 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [713] [713] L802-1-->L804: Formula: (and (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t2523~0.base_11|) (= (store |v_#valid_34| |v_ULTIMATE.start_main_~#t2523~0.base_11| 1) |v_#valid_33|) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t2523~0.base_11| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t2523~0.base_11|) |v_ULTIMATE.start_main_~#t2523~0.offset_10| 1)) |v_#memory_int_15|) (= (select |v_#valid_34| |v_ULTIMATE.start_main_~#t2523~0.base_11|) 0) (= 0 |v_ULTIMATE.start_main_~#t2523~0.offset_10|) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t2523~0.base_11| 4)) (not (= 0 |v_ULTIMATE.start_main_~#t2523~0.base_11|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_16|, #length=|v_#length_18|} OutVars{ULTIMATE.start_main_~#t2523~0.base=|v_ULTIMATE.start_main_~#t2523~0.base_11|, #StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_33|, #memory_int=|v_#memory_int_15|, ULTIMATE.start_main_#t~nondet15=|v_ULTIMATE.start_main_#t~nondet15_5|, #length=|v_#length_17|, ULTIMATE.start_main_~#t2523~0.offset=|v_ULTIMATE.start_main_~#t2523~0.offset_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2523~0.base, #valid, #memory_int, ULTIMATE.start_main_#t~nondet15, #length, ULTIMATE.start_main_~#t2523~0.offset] because there is no mapped edge [2019-11-28 18:33:23,634 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [702] [702] L804-1-->L806: Formula: (and (= 0 |v_ULTIMATE.start_main_~#t2524~0.offset_10|) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t2524~0.base_10| 4)) (= (store |v_#valid_30| |v_ULTIMATE.start_main_~#t2524~0.base_10| 1) |v_#valid_29|) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t2524~0.base_10|) (= 0 (select |v_#valid_30| |v_ULTIMATE.start_main_~#t2524~0.base_10|)) (not (= |v_ULTIMATE.start_main_~#t2524~0.base_10| 0)) (= |v_#memory_int_13| (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2524~0.base_10| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t2524~0.base_10|) |v_ULTIMATE.start_main_~#t2524~0.offset_10| 2)))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_30|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_29|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_~#t2524~0.base=|v_ULTIMATE.start_main_~#t2524~0.base_10|, ULTIMATE.start_main_#t~nondet16=|v_ULTIMATE.start_main_#t~nondet16_6|, #length=|v_#length_15|, ULTIMATE.start_main_~#t2524~0.offset=|v_ULTIMATE.start_main_~#t2524~0.offset_10|} AuxVars[] AssignedVars[#valid, #memory_int, ULTIMATE.start_main_~#t2524~0.base, ULTIMATE.start_main_#t~nondet16, #length, ULTIMATE.start_main_~#t2524~0.offset] because there is no mapped edge [2019-11-28 18:33:23,634 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [616] [616] P2ENTRY-->L4-3: Formula: (and (= v_~y$w_buff0~0_29 v_~y$w_buff1~0_24) (= v_P2Thread1of1ForFork0_~arg.base_9 |v_P2Thread1of1ForFork0_#in~arg.base_11|) (= 2 v_~y$w_buff0~0_28) (= (ite (not (and (not (= 0 (mod v_~y$w_buff1_used~0_54 256))) (not (= (mod v_~y$w_buff0_used~0_103 256) 0)))) 1 0) |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_9|) (= v_~y$w_buff0_used~0_103 1) (= v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_11 |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_9|) (not (= 0 v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_11)) (= v_~y$w_buff1_used~0_54 v_~y$w_buff0_used~0_104) (= |v_P2Thread1of1ForFork0_#in~arg.offset_11| v_P2Thread1of1ForFork0_~arg.offset_9)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_11|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_104, ~y$w_buff0~0=v_~y$w_buff0~0_29, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_11|} OutVars{P2Thread1of1ForFork0_~arg.base=v_P2Thread1of1ForFork0_~arg.base_9, P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_11|, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_9|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_103, ~y$w_buff1~0=v_~y$w_buff1~0_24, ~y$w_buff0~0=v_~y$w_buff0~0_28, P2Thread1of1ForFork0_~arg.offset=v_P2Thread1of1ForFork0_~arg.offset_9, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_11|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_11, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_54} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-11-28 18:33:23,635 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [720] [720] P0ENTRY-->P0EXIT: Formula: (and (= v_~x~0_47 v_~__unbuffered_p0_EAX~0_32) (= 0 |v_P0Thread1of1ForFork1_#res.offset_13|) (= (+ v_~__unbuffered_cnt~0_81 1) v_~__unbuffered_cnt~0_80) (= v_~z~0_109 2) (= v_P0Thread1of1ForFork1_~arg.offset_19 |v_P0Thread1of1ForFork1_#in~arg.offset_21|) (= |v_P0Thread1of1ForFork1_#in~arg.base_21| v_P0Thread1of1ForFork1_~arg.base_19) (= |v_P0Thread1of1ForFork1_#res.base_13| 0)) InVars {P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_21|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_81, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_21|, ~x~0=v_~x~0_47} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_32, P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_13|, P0Thread1of1ForFork1_#in~arg.offset=|v_P0Thread1of1ForFork1_#in~arg.offset_21|, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_13|, P0Thread1of1ForFork1_~arg.offset=v_P0Thread1of1ForFork1_~arg.offset_19, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_80, ~z~0=v_~z~0_109, P0Thread1of1ForFork1_#in~arg.base=|v_P0Thread1of1ForFork1_#in~arg.base_21|, ~x~0=v_~x~0_47, P0Thread1of1ForFork1_~arg.base=v_P0Thread1of1ForFork1_~arg.base_19} AuxVars[] AssignedVars[~__unbuffered_p0_EAX~0, P0Thread1of1ForFork1_#res.offset, P0Thread1of1ForFork1_#res.base, P0Thread1of1ForFork1_~arg.offset, ~__unbuffered_cnt~0, ~z~0, P0Thread1of1ForFork1_~arg.base] because there is no mapped edge [2019-11-28 18:33:23,636 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [691] [691] L780-->L780-2: Formula: (let ((.cse1 (= (mod ~y$w_buff0_used~0_In-1611046035 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In-1611046035 256)))) (or (and (not .cse0) (= |P2Thread1of1ForFork0_#t~ite11_Out-1611046035| 0) (not .cse1)) (and (= |P2Thread1of1ForFork0_#t~ite11_Out-1611046035| ~y$w_buff0_used~0_In-1611046035) (or .cse1 .cse0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1611046035, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1611046035} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1611046035, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out-1611046035|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1611046035} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-11-28 18:33:23,637 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [678] [678] L750-2-->L750-5: Formula: (let ((.cse1 (= |P1Thread1of1ForFork2_#t~ite4_Out-1363482218| |P1Thread1of1ForFork2_#t~ite3_Out-1363482218|)) (.cse0 (= 0 (mod ~y$w_buff1_used~0_In-1363482218 256))) (.cse2 (= (mod ~y$r_buff1_thd2~0_In-1363482218 256) 0))) (or (and (= |P1Thread1of1ForFork2_#t~ite3_Out-1363482218| ~y$w_buff1~0_In-1363482218) (not .cse0) .cse1 (not .cse2)) (and .cse1 (or .cse0 .cse2) (= |P1Thread1of1ForFork2_#t~ite3_Out-1363482218| ~y~0_In-1363482218)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1363482218, ~y$w_buff1~0=~y$w_buff1~0_In-1363482218, ~y~0=~y~0_In-1363482218, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1363482218} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1363482218, ~y$w_buff1~0=~y$w_buff1~0_In-1363482218, P1Thread1of1ForFork2_#t~ite4=|P1Thread1of1ForFork2_#t~ite4_Out-1363482218|, ~y~0=~y~0_In-1363482218, P1Thread1of1ForFork2_#t~ite3=|P1Thread1of1ForFork2_#t~ite3_Out-1363482218|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1363482218} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite4, P1Thread1of1ForFork2_#t~ite3] because there is no mapped edge [2019-11-28 18:33:23,637 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [694] [694] L751-->L751-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In-467953725 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In-467953725 256)))) (or (and (= ~y$w_buff0_used~0_In-467953725 |P1Thread1of1ForFork2_#t~ite5_Out-467953725|) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= |P1Thread1of1ForFork2_#t~ite5_Out-467953725| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-467953725, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-467953725} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-467953725, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-467953725, P1Thread1of1ForFork2_#t~ite5=|P1Thread1of1ForFork2_#t~ite5_Out-467953725|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite5] because there is no mapped edge [2019-11-28 18:33:23,638 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [684] [684] L781-->L781-2: Formula: (let ((.cse2 (= 0 (mod ~y$r_buff1_thd3~0_In-807219425 256))) (.cse3 (= 0 (mod ~y$w_buff1_used~0_In-807219425 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-807219425 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In-807219425 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite12_Out-807219425| ~y$w_buff1_used~0_In-807219425) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |P2Thread1of1ForFork0_#t~ite12_Out-807219425| 0) (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-807219425, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-807219425, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-807219425, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-807219425} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In-807219425, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-807219425, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out-807219425|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-807219425, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-807219425} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-11-28 18:33:23,638 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [685] [685] L752-->L752-2: Formula: (let ((.cse3 (= 0 (mod ~y$w_buff1_used~0_In-167094018 256))) (.cse2 (= (mod ~y$r_buff1_thd2~0_In-167094018 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In-167094018 256))) (.cse0 (= 0 (mod ~y$w_buff0_used~0_In-167094018 256)))) (or (and (= 0 |P1Thread1of1ForFork2_#t~ite6_Out-167094018|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (= ~y$w_buff1_used~0_In-167094018 |P1Thread1of1ForFork2_#t~ite6_Out-167094018|) (or .cse1 .cse0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-167094018, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-167094018, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-167094018, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-167094018} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-167094018, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-167094018, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-167094018, P1Thread1of1ForFork2_#t~ite6=|P1Thread1of1ForFork2_#t~ite6_Out-167094018|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-167094018} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite6] because there is no mapped edge [2019-11-28 18:33:23,639 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [693] [693] L753-->L753-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In1324152761 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd2~0_In1324152761 256)))) (or (and (= ~y$r_buff0_thd2~0_In1324152761 |P1Thread1of1ForFork2_#t~ite7_Out1324152761|) (or .cse0 .cse1)) (and (= 0 |P1Thread1of1ForFork2_#t~ite7_Out1324152761|) (not .cse0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1324152761, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1324152761} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1324152761, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1324152761, P1Thread1of1ForFork2_#t~ite7=|P1Thread1of1ForFork2_#t~ite7_Out1324152761|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite7] because there is no mapped edge [2019-11-28 18:33:23,639 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [690] [690] L754-->L754-2: Formula: (let ((.cse3 (= 0 (mod ~y$r_buff0_thd2~0_In1619644640 256))) (.cse2 (= (mod ~y$w_buff0_used~0_In1619644640 256) 0)) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In1619644640 256))) (.cse0 (= 0 (mod ~y$r_buff1_thd2~0_In1619644640 256)))) (or (and (= |P1Thread1of1ForFork2_#t~ite8_Out1619644640| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse3 .cse2) (or .cse1 .cse0) (= |P1Thread1of1ForFork2_#t~ite8_Out1619644640| ~y$r_buff1_thd2~0_In1619644640)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1619644640, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1619644640, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1619644640, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1619644640} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1619644640, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1619644640, P1Thread1of1ForFork2_#t~ite8=|P1Thread1of1ForFork2_#t~ite8_Out1619644640|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1619644640, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1619644640} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite8] because there is no mapped edge [2019-11-28 18:33:23,639 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [712] [712] L754-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= |v_P1Thread1of1ForFork2_#t~ite8_24| v_~y$r_buff1_thd2~0_103) (= v_~__unbuffered_cnt~0_54 (+ v_~__unbuffered_cnt~0_55 1))) InVars {P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_24|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55} OutVars{~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_103, P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, P1Thread1of1ForFork2_#t~ite8=|v_P1Thread1of1ForFork2_#t~ite8_23|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_54, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[~y$r_buff1_thd2~0, P1Thread1of1ForFork2_#res.offset, P1Thread1of1ForFork2_#t~ite8, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-11-28 18:33:23,640 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [688] [688] L782-->L783: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In796242937 256))) (.cse2 (= (mod ~y$r_buff0_thd3~0_In796242937 256) 0)) (.cse0 (= ~y$r_buff0_thd3~0_In796242937 ~y$r_buff0_thd3~0_Out796242937))) (or (and .cse0 .cse1) (and (= 0 ~y$r_buff0_thd3~0_Out796242937) (not .cse2) (not .cse1)) (and .cse2 .cse0))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In796242937, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In796242937} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In796242937, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out796242937, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out796242937|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-11-28 18:33:23,640 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [689] [689] L783-->L783-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff1_used~0_In357477073 256))) (.cse0 (= (mod ~y$r_buff1_thd3~0_In357477073 256) 0)) (.cse3 (= 0 (mod ~y$r_buff0_thd3~0_In357477073 256))) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In357477073 256)))) (or (and (or .cse0 .cse1) (= ~y$r_buff1_thd3~0_In357477073 |P2Thread1of1ForFork0_#t~ite14_Out357477073|) (or .cse2 .cse3)) (and (= 0 |P2Thread1of1ForFork0_#t~ite14_Out357477073|) (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In357477073, ~y$w_buff0_used~0=~y$w_buff0_used~0_In357477073, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In357477073, ~y$w_buff1_used~0=~y$w_buff1_used~0_In357477073} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out357477073|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In357477073, ~y$w_buff0_used~0=~y$w_buff0_used~0_In357477073, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In357477073, ~y$w_buff1_used~0=~y$w_buff1_used~0_In357477073} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-11-28 18:33:23,640 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L783-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= |v_P2Thread1of1ForFork0_#t~ite14_24| v_~y$r_buff1_thd3~0_99) (= (+ v_~__unbuffered_cnt~0_67 1) v_~__unbuffered_cnt~0_66) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_24|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_67} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_23|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_99, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_66, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-11-28 18:33:23,641 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [614] [614] L806-1-->L812: Formula: (and (= v_~main$tmp_guard0~0_7 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_14) 1 0) 0) 0 1)) (not (= (mod v_~main$tmp_guard0~0_7 256) 0))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14} OutVars{~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14, ULTIMATE.start_main_#t~nondet17=|v_ULTIMATE.start_main_#t~nondet17_5|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_7} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet17, ~main$tmp_guard0~0] because there is no mapped edge [2019-11-28 18:33:23,641 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [692] [692] L812-2-->L812-5: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In-1376643054 256))) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In-1376643054 256))) (.cse1 (= |ULTIMATE.start_main_#t~ite19_Out-1376643054| |ULTIMATE.start_main_#t~ite18_Out-1376643054|))) (or (and (= |ULTIMATE.start_main_#t~ite18_Out-1376643054| ~y$w_buff1~0_In-1376643054) (not .cse0) .cse1 (not .cse2)) (and (or .cse0 .cse2) (= |ULTIMATE.start_main_#t~ite18_Out-1376643054| ~y~0_In-1376643054) .cse1))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-1376643054, ~y~0=~y~0_In-1376643054, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1376643054, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1376643054} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-1376643054, ULTIMATE.start_main_#t~ite18=|ULTIMATE.start_main_#t~ite18_Out-1376643054|, ULTIMATE.start_main_#t~ite19=|ULTIMATE.start_main_#t~ite19_Out-1376643054|, ~y~0=~y~0_In-1376643054, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1376643054, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1376643054} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite18, ULTIMATE.start_main_#t~ite19] because there is no mapped edge [2019-11-28 18:33:23,642 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [676] [676] L813-->L813-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In-1358340014 256))) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1358340014 256)))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite20_Out-1358340014| ~y$w_buff0_used~0_In-1358340014)) (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite20_Out-1358340014| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1358340014, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1358340014} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1358340014, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1358340014, ULTIMATE.start_main_#t~ite20=|ULTIMATE.start_main_#t~ite20_Out-1358340014|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite20] because there is no mapped edge [2019-11-28 18:33:23,642 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [683] [683] L814-->L814-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In85907139 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In85907139 256))) (.cse2 (= 0 (mod ~y$r_buff1_thd0~0_In85907139 256))) (.cse3 (= 0 (mod ~y$w_buff1_used~0_In85907139 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite21_Out85907139|)) (and (or .cse0 .cse1) (= ~y$w_buff1_used~0_In85907139 |ULTIMATE.start_main_#t~ite21_Out85907139|) (or .cse2 .cse3)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In85907139, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In85907139, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In85907139, ~y$w_buff1_used~0=~y$w_buff1_used~0_In85907139} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In85907139, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In85907139, ULTIMATE.start_main_#t~ite21=|ULTIMATE.start_main_#t~ite21_Out85907139|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In85907139, ~y$w_buff1_used~0=~y$w_buff1_used~0_In85907139} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite21] because there is no mapped edge [2019-11-28 18:33:23,643 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [680] [680] L815-->L815-2: Formula: (let ((.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In213564249 256))) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In213564249 256)))) (or (and (= ~y$r_buff0_thd0~0_In213564249 |ULTIMATE.start_main_#t~ite22_Out213564249|) (or .cse0 .cse1)) (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite22_Out213564249|) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In213564249, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In213564249} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In213564249, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In213564249, ULTIMATE.start_main_#t~ite22=|ULTIMATE.start_main_#t~ite22_Out213564249|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite22] because there is no mapped edge [2019-11-28 18:33:23,644 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [686] [686] L816-->L816-2: Formula: (let ((.cse3 (= 0 (mod ~y$w_buff0_used~0_In1539316582 256))) (.cse2 (= 0 (mod ~y$r_buff0_thd0~0_In1539316582 256))) (.cse0 (= (mod ~y$r_buff1_thd0~0_In1539316582 256) 0)) (.cse1 (= 0 (mod ~y$w_buff1_used~0_In1539316582 256)))) (or (and (= ~y$r_buff1_thd0~0_In1539316582 |ULTIMATE.start_main_#t~ite23_Out1539316582|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1))) (= |ULTIMATE.start_main_#t~ite23_Out1539316582| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1539316582, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1539316582, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1539316582, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1539316582} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1539316582, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1539316582, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1539316582, ULTIMATE.start_main_#t~ite23=|ULTIMATE.start_main_#t~ite23_Out1539316582|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1539316582} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite23] because there is no mapped edge [2019-11-28 18:33:23,647 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [723] [723] L827-->L827-8: Formula: (let ((.cse1 (= 0 (mod ~weak$$choice2~0_In1144169944 256)))) (or (and (let ((.cse0 (= 0 (mod ~y$r_buff0_thd0~0_In1144169944 256)))) (or (= 0 (mod ~y$w_buff0_used~0_In1144169944 256)) (and .cse0 (= (mod ~y$w_buff1_used~0_In1144169944 256) 0)) (and (= 0 (mod ~y$r_buff1_thd0~0_In1144169944 256)) .cse0))) (= |ULTIMATE.start_main_#t~ite38_Out1144169944| ~y$w_buff1_used~0_In1144169944) (= |ULTIMATE.start_main_#t~ite38_Out1144169944| |ULTIMATE.start_main_#t~ite39_Out1144169944|) .cse1) (and (= |ULTIMATE.start_main_#t~ite39_Out1144169944| ~y$w_buff1_used~0_In1144169944) (= |ULTIMATE.start_main_#t~ite38_In1144169944| |ULTIMATE.start_main_#t~ite38_Out1144169944|) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1144169944, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1144169944, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_In1144169944|, ~weak$$choice2~0=~weak$$choice2~0_In1144169944, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1144169944, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1144169944} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1144169944, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out1144169944|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1144169944, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_Out1144169944|, ~weak$$choice2~0=~weak$$choice2~0_In1144169944, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1144169944, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1144169944} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite38] because there is no mapped edge [2019-11-28 18:33:23,647 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [649] [649] L828-->L829: Formula: (and (not (= 0 (mod v_~weak$$choice2~0_25 256))) (= v_~y$r_buff0_thd0~0_98 v_~y$r_buff0_thd0~0_97)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_98, ~weak$$choice2~0=v_~weak$$choice2~0_25} OutVars{ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_13|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_8|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_97, ~weak$$choice2~0=v_~weak$$choice2~0_25, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_9|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_#t~ite40, ~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-11-28 18:33:23,648 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [706] [706] L831-->L4: Formula: (and (= v_~y~0_99 v_~y$mem_tmp~0_10) (not (= (mod v_~y$flush_delayed~0_27 256) 0)) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4| (mod v_~main$tmp_guard1~0_12 256)) (= 0 v_~y$flush_delayed~0_26)) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_10, ~y$flush_delayed~0=v_~y$flush_delayed~0_27, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_10, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_9, ~y$flush_delayed~0=v_~y$flush_delayed~0_26, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_24|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_12, ~y~0=v_~y~0_99, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ~y$flush_delayed~0, ULTIMATE.start_main_#t~ite46, ~y~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-11-28 18:33:23,649 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [709] [709] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-11-28 18:33:23,768 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2019-11-28 18:33:23,768 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-28 18:33:23,770 INFO L168 Benchmark]: Toolchain (without parser) took 24349.33 ms. Allocated memory was 1.0 GB in the beginning and 2.1 GB in the end (delta: 1.1 GB). Free memory was 957.7 MB in the beginning and 1.2 GB in the end (delta: -258.0 MB). Peak memory consumption was 808.9 MB. Max. memory is 11.5 GB. [2019-11-28 18:33:23,771 INFO L168 Benchmark]: CDTParser took 0.86 ms. Allocated memory is still 1.0 GB. Free memory is still 987.2 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 18:33:23,771 INFO L168 Benchmark]: CACSL2BoogieTranslator took 764.57 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 141.6 MB). Free memory was 952.3 MB in the beginning and 1.1 GB in the end (delta: -152.6 MB). Peak memory consumption was 25.9 MB. Max. memory is 11.5 GB. [2019-11-28 18:33:23,772 INFO L168 Benchmark]: Boogie Procedure Inliner took 84.29 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.6 MB). Peak memory consumption was 6.6 MB. Max. memory is 11.5 GB. [2019-11-28 18:33:23,772 INFO L168 Benchmark]: Boogie Preprocessor took 40.50 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 18:33:23,773 INFO L168 Benchmark]: RCFGBuilder took 824.19 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 50.8 MB). Peak memory consumption was 50.8 MB. Max. memory is 11.5 GB. [2019-11-28 18:33:23,773 INFO L168 Benchmark]: TraceAbstraction took 22489.55 ms. Allocated memory was 1.2 GB in the beginning and 2.1 GB in the end (delta: 925.4 MB). Free memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: -188.1 MB). Peak memory consumption was 737.3 MB. Max. memory is 11.5 GB. [2019-11-28 18:33:23,773 INFO L168 Benchmark]: Witness Printer took 140.50 ms. Allocated memory is still 2.1 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 19.9 MB). Peak memory consumption was 19.9 MB. Max. memory is 11.5 GB. [2019-11-28 18:33:23,776 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.86 ms. Allocated memory is still 1.0 GB. Free memory is still 987.2 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 764.57 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 141.6 MB). Free memory was 952.3 MB in the beginning and 1.1 GB in the end (delta: -152.6 MB). Peak memory consumption was 25.9 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 84.29 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.6 MB). Peak memory consumption was 6.6 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 40.50 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 824.19 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 50.8 MB). Peak memory consumption was 50.8 MB. Max. memory is 11.5 GB. * TraceAbstraction took 22489.55 ms. Allocated memory was 1.2 GB in the beginning and 2.1 GB in the end (delta: 925.4 MB). Free memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: -188.1 MB). Peak memory consumption was 737.3 MB. Max. memory is 11.5 GB. * Witness Printer took 140.50 ms. Allocated memory is still 2.1 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 19.9 MB). Peak memory consumption was 19.9 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 5.3s, 162 ProgramPointsBefore, 83 ProgramPointsAfterwards, 193 TransitionsBefore, 94 TransitionsAfterwards, 11490 CoEnabledTransitionPairs, 7 FixpointIterations, 31 TrivialSequentialCompositions, 43 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 37 ConcurrentYvCompositions, 24 ChoiceCompositions, 4225 VarBasedMoverChecksPositive, 199 VarBasedMoverChecksNegative, 61 SemBasedMoverChecksPositive, 194 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 1.3s, 0 MoverChecksTotal, 48124 CheckedPairsTotal, 111 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L802] FCALL, FORK 0 pthread_create(&t2522, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L804] FCALL, FORK 0 pthread_create(&t2523, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L806] FCALL, FORK 0 pthread_create(&t2524, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L769] 3 y$r_buff1_thd0 = y$r_buff0_thd0 [L770] 3 y$r_buff1_thd1 = y$r_buff0_thd1 [L771] 3 y$r_buff1_thd2 = y$r_buff0_thd2 [L772] 3 y$r_buff1_thd3 = y$r_buff0_thd3 [L773] 3 y$r_buff0_thd3 = (_Bool)1 [L776] 3 z = 1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L779] EXPR 3 y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L744] 2 x = 1 [L747] 2 y = 1 VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L779] 3 y = y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) [L750] EXPR 2 y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=2] [L780] 3 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : y$w_buff0_used [L750] 2 y = y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) [L751] 2 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$w_buff0_used [L752] 2 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used [L753] 2 y$r_buff0_thd2 = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$r_buff0_thd2 [L781] 3 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd3 || y$w_buff1_used && y$r_buff1_thd3 ? (_Bool)0 : y$w_buff1_used [L812] EXPR 0 y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L812] 0 y = y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) [L813] 0 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used [L814] 0 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$w_buff1_used [L815] 0 y$r_buff0_thd0 = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$r_buff0_thd0 [L816] 0 y$r_buff1_thd0 = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$r_buff1_thd0 [L819] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L820] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L821] 0 y$flush_delayed = weak$$choice2 [L822] 0 y$mem_tmp = y VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L823] EXPR 0 !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L823] 0 y = !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) [L824] EXPR 0 weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L824] 0 y$w_buff0 = weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) [L825] EXPR 0 weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L825] 0 y$w_buff1 = weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) [L826] EXPR 0 weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L826] 0 y$w_buff0_used = weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) [L827] 0 y$w_buff1_used = weak$$choice2 ? y$w_buff1_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L829] EXPR 0 weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] [L829] 0 y$r_buff1_thd0 = weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L830] 0 main$tmp_guard1 = !(y == 2 && z == 2 && __unbuffered_p0_EAX == 0) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=2] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 153 locations, 2 error locations. Result: UNSAFE, OverallTime: 22.2s, OverallIterations: 19, TraceHistogramMax: 1, AutomataDifference: 6.1s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 1908 SDtfs, 1841 SDslu, 4564 SDs, 0 SdLazy, 2592 SolverSat, 149 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 2.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 168 GetRequests, 28 SyntacticMatches, 14 SemanticMatches, 126 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 288 ImplicationChecksByTransitivity, 1.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=26410occurred in iteration=5, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 5.1s AutomataMinimizationTime, 18 MinimizatonAttempts, 19103 StatesRemovedByMinimization, 13 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.5s SatisfiabilityAnalysisTime, 2.1s InterpolantComputationTime, 794 NumberOfCodeBlocks, 794 NumberOfCodeBlocksAsserted, 19 NumberOfCheckSat, 719 ConstructedInterpolants, 0 QuantifiedInterpolants, 135830 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 18 InterpolantComputations, 18 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...