./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/systemc/toy1.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx12G -Xms1G -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/systemc/toy1.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 133c91eb4ca703e3ebf3582d43ed0be6dbefca67 .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-11-28 17:32:26,170 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-28 17:32:26,173 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-28 17:32:26,191 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-28 17:32:26,192 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-28 17:32:26,194 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-28 17:32:26,196 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-28 17:32:26,206 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-28 17:32:26,212 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-28 17:32:26,215 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-28 17:32:26,216 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-28 17:32:26,218 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-28 17:32:26,219 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-28 17:32:26,221 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-28 17:32:26,222 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-28 17:32:26,224 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-28 17:32:26,225 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-28 17:32:26,228 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-28 17:32:26,231 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-28 17:32:26,235 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-28 17:32:26,239 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-28 17:32:26,244 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-28 17:32:26,245 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-28 17:32:26,247 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-28 17:32:26,251 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-28 17:32:26,251 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-28 17:32:26,251 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-28 17:32:26,253 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-28 17:32:26,254 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-28 17:32:26,255 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-28 17:32:26,255 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-28 17:32:26,256 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-28 17:32:26,256 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-28 17:32:26,258 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-28 17:32:26,259 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-28 17:32:26,259 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-28 17:32:26,260 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-28 17:32:26,261 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-28 17:32:26,261 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-28 17:32:26,262 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-28 17:32:26,263 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-28 17:32:26,264 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-28 17:32:26,302 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-28 17:32:26,302 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-28 17:32:26,304 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-28 17:32:26,304 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-28 17:32:26,304 INFO L138 SettingsManager]: * Use SBE=true [2019-11-28 17:32:26,304 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-28 17:32:26,305 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-28 17:32:26,305 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-28 17:32:26,305 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-28 17:32:26,306 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-28 17:32:26,306 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-28 17:32:26,306 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-28 17:32:26,306 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-28 17:32:26,307 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-28 17:32:26,307 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-28 17:32:26,307 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-28 17:32:26,308 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-28 17:32:26,308 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-28 17:32:26,308 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-28 17:32:26,308 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-28 17:32:26,309 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-28 17:32:26,309 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 17:32:26,309 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-28 17:32:26,310 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-28 17:32:26,310 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-28 17:32:26,310 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-28 17:32:26,310 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-28 17:32:26,311 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-28 17:32:26,311 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-11-28 17:32:26,311 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 133c91eb4ca703e3ebf3582d43ed0be6dbefca67 [2019-11-28 17:32:26,653 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-28 17:32:26,667 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-28 17:32:26,671 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-28 17:32:26,673 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-28 17:32:26,673 INFO L275 PluginConnector]: CDTParser initialized [2019-11-28 17:32:26,674 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/toy1.cil.c [2019-11-28 17:32:26,752 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7430e6e85/5d968445a76c479aa6d3e36a2ec9d178/FLAG52be773c4 [2019-11-28 17:32:27,280 INFO L306 CDTParser]: Found 1 translation units. [2019-11-28 17:32:27,281 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/toy1.cil.c [2019-11-28 17:32:27,292 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7430e6e85/5d968445a76c479aa6d3e36a2ec9d178/FLAG52be773c4 [2019-11-28 17:32:27,603 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7430e6e85/5d968445a76c479aa6d3e36a2ec9d178 [2019-11-28 17:32:27,606 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-28 17:32:27,608 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-28 17:32:27,609 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-28 17:32:27,609 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-28 17:32:27,613 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-28 17:32:27,614 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 05:32:27" (1/1) ... [2019-11-28 17:32:27,617 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@717e9a17 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:27, skipping insertion in model container [2019-11-28 17:32:27,617 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 05:32:27" (1/1) ... [2019-11-28 17:32:27,625 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-11-28 17:32:27,681 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-11-28 17:32:27,945 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 17:32:27,951 INFO L203 MainTranslator]: Completed pre-run [2019-11-28 17:32:28,090 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 17:32:28,108 INFO L208 MainTranslator]: Completed translation [2019-11-28 17:32:28,109 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:28 WrapperNode [2019-11-28 17:32:28,109 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-28 17:32:28,110 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-28 17:32:28,111 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-28 17:32:28,111 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-28 17:32:28,120 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:28" (1/1) ... [2019-11-28 17:32:28,129 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:28" (1/1) ... [2019-11-28 17:32:28,161 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-28 17:32:28,162 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-28 17:32:28,162 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-28 17:32:28,162 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-28 17:32:28,172 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:28" (1/1) ... [2019-11-28 17:32:28,172 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:28" (1/1) ... [2019-11-28 17:32:28,174 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:28" (1/1) ... [2019-11-28 17:32:28,175 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:28" (1/1) ... [2019-11-28 17:32:28,181 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:28" (1/1) ... [2019-11-28 17:32:28,192 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:28" (1/1) ... [2019-11-28 17:32:28,195 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:28" (1/1) ... [2019-11-28 17:32:28,200 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-28 17:32:28,201 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-28 17:32:28,201 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-28 17:32:28,201 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-28 17:32:28,202 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:28" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 17:32:28,267 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-28 17:32:28,268 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-28 17:32:28,957 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-28 17:32:28,957 INFO L287 CfgBuilder]: Removed 28 assume(true) statements. [2019-11-28 17:32:28,959 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 05:32:28 BoogieIcfgContainer [2019-11-28 17:32:28,959 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-28 17:32:28,961 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-28 17:32:28,961 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-28 17:32:28,966 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-28 17:32:28,968 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 05:32:27" (1/3) ... [2019-11-28 17:32:28,969 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3777e2e6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 05:32:28, skipping insertion in model container [2019-11-28 17:32:28,970 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:28" (2/3) ... [2019-11-28 17:32:28,970 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3777e2e6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 05:32:28, skipping insertion in model container [2019-11-28 17:32:28,971 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 05:32:28" (3/3) ... [2019-11-28 17:32:28,973 INFO L109 eAbstractionObserver]: Analyzing ICFG toy1.cil.c [2019-11-28 17:32:28,984 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-28 17:32:28,993 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-11-28 17:32:29,007 INFO L249 AbstractCegarLoop]: Starting to check reachability of 2 error locations. [2019-11-28 17:32:29,043 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-28 17:32:29,043 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-28 17:32:29,043 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-28 17:32:29,043 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-28 17:32:29,044 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-28 17:32:29,044 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-28 17:32:29,044 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-28 17:32:29,044 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-28 17:32:29,075 INFO L276 IsEmpty]: Start isEmpty. Operand 129 states. [2019-11-28 17:32:29,083 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-28 17:32:29,083 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:29,084 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:29,085 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:29,091 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:29,092 INFO L82 PathProgramCache]: Analyzing trace with hash -895778166, now seen corresponding path program 1 times [2019-11-28 17:32:29,101 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:29,102 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1165613431] [2019-11-28 17:32:29,102 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:29,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:29,286 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:29,287 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1165613431] [2019-11-28 17:32:29,288 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:29,289 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:29,291 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [217984007] [2019-11-28 17:32:29,297 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:29,298 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:29,312 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:29,313 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:29,315 INFO L87 Difference]: Start difference. First operand 129 states. Second operand 3 states. [2019-11-28 17:32:29,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:29,367 INFO L93 Difference]: Finished difference Result 250 states and 461 transitions. [2019-11-28 17:32:29,368 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:29,369 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 36 [2019-11-28 17:32:29,370 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:29,383 INFO L225 Difference]: With dead ends: 250 [2019-11-28 17:32:29,383 INFO L226 Difference]: Without dead ends: 125 [2019-11-28 17:32:29,387 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:29,405 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125 states. [2019-11-28 17:32:29,431 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125 to 125. [2019-11-28 17:32:29,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125 states. [2019-11-28 17:32:29,435 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 218 transitions. [2019-11-28 17:32:29,437 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 218 transitions. Word has length 36 [2019-11-28 17:32:29,437 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:29,438 INFO L462 AbstractCegarLoop]: Abstraction has 125 states and 218 transitions. [2019-11-28 17:32:29,438 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:29,438 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 218 transitions. [2019-11-28 17:32:29,440 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-28 17:32:29,440 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:29,440 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:29,441 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:29,441 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:29,441 INFO L82 PathProgramCache]: Analyzing trace with hash -1597378040, now seen corresponding path program 1 times [2019-11-28 17:32:29,442 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:29,442 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1827504983] [2019-11-28 17:32:29,442 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:29,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:29,500 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:29,505 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1827504983] [2019-11-28 17:32:29,505 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:29,506 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:29,506 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [686044432] [2019-11-28 17:32:29,510 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:29,511 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:29,511 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:29,511 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:29,512 INFO L87 Difference]: Start difference. First operand 125 states and 218 transitions. Second operand 3 states. [2019-11-28 17:32:29,566 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:29,566 INFO L93 Difference]: Finished difference Result 240 states and 420 transitions. [2019-11-28 17:32:29,567 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:29,567 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 36 [2019-11-28 17:32:29,567 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:29,569 INFO L225 Difference]: With dead ends: 240 [2019-11-28 17:32:29,569 INFO L226 Difference]: Without dead ends: 125 [2019-11-28 17:32:29,571 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:29,572 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125 states. [2019-11-28 17:32:29,585 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125 to 125. [2019-11-28 17:32:29,586 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125 states. [2019-11-28 17:32:29,587 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 217 transitions. [2019-11-28 17:32:29,588 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 217 transitions. Word has length 36 [2019-11-28 17:32:29,588 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:29,588 INFO L462 AbstractCegarLoop]: Abstraction has 125 states and 217 transitions. [2019-11-28 17:32:29,588 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:29,589 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 217 transitions. [2019-11-28 17:32:29,590 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-28 17:32:29,590 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:29,591 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:29,591 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:29,591 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:29,592 INFO L82 PathProgramCache]: Analyzing trace with hash -211174646, now seen corresponding path program 1 times [2019-11-28 17:32:29,592 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:29,592 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [628725170] [2019-11-28 17:32:29,592 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:29,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:29,697 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:29,698 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [628725170] [2019-11-28 17:32:29,698 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:29,699 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:29,699 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1531736599] [2019-11-28 17:32:29,699 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:29,700 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:29,700 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:29,700 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:29,701 INFO L87 Difference]: Start difference. First operand 125 states and 217 transitions. Second operand 3 states. [2019-11-28 17:32:29,818 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:29,818 INFO L93 Difference]: Finished difference Result 328 states and 568 transitions. [2019-11-28 17:32:29,819 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:29,819 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 36 [2019-11-28 17:32:29,819 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:29,822 INFO L225 Difference]: With dead ends: 328 [2019-11-28 17:32:29,822 INFO L226 Difference]: Without dead ends: 214 [2019-11-28 17:32:29,824 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:29,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 214 states. [2019-11-28 17:32:29,858 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 214 to 200. [2019-11-28 17:32:29,859 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 200 states. [2019-11-28 17:32:29,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 200 states to 200 states and 335 transitions. [2019-11-28 17:32:29,861 INFO L78 Accepts]: Start accepts. Automaton has 200 states and 335 transitions. Word has length 36 [2019-11-28 17:32:29,861 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:29,862 INFO L462 AbstractCegarLoop]: Abstraction has 200 states and 335 transitions. [2019-11-28 17:32:29,862 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:29,862 INFO L276 IsEmpty]: Start isEmpty. Operand 200 states and 335 transitions. [2019-11-28 17:32:29,864 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-28 17:32:29,866 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:29,866 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:29,867 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:29,867 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:29,867 INFO L82 PathProgramCache]: Analyzing trace with hash 1832431686, now seen corresponding path program 1 times [2019-11-28 17:32:29,868 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:29,868 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1834233600] [2019-11-28 17:32:29,868 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:29,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:29,946 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:29,946 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1834233600] [2019-11-28 17:32:29,946 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:29,947 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 17:32:29,947 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1095024726] [2019-11-28 17:32:29,948 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 17:32:29,948 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:29,948 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 17:32:29,948 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 17:32:29,949 INFO L87 Difference]: Start difference. First operand 200 states and 335 transitions. Second operand 4 states. [2019-11-28 17:32:30,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:30,140 INFO L93 Difference]: Finished difference Result 542 states and 911 transitions. [2019-11-28 17:32:30,141 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 17:32:30,141 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2019-11-28 17:32:30,141 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:30,144 INFO L225 Difference]: With dead ends: 542 [2019-11-28 17:32:30,145 INFO L226 Difference]: Without dead ends: 354 [2019-11-28 17:32:30,150 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:32:30,152 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 354 states. [2019-11-28 17:32:30,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 354 to 344. [2019-11-28 17:32:30,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 344 states. [2019-11-28 17:32:30,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 344 states to 344 states and 577 transitions. [2019-11-28 17:32:30,206 INFO L78 Accepts]: Start accepts. Automaton has 344 states and 577 transitions. Word has length 36 [2019-11-28 17:32:30,206 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:30,206 INFO L462 AbstractCegarLoop]: Abstraction has 344 states and 577 transitions. [2019-11-28 17:32:30,206 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 17:32:30,206 INFO L276 IsEmpty]: Start isEmpty. Operand 344 states and 577 transitions. [2019-11-28 17:32:30,211 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-28 17:32:30,211 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:30,211 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:30,216 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:30,216 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:30,216 INFO L82 PathProgramCache]: Analyzing trace with hash -539307576, now seen corresponding path program 1 times [2019-11-28 17:32:30,217 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:30,217 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [569271540] [2019-11-28 17:32:30,217 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:30,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:30,309 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:30,310 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [569271540] [2019-11-28 17:32:30,310 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:30,310 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 17:32:30,310 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [594139445] [2019-11-28 17:32:30,311 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 17:32:30,311 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:30,312 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 17:32:30,312 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 17:32:30,313 INFO L87 Difference]: Start difference. First operand 344 states and 577 transitions. Second operand 4 states. [2019-11-28 17:32:30,450 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:30,450 INFO L93 Difference]: Finished difference Result 967 states and 1626 transitions. [2019-11-28 17:32:30,451 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 17:32:30,451 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2019-11-28 17:32:30,451 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:30,456 INFO L225 Difference]: With dead ends: 967 [2019-11-28 17:32:30,456 INFO L226 Difference]: Without dead ends: 636 [2019-11-28 17:32:30,459 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:32:30,461 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 636 states. [2019-11-28 17:32:30,502 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 636 to 626. [2019-11-28 17:32:30,502 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 626 states. [2019-11-28 17:32:30,507 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 1047 transitions. [2019-11-28 17:32:30,507 INFO L78 Accepts]: Start accepts. Automaton has 626 states and 1047 transitions. Word has length 36 [2019-11-28 17:32:30,508 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:30,508 INFO L462 AbstractCegarLoop]: Abstraction has 626 states and 1047 transitions. [2019-11-28 17:32:30,508 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 17:32:30,508 INFO L276 IsEmpty]: Start isEmpty. Operand 626 states and 1047 transitions. [2019-11-28 17:32:30,510 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-28 17:32:30,511 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:30,511 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:30,511 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:30,512 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:30,512 INFO L82 PathProgramCache]: Analyzing trace with hash -477267962, now seen corresponding path program 1 times [2019-11-28 17:32:30,513 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:30,513 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1330324721] [2019-11-28 17:32:30,514 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:30,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:30,587 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:30,588 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1330324721] [2019-11-28 17:32:30,588 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:30,590 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 17:32:30,590 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [955538398] [2019-11-28 17:32:30,590 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 17:32:30,591 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:30,591 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 17:32:30,592 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 17:32:30,592 INFO L87 Difference]: Start difference. First operand 626 states and 1047 transitions. Second operand 4 states. [2019-11-28 17:32:30,757 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:30,757 INFO L93 Difference]: Finished difference Result 1903 states and 3163 transitions. [2019-11-28 17:32:30,758 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 17:32:30,758 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2019-11-28 17:32:30,758 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:30,766 INFO L225 Difference]: With dead ends: 1903 [2019-11-28 17:32:30,767 INFO L226 Difference]: Without dead ends: 1291 [2019-11-28 17:32:30,769 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:32:30,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1291 states. [2019-11-28 17:32:30,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1291 to 1281. [2019-11-28 17:32:30,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1281 states. [2019-11-28 17:32:30,844 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1281 states to 1281 states and 2107 transitions. [2019-11-28 17:32:30,845 INFO L78 Accepts]: Start accepts. Automaton has 1281 states and 2107 transitions. Word has length 36 [2019-11-28 17:32:30,847 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:30,847 INFO L462 AbstractCegarLoop]: Abstraction has 1281 states and 2107 transitions. [2019-11-28 17:32:30,848 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 17:32:30,848 INFO L276 IsEmpty]: Start isEmpty. Operand 1281 states and 2107 transitions. [2019-11-28 17:32:30,850 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-28 17:32:30,850 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:30,850 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:30,850 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:30,851 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:30,851 INFO L82 PathProgramCache]: Analyzing trace with hash -336719352, now seen corresponding path program 1 times [2019-11-28 17:32:30,851 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:30,851 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [76823292] [2019-11-28 17:32:30,852 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:30,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:30,905 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:30,906 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [76823292] [2019-11-28 17:32:30,906 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:30,906 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:30,907 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [763723193] [2019-11-28 17:32:30,907 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:30,907 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:30,907 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:30,908 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:30,908 INFO L87 Difference]: Start difference. First operand 1281 states and 2107 transitions. Second operand 3 states. [2019-11-28 17:32:31,039 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:31,040 INFO L93 Difference]: Finished difference Result 2615 states and 4310 transitions. [2019-11-28 17:32:31,040 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:31,041 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 36 [2019-11-28 17:32:31,041 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:31,049 INFO L225 Difference]: With dead ends: 2615 [2019-11-28 17:32:31,049 INFO L226 Difference]: Without dead ends: 1391 [2019-11-28 17:32:31,052 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:31,055 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1391 states. [2019-11-28 17:32:31,118 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1391 to 1382. [2019-11-28 17:32:31,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1382 states. [2019-11-28 17:32:31,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1382 states to 1382 states and 2266 transitions. [2019-11-28 17:32:31,126 INFO L78 Accepts]: Start accepts. Automaton has 1382 states and 2266 transitions. Word has length 36 [2019-11-28 17:32:31,126 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:31,126 INFO L462 AbstractCegarLoop]: Abstraction has 1382 states and 2266 transitions. [2019-11-28 17:32:31,127 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:31,127 INFO L276 IsEmpty]: Start isEmpty. Operand 1382 states and 2266 transitions. [2019-11-28 17:32:31,130 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-28 17:32:31,130 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:31,131 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:31,131 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:31,131 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:31,132 INFO L82 PathProgramCache]: Analyzing trace with hash 952985988, now seen corresponding path program 1 times [2019-11-28 17:32:31,132 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:31,133 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1086450991] [2019-11-28 17:32:31,133 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:31,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:31,190 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:31,190 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1086450991] [2019-11-28 17:32:31,190 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:31,191 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 17:32:31,191 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1695860574] [2019-11-28 17:32:31,191 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 17:32:31,192 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:31,193 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 17:32:31,194 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 17:32:31,194 INFO L87 Difference]: Start difference. First operand 1382 states and 2266 transitions. Second operand 4 states. [2019-11-28 17:32:31,366 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:31,366 INFO L93 Difference]: Finished difference Result 2900 states and 4764 transitions. [2019-11-28 17:32:31,367 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-28 17:32:31,367 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2019-11-28 17:32:31,367 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:31,375 INFO L225 Difference]: With dead ends: 2900 [2019-11-28 17:32:31,376 INFO L226 Difference]: Without dead ends: 1552 [2019-11-28 17:32:31,378 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:32:31,380 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1552 states. [2019-11-28 17:32:31,450 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1552 to 1539. [2019-11-28 17:32:31,450 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1539 states. [2019-11-28 17:32:31,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1539 states to 1539 states and 2488 transitions. [2019-11-28 17:32:31,457 INFO L78 Accepts]: Start accepts. Automaton has 1539 states and 2488 transitions. Word has length 36 [2019-11-28 17:32:31,457 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:31,458 INFO L462 AbstractCegarLoop]: Abstraction has 1539 states and 2488 transitions. [2019-11-28 17:32:31,458 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 17:32:31,458 INFO L276 IsEmpty]: Start isEmpty. Operand 1539 states and 2488 transitions. [2019-11-28 17:32:31,459 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-28 17:32:31,459 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:31,459 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:31,460 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:31,460 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:31,460 INFO L82 PathProgramCache]: Analyzing trace with hash -635361914, now seen corresponding path program 1 times [2019-11-28 17:32:31,461 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:31,461 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1481238282] [2019-11-28 17:32:31,462 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:31,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:31,501 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:31,502 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1481238282] [2019-11-28 17:32:31,502 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:31,502 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 17:32:31,503 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [160026914] [2019-11-28 17:32:31,503 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 17:32:31,503 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:31,504 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 17:32:31,505 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 17:32:31,505 INFO L87 Difference]: Start difference. First operand 1539 states and 2488 transitions. Second operand 4 states. [2019-11-28 17:32:31,655 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:31,655 INFO L93 Difference]: Finished difference Result 3378 states and 5467 transitions. [2019-11-28 17:32:31,656 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-28 17:32:31,656 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2019-11-28 17:32:31,657 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:31,667 INFO L225 Difference]: With dead ends: 3378 [2019-11-28 17:32:31,667 INFO L226 Difference]: Without dead ends: 1885 [2019-11-28 17:32:31,671 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:32:31,673 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1885 states. [2019-11-28 17:32:31,764 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1885 to 1859. [2019-11-28 17:32:31,765 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1859 states. [2019-11-28 17:32:31,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1859 states to 1859 states and 2968 transitions. [2019-11-28 17:32:31,774 INFO L78 Accepts]: Start accepts. Automaton has 1859 states and 2968 transitions. Word has length 36 [2019-11-28 17:32:31,774 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:31,774 INFO L462 AbstractCegarLoop]: Abstraction has 1859 states and 2968 transitions. [2019-11-28 17:32:31,774 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 17:32:31,775 INFO L276 IsEmpty]: Start isEmpty. Operand 1859 states and 2968 transitions. [2019-11-28 17:32:31,776 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2019-11-28 17:32:31,776 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:31,776 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:31,777 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:31,777 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:31,778 INFO L82 PathProgramCache]: Analyzing trace with hash -1915225592, now seen corresponding path program 1 times [2019-11-28 17:32:31,778 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:31,779 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1972816062] [2019-11-28 17:32:31,779 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:31,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:31,817 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:31,818 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1972816062] [2019-11-28 17:32:31,818 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:31,818 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:31,819 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1797400194] [2019-11-28 17:32:31,819 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:31,819 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:31,819 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:31,820 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:31,820 INFO L87 Difference]: Start difference. First operand 1859 states and 2968 transitions. Second operand 3 states. [2019-11-28 17:32:31,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:31,936 INFO L93 Difference]: Finished difference Result 3335 states and 5328 transitions. [2019-11-28 17:32:31,937 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:31,937 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 36 [2019-11-28 17:32:31,939 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:31,947 INFO L225 Difference]: With dead ends: 3335 [2019-11-28 17:32:31,948 INFO L226 Difference]: Without dead ends: 1504 [2019-11-28 17:32:31,952 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:31,954 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1504 states. [2019-11-28 17:32:32,019 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1504 to 1493. [2019-11-28 17:32:32,020 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1493 states. [2019-11-28 17:32:32,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1493 states to 1493 states and 2352 transitions. [2019-11-28 17:32:32,026 INFO L78 Accepts]: Start accepts. Automaton has 1493 states and 2352 transitions. Word has length 36 [2019-11-28 17:32:32,030 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:32,030 INFO L462 AbstractCegarLoop]: Abstraction has 1493 states and 2352 transitions. [2019-11-28 17:32:32,030 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:32,031 INFO L276 IsEmpty]: Start isEmpty. Operand 1493 states and 2352 transitions. [2019-11-28 17:32:32,033 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2019-11-28 17:32:32,033 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:32,034 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:32,034 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:32,034 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:32,035 INFO L82 PathProgramCache]: Analyzing trace with hash -547155332, now seen corresponding path program 1 times [2019-11-28 17:32:32,035 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:32,035 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1200674696] [2019-11-28 17:32:32,036 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:32,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:32,079 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:32,080 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1200674696] [2019-11-28 17:32:32,080 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:32,080 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:32,081 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1130638153] [2019-11-28 17:32:32,081 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:32,081 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:32,081 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:32,082 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:32,082 INFO L87 Difference]: Start difference. First operand 1493 states and 2352 transitions. Second operand 3 states. [2019-11-28 17:32:32,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:32,209 INFO L93 Difference]: Finished difference Result 3728 states and 5928 transitions. [2019-11-28 17:32:32,210 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:32,210 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 46 [2019-11-28 17:32:32,210 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:32,222 INFO L225 Difference]: With dead ends: 3728 [2019-11-28 17:32:32,222 INFO L226 Difference]: Without dead ends: 2289 [2019-11-28 17:32:32,225 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:32,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2289 states. [2019-11-28 17:32:32,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2289 to 2285. [2019-11-28 17:32:32,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2285 states. [2019-11-28 17:32:32,354 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2285 states to 2285 states and 3596 transitions. [2019-11-28 17:32:32,355 INFO L78 Accepts]: Start accepts. Automaton has 2285 states and 3596 transitions. Word has length 46 [2019-11-28 17:32:32,355 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:32,355 INFO L462 AbstractCegarLoop]: Abstraction has 2285 states and 3596 transitions. [2019-11-28 17:32:32,355 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:32,355 INFO L276 IsEmpty]: Start isEmpty. Operand 2285 states and 3596 transitions. [2019-11-28 17:32:32,358 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2019-11-28 17:32:32,358 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:32,358 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:32,359 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:32,359 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:32,359 INFO L82 PathProgramCache]: Analyzing trace with hash -299008838, now seen corresponding path program 1 times [2019-11-28 17:32:32,359 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:32,361 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [187645743] [2019-11-28 17:32:32,362 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:32,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:32,392 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2019-11-28 17:32:32,392 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [187645743] [2019-11-28 17:32:32,392 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:32,392 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:32,393 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1389145944] [2019-11-28 17:32:32,393 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:32,394 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:32,394 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:32,394 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:32,394 INFO L87 Difference]: Start difference. First operand 2285 states and 3596 transitions. Second operand 3 states. [2019-11-28 17:32:32,500 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:32,501 INFO L93 Difference]: Finished difference Result 4472 states and 7066 transitions. [2019-11-28 17:32:32,501 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:32,502 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 46 [2019-11-28 17:32:32,502 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:32,515 INFO L225 Difference]: With dead ends: 4472 [2019-11-28 17:32:32,515 INFO L226 Difference]: Without dead ends: 2241 [2019-11-28 17:32:32,519 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:32,522 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2241 states. [2019-11-28 17:32:32,639 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2241 to 2241. [2019-11-28 17:32:32,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2241 states. [2019-11-28 17:32:32,649 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2241 states to 2241 states and 3539 transitions. [2019-11-28 17:32:32,650 INFO L78 Accepts]: Start accepts. Automaton has 2241 states and 3539 transitions. Word has length 46 [2019-11-28 17:32:32,650 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:32,650 INFO L462 AbstractCegarLoop]: Abstraction has 2241 states and 3539 transitions. [2019-11-28 17:32:32,651 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:32,651 INFO L276 IsEmpty]: Start isEmpty. Operand 2241 states and 3539 transitions. [2019-11-28 17:32:32,653 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2019-11-28 17:32:32,653 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:32,654 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:32,654 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:32,654 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:32,655 INFO L82 PathProgramCache]: Analyzing trace with hash -336670593, now seen corresponding path program 1 times [2019-11-28 17:32:32,655 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:32,655 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1344140276] [2019-11-28 17:32:32,656 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:32,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:32,710 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:32,711 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1344140276] [2019-11-28 17:32:32,711 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:32,712 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:32,712 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [882199834] [2019-11-28 17:32:32,712 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:32,713 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:32,713 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:32,714 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:32,714 INFO L87 Difference]: Start difference. First operand 2241 states and 3539 transitions. Second operand 3 states. [2019-11-28 17:32:32,941 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:32,941 INFO L93 Difference]: Finished difference Result 5761 states and 9163 transitions. [2019-11-28 17:32:32,942 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:32,942 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 47 [2019-11-28 17:32:32,942 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:32,967 INFO L225 Difference]: With dead ends: 5761 [2019-11-28 17:32:32,967 INFO L226 Difference]: Without dead ends: 3574 [2019-11-28 17:32:32,974 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:32,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3574 states. [2019-11-28 17:32:33,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3574 to 3570. [2019-11-28 17:32:33,196 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3570 states. [2019-11-28 17:32:33,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3570 states to 3570 states and 5623 transitions. [2019-11-28 17:32:33,215 INFO L78 Accepts]: Start accepts. Automaton has 3570 states and 5623 transitions. Word has length 47 [2019-11-28 17:32:33,216 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:33,216 INFO L462 AbstractCegarLoop]: Abstraction has 3570 states and 5623 transitions. [2019-11-28 17:32:33,216 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:33,216 INFO L276 IsEmpty]: Start isEmpty. Operand 3570 states and 5623 transitions. [2019-11-28 17:32:33,219 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2019-11-28 17:32:33,220 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:33,220 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:33,220 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:33,221 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:33,221 INFO L82 PathProgramCache]: Analyzing trace with hash 1825522215, now seen corresponding path program 1 times [2019-11-28 17:32:33,221 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:33,226 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2133609663] [2019-11-28 17:32:33,226 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:33,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:33,260 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:33,261 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2133609663] [2019-11-28 17:32:33,261 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:33,261 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:33,261 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [994037980] [2019-11-28 17:32:33,262 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:33,262 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:33,262 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:33,262 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:33,263 INFO L87 Difference]: Start difference. First operand 3570 states and 5623 transitions. Second operand 3 states. [2019-11-28 17:32:33,552 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:33,552 INFO L93 Difference]: Finished difference Result 9081 states and 14487 transitions. [2019-11-28 17:32:33,553 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:33,553 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2019-11-28 17:32:33,554 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:33,584 INFO L225 Difference]: With dead ends: 9081 [2019-11-28 17:32:33,584 INFO L226 Difference]: Without dead ends: 5569 [2019-11-28 17:32:33,592 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:33,599 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5569 states. [2019-11-28 17:32:33,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5569 to 5565. [2019-11-28 17:32:33,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5565 states. [2019-11-28 17:32:33,907 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5565 states to 5565 states and 8840 transitions. [2019-11-28 17:32:33,908 INFO L78 Accepts]: Start accepts. Automaton has 5565 states and 8840 transitions. Word has length 48 [2019-11-28 17:32:33,910 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:33,910 INFO L462 AbstractCegarLoop]: Abstraction has 5565 states and 8840 transitions. [2019-11-28 17:32:33,910 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:33,910 INFO L276 IsEmpty]: Start isEmpty. Operand 5565 states and 8840 transitions. [2019-11-28 17:32:33,915 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2019-11-28 17:32:33,916 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:33,916 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:33,916 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:33,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:33,917 INFO L82 PathProgramCache]: Analyzing trace with hash 2073668709, now seen corresponding path program 1 times [2019-11-28 17:32:33,917 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:33,918 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [912342351] [2019-11-28 17:32:33,918 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:33,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:33,939 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2019-11-28 17:32:33,939 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [912342351] [2019-11-28 17:32:33,939 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:33,939 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:33,940 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [473057846] [2019-11-28 17:32:33,940 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:33,940 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:33,940 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:33,940 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:33,941 INFO L87 Difference]: Start difference. First operand 5565 states and 8840 transitions. Second operand 3 states. [2019-11-28 17:32:34,225 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:34,225 INFO L93 Difference]: Finished difference Result 11028 states and 17554 transitions. [2019-11-28 17:32:34,226 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:34,226 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2019-11-28 17:32:34,226 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:34,271 INFO L225 Difference]: With dead ends: 11028 [2019-11-28 17:32:34,272 INFO L226 Difference]: Without dead ends: 5521 [2019-11-28 17:32:34,283 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:34,291 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5521 states. [2019-11-28 17:32:34,580 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5521 to 5521. [2019-11-28 17:32:34,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5521 states. [2019-11-28 17:32:34,594 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5521 states to 5521 states and 8785 transitions. [2019-11-28 17:32:34,595 INFO L78 Accepts]: Start accepts. Automaton has 5521 states and 8785 transitions. Word has length 48 [2019-11-28 17:32:34,595 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:34,595 INFO L462 AbstractCegarLoop]: Abstraction has 5521 states and 8785 transitions. [2019-11-28 17:32:34,595 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:34,595 INFO L276 IsEmpty]: Start isEmpty. Operand 5521 states and 8785 transitions. [2019-11-28 17:32:34,599 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-11-28 17:32:34,599 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:34,599 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:34,599 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:34,600 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:34,600 INFO L82 PathProgramCache]: Analyzing trace with hash 963117268, now seen corresponding path program 1 times [2019-11-28 17:32:34,600 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:34,600 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1866106261] [2019-11-28 17:32:34,600 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:34,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:34,626 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:34,626 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1866106261] [2019-11-28 17:32:34,626 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:34,626 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:34,627 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1243222093] [2019-11-28 17:32:34,627 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:34,627 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:34,627 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:34,628 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:34,628 INFO L87 Difference]: Start difference. First operand 5521 states and 8785 transitions. Second operand 3 states. [2019-11-28 17:32:35,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:35,064 INFO L93 Difference]: Finished difference Result 15573 states and 24710 transitions. [2019-11-28 17:32:35,065 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:35,065 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 49 [2019-11-28 17:32:35,065 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:35,095 INFO L225 Difference]: With dead ends: 15573 [2019-11-28 17:32:35,096 INFO L226 Difference]: Without dead ends: 8340 [2019-11-28 17:32:35,111 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:35,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8340 states. [2019-11-28 17:32:35,469 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8340 to 8340. [2019-11-28 17:32:35,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8340 states. [2019-11-28 17:32:35,488 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8340 states to 8340 states and 13079 transitions. [2019-11-28 17:32:35,489 INFO L78 Accepts]: Start accepts. Automaton has 8340 states and 13079 transitions. Word has length 49 [2019-11-28 17:32:35,490 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:35,490 INFO L462 AbstractCegarLoop]: Abstraction has 8340 states and 13079 transitions. [2019-11-28 17:32:35,490 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:35,490 INFO L276 IsEmpty]: Start isEmpty. Operand 8340 states and 13079 transitions. [2019-11-28 17:32:35,497 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2019-11-28 17:32:35,498 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:35,498 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:35,498 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:35,498 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:35,499 INFO L82 PathProgramCache]: Analyzing trace with hash 1798060104, now seen corresponding path program 1 times [2019-11-28 17:32:35,499 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:35,499 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1062430712] [2019-11-28 17:32:35,500 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:35,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:35,551 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:35,552 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1062430712] [2019-11-28 17:32:35,552 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:35,552 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:35,553 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1182302489] [2019-11-28 17:32:35,553 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:35,553 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:35,553 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:35,553 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:35,554 INFO L87 Difference]: Start difference. First operand 8340 states and 13079 transitions. Second operand 3 states. [2019-11-28 17:32:35,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:35,957 INFO L93 Difference]: Finished difference Result 17187 states and 26897 transitions. [2019-11-28 17:32:35,957 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:35,958 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 53 [2019-11-28 17:32:35,958 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:35,981 INFO L225 Difference]: With dead ends: 17187 [2019-11-28 17:32:35,982 INFO L226 Difference]: Without dead ends: 8883 [2019-11-28 17:32:35,997 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:36,008 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8883 states. [2019-11-28 17:32:36,307 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8883 to 8322. [2019-11-28 17:32:36,308 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8322 states. [2019-11-28 17:32:36,325 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8322 states to 8322 states and 12796 transitions. [2019-11-28 17:32:36,326 INFO L78 Accepts]: Start accepts. Automaton has 8322 states and 12796 transitions. Word has length 53 [2019-11-28 17:32:36,326 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:36,326 INFO L462 AbstractCegarLoop]: Abstraction has 8322 states and 12796 transitions. [2019-11-28 17:32:36,326 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:36,326 INFO L276 IsEmpty]: Start isEmpty. Operand 8322 states and 12796 transitions. [2019-11-28 17:32:36,333 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2019-11-28 17:32:36,333 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:36,333 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:36,334 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:36,334 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:36,334 INFO L82 PathProgramCache]: Analyzing trace with hash -833394239, now seen corresponding path program 1 times [2019-11-28 17:32:36,335 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:36,335 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1974966275] [2019-11-28 17:32:36,335 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:36,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:36,357 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2019-11-28 17:32:36,357 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1974966275] [2019-11-28 17:32:36,358 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:36,358 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:36,358 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1424798925] [2019-11-28 17:32:36,359 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:36,359 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:36,359 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:36,360 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:36,360 INFO L87 Difference]: Start difference. First operand 8322 states and 12796 transitions. Second operand 3 states. [2019-11-28 17:32:37,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:37,097 INFO L93 Difference]: Finished difference Result 24654 states and 37995 transitions. [2019-11-28 17:32:37,097 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:37,097 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 55 [2019-11-28 17:32:37,098 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:37,133 INFO L225 Difference]: With dead ends: 24654 [2019-11-28 17:32:37,133 INFO L226 Difference]: Without dead ends: 16335 [2019-11-28 17:32:37,146 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:37,169 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16335 states. [2019-11-28 17:32:37,818 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16335 to 16203. [2019-11-28 17:32:37,819 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16203 states. [2019-11-28 17:32:37,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16203 states to 16203 states and 25040 transitions. [2019-11-28 17:32:37,849 INFO L78 Accepts]: Start accepts. Automaton has 16203 states and 25040 transitions. Word has length 55 [2019-11-28 17:32:37,850 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:37,850 INFO L462 AbstractCegarLoop]: Abstraction has 16203 states and 25040 transitions. [2019-11-28 17:32:37,850 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:37,850 INFO L276 IsEmpty]: Start isEmpty. Operand 16203 states and 25040 transitions. [2019-11-28 17:32:37,861 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2019-11-28 17:32:37,861 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:37,861 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:37,862 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:37,862 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:37,862 INFO L82 PathProgramCache]: Analyzing trace with hash -539805076, now seen corresponding path program 1 times [2019-11-28 17:32:37,863 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:37,863 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [948642024] [2019-11-28 17:32:37,863 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:37,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:37,900 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:37,900 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [948642024] [2019-11-28 17:32:37,900 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:37,901 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:37,901 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [240495300] [2019-11-28 17:32:37,901 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:37,902 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:37,902 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:37,902 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:37,903 INFO L87 Difference]: Start difference. First operand 16203 states and 25040 transitions. Second operand 3 states. [2019-11-28 17:32:38,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:38,703 INFO L93 Difference]: Finished difference Result 33061 states and 51038 transitions. [2019-11-28 17:32:38,704 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:38,704 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 86 [2019-11-28 17:32:38,705 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:38,757 INFO L225 Difference]: With dead ends: 33061 [2019-11-28 17:32:38,758 INFO L226 Difference]: Without dead ends: 16887 [2019-11-28 17:32:38,794 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:38,818 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16887 states. [2019-11-28 17:32:39,388 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16887 to 16823. [2019-11-28 17:32:39,388 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16823 states. [2019-11-28 17:32:39,428 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16823 states to 16823 states and 25342 transitions. [2019-11-28 17:32:39,428 INFO L78 Accepts]: Start accepts. Automaton has 16823 states and 25342 transitions. Word has length 86 [2019-11-28 17:32:39,429 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:39,429 INFO L462 AbstractCegarLoop]: Abstraction has 16823 states and 25342 transitions. [2019-11-28 17:32:39,429 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:39,429 INFO L276 IsEmpty]: Start isEmpty. Operand 16823 states and 25342 transitions. [2019-11-28 17:32:39,441 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2019-11-28 17:32:39,441 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:39,442 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:39,442 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:39,442 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:39,443 INFO L82 PathProgramCache]: Analyzing trace with hash -1404681213, now seen corresponding path program 1 times [2019-11-28 17:32:39,443 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:39,443 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [474406470] [2019-11-28 17:32:39,443 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:39,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:39,495 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-11-28 17:32:39,496 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [474406470] [2019-11-28 17:32:39,496 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:39,496 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 17:32:39,497 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [951541084] [2019-11-28 17:32:39,500 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 17:32:39,500 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:39,500 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 17:32:39,501 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 17:32:39,501 INFO L87 Difference]: Start difference. First operand 16823 states and 25342 transitions. Second operand 4 states. [2019-11-28 17:32:40,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:40,167 INFO L93 Difference]: Finished difference Result 27813 states and 42042 transitions. [2019-11-28 17:32:40,167 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-28 17:32:40,168 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 87 [2019-11-28 17:32:40,168 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:40,368 INFO L225 Difference]: With dead ends: 27813 [2019-11-28 17:32:40,368 INFO L226 Difference]: Without dead ends: 15935 [2019-11-28 17:32:40,378 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:32:40,390 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15935 states. [2019-11-28 17:32:41,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15935 to 15811. [2019-11-28 17:32:41,089 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15811 states. [2019-11-28 17:32:41,135 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15811 states to 15811 states and 23636 transitions. [2019-11-28 17:32:41,135 INFO L78 Accepts]: Start accepts. Automaton has 15811 states and 23636 transitions. Word has length 87 [2019-11-28 17:32:41,136 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:41,136 INFO L462 AbstractCegarLoop]: Abstraction has 15811 states and 23636 transitions. [2019-11-28 17:32:41,137 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 17:32:41,137 INFO L276 IsEmpty]: Start isEmpty. Operand 15811 states and 23636 transitions. [2019-11-28 17:32:41,147 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2019-11-28 17:32:41,148 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:41,148 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:41,148 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:41,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:41,149 INFO L82 PathProgramCache]: Analyzing trace with hash 1520792899, now seen corresponding path program 1 times [2019-11-28 17:32:41,150 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:41,150 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2130486265] [2019-11-28 17:32:41,150 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:41,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:41,201 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:41,203 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2130486265] [2019-11-28 17:32:41,204 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:41,204 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:41,204 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [571888387] [2019-11-28 17:32:41,205 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:41,205 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:41,206 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:41,206 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:41,206 INFO L87 Difference]: Start difference. First operand 15811 states and 23636 transitions. Second operand 3 states. [2019-11-28 17:32:41,810 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:41,810 INFO L93 Difference]: Finished difference Result 32391 states and 48370 transitions. [2019-11-28 17:32:41,810 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:41,810 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 87 [2019-11-28 17:32:41,811 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:41,847 INFO L225 Difference]: With dead ends: 32391 [2019-11-28 17:32:41,847 INFO L226 Difference]: Without dead ends: 16621 [2019-11-28 17:32:41,865 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:41,880 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16621 states. [2019-11-28 17:32:42,725 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16621 to 16541. [2019-11-28 17:32:42,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16541 states. [2019-11-28 17:32:42,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16541 states to 16541 states and 24008 transitions. [2019-11-28 17:32:42,754 INFO L78 Accepts]: Start accepts. Automaton has 16541 states and 24008 transitions. Word has length 87 [2019-11-28 17:32:42,754 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:42,755 INFO L462 AbstractCegarLoop]: Abstraction has 16541 states and 24008 transitions. [2019-11-28 17:32:42,755 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:42,755 INFO L276 IsEmpty]: Start isEmpty. Operand 16541 states and 24008 transitions. [2019-11-28 17:32:42,760 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2019-11-28 17:32:42,761 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:42,761 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:42,761 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:42,761 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:42,761 INFO L82 PathProgramCache]: Analyzing trace with hash -1973365524, now seen corresponding path program 1 times [2019-11-28 17:32:42,762 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:42,762 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1208728730] [2019-11-28 17:32:42,762 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:42,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:42,801 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:42,801 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1208728730] [2019-11-28 17:32:42,801 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:42,802 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:42,802 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [462464309] [2019-11-28 17:32:42,802 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:42,802 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:42,803 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:42,803 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:42,803 INFO L87 Difference]: Start difference. First operand 16541 states and 24008 transitions. Second operand 3 states. [2019-11-28 17:32:43,284 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:43,285 INFO L93 Difference]: Finished difference Result 33498 states and 48738 transitions. [2019-11-28 17:32:43,285 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:43,285 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 88 [2019-11-28 17:32:43,286 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:43,312 INFO L225 Difference]: With dead ends: 33498 [2019-11-28 17:32:43,312 INFO L226 Difference]: Without dead ends: 17018 [2019-11-28 17:32:43,333 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:43,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17018 states. [2019-11-28 17:32:43,920 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17018 to 13513. [2019-11-28 17:32:43,921 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13513 states. [2019-11-28 17:32:43,948 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13513 states to 13513 states and 18922 transitions. [2019-11-28 17:32:43,949 INFO L78 Accepts]: Start accepts. Automaton has 13513 states and 18922 transitions. Word has length 88 [2019-11-28 17:32:43,949 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:43,949 INFO L462 AbstractCegarLoop]: Abstraction has 13513 states and 18922 transitions. [2019-11-28 17:32:43,949 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:43,950 INFO L276 IsEmpty]: Start isEmpty. Operand 13513 states and 18922 transitions. [2019-11-28 17:32:43,958 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2019-11-28 17:32:43,959 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:43,959 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:43,959 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:43,960 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:43,960 INFO L82 PathProgramCache]: Analyzing trace with hash 663253701, now seen corresponding path program 1 times [2019-11-28 17:32:43,960 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:43,961 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1462481697] [2019-11-28 17:32:43,961 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:43,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:44,004 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-11-28 17:32:44,004 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1462481697] [2019-11-28 17:32:44,005 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:44,005 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:44,005 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1930864716] [2019-11-28 17:32:44,005 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:44,008 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:44,008 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:44,008 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:44,009 INFO L87 Difference]: Start difference. First operand 13513 states and 18922 transitions. Second operand 3 states. [2019-11-28 17:32:44,845 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:44,845 INFO L93 Difference]: Finished difference Result 24045 states and 33699 transitions. [2019-11-28 17:32:44,846 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:44,846 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 89 [2019-11-28 17:32:44,846 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:44,864 INFO L225 Difference]: With dead ends: 24045 [2019-11-28 17:32:44,864 INFO L226 Difference]: Without dead ends: 15655 [2019-11-28 17:32:44,874 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:44,889 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15655 states. [2019-11-28 17:32:45,329 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15655 to 15175. [2019-11-28 17:32:45,329 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15175 states. [2019-11-28 17:32:45,352 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15175 states to 15175 states and 20753 transitions. [2019-11-28 17:32:45,353 INFO L78 Accepts]: Start accepts. Automaton has 15175 states and 20753 transitions. Word has length 89 [2019-11-28 17:32:45,353 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:45,353 INFO L462 AbstractCegarLoop]: Abstraction has 15175 states and 20753 transitions. [2019-11-28 17:32:45,353 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:45,353 INFO L276 IsEmpty]: Start isEmpty. Operand 15175 states and 20753 transitions. [2019-11-28 17:32:45,368 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2019-11-28 17:32:45,368 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:45,368 INFO L410 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:45,369 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:45,369 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:45,369 INFO L82 PathProgramCache]: Analyzing trace with hash 1690650567, now seen corresponding path program 1 times [2019-11-28 17:32:45,369 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:45,370 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [251484360] [2019-11-28 17:32:45,370 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:45,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:45,412 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2019-11-28 17:32:45,413 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [251484360] [2019-11-28 17:32:45,413 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:45,413 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:45,413 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [374801427] [2019-11-28 17:32:45,414 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:45,414 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:45,414 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:45,415 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:45,415 INFO L87 Difference]: Start difference. First operand 15175 states and 20753 transitions. Second operand 3 states. [2019-11-28 17:32:45,821 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:45,821 INFO L93 Difference]: Finished difference Result 29588 states and 40424 transitions. [2019-11-28 17:32:45,821 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:45,822 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 116 [2019-11-28 17:32:45,822 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:45,837 INFO L225 Difference]: With dead ends: 29588 [2019-11-28 17:32:45,838 INFO L226 Difference]: Without dead ends: 15105 [2019-11-28 17:32:45,851 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:45,865 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15105 states. [2019-11-28 17:32:46,586 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15105 to 15105. [2019-11-28 17:32:46,586 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15105 states. [2019-11-28 17:32:46,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15105 states to 15105 states and 20599 transitions. [2019-11-28 17:32:46,605 INFO L78 Accepts]: Start accepts. Automaton has 15105 states and 20599 transitions. Word has length 116 [2019-11-28 17:32:46,605 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:46,605 INFO L462 AbstractCegarLoop]: Abstraction has 15105 states and 20599 transitions. [2019-11-28 17:32:46,605 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:46,606 INFO L276 IsEmpty]: Start isEmpty. Operand 15105 states and 20599 transitions. [2019-11-28 17:32:46,620 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2019-11-28 17:32:46,620 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:46,621 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:46,621 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:46,621 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:46,621 INFO L82 PathProgramCache]: Analyzing trace with hash -1184080698, now seen corresponding path program 1 times [2019-11-28 17:32:46,621 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:46,621 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1279039213] [2019-11-28 17:32:46,621 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:46,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:46,650 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2019-11-28 17:32:46,651 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1279039213] [2019-11-28 17:32:46,651 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:46,651 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:46,651 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1685547784] [2019-11-28 17:32:46,652 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:46,652 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:46,652 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:46,653 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:46,653 INFO L87 Difference]: Start difference. First operand 15105 states and 20599 transitions. Second operand 3 states. [2019-11-28 17:32:47,006 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:47,006 INFO L93 Difference]: Finished difference Result 25662 states and 34928 transitions. [2019-11-28 17:32:47,007 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:47,007 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 127 [2019-11-28 17:32:47,007 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:47,017 INFO L225 Difference]: With dead ends: 25662 [2019-11-28 17:32:47,018 INFO L226 Difference]: Without dead ends: 10614 [2019-11-28 17:32:47,031 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:47,038 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10614 states. [2019-11-28 17:32:47,273 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10614 to 8646. [2019-11-28 17:32:47,273 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8646 states. [2019-11-28 17:32:47,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8646 states to 8646 states and 11323 transitions. [2019-11-28 17:32:47,283 INFO L78 Accepts]: Start accepts. Automaton has 8646 states and 11323 transitions. Word has length 127 [2019-11-28 17:32:47,283 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:47,283 INFO L462 AbstractCegarLoop]: Abstraction has 8646 states and 11323 transitions. [2019-11-28 17:32:47,283 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:47,283 INFO L276 IsEmpty]: Start isEmpty. Operand 8646 states and 11323 transitions. [2019-11-28 17:32:47,293 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2019-11-28 17:32:47,293 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:47,293 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:47,294 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:47,294 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:47,294 INFO L82 PathProgramCache]: Analyzing trace with hash 762576065, now seen corresponding path program 1 times [2019-11-28 17:32:47,294 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:47,294 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019836139] [2019-11-28 17:32:47,294 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:47,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:47,336 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 43 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2019-11-28 17:32:47,336 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019836139] [2019-11-28 17:32:47,337 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:47,337 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:47,337 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [437006896] [2019-11-28 17:32:47,338 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:47,338 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:47,338 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:47,338 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:47,339 INFO L87 Difference]: Start difference. First operand 8646 states and 11323 transitions. Second operand 3 states. [2019-11-28 17:32:47,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:47,604 INFO L93 Difference]: Finished difference Result 14253 states and 18666 transitions. [2019-11-28 17:32:47,605 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:47,605 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 128 [2019-11-28 17:32:47,605 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:47,611 INFO L225 Difference]: With dead ends: 14253 [2019-11-28 17:32:47,612 INFO L226 Difference]: Without dead ends: 6761 [2019-11-28 17:32:47,617 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:47,622 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6761 states. [2019-11-28 17:32:47,810 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6761 to 6175. [2019-11-28 17:32:47,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6175 states. [2019-11-28 17:32:47,817 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6175 states to 6175 states and 7922 transitions. [2019-11-28 17:32:47,817 INFO L78 Accepts]: Start accepts. Automaton has 6175 states and 7922 transitions. Word has length 128 [2019-11-28 17:32:47,817 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:47,817 INFO L462 AbstractCegarLoop]: Abstraction has 6175 states and 7922 transitions. [2019-11-28 17:32:47,817 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:47,817 INFO L276 IsEmpty]: Start isEmpty. Operand 6175 states and 7922 transitions. [2019-11-28 17:32:47,822 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-11-28 17:32:47,822 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:47,823 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:47,823 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:47,823 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:47,823 INFO L82 PathProgramCache]: Analyzing trace with hash 843157933, now seen corresponding path program 1 times [2019-11-28 17:32:47,824 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:47,824 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [773625805] [2019-11-28 17:32:47,824 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:47,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:47,868 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2019-11-28 17:32:47,869 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [773625805] [2019-11-28 17:32:47,869 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:47,869 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:47,870 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [815069629] [2019-11-28 17:32:47,870 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:47,870 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:47,870 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:47,871 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:47,871 INFO L87 Difference]: Start difference. First operand 6175 states and 7922 transitions. Second operand 3 states. [2019-11-28 17:32:48,260 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:48,260 INFO L93 Difference]: Finished difference Result 11963 states and 15332 transitions. [2019-11-28 17:32:48,261 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:48,261 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 134 [2019-11-28 17:32:48,262 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:48,270 INFO L225 Difference]: With dead ends: 11963 [2019-11-28 17:32:48,271 INFO L226 Difference]: Without dead ends: 6174 [2019-11-28 17:32:48,277 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:48,284 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6174 states. [2019-11-28 17:32:48,592 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6174 to 6134. [2019-11-28 17:32:48,592 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6134 states. [2019-11-28 17:32:48,601 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6134 states to 6134 states and 7839 transitions. [2019-11-28 17:32:48,601 INFO L78 Accepts]: Start accepts. Automaton has 6134 states and 7839 transitions. Word has length 134 [2019-11-28 17:32:48,602 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:48,602 INFO L462 AbstractCegarLoop]: Abstraction has 6134 states and 7839 transitions. [2019-11-28 17:32:48,602 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:48,602 INFO L276 IsEmpty]: Start isEmpty. Operand 6134 states and 7839 transitions. [2019-11-28 17:32:48,607 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-11-28 17:32:48,608 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:48,608 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:48,608 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:48,609 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:48,609 INFO L82 PathProgramCache]: Analyzing trace with hash 713131341, now seen corresponding path program 1 times [2019-11-28 17:32:48,609 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:48,609 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1656983753] [2019-11-28 17:32:48,610 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:48,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:48,661 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2019-11-28 17:32:48,662 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1656983753] [2019-11-28 17:32:48,662 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:48,662 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:48,663 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [201830618] [2019-11-28 17:32:48,663 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:48,663 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:48,664 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:48,664 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:48,664 INFO L87 Difference]: Start difference. First operand 6134 states and 7839 transitions. Second operand 3 states. [2019-11-28 17:32:49,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:49,324 INFO L93 Difference]: Finished difference Result 11902 states and 15193 transitions. [2019-11-28 17:32:49,325 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:49,325 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 134 [2019-11-28 17:32:49,325 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:49,333 INFO L225 Difference]: With dead ends: 11902 [2019-11-28 17:32:49,333 INFO L226 Difference]: Without dead ends: 6144 [2019-11-28 17:32:49,339 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:49,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6144 states. [2019-11-28 17:32:49,695 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6144 to 6104. [2019-11-28 17:32:49,695 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6104 states. [2019-11-28 17:32:49,703 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6104 states to 6104 states and 7768 transitions. [2019-11-28 17:32:49,704 INFO L78 Accepts]: Start accepts. Automaton has 6104 states and 7768 transitions. Word has length 134 [2019-11-28 17:32:49,704 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:49,704 INFO L462 AbstractCegarLoop]: Abstraction has 6104 states and 7768 transitions. [2019-11-28 17:32:49,704 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:49,705 INFO L276 IsEmpty]: Start isEmpty. Operand 6104 states and 7768 transitions. [2019-11-28 17:32:49,710 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2019-11-28 17:32:49,710 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:49,711 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:49,711 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:49,711 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:49,711 INFO L82 PathProgramCache]: Analyzing trace with hash -57826629, now seen corresponding path program 1 times [2019-11-28 17:32:49,711 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:49,712 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [946332099] [2019-11-28 17:32:49,712 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:49,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:49,757 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 46 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2019-11-28 17:32:49,757 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [946332099] [2019-11-28 17:32:49,758 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:49,758 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:49,758 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1740077650] [2019-11-28 17:32:49,758 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:49,759 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:49,759 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:49,759 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:49,759 INFO L87 Difference]: Start difference. First operand 6104 states and 7768 transitions. Second operand 3 states. [2019-11-28 17:32:49,938 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:49,938 INFO L93 Difference]: Finished difference Result 10914 states and 13936 transitions. [2019-11-28 17:32:49,938 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:49,939 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 137 [2019-11-28 17:32:49,939 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:49,943 INFO L225 Difference]: With dead ends: 10914 [2019-11-28 17:32:49,943 INFO L226 Difference]: Without dead ends: 5174 [2019-11-28 17:32:49,947 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:49,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5174 states. [2019-11-28 17:32:50,080 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5174 to 5102. [2019-11-28 17:32:50,081 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5102 states. [2019-11-28 17:32:50,085 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5102 states to 5102 states and 6390 transitions. [2019-11-28 17:32:50,086 INFO L78 Accepts]: Start accepts. Automaton has 5102 states and 6390 transitions. Word has length 137 [2019-11-28 17:32:50,086 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:50,086 INFO L462 AbstractCegarLoop]: Abstraction has 5102 states and 6390 transitions. [2019-11-28 17:32:50,086 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:50,086 INFO L276 IsEmpty]: Start isEmpty. Operand 5102 states and 6390 transitions. [2019-11-28 17:32:50,089 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2019-11-28 17:32:50,089 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:50,089 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:50,089 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:50,090 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:50,090 INFO L82 PathProgramCache]: Analyzing trace with hash -76782736, now seen corresponding path program 1 times [2019-11-28 17:32:50,090 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:50,090 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [148299146] [2019-11-28 17:32:50,090 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:50,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:50,131 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 45 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2019-11-28 17:32:50,132 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [148299146] [2019-11-28 17:32:50,132 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:50,133 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:50,135 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1141234600] [2019-11-28 17:32:50,135 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:50,136 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:50,136 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:50,136 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:50,136 INFO L87 Difference]: Start difference. First operand 5102 states and 6390 transitions. Second operand 3 states. [2019-11-28 17:32:50,345 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:50,345 INFO L93 Difference]: Finished difference Result 9187 states and 11545 transitions. [2019-11-28 17:32:50,346 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:50,346 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 137 [2019-11-28 17:32:50,347 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:50,352 INFO L225 Difference]: With dead ends: 9187 [2019-11-28 17:32:50,352 INFO L226 Difference]: Without dead ends: 4126 [2019-11-28 17:32:50,358 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:50,362 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4126 states. [2019-11-28 17:32:50,592 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4126 to 4106. [2019-11-28 17:32:50,593 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4106 states. [2019-11-28 17:32:50,600 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4106 states to 4106 states and 5057 transitions. [2019-11-28 17:32:50,601 INFO L78 Accepts]: Start accepts. Automaton has 4106 states and 5057 transitions. Word has length 137 [2019-11-28 17:32:50,601 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:50,602 INFO L462 AbstractCegarLoop]: Abstraction has 4106 states and 5057 transitions. [2019-11-28 17:32:50,602 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:50,602 INFO L276 IsEmpty]: Start isEmpty. Operand 4106 states and 5057 transitions. [2019-11-28 17:32:50,607 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 171 [2019-11-28 17:32:50,607 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:50,608 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:50,608 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:50,608 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:50,609 INFO L82 PathProgramCache]: Analyzing trace with hash -691267920, now seen corresponding path program 1 times [2019-11-28 17:32:50,609 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:50,609 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1367922111] [2019-11-28 17:32:50,610 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:50,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:50,666 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 75 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2019-11-28 17:32:50,667 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1367922111] [2019-11-28 17:32:50,667 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:50,667 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:50,668 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [117489259] [2019-11-28 17:32:50,668 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:50,668 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:50,669 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:50,669 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:50,669 INFO L87 Difference]: Start difference. First operand 4106 states and 5057 transitions. Second operand 3 states. [2019-11-28 17:32:50,866 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:50,867 INFO L93 Difference]: Finished difference Result 7627 states and 9455 transitions. [2019-11-28 17:32:50,867 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:50,867 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 170 [2019-11-28 17:32:50,868 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:50,872 INFO L225 Difference]: With dead ends: 7627 [2019-11-28 17:32:50,872 INFO L226 Difference]: Without dead ends: 3797 [2019-11-28 17:32:50,876 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:50,878 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3797 states. [2019-11-28 17:32:51,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3797 to 3568. [2019-11-28 17:32:51,041 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3568 states. [2019-11-28 17:32:51,044 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3568 states to 3568 states and 4348 transitions. [2019-11-28 17:32:51,044 INFO L78 Accepts]: Start accepts. Automaton has 3568 states and 4348 transitions. Word has length 170 [2019-11-28 17:32:51,046 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:51,046 INFO L462 AbstractCegarLoop]: Abstraction has 3568 states and 4348 transitions. [2019-11-28 17:32:51,046 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:51,046 INFO L276 IsEmpty]: Start isEmpty. Operand 3568 states and 4348 transitions. [2019-11-28 17:32:51,048 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 178 [2019-11-28 17:32:51,048 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:51,049 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:51,049 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:51,049 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:51,049 INFO L82 PathProgramCache]: Analyzing trace with hash 307077909, now seen corresponding path program 1 times [2019-11-28 17:32:51,050 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:51,050 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1066809296] [2019-11-28 17:32:51,050 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:51,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:51,089 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 82 proven. 0 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2019-11-28 17:32:51,089 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1066809296] [2019-11-28 17:32:51,089 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:51,089 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:51,090 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1101145729] [2019-11-28 17:32:51,090 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:51,090 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:51,091 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:51,091 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:51,091 INFO L87 Difference]: Start difference. First operand 3568 states and 4348 transitions. Second operand 3 states. [2019-11-28 17:32:51,270 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:51,270 INFO L93 Difference]: Finished difference Result 8940 states and 10936 transitions. [2019-11-28 17:32:51,271 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:51,271 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 177 [2019-11-28 17:32:51,271 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:51,276 INFO L225 Difference]: With dead ends: 8940 [2019-11-28 17:32:51,276 INFO L226 Difference]: Without dead ends: 5648 [2019-11-28 17:32:51,279 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:51,282 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5648 states. [2019-11-28 17:32:51,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5648 to 5422. [2019-11-28 17:32:51,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5422 states. [2019-11-28 17:32:51,437 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5422 states to 5422 states and 6526 transitions. [2019-11-28 17:32:51,437 INFO L78 Accepts]: Start accepts. Automaton has 5422 states and 6526 transitions. Word has length 177 [2019-11-28 17:32:51,438 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:51,438 INFO L462 AbstractCegarLoop]: Abstraction has 5422 states and 6526 transitions. [2019-11-28 17:32:51,438 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:51,438 INFO L276 IsEmpty]: Start isEmpty. Operand 5422 states and 6526 transitions. [2019-11-28 17:32:51,441 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 181 [2019-11-28 17:32:51,441 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:51,441 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:51,441 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:51,442 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:51,442 INFO L82 PathProgramCache]: Analyzing trace with hash -2095538940, now seen corresponding path program 1 times [2019-11-28 17:32:51,442 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:51,442 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2126852695] [2019-11-28 17:32:51,442 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:51,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:51,480 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 79 proven. 0 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2019-11-28 17:32:51,480 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2126852695] [2019-11-28 17:32:51,480 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:51,481 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:51,481 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [677965665] [2019-11-28 17:32:51,481 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:51,481 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:51,481 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:51,482 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:51,482 INFO L87 Difference]: Start difference. First operand 5422 states and 6526 transitions. Second operand 3 states. [2019-11-28 17:32:51,621 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:51,621 INFO L93 Difference]: Finished difference Result 8854 states and 10720 transitions. [2019-11-28 17:32:51,621 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:51,621 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 180 [2019-11-28 17:32:51,622 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:51,624 INFO L225 Difference]: With dead ends: 8854 [2019-11-28 17:32:51,625 INFO L226 Difference]: Without dead ends: 3708 [2019-11-28 17:32:51,627 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:51,630 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3708 states. [2019-11-28 17:32:51,923 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3708 to 3100. [2019-11-28 17:32:51,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3100 states. [2019-11-28 17:32:51,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3100 states to 3100 states and 3693 transitions. [2019-11-28 17:32:51,926 INFO L78 Accepts]: Start accepts. Automaton has 3100 states and 3693 transitions. Word has length 180 [2019-11-28 17:32:51,927 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:51,927 INFO L462 AbstractCegarLoop]: Abstraction has 3100 states and 3693 transitions. [2019-11-28 17:32:51,927 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:51,927 INFO L276 IsEmpty]: Start isEmpty. Operand 3100 states and 3693 transitions. [2019-11-28 17:32:51,929 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 181 [2019-11-28 17:32:51,929 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:51,930 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:51,930 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:51,930 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:51,930 INFO L82 PathProgramCache]: Analyzing trace with hash -1037700862, now seen corresponding path program 1 times [2019-11-28 17:32:51,930 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:51,930 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [602103544] [2019-11-28 17:32:51,931 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:51,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:51,995 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 91 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-11-28 17:32:51,996 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [602103544] [2019-11-28 17:32:51,996 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:51,996 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 17:32:51,996 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [954543787] [2019-11-28 17:32:51,997 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 17:32:51,997 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:51,997 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 17:32:51,997 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 17:32:51,997 INFO L87 Difference]: Start difference. First operand 3100 states and 3693 transitions. Second operand 4 states. [2019-11-28 17:32:52,153 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:52,153 INFO L93 Difference]: Finished difference Result 4701 states and 5585 transitions. [2019-11-28 17:32:52,154 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 17:32:52,154 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 180 [2019-11-28 17:32:52,154 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:52,156 INFO L225 Difference]: With dead ends: 4701 [2019-11-28 17:32:52,156 INFO L226 Difference]: Without dead ends: 1877 [2019-11-28 17:32:52,161 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:32:52,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1877 states. [2019-11-28 17:32:52,257 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1877 to 1590. [2019-11-28 17:32:52,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1590 states. [2019-11-28 17:32:52,260 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1590 states to 1590 states and 1853 transitions. [2019-11-28 17:32:52,260 INFO L78 Accepts]: Start accepts. Automaton has 1590 states and 1853 transitions. Word has length 180 [2019-11-28 17:32:52,260 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:52,261 INFO L462 AbstractCegarLoop]: Abstraction has 1590 states and 1853 transitions. [2019-11-28 17:32:52,261 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 17:32:52,261 INFO L276 IsEmpty]: Start isEmpty. Operand 1590 states and 1853 transitions. [2019-11-28 17:32:52,262 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 185 [2019-11-28 17:32:52,262 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:52,263 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:52,263 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:52,263 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:52,263 INFO L82 PathProgramCache]: Analyzing trace with hash 1351947795, now seen corresponding path program 1 times [2019-11-28 17:32:52,263 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:52,263 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1137416342] [2019-11-28 17:32:52,264 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:52,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:52,330 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 100 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-28 17:32:52,330 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1137416342] [2019-11-28 17:32:52,331 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:52,331 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:52,331 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [431235719] [2019-11-28 17:32:52,331 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:52,331 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:52,332 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:52,332 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:52,332 INFO L87 Difference]: Start difference. First operand 1590 states and 1853 transitions. Second operand 3 states. [2019-11-28 17:32:52,477 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:52,477 INFO L93 Difference]: Finished difference Result 4058 states and 4759 transitions. [2019-11-28 17:32:52,478 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:52,478 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 184 [2019-11-28 17:32:52,478 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:52,480 INFO L225 Difference]: With dead ends: 4058 [2019-11-28 17:32:52,480 INFO L226 Difference]: Without dead ends: 2438 [2019-11-28 17:32:52,481 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:52,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2438 states. [2019-11-28 17:32:52,557 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2438 to 2426. [2019-11-28 17:32:52,558 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2426 states. [2019-11-28 17:32:52,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2426 states to 2426 states and 2829 transitions. [2019-11-28 17:32:52,560 INFO L78 Accepts]: Start accepts. Automaton has 2426 states and 2829 transitions. Word has length 184 [2019-11-28 17:32:52,560 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:52,560 INFO L462 AbstractCegarLoop]: Abstraction has 2426 states and 2829 transitions. [2019-11-28 17:32:52,560 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:52,560 INFO L276 IsEmpty]: Start isEmpty. Operand 2426 states and 2829 transitions. [2019-11-28 17:32:52,561 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 185 [2019-11-28 17:32:52,561 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:52,562 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:52,562 INFO L410 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:52,562 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:52,562 INFO L82 PathProgramCache]: Analyzing trace with hash 1047126543, now seen corresponding path program 1 times [2019-11-28 17:32:52,562 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:52,562 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1621511031] [2019-11-28 17:32:52,562 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:52,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:52,609 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 93 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-11-28 17:32:52,609 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1621511031] [2019-11-28 17:32:52,610 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:52,610 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:52,610 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2144085183] [2019-11-28 17:32:52,610 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:52,611 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:52,611 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:52,611 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:52,611 INFO L87 Difference]: Start difference. First operand 2426 states and 2829 transitions. Second operand 3 states. [2019-11-28 17:32:52,691 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:52,691 INFO L93 Difference]: Finished difference Result 3380 states and 3910 transitions. [2019-11-28 17:32:52,692 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:52,692 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 184 [2019-11-28 17:32:52,692 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:52,693 INFO L225 Difference]: With dead ends: 3380 [2019-11-28 17:32:52,693 INFO L226 Difference]: Without dead ends: 1220 [2019-11-28 17:32:52,694 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:52,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1220 states. [2019-11-28 17:32:52,732 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1220 to 1198. [2019-11-28 17:32:52,732 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1198 states. [2019-11-28 17:32:52,733 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1198 states to 1198 states and 1326 transitions. [2019-11-28 17:32:52,733 INFO L78 Accepts]: Start accepts. Automaton has 1198 states and 1326 transitions. Word has length 184 [2019-11-28 17:32:52,733 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:52,733 INFO L462 AbstractCegarLoop]: Abstraction has 1198 states and 1326 transitions. [2019-11-28 17:32:52,733 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:52,734 INFO L276 IsEmpty]: Start isEmpty. Operand 1198 states and 1326 transitions. [2019-11-28 17:32:52,734 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 186 [2019-11-28 17:32:52,734 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:52,735 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:52,735 INFO L410 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:52,735 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:52,735 INFO L82 PathProgramCache]: Analyzing trace with hash -1330592792, now seen corresponding path program 1 times [2019-11-28 17:32:52,735 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:52,735 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [537076949] [2019-11-28 17:32:52,735 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:52,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:52,787 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 107 trivial. 0 not checked. [2019-11-28 17:32:52,787 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [537076949] [2019-11-28 17:32:52,787 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:52,787 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:52,787 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [613902005] [2019-11-28 17:32:52,788 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:52,788 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:52,788 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:52,788 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:52,789 INFO L87 Difference]: Start difference. First operand 1198 states and 1326 transitions. Second operand 3 states. [2019-11-28 17:32:52,875 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:52,876 INFO L93 Difference]: Finished difference Result 1202 states and 1331 transitions. [2019-11-28 17:32:52,876 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:52,876 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 185 [2019-11-28 17:32:52,877 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:52,878 INFO L225 Difference]: With dead ends: 1202 [2019-11-28 17:32:52,878 INFO L226 Difference]: Without dead ends: 1200 [2019-11-28 17:32:52,878 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:52,880 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1200 states. [2019-11-28 17:32:52,961 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1200 to 1200. [2019-11-28 17:32:52,961 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1200 states. [2019-11-28 17:32:52,962 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1200 states to 1200 states and 1328 transitions. [2019-11-28 17:32:52,963 INFO L78 Accepts]: Start accepts. Automaton has 1200 states and 1328 transitions. Word has length 185 [2019-11-28 17:32:52,963 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:52,963 INFO L462 AbstractCegarLoop]: Abstraction has 1200 states and 1328 transitions. [2019-11-28 17:32:52,963 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:52,963 INFO L276 IsEmpty]: Start isEmpty. Operand 1200 states and 1328 transitions. [2019-11-28 17:32:52,965 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 186 [2019-11-28 17:32:52,965 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:52,965 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:52,965 INFO L410 AbstractCegarLoop]: === Iteration 38 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:52,965 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:52,966 INFO L82 PathProgramCache]: Analyzing trace with hash -1330591190, now seen corresponding path program 1 times [2019-11-28 17:32:52,966 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:52,966 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [40536517] [2019-11-28 17:32:52,966 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:52,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:53,241 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 81 proven. 15 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2019-11-28 17:32:53,241 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [40536517] [2019-11-28 17:32:53,242 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [979798279] [2019-11-28 17:32:53,242 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-28 17:32:53,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:53,380 INFO L264 TraceCheckSpWp]: Trace formula consists of 499 conjuncts, 19 conjunts are in the unsatisfiable core [2019-11-28 17:32:53,407 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-11-28 17:32:53,548 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 81 proven. 15 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2019-11-28 17:32:53,549 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-11-28 17:32:53,549 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 10 [2019-11-28 17:32:53,550 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1773806456] [2019-11-28 17:32:53,550 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-11-28 17:32:53,551 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:53,551 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-11-28 17:32:53,551 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2019-11-28 17:32:53,551 INFO L87 Difference]: Start difference. First operand 1200 states and 1328 transitions. Second operand 10 states. [2019-11-28 17:32:54,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:54,116 INFO L93 Difference]: Finished difference Result 2336 states and 2602 transitions. [2019-11-28 17:32:54,117 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-11-28 17:32:54,117 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 185 [2019-11-28 17:32:54,118 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:54,123 INFO L225 Difference]: With dead ends: 2336 [2019-11-28 17:32:54,124 INFO L226 Difference]: Without dead ends: 1732 [2019-11-28 17:32:54,125 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 206 GetRequests, 188 SyntacticMatches, 2 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=64, Invalid=242, Unknown=0, NotChecked=0, Total=306 [2019-11-28 17:32:54,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1732 states. [2019-11-28 17:32:54,296 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1732 to 1546. [2019-11-28 17:32:54,296 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1546 states. [2019-11-28 17:32:54,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1546 states to 1546 states and 1714 transitions. [2019-11-28 17:32:54,300 INFO L78 Accepts]: Start accepts. Automaton has 1546 states and 1714 transitions. Word has length 185 [2019-11-28 17:32:54,301 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:54,301 INFO L462 AbstractCegarLoop]: Abstraction has 1546 states and 1714 transitions. [2019-11-28 17:32:54,301 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-11-28 17:32:54,302 INFO L276 IsEmpty]: Start isEmpty. Operand 1546 states and 1714 transitions. [2019-11-28 17:32:54,306 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 187 [2019-11-28 17:32:54,306 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:54,308 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:54,514 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-11-28 17:32:54,514 INFO L410 AbstractCegarLoop]: === Iteration 39 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:54,514 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:54,515 INFO L82 PathProgramCache]: Analyzing trace with hash 1701344696, now seen corresponding path program 1 times [2019-11-28 17:32:54,515 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:54,516 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1574256717] [2019-11-28 17:32:54,516 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:54,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 17:32:54,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 17:32:54,687 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-28 17:32:54,687 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-28 17:32:54,904 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 05:32:54 BoogieIcfgContainer [2019-11-28 17:32:54,904 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-28 17:32:54,904 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-28 17:32:54,904 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-28 17:32:54,905 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-28 17:32:54,905 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 05:32:28" (3/4) ... [2019-11-28 17:32:54,908 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-28 17:32:55,167 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2019-11-28 17:32:55,168 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-28 17:32:55,171 INFO L168 Benchmark]: Toolchain (without parser) took 27561.62 ms. Allocated memory was 1.0 GB in the beginning and 3.6 GB in the end (delta: 2.6 GB). Free memory was 956.3 MB in the beginning and 2.0 GB in the end (delta: -1.0 GB). Peak memory consumption was 1.6 GB. Max. memory is 11.5 GB. [2019-11-28 17:32:55,171 INFO L168 Benchmark]: CDTParser took 0.36 ms. Allocated memory is still 1.0 GB. Free memory is still 987.2 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 17:32:55,172 INFO L168 Benchmark]: CACSL2BoogieTranslator took 500.96 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 145.8 MB). Free memory was 956.3 MB in the beginning and 1.1 GB in the end (delta: -179.5 MB). Peak memory consumption was 25.9 MB. Max. memory is 11.5 GB. [2019-11-28 17:32:55,172 INFO L168 Benchmark]: Boogie Procedure Inliner took 51.05 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 17:32:55,173 INFO L168 Benchmark]: Boogie Preprocessor took 38.62 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.6 MB). Peak memory consumption was 6.6 MB. Max. memory is 11.5 GB. [2019-11-28 17:32:55,173 INFO L168 Benchmark]: RCFGBuilder took 758.44 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 50.3 MB). Peak memory consumption was 50.3 MB. Max. memory is 11.5 GB. [2019-11-28 17:32:55,173 INFO L168 Benchmark]: TraceAbstraction took 25942.60 ms. Allocated memory was 1.2 GB in the beginning and 3.6 GB in the end (delta: 2.5 GB). Free memory was 1.1 GB in the beginning and 2.0 GB in the end (delta: -924.6 MB). Peak memory consumption was 1.5 GB. Max. memory is 11.5 GB. [2019-11-28 17:32:55,174 INFO L168 Benchmark]: Witness Printer took 263.31 ms. Allocated memory is still 3.6 GB. Free memory was 2.0 GB in the beginning and 2.0 GB in the end (delta: 88 B). Peak memory consumption was 88 B. Max. memory is 11.5 GB. [2019-11-28 17:32:55,175 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.36 ms. Allocated memory is still 1.0 GB. Free memory is still 987.2 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 500.96 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 145.8 MB). Free memory was 956.3 MB in the beginning and 1.1 GB in the end (delta: -179.5 MB). Peak memory consumption was 25.9 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 51.05 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 38.62 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.6 MB). Peak memory consumption was 6.6 MB. Max. memory is 11.5 GB. * RCFGBuilder took 758.44 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 50.3 MB). Peak memory consumption was 50.3 MB. Max. memory is 11.5 GB. * TraceAbstraction took 25942.60 ms. Allocated memory was 1.2 GB in the beginning and 3.6 GB in the end (delta: 2.5 GB). Free memory was 1.1 GB in the beginning and 2.0 GB in the end (delta: -924.6 MB). Peak memory consumption was 1.5 GB. Max. memory is 11.5 GB. * Witness Printer took 263.31 ms. Allocated memory is still 3.6 GB. Free memory was 2.0 GB in the beginning and 2.0 GB in the end (delta: 88 B). Peak memory consumption was 88 B. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 13]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L18] int c ; [L19] int c_t ; [L20] int c_req_up ; [L21] int p_in ; [L22] int p_out ; [L23] int wl_st ; [L24] int c1_st ; [L25] int c2_st ; [L26] int wb_st ; [L27] int r_st ; [L28] int wl_i ; [L29] int c1_i ; [L30] int c2_i ; [L31] int wb_i ; [L32] int r_i ; [L33] int wl_pc ; [L34] int c1_pc ; [L35] int c2_pc ; [L36] int wb_pc ; [L37] int e_e ; [L38] int e_f ; [L39] int e_g ; [L40] int e_c ; [L41] int e_p_in ; [L42] int e_wl ; [L48] int d ; [L49] int data ; [L50] int processed ; [L51] static int t_b ; VAL [c=0, c1_i=0, c1_pc=0, c1_st=0, c2_i=0, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=0, e_e=0, e_f=0, e_g=0, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=0, wb_pc=0, wb_st=0, wl_i=0, wl_pc=0, wl_st=0] [L691] int __retres1 ; [L695] e_wl = 2 [L696] e_c = e_wl [L697] e_g = e_c [L698] e_f = e_g [L699] e_e = e_f [L700] wl_pc = 0 [L701] c1_pc = 0 [L702] c2_pc = 0 [L703] wb_pc = 0 [L704] wb_i = 1 [L705] c2_i = wb_i [L706] c1_i = c2_i [L707] wl_i = c1_i [L708] r_i = 0 [L709] c_req_up = 0 [L710] d = 0 [L711] c = 0 [L402] int kernel_st ; [L405] kernel_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L406] COND FALSE !((int )c_req_up == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L417] COND TRUE (int )wl_i == 1 [L418] wl_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L422] COND TRUE (int )c1_i == 1 [L423] c1_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L427] COND TRUE (int )c2_i == 1 [L428] c2_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L432] COND TRUE (int )wb_i == 1 [L433] wb_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L437] COND FALSE !((int )r_i == 1) [L440] r_st = 2 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L442] COND FALSE !((int )e_f == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L447] COND FALSE !((int )e_g == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L452] COND FALSE !((int )e_e == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L457] COND FALSE !((int )e_c == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L462] COND FALSE !((int )e_wl == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L467] COND FALSE !((int )wl_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L475] COND FALSE !((int )wl_pc == 2) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L485] COND FALSE !((int )c1_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L494] COND FALSE !((int )c2_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L503] COND FALSE !((int )wb_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L512] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L517] COND FALSE !((int )e_e == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L522] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L527] COND FALSE !((int )e_g == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L532] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L537] COND FALSE !((int )e_wl == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L543] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L546] kernel_st = 1 [L288] int tmp ; [L289] int tmp___0 ; [L290] int tmp___1 ; [L291] int tmp___2 ; [L292] int tmp___3 ; VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L296] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L298] COND TRUE (int )wl_st == 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L319] COND TRUE (int )wl_st == 0 [L321] tmp = __VERIFIER_nondet_int() [L323] COND TRUE \read(tmp) [L325] wl_st = 1 [L53] int t ; VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L56] COND TRUE (int )wl_pc == 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L70] wl_st = 2 [L71] wl_pc = 1 [L72] e_wl = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L334] COND TRUE (int )c1_st == 0 [L336] tmp___0 = __VERIFIER_nondet_int() [L338] COND TRUE \read(tmp___0) [L340] c1_st = 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L139] COND TRUE (int )c1_pc == 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L150] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L152] c1_st = 2 [L153] c1_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L349] COND TRUE (int )c2_st == 0 [L351] tmp___1 = __VERIFIER_nondet_int() [L353] COND TRUE \read(tmp___1) [L355] c2_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L184] COND TRUE (int )c2_pc == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L195] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L197] c2_st = 2 [L198] c2_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L364] COND TRUE (int )wb_st == 0 [L366] tmp___2 = __VERIFIER_nondet_int() [L368] COND TRUE \read(tmp___2) [L370] wb_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L229] COND TRUE (int )wb_pc == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L240] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L242] wb_st = 2 [L243] wb_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L379] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L296] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L298] COND FALSE !((int )wl_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L301] COND FALSE !((int )c1_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L304] COND FALSE !((int )c2_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L307] COND FALSE !((int )wb_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L310] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L549] kernel_st = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L550] COND FALSE !((int )c_req_up == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L561] kernel_st = 3 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L562] COND FALSE !((int )e_f == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L567] COND FALSE !((int )e_g == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L572] COND FALSE !((int )e_e == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L577] COND FALSE !((int )e_c == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L582] COND TRUE (int )e_wl == 0 [L583] e_wl = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L587] COND TRUE (int )wl_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L588] COND TRUE (int )e_wl == 1 [L589] wl_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L605] COND TRUE (int )c1_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L606] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L614] COND TRUE (int )c2_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L615] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L623] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L624] COND FALSE !((int )e_g == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L632] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L637] COND FALSE !((int )e_e == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L642] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L647] COND FALSE !((int )e_g == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L652] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L657] COND TRUE (int )e_wl == 1 [L658] e_wl = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L662] COND TRUE (int )wl_st == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L543] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L546] kernel_st = 1 [L288] int tmp ; [L289] int tmp___0 ; [L290] int tmp___1 ; [L291] int tmp___2 ; [L292] int tmp___3 ; VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L296] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L298] COND TRUE (int )wl_st == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L319] COND TRUE (int )wl_st == 0 [L321] tmp = __VERIFIER_nondet_int() [L323] COND TRUE \read(tmp) [L325] wl_st = 1 [L53] int t ; VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L56] COND FALSE !((int )wl_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L59] COND FALSE !((int )wl_pc == 2) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L62] COND TRUE (int )wl_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L77] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L79] t = d [L80] data = d [L81] processed = 0 [L82] e_f = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L83] COND TRUE (int )c1_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L84] COND TRUE (int )e_f == 1 [L85] c1_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L92] COND TRUE (int )c2_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L93] COND TRUE (int )e_f == 1 [L94] c2_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L101] e_f = 2 [L102] wl_st = 2 [L103] wl_pc = 2 [L104] t_b = t VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L334] COND TRUE (int )c1_st == 0 [L336] tmp___0 = __VERIFIER_nondet_int() [L338] COND TRUE \read(tmp___0) [L340] c1_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L139] COND FALSE !((int )c1_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L142] COND TRUE (int )c1_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L157] COND TRUE ! processed [L158] data += 1 [L159] e_g = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L160] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L161] COND TRUE (int )e_g == 1 [L162] wb_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L169] e_g = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L150] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L152] c1_st = 2 [L153] c1_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L349] COND TRUE (int )c2_st == 0 [L351] tmp___1 = __VERIFIER_nondet_int() [L353] COND TRUE \read(tmp___1) [L355] c2_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L184] COND FALSE !((int )c2_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L187] COND TRUE (int )c2_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L202] COND TRUE ! processed [L203] data += 1 [L204] e_g = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L205] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L206] COND TRUE (int )e_g == 1 [L207] wb_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L214] e_g = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L195] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L197] c2_st = 2 [L198] c2_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L364] COND TRUE (int )wb_st == 0 [L366] tmp___2 = __VERIFIER_nondet_int() [L368] COND TRUE \read(tmp___2) [L370] wb_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L229] COND FALSE !((int )wb_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L232] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L247] c_t = data [L248] c_req_up = 1 [L249] processed = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L240] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L242] wb_st = 2 [L243] wb_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L379] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L296] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L298] COND FALSE !((int )wl_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L301] COND FALSE !((int )c1_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L304] COND FALSE !((int )c2_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L307] COND FALSE !((int )wb_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L310] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L549] kernel_st = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L550] COND TRUE (int )c_req_up == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L551] COND TRUE c != c_t [L552] c = c_t [L553] e_c = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L557] c_req_up = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L561] kernel_st = 3 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L562] COND FALSE !((int )e_f == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L567] COND FALSE !((int )e_g == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L572] COND FALSE !((int )e_e == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L577] COND TRUE (int )e_c == 0 [L578] e_c = 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L582] COND FALSE !((int )e_wl == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L587] COND FALSE !((int )wl_pc == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L595] COND TRUE (int )wl_pc == 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L596] COND FALSE !((int )e_e == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L605] COND TRUE (int )c1_pc == 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L606] COND FALSE !((int )e_f == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L614] COND TRUE (int )c2_pc == 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L615] COND FALSE !((int )e_f == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L623] COND TRUE (int )wb_pc == 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L624] COND FALSE !((int )e_g == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L632] COND TRUE (int )e_c == 1 [L633] r_st = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L637] COND FALSE !((int )e_e == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L642] COND FALSE !((int )e_f == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L647] COND FALSE !((int )e_g == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L652] COND TRUE (int )e_c == 1 [L653] e_c = 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L657] COND FALSE !((int )e_wl == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L662] COND FALSE !((int )wl_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L665] COND FALSE !((int )c1_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L668] COND FALSE !((int )c2_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L671] COND FALSE !((int )wb_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L674] COND TRUE (int )r_st == 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L543] COND TRUE 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L546] kernel_st = 1 [L288] int tmp ; [L289] int tmp___0 ; [L290] int tmp___1 ; [L291] int tmp___2 ; [L292] int tmp___3 ; VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L296] COND TRUE 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L298] COND FALSE !((int )wl_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L301] COND FALSE !((int )c1_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L304] COND FALSE !((int )c2_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L307] COND FALSE !((int )wb_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L310] COND TRUE (int )r_st == 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L319] COND FALSE !((int )wl_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L334] COND FALSE !((int )c1_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L349] COND FALSE !((int )c2_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L364] COND FALSE !((int )wb_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L379] COND TRUE (int )r_st == 0 [L381] tmp___3 = __VERIFIER_nondet_int() [L383] COND TRUE \read(tmp___3) [L385] r_st = 1 [L261] d = c [L262] e_e = 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L263] COND FALSE !((int )wl_pc == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L271] COND TRUE (int )wl_pc == 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L272] COND TRUE (int )e_e == 1 [L273] wl_st = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L281] e_e = 2 [L282] r_st = 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L296] COND TRUE 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L298] COND TRUE (int )wl_st == 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L319] COND TRUE (int )wl_st == 0 [L321] tmp = __VERIFIER_nondet_int() [L323] COND TRUE \read(tmp) [L325] wl_st = 1 [L53] int t ; VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L56] COND FALSE !((int )wl_pc == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L59] COND TRUE (int )wl_pc == 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L108] t = t_b VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L109] COND FALSE !(d == t + 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L112] COND TRUE d == t + 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L120] COND FALSE !(d == t + 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L13] __VERIFIER_error() VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 129 locations, 2 error locations. Result: UNSAFE, OverallTime: 25.6s, OverallIterations: 39, TraceHistogramMax: 6, AutomataDifference: 12.3s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 8305 SDtfs, 6676 SDslu, 6853 SDs, 0 SdLazy, 904 SolverSat, 221 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.1s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 337 GetRequests, 266 SyntacticMatches, 4 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=16823occurred in iteration=19, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 9.8s AutomataMinimizationTime, 38 MinimizatonAttempts, 9357 StatesRemovedByMinimization, 31 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 0.5s SatisfiabilityAnalysisTime, 1.3s InterpolantComputationTime, 3918 NumberOfCodeBlocks, 3918 NumberOfCodeBlocksAsserted, 40 NumberOfCheckSat, 3693 ConstructedInterpolants, 0 QuantifiedInterpolants, 995189 SizeOfPredicates, 8 NumberOfNonLiveVariables, 499 ConjunctsInSsa, 19 ConjunctsInUnsatCore, 39 InterpolantComputations, 37 PerfectInterpolantSequences, 1373/1403 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...