./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/systemc/toy2.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx12G -Xms1G -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/systemc/toy2.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c8989412e094655bcf4508d76eb9764ed06d0b34 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-11-28 17:32:29,089 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-28 17:32:29,093 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-28 17:32:29,111 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-28 17:32:29,112 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-28 17:32:29,114 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-28 17:32:29,116 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-28 17:32:29,126 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-28 17:32:29,132 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-28 17:32:29,135 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-28 17:32:29,137 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-28 17:32:29,139 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-28 17:32:29,139 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-28 17:32:29,143 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-28 17:32:29,144 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-28 17:32:29,146 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-28 17:32:29,150 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-28 17:32:29,151 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-28 17:32:29,154 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-28 17:32:29,157 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-28 17:32:29,159 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-28 17:32:29,160 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-28 17:32:29,161 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-28 17:32:29,162 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-28 17:32:29,164 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-28 17:32:29,165 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-28 17:32:29,165 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-28 17:32:29,166 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-28 17:32:29,167 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-28 17:32:29,168 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-28 17:32:29,168 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-28 17:32:29,169 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-28 17:32:29,170 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-28 17:32:29,170 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-28 17:32:29,172 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-28 17:32:29,172 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-28 17:32:29,173 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-28 17:32:29,173 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-28 17:32:29,173 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-28 17:32:29,174 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-28 17:32:29,175 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-28 17:32:29,177 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-28 17:32:29,203 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-28 17:32:29,203 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-28 17:32:29,205 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-28 17:32:29,205 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-28 17:32:29,205 INFO L138 SettingsManager]: * Use SBE=true [2019-11-28 17:32:29,206 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-28 17:32:29,206 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-28 17:32:29,206 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-28 17:32:29,207 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-28 17:32:29,207 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-28 17:32:29,207 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-28 17:32:29,207 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-28 17:32:29,208 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-28 17:32:29,208 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-28 17:32:29,208 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-28 17:32:29,208 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-28 17:32:29,209 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-28 17:32:29,209 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-28 17:32:29,209 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-28 17:32:29,210 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-28 17:32:29,210 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-28 17:32:29,210 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 17:32:29,211 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-28 17:32:29,211 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-28 17:32:29,211 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-28 17:32:29,211 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-28 17:32:29,212 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-28 17:32:29,212 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-28 17:32:29,212 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-11-28 17:32:29,213 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c8989412e094655bcf4508d76eb9764ed06d0b34 [2019-11-28 17:32:29,515 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-28 17:32:29,539 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-28 17:32:29,543 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-28 17:32:29,544 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-28 17:32:29,546 INFO L275 PluginConnector]: CDTParser initialized [2019-11-28 17:32:29,547 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/toy2.cil.c [2019-11-28 17:32:29,624 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/afecdfb4a/b18e709e244b446f893ddfa553ed6c17/FLAG1fca23601 [2019-11-28 17:32:30,194 INFO L306 CDTParser]: Found 1 translation units. [2019-11-28 17:32:30,198 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/toy2.cil.c [2019-11-28 17:32:30,223 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/afecdfb4a/b18e709e244b446f893ddfa553ed6c17/FLAG1fca23601 [2019-11-28 17:32:30,497 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/afecdfb4a/b18e709e244b446f893ddfa553ed6c17 [2019-11-28 17:32:30,501 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-28 17:32:30,503 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-28 17:32:30,504 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-28 17:32:30,504 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-28 17:32:30,508 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-28 17:32:30,509 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 05:32:30" (1/1) ... [2019-11-28 17:32:30,512 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@dc4abe4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:30, skipping insertion in model container [2019-11-28 17:32:30,513 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 05:32:30" (1/1) ... [2019-11-28 17:32:30,521 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-11-28 17:32:30,573 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-11-28 17:32:30,846 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 17:32:30,852 INFO L203 MainTranslator]: Completed pre-run [2019-11-28 17:32:30,969 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 17:32:30,985 INFO L208 MainTranslator]: Completed translation [2019-11-28 17:32:30,985 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:30 WrapperNode [2019-11-28 17:32:30,986 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-28 17:32:30,986 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-28 17:32:30,986 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-28 17:32:30,986 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-28 17:32:30,993 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:30" (1/1) ... [2019-11-28 17:32:31,001 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:30" (1/1) ... [2019-11-28 17:32:31,036 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-28 17:32:31,036 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-28 17:32:31,037 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-28 17:32:31,037 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-28 17:32:31,046 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:30" (1/1) ... [2019-11-28 17:32:31,046 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:30" (1/1) ... [2019-11-28 17:32:31,049 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:30" (1/1) ... [2019-11-28 17:32:31,049 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:30" (1/1) ... [2019-11-28 17:32:31,056 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:30" (1/1) ... [2019-11-28 17:32:31,066 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:30" (1/1) ... [2019-11-28 17:32:31,070 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:30" (1/1) ... [2019-11-28 17:32:31,074 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-28 17:32:31,075 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-28 17:32:31,075 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-28 17:32:31,075 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-28 17:32:31,077 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:30" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 17:32:31,151 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-28 17:32:31,152 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-28 17:32:31,865 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-28 17:32:31,865 INFO L287 CfgBuilder]: Removed 26 assume(true) statements. [2019-11-28 17:32:31,867 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 05:32:31 BoogieIcfgContainer [2019-11-28 17:32:31,867 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-28 17:32:31,869 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-28 17:32:31,869 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-28 17:32:31,872 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-28 17:32:31,873 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 05:32:30" (1/3) ... [2019-11-28 17:32:31,874 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@524b836 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 05:32:31, skipping insertion in model container [2019-11-28 17:32:31,874 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:30" (2/3) ... [2019-11-28 17:32:31,875 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@524b836 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 05:32:31, skipping insertion in model container [2019-11-28 17:32:31,875 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 05:32:31" (3/3) ... [2019-11-28 17:32:31,877 INFO L109 eAbstractionObserver]: Analyzing ICFG toy2.cil.c [2019-11-28 17:32:31,888 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-28 17:32:31,896 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-11-28 17:32:31,911 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-11-28 17:32:31,940 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-28 17:32:31,941 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-28 17:32:31,941 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-28 17:32:31,941 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-28 17:32:31,942 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-28 17:32:31,942 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-28 17:32:31,943 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-28 17:32:31,943 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-28 17:32:31,965 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states. [2019-11-28 17:32:31,975 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-11-28 17:32:31,976 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:31,977 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:31,977 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:31,984 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:31,985 INFO L82 PathProgramCache]: Analyzing trace with hash 1633671955, now seen corresponding path program 1 times [2019-11-28 17:32:31,994 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:31,995 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1518975161] [2019-11-28 17:32:31,995 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:32,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:32,172 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:32,173 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1518975161] [2019-11-28 17:32:32,174 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:32,174 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:32,176 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [334603812] [2019-11-28 17:32:32,181 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:32,182 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:32,196 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:32,197 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:32,199 INFO L87 Difference]: Start difference. First operand 125 states. Second operand 3 states. [2019-11-28 17:32:32,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:32,251 INFO L93 Difference]: Finished difference Result 242 states and 449 transitions. [2019-11-28 17:32:32,252 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:32,254 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 35 [2019-11-28 17:32:32,254 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:32,267 INFO L225 Difference]: With dead ends: 242 [2019-11-28 17:32:32,267 INFO L226 Difference]: Without dead ends: 121 [2019-11-28 17:32:32,271 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:32,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121 states. [2019-11-28 17:32:32,317 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121 to 121. [2019-11-28 17:32:32,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 121 states. [2019-11-28 17:32:32,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121 states to 121 states and 213 transitions. [2019-11-28 17:32:32,323 INFO L78 Accepts]: Start accepts. Automaton has 121 states and 213 transitions. Word has length 35 [2019-11-28 17:32:32,323 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:32,324 INFO L462 AbstractCegarLoop]: Abstraction has 121 states and 213 transitions. [2019-11-28 17:32:32,324 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:32,324 INFO L276 IsEmpty]: Start isEmpty. Operand 121 states and 213 transitions. [2019-11-28 17:32:32,326 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-11-28 17:32:32,326 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:32,326 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:32,327 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:32,327 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:32,327 INFO L82 PathProgramCache]: Analyzing trace with hash 1611039701, now seen corresponding path program 1 times [2019-11-28 17:32:32,328 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:32,328 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [690144066] [2019-11-28 17:32:32,328 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:32,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:32,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:32,400 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [690144066] [2019-11-28 17:32:32,400 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:32,401 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:32,401 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1177578216] [2019-11-28 17:32:32,403 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:32,403 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:32,404 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:32,404 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:32,404 INFO L87 Difference]: Start difference. First operand 121 states and 213 transitions. Second operand 3 states. [2019-11-28 17:32:32,430 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:32,431 INFO L93 Difference]: Finished difference Result 232 states and 410 transitions. [2019-11-28 17:32:32,432 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:32,432 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 35 [2019-11-28 17:32:32,432 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:32,434 INFO L225 Difference]: With dead ends: 232 [2019-11-28 17:32:32,434 INFO L226 Difference]: Without dead ends: 121 [2019-11-28 17:32:32,436 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:32,437 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121 states. [2019-11-28 17:32:32,450 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121 to 121. [2019-11-28 17:32:32,451 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 121 states. [2019-11-28 17:32:32,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121 states to 121 states and 212 transitions. [2019-11-28 17:32:32,455 INFO L78 Accepts]: Start accepts. Automaton has 121 states and 212 transitions. Word has length 35 [2019-11-28 17:32:32,455 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:32,455 INFO L462 AbstractCegarLoop]: Abstraction has 121 states and 212 transitions. [2019-11-28 17:32:32,455 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:32,456 INFO L276 IsEmpty]: Start isEmpty. Operand 121 states and 212 transitions. [2019-11-28 17:32:32,460 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-11-28 17:32:32,460 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:32,461 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:32,461 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:32,461 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:32,462 INFO L82 PathProgramCache]: Analyzing trace with hash 1101566611, now seen corresponding path program 1 times [2019-11-28 17:32:32,462 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:32,462 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [608651203] [2019-11-28 17:32:32,462 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:32,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:32,578 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:32,579 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [608651203] [2019-11-28 17:32:32,579 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:32,579 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:32,580 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1972592258] [2019-11-28 17:32:32,580 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:32,581 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:32,581 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:32,581 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:32,582 INFO L87 Difference]: Start difference. First operand 121 states and 212 transitions. Second operand 3 states. [2019-11-28 17:32:32,749 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:32,750 INFO L93 Difference]: Finished difference Result 316 states and 553 transitions. [2019-11-28 17:32:32,752 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:32,752 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 35 [2019-11-28 17:32:32,752 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:32,757 INFO L225 Difference]: With dead ends: 316 [2019-11-28 17:32:32,760 INFO L226 Difference]: Without dead ends: 206 [2019-11-28 17:32:32,762 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:32,765 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 206 states. [2019-11-28 17:32:32,802 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 206 to 196. [2019-11-28 17:32:32,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 196 states. [2019-11-28 17:32:32,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 196 states to 196 states and 330 transitions. [2019-11-28 17:32:32,810 INFO L78 Accepts]: Start accepts. Automaton has 196 states and 330 transitions. Word has length 35 [2019-11-28 17:32:32,810 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:32,810 INFO L462 AbstractCegarLoop]: Abstraction has 196 states and 330 transitions. [2019-11-28 17:32:32,811 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:32,811 INFO L276 IsEmpty]: Start isEmpty. Operand 196 states and 330 transitions. [2019-11-28 17:32:32,813 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-11-28 17:32:32,815 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:32,815 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:32,816 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:32,816 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:32,816 INFO L82 PathProgramCache]: Analyzing trace with hash 197658071, now seen corresponding path program 1 times [2019-11-28 17:32:32,817 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:32,817 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2057139300] [2019-11-28 17:32:32,818 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:32,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:32,889 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:32,890 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2057139300] [2019-11-28 17:32:32,890 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:32,890 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 17:32:32,891 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2116363140] [2019-11-28 17:32:32,891 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 17:32:32,892 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:32,892 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 17:32:32,893 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 17:32:32,893 INFO L87 Difference]: Start difference. First operand 196 states and 330 transitions. Second operand 4 states. [2019-11-28 17:32:33,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:33,055 INFO L93 Difference]: Finished difference Result 530 states and 896 transitions. [2019-11-28 17:32:33,056 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 17:32:33,056 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 35 [2019-11-28 17:32:33,056 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:33,060 INFO L225 Difference]: With dead ends: 530 [2019-11-28 17:32:33,060 INFO L226 Difference]: Without dead ends: 346 [2019-11-28 17:32:33,061 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:32:33,063 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 346 states. [2019-11-28 17:32:33,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 346 to 340. [2019-11-28 17:32:33,098 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 340 states. [2019-11-28 17:32:33,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 340 states to 340 states and 572 transitions. [2019-11-28 17:32:33,103 INFO L78 Accepts]: Start accepts. Automaton has 340 states and 572 transitions. Word has length 35 [2019-11-28 17:32:33,103 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:33,103 INFO L462 AbstractCegarLoop]: Abstraction has 340 states and 572 transitions. [2019-11-28 17:32:33,104 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 17:32:33,104 INFO L276 IsEmpty]: Start isEmpty. Operand 340 states and 572 transitions. [2019-11-28 17:32:33,106 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-11-28 17:32:33,108 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:33,108 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:33,111 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:33,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:33,111 INFO L82 PathProgramCache]: Analyzing trace with hash 259697685, now seen corresponding path program 1 times [2019-11-28 17:32:33,112 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:33,112 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1834233600] [2019-11-28 17:32:33,113 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:33,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:33,162 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:33,162 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1834233600] [2019-11-28 17:32:33,163 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:33,163 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 17:32:33,163 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1095024726] [2019-11-28 17:32:33,164 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 17:32:33,164 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:33,164 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 17:32:33,164 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 17:32:33,165 INFO L87 Difference]: Start difference. First operand 340 states and 572 transitions. Second operand 4 states. [2019-11-28 17:32:33,289 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:33,289 INFO L93 Difference]: Finished difference Result 955 states and 1611 transitions. [2019-11-28 17:32:33,290 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 17:32:33,290 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 35 [2019-11-28 17:32:33,290 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:33,294 INFO L225 Difference]: With dead ends: 955 [2019-11-28 17:32:33,294 INFO L226 Difference]: Without dead ends: 628 [2019-11-28 17:32:33,296 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:32:33,297 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 628 states. [2019-11-28 17:32:33,330 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 628 to 622. [2019-11-28 17:32:33,331 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 622 states. [2019-11-28 17:32:33,334 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 622 states to 622 states and 1042 transitions. [2019-11-28 17:32:33,334 INFO L78 Accepts]: Start accepts. Automaton has 622 states and 1042 transitions. Word has length 35 [2019-11-28 17:32:33,334 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:33,334 INFO L462 AbstractCegarLoop]: Abstraction has 622 states and 1042 transitions. [2019-11-28 17:32:33,334 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 17:32:33,335 INFO L276 IsEmpty]: Start isEmpty. Operand 622 states and 1042 transitions. [2019-11-28 17:32:33,337 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-11-28 17:32:33,337 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:33,337 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:33,338 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:33,338 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:33,338 INFO L82 PathProgramCache]: Analyzing trace with hash 400246295, now seen corresponding path program 1 times [2019-11-28 17:32:33,338 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:33,339 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [69550968] [2019-11-28 17:32:33,339 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:33,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:33,381 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:33,381 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [69550968] [2019-11-28 17:32:33,382 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:33,383 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 17:32:33,383 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [812636692] [2019-11-28 17:32:33,383 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 17:32:33,384 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:33,384 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 17:32:33,384 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 17:32:33,385 INFO L87 Difference]: Start difference. First operand 622 states and 1042 transitions. Second operand 4 states. [2019-11-28 17:32:33,550 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:33,550 INFO L93 Difference]: Finished difference Result 1891 states and 3148 transitions. [2019-11-28 17:32:33,551 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 17:32:33,551 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 35 [2019-11-28 17:32:33,551 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:33,560 INFO L225 Difference]: With dead ends: 1891 [2019-11-28 17:32:33,560 INFO L226 Difference]: Without dead ends: 1283 [2019-11-28 17:32:33,563 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:32:33,565 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1283 states. [2019-11-28 17:32:33,627 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1283 to 1277. [2019-11-28 17:32:33,628 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1277 states. [2019-11-28 17:32:33,634 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1277 states to 1277 states and 2102 transitions. [2019-11-28 17:32:33,634 INFO L78 Accepts]: Start accepts. Automaton has 1277 states and 2102 transitions. Word has length 35 [2019-11-28 17:32:33,634 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:33,635 INFO L462 AbstractCegarLoop]: Abstraction has 1277 states and 2102 transitions. [2019-11-28 17:32:33,635 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 17:32:33,635 INFO L276 IsEmpty]: Start isEmpty. Operand 1277 states and 2102 transitions. [2019-11-28 17:32:33,637 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-11-28 17:32:33,638 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:33,638 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:33,638 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:33,639 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:33,639 INFO L82 PathProgramCache]: Analyzing trace with hash 266232789, now seen corresponding path program 1 times [2019-11-28 17:32:33,639 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:33,640 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [927418817] [2019-11-28 17:32:33,640 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:33,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:33,708 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:33,709 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [927418817] [2019-11-28 17:32:33,709 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:33,709 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:33,710 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [119646394] [2019-11-28 17:32:33,710 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:33,717 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:33,717 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:33,718 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:33,718 INFO L87 Difference]: Start difference. First operand 1277 states and 2102 transitions. Second operand 3 states. [2019-11-28 17:32:33,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:33,849 INFO L93 Difference]: Finished difference Result 2603 states and 4295 transitions. [2019-11-28 17:32:33,849 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:33,850 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 35 [2019-11-28 17:32:33,850 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:33,859 INFO L225 Difference]: With dead ends: 2603 [2019-11-28 17:32:33,859 INFO L226 Difference]: Without dead ends: 1383 [2019-11-28 17:32:33,862 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:33,865 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1383 states. [2019-11-28 17:32:33,936 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1383 to 1376. [2019-11-28 17:32:33,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1376 states. [2019-11-28 17:32:33,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1376 states to 1376 states and 2257 transitions. [2019-11-28 17:32:33,944 INFO L78 Accepts]: Start accepts. Automaton has 1376 states and 2257 transitions. Word has length 35 [2019-11-28 17:32:33,944 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:33,944 INFO L462 AbstractCegarLoop]: Abstraction has 1376 states and 2257 transitions. [2019-11-28 17:32:33,944 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:33,945 INFO L276 IsEmpty]: Start isEmpty. Operand 1376 states and 2257 transitions. [2019-11-28 17:32:33,946 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-11-28 17:32:33,947 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:33,948 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:33,948 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:33,949 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:33,949 INFO L82 PathProgramCache]: Analyzing trace with hash -1908921127, now seen corresponding path program 1 times [2019-11-28 17:32:33,950 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:33,950 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [245666568] [2019-11-28 17:32:33,951 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:33,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:34,027 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:34,027 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [245666568] [2019-11-28 17:32:34,028 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:34,029 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 17:32:34,030 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1823760229] [2019-11-28 17:32:34,030 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 17:32:34,033 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:34,033 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 17:32:34,034 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 17:32:34,034 INFO L87 Difference]: Start difference. First operand 1376 states and 2257 transitions. Second operand 4 states. [2019-11-28 17:32:34,197 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:34,197 INFO L93 Difference]: Finished difference Result 2882 states and 4737 transitions. [2019-11-28 17:32:34,198 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-28 17:32:34,199 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 35 [2019-11-28 17:32:34,199 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:34,208 INFO L225 Difference]: With dead ends: 2882 [2019-11-28 17:32:34,209 INFO L226 Difference]: Without dead ends: 1540 [2019-11-28 17:32:34,212 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:32:34,215 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1540 states. [2019-11-28 17:32:34,322 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1540 to 1529. [2019-11-28 17:32:34,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1529 states. [2019-11-28 17:32:34,329 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1529 states to 1529 states and 2471 transitions. [2019-11-28 17:32:34,329 INFO L78 Accepts]: Start accepts. Automaton has 1529 states and 2471 transitions. Word has length 35 [2019-11-28 17:32:34,330 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:34,330 INFO L462 AbstractCegarLoop]: Abstraction has 1529 states and 2471 transitions. [2019-11-28 17:32:34,330 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 17:32:34,331 INFO L276 IsEmpty]: Start isEmpty. Operand 1529 states and 2471 transitions. [2019-11-28 17:32:34,331 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-11-28 17:32:34,332 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:34,332 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:34,332 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:34,332 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:34,333 INFO L82 PathProgramCache]: Analyzing trace with hash 1364977815, now seen corresponding path program 1 times [2019-11-28 17:32:34,333 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:34,334 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [360136354] [2019-11-28 17:32:34,334 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:34,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:34,370 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:34,370 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [360136354] [2019-11-28 17:32:34,370 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:34,371 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 17:32:34,372 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [179340243] [2019-11-28 17:32:34,372 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 17:32:34,373 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:34,373 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 17:32:34,374 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 17:32:34,374 INFO L87 Difference]: Start difference. First operand 1529 states and 2471 transitions. Second operand 4 states. [2019-11-28 17:32:34,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:34,527 INFO L93 Difference]: Finished difference Result 3348 states and 5416 transitions. [2019-11-28 17:32:34,528 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-28 17:32:34,528 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 35 [2019-11-28 17:32:34,528 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:34,540 INFO L225 Difference]: With dead ends: 3348 [2019-11-28 17:32:34,540 INFO L226 Difference]: Without dead ends: 1865 [2019-11-28 17:32:34,543 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:32:34,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1865 states. [2019-11-28 17:32:34,643 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1865 to 1841. [2019-11-28 17:32:34,644 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1841 states. [2019-11-28 17:32:34,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1841 states to 1841 states and 2935 transitions. [2019-11-28 17:32:34,655 INFO L78 Accepts]: Start accepts. Automaton has 1841 states and 2935 transitions. Word has length 35 [2019-11-28 17:32:34,655 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:34,655 INFO L462 AbstractCegarLoop]: Abstraction has 1841 states and 2935 transitions. [2019-11-28 17:32:34,656 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 17:32:34,656 INFO L276 IsEmpty]: Start isEmpty. Operand 1841 states and 2935 transitions. [2019-11-28 17:32:34,657 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2019-11-28 17:32:34,657 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:34,657 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:34,657 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:34,658 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:34,658 INFO L82 PathProgramCache]: Analyzing trace with hash 353860565, now seen corresponding path program 1 times [2019-11-28 17:32:34,658 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:34,659 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1893730445] [2019-11-28 17:32:34,659 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:34,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:34,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:34,686 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1893730445] [2019-11-28 17:32:34,686 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:34,686 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:34,686 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [657006304] [2019-11-28 17:32:34,686 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:34,687 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:34,687 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:34,687 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:34,687 INFO L87 Difference]: Start difference. First operand 1841 states and 2935 transitions. Second operand 3 states. [2019-11-28 17:32:34,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:34,800 INFO L93 Difference]: Finished difference Result 3307 states and 5278 transitions. [2019-11-28 17:32:34,801 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:34,801 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 35 [2019-11-28 17:32:34,801 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:34,809 INFO L225 Difference]: With dead ends: 3307 [2019-11-28 17:32:34,810 INFO L226 Difference]: Without dead ends: 1494 [2019-11-28 17:32:34,813 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:34,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1494 states. [2019-11-28 17:32:34,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1494 to 1483. [2019-11-28 17:32:34,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1483 states. [2019-11-28 17:32:34,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1483 states to 1483 states and 2335 transitions. [2019-11-28 17:32:34,885 INFO L78 Accepts]: Start accepts. Automaton has 1483 states and 2335 transitions. Word has length 35 [2019-11-28 17:32:34,886 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:34,886 INFO L462 AbstractCegarLoop]: Abstraction has 1483 states and 2335 transitions. [2019-11-28 17:32:34,886 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:34,886 INFO L276 IsEmpty]: Start isEmpty. Operand 1483 states and 2335 transitions. [2019-11-28 17:32:34,888 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2019-11-28 17:32:34,888 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:34,888 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:34,889 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:34,889 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:34,889 INFO L82 PathProgramCache]: Analyzing trace with hash -209495903, now seen corresponding path program 1 times [2019-11-28 17:32:34,889 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:34,890 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [289496047] [2019-11-28 17:32:34,890 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:34,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:34,921 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:34,921 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [289496047] [2019-11-28 17:32:34,921 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:34,921 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:34,922 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [76398195] [2019-11-28 17:32:34,922 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:34,922 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:34,922 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:34,923 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:34,923 INFO L87 Difference]: Start difference. First operand 1483 states and 2335 transitions. Second operand 3 states. [2019-11-28 17:32:35,050 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:35,051 INFO L93 Difference]: Finished difference Result 3698 states and 5877 transitions. [2019-11-28 17:32:35,051 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:35,051 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 45 [2019-11-28 17:32:35,052 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:35,066 INFO L225 Difference]: With dead ends: 3698 [2019-11-28 17:32:35,067 INFO L226 Difference]: Without dead ends: 2269 [2019-11-28 17:32:35,071 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:35,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2269 states. [2019-11-28 17:32:35,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2269 to 2267. [2019-11-28 17:32:35,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2267 states. [2019-11-28 17:32:35,212 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2267 states to 2267 states and 3563 transitions. [2019-11-28 17:32:35,213 INFO L78 Accepts]: Start accepts. Automaton has 2267 states and 3563 transitions. Word has length 45 [2019-11-28 17:32:35,213 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:35,213 INFO L462 AbstractCegarLoop]: Abstraction has 2267 states and 3563 transitions. [2019-11-28 17:32:35,213 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:35,214 INFO L276 IsEmpty]: Start isEmpty. Operand 2267 states and 3563 transitions. [2019-11-28 17:32:35,215 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2019-11-28 17:32:35,216 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:35,216 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:35,216 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:35,217 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:35,217 INFO L82 PathProgramCache]: Analyzing trace with hash 214150819, now seen corresponding path program 1 times [2019-11-28 17:32:35,217 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:35,219 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1419749084] [2019-11-28 17:32:35,219 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:35,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:35,255 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2019-11-28 17:32:35,255 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1419749084] [2019-11-28 17:32:35,256 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:35,256 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:35,256 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [207781523] [2019-11-28 17:32:35,256 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:35,257 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:35,257 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:35,257 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:35,258 INFO L87 Difference]: Start difference. First operand 2267 states and 3563 transitions. Second operand 3 states. [2019-11-28 17:32:35,366 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:35,367 INFO L93 Difference]: Finished difference Result 4436 states and 7000 transitions. [2019-11-28 17:32:35,367 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:35,367 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 45 [2019-11-28 17:32:35,368 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:35,381 INFO L225 Difference]: With dead ends: 4436 [2019-11-28 17:32:35,381 INFO L226 Difference]: Without dead ends: 2223 [2019-11-28 17:32:35,385 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:35,390 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2223 states. [2019-11-28 17:32:35,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2223 to 2223. [2019-11-28 17:32:35,499 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2223 states. [2019-11-28 17:32:35,508 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2223 states to 2223 states and 3506 transitions. [2019-11-28 17:32:35,509 INFO L78 Accepts]: Start accepts. Automaton has 2223 states and 3506 transitions. Word has length 45 [2019-11-28 17:32:35,510 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:35,511 INFO L462 AbstractCegarLoop]: Abstraction has 2223 states and 3506 transitions. [2019-11-28 17:32:35,511 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:35,511 INFO L276 IsEmpty]: Start isEmpty. Operand 2223 states and 3506 transitions. [2019-11-28 17:32:35,513 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2019-11-28 17:32:35,513 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:35,513 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:35,514 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:35,514 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:35,514 INFO L82 PathProgramCache]: Analyzing trace with hash 1700232685, now seen corresponding path program 1 times [2019-11-28 17:32:35,515 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:35,515 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1154539288] [2019-11-28 17:32:35,516 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:35,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:35,555 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:35,555 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1154539288] [2019-11-28 17:32:35,556 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:35,556 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:35,556 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [825502508] [2019-11-28 17:32:35,557 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:35,557 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:35,558 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:35,558 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:35,558 INFO L87 Difference]: Start difference. First operand 2223 states and 3506 transitions. Second operand 3 states. [2019-11-28 17:32:35,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:35,782 INFO L93 Difference]: Finished difference Result 5707 states and 9064 transitions. [2019-11-28 17:32:35,782 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:35,783 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 46 [2019-11-28 17:32:35,784 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:35,807 INFO L225 Difference]: With dead ends: 5707 [2019-11-28 17:32:35,808 INFO L226 Difference]: Without dead ends: 3538 [2019-11-28 17:32:35,815 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:35,822 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3538 states. [2019-11-28 17:32:36,122 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3538 to 3536. [2019-11-28 17:32:36,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3536 states. [2019-11-28 17:32:36,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3536 states to 3536 states and 5558 transitions. [2019-11-28 17:32:36,137 INFO L78 Accepts]: Start accepts. Automaton has 3536 states and 5558 transitions. Word has length 46 [2019-11-28 17:32:36,137 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:36,137 INFO L462 AbstractCegarLoop]: Abstraction has 3536 states and 5558 transitions. [2019-11-28 17:32:36,138 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:36,138 INFO L276 IsEmpty]: Start isEmpty. Operand 3536 states and 5558 transitions. [2019-11-28 17:32:36,140 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2019-11-28 17:32:36,141 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:36,141 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:36,141 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:36,142 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:36,142 INFO L82 PathProgramCache]: Analyzing trace with hash 1601371510, now seen corresponding path program 1 times [2019-11-28 17:32:36,142 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:36,148 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [427307159] [2019-11-28 17:32:36,148 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:36,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:36,196 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:36,196 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [427307159] [2019-11-28 17:32:36,196 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:36,197 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:36,197 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [803116732] [2019-11-28 17:32:36,197 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:36,197 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:36,197 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:36,199 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:36,199 INFO L87 Difference]: Start difference. First operand 3536 states and 5558 transitions. Second operand 3 states. [2019-11-28 17:32:36,493 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:36,493 INFO L93 Difference]: Finished difference Result 8979 states and 14292 transitions. [2019-11-28 17:32:36,493 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:36,494 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 47 [2019-11-28 17:32:36,495 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:36,524 INFO L225 Difference]: With dead ends: 8979 [2019-11-28 17:32:36,524 INFO L226 Difference]: Without dead ends: 5501 [2019-11-28 17:32:36,532 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:36,540 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5501 states. [2019-11-28 17:32:36,805 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5501 to 5499. [2019-11-28 17:32:36,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5499 states. [2019-11-28 17:32:36,832 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5499 states to 5499 states and 8711 transitions. [2019-11-28 17:32:36,833 INFO L78 Accepts]: Start accepts. Automaton has 5499 states and 8711 transitions. Word has length 47 [2019-11-28 17:32:36,834 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:36,834 INFO L462 AbstractCegarLoop]: Abstraction has 5499 states and 8711 transitions. [2019-11-28 17:32:36,835 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:36,835 INFO L276 IsEmpty]: Start isEmpty. Operand 5499 states and 8711 transitions. [2019-11-28 17:32:36,839 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2019-11-28 17:32:36,839 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:36,839 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:36,840 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:36,840 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:36,840 INFO L82 PathProgramCache]: Analyzing trace with hash 2025018232, now seen corresponding path program 1 times [2019-11-28 17:32:36,840 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:36,841 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2009461238] [2019-11-28 17:32:36,841 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:36,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:36,863 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2019-11-28 17:32:36,863 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2009461238] [2019-11-28 17:32:36,863 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:36,863 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:36,864 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1129393843] [2019-11-28 17:32:36,864 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:36,864 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:36,864 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:36,864 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:36,865 INFO L87 Difference]: Start difference. First operand 5499 states and 8711 transitions. Second operand 3 states. [2019-11-28 17:32:37,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:37,114 INFO L93 Difference]: Finished difference Result 10896 states and 17296 transitions. [2019-11-28 17:32:37,114 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:37,115 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 47 [2019-11-28 17:32:37,115 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:37,140 INFO L225 Difference]: With dead ends: 10896 [2019-11-28 17:32:37,140 INFO L226 Difference]: Without dead ends: 5455 [2019-11-28 17:32:37,150 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:37,159 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5455 states. [2019-11-28 17:32:37,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5455 to 5455. [2019-11-28 17:32:37,546 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5455 states. [2019-11-28 17:32:37,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5455 states to 5455 states and 8656 transitions. [2019-11-28 17:32:37,560 INFO L78 Accepts]: Start accepts. Automaton has 5455 states and 8656 transitions. Word has length 47 [2019-11-28 17:32:37,561 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:37,561 INFO L462 AbstractCegarLoop]: Abstraction has 5455 states and 8656 transitions. [2019-11-28 17:32:37,561 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:37,561 INFO L276 IsEmpty]: Start isEmpty. Operand 5455 states and 8656 transitions. [2019-11-28 17:32:37,564 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2019-11-28 17:32:37,565 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:37,565 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:37,565 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:37,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:37,566 INFO L82 PathProgramCache]: Analyzing trace with hash -2129316584, now seen corresponding path program 1 times [2019-11-28 17:32:37,566 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:37,566 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1667980064] [2019-11-28 17:32:37,567 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:37,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:37,595 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:37,595 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1667980064] [2019-11-28 17:32:37,596 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:37,596 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:37,596 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [367965693] [2019-11-28 17:32:37,596 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:37,597 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:37,597 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:37,597 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:37,598 INFO L87 Difference]: Start difference. First operand 5455 states and 8656 transitions. Second operand 3 states. [2019-11-28 17:32:37,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:37,992 INFO L93 Difference]: Finished difference Result 15441 states and 24452 transitions. [2019-11-28 17:32:37,992 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:37,993 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2019-11-28 17:32:37,993 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:38,021 INFO L225 Difference]: With dead ends: 15441 [2019-11-28 17:32:38,021 INFO L226 Difference]: Without dead ends: 8274 [2019-11-28 17:32:38,039 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:38,053 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8274 states. [2019-11-28 17:32:38,416 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8274 to 8274. [2019-11-28 17:32:38,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8274 states. [2019-11-28 17:32:38,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8274 states to 8274 states and 12950 transitions. [2019-11-28 17:32:38,437 INFO L78 Accepts]: Start accepts. Automaton has 8274 states and 12950 transitions. Word has length 48 [2019-11-28 17:32:38,437 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:38,437 INFO L462 AbstractCegarLoop]: Abstraction has 8274 states and 12950 transitions. [2019-11-28 17:32:38,437 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:38,438 INFO L276 IsEmpty]: Start isEmpty. Operand 8274 states and 12950 transitions. [2019-11-28 17:32:38,442 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2019-11-28 17:32:38,443 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:38,443 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:38,443 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:38,444 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:38,444 INFO L82 PathProgramCache]: Analyzing trace with hash -1392856220, now seen corresponding path program 1 times [2019-11-28 17:32:38,444 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:38,445 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [834132276] [2019-11-28 17:32:38,445 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:38,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:38,491 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:38,492 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [834132276] [2019-11-28 17:32:38,492 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:38,492 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:38,492 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [771751881] [2019-11-28 17:32:38,493 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:38,493 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:38,493 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:38,493 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:38,494 INFO L87 Difference]: Start difference. First operand 8274 states and 12950 transitions. Second operand 3 states. [2019-11-28 17:32:38,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:38,879 INFO L93 Difference]: Finished difference Result 17053 states and 26638 transitions. [2019-11-28 17:32:38,880 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:38,880 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 52 [2019-11-28 17:32:38,880 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:38,901 INFO L225 Difference]: With dead ends: 17053 [2019-11-28 17:32:38,901 INFO L226 Difference]: Without dead ends: 8815 [2019-11-28 17:32:38,917 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:38,928 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8815 states. [2019-11-28 17:32:39,233 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8815 to 8272. [2019-11-28 17:32:39,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8272 states. [2019-11-28 17:32:39,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8272 states to 8272 states and 12699 transitions. [2019-11-28 17:32:39,251 INFO L78 Accepts]: Start accepts. Automaton has 8272 states and 12699 transitions. Word has length 52 [2019-11-28 17:32:39,251 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:39,252 INFO L462 AbstractCegarLoop]: Abstraction has 8272 states and 12699 transitions. [2019-11-28 17:32:39,252 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:39,252 INFO L276 IsEmpty]: Start isEmpty. Operand 8272 states and 12699 transitions. [2019-11-28 17:32:39,260 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2019-11-28 17:32:39,260 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:39,260 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:39,261 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:39,261 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:39,261 INFO L82 PathProgramCache]: Analyzing trace with hash 1708846795, now seen corresponding path program 1 times [2019-11-28 17:32:39,262 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:39,262 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1013471707] [2019-11-28 17:32:39,262 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:39,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:39,302 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2019-11-28 17:32:39,303 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1013471707] [2019-11-28 17:32:39,303 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:39,303 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:39,303 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [790134210] [2019-11-28 17:32:39,304 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:39,304 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:39,304 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:39,304 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:39,304 INFO L87 Difference]: Start difference. First operand 8272 states and 12699 transitions. Second operand 3 states. [2019-11-28 17:32:39,953 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:39,954 INFO L93 Difference]: Finished difference Result 24504 states and 37704 transitions. [2019-11-28 17:32:39,954 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:39,954 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 54 [2019-11-28 17:32:39,955 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:39,997 INFO L225 Difference]: With dead ends: 24504 [2019-11-28 17:32:39,998 INFO L226 Difference]: Without dead ends: 16235 [2019-11-28 17:32:40,022 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:40,054 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16235 states. [2019-11-28 17:32:40,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16235 to 16105. [2019-11-28 17:32:40,852 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16105 states. [2019-11-28 17:32:40,894 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16105 states to 16105 states and 24847 transitions. [2019-11-28 17:32:40,895 INFO L78 Accepts]: Start accepts. Automaton has 16105 states and 24847 transitions. Word has length 54 [2019-11-28 17:32:40,895 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:40,896 INFO L462 AbstractCegarLoop]: Abstraction has 16105 states and 24847 transitions. [2019-11-28 17:32:40,896 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:40,896 INFO L276 IsEmpty]: Start isEmpty. Operand 16105 states and 24847 transitions. [2019-11-28 17:32:40,914 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2019-11-28 17:32:40,914 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:40,915 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:40,915 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:40,916 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:40,916 INFO L82 PathProgramCache]: Analyzing trace with hash 194830513, now seen corresponding path program 1 times [2019-11-28 17:32:40,918 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:40,919 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [253711853] [2019-11-28 17:32:40,919 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:40,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:40,964 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:40,965 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [253711853] [2019-11-28 17:32:40,966 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:40,966 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:40,966 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [95534544] [2019-11-28 17:32:40,968 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:40,969 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:40,969 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:40,970 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:40,970 INFO L87 Difference]: Start difference. First operand 16105 states and 24847 transitions. Second operand 3 states. [2019-11-28 17:32:41,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:41,631 INFO L93 Difference]: Finished difference Result 32865 states and 50652 transitions. [2019-11-28 17:32:41,632 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:41,632 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 85 [2019-11-28 17:32:41,632 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:41,880 INFO L225 Difference]: With dead ends: 32865 [2019-11-28 17:32:41,881 INFO L226 Difference]: Without dead ends: 16789 [2019-11-28 17:32:41,913 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:41,933 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16789 states. [2019-11-28 17:32:42,629 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16789 to 16725. [2019-11-28 17:32:42,630 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16725 states. [2019-11-28 17:32:42,663 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16725 states to 16725 states and 25149 transitions. [2019-11-28 17:32:42,664 INFO L78 Accepts]: Start accepts. Automaton has 16725 states and 25149 transitions. Word has length 85 [2019-11-28 17:32:42,664 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:42,664 INFO L462 AbstractCegarLoop]: Abstraction has 16725 states and 25149 transitions. [2019-11-28 17:32:42,664 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:42,665 INFO L276 IsEmpty]: Start isEmpty. Operand 16725 states and 25149 transitions. [2019-11-28 17:32:42,675 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2019-11-28 17:32:42,675 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:42,676 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:42,676 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:42,676 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:42,677 INFO L82 PathProgramCache]: Analyzing trace with hash 164482089, now seen corresponding path program 1 times [2019-11-28 17:32:42,677 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:42,677 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1948415908] [2019-11-28 17:32:42,677 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:42,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:42,716 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-11-28 17:32:42,716 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1948415908] [2019-11-28 17:32:42,717 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:42,717 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 17:32:42,717 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [419407424] [2019-11-28 17:32:42,718 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 17:32:42,718 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:42,718 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 17:32:42,718 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 17:32:42,719 INFO L87 Difference]: Start difference. First operand 16725 states and 25149 transitions. Second operand 4 states. [2019-11-28 17:32:43,331 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:43,331 INFO L93 Difference]: Finished difference Result 27583 states and 41591 transitions. [2019-11-28 17:32:43,333 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-11-28 17:32:43,333 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 86 [2019-11-28 17:32:43,333 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:43,375 INFO L225 Difference]: With dead ends: 27583 [2019-11-28 17:32:43,376 INFO L226 Difference]: Without dead ends: 15803 [2019-11-28 17:32:43,393 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:32:43,408 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15803 states. [2019-11-28 17:32:44,299 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15803 to 15713. [2019-11-28 17:32:44,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15713 states. [2019-11-28 17:32:44,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15713 states to 15713 states and 23443 transitions. [2019-11-28 17:32:44,322 INFO L78 Accepts]: Start accepts. Automaton has 15713 states and 23443 transitions. Word has length 86 [2019-11-28 17:32:44,322 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:44,322 INFO L462 AbstractCegarLoop]: Abstraction has 15713 states and 23443 transitions. [2019-11-28 17:32:44,323 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 17:32:44,323 INFO L276 IsEmpty]: Start isEmpty. Operand 15713 states and 23443 transitions. [2019-11-28 17:32:44,331 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2019-11-28 17:32:44,331 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:44,331 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:44,332 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:44,332 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:44,332 INFO L82 PathProgramCache]: Analyzing trace with hash -433884439, now seen corresponding path program 1 times [2019-11-28 17:32:44,333 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:44,333 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1859704899] [2019-11-28 17:32:44,333 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:44,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:44,372 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:44,373 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1859704899] [2019-11-28 17:32:44,373 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:44,373 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:44,374 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [563874573] [2019-11-28 17:32:44,374 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:44,374 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:44,375 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:44,375 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:44,375 INFO L87 Difference]: Start difference. First operand 15713 states and 23443 transitions. Second operand 3 states. [2019-11-28 17:32:44,814 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:44,814 INFO L93 Difference]: Finished difference Result 32195 states and 47984 transitions. [2019-11-28 17:32:44,814 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:44,814 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 86 [2019-11-28 17:32:44,815 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:44,858 INFO L225 Difference]: With dead ends: 32195 [2019-11-28 17:32:44,858 INFO L226 Difference]: Without dead ends: 16523 [2019-11-28 17:32:44,877 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:44,894 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16523 states. [2019-11-28 17:32:45,407 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16523 to 16443. [2019-11-28 17:32:45,408 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16443 states. [2019-11-28 17:32:45,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16443 states to 16443 states and 23815 transitions. [2019-11-28 17:32:45,429 INFO L78 Accepts]: Start accepts. Automaton has 16443 states and 23815 transitions. Word has length 86 [2019-11-28 17:32:45,430 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:45,430 INFO L462 AbstractCegarLoop]: Abstraction has 16443 states and 23815 transitions. [2019-11-28 17:32:45,430 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:45,430 INFO L276 IsEmpty]: Start isEmpty. Operand 16443 states and 23815 transitions. [2019-11-28 17:32:45,437 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2019-11-28 17:32:45,438 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:45,438 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:45,438 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:45,439 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:45,439 INFO L82 PathProgramCache]: Analyzing trace with hash -1869450223, now seen corresponding path program 1 times [2019-11-28 17:32:45,439 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:45,439 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1889796465] [2019-11-28 17:32:45,440 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:45,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:45,468 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:45,468 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1889796465] [2019-11-28 17:32:45,469 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:45,469 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:45,469 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [393616747] [2019-11-28 17:32:45,470 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:45,470 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:45,470 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:45,470 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:45,471 INFO L87 Difference]: Start difference. First operand 16443 states and 23815 transitions. Second operand 3 states. [2019-11-28 17:32:46,477 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:46,478 INFO L93 Difference]: Finished difference Result 33302 states and 48352 transitions. [2019-11-28 17:32:46,479 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:46,479 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 87 [2019-11-28 17:32:46,479 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:46,524 INFO L225 Difference]: With dead ends: 33302 [2019-11-28 17:32:46,524 INFO L226 Difference]: Without dead ends: 16920 [2019-11-28 17:32:46,545 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:46,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16920 states. [2019-11-28 17:32:47,028 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16920 to 13439. [2019-11-28 17:32:47,028 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13439 states. [2019-11-28 17:32:47,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13439 states to 13439 states and 18777 transitions. [2019-11-28 17:32:47,052 INFO L78 Accepts]: Start accepts. Automaton has 13439 states and 18777 transitions. Word has length 87 [2019-11-28 17:32:47,053 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:47,053 INFO L462 AbstractCegarLoop]: Abstraction has 13439 states and 18777 transitions. [2019-11-28 17:32:47,053 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:47,053 INFO L276 IsEmpty]: Start isEmpty. Operand 13439 states and 18777 transitions. [2019-11-28 17:32:47,061 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2019-11-28 17:32:47,061 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:47,061 INFO L410 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:47,062 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:47,062 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:47,062 INFO L82 PathProgramCache]: Analyzing trace with hash -2059863225, now seen corresponding path program 1 times [2019-11-28 17:32:47,063 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:47,069 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [161578417] [2019-11-28 17:32:47,069 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:47,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:47,117 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2019-11-28 17:32:47,118 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [161578417] [2019-11-28 17:32:47,118 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:47,118 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:47,119 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1379555991] [2019-11-28 17:32:47,119 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:47,119 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:47,120 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:47,120 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:47,120 INFO L87 Difference]: Start difference. First operand 13439 states and 18777 transitions. Second operand 3 states. [2019-11-28 17:32:47,698 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:47,698 INFO L93 Difference]: Finished difference Result 23921 states and 33457 transitions. [2019-11-28 17:32:47,699 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:47,699 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 88 [2019-11-28 17:32:47,699 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:47,720 INFO L225 Difference]: With dead ends: 23921 [2019-11-28 17:32:47,721 INFO L226 Difference]: Without dead ends: 15605 [2019-11-28 17:32:47,733 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:47,747 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15605 states. [2019-11-28 17:32:48,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15605 to 15125. [2019-11-28 17:32:48,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15125 states. [2019-11-28 17:32:48,739 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15125 states to 15125 states and 20656 transitions. [2019-11-28 17:32:48,740 INFO L78 Accepts]: Start accepts. Automaton has 15125 states and 20656 transitions. Word has length 88 [2019-11-28 17:32:48,740 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:48,740 INFO L462 AbstractCegarLoop]: Abstraction has 15125 states and 20656 transitions. [2019-11-28 17:32:48,740 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:48,740 INFO L276 IsEmpty]: Start isEmpty. Operand 15125 states and 20656 transitions. [2019-11-28 17:32:48,755 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2019-11-28 17:32:48,755 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:48,755 INFO L410 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:48,756 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:48,756 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:48,756 INFO L82 PathProgramCache]: Analyzing trace with hash 1061949686, now seen corresponding path program 1 times [2019-11-28 17:32:48,756 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:48,756 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2111884708] [2019-11-28 17:32:48,757 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:48,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:48,790 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2019-11-28 17:32:48,791 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2111884708] [2019-11-28 17:32:48,791 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:48,792 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:48,792 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1069478271] [2019-11-28 17:32:48,792 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:48,793 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:48,793 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:48,793 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:48,793 INFO L87 Difference]: Start difference. First operand 15125 states and 20656 transitions. Second operand 3 states. [2019-11-28 17:32:49,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:49,258 INFO L93 Difference]: Finished difference Result 29488 states and 40230 transitions. [2019-11-28 17:32:49,259 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:49,259 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 115 [2019-11-28 17:32:49,259 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:49,274 INFO L225 Difference]: With dead ends: 29488 [2019-11-28 17:32:49,274 INFO L226 Difference]: Without dead ends: 15055 [2019-11-28 17:32:49,287 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:49,300 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15055 states. [2019-11-28 17:32:49,703 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15055 to 15055. [2019-11-28 17:32:49,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15055 states. [2019-11-28 17:32:49,720 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15055 states to 15055 states and 20502 transitions. [2019-11-28 17:32:49,720 INFO L78 Accepts]: Start accepts. Automaton has 15055 states and 20502 transitions. Word has length 115 [2019-11-28 17:32:49,720 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:49,720 INFO L462 AbstractCegarLoop]: Abstraction has 15055 states and 20502 transitions. [2019-11-28 17:32:49,721 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:49,721 INFO L276 IsEmpty]: Start isEmpty. Operand 15055 states and 20502 transitions. [2019-11-28 17:32:49,734 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 127 [2019-11-28 17:32:49,735 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:49,735 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:49,736 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:49,736 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:49,736 INFO L82 PathProgramCache]: Analyzing trace with hash -1410428474, now seen corresponding path program 1 times [2019-11-28 17:32:49,736 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:49,737 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1227386767] [2019-11-28 17:32:49,737 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:49,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:49,773 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2019-11-28 17:32:49,773 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1227386767] [2019-11-28 17:32:49,773 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:49,774 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:49,774 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1345035864] [2019-11-28 17:32:49,775 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:49,775 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:49,775 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:49,775 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:49,776 INFO L87 Difference]: Start difference. First operand 15055 states and 20502 transitions. Second operand 3 states. [2019-11-28 17:32:50,145 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:50,146 INFO L93 Difference]: Finished difference Result 25586 states and 34782 transitions. [2019-11-28 17:32:50,146 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:50,146 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 126 [2019-11-28 17:32:50,146 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:50,158 INFO L225 Difference]: With dead ends: 25586 [2019-11-28 17:32:50,158 INFO L226 Difference]: Without dead ends: 10588 [2019-11-28 17:32:50,168 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:50,174 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10588 states. [2019-11-28 17:32:50,766 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10588 to 8620. [2019-11-28 17:32:50,767 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8620 states. [2019-11-28 17:32:50,777 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8620 states to 8620 states and 11274 transitions. [2019-11-28 17:32:50,777 INFO L78 Accepts]: Start accepts. Automaton has 8620 states and 11274 transitions. Word has length 126 [2019-11-28 17:32:50,777 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:50,777 INFO L462 AbstractCegarLoop]: Abstraction has 8620 states and 11274 transitions. [2019-11-28 17:32:50,777 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:50,778 INFO L276 IsEmpty]: Start isEmpty. Operand 8620 states and 11274 transitions. [2019-11-28 17:32:50,786 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2019-11-28 17:32:50,786 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:50,787 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:50,787 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:50,787 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:50,788 INFO L82 PathProgramCache]: Analyzing trace with hash 314934891, now seen corresponding path program 1 times [2019-11-28 17:32:50,788 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:50,788 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1703967398] [2019-11-28 17:32:50,788 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:50,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:50,819 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 43 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2019-11-28 17:32:50,820 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1703967398] [2019-11-28 17:32:50,820 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:50,820 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:50,821 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [866944089] [2019-11-28 17:32:50,821 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:50,821 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:50,822 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:50,822 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:50,822 INFO L87 Difference]: Start difference. First operand 8620 states and 11274 transitions. Second operand 3 states. [2019-11-28 17:32:51,045 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:51,045 INFO L93 Difference]: Finished difference Result 14199 states and 18567 transitions. [2019-11-28 17:32:51,045 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:51,046 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 127 [2019-11-28 17:32:51,046 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:51,054 INFO L225 Difference]: With dead ends: 14199 [2019-11-28 17:32:51,054 INFO L226 Difference]: Without dead ends: 6733 [2019-11-28 17:32:51,061 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:51,066 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6733 states. [2019-11-28 17:32:51,431 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6733 to 6149. [2019-11-28 17:32:51,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6149 states. [2019-11-28 17:32:51,444 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6149 states to 6149 states and 7873 transitions. [2019-11-28 17:32:51,444 INFO L78 Accepts]: Start accepts. Automaton has 6149 states and 7873 transitions. Word has length 127 [2019-11-28 17:32:51,444 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:51,445 INFO L462 AbstractCegarLoop]: Abstraction has 6149 states and 7873 transitions. [2019-11-28 17:32:51,445 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:51,445 INFO L276 IsEmpty]: Start isEmpty. Operand 6149 states and 7873 transitions. [2019-11-28 17:32:51,459 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2019-11-28 17:32:51,459 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:51,459 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:51,460 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:51,460 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:51,460 INFO L82 PathProgramCache]: Analyzing trace with hash -146147841, now seen corresponding path program 1 times [2019-11-28 17:32:51,461 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:51,461 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [766922644] [2019-11-28 17:32:51,461 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:51,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:51,526 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2019-11-28 17:32:51,526 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [766922644] [2019-11-28 17:32:51,527 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:51,527 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:51,527 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [596884055] [2019-11-28 17:32:51,528 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:51,528 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:51,528 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:51,529 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:51,529 INFO L87 Difference]: Start difference. First operand 6149 states and 7873 transitions. Second operand 3 states. [2019-11-28 17:32:51,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:51,853 INFO L93 Difference]: Finished difference Result 11907 states and 15226 transitions. [2019-11-28 17:32:51,853 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:51,854 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 133 [2019-11-28 17:32:51,854 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:51,862 INFO L225 Difference]: With dead ends: 11907 [2019-11-28 17:32:51,863 INFO L226 Difference]: Without dead ends: 6149 [2019-11-28 17:32:51,869 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:51,876 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6149 states. [2019-11-28 17:32:52,260 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6149 to 6109. [2019-11-28 17:32:52,261 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6109 states. [2019-11-28 17:32:52,271 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6109 states to 6109 states and 7791 transitions. [2019-11-28 17:32:52,272 INFO L78 Accepts]: Start accepts. Automaton has 6109 states and 7791 transitions. Word has length 133 [2019-11-28 17:32:52,272 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:52,272 INFO L462 AbstractCegarLoop]: Abstraction has 6109 states and 7791 transitions. [2019-11-28 17:32:52,272 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:52,273 INFO L276 IsEmpty]: Start isEmpty. Operand 6109 states and 7791 transitions. [2019-11-28 17:32:52,280 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2019-11-28 17:32:52,280 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:52,281 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:52,281 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:52,281 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:52,282 INFO L82 PathProgramCache]: Analyzing trace with hash 1797709215, now seen corresponding path program 1 times [2019-11-28 17:32:52,282 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:52,283 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1926335303] [2019-11-28 17:32:52,283 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:52,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:52,361 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2019-11-28 17:32:52,362 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1926335303] [2019-11-28 17:32:52,362 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:52,363 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:52,363 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [946585036] [2019-11-28 17:32:52,364 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:52,364 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:52,365 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:52,365 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:52,365 INFO L87 Difference]: Start difference. First operand 6109 states and 7791 transitions. Second operand 3 states. [2019-11-28 17:32:52,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:52,670 INFO L93 Difference]: Finished difference Result 11855 states and 15104 transitions. [2019-11-28 17:32:52,670 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:52,671 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 133 [2019-11-28 17:32:52,671 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:52,679 INFO L225 Difference]: With dead ends: 11855 [2019-11-28 17:32:52,679 INFO L226 Difference]: Without dead ends: 6118 [2019-11-28 17:32:52,684 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:52,690 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6118 states. [2019-11-28 17:32:53,013 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6118 to 6078. [2019-11-28 17:32:53,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6078 states. [2019-11-28 17:32:53,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6078 states to 6078 states and 7719 transitions. [2019-11-28 17:32:53,027 INFO L78 Accepts]: Start accepts. Automaton has 6078 states and 7719 transitions. Word has length 133 [2019-11-28 17:32:53,027 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:53,027 INFO L462 AbstractCegarLoop]: Abstraction has 6078 states and 7719 transitions. [2019-11-28 17:32:53,028 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:53,028 INFO L276 IsEmpty]: Start isEmpty. Operand 6078 states and 7719 transitions. [2019-11-28 17:32:53,034 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2019-11-28 17:32:53,035 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:53,035 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:53,036 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:53,036 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:53,036 INFO L82 PathProgramCache]: Analyzing trace with hash 282610594, now seen corresponding path program 1 times [2019-11-28 17:32:53,036 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:53,037 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [59807488] [2019-11-28 17:32:53,037 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:53,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:53,092 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 46 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2019-11-28 17:32:53,093 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [59807488] [2019-11-28 17:32:53,093 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:53,093 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:53,094 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [171411150] [2019-11-28 17:32:53,094 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:53,094 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:53,095 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:53,095 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:53,095 INFO L87 Difference]: Start difference. First operand 6078 states and 7719 transitions. Second operand 3 states. [2019-11-28 17:32:53,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:53,347 INFO L93 Difference]: Finished difference Result 10860 states and 13837 transitions. [2019-11-28 17:32:53,347 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:53,347 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 136 [2019-11-28 17:32:53,348 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:53,354 INFO L225 Difference]: With dead ends: 10860 [2019-11-28 17:32:53,354 INFO L226 Difference]: Without dead ends: 5146 [2019-11-28 17:32:53,361 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:53,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5146 states. [2019-11-28 17:32:53,692 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5146 to 5076. [2019-11-28 17:32:53,692 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5076 states. [2019-11-28 17:32:53,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5076 states to 5076 states and 6341 transitions. [2019-11-28 17:32:53,702 INFO L78 Accepts]: Start accepts. Automaton has 5076 states and 6341 transitions. Word has length 136 [2019-11-28 17:32:53,703 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:53,703 INFO L462 AbstractCegarLoop]: Abstraction has 5076 states and 6341 transitions. [2019-11-28 17:32:53,703 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:53,703 INFO L276 IsEmpty]: Start isEmpty. Operand 5076 states and 6341 transitions. [2019-11-28 17:32:53,707 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2019-11-28 17:32:53,707 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:53,707 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:53,708 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:53,708 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:53,708 INFO L82 PathProgramCache]: Analyzing trace with hash -1519116211, now seen corresponding path program 1 times [2019-11-28 17:32:53,709 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:53,709 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [303207544] [2019-11-28 17:32:53,709 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:53,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:53,773 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 45 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2019-11-28 17:32:53,775 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [303207544] [2019-11-28 17:32:53,775 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:53,775 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:53,778 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [108816392] [2019-11-28 17:32:53,779 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:53,779 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:53,780 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:53,780 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:53,781 INFO L87 Difference]: Start difference. First operand 5076 states and 6341 transitions. Second operand 3 states. [2019-11-28 17:32:54,067 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:54,068 INFO L93 Difference]: Finished difference Result 9133 states and 11446 transitions. [2019-11-28 17:32:54,068 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:54,069 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 136 [2019-11-28 17:32:54,069 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:54,075 INFO L225 Difference]: With dead ends: 9133 [2019-11-28 17:32:54,075 INFO L226 Difference]: Without dead ends: 4098 [2019-11-28 17:32:54,081 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:54,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4098 states. [2019-11-28 17:32:54,303 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4098 to 4080. [2019-11-28 17:32:54,303 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4080 states. [2019-11-28 17:32:54,309 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4080 states to 4080 states and 5008 transitions. [2019-11-28 17:32:54,309 INFO L78 Accepts]: Start accepts. Automaton has 4080 states and 5008 transitions. Word has length 136 [2019-11-28 17:32:54,310 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:54,310 INFO L462 AbstractCegarLoop]: Abstraction has 4080 states and 5008 transitions. [2019-11-28 17:32:54,310 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:54,310 INFO L276 IsEmpty]: Start isEmpty. Operand 4080 states and 5008 transitions. [2019-11-28 17:32:54,313 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 170 [2019-11-28 17:32:54,313 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:54,313 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:54,314 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:54,314 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:54,314 INFO L82 PathProgramCache]: Analyzing trace with hash -1856914244, now seen corresponding path program 1 times [2019-11-28 17:32:54,314 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:54,314 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [767114534] [2019-11-28 17:32:54,315 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:54,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:54,382 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 75 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2019-11-28 17:32:54,383 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [767114534] [2019-11-28 17:32:54,383 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:54,383 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:54,383 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [368362989] [2019-11-28 17:32:54,384 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:54,384 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:54,384 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:54,384 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:54,385 INFO L87 Difference]: Start difference. First operand 4080 states and 5008 transitions. Second operand 3 states. [2019-11-28 17:32:54,708 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:54,709 INFO L93 Difference]: Finished difference Result 7575 states and 9357 transitions. [2019-11-28 17:32:54,709 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:54,709 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 169 [2019-11-28 17:32:54,710 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:54,714 INFO L225 Difference]: With dead ends: 7575 [2019-11-28 17:32:54,714 INFO L226 Difference]: Without dead ends: 3771 [2019-11-28 17:32:54,727 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:54,731 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3771 states. [2019-11-28 17:32:54,983 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3771 to 3560. [2019-11-28 17:32:54,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3560 states. [2019-11-28 17:32:54,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3560 states to 3560 states and 4335 transitions. [2019-11-28 17:32:54,990 INFO L78 Accepts]: Start accepts. Automaton has 3560 states and 4335 transitions. Word has length 169 [2019-11-28 17:32:54,990 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:54,991 INFO L462 AbstractCegarLoop]: Abstraction has 3560 states and 4335 transitions. [2019-11-28 17:32:54,991 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:54,991 INFO L276 IsEmpty]: Start isEmpty. Operand 3560 states and 4335 transitions. [2019-11-28 17:32:54,995 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2019-11-28 17:32:54,995 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:54,996 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:54,996 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:54,996 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:54,997 INFO L82 PathProgramCache]: Analyzing trace with hash 38014472, now seen corresponding path program 1 times [2019-11-28 17:32:54,997 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:54,997 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [157103928] [2019-11-28 17:32:54,997 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:55,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:55,062 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 82 proven. 0 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2019-11-28 17:32:55,062 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [157103928] [2019-11-28 17:32:55,062 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:55,062 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:55,063 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1693103837] [2019-11-28 17:32:55,063 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:55,063 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:55,064 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:55,064 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:55,064 INFO L87 Difference]: Start difference. First operand 3560 states and 4335 transitions. Second operand 3 states. [2019-11-28 17:32:55,431 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:55,431 INFO L93 Difference]: Finished difference Result 8918 states and 10901 transitions. [2019-11-28 17:32:55,431 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:55,432 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 176 [2019-11-28 17:32:55,432 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:55,437 INFO L225 Difference]: With dead ends: 8918 [2019-11-28 17:32:55,438 INFO L226 Difference]: Without dead ends: 5634 [2019-11-28 17:32:55,440 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:55,444 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5634 states. [2019-11-28 17:32:55,592 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5634 to 5414. [2019-11-28 17:32:55,592 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5414 states. [2019-11-28 17:32:55,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5414 states to 5414 states and 6513 transitions. [2019-11-28 17:32:55,598 INFO L78 Accepts]: Start accepts. Automaton has 5414 states and 6513 transitions. Word has length 176 [2019-11-28 17:32:55,599 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:55,599 INFO L462 AbstractCegarLoop]: Abstraction has 5414 states and 6513 transitions. [2019-11-28 17:32:55,599 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:55,599 INFO L276 IsEmpty]: Start isEmpty. Operand 5414 states and 6513 transitions. [2019-11-28 17:32:55,602 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-11-28 17:32:55,602 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:55,603 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:55,603 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:55,603 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:55,603 INFO L82 PathProgramCache]: Analyzing trace with hash -1974043446, now seen corresponding path program 1 times [2019-11-28 17:32:55,603 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:55,603 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1886700397] [2019-11-28 17:32:55,604 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:55,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:55,643 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 79 proven. 0 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2019-11-28 17:32:55,643 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1886700397] [2019-11-28 17:32:55,644 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:55,644 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:55,644 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1568173680] [2019-11-28 17:32:55,644 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:55,645 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:55,645 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:55,645 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:55,645 INFO L87 Difference]: Start difference. First operand 5414 states and 6513 transitions. Second operand 3 states. [2019-11-28 17:32:55,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:55,799 INFO L93 Difference]: Finished difference Result 8838 states and 10694 transitions. [2019-11-28 17:32:55,800 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:55,800 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 179 [2019-11-28 17:32:55,800 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:55,804 INFO L225 Difference]: With dead ends: 8838 [2019-11-28 17:32:55,804 INFO L226 Difference]: Without dead ends: 3700 [2019-11-28 17:32:55,807 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:55,810 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3700 states. [2019-11-28 17:32:55,906 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3700 to 3094. [2019-11-28 17:32:55,907 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3094 states. [2019-11-28 17:32:55,910 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3094 states to 3094 states and 3684 transitions. [2019-11-28 17:32:55,910 INFO L78 Accepts]: Start accepts. Automaton has 3094 states and 3684 transitions. Word has length 179 [2019-11-28 17:32:55,910 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:55,910 INFO L462 AbstractCegarLoop]: Abstraction has 3094 states and 3684 transitions. [2019-11-28 17:32:55,910 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:55,910 INFO L276 IsEmpty]: Start isEmpty. Operand 3094 states and 3684 transitions. [2019-11-28 17:32:55,913 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2019-11-28 17:32:55,913 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:55,913 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:55,913 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:55,913 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:55,913 INFO L82 PathProgramCache]: Analyzing trace with hash -831540980, now seen corresponding path program 1 times [2019-11-28 17:32:55,914 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:55,914 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1392224270] [2019-11-28 17:32:55,914 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:55,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:55,966 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 91 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-11-28 17:32:55,967 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1392224270] [2019-11-28 17:32:55,967 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:55,967 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-11-28 17:32:55,967 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [50896396] [2019-11-28 17:32:55,968 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-11-28 17:32:55,968 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:55,968 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-11-28 17:32:55,971 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-11-28 17:32:55,971 INFO L87 Difference]: Start difference. First operand 3094 states and 3684 transitions. Second operand 4 states. [2019-11-28 17:32:56,117 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:56,117 INFO L93 Difference]: Finished difference Result 4689 states and 5567 transitions. [2019-11-28 17:32:56,117 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-11-28 17:32:56,117 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 179 [2019-11-28 17:32:56,118 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:56,120 INFO L225 Difference]: With dead ends: 4689 [2019-11-28 17:32:56,120 INFO L226 Difference]: Without dead ends: 1871 [2019-11-28 17:32:56,122 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:32:56,123 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1871 states. [2019-11-28 17:32:56,179 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1871 to 1584. [2019-11-28 17:32:56,179 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1584 states. [2019-11-28 17:32:56,181 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1584 states to 1584 states and 1844 transitions. [2019-11-28 17:32:56,181 INFO L78 Accepts]: Start accepts. Automaton has 1584 states and 1844 transitions. Word has length 179 [2019-11-28 17:32:56,181 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:56,181 INFO L462 AbstractCegarLoop]: Abstraction has 1584 states and 1844 transitions. [2019-11-28 17:32:56,182 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-11-28 17:32:56,182 INFO L276 IsEmpty]: Start isEmpty. Operand 1584 states and 1844 transitions. [2019-11-28 17:32:56,182 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 184 [2019-11-28 17:32:56,183 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:56,183 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:56,183 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:56,183 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:56,183 INFO L82 PathProgramCache]: Analyzing trace with hash 1681635082, now seen corresponding path program 1 times [2019-11-28 17:32:56,183 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:56,184 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1998211481] [2019-11-28 17:32:56,184 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:56,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:56,234 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 100 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-11-28 17:32:56,234 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1998211481] [2019-11-28 17:32:56,235 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:56,235 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:56,235 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1815624863] [2019-11-28 17:32:56,235 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:56,235 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:56,236 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:56,236 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:56,236 INFO L87 Difference]: Start difference. First operand 1584 states and 1844 transitions. Second operand 3 states. [2019-11-28 17:32:56,369 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:56,369 INFO L93 Difference]: Finished difference Result 4040 states and 4732 transitions. [2019-11-28 17:32:56,369 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:56,369 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 183 [2019-11-28 17:32:56,370 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:56,372 INFO L225 Difference]: With dead ends: 4040 [2019-11-28 17:32:56,372 INFO L226 Difference]: Without dead ends: 2426 [2019-11-28 17:32:56,373 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:56,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2426 states. [2019-11-28 17:32:56,453 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2426 to 2416. [2019-11-28 17:32:56,453 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2416 states. [2019-11-28 17:32:56,456 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2416 states to 2416 states and 2812 transitions. [2019-11-28 17:32:56,456 INFO L78 Accepts]: Start accepts. Automaton has 2416 states and 2812 transitions. Word has length 183 [2019-11-28 17:32:56,456 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:56,456 INFO L462 AbstractCegarLoop]: Abstraction has 2416 states and 2812 transitions. [2019-11-28 17:32:56,456 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:56,456 INFO L276 IsEmpty]: Start isEmpty. Operand 2416 states and 2812 transitions. [2019-11-28 17:32:56,458 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 184 [2019-11-28 17:32:56,458 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:56,458 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:56,458 INFO L410 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:56,458 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:56,458 INFO L82 PathProgramCache]: Analyzing trace with hash 1256160142, now seen corresponding path program 1 times [2019-11-28 17:32:56,459 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:56,459 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1828121971] [2019-11-28 17:32:56,459 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:56,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:56,517 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 93 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-11-28 17:32:56,518 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1828121971] [2019-11-28 17:32:56,518 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:56,518 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:56,519 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2021604437] [2019-11-28 17:32:56,519 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:56,519 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:56,520 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:56,520 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:56,520 INFO L87 Difference]: Start difference. First operand 2416 states and 2812 transitions. Second operand 3 states. [2019-11-28 17:32:56,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:56,633 INFO L93 Difference]: Finished difference Result 3364 states and 3884 transitions. [2019-11-28 17:32:56,634 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:56,634 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 183 [2019-11-28 17:32:56,635 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:56,636 INFO L225 Difference]: With dead ends: 3364 [2019-11-28 17:32:56,636 INFO L226 Difference]: Without dead ends: 1214 [2019-11-28 17:32:56,639 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:56,640 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1214 states. [2019-11-28 17:32:56,727 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1214 to 1192. [2019-11-28 17:32:56,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1192 states. [2019-11-28 17:32:56,729 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1192 states to 1192 states and 1317 transitions. [2019-11-28 17:32:56,730 INFO L78 Accepts]: Start accepts. Automaton has 1192 states and 1317 transitions. Word has length 183 [2019-11-28 17:32:56,730 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:56,731 INFO L462 AbstractCegarLoop]: Abstraction has 1192 states and 1317 transitions. [2019-11-28 17:32:56,731 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:56,731 INFO L276 IsEmpty]: Start isEmpty. Operand 1192 states and 1317 transitions. [2019-11-28 17:32:56,733 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 185 [2019-11-28 17:32:56,733 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:56,734 INFO L410 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:56,734 INFO L410 AbstractCegarLoop]: === Iteration 37 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:56,735 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:56,735 INFO L82 PathProgramCache]: Analyzing trace with hash 1772258692, now seen corresponding path program 1 times [2019-11-28 17:32:56,735 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:56,736 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1575464777] [2019-11-28 17:32:56,736 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:56,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 17:32:56,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 17:32:56,898 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-28 17:32:56,898 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-28 17:32:57,118 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 05:32:57 BoogieIcfgContainer [2019-11-28 17:32:57,118 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-28 17:32:57,118 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-28 17:32:57,118 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-28 17:32:57,119 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-28 17:32:57,119 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 05:32:31" (3/4) ... [2019-11-28 17:32:57,121 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-28 17:32:57,322 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2019-11-28 17:32:57,322 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-28 17:32:57,324 INFO L168 Benchmark]: Toolchain (without parser) took 26821.57 ms. Allocated memory was 1.0 GB in the beginning and 3.3 GB in the end (delta: 2.2 GB). Free memory was 955.0 MB in the beginning and 1.7 GB in the end (delta: -722.4 MB). Peak memory consumption was 1.5 GB. Max. memory is 11.5 GB. [2019-11-28 17:32:57,325 INFO L168 Benchmark]: CDTParser took 0.99 ms. Allocated memory is still 1.0 GB. Free memory is still 981.8 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 17:32:57,325 INFO L168 Benchmark]: CACSL2BoogieTranslator took 482.24 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 142.6 MB). Free memory was 955.0 MB in the beginning and 1.1 GB in the end (delta: -177.6 MB). Peak memory consumption was 27.1 MB. Max. memory is 11.5 GB. [2019-11-28 17:32:57,325 INFO L168 Benchmark]: Boogie Procedure Inliner took 49.81 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 17:32:57,325 INFO L168 Benchmark]: Boogie Preprocessor took 38.18 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.6 MB). Peak memory consumption was 6.6 MB. Max. memory is 11.5 GB. [2019-11-28 17:32:57,326 INFO L168 Benchmark]: RCFGBuilder took 792.72 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 39.2 MB). Peak memory consumption was 39.2 MB. Max. memory is 11.5 GB. [2019-11-28 17:32:57,326 INFO L168 Benchmark]: TraceAbstraction took 25249.35 ms. Allocated memory was 1.2 GB in the beginning and 3.3 GB in the end (delta: 2.1 GB). Free memory was 1.1 GB in the beginning and 1.7 GB in the end (delta: -635.9 MB). Peak memory consumption was 1.5 GB. Max. memory is 11.5 GB. [2019-11-28 17:32:57,326 INFO L168 Benchmark]: Witness Printer took 203.57 ms. Allocated memory is still 3.3 GB. Free memory was 1.7 GB in the beginning and 1.7 GB in the end (delta: 45.2 MB). Peak memory consumption was 45.2 MB. Max. memory is 11.5 GB. [2019-11-28 17:32:57,329 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.99 ms. Allocated memory is still 1.0 GB. Free memory is still 981.8 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 482.24 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 142.6 MB). Free memory was 955.0 MB in the beginning and 1.1 GB in the end (delta: -177.6 MB). Peak memory consumption was 27.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 49.81 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 38.18 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.6 MB). Peak memory consumption was 6.6 MB. Max. memory is 11.5 GB. * RCFGBuilder took 792.72 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 39.2 MB). Peak memory consumption was 39.2 MB. Max. memory is 11.5 GB. * TraceAbstraction took 25249.35 ms. Allocated memory was 1.2 GB in the beginning and 3.3 GB in the end (delta: 2.1 GB). Free memory was 1.1 GB in the beginning and 1.7 GB in the end (delta: -635.9 MB). Peak memory consumption was 1.5 GB. Max. memory is 11.5 GB. * Witness Printer took 203.57 ms. Allocated memory is still 3.3 GB. Free memory was 1.7 GB in the beginning and 1.7 GB in the end (delta: 45.2 MB). Peak memory consumption was 45.2 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 13]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L18] int c ; [L19] int c_t ; [L20] int c_req_up ; [L21] int p_in ; [L22] int p_out ; [L23] int wl_st ; [L24] int c1_st ; [L25] int c2_st ; [L26] int wb_st ; [L27] int r_st ; [L28] int wl_i ; [L29] int c1_i ; [L30] int c2_i ; [L31] int wb_i ; [L32] int r_i ; [L33] int wl_pc ; [L34] int c1_pc ; [L35] int c2_pc ; [L36] int wb_pc ; [L37] int e_e ; [L38] int e_f ; [L39] int e_g ; [L40] int e_c ; [L41] int e_p_in ; [L42] int e_wl ; [L48] int d ; [L49] int data ; [L50] int processed ; [L51] static int t_b ; VAL [c=0, c1_i=0, c1_pc=0, c1_st=0, c2_i=0, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=0, e_e=0, e_f=0, e_g=0, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=0, wb_pc=0, wb_st=0, wl_i=0, wl_pc=0, wl_st=0] [L679] int __retres1 ; [L683] e_wl = 2 [L684] e_c = e_wl [L685] e_g = e_c [L686] e_f = e_g [L687] e_e = e_f [L688] wl_pc = 0 [L689] c1_pc = 0 [L690] c2_pc = 0 [L691] wb_pc = 0 [L692] wb_i = 1 [L693] c2_i = wb_i [L694] c1_i = c2_i [L695] wl_i = c1_i [L696] r_i = 0 [L697] c_req_up = 0 [L698] d = 0 [L699] c = 0 [L390] int kernel_st ; [L393] kernel_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L394] COND FALSE !((int )c_req_up == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L405] COND TRUE (int )wl_i == 1 [L406] wl_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L410] COND TRUE (int )c1_i == 1 [L411] c1_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L415] COND TRUE (int )c2_i == 1 [L416] c2_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L420] COND TRUE (int )wb_i == 1 [L421] wb_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L425] COND FALSE !((int )r_i == 1) [L428] r_st = 2 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L430] COND FALSE !((int )e_f == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L435] COND FALSE !((int )e_g == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L440] COND FALSE !((int )e_e == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L445] COND FALSE !((int )e_c == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L450] COND FALSE !((int )e_wl == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L455] COND FALSE !((int )wl_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L463] COND FALSE !((int )wl_pc == 2) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L473] COND FALSE !((int )c1_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L482] COND FALSE !((int )c2_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L491] COND FALSE !((int )wb_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L500] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L505] COND FALSE !((int )e_e == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L510] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L515] COND FALSE !((int )e_g == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L520] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L525] COND FALSE !((int )e_wl == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L531] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L534] kernel_st = 1 [L276] int tmp ; [L277] int tmp___0 ; [L278] int tmp___1 ; [L279] int tmp___2 ; [L280] int tmp___3 ; VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L284] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L286] COND TRUE (int )wl_st == 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L307] COND TRUE (int )wl_st == 0 [L309] tmp = __VERIFIER_nondet_int() [L311] COND TRUE \read(tmp) [L313] wl_st = 1 [L53] int t ; VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L56] COND TRUE (int )wl_pc == 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L70] wl_st = 2 [L71] wl_pc = 1 [L72] e_wl = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L322] COND TRUE (int )c1_st == 0 [L324] tmp___0 = __VERIFIER_nondet_int() [L326] COND TRUE \read(tmp___0) [L328] c1_st = 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L127] COND TRUE (int )c1_pc == 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L138] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L140] c1_st = 2 [L141] c1_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L337] COND TRUE (int )c2_st == 0 [L339] tmp___1 = __VERIFIER_nondet_int() [L341] COND TRUE \read(tmp___1) [L343] c2_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L172] COND TRUE (int )c2_pc == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L183] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L185] c2_st = 2 [L186] c2_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L352] COND TRUE (int )wb_st == 0 [L354] tmp___2 = __VERIFIER_nondet_int() [L356] COND TRUE \read(tmp___2) [L358] wb_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L217] COND TRUE (int )wb_pc == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L228] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L230] wb_st = 2 [L231] wb_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L367] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L284] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L286] COND FALSE !((int )wl_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L289] COND FALSE !((int )c1_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L292] COND FALSE !((int )c2_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L295] COND FALSE !((int )wb_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L298] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L537] kernel_st = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L538] COND FALSE !((int )c_req_up == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L549] kernel_st = 3 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L550] COND FALSE !((int )e_f == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L555] COND FALSE !((int )e_g == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L560] COND FALSE !((int )e_e == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L565] COND FALSE !((int )e_c == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L570] COND TRUE (int )e_wl == 0 [L571] e_wl = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L575] COND TRUE (int )wl_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L576] COND TRUE (int )e_wl == 1 [L577] wl_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L593] COND TRUE (int )c1_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L594] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L602] COND TRUE (int )c2_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L603] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L611] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L612] COND FALSE !((int )e_g == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L620] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L625] COND FALSE !((int )e_e == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L630] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L635] COND FALSE !((int )e_g == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L640] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L645] COND TRUE (int )e_wl == 1 [L646] e_wl = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L650] COND TRUE (int )wl_st == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L531] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L534] kernel_st = 1 [L276] int tmp ; [L277] int tmp___0 ; [L278] int tmp___1 ; [L279] int tmp___2 ; [L280] int tmp___3 ; VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L284] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L286] COND TRUE (int )wl_st == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L307] COND TRUE (int )wl_st == 0 [L309] tmp = __VERIFIER_nondet_int() [L311] COND TRUE \read(tmp) [L313] wl_st = 1 [L53] int t ; VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L56] COND FALSE !((int )wl_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L59] COND FALSE !((int )wl_pc == 2) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L62] COND TRUE (int )wl_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L77] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L79] t = d [L80] data = d [L81] processed = 0 [L82] e_f = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L83] COND TRUE (int )c1_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L84] COND TRUE (int )e_f == 1 [L85] c1_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L92] COND TRUE (int )c2_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L93] COND TRUE (int )e_f == 1 [L94] c2_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L101] e_f = 2 [L102] wl_st = 2 [L103] wl_pc = 2 [L104] t_b = t VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L322] COND TRUE (int )c1_st == 0 [L324] tmp___0 = __VERIFIER_nondet_int() [L326] COND TRUE \read(tmp___0) [L328] c1_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L127] COND FALSE !((int )c1_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L130] COND TRUE (int )c1_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L145] COND TRUE ! processed [L146] data += 1 [L147] e_g = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L148] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L149] COND TRUE (int )e_g == 1 [L150] wb_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L157] e_g = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L138] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L140] c1_st = 2 [L141] c1_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L337] COND TRUE (int )c2_st == 0 [L339] tmp___1 = __VERIFIER_nondet_int() [L341] COND TRUE \read(tmp___1) [L343] c2_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L172] COND FALSE !((int )c2_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L175] COND TRUE (int )c2_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L190] COND TRUE ! processed [L191] data += 1 [L192] e_g = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L193] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L194] COND TRUE (int )e_g == 1 [L195] wb_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L202] e_g = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L183] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L185] c2_st = 2 [L186] c2_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L352] COND TRUE (int )wb_st == 0 [L354] tmp___2 = __VERIFIER_nondet_int() [L356] COND TRUE \read(tmp___2) [L358] wb_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L217] COND FALSE !((int )wb_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L220] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L235] c_t = data [L236] c_req_up = 1 [L237] processed = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L228] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L230] wb_st = 2 [L231] wb_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L367] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L284] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L286] COND FALSE !((int )wl_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L289] COND FALSE !((int )c1_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L292] COND FALSE !((int )c2_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L295] COND FALSE !((int )wb_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L298] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L537] kernel_st = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L538] COND TRUE (int )c_req_up == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L539] COND TRUE c != c_t [L540] c = c_t [L541] e_c = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L545] c_req_up = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L549] kernel_st = 3 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L550] COND FALSE !((int )e_f == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L555] COND FALSE !((int )e_g == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L560] COND FALSE !((int )e_e == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L565] COND TRUE (int )e_c == 0 [L566] e_c = 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L570] COND FALSE !((int )e_wl == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L575] COND FALSE !((int )wl_pc == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L583] COND TRUE (int )wl_pc == 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L584] COND FALSE !((int )e_e == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L593] COND TRUE (int )c1_pc == 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L594] COND FALSE !((int )e_f == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L602] COND TRUE (int )c2_pc == 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L603] COND FALSE !((int )e_f == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L611] COND TRUE (int )wb_pc == 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L612] COND FALSE !((int )e_g == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L620] COND TRUE (int )e_c == 1 [L621] r_st = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L625] COND FALSE !((int )e_e == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L630] COND FALSE !((int )e_f == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L635] COND FALSE !((int )e_g == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L640] COND TRUE (int )e_c == 1 [L641] e_c = 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L645] COND FALSE !((int )e_wl == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L650] COND FALSE !((int )wl_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L653] COND FALSE !((int )c1_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L656] COND FALSE !((int )c2_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L659] COND FALSE !((int )wb_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L662] COND TRUE (int )r_st == 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L531] COND TRUE 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L534] kernel_st = 1 [L276] int tmp ; [L277] int tmp___0 ; [L278] int tmp___1 ; [L279] int tmp___2 ; [L280] int tmp___3 ; VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L284] COND TRUE 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L286] COND FALSE !((int )wl_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L289] COND FALSE !((int )c1_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L292] COND FALSE !((int )c2_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L295] COND FALSE !((int )wb_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L298] COND TRUE (int )r_st == 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L307] COND FALSE !((int )wl_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L322] COND FALSE !((int )c1_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L337] COND FALSE !((int )c2_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L352] COND FALSE !((int )wb_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L367] COND TRUE (int )r_st == 0 [L369] tmp___3 = __VERIFIER_nondet_int() [L371] COND TRUE \read(tmp___3) [L373] r_st = 1 [L249] d = c [L250] e_e = 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L251] COND FALSE !((int )wl_pc == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L259] COND TRUE (int )wl_pc == 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L260] COND TRUE (int )e_e == 1 [L261] wl_st = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L269] e_e = 2 [L270] r_st = 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L284] COND TRUE 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L286] COND TRUE (int )wl_st == 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L307] COND TRUE (int )wl_st == 0 [L309] tmp = __VERIFIER_nondet_int() [L311] COND TRUE \read(tmp) [L313] wl_st = 1 [L53] int t ; VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L56] COND FALSE !((int )wl_pc == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L59] COND TRUE (int )wl_pc == 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L108] t = t_b VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L109] COND FALSE !(d == t + 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L13] __VERIFIER_error() VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 125 locations, 1 error locations. Result: UNSAFE, OverallTime: 24.9s, OverallIterations: 37, TraceHistogramMax: 6, AutomataDifference: 11.5s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 7566 SDtfs, 5932 SDslu, 4273 SDs, 0 SdLazy, 705 SolverSat, 210 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.9s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 128 GetRequests, 76 SyntacticMatches, 2 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=16725occurred in iteration=19, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 10.7s AutomataMinimizationTime, 36 MinimizatonAttempts, 9031 StatesRemovedByMinimization, 30 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 1.0s InterpolantComputationTime, 3325 NumberOfCodeBlocks, 3325 NumberOfCodeBlocksAsserted, 37 NumberOfCheckSat, 3105 ConstructedInterpolants, 0 QuantifiedInterpolants, 546256 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 36 InterpolantComputations, 36 PerfectInterpolantSequences, 1082/1082 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...