./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/systemc/transmitter.03.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx12G -Xms1G -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/systemc/transmitter.03.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 447c919af4e106e36f468570351956f4c77293d2 .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-11-28 17:32:41,892 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-11-28 17:32:41,895 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-11-28 17:32:41,914 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-11-28 17:32:41,914 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-11-28 17:32:41,916 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-11-28 17:32:41,917 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-11-28 17:32:41,919 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-11-28 17:32:41,921 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-11-28 17:32:41,922 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-11-28 17:32:41,923 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-11-28 17:32:41,924 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-11-28 17:32:41,925 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-11-28 17:32:41,926 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-11-28 17:32:41,927 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-11-28 17:32:41,928 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-11-28 17:32:41,929 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-11-28 17:32:41,930 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-11-28 17:32:41,932 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-11-28 17:32:41,934 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-11-28 17:32:41,937 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-11-28 17:32:41,940 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-11-28 17:32:41,943 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-11-28 17:32:41,944 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-11-28 17:32:41,950 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-11-28 17:32:41,951 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-11-28 17:32:41,951 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-11-28 17:32:41,952 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-11-28 17:32:41,954 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-11-28 17:32:41,955 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-11-28 17:32:41,956 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-11-28 17:32:41,957 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-11-28 17:32:41,958 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-11-28 17:32:41,959 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-11-28 17:32:41,961 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-11-28 17:32:41,964 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-11-28 17:32:41,965 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-11-28 17:32:41,966 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-11-28 17:32:41,966 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-11-28 17:32:41,968 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-11-28 17:32:41,970 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-11-28 17:32:41,971 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-11-28 17:32:41,994 INFO L113 SettingsManager]: Loading preferences was successful [2019-11-28 17:32:41,995 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-11-28 17:32:41,997 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-11-28 17:32:41,997 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-11-28 17:32:41,997 INFO L138 SettingsManager]: * Use SBE=true [2019-11-28 17:32:41,998 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-11-28 17:32:41,998 INFO L138 SettingsManager]: * sizeof long=4 [2019-11-28 17:32:41,998 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-11-28 17:32:41,999 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-11-28 17:32:41,999 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-11-28 17:32:42,000 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-11-28 17:32:42,000 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-11-28 17:32:42,001 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-11-28 17:32:42,001 INFO L138 SettingsManager]: * sizeof long double=12 [2019-11-28 17:32:42,002 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-11-28 17:32:42,002 INFO L138 SettingsManager]: * Use constant arrays=true [2019-11-28 17:32:42,002 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-11-28 17:32:42,003 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-11-28 17:32:42,003 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-11-28 17:32:42,003 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-11-28 17:32:42,004 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-11-28 17:32:42,004 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 17:32:42,005 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-11-28 17:32:42,005 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-11-28 17:32:42,005 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-11-28 17:32:42,006 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-11-28 17:32:42,006 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-11-28 17:32:42,006 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-11-28 17:32:42,006 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-11-28 17:32:42,007 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 447c919af4e106e36f468570351956f4c77293d2 [2019-11-28 17:32:42,353 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-11-28 17:32:42,367 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-11-28 17:32:42,371 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-11-28 17:32:42,373 INFO L271 PluginConnector]: Initializing CDTParser... [2019-11-28 17:32:42,373 INFO L275 PluginConnector]: CDTParser initialized [2019-11-28 17:32:42,374 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.03.cil.c [2019-11-28 17:32:42,438 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8d86b2931/ea2b5d13990a4c3f94ba8073c435f405/FLAG9f6a67976 [2019-11-28 17:32:42,911 INFO L306 CDTParser]: Found 1 translation units. [2019-11-28 17:32:42,912 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.03.cil.c [2019-11-28 17:32:42,924 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8d86b2931/ea2b5d13990a4c3f94ba8073c435f405/FLAG9f6a67976 [2019-11-28 17:32:43,230 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8d86b2931/ea2b5d13990a4c3f94ba8073c435f405 [2019-11-28 17:32:43,233 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-11-28 17:32:43,235 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-11-28 17:32:43,236 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-11-28 17:32:43,236 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-11-28 17:32:43,240 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-11-28 17:32:43,241 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 05:32:43" (1/1) ... [2019-11-28 17:32:43,245 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@24c7a7ad and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:43, skipping insertion in model container [2019-11-28 17:32:43,245 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 05:32:43" (1/1) ... [2019-11-28 17:32:43,253 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-11-28 17:32:43,298 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-11-28 17:32:43,635 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 17:32:43,641 INFO L203 MainTranslator]: Completed pre-run [2019-11-28 17:32:43,771 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-11-28 17:32:43,793 INFO L208 MainTranslator]: Completed translation [2019-11-28 17:32:43,794 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:43 WrapperNode [2019-11-28 17:32:43,794 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-11-28 17:32:43,795 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-11-28 17:32:43,795 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-11-28 17:32:43,795 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-11-28 17:32:43,804 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:43" (1/1) ... [2019-11-28 17:32:43,813 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:43" (1/1) ... [2019-11-28 17:32:43,864 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-11-28 17:32:43,865 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-11-28 17:32:43,865 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-11-28 17:32:43,865 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-11-28 17:32:43,877 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:43" (1/1) ... [2019-11-28 17:32:43,877 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:43" (1/1) ... [2019-11-28 17:32:43,881 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:43" (1/1) ... [2019-11-28 17:32:43,882 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:43" (1/1) ... [2019-11-28 17:32:43,894 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:43" (1/1) ... [2019-11-28 17:32:43,909 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:43" (1/1) ... [2019-11-28 17:32:43,913 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:43" (1/1) ... [2019-11-28 17:32:43,921 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-11-28 17:32:43,922 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-11-28 17:32:43,922 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-11-28 17:32:43,922 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-11-28 17:32:43,923 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:43" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-11-28 17:32:44,006 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-11-28 17:32:44,006 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-11-28 17:32:45,023 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-11-28 17:32:45,023 INFO L287 CfgBuilder]: Removed 119 assume(true) statements. [2019-11-28 17:32:45,025 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 05:32:45 BoogieIcfgContainer [2019-11-28 17:32:45,025 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-11-28 17:32:45,027 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-11-28 17:32:45,027 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-11-28 17:32:45,031 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-11-28 17:32:45,032 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 05:32:43" (1/3) ... [2019-11-28 17:32:45,033 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@406e1010 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 05:32:45, skipping insertion in model container [2019-11-28 17:32:45,033 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 05:32:43" (2/3) ... [2019-11-28 17:32:45,034 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@406e1010 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 05:32:45, skipping insertion in model container [2019-11-28 17:32:45,034 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 05:32:45" (3/3) ... [2019-11-28 17:32:45,036 INFO L109 eAbstractionObserver]: Analyzing ICFG transmitter.03.cil.c [2019-11-28 17:32:45,046 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-11-28 17:32:45,055 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-11-28 17:32:45,069 INFO L249 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2019-11-28 17:32:45,114 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-11-28 17:32:45,115 INFO L374 AbstractCegarLoop]: Hoare is true [2019-11-28 17:32:45,115 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-11-28 17:32:45,115 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-11-28 17:32:45,116 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-11-28 17:32:45,116 INFO L378 AbstractCegarLoop]: Difference is false [2019-11-28 17:32:45,117 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-11-28 17:32:45,117 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-11-28 17:32:45,149 INFO L276 IsEmpty]: Start isEmpty. Operand 276 states. [2019-11-28 17:32:45,160 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-28 17:32:45,161 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:45,163 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:45,163 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:45,171 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:45,172 INFO L82 PathProgramCache]: Analyzing trace with hash -1838342379, now seen corresponding path program 1 times [2019-11-28 17:32:45,181 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:45,182 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1361739530] [2019-11-28 17:32:45,182 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:45,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:45,347 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:45,348 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1361739530] [2019-11-28 17:32:45,349 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:45,349 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:45,351 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2086764777] [2019-11-28 17:32:45,357 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:45,358 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:45,368 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:45,369 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:45,370 INFO L87 Difference]: Start difference. First operand 276 states. Second operand 3 states. [2019-11-28 17:32:45,450 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:45,451 INFO L93 Difference]: Finished difference Result 547 states and 857 transitions. [2019-11-28 17:32:45,451 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:45,453 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-28 17:32:45,454 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:45,475 INFO L225 Difference]: With dead ends: 547 [2019-11-28 17:32:45,475 INFO L226 Difference]: Without dead ends: 272 [2019-11-28 17:32:45,480 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:45,502 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 272 states. [2019-11-28 17:32:45,555 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 272 to 272. [2019-11-28 17:32:45,557 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 272 states. [2019-11-28 17:32:45,562 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 272 states to 272 states and 412 transitions. [2019-11-28 17:32:45,564 INFO L78 Accepts]: Start accepts. Automaton has 272 states and 412 transitions. Word has length 61 [2019-11-28 17:32:45,565 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:45,565 INFO L462 AbstractCegarLoop]: Abstraction has 272 states and 412 transitions. [2019-11-28 17:32:45,565 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:45,565 INFO L276 IsEmpty]: Start isEmpty. Operand 272 states and 412 transitions. [2019-11-28 17:32:45,568 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-28 17:32:45,568 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:45,569 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:45,569 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:45,569 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:45,570 INFO L82 PathProgramCache]: Analyzing trace with hash 1195707667, now seen corresponding path program 1 times [2019-11-28 17:32:45,570 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:45,571 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [807130280] [2019-11-28 17:32:45,571 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:45,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:45,645 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:45,645 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [807130280] [2019-11-28 17:32:45,646 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:45,646 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 17:32:45,647 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2011191695] [2019-11-28 17:32:45,653 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:45,653 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:45,654 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:45,654 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:45,654 INFO L87 Difference]: Start difference. First operand 272 states and 412 transitions. Second operand 3 states. [2019-11-28 17:32:45,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:45,807 INFO L93 Difference]: Finished difference Result 730 states and 1104 transitions. [2019-11-28 17:32:45,808 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:45,808 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-28 17:32:45,808 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:45,813 INFO L225 Difference]: With dead ends: 730 [2019-11-28 17:32:45,813 INFO L226 Difference]: Without dead ends: 466 [2019-11-28 17:32:45,816 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:45,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 466 states. [2019-11-28 17:32:45,854 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 466 to 464. [2019-11-28 17:32:45,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-11-28 17:32:45,860 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 694 transitions. [2019-11-28 17:32:45,860 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 694 transitions. Word has length 61 [2019-11-28 17:32:45,861 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:45,861 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 694 transitions. [2019-11-28 17:32:45,862 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:45,862 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 694 transitions. [2019-11-28 17:32:45,865 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-28 17:32:45,868 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:45,868 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:45,869 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:45,869 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:45,869 INFO L82 PathProgramCache]: Analyzing trace with hash 266288339, now seen corresponding path program 1 times [2019-11-28 17:32:45,870 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:45,870 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1242277963] [2019-11-28 17:32:45,870 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:45,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:45,947 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:45,948 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1242277963] [2019-11-28 17:32:45,948 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:45,949 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 17:32:45,950 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1991246521] [2019-11-28 17:32:45,950 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:45,951 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:45,952 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:45,952 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:45,952 INFO L87 Difference]: Start difference. First operand 464 states and 694 transitions. Second operand 3 states. [2019-11-28 17:32:45,998 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:45,999 INFO L93 Difference]: Finished difference Result 919 states and 1375 transitions. [2019-11-28 17:32:45,999 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:46,001 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-28 17:32:46,006 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:46,010 INFO L225 Difference]: With dead ends: 919 [2019-11-28 17:32:46,010 INFO L226 Difference]: Without dead ends: 464 [2019-11-28 17:32:46,011 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:46,014 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-11-28 17:32:46,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-11-28 17:32:46,041 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-11-28 17:32:46,044 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 686 transitions. [2019-11-28 17:32:46,044 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 686 transitions. Word has length 61 [2019-11-28 17:32:46,044 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:46,044 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 686 transitions. [2019-11-28 17:32:46,045 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:46,045 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 686 transitions. [2019-11-28 17:32:46,046 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-28 17:32:46,046 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:46,047 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:46,047 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:46,047 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:46,047 INFO L82 PathProgramCache]: Analyzing trace with hash 710189013, now seen corresponding path program 1 times [2019-11-28 17:32:46,048 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:46,048 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [631125615] [2019-11-28 17:32:46,048 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:46,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:46,096 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:46,097 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [631125615] [2019-11-28 17:32:46,097 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:46,097 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 17:32:46,097 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1612902336] [2019-11-28 17:32:46,098 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:46,098 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:46,098 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:46,099 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:46,099 INFO L87 Difference]: Start difference. First operand 464 states and 686 transitions. Second operand 3 states. [2019-11-28 17:32:46,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:46,143 INFO L93 Difference]: Finished difference Result 918 states and 1358 transitions. [2019-11-28 17:32:46,144 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:46,144 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-28 17:32:46,144 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:46,147 INFO L225 Difference]: With dead ends: 918 [2019-11-28 17:32:46,147 INFO L226 Difference]: Without dead ends: 464 [2019-11-28 17:32:46,149 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:46,150 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-11-28 17:32:46,173 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-11-28 17:32:46,173 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-11-28 17:32:46,175 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 678 transitions. [2019-11-28 17:32:46,175 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 678 transitions. Word has length 61 [2019-11-28 17:32:46,176 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:46,176 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 678 transitions. [2019-11-28 17:32:46,176 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:46,176 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 678 transitions. [2019-11-28 17:32:46,177 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-28 17:32:46,178 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:46,178 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:46,178 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:46,178 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:46,179 INFO L82 PathProgramCache]: Analyzing trace with hash -1623736427, now seen corresponding path program 1 times [2019-11-28 17:32:46,179 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:46,179 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1796859229] [2019-11-28 17:32:46,180 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:46,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:46,238 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:46,240 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1796859229] [2019-11-28 17:32:46,240 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:46,240 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 17:32:46,241 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [399611729] [2019-11-28 17:32:46,241 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:46,241 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:46,242 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:46,243 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:46,244 INFO L87 Difference]: Start difference. First operand 464 states and 678 transitions. Second operand 3 states. [2019-11-28 17:32:46,288 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:46,288 INFO L93 Difference]: Finished difference Result 917 states and 1341 transitions. [2019-11-28 17:32:46,289 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:46,289 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-28 17:32:46,289 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:46,292 INFO L225 Difference]: With dead ends: 917 [2019-11-28 17:32:46,292 INFO L226 Difference]: Without dead ends: 464 [2019-11-28 17:32:46,294 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:46,295 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-11-28 17:32:46,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-11-28 17:32:46,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-11-28 17:32:46,319 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 670 transitions. [2019-11-28 17:32:46,319 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 670 transitions. Word has length 61 [2019-11-28 17:32:46,319 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:46,320 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 670 transitions. [2019-11-28 17:32:46,320 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:46,320 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 670 transitions. [2019-11-28 17:32:46,322 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-28 17:32:46,323 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:46,323 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:46,323 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:46,323 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:46,324 INFO L82 PathProgramCache]: Analyzing trace with hash -175003691, now seen corresponding path program 1 times [2019-11-28 17:32:46,324 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:46,324 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1943504190] [2019-11-28 17:32:46,325 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:46,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:46,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:46,399 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1943504190] [2019-11-28 17:32:46,400 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:46,401 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 17:32:46,401 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [910774533] [2019-11-28 17:32:46,402 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:46,402 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:46,402 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:46,403 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:46,403 INFO L87 Difference]: Start difference. First operand 464 states and 670 transitions. Second operand 3 states. [2019-11-28 17:32:46,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:46,475 INFO L93 Difference]: Finished difference Result 916 states and 1324 transitions. [2019-11-28 17:32:46,476 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:46,476 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-28 17:32:46,476 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:46,479 INFO L225 Difference]: With dead ends: 916 [2019-11-28 17:32:46,479 INFO L226 Difference]: Without dead ends: 464 [2019-11-28 17:32:46,481 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:46,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-11-28 17:32:46,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-11-28 17:32:46,508 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-11-28 17:32:46,510 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 654 transitions. [2019-11-28 17:32:46,510 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 654 transitions. Word has length 61 [2019-11-28 17:32:46,510 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:46,511 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 654 transitions. [2019-11-28 17:32:46,511 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:46,511 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 654 transitions. [2019-11-28 17:32:46,513 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-28 17:32:46,513 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:46,514 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:46,518 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:46,518 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:46,519 INFO L82 PathProgramCache]: Analyzing trace with hash -1945036492, now seen corresponding path program 1 times [2019-11-28 17:32:46,519 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:46,520 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1583389484] [2019-11-28 17:32:46,520 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:46,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:46,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:46,590 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1583389484] [2019-11-28 17:32:46,590 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:46,590 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 17:32:46,591 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1073000895] [2019-11-28 17:32:46,591 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:46,597 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:46,597 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:46,597 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:46,598 INFO L87 Difference]: Start difference. First operand 464 states and 654 transitions. Second operand 3 states. [2019-11-28 17:32:46,683 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:46,684 INFO L93 Difference]: Finished difference Result 914 states and 1289 transitions. [2019-11-28 17:32:46,684 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:46,685 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-28 17:32:46,685 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:46,689 INFO L225 Difference]: With dead ends: 914 [2019-11-28 17:32:46,689 INFO L226 Difference]: Without dead ends: 464 [2019-11-28 17:32:46,691 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:46,692 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-11-28 17:32:46,719 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-11-28 17:32:46,719 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-11-28 17:32:46,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 638 transitions. [2019-11-28 17:32:46,722 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 638 transitions. Word has length 61 [2019-11-28 17:32:46,723 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:46,723 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 638 transitions. [2019-11-28 17:32:46,723 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:46,723 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 638 transitions. [2019-11-28 17:32:46,724 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-28 17:32:46,724 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:46,725 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:46,725 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:46,725 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:46,726 INFO L82 PathProgramCache]: Analyzing trace with hash -1902661357, now seen corresponding path program 1 times [2019-11-28 17:32:46,726 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:46,727 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [780750331] [2019-11-28 17:32:46,727 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:46,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:46,843 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:46,844 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [780750331] [2019-11-28 17:32:46,844 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:46,845 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 17:32:46,845 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [482827288] [2019-11-28 17:32:46,846 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:46,846 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:46,847 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:46,847 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:46,847 INFO L87 Difference]: Start difference. First operand 464 states and 638 transitions. Second operand 3 states. [2019-11-28 17:32:46,935 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:46,936 INFO L93 Difference]: Finished difference Result 915 states and 1259 transitions. [2019-11-28 17:32:46,937 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:46,937 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-28 17:32:46,938 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:46,941 INFO L225 Difference]: With dead ends: 915 [2019-11-28 17:32:46,942 INFO L226 Difference]: Without dead ends: 464 [2019-11-28 17:32:46,943 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:46,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2019-11-28 17:32:46,978 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2019-11-28 17:32:46,979 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2019-11-28 17:32:46,981 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 622 transitions. [2019-11-28 17:32:46,981 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 622 transitions. Word has length 61 [2019-11-28 17:32:46,982 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:46,982 INFO L462 AbstractCegarLoop]: Abstraction has 464 states and 622 transitions. [2019-11-28 17:32:46,982 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:46,982 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 622 transitions. [2019-11-28 17:32:46,983 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-11-28 17:32:46,983 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:46,983 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:46,983 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:46,984 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:46,984 INFO L82 PathProgramCache]: Analyzing trace with hash 398161233, now seen corresponding path program 1 times [2019-11-28 17:32:46,984 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:46,985 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [206366565] [2019-11-28 17:32:46,985 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:47,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:47,053 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:47,053 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [206366565] [2019-11-28 17:32:47,054 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:47,054 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:47,058 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2058121126] [2019-11-28 17:32:47,059 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:47,059 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:47,059 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:47,061 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:47,062 INFO L87 Difference]: Start difference. First operand 464 states and 622 transitions. Second operand 3 states. [2019-11-28 17:32:47,205 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:47,206 INFO L93 Difference]: Finished difference Result 1299 states and 1732 transitions. [2019-11-28 17:32:47,206 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:47,206 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 61 [2019-11-28 17:32:47,207 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:47,211 INFO L225 Difference]: With dead ends: 1299 [2019-11-28 17:32:47,211 INFO L226 Difference]: Without dead ends: 884 [2019-11-28 17:32:47,213 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:47,214 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 884 states. [2019-11-28 17:32:47,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 884 to 834. [2019-11-28 17:32:47,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 834 states. [2019-11-28 17:32:47,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 834 states to 834 states and 1099 transitions. [2019-11-28 17:32:47,263 INFO L78 Accepts]: Start accepts. Automaton has 834 states and 1099 transitions. Word has length 61 [2019-11-28 17:32:47,265 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:47,265 INFO L462 AbstractCegarLoop]: Abstraction has 834 states and 1099 transitions. [2019-11-28 17:32:47,265 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:47,265 INFO L276 IsEmpty]: Start isEmpty. Operand 834 states and 1099 transitions. [2019-11-28 17:32:47,266 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2019-11-28 17:32:47,266 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:47,266 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:47,266 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:47,267 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:47,267 INFO L82 PathProgramCache]: Analyzing trace with hash -276756042, now seen corresponding path program 1 times [2019-11-28 17:32:47,267 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:47,267 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [86428638] [2019-11-28 17:32:47,268 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:47,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:47,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:47,313 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [86428638] [2019-11-28 17:32:47,314 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:47,314 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:47,314 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [721034746] [2019-11-28 17:32:47,314 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:47,315 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:47,315 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:47,315 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:47,316 INFO L87 Difference]: Start difference. First operand 834 states and 1099 transitions. Second operand 3 states. [2019-11-28 17:32:47,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:47,436 INFO L93 Difference]: Finished difference Result 2234 states and 2945 transitions. [2019-11-28 17:32:47,436 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:47,437 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 62 [2019-11-28 17:32:47,437 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:47,444 INFO L225 Difference]: With dead ends: 2234 [2019-11-28 17:32:47,445 INFO L226 Difference]: Without dead ends: 1494 [2019-11-28 17:32:47,447 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:47,449 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1494 states. [2019-11-28 17:32:47,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1494 to 1424. [2019-11-28 17:32:47,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1424 states. [2019-11-28 17:32:47,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1424 states to 1424 states and 1862 transitions. [2019-11-28 17:32:47,527 INFO L78 Accepts]: Start accepts. Automaton has 1424 states and 1862 transitions. Word has length 62 [2019-11-28 17:32:47,529 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:47,530 INFO L462 AbstractCegarLoop]: Abstraction has 1424 states and 1862 transitions. [2019-11-28 17:32:47,530 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:47,530 INFO L276 IsEmpty]: Start isEmpty. Operand 1424 states and 1862 transitions. [2019-11-28 17:32:47,531 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-11-28 17:32:47,531 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:47,531 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:47,532 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:47,532 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:47,532 INFO L82 PathProgramCache]: Analyzing trace with hash -2032591659, now seen corresponding path program 1 times [2019-11-28 17:32:47,532 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:47,533 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [232262271] [2019-11-28 17:32:47,533 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:47,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:47,582 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:47,582 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [232262271] [2019-11-28 17:32:47,582 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:47,582 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:47,583 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [78474075] [2019-11-28 17:32:47,583 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:47,584 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:47,584 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:47,584 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:47,584 INFO L87 Difference]: Start difference. First operand 1424 states and 1862 transitions. Second operand 3 states. [2019-11-28 17:32:47,751 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:47,751 INFO L93 Difference]: Finished difference Result 3972 states and 5180 transitions. [2019-11-28 17:32:47,751 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:47,752 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 63 [2019-11-28 17:32:47,752 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:47,765 INFO L225 Difference]: With dead ends: 3972 [2019-11-28 17:32:47,765 INFO L226 Difference]: Without dead ends: 2642 [2019-11-28 17:32:47,768 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:47,772 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2642 states. [2019-11-28 17:32:47,886 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2642 to 2560. [2019-11-28 17:32:47,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2560 states. [2019-11-28 17:32:47,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2560 states to 2560 states and 3314 transitions. [2019-11-28 17:32:47,895 INFO L78 Accepts]: Start accepts. Automaton has 2560 states and 3314 transitions. Word has length 63 [2019-11-28 17:32:47,896 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:47,896 INFO L462 AbstractCegarLoop]: Abstraction has 2560 states and 3314 transitions. [2019-11-28 17:32:47,896 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:47,896 INFO L276 IsEmpty]: Start isEmpty. Operand 2560 states and 3314 transitions. [2019-11-28 17:32:47,898 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2019-11-28 17:32:47,898 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:47,898 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:47,898 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:47,899 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:47,899 INFO L82 PathProgramCache]: Analyzing trace with hash -1324102959, now seen corresponding path program 1 times [2019-11-28 17:32:47,899 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:47,899 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [274323586] [2019-11-28 17:32:47,900 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:47,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:47,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:47,921 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [274323586] [2019-11-28 17:32:47,921 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:47,921 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:47,921 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [553573707] [2019-11-28 17:32:47,922 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:47,922 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:47,923 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:47,923 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:47,923 INFO L87 Difference]: Start difference. First operand 2560 states and 3314 transitions. Second operand 3 states. [2019-11-28 17:32:48,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:48,043 INFO L93 Difference]: Finished difference Result 4968 states and 6441 transitions. [2019-11-28 17:32:48,044 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:48,044 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 63 [2019-11-28 17:32:48,044 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:48,056 INFO L225 Difference]: With dead ends: 4968 [2019-11-28 17:32:48,057 INFO L226 Difference]: Without dead ends: 2474 [2019-11-28 17:32:48,061 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:48,065 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2474 states. [2019-11-28 17:32:48,168 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2474 to 2474. [2019-11-28 17:32:48,168 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2474 states. [2019-11-28 17:32:48,176 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2474 states to 2474 states and 3208 transitions. [2019-11-28 17:32:48,176 INFO L78 Accepts]: Start accepts. Automaton has 2474 states and 3208 transitions. Word has length 63 [2019-11-28 17:32:48,177 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:48,177 INFO L462 AbstractCegarLoop]: Abstraction has 2474 states and 3208 transitions. [2019-11-28 17:32:48,177 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:48,177 INFO L276 IsEmpty]: Start isEmpty. Operand 2474 states and 3208 transitions. [2019-11-28 17:32:48,178 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2019-11-28 17:32:48,179 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:48,179 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:48,179 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:48,179 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:48,180 INFO L82 PathProgramCache]: Analyzing trace with hash -1607983393, now seen corresponding path program 1 times [2019-11-28 17:32:48,180 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:48,180 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [702588837] [2019-11-28 17:32:48,180 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:48,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:48,219 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:48,220 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [702588837] [2019-11-28 17:32:48,220 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:48,220 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 17:32:48,220 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1288648438] [2019-11-28 17:32:48,221 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:48,222 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:48,222 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:48,222 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:48,223 INFO L87 Difference]: Start difference. First operand 2474 states and 3208 transitions. Second operand 3 states. [2019-11-28 17:32:48,537 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:48,538 INFO L93 Difference]: Finished difference Result 7190 states and 9333 transitions. [2019-11-28 17:32:48,538 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:48,539 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 64 [2019-11-28 17:32:48,539 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:48,566 INFO L225 Difference]: With dead ends: 7190 [2019-11-28 17:32:48,567 INFO L226 Difference]: Without dead ends: 4786 [2019-11-28 17:32:48,572 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:48,579 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4786 states. [2019-11-28 17:32:48,815 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4786 to 4754. [2019-11-28 17:32:48,816 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4754 states. [2019-11-28 17:32:48,834 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4754 states to 4754 states and 6114 transitions. [2019-11-28 17:32:48,835 INFO L78 Accepts]: Start accepts. Automaton has 4754 states and 6114 transitions. Word has length 64 [2019-11-28 17:32:48,835 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:48,835 INFO L462 AbstractCegarLoop]: Abstraction has 4754 states and 6114 transitions. [2019-11-28 17:32:48,836 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:48,836 INFO L276 IsEmpty]: Start isEmpty. Operand 4754 states and 6114 transitions. [2019-11-28 17:32:48,839 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2019-11-28 17:32:48,839 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:48,839 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:48,840 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:48,840 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:48,840 INFO L82 PathProgramCache]: Analyzing trace with hash 93244939, now seen corresponding path program 1 times [2019-11-28 17:32:48,841 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:48,849 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1539327441] [2019-11-28 17:32:48,850 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:48,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:48,902 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:48,903 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1539327441] [2019-11-28 17:32:48,904 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:48,904 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:48,905 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1183267137] [2019-11-28 17:32:48,905 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:48,905 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:48,906 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:48,906 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:48,906 INFO L87 Difference]: Start difference. First operand 4754 states and 6114 transitions. Second operand 3 states. [2019-11-28 17:32:49,326 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:49,326 INFO L93 Difference]: Finished difference Result 14046 states and 18043 transitions. [2019-11-28 17:32:49,327 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:49,328 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 81 [2019-11-28 17:32:49,329 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:49,388 INFO L225 Difference]: With dead ends: 14046 [2019-11-28 17:32:49,388 INFO L226 Difference]: Without dead ends: 9384 [2019-11-28 17:32:49,399 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:49,418 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9384 states. [2019-11-28 17:32:49,932 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9384 to 9384. [2019-11-28 17:32:49,933 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9384 states. [2019-11-28 17:32:49,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9384 states to 9384 states and 11994 transitions. [2019-11-28 17:32:49,970 INFO L78 Accepts]: Start accepts. Automaton has 9384 states and 11994 transitions. Word has length 81 [2019-11-28 17:32:49,970 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:49,971 INFO L462 AbstractCegarLoop]: Abstraction has 9384 states and 11994 transitions. [2019-11-28 17:32:49,971 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:49,971 INFO L276 IsEmpty]: Start isEmpty. Operand 9384 states and 11994 transitions. [2019-11-28 17:32:49,981 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-11-28 17:32:49,982 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:49,982 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:49,983 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:49,983 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:49,983 INFO L82 PathProgramCache]: Analyzing trace with hash -447123663, now seen corresponding path program 1 times [2019-11-28 17:32:49,984 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:49,984 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [884162572] [2019-11-28 17:32:49,984 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:50,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:50,129 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2019-11-28 17:32:50,130 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [884162572] [2019-11-28 17:32:50,130 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:50,130 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 17:32:50,131 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [348064582] [2019-11-28 17:32:50,132 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:50,132 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:50,132 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:50,132 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:50,133 INFO L87 Difference]: Start difference. First operand 9384 states and 11994 transitions. Second operand 3 states. [2019-11-28 17:32:50,708 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:50,708 INFO L93 Difference]: Finished difference Result 22768 states and 29084 transitions. [2019-11-28 17:32:50,709 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:50,709 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 110 [2019-11-28 17:32:50,709 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:50,773 INFO L225 Difference]: With dead ends: 22768 [2019-11-28 17:32:50,774 INFO L226 Difference]: Without dead ends: 13486 [2019-11-28 17:32:50,791 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:50,810 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13486 states. [2019-11-28 17:32:51,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13486 to 13420. [2019-11-28 17:32:51,545 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13420 states. [2019-11-28 17:32:51,580 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13420 states to 13420 states and 17034 transitions. [2019-11-28 17:32:51,581 INFO L78 Accepts]: Start accepts. Automaton has 13420 states and 17034 transitions. Word has length 110 [2019-11-28 17:32:51,581 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:51,581 INFO L462 AbstractCegarLoop]: Abstraction has 13420 states and 17034 transitions. [2019-11-28 17:32:51,582 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:51,582 INFO L276 IsEmpty]: Start isEmpty. Operand 13420 states and 17034 transitions. [2019-11-28 17:32:51,594 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-11-28 17:32:51,595 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:51,595 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:51,596 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:51,596 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:51,596 INFO L82 PathProgramCache]: Analyzing trace with hash -2122456675, now seen corresponding path program 1 times [2019-11-28 17:32:51,597 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:51,597 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [385129777] [2019-11-28 17:32:51,597 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:51,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:51,655 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2019-11-28 17:32:51,656 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [385129777] [2019-11-28 17:32:51,658 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:51,658 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-11-28 17:32:51,659 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [540953534] [2019-11-28 17:32:51,659 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:51,659 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:51,660 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:51,660 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:51,660 INFO L87 Difference]: Start difference. First operand 13420 states and 17034 transitions. Second operand 3 states. [2019-11-28 17:32:52,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:52,381 INFO L93 Difference]: Finished difference Result 32624 states and 41352 transitions. [2019-11-28 17:32:52,381 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:32:52,381 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 110 [2019-11-28 17:32:52,382 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:52,427 INFO L225 Difference]: With dead ends: 32624 [2019-11-28 17:32:52,428 INFO L226 Difference]: Without dead ends: 19278 [2019-11-28 17:32:52,454 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:52,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19278 states. [2019-11-28 17:32:53,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19278 to 19180. [2019-11-28 17:32:53,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19180 states. [2019-11-28 17:32:53,477 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19180 states to 19180 states and 24146 transitions. [2019-11-28 17:32:53,478 INFO L78 Accepts]: Start accepts. Automaton has 19180 states and 24146 transitions. Word has length 110 [2019-11-28 17:32:53,479 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:53,479 INFO L462 AbstractCegarLoop]: Abstraction has 19180 states and 24146 transitions. [2019-11-28 17:32:53,479 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:32:53,479 INFO L276 IsEmpty]: Start isEmpty. Operand 19180 states and 24146 transitions. [2019-11-28 17:32:53,493 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-11-28 17:32:53,494 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:53,494 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:53,495 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:53,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:53,495 INFO L82 PathProgramCache]: Analyzing trace with hash -4233773, now seen corresponding path program 1 times [2019-11-28 17:32:53,495 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:53,496 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1983796490] [2019-11-28 17:32:53,496 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:53,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:53,556 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-28 17:32:53,557 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1983796490] [2019-11-28 17:32:53,557 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:53,557 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 17:32:53,558 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1569515471] [2019-11-28 17:32:53,558 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 17:32:53,558 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:53,559 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 17:32:53,559 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:32:53,559 INFO L87 Difference]: Start difference. First operand 19180 states and 24146 transitions. Second operand 5 states. [2019-11-28 17:32:55,044 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:55,045 INFO L93 Difference]: Finished difference Result 47102 states and 59685 transitions. [2019-11-28 17:32:55,045 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 17:32:55,046 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 110 [2019-11-28 17:32:55,046 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:55,125 INFO L225 Difference]: With dead ends: 47102 [2019-11-28 17:32:55,125 INFO L226 Difference]: Without dead ends: 28012 [2019-11-28 17:32:55,161 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-28 17:32:55,207 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28012 states. [2019-11-28 17:32:56,303 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28012 to 19324. [2019-11-28 17:32:56,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19324 states. [2019-11-28 17:32:56,365 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19324 states to 19324 states and 23950 transitions. [2019-11-28 17:32:56,366 INFO L78 Accepts]: Start accepts. Automaton has 19324 states and 23950 transitions. Word has length 110 [2019-11-28 17:32:56,366 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:56,367 INFO L462 AbstractCegarLoop]: Abstraction has 19324 states and 23950 transitions. [2019-11-28 17:32:56,367 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 17:32:56,367 INFO L276 IsEmpty]: Start isEmpty. Operand 19324 states and 23950 transitions. [2019-11-28 17:32:56,392 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-11-28 17:32:56,393 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:56,393 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:56,393 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:56,394 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:56,394 INFO L82 PathProgramCache]: Analyzing trace with hash 2012797655, now seen corresponding path program 1 times [2019-11-28 17:32:56,395 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:56,395 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1311791417] [2019-11-28 17:32:56,395 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:56,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:56,502 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-28 17:32:56,503 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1311791417] [2019-11-28 17:32:56,503 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:56,504 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 17:32:56,504 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [937694072] [2019-11-28 17:32:56,505 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 17:32:56,506 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:56,506 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 17:32:56,507 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:32:56,507 INFO L87 Difference]: Start difference. First operand 19324 states and 23950 transitions. Second operand 5 states. [2019-11-28 17:32:58,702 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:32:58,703 INFO L93 Difference]: Finished difference Result 45442 states and 56677 transitions. [2019-11-28 17:32:58,704 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 17:32:58,704 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 110 [2019-11-28 17:32:58,704 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:32:58,763 INFO L225 Difference]: With dead ends: 45442 [2019-11-28 17:32:58,763 INFO L226 Difference]: Without dead ends: 26232 [2019-11-28 17:32:58,787 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-28 17:32:58,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26232 states. [2019-11-28 17:32:59,707 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26232 to 19420. [2019-11-28 17:32:59,707 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19420 states. [2019-11-28 17:32:59,747 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19420 states to 19420 states and 23690 transitions. [2019-11-28 17:32:59,748 INFO L78 Accepts]: Start accepts. Automaton has 19420 states and 23690 transitions. Word has length 110 [2019-11-28 17:32:59,748 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:32:59,748 INFO L462 AbstractCegarLoop]: Abstraction has 19420 states and 23690 transitions. [2019-11-28 17:32:59,749 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 17:32:59,749 INFO L276 IsEmpty]: Start isEmpty. Operand 19420 states and 23690 transitions. [2019-11-28 17:32:59,763 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-11-28 17:32:59,763 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:32:59,764 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:32:59,764 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:32:59,764 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:32:59,765 INFO L82 PathProgramCache]: Analyzing trace with hash 564093659, now seen corresponding path program 1 times [2019-11-28 17:32:59,765 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:32:59,765 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1140866551] [2019-11-28 17:32:59,765 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:32:59,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:32:59,807 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:32:59,808 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1140866551] [2019-11-28 17:32:59,808 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:32:59,808 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:32:59,808 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [365174712] [2019-11-28 17:32:59,809 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:32:59,810 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:32:59,810 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:32:59,810 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:32:59,810 INFO L87 Difference]: Start difference. First operand 19420 states and 23690 transitions. Second operand 3 states. [2019-11-28 17:33:01,010 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:33:01,011 INFO L93 Difference]: Finished difference Result 29198 states and 35739 transitions. [2019-11-28 17:33:01,011 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:33:01,012 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 110 [2019-11-28 17:33:01,012 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:33:01,055 INFO L225 Difference]: With dead ends: 29198 [2019-11-28 17:33:01,056 INFO L226 Difference]: Without dead ends: 19420 [2019-11-28 17:33:01,070 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:33:01,090 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19420 states. [2019-11-28 17:33:01,860 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19420 to 19350. [2019-11-28 17:33:01,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19350 states. [2019-11-28 17:33:01,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19350 states to 19350 states and 23356 transitions. [2019-11-28 17:33:01,895 INFO L78 Accepts]: Start accepts. Automaton has 19350 states and 23356 transitions. Word has length 110 [2019-11-28 17:33:01,895 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:33:01,895 INFO L462 AbstractCegarLoop]: Abstraction has 19350 states and 23356 transitions. [2019-11-28 17:33:01,895 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:33:01,896 INFO L276 IsEmpty]: Start isEmpty. Operand 19350 states and 23356 transitions. [2019-11-28 17:33:01,906 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2019-11-28 17:33:01,907 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:33:01,907 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:33:01,907 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:33:01,908 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:33:01,908 INFO L82 PathProgramCache]: Analyzing trace with hash 770898653, now seen corresponding path program 1 times [2019-11-28 17:33:01,908 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:33:01,908 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [520398193] [2019-11-28 17:33:01,909 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:33:01,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:33:01,978 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-28 17:33:01,979 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [520398193] [2019-11-28 17:33:01,979 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:33:01,979 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 17:33:01,980 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [260393833] [2019-11-28 17:33:01,980 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 17:33:01,981 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:33:01,981 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 17:33:01,981 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:33:01,981 INFO L87 Difference]: Start difference. First operand 19350 states and 23356 transitions. Second operand 5 states. [2019-11-28 17:33:03,446 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:33:03,446 INFO L93 Difference]: Finished difference Result 37116 states and 45101 transitions. [2019-11-28 17:33:03,447 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 17:33:03,447 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 111 [2019-11-28 17:33:03,447 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:33:03,477 INFO L225 Difference]: With dead ends: 37116 [2019-11-28 17:33:03,477 INFO L226 Difference]: Without dead ends: 17840 [2019-11-28 17:33:03,494 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-28 17:33:03,510 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17840 states. [2019-11-28 17:33:04,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17840 to 13178. [2019-11-28 17:33:04,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13178 states. [2019-11-28 17:33:04,232 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13178 states to 13178 states and 15698 transitions. [2019-11-28 17:33:04,232 INFO L78 Accepts]: Start accepts. Automaton has 13178 states and 15698 transitions. Word has length 111 [2019-11-28 17:33:04,232 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:33:04,232 INFO L462 AbstractCegarLoop]: Abstraction has 13178 states and 15698 transitions. [2019-11-28 17:33:04,233 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 17:33:04,233 INFO L276 IsEmpty]: Start isEmpty. Operand 13178 states and 15698 transitions. [2019-11-28 17:33:04,240 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2019-11-28 17:33:04,241 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:33:04,241 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:33:04,242 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:33:04,242 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:33:04,242 INFO L82 PathProgramCache]: Analyzing trace with hash 273196097, now seen corresponding path program 1 times [2019-11-28 17:33:04,242 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:33:04,243 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1412575146] [2019-11-28 17:33:04,243 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:33:04,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:33:04,280 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 18 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:33:04,282 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1412575146] [2019-11-28 17:33:04,282 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:33:04,282 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:33:04,282 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1228534181] [2019-11-28 17:33:04,283 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:33:04,283 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:33:04,283 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:33:04,284 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:33:04,284 INFO L87 Difference]: Start difference. First operand 13178 states and 15698 transitions. Second operand 3 states. [2019-11-28 17:33:04,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:33:04,823 INFO L93 Difference]: Finished difference Result 21196 states and 25354 transitions. [2019-11-28 17:33:04,823 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:33:04,823 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 113 [2019-11-28 17:33:04,824 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:33:04,841 INFO L225 Difference]: With dead ends: 21196 [2019-11-28 17:33:04,842 INFO L226 Difference]: Without dead ends: 11030 [2019-11-28 17:33:04,856 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:33:04,867 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11030 states. [2019-11-28 17:33:05,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11030 to 11026. [2019-11-28 17:33:05,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11026 states. [2019-11-28 17:33:05,357 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11026 states to 11026 states and 13114 transitions. [2019-11-28 17:33:05,357 INFO L78 Accepts]: Start accepts. Automaton has 11026 states and 13114 transitions. Word has length 113 [2019-11-28 17:33:05,358 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:33:05,358 INFO L462 AbstractCegarLoop]: Abstraction has 11026 states and 13114 transitions. [2019-11-28 17:33:05,358 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:33:05,358 INFO L276 IsEmpty]: Start isEmpty. Operand 11026 states and 13114 transitions. [2019-11-28 17:33:05,365 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 147 [2019-11-28 17:33:05,365 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:33:05,366 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:33:05,366 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:33:05,366 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:33:05,366 INFO L82 PathProgramCache]: Analyzing trace with hash 1857340375, now seen corresponding path program 1 times [2019-11-28 17:33:05,367 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:33:05,367 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1112414022] [2019-11-28 17:33:05,367 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:33:05,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:33:05,410 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:33:05,411 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1112414022] [2019-11-28 17:33:05,411 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:33:05,412 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:33:05,412 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [87265895] [2019-11-28 17:33:05,412 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:33:05,413 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:33:05,413 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:33:05,413 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:33:05,413 INFO L87 Difference]: Start difference. First operand 11026 states and 13114 transitions. Second operand 3 states. [2019-11-28 17:33:05,937 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:33:05,939 INFO L93 Difference]: Finished difference Result 20200 states and 24102 transitions. [2019-11-28 17:33:05,939 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:33:05,939 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 146 [2019-11-28 17:33:05,940 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:33:05,952 INFO L225 Difference]: With dead ends: 20200 [2019-11-28 17:33:05,952 INFO L226 Difference]: Without dead ends: 11030 [2019-11-28 17:33:05,963 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:33:05,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11030 states. [2019-11-28 17:33:06,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11030 to 11026. [2019-11-28 17:33:06,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11026 states. [2019-11-28 17:33:06,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11026 states to 11026 states and 13034 transitions. [2019-11-28 17:33:06,338 INFO L78 Accepts]: Start accepts. Automaton has 11026 states and 13034 transitions. Word has length 146 [2019-11-28 17:33:06,339 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:33:06,339 INFO L462 AbstractCegarLoop]: Abstraction has 11026 states and 13034 transitions. [2019-11-28 17:33:06,339 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:33:06,339 INFO L276 IsEmpty]: Start isEmpty. Operand 11026 states and 13034 transitions. [2019-11-28 17:33:06,347 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2019-11-28 17:33:06,347 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:33:06,348 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:33:06,348 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:33:06,348 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:33:06,348 INFO L82 PathProgramCache]: Analyzing trace with hash 1216535548, now seen corresponding path program 1 times [2019-11-28 17:33:06,349 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:33:06,349 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [817702094] [2019-11-28 17:33:06,349 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:33:06,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:33:06,405 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-28 17:33:06,406 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [817702094] [2019-11-28 17:33:06,406 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:33:06,406 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-11-28 17:33:06,407 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1171280461] [2019-11-28 17:33:06,408 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-11-28 17:33:06,410 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:33:06,410 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-11-28 17:33:06,411 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-11-28 17:33:06,411 INFO L87 Difference]: Start difference. First operand 11026 states and 13034 transitions. Second operand 5 states. [2019-11-28 17:33:07,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:33:07,344 INFO L93 Difference]: Finished difference Result 35306 states and 41589 transitions. [2019-11-28 17:33:07,344 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-11-28 17:33:07,345 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 176 [2019-11-28 17:33:07,345 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:33:07,372 INFO L225 Difference]: With dead ends: 35306 [2019-11-28 17:33:07,372 INFO L226 Difference]: Without dead ends: 24343 [2019-11-28 17:33:07,387 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-11-28 17:33:07,406 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24343 states. [2019-11-28 17:33:07,978 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24343 to 11410. [2019-11-28 17:33:07,979 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11410 states. [2019-11-28 17:33:07,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11410 states to 11410 states and 13328 transitions. [2019-11-28 17:33:07,995 INFO L78 Accepts]: Start accepts. Automaton has 11410 states and 13328 transitions. Word has length 176 [2019-11-28 17:33:07,996 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:33:07,996 INFO L462 AbstractCegarLoop]: Abstraction has 11410 states and 13328 transitions. [2019-11-28 17:33:07,996 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-11-28 17:33:07,996 INFO L276 IsEmpty]: Start isEmpty. Operand 11410 states and 13328 transitions. [2019-11-28 17:33:08,004 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2019-11-28 17:33:08,004 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:33:08,004 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:33:08,005 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:33:08,005 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:33:08,005 INFO L82 PathProgramCache]: Analyzing trace with hash 2104709508, now seen corresponding path program 1 times [2019-11-28 17:33:08,005 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:33:08,006 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1309171883] [2019-11-28 17:33:08,006 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:33:08,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:33:08,090 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:33:08,091 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1309171883] [2019-11-28 17:33:08,091 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:33:08,091 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:33:08,091 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1392974656] [2019-11-28 17:33:08,092 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:33:08,092 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:33:08,092 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:33:08,093 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:33:08,093 INFO L87 Difference]: Start difference. First operand 11410 states and 13328 transitions. Second operand 3 states. [2019-11-28 17:33:09,194 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:33:09,195 INFO L93 Difference]: Finished difference Result 19722 states and 23103 transitions. [2019-11-28 17:33:09,195 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:33:09,195 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 176 [2019-11-28 17:33:09,195 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:33:09,206 INFO L225 Difference]: With dead ends: 19722 [2019-11-28 17:33:09,206 INFO L226 Difference]: Without dead ends: 11442 [2019-11-28 17:33:09,214 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:33:09,222 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11442 states. [2019-11-28 17:33:09,660 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11442 to 11410. [2019-11-28 17:33:09,661 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11410 states. [2019-11-28 17:33:09,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11410 states to 11410 states and 13120 transitions. [2019-11-28 17:33:09,675 INFO L78 Accepts]: Start accepts. Automaton has 11410 states and 13120 transitions. Word has length 176 [2019-11-28 17:33:09,675 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:33:09,675 INFO L462 AbstractCegarLoop]: Abstraction has 11410 states and 13120 transitions. [2019-11-28 17:33:09,675 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:33:09,676 INFO L276 IsEmpty]: Start isEmpty. Operand 11410 states and 13120 transitions. [2019-11-28 17:33:09,682 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2019-11-28 17:33:09,682 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:33:09,682 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:33:09,683 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:33:09,683 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:33:09,683 INFO L82 PathProgramCache]: Analyzing trace with hash 251088387, now seen corresponding path program 1 times [2019-11-28 17:33:09,683 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:33:09,683 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2005217343] [2019-11-28 17:33:09,684 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:33:09,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:33:09,737 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-11-28 17:33:09,738 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2005217343] [2019-11-28 17:33:09,738 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:33:09,738 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:33:09,739 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [967159267] [2019-11-28 17:33:09,739 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:33:09,739 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:33:09,740 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:33:09,740 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:33:09,740 INFO L87 Difference]: Start difference. First operand 11410 states and 13120 transitions. Second operand 3 states. [2019-11-28 17:33:10,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:33:10,609 INFO L93 Difference]: Finished difference Result 22664 states and 25875 transitions. [2019-11-28 17:33:10,609 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:33:10,609 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 178 [2019-11-28 17:33:10,610 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:33:10,620 INFO L225 Difference]: With dead ends: 22664 [2019-11-28 17:33:10,620 INFO L226 Difference]: Without dead ends: 6788 [2019-11-28 17:33:10,634 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:33:10,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6788 states. [2019-11-28 17:33:10,933 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6788 to 6580. [2019-11-28 17:33:10,933 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6580 states. [2019-11-28 17:33:10,941 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6580 states to 6580 states and 7290 transitions. [2019-11-28 17:33:10,941 INFO L78 Accepts]: Start accepts. Automaton has 6580 states and 7290 transitions. Word has length 178 [2019-11-28 17:33:10,942 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:33:10,942 INFO L462 AbstractCegarLoop]: Abstraction has 6580 states and 7290 transitions. [2019-11-28 17:33:10,942 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:33:10,942 INFO L276 IsEmpty]: Start isEmpty. Operand 6580 states and 7290 transitions. [2019-11-28 17:33:10,948 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 181 [2019-11-28 17:33:10,948 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:33:10,949 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:33:10,949 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:33:10,949 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:33:10,949 INFO L82 PathProgramCache]: Analyzing trace with hash -32931800, now seen corresponding path program 1 times [2019-11-28 17:33:10,950 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:33:10,950 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [843309031] [2019-11-28 17:33:10,950 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:33:10,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-11-28 17:33:11,003 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-11-28 17:33:11,003 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [843309031] [2019-11-28 17:33:11,004 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-11-28 17:33:11,004 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-11-28 17:33:11,004 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1452018638] [2019-11-28 17:33:11,004 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-11-28 17:33:11,005 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-11-28 17:33:11,005 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-11-28 17:33:11,005 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:33:11,005 INFO L87 Difference]: Start difference. First operand 6580 states and 7290 transitions. Second operand 3 states. [2019-11-28 17:33:11,317 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-11-28 17:33:11,318 INFO L93 Difference]: Finished difference Result 11554 states and 12829 transitions. [2019-11-28 17:33:11,318 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-11-28 17:33:11,318 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 180 [2019-11-28 17:33:11,319 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-11-28 17:33:11,326 INFO L225 Difference]: With dead ends: 11554 [2019-11-28 17:33:11,326 INFO L226 Difference]: Without dead ends: 6580 [2019-11-28 17:33:11,332 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-11-28 17:33:11,337 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6580 states. [2019-11-28 17:33:11,588 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6580 to 6580. [2019-11-28 17:33:11,589 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6580 states. [2019-11-28 17:33:11,596 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6580 states to 6580 states and 7212 transitions. [2019-11-28 17:33:11,596 INFO L78 Accepts]: Start accepts. Automaton has 6580 states and 7212 transitions. Word has length 180 [2019-11-28 17:33:11,596 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-11-28 17:33:11,596 INFO L462 AbstractCegarLoop]: Abstraction has 6580 states and 7212 transitions. [2019-11-28 17:33:11,597 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-11-28 17:33:11,597 INFO L276 IsEmpty]: Start isEmpty. Operand 6580 states and 7212 transitions. [2019-11-28 17:33:11,602 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 183 [2019-11-28 17:33:11,603 INFO L402 BasicCegarLoop]: Found error trace [2019-11-28 17:33:11,603 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-11-28 17:33:11,603 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-11-28 17:33:11,603 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-11-28 17:33:11,603 INFO L82 PathProgramCache]: Analyzing trace with hash 1382104249, now seen corresponding path program 1 times [2019-11-28 17:33:11,603 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-11-28 17:33:11,604 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [702949932] [2019-11-28 17:33:11,604 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-11-28 17:33:11,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 17:33:11,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-11-28 17:33:11,732 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-11-28 17:33:11,733 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-11-28 17:33:11,885 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 05:33:11 BoogieIcfgContainer [2019-11-28 17:33:11,886 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-11-28 17:33:11,886 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-11-28 17:33:11,886 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-11-28 17:33:11,886 INFO L275 PluginConnector]: Witness Printer initialized [2019-11-28 17:33:11,887 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 05:32:45" (3/4) ... [2019-11-28 17:33:11,889 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-11-28 17:33:12,077 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2019-11-28 17:33:12,078 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-11-28 17:33:12,080 INFO L168 Benchmark]: Toolchain (without parser) took 28844.59 ms. Allocated memory was 1.0 GB in the beginning and 3.2 GB in the end (delta: 2.1 GB). Free memory was 956.3 MB in the beginning and 714.0 MB in the end (delta: 242.4 MB). Peak memory consumption was 2.4 GB. Max. memory is 11.5 GB. [2019-11-28 17:33:12,080 INFO L168 Benchmark]: CDTParser took 0.30 ms. Allocated memory is still 1.0 GB. Free memory is still 987.2 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 17:33:12,081 INFO L168 Benchmark]: CACSL2BoogieTranslator took 558.33 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 114.3 MB). Free memory was 956.3 MB in the beginning and 1.1 GB in the end (delta: -147.6 MB). Peak memory consumption was 25.9 MB. Max. memory is 11.5 GB. [2019-11-28 17:33:12,081 INFO L168 Benchmark]: Boogie Procedure Inliner took 69.79 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. [2019-11-28 17:33:12,082 INFO L168 Benchmark]: Boogie Preprocessor took 56.54 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 1.7 MB). Peak memory consumption was 1.7 MB. Max. memory is 11.5 GB. [2019-11-28 17:33:12,082 INFO L168 Benchmark]: RCFGBuilder took 1103.43 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 65.0 MB). Peak memory consumption was 65.0 MB. Max. memory is 11.5 GB. [2019-11-28 17:33:12,082 INFO L168 Benchmark]: TraceAbstraction took 26858.86 ms. Allocated memory was 1.1 GB in the beginning and 3.2 GB in the end (delta: 2.0 GB). Free memory was 1.0 GB in the beginning and 714.0 MB in the end (delta: 316.5 MB). Peak memory consumption was 2.3 GB. Max. memory is 11.5 GB. [2019-11-28 17:33:12,083 INFO L168 Benchmark]: Witness Printer took 191.51 ms. Allocated memory is still 3.2 GB. Free memory is still 714.0 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-11-28 17:33:12,086 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.30 ms. Allocated memory is still 1.0 GB. Free memory is still 987.2 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 558.33 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 114.3 MB). Free memory was 956.3 MB in the beginning and 1.1 GB in the end (delta: -147.6 MB). Peak memory consumption was 25.9 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 69.79 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 56.54 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 1.7 MB). Peak memory consumption was 1.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1103.43 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 65.0 MB). Peak memory consumption was 65.0 MB. Max. memory is 11.5 GB. * TraceAbstraction took 26858.86 ms. Allocated memory was 1.1 GB in the beginning and 3.2 GB in the end (delta: 2.0 GB). Free memory was 1.0 GB in the beginning and 714.0 MB in the end (delta: 316.5 MB). Peak memory consumption was 2.3 GB. Max. memory is 11.5 GB. * Witness Printer took 191.51 ms. Allocated memory is still 3.2 GB. Free memory is still 714.0 MB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int m_st ; [L20] int t1_st ; [L21] int t2_st ; [L22] int t3_st ; [L23] int m_i ; [L24] int t1_i ; [L25] int t2_i ; [L26] int t3_i ; [L27] int M_E = 2; [L28] int T1_E = 2; [L29] int T2_E = 2; [L30] int T3_E = 2; [L31] int E_1 = 2; [L32] int E_2 = 2; [L33] int E_3 = 2; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0] [L687] int __retres1 ; [L600] m_i = 1 [L601] t1_i = 1 [L602] t2_i = 1 [L603] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L628] int kernel_st ; [L629] int tmp ; [L630] int tmp___0 ; [L634] kernel_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L271] COND TRUE m_i == 1 [L272] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L276] COND TRUE t1_i == 1 [L277] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L281] COND TRUE t2_i == 1 [L282] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L286] COND TRUE t3_i == 1 [L287] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L408] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L413] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L418] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L423] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L428] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L433] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L438] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; [L184] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L187] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L197] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L199] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L203] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L206] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L216] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L218] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L506] tmp___0 = is_transmit1_triggered() [L508] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L222] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L225] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L235] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L237] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L514] tmp___1 = is_transmit2_triggered() [L516] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L241] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L244] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L254] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L256] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L522] tmp___2 = is_transmit3_triggered() [L524] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L451] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L456] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L461] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L466] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L471] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L476] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L481] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L642] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L645] kernel_st = 1 [L327] int tmp ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L331] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L296] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L299] COND TRUE m_st == 0 [L300] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L322] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L334] tmp = exists_runnable_thread() [L336] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L341] COND TRUE m_st == 0 [L342] int tmp_ndt_1; [L343] tmp_ndt_1 = __VERIFIER_nondet_int() [L344] COND FALSE !(\read(tmp_ndt_1)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L355] COND TRUE t1_st == 0 [L356] int tmp_ndt_2; [L357] tmp_ndt_2 = __VERIFIER_nondet_int() [L358] COND TRUE \read(tmp_ndt_2) [L360] t1_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L84] COND TRUE t1_pc == 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L95] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L97] t1_pc = 1 [L98] t1_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L369] COND TRUE t2_st == 0 [L370] int tmp_ndt_3; [L371] tmp_ndt_3 = __VERIFIER_nondet_int() [L372] COND TRUE \read(tmp_ndt_3) [L374] t2_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L119] COND TRUE t2_pc == 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L130] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L132] t2_pc = 1 [L133] t2_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0] [L383] COND TRUE t3_st == 0 [L384] int tmp_ndt_4; [L385] tmp_ndt_4 = __VERIFIER_nondet_int() [L386] COND TRUE \read(tmp_ndt_4) [L388] t3_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1] [L154] COND TRUE t3_pc == 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1] [L165] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1] [L167] t3_pc = 1 [L168] t3_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L331] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L296] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L299] COND TRUE m_st == 0 [L300] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L322] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L334] tmp = exists_runnable_thread() [L336] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L341] COND TRUE m_st == 0 [L342] int tmp_ndt_1; [L343] tmp_ndt_1 = __VERIFIER_nondet_int() [L344] COND TRUE \read(tmp_ndt_1) [L346] m_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L43] COND TRUE m_pc == 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L54] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L57] E_1 = 1 [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; [L184] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L187] COND FALSE !(m_pc == 1) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L197] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L199] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L203] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L206] COND TRUE t1_pc == 1 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L207] COND TRUE E_1 == 1 [L208] __retres1 = 1 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L218] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L506] tmp___0 = is_transmit1_triggered() [L508] COND TRUE \read(tmp___0) [L509] t1_st = 0 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L222] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L225] COND TRUE t2_pc == 1 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L226] COND FALSE !(E_2 == 1) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L235] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L237] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L514] tmp___1 = is_transmit2_triggered() [L516] COND FALSE !(\read(tmp___1)) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L241] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L244] COND TRUE t3_pc == 1 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L245] COND FALSE !(E_3 == 1) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L254] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L256] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L522] tmp___2 = is_transmit3_triggered() [L524] COND FALSE !(\read(tmp___2)) VAL [E_1=1, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L59] E_1 = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L62] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L64] m_pc = 1 [L65] m_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L355] COND TRUE t1_st == 0 [L356] int tmp_ndt_2; [L357] tmp_ndt_2 = __VERIFIER_nondet_int() [L358] COND TRUE \read(tmp_ndt_2) [L360] t1_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L84] COND FALSE !(t1_pc == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L87] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L103] E_2 = 1 [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; [L184] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L187] COND TRUE m_pc == 1 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L188] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L197] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L199] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L203] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L206] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L207] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L216] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L218] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L506] tmp___0 = is_transmit1_triggered() [L508] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L222] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L225] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L226] COND TRUE E_2 == 1 [L227] __retres1 = 1 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L237] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L514] tmp___1 = is_transmit2_triggered() [L516] COND TRUE \read(tmp___1) [L517] t2_st = 0 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L241] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L244] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L245] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L254] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L256] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L522] tmp___2 = is_transmit3_triggered() [L524] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=1, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L105] E_2 = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L95] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L97] t1_pc = 1 [L98] t1_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L369] COND TRUE t2_st == 0 [L370] int tmp_ndt_3; [L371] tmp_ndt_3 = __VERIFIER_nondet_int() [L372] COND TRUE \read(tmp_ndt_3) [L374] t2_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L119] COND FALSE !(t2_pc == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L122] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L138] E_3 = 1 [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; [L184] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L187] COND TRUE m_pc == 1 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L188] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L197] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L199] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L203] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L206] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L207] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L216] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L218] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L506] tmp___0 = is_transmit1_triggered() [L508] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L222] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L225] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L226] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L235] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L237] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L514] tmp___1 = is_transmit2_triggered() [L516] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L241] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L244] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L245] COND TRUE E_3 == 1 [L246] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L256] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2] [L522] tmp___2 = is_transmit3_triggered() [L524] COND TRUE \read(tmp___2) [L525] t3_st = 0 VAL [E_1=2, E_2=2, E_3=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L140] E_3 = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L130] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L132] t2_pc = 1 [L133] t2_st = 2 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0] [L383] COND TRUE t3_st == 0 [L384] int tmp_ndt_4; [L385] tmp_ndt_4 = __VERIFIER_nondet_int() [L386] COND TRUE \read(tmp_ndt_4) [L388] t3_st = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] [L154] COND FALSE !(t3_pc == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] [L157] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] [L11] __VERIFIER_error() VAL [E_1=2, E_2=2, E_3=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 276 locations, 1 error locations. Result: UNSAFE, OverallTime: 26.6s, OverallIterations: 27, TraceHistogramMax: 2, AutomataDifference: 14.7s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 10884 SDtfs, 10117 SDslu, 7643 SDs, 0 SdLazy, 500 SolverSat, 248 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.8s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 92 GetRequests, 50 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=19420occurred in iteration=18, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 9.5s AutomataMinimizationTime, 26 MinimizatonAttempts, 33813 StatesRemovedByMinimization, 16 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 0.9s InterpolantComputationTime, 2694 NumberOfCodeBlocks, 2694 NumberOfCodeBlocksAsserted, 27 NumberOfCheckSat, 2486 ConstructedInterpolants, 0 QuantifiedInterpolants, 403400 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 26 InterpolantComputations, 26 PerfectInterpolantSequences, 228/228 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...