./Ultimate.py --spec ../../sv-benchmarks/c/properties/valid-memsafety.prp --file ../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_-write.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for memory safety (deref-memtrack) Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/config/AutomizerMemDerefMemtrack.xml -i ../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_-write.c -s /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 68d161eb03bccd8280d2086bc4cdb7b46f7ee157 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Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(valid-deref) --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 17:19:31,237 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 17:19:31,238 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 17:19:31,248 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 17:19:31,248 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 17:19:31,249 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 17:19:31,250 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 17:19:31,251 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 17:19:31,252 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 17:19:31,253 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 17:19:31,253 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 17:19:31,254 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 17:19:31,254 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 17:19:31,255 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 17:19:31,256 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 17:19:31,257 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 17:19:31,257 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 17:19:31,258 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 17:19:31,259 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 17:19:31,261 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 17:19:31,262 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 17:19:31,263 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 17:19:31,264 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 17:19:31,265 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 17:19:31,266 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 17:19:31,267 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 17:19:31,267 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 17:19:31,267 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 17:19:31,267 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 17:19:31,268 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 17:19:31,268 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 17:19:31,269 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 17:19:31,269 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 17:19:31,270 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 17:19:31,271 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 17:19:31,271 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 17:19:31,271 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 17:19:31,271 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 17:19:31,272 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 17:19:31,272 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 17:19:31,273 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 17:19:31,273 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf [2019-12-07 17:19:31,283 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 17:19:31,284 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 17:19:31,284 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 17:19:31,285 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 17:19:31,285 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 17:19:31,285 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 17:19:31,285 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 17:19:31,285 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2019-12-07 17:19:31,285 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 17:19:31,285 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 17:19:31,286 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 17:19:31,286 INFO L138 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2019-12-07 17:19:31,286 INFO L138 SettingsManager]: * Bitprecise bitfields=true [2019-12-07 17:19:31,286 INFO L138 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2019-12-07 17:19:31,286 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 17:19:31,286 INFO L138 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2019-12-07 17:19:31,286 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 17:19:31,286 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 17:19:31,287 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 17:19:31,287 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 17:19:31,287 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 17:19:31,287 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 17:19:31,287 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 17:19:31,287 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 17:19:31,287 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 17:19:31,287 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 17:19:31,288 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 17:19:31,288 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 17:19:31,288 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 68d161eb03bccd8280d2086bc4cdb7b46f7ee157 [2019-12-07 17:19:31,387 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 17:19:31,397 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 17:19:31,400 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 17:19:31,401 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 17:19:31,402 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 17:19:31,402 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_-write.c [2019-12-07 17:19:31,444 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/data/00645c5aa/a5686b01a13c41369e07d85f67008df1/FLAG947480871 [2019-12-07 17:19:31,767 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 17:19:31,768 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration_-write.c [2019-12-07 17:19:31,772 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/data/00645c5aa/a5686b01a13c41369e07d85f67008df1/FLAG947480871 [2019-12-07 17:19:31,780 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/data/00645c5aa/a5686b01a13c41369e07d85f67008df1 [2019-12-07 17:19:31,783 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 17:19:31,784 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2019-12-07 17:19:31,784 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 17:19:31,784 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 17:19:31,786 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 17:19:31,787 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 05:19:31" (1/1) ... [2019-12-07 17:19:31,789 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@45c8495d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:19:31, skipping insertion in model container [2019-12-07 17:19:31,789 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 05:19:31" (1/1) ... [2019-12-07 17:19:31,793 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 17:19:31,805 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 17:19:31,943 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 17:19:31,952 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 17:19:31,963 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 17:19:31,973 INFO L208 MainTranslator]: Completed translation [2019-12-07 17:19:31,973 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:19:31 WrapperNode [2019-12-07 17:19:31,973 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 17:19:31,974 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 17:19:31,974 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 17:19:31,974 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 17:19:31,982 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:19:31" (1/1) ... [2019-12-07 17:19:31,982 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:19:31" (1/1) ... [2019-12-07 17:19:31,988 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:19:31" (1/1) ... [2019-12-07 17:19:31,988 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:19:31" (1/1) ... [2019-12-07 17:19:31,992 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:19:31" (1/1) ... [2019-12-07 17:19:31,995 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:19:31" (1/1) ... [2019-12-07 17:19:31,996 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:19:31" (1/1) ... [2019-12-07 17:19:31,997 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 17:19:31,998 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 17:19:31,998 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 17:19:31,998 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 17:19:31,998 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:19:31" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 17:19:32,037 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2019-12-07 17:19:32,037 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 17:19:32,037 INFO L138 BoogieDeclarations]: Found implementation of procedure foo [2019-12-07 17:19:32,038 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2019-12-07 17:19:32,038 INFO L130 BoogieDeclarations]: Found specification of procedure foo [2019-12-07 17:19:32,038 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-12-07 17:19:32,038 INFO L130 BoogieDeclarations]: Found specification of procedure main [2019-12-07 17:19:32,038 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 17:19:32,038 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 17:19:32,038 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 17:19:32,038 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2019-12-07 17:19:32,038 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 17:19:32,197 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 17:19:32,197 INFO L287 CfgBuilder]: Removed 3 assume(true) statements. [2019-12-07 17:19:32,198 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:19:32 BoogieIcfgContainer [2019-12-07 17:19:32,198 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 17:19:32,199 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 17:19:32,199 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 17:19:32,201 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 17:19:32,201 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 05:19:31" (1/3) ... [2019-12-07 17:19:32,201 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@66023c9c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 05:19:32, skipping insertion in model container [2019-12-07 17:19:32,201 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:19:31" (2/3) ... [2019-12-07 17:19:32,202 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@66023c9c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 05:19:32, skipping insertion in model container [2019-12-07 17:19:32,202 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:19:32" (3/3) ... [2019-12-07 17:19:32,203 INFO L109 eAbstractionObserver]: Analyzing ICFG ArraysWithLenghtAtDeclaration_-write.c [2019-12-07 17:19:32,210 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 17:19:32,214 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 8 error locations. [2019-12-07 17:19:32,221 INFO L249 AbstractCegarLoop]: Starting to check reachability of 8 error locations. [2019-12-07 17:19:32,233 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 17:19:32,233 INFO L374 AbstractCegarLoop]: Hoare is false [2019-12-07 17:19:32,233 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 17:19:32,233 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 17:19:32,233 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 17:19:32,234 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 17:19:32,234 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 17:19:32,234 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 17:19:32,245 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states. [2019-12-07 17:19:32,251 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 11 [2019-12-07 17:19:32,251 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:32,251 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:32,252 INFO L410 AbstractCegarLoop]: === Iteration 1 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:32,256 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:32,256 INFO L82 PathProgramCache]: Analyzing trace with hash 1909189377, now seen corresponding path program 1 times [2019-12-07 17:19:32,261 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:32,262 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1950747589] [2019-12-07 17:19:32,262 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:19:32,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:32,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:32,376 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:19:32,376 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1950747589] [2019-12-07 17:19:32,377 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:19:32,377 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 17:19:32,377 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [334849552] [2019-12-07 17:19:32,380 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:19:32,380 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:19:32,389 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:19:32,390 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:19:32,391 INFO L87 Difference]: Start difference. First operand 40 states. Second operand 4 states. [2019-12-07 17:19:32,507 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:19:32,507 INFO L93 Difference]: Finished difference Result 58 states and 63 transitions. [2019-12-07 17:19:32,508 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:19:32,509 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 10 [2019-12-07 17:19:32,509 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:19:32,517 INFO L225 Difference]: With dead ends: 58 [2019-12-07 17:19:32,518 INFO L226 Difference]: Without dead ends: 54 [2019-12-07 17:19:32,519 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:19:32,535 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2019-12-07 17:19:32,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 39. [2019-12-07 17:19:32,553 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39 states. [2019-12-07 17:19:32,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 42 transitions. [2019-12-07 17:19:32,555 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 42 transitions. Word has length 10 [2019-12-07 17:19:32,555 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:19:32,555 INFO L462 AbstractCegarLoop]: Abstraction has 39 states and 42 transitions. [2019-12-07 17:19:32,555 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:19:32,555 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 42 transitions. [2019-12-07 17:19:32,555 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-12-07 17:19:32,556 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:32,556 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:32,556 INFO L410 AbstractCegarLoop]: === Iteration 2 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:32,556 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:32,556 INFO L82 PathProgramCache]: Analyzing trace with hash -941983064, now seen corresponding path program 1 times [2019-12-07 17:19:32,556 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:32,557 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [59733983] [2019-12-07 17:19:32,557 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:19:32,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:32,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:32,601 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:19:32,602 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [59733983] [2019-12-07 17:19:32,602 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:19:32,602 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:19:32,602 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2080068339] [2019-12-07 17:19:32,603 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:19:32,603 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:19:32,604 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:19:32,604 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:19:32,604 INFO L87 Difference]: Start difference. First operand 39 states and 42 transitions. Second operand 4 states. [2019-12-07 17:19:32,664 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:19:32,665 INFO L93 Difference]: Finished difference Result 49 states and 53 transitions. [2019-12-07 17:19:32,665 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 17:19:32,665 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-12-07 17:19:32,665 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:19:32,667 INFO L225 Difference]: With dead ends: 49 [2019-12-07 17:19:32,667 INFO L226 Difference]: Without dead ends: 49 [2019-12-07 17:19:32,667 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:19:32,668 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2019-12-07 17:19:32,670 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 41. [2019-12-07 17:19:32,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41 states. [2019-12-07 17:19:32,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 45 transitions. [2019-12-07 17:19:32,671 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 45 transitions. Word has length 11 [2019-12-07 17:19:32,671 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:19:32,671 INFO L462 AbstractCegarLoop]: Abstraction has 41 states and 45 transitions. [2019-12-07 17:19:32,672 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:19:32,672 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 45 transitions. [2019-12-07 17:19:32,672 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2019-12-07 17:19:32,672 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:32,672 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:32,672 INFO L410 AbstractCegarLoop]: === Iteration 3 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:32,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:32,672 INFO L82 PathProgramCache]: Analyzing trace with hash 863296133, now seen corresponding path program 1 times [2019-12-07 17:19:32,673 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:32,673 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [312788761] [2019-12-07 17:19:32,673 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:19:32,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:32,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:32,718 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:19:32,719 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [312788761] [2019-12-07 17:19:32,719 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:19:32,719 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:19:32,719 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [256137555] [2019-12-07 17:19:32,719 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:19:32,720 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:19:32,720 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:19:32,720 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:19:32,720 INFO L87 Difference]: Start difference. First operand 41 states and 45 transitions. Second operand 6 states. [2019-12-07 17:19:32,801 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:19:32,801 INFO L93 Difference]: Finished difference Result 40 states and 44 transitions. [2019-12-07 17:19:32,802 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 17:19:32,802 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 12 [2019-12-07 17:19:32,802 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:19:32,802 INFO L225 Difference]: With dead ends: 40 [2019-12-07 17:19:32,802 INFO L226 Difference]: Without dead ends: 40 [2019-12-07 17:19:32,803 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2019-12-07 17:19:32,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2019-12-07 17:19:32,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 40. [2019-12-07 17:19:32,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40 states. [2019-12-07 17:19:32,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 44 transitions. [2019-12-07 17:19:32,807 INFO L78 Accepts]: Start accepts. Automaton has 40 states and 44 transitions. Word has length 12 [2019-12-07 17:19:32,807 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:19:32,807 INFO L462 AbstractCegarLoop]: Abstraction has 40 states and 44 transitions. [2019-12-07 17:19:32,807 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:19:32,807 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 44 transitions. [2019-12-07 17:19:32,807 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2019-12-07 17:19:32,807 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:32,807 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:32,808 INFO L410 AbstractCegarLoop]: === Iteration 4 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:32,808 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:32,808 INFO L82 PathProgramCache]: Analyzing trace with hash 863296134, now seen corresponding path program 1 times [2019-12-07 17:19:32,808 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:32,808 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1258179990] [2019-12-07 17:19:32,808 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:19:32,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:32,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:32,867 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:19:32,867 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1258179990] [2019-12-07 17:19:32,867 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:19:32,868 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 17:19:32,868 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [505441048] [2019-12-07 17:19:32,868 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 17:19:32,868 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:19:32,869 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 17:19:32,869 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:19:32,869 INFO L87 Difference]: Start difference. First operand 40 states and 44 transitions. Second operand 7 states. [2019-12-07 17:19:32,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:19:32,977 INFO L93 Difference]: Finished difference Result 42 states and 46 transitions. [2019-12-07 17:19:32,977 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 17:19:32,977 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 12 [2019-12-07 17:19:32,978 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:19:32,978 INFO L225 Difference]: With dead ends: 42 [2019-12-07 17:19:32,978 INFO L226 Difference]: Without dead ends: 42 [2019-12-07 17:19:32,979 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2019-12-07 17:19:32,979 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states. [2019-12-07 17:19:32,981 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 39. [2019-12-07 17:19:32,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39 states. [2019-12-07 17:19:32,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 43 transitions. [2019-12-07 17:19:32,982 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 43 transitions. Word has length 12 [2019-12-07 17:19:32,982 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:19:32,982 INFO L462 AbstractCegarLoop]: Abstraction has 39 states and 43 transitions. [2019-12-07 17:19:32,983 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 17:19:32,983 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 43 transitions. [2019-12-07 17:19:32,983 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 17:19:32,983 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:32,983 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:32,983 INFO L410 AbstractCegarLoop]: === Iteration 5 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:32,983 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:32,984 INFO L82 PathProgramCache]: Analyzing trace with hash 143250926, now seen corresponding path program 1 times [2019-12-07 17:19:32,984 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:32,984 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1703802206] [2019-12-07 17:19:32,984 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:19:32,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:33,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:33,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:33,026 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:19:33,026 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1703802206] [2019-12-07 17:19:33,026 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:19:33,026 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:19:33,026 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1080964015] [2019-12-07 17:19:33,027 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:19:33,027 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:19:33,027 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:19:33,027 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:19:33,027 INFO L87 Difference]: Start difference. First operand 39 states and 43 transitions. Second operand 4 states. [2019-12-07 17:19:33,067 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:19:33,067 INFO L93 Difference]: Finished difference Result 37 states and 41 transitions. [2019-12-07 17:19:33,067 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 17:19:33,067 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-12-07 17:19:33,067 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:19:33,068 INFO L225 Difference]: With dead ends: 37 [2019-12-07 17:19:33,068 INFO L226 Difference]: Without dead ends: 37 [2019-12-07 17:19:33,068 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:19:33,069 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2019-12-07 17:19:33,070 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 37. [2019-12-07 17:19:33,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37 states. [2019-12-07 17:19:33,071 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 41 transitions. [2019-12-07 17:19:33,071 INFO L78 Accepts]: Start accepts. Automaton has 37 states and 41 transitions. Word has length 15 [2019-12-07 17:19:33,071 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:19:33,071 INFO L462 AbstractCegarLoop]: Abstraction has 37 states and 41 transitions. [2019-12-07 17:19:33,072 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:19:33,072 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 41 transitions. [2019-12-07 17:19:33,072 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 17:19:33,072 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:33,072 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:33,072 INFO L410 AbstractCegarLoop]: === Iteration 6 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:33,072 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:33,073 INFO L82 PathProgramCache]: Analyzing trace with hash 143250927, now seen corresponding path program 1 times [2019-12-07 17:19:33,073 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:33,073 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [951352260] [2019-12-07 17:19:33,073 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:19:33,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:33,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:33,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:33,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:19:33,114 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [951352260] [2019-12-07 17:19:33,114 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:19:33,114 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 17:19:33,114 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [417118703] [2019-12-07 17:19:33,114 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:19:33,115 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:19:33,115 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:19:33,115 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:19:33,115 INFO L87 Difference]: Start difference. First operand 37 states and 41 transitions. Second operand 6 states. [2019-12-07 17:19:33,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:19:33,209 INFO L93 Difference]: Finished difference Result 56 states and 61 transitions. [2019-12-07 17:19:33,209 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 17:19:33,210 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 15 [2019-12-07 17:19:33,210 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:19:33,210 INFO L225 Difference]: With dead ends: 56 [2019-12-07 17:19:33,210 INFO L226 Difference]: Without dead ends: 56 [2019-12-07 17:19:33,211 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2019-12-07 17:19:33,211 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56 states. [2019-12-07 17:19:33,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56 to 41. [2019-12-07 17:19:33,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41 states. [2019-12-07 17:19:33,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 46 transitions. [2019-12-07 17:19:33,215 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 46 transitions. Word has length 15 [2019-12-07 17:19:33,216 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:19:33,216 INFO L462 AbstractCegarLoop]: Abstraction has 41 states and 46 transitions. [2019-12-07 17:19:33,216 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:19:33,216 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 46 transitions. [2019-12-07 17:19:33,216 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2019-12-07 17:19:33,216 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:33,217 INFO L410 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:33,217 INFO L410 AbstractCegarLoop]: === Iteration 7 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:33,217 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:33,217 INFO L82 PathProgramCache]: Analyzing trace with hash 1623425863, now seen corresponding path program 1 times [2019-12-07 17:19:33,217 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:33,217 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1671336038] [2019-12-07 17:19:33,217 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:19:33,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:33,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:33,275 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:19:33,275 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1671336038] [2019-12-07 17:19:33,276 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [598414568] [2019-12-07 17:19:33,276 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:33,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:33,304 INFO L264 TraceCheckSpWp]: Trace formula consists of 75 conjuncts, 5 conjunts are in the unsatisfiable core [2019-12-07 17:19:33,307 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:19:33,330 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:19:33,330 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:19:33,330 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 3] total 9 [2019-12-07 17:19:33,331 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1419957102] [2019-12-07 17:19:33,331 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 17:19:33,331 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:19:33,331 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 17:19:33,332 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2019-12-07 17:19:33,332 INFO L87 Difference]: Start difference. First operand 41 states and 46 transitions. Second operand 10 states. [2019-12-07 17:19:33,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:19:33,559 INFO L93 Difference]: Finished difference Result 85 states and 92 transitions. [2019-12-07 17:19:33,559 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 17:19:33,559 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 16 [2019-12-07 17:19:33,560 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:19:33,561 INFO L225 Difference]: With dead ends: 85 [2019-12-07 17:19:33,561 INFO L226 Difference]: Without dead ends: 82 [2019-12-07 17:19:33,561 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 15 SyntacticMatches, 1 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 37 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=77, Invalid=229, Unknown=0, NotChecked=0, Total=306 [2019-12-07 17:19:33,562 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states. [2019-12-07 17:19:33,566 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 53. [2019-12-07 17:19:33,566 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53 states. [2019-12-07 17:19:33,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 59 transitions. [2019-12-07 17:19:33,567 INFO L78 Accepts]: Start accepts. Automaton has 53 states and 59 transitions. Word has length 16 [2019-12-07 17:19:33,567 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:19:33,567 INFO L462 AbstractCegarLoop]: Abstraction has 53 states and 59 transitions. [2019-12-07 17:19:33,567 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 17:19:33,572 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states and 59 transitions. [2019-12-07 17:19:33,572 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2019-12-07 17:19:33,572 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:33,572 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:33,773 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:33,774 INFO L410 AbstractCegarLoop]: === Iteration 8 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:33,775 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:33,776 INFO L82 PathProgramCache]: Analyzing trace with hash 2121234190, now seen corresponding path program 1 times [2019-12-07 17:19:33,776 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:33,776 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [892416432] [2019-12-07 17:19:33,777 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:19:33,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:33,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:33,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:33,859 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:19:33,859 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [892416432] [2019-12-07 17:19:33,860 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1533558684] [2019-12-07 17:19:33,860 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:33,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:33,882 INFO L264 TraceCheckSpWp]: Trace formula consists of 82 conjuncts, 6 conjunts are in the unsatisfiable core [2019-12-07 17:19:33,883 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:19:33,917 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:19:33,917 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:19:33,918 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6] total 10 [2019-12-07 17:19:33,918 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1846616396] [2019-12-07 17:19:33,918 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 17:19:33,919 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:19:33,919 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 17:19:33,919 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2019-12-07 17:19:33,919 INFO L87 Difference]: Start difference. First operand 53 states and 59 transitions. Second operand 10 states. [2019-12-07 17:19:34,055 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:19:34,055 INFO L93 Difference]: Finished difference Result 86 states and 90 transitions. [2019-12-07 17:19:34,055 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 17:19:34,055 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 20 [2019-12-07 17:19:34,056 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:19:34,056 INFO L225 Difference]: With dead ends: 86 [2019-12-07 17:19:34,056 INFO L226 Difference]: Without dead ends: 77 [2019-12-07 17:19:34,057 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 19 SyntacticMatches, 1 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=54, Invalid=128, Unknown=0, NotChecked=0, Total=182 [2019-12-07 17:19:34,057 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77 states. [2019-12-07 17:19:34,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77 to 58. [2019-12-07 17:19:34,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 58 states. [2019-12-07 17:19:34,062 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 62 transitions. [2019-12-07 17:19:34,063 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 62 transitions. Word has length 20 [2019-12-07 17:19:34,063 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:19:34,063 INFO L462 AbstractCegarLoop]: Abstraction has 58 states and 62 transitions. [2019-12-07 17:19:34,063 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 17:19:34,063 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 62 transitions. [2019-12-07 17:19:34,064 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 17:19:34,064 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:34,064 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:34,265 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:34,265 INFO L410 AbstractCegarLoop]: === Iteration 9 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:34,266 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:34,266 INFO L82 PathProgramCache]: Analyzing trace with hash -523456177, now seen corresponding path program 2 times [2019-12-07 17:19:34,267 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:34,267 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1612152046] [2019-12-07 17:19:34,267 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:19:34,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:34,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:34,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:34,412 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-12-07 17:19:34,413 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1612152046] [2019-12-07 17:19:34,413 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:19:34,413 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:19:34,414 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [755453539] [2019-12-07 17:19:34,414 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:19:34,415 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:19:34,415 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:19:34,415 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:19:34,416 INFO L87 Difference]: Start difference. First operand 58 states and 62 transitions. Second operand 4 states. [2019-12-07 17:19:34,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:19:34,478 INFO L93 Difference]: Finished difference Result 62 states and 66 transitions. [2019-12-07 17:19:34,479 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 17:19:34,479 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 25 [2019-12-07 17:19:34,479 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:19:34,480 INFO L225 Difference]: With dead ends: 62 [2019-12-07 17:19:34,480 INFO L226 Difference]: Without dead ends: 62 [2019-12-07 17:19:34,480 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:19:34,481 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states. [2019-12-07 17:19:34,484 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 60. [2019-12-07 17:19:34,484 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2019-12-07 17:19:34,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 64 transitions. [2019-12-07 17:19:34,485 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 64 transitions. Word has length 25 [2019-12-07 17:19:34,485 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:19:34,485 INFO L462 AbstractCegarLoop]: Abstraction has 60 states and 64 transitions. [2019-12-07 17:19:34,485 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:19:34,485 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 64 transitions. [2019-12-07 17:19:34,486 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-12-07 17:19:34,486 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:34,486 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:34,487 INFO L410 AbstractCegarLoop]: === Iteration 10 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:34,487 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:34,487 INFO L82 PathProgramCache]: Analyzing trace with hash 2020089664, now seen corresponding path program 1 times [2019-12-07 17:19:34,487 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:34,487 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2105185896] [2019-12-07 17:19:34,487 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:19:34,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:34,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:34,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:34,556 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 1 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:19:34,556 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2105185896] [2019-12-07 17:19:34,556 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [504188970] [2019-12-07 17:19:34,557 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:34,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:34,581 INFO L264 TraceCheckSpWp]: Trace formula consists of 106 conjuncts, 3 conjunts are in the unsatisfiable core [2019-12-07 17:19:34,582 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:19:34,597 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-12-07 17:19:34,597 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:19:34,597 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 4] total 11 [2019-12-07 17:19:34,598 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1528126356] [2019-12-07 17:19:34,598 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 17:19:34,598 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:19:34,598 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 17:19:34,598 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=82, Unknown=0, NotChecked=0, Total=110 [2019-12-07 17:19:34,598 INFO L87 Difference]: Start difference. First operand 60 states and 64 transitions. Second operand 11 states. [2019-12-07 17:19:34,805 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:19:34,805 INFO L93 Difference]: Finished difference Result 118 states and 126 transitions. [2019-12-07 17:19:34,805 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-12-07 17:19:34,805 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 31 [2019-12-07 17:19:34,805 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:19:34,806 INFO L225 Difference]: With dead ends: 118 [2019-12-07 17:19:34,806 INFO L226 Difference]: Without dead ends: 118 [2019-12-07 17:19:34,806 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 33 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 47 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=80, Invalid=226, Unknown=0, NotChecked=0, Total=306 [2019-12-07 17:19:34,807 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states. [2019-12-07 17:19:34,811 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 96. [2019-12-07 17:19:34,811 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 96 states. [2019-12-07 17:19:34,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96 states to 96 states and 114 transitions. [2019-12-07 17:19:34,812 INFO L78 Accepts]: Start accepts. Automaton has 96 states and 114 transitions. Word has length 31 [2019-12-07 17:19:34,812 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:19:34,812 INFO L462 AbstractCegarLoop]: Abstraction has 96 states and 114 transitions. [2019-12-07 17:19:34,812 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 17:19:34,812 INFO L276 IsEmpty]: Start isEmpty. Operand 96 states and 114 transitions. [2019-12-07 17:19:34,813 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-12-07 17:19:34,813 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:34,813 INFO L410 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 4, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:35,014 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:35,015 INFO L410 AbstractCegarLoop]: === Iteration 11 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:35,016 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:35,016 INFO L82 PathProgramCache]: Analyzing trace with hash -1710006518, now seen corresponding path program 1 times [2019-12-07 17:19:35,017 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:35,017 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1836383653] [2019-12-07 17:19:35,018 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:19:35,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:35,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:35,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:35,162 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 35 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2019-12-07 17:19:35,162 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1836383653] [2019-12-07 17:19:35,162 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1249601139] [2019-12-07 17:19:35,162 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:35,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:35,191 INFO L264 TraceCheckSpWp]: Trace formula consists of 144 conjuncts, 7 conjunts are in the unsatisfiable core [2019-12-07 17:19:35,193 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:19:35,219 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 27 proven. 9 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2019-12-07 17:19:35,219 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:19:35,219 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 4] total 12 [2019-12-07 17:19:35,219 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1574016189] [2019-12-07 17:19:35,220 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 17:19:35,220 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:19:35,220 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 17:19:35,220 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=126, Unknown=0, NotChecked=0, Total=156 [2019-12-07 17:19:35,221 INFO L87 Difference]: Start difference. First operand 96 states and 114 transitions. Second operand 13 states. [2019-12-07 17:19:35,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:19:35,525 INFO L93 Difference]: Finished difference Result 152 states and 170 transitions. [2019-12-07 17:19:35,526 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2019-12-07 17:19:35,526 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 42 [2019-12-07 17:19:35,526 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:19:35,527 INFO L225 Difference]: With dead ends: 152 [2019-12-07 17:19:35,528 INFO L226 Difference]: Without dead ends: 152 [2019-12-07 17:19:35,528 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 42 SyntacticMatches, 1 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 69 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=96, Invalid=366, Unknown=0, NotChecked=0, Total=462 [2019-12-07 17:19:35,528 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152 states. [2019-12-07 17:19:35,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152 to 124. [2019-12-07 17:19:35,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 124 states. [2019-12-07 17:19:35,535 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 144 transitions. [2019-12-07 17:19:35,535 INFO L78 Accepts]: Start accepts. Automaton has 124 states and 144 transitions. Word has length 42 [2019-12-07 17:19:35,535 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:19:35,535 INFO L462 AbstractCegarLoop]: Abstraction has 124 states and 144 transitions. [2019-12-07 17:19:35,535 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 17:19:35,535 INFO L276 IsEmpty]: Start isEmpty. Operand 124 states and 144 transitions. [2019-12-07 17:19:35,536 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2019-12-07 17:19:35,536 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:35,536 INFO L410 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:35,737 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:35,738 INFO L410 AbstractCegarLoop]: === Iteration 12 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:35,738 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:35,738 INFO L82 PathProgramCache]: Analyzing trace with hash -1860847279, now seen corresponding path program 1 times [2019-12-07 17:19:35,739 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:35,739 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [451952771] [2019-12-07 17:19:35,739 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:19:35,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:35,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:35,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:35,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:35,958 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 5 proven. 41 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-12-07 17:19:35,958 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [451952771] [2019-12-07 17:19:35,958 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1723434100] [2019-12-07 17:19:35,958 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:35,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:35,985 INFO L264 TraceCheckSpWp]: Trace formula consists of 151 conjuncts, 8 conjunts are in the unsatisfiable core [2019-12-07 17:19:35,987 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:19:36,036 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 32 proven. 7 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-12-07 17:19:36,036 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:19:36,036 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 8] total 16 [2019-12-07 17:19:36,036 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1896545648] [2019-12-07 17:19:36,037 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 17:19:36,037 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:19:36,037 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 17:19:36,038 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=196, Unknown=0, NotChecked=0, Total=240 [2019-12-07 17:19:36,038 INFO L87 Difference]: Start difference. First operand 124 states and 144 transitions. Second operand 16 states. [2019-12-07 17:19:36,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:19:36,254 INFO L93 Difference]: Finished difference Result 141 states and 154 transitions. [2019-12-07 17:19:36,255 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 17:19:36,255 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 46 [2019-12-07 17:19:36,255 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:19:36,256 INFO L225 Difference]: With dead ends: 141 [2019-12-07 17:19:36,256 INFO L226 Difference]: Without dead ends: 135 [2019-12-07 17:19:36,257 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 48 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 48 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=107, Invalid=355, Unknown=0, NotChecked=0, Total=462 [2019-12-07 17:19:36,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states. [2019-12-07 17:19:36,261 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 112. [2019-12-07 17:19:36,261 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112 states. [2019-12-07 17:19:36,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 126 transitions. [2019-12-07 17:19:36,263 INFO L78 Accepts]: Start accepts. Automaton has 112 states and 126 transitions. Word has length 46 [2019-12-07 17:19:36,263 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:19:36,263 INFO L462 AbstractCegarLoop]: Abstraction has 112 states and 126 transitions. [2019-12-07 17:19:36,263 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 17:19:36,263 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 126 transitions. [2019-12-07 17:19:36,264 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-12-07 17:19:36,264 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:36,265 INFO L410 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:36,465 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:36,466 INFO L410 AbstractCegarLoop]: === Iteration 13 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:36,466 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:36,467 INFO L82 PathProgramCache]: Analyzing trace with hash -1743494932, now seen corresponding path program 2 times [2019-12-07 17:19:36,467 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:36,468 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [256980493] [2019-12-07 17:19:36,468 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:19:36,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:36,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:36,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:36,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:36,555 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2019-12-07 17:19:36,555 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [256980493] [2019-12-07 17:19:36,555 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [487449274] [2019-12-07 17:19:36,555 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:36,584 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 17:19:36,585 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:19:36,585 INFO L264 TraceCheckSpWp]: Trace formula consists of 163 conjuncts, 10 conjunts are in the unsatisfiable core [2019-12-07 17:19:36,587 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:19:36,605 INFO L430 ElimStorePlain]: Different costs {0=[|v_#length_12|], 1=[|v_#valid_24|]} [2019-12-07 17:19:36,611 INFO L189 IndexEqualityManager]: detected not equals via solver [2019-12-07 17:19:36,617 INFO L377 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 11 [2019-12-07 17:19:36,617 INFO L534 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-12-07 17:19:36,625 INFO L614 ElimStorePlain]: treesize reduction 0, result has 100.0 percent of original size [2019-12-07 17:19:36,626 INFO L189 IndexEqualityManager]: detected not equals via solver [2019-12-07 17:19:36,628 INFO L377 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 3 [2019-12-07 17:19:36,629 INFO L534 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2019-12-07 17:19:36,633 INFO L614 ElimStorePlain]: treesize reduction 0, result has 100.0 percent of original size [2019-12-07 17:19:36,634 INFO L534 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-12-07 17:19:36,634 INFO L239 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:24, output treesize:17 [2019-12-07 17:19:36,738 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2019-12-07 17:19:36,739 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:19:36,739 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 7 [2019-12-07 17:19:36,739 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [912765311] [2019-12-07 17:19:36,739 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 17:19:36,739 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:19:36,739 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 17:19:36,740 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2019-12-07 17:19:36,740 INFO L87 Difference]: Start difference. First operand 112 states and 126 transitions. Second operand 8 states. [2019-12-07 17:19:36,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:19:36,860 INFO L93 Difference]: Finished difference Result 112 states and 125 transitions. [2019-12-07 17:19:36,860 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 17:19:36,860 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 51 [2019-12-07 17:19:36,860 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:19:36,861 INFO L225 Difference]: With dead ends: 112 [2019-12-07 17:19:36,861 INFO L226 Difference]: Without dead ends: 112 [2019-12-07 17:19:36,861 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 52 SyntacticMatches, 4 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2019-12-07 17:19:36,862 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2019-12-07 17:19:36,864 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 112. [2019-12-07 17:19:36,864 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112 states. [2019-12-07 17:19:36,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 125 transitions. [2019-12-07 17:19:36,865 INFO L78 Accepts]: Start accepts. Automaton has 112 states and 125 transitions. Word has length 51 [2019-12-07 17:19:36,865 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:19:36,865 INFO L462 AbstractCegarLoop]: Abstraction has 112 states and 125 transitions. [2019-12-07 17:19:36,865 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 17:19:36,866 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 125 transitions. [2019-12-07 17:19:36,867 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2019-12-07 17:19:36,867 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:36,867 INFO L410 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 8, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:37,068 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:37,068 INFO L410 AbstractCegarLoop]: === Iteration 14 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:37,068 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:37,068 INFO L82 PathProgramCache]: Analyzing trace with hash 1240037378, now seen corresponding path program 2 times [2019-12-07 17:19:37,069 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:37,069 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [487091269] [2019-12-07 17:19:37,069 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:19:37,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:37,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:37,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:37,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:37,187 INFO L134 CoverageAnalysis]: Checked inductivity of 191 backedges. 113 proven. 13 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2019-12-07 17:19:37,187 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [487091269] [2019-12-07 17:19:37,188 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1933232660] [2019-12-07 17:19:37,188 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:37,229 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 17:19:37,230 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:19:37,230 INFO L264 TraceCheckSpWp]: Trace formula consists of 225 conjuncts, 9 conjunts are in the unsatisfiable core [2019-12-07 17:19:37,233 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:19:37,283 INFO L134 CoverageAnalysis]: Checked inductivity of 191 backedges. 93 proven. 21 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2019-12-07 17:19:37,283 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:19:37,284 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 5] total 15 [2019-12-07 17:19:37,284 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [968787335] [2019-12-07 17:19:37,284 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 17:19:37,284 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:19:37,284 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 17:19:37,284 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=198, Unknown=0, NotChecked=0, Total=240 [2019-12-07 17:19:37,285 INFO L87 Difference]: Start difference. First operand 112 states and 125 transitions. Second operand 16 states. [2019-12-07 17:19:37,646 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:19:37,646 INFO L93 Difference]: Finished difference Result 188 states and 199 transitions. [2019-12-07 17:19:37,647 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 17:19:37,647 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 73 [2019-12-07 17:19:37,647 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:19:37,648 INFO L225 Difference]: With dead ends: 188 [2019-12-07 17:19:37,648 INFO L226 Difference]: Without dead ends: 188 [2019-12-07 17:19:37,648 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 74 SyntacticMatches, 1 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 120 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=126, Invalid=576, Unknown=0, NotChecked=0, Total=702 [2019-12-07 17:19:37,649 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 188 states. [2019-12-07 17:19:37,652 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 137. [2019-12-07 17:19:37,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 137 states. [2019-12-07 17:19:37,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137 states to 137 states and 151 transitions. [2019-12-07 17:19:37,652 INFO L78 Accepts]: Start accepts. Automaton has 137 states and 151 transitions. Word has length 73 [2019-12-07 17:19:37,653 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:19:37,653 INFO L462 AbstractCegarLoop]: Abstraction has 137 states and 151 transitions. [2019-12-07 17:19:37,653 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 17:19:37,653 INFO L276 IsEmpty]: Start isEmpty. Operand 137 states and 151 transitions. [2019-12-07 17:19:37,654 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2019-12-07 17:19:37,654 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:37,654 INFO L410 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 8, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:37,854 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:37,855 INFO L410 AbstractCegarLoop]: === Iteration 15 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:37,855 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:37,856 INFO L82 PathProgramCache]: Analyzing trace with hash -976841143, now seen corresponding path program 3 times [2019-12-07 17:19:37,856 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:37,856 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1477688218] [2019-12-07 17:19:37,857 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:19:37,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:37,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:37,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:37,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:37,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:38,022 INFO L134 CoverageAnalysis]: Checked inductivity of 193 backedges. 70 proven. 102 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2019-12-07 17:19:38,023 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1477688218] [2019-12-07 17:19:38,023 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1273224462] [2019-12-07 17:19:38,023 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:38,050 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-12-07 17:19:38,050 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:19:38,050 INFO L264 TraceCheckSpWp]: Trace formula consists of 115 conjuncts, 8 conjunts are in the unsatisfiable core [2019-12-07 17:19:38,052 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:19:38,055 INFO L430 ElimStorePlain]: Different costs {0=[|v_#length_13|], 1=[|v_#valid_25|]} [2019-12-07 17:19:38,057 INFO L189 IndexEqualityManager]: detected not equals via solver [2019-12-07 17:19:38,058 INFO L377 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 11 [2019-12-07 17:19:38,058 INFO L534 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-12-07 17:19:38,064 INFO L614 ElimStorePlain]: treesize reduction 0, result has 100.0 percent of original size [2019-12-07 17:19:38,065 INFO L189 IndexEqualityManager]: detected not equals via solver [2019-12-07 17:19:38,066 INFO L377 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 3 [2019-12-07 17:19:38,067 INFO L534 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2019-12-07 17:19:38,070 INFO L614 ElimStorePlain]: treesize reduction 0, result has 100.0 percent of original size [2019-12-07 17:19:38,071 INFO L534 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-12-07 17:19:38,071 INFO L239 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:21, output treesize:14 [2019-12-07 17:19:38,283 INFO L134 CoverageAnalysis]: Checked inductivity of 193 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 183 trivial. 0 not checked. [2019-12-07 17:19:38,283 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-12-07 17:19:38,283 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [15] total 20 [2019-12-07 17:19:38,284 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1888247198] [2019-12-07 17:19:38,284 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 17:19:38,284 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:19:38,284 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 17:19:38,284 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=63, Invalid=317, Unknown=0, NotChecked=0, Total=380 [2019-12-07 17:19:38,284 INFO L87 Difference]: Start difference. First operand 137 states and 151 transitions. Second operand 7 states. [2019-12-07 17:19:38,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:19:38,332 INFO L93 Difference]: Finished difference Result 137 states and 147 transitions. [2019-12-07 17:19:38,332 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 17:19:38,332 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 77 [2019-12-07 17:19:38,332 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:19:38,333 INFO L225 Difference]: With dead ends: 137 [2019-12-07 17:19:38,333 INFO L226 Difference]: Without dead ends: 137 [2019-12-07 17:19:38,333 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 96 GetRequests, 73 SyntacticMatches, 5 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 114 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=63, Invalid=317, Unknown=0, NotChecked=0, Total=380 [2019-12-07 17:19:38,334 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 137 states. [2019-12-07 17:19:38,336 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 137 to 136. [2019-12-07 17:19:38,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 136 states. [2019-12-07 17:19:38,337 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 146 transitions. [2019-12-07 17:19:38,337 INFO L78 Accepts]: Start accepts. Automaton has 136 states and 146 transitions. Word has length 77 [2019-12-07 17:19:38,337 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:19:38,337 INFO L462 AbstractCegarLoop]: Abstraction has 136 states and 146 transitions. [2019-12-07 17:19:38,337 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 17:19:38,337 INFO L276 IsEmpty]: Start isEmpty. Operand 136 states and 146 transitions. [2019-12-07 17:19:38,339 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2019-12-07 17:19:38,339 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:38,339 INFO L410 BasicCegarLoop]: trace histogram [13, 12, 12, 12, 12, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:38,539 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:38,540 INFO L410 AbstractCegarLoop]: === Iteration 16 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:38,541 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:38,541 INFO L82 PathProgramCache]: Analyzing trace with hash -526178640, now seen corresponding path program 3 times [2019-12-07 17:19:38,541 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:38,542 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [165977107] [2019-12-07 17:19:38,542 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:19:38,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:38,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:38,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:38,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:38,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:38,704 INFO L134 CoverageAnalysis]: Checked inductivity of 435 backedges. 274 proven. 102 refuted. 0 times theorem prover too weak. 59 trivial. 0 not checked. [2019-12-07 17:19:38,704 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [165977107] [2019-12-07 17:19:38,704 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [435935851] [2019-12-07 17:19:38,704 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:38,740 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2019-12-07 17:19:38,740 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:19:38,741 INFO L264 TraceCheckSpWp]: Trace formula consists of 234 conjuncts, 10 conjunts are in the unsatisfiable core [2019-12-07 17:19:38,744 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:19:38,841 INFO L134 CoverageAnalysis]: Checked inductivity of 435 backedges. 207 proven. 28 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2019-12-07 17:19:38,841 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:19:38,841 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 10] total 24 [2019-12-07 17:19:38,841 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1670042224] [2019-12-07 17:19:38,842 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2019-12-07 17:19:38,842 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:19:38,842 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2019-12-07 17:19:38,842 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=486, Unknown=0, NotChecked=0, Total=552 [2019-12-07 17:19:38,842 INFO L87 Difference]: Start difference. First operand 136 states and 146 transitions. Second operand 24 states. [2019-12-07 17:19:39,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:19:39,695 INFO L93 Difference]: Finished difference Result 224 states and 237 transitions. [2019-12-07 17:19:39,695 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-12-07 17:19:39,695 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 104 [2019-12-07 17:19:39,696 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:19:39,697 INFO L225 Difference]: With dead ends: 224 [2019-12-07 17:19:39,697 INFO L226 Difference]: Without dead ends: 218 [2019-12-07 17:19:39,697 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 151 GetRequests, 106 SyntacticMatches, 0 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 442 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=399, Invalid=1763, Unknown=0, NotChecked=0, Total=2162 [2019-12-07 17:19:39,698 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 218 states. [2019-12-07 17:19:39,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 218 to 180. [2019-12-07 17:19:39,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 180 states. [2019-12-07 17:19:39,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 180 states to 180 states and 193 transitions. [2019-12-07 17:19:39,702 INFO L78 Accepts]: Start accepts. Automaton has 180 states and 193 transitions. Word has length 104 [2019-12-07 17:19:39,702 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:19:39,702 INFO L462 AbstractCegarLoop]: Abstraction has 180 states and 193 transitions. [2019-12-07 17:19:39,702 INFO L463 AbstractCegarLoop]: Interpolant automaton has 24 states. [2019-12-07 17:19:39,702 INFO L276 IsEmpty]: Start isEmpty. Operand 180 states and 193 transitions. [2019-12-07 17:19:39,703 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2019-12-07 17:19:39,703 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:39,703 INFO L410 BasicCegarLoop]: trace histogram [13, 13, 13, 13, 13, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:39,903 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:39,904 INFO L410 AbstractCegarLoop]: === Iteration 17 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:39,905 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:39,905 INFO L82 PathProgramCache]: Analyzing trace with hash -118889443, now seen corresponding path program 2 times [2019-12-07 17:19:39,906 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:39,906 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1753477991] [2019-12-07 17:19:39,906 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:19:39,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:39,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:39,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:39,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:39,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:39,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:40,028 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 229 proven. 34 refuted. 0 times theorem prover too weak. 249 trivial. 0 not checked. [2019-12-07 17:19:40,028 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1753477991] [2019-12-07 17:19:40,028 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [328038192] [2019-12-07 17:19:40,029 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:40,053 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2019-12-07 17:19:40,053 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:19:40,053 INFO L264 TraceCheckSpWp]: Trace formula consists of 49 conjuncts, 8 conjunts are in the unsatisfiable core [2019-12-07 17:19:40,055 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:19:40,057 INFO L430 ElimStorePlain]: Different costs {0=[|v_#length_14|], 1=[|v_#valid_26|]} [2019-12-07 17:19:40,061 INFO L189 IndexEqualityManager]: detected not equals via solver [2019-12-07 17:19:40,062 INFO L377 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 11 [2019-12-07 17:19:40,062 INFO L534 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-12-07 17:19:40,072 INFO L614 ElimStorePlain]: treesize reduction 0, result has 100.0 percent of original size [2019-12-07 17:19:40,074 INFO L189 IndexEqualityManager]: detected not equals via solver [2019-12-07 17:19:40,075 INFO L377 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 3 [2019-12-07 17:19:40,075 INFO L534 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2019-12-07 17:19:40,080 INFO L614 ElimStorePlain]: treesize reduction 0, result has 100.0 percent of original size [2019-12-07 17:19:40,080 INFO L534 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-12-07 17:19:40,080 INFO L239 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:21, output treesize:14 [2019-12-07 17:19:40,293 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 512 trivial. 0 not checked. [2019-12-07 17:19:40,294 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-12-07 17:19:40,294 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [11] total 15 [2019-12-07 17:19:40,294 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2133279811] [2019-12-07 17:19:40,294 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:19:40,294 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:19:40,295 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:19:40,295 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=165, Unknown=0, NotChecked=0, Total=210 [2019-12-07 17:19:40,295 INFO L87 Difference]: Start difference. First operand 180 states and 193 transitions. Second operand 6 states. [2019-12-07 17:19:40,333 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:19:40,333 INFO L93 Difference]: Finished difference Result 179 states and 192 transitions. [2019-12-07 17:19:40,333 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:19:40,333 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 119 [2019-12-07 17:19:40,333 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:19:40,334 INFO L225 Difference]: With dead ends: 179 [2019-12-07 17:19:40,334 INFO L226 Difference]: Without dead ends: 179 [2019-12-07 17:19:40,334 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 137 GetRequests, 117 SyntacticMatches, 7 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 74 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=165, Unknown=0, NotChecked=0, Total=210 [2019-12-07 17:19:40,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states. [2019-12-07 17:19:40,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 179. [2019-12-07 17:19:40,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 179 states. [2019-12-07 17:19:40,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 192 transitions. [2019-12-07 17:19:40,339 INFO L78 Accepts]: Start accepts. Automaton has 179 states and 192 transitions. Word has length 119 [2019-12-07 17:19:40,340 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:19:40,340 INFO L462 AbstractCegarLoop]: Abstraction has 179 states and 192 transitions. [2019-12-07 17:19:40,340 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:19:40,340 INFO L276 IsEmpty]: Start isEmpty. Operand 179 states and 192 transitions. [2019-12-07 17:19:40,340 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2019-12-07 17:19:40,341 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:40,341 INFO L410 BasicCegarLoop]: trace histogram [13, 13, 13, 13, 13, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:40,541 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:40,542 INFO L410 AbstractCegarLoop]: === Iteration 18 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:40,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:40,543 INFO L82 PathProgramCache]: Analyzing trace with hash 1512623851, now seen corresponding path program 1 times [2019-12-07 17:19:40,543 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:40,544 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1185191945] [2019-12-07 17:19:40,544 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:19:40,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:40,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:40,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:40,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:40,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:40,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:40,664 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 229 proven. 34 refuted. 0 times theorem prover too weak. 249 trivial. 0 not checked. [2019-12-07 17:19:40,664 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1185191945] [2019-12-07 17:19:40,665 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [876825558] [2019-12-07 17:19:40,665 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:40,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:40,710 INFO L264 TraceCheckSpWp]: Trace formula consists of 347 conjuncts, 12 conjunts are in the unsatisfiable core [2019-12-07 17:19:40,712 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:19:40,823 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 253 proven. 34 refuted. 0 times theorem prover too weak. 225 trivial. 0 not checked. [2019-12-07 17:19:40,823 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:19:40,823 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 12] total 20 [2019-12-07 17:19:40,823 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1278316558] [2019-12-07 17:19:40,824 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2019-12-07 17:19:40,824 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:19:40,824 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2019-12-07 17:19:40,824 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=79, Invalid=301, Unknown=0, NotChecked=0, Total=380 [2019-12-07 17:19:40,824 INFO L87 Difference]: Start difference. First operand 179 states and 192 transitions. Second operand 20 states. [2019-12-07 17:19:41,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:19:41,188 INFO L93 Difference]: Finished difference Result 267 states and 280 transitions. [2019-12-07 17:19:41,188 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 17:19:41,188 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 122 [2019-12-07 17:19:41,188 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:19:41,189 INFO L225 Difference]: With dead ends: 267 [2019-12-07 17:19:41,189 INFO L226 Difference]: Without dead ends: 264 [2019-12-07 17:19:41,190 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 158 GetRequests, 126 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 167 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=212, Invalid=910, Unknown=0, NotChecked=0, Total=1122 [2019-12-07 17:19:41,190 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 264 states. [2019-12-07 17:19:41,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 264 to 176. [2019-12-07 17:19:41,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 176 states. [2019-12-07 17:19:41,195 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 186 transitions. [2019-12-07 17:19:41,195 INFO L78 Accepts]: Start accepts. Automaton has 176 states and 186 transitions. Word has length 122 [2019-12-07 17:19:41,195 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:19:41,195 INFO L462 AbstractCegarLoop]: Abstraction has 176 states and 186 transitions. [2019-12-07 17:19:41,195 INFO L463 AbstractCegarLoop]: Interpolant automaton has 20 states. [2019-12-07 17:19:41,195 INFO L276 IsEmpty]: Start isEmpty. Operand 176 states and 186 transitions. [2019-12-07 17:19:41,196 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2019-12-07 17:19:41,196 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:41,196 INFO L410 BasicCegarLoop]: trace histogram [14, 14, 14, 14, 14, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:41,397 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:41,398 INFO L410 AbstractCegarLoop]: === Iteration 19 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:41,398 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:41,398 INFO L82 PathProgramCache]: Analyzing trace with hash -1295783610, now seen corresponding path program 2 times [2019-12-07 17:19:41,399 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:41,399 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1081928285] [2019-12-07 17:19:41,399 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:19:41,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:41,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:41,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:41,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:41,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:41,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:41,541 INFO L134 CoverageAnalysis]: Checked inductivity of 581 backedges. 277 proven. 55 refuted. 0 times theorem prover too weak. 249 trivial. 0 not checked. [2019-12-07 17:19:41,541 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1081928285] [2019-12-07 17:19:41,541 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1053624970] [2019-12-07 17:19:41,541 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:41,566 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2019-12-07 17:19:41,566 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:19:41,567 INFO L264 TraceCheckSpWp]: Trace formula consists of 59 conjuncts, 8 conjunts are in the unsatisfiable core [2019-12-07 17:19:41,568 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:19:41,602 INFO L343 Elim1Store]: treesize reduction 14, result has 50.0 percent of original size [2019-12-07 17:19:41,603 INFO L377 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 24 treesize of output 29 [2019-12-07 17:19:41,603 INFO L534 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-12-07 17:19:41,606 INFO L614 ElimStorePlain]: treesize reduction 0, result has 100.0 percent of original size [2019-12-07 17:19:41,607 INFO L534 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-12-07 17:19:41,607 INFO L239 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:23, output treesize:15 [2019-12-07 17:19:41,651 INFO L343 Elim1Store]: treesize reduction 14, result has 50.0 percent of original size [2019-12-07 17:19:41,651 INFO L377 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 24 treesize of output 29 [2019-12-07 17:19:41,651 INFO L534 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-12-07 17:19:41,654 INFO L614 ElimStorePlain]: treesize reduction 0, result has 100.0 percent of original size [2019-12-07 17:19:41,655 INFO L534 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-12-07 17:19:41,655 INFO L239 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:23, output treesize:15 [2019-12-07 17:19:41,703 INFO L343 Elim1Store]: treesize reduction 14, result has 50.0 percent of original size [2019-12-07 17:19:41,703 INFO L377 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 24 treesize of output 29 [2019-12-07 17:19:41,704 INFO L534 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-12-07 17:19:41,708 INFO L614 ElimStorePlain]: treesize reduction 0, result has 100.0 percent of original size [2019-12-07 17:19:41,708 INFO L534 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-12-07 17:19:41,708 INFO L239 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:23, output treesize:15 [2019-12-07 17:19:41,756 INFO L343 Elim1Store]: treesize reduction 14, result has 50.0 percent of original size [2019-12-07 17:19:41,756 INFO L377 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 24 treesize of output 29 [2019-12-07 17:19:41,756 INFO L534 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-12-07 17:19:41,761 INFO L614 ElimStorePlain]: treesize reduction 0, result has 100.0 percent of original size [2019-12-07 17:19:41,761 INFO L534 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-12-07 17:19:41,761 INFO L239 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:23, output treesize:15 [2019-12-07 17:19:41,886 INFO L134 CoverageAnalysis]: Checked inductivity of 581 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 581 trivial. 0 not checked. [2019-12-07 17:19:41,886 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-12-07 17:19:41,887 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [12] total 16 [2019-12-07 17:19:41,887 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1938907104] [2019-12-07 17:19:41,887 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:19:41,887 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:19:41,887 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:19:41,887 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=192, Unknown=0, NotChecked=0, Total=240 [2019-12-07 17:19:41,887 INFO L87 Difference]: Start difference. First operand 176 states and 186 transitions. Second operand 6 states. [2019-12-07 17:19:41,955 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:19:41,955 INFO L93 Difference]: Finished difference Result 175 states and 185 transitions. [2019-12-07 17:19:41,955 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 17:19:41,955 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 127 [2019-12-07 17:19:41,956 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:19:41,956 INFO L225 Difference]: With dead ends: 175 [2019-12-07 17:19:41,956 INFO L226 Difference]: Without dead ends: 154 [2019-12-07 17:19:41,957 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 147 GetRequests, 125 SyntacticMatches, 7 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 94 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=52, Invalid=220, Unknown=0, NotChecked=0, Total=272 [2019-12-07 17:19:41,957 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154 states. [2019-12-07 17:19:41,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154 to 154. [2019-12-07 17:19:41,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2019-12-07 17:19:41,960 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 159 transitions. [2019-12-07 17:19:41,960 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 159 transitions. Word has length 127 [2019-12-07 17:19:41,960 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:19:41,961 INFO L462 AbstractCegarLoop]: Abstraction has 154 states and 159 transitions. [2019-12-07 17:19:41,961 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:19:41,961 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 159 transitions. [2019-12-07 17:19:41,962 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2019-12-07 17:19:41,962 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:41,962 INFO L410 BasicCegarLoop]: trace histogram [20, 19, 19, 19, 19, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:42,162 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:42,163 INFO L410 AbstractCegarLoop]: === Iteration 20 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:42,163 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:42,164 INFO L82 PathProgramCache]: Analyzing trace with hash -1371846361, now seen corresponding path program 4 times [2019-12-07 17:19:42,164 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:42,164 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2059159420] [2019-12-07 17:19:42,165 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:19:42,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:42,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:42,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:42,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:42,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:42,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:42,433 INFO L134 CoverageAnalysis]: Checked inductivity of 1051 backedges. 461 proven. 49 refuted. 0 times theorem prover too weak. 541 trivial. 0 not checked. [2019-12-07 17:19:42,433 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2059159420] [2019-12-07 17:19:42,433 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2055052022] [2019-12-07 17:19:42,434 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:42,498 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 17:19:42,498 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:19:42,499 INFO L264 TraceCheckSpWp]: Trace formula consists of 423 conjuncts, 13 conjunts are in the unsatisfiable core [2019-12-07 17:19:42,501 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:19:42,574 INFO L134 CoverageAnalysis]: Checked inductivity of 1051 backedges. 402 proven. 60 refuted. 0 times theorem prover too weak. 589 trivial. 0 not checked. [2019-12-07 17:19:42,575 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:19:42,575 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 7] total 21 [2019-12-07 17:19:42,575 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [720770379] [2019-12-07 17:19:42,575 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2019-12-07 17:19:42,575 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:19:42,576 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2019-12-07 17:19:42,576 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=72, Invalid=390, Unknown=0, NotChecked=0, Total=462 [2019-12-07 17:19:42,576 INFO L87 Difference]: Start difference. First operand 154 states and 159 transitions. Second operand 22 states. [2019-12-07 17:19:43,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:19:43,058 INFO L93 Difference]: Finished difference Result 293 states and 311 transitions. [2019-12-07 17:19:43,058 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-12-07 17:19:43,058 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 150 [2019-12-07 17:19:43,059 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:19:43,060 INFO L225 Difference]: With dead ends: 293 [2019-12-07 17:19:43,060 INFO L226 Difference]: Without dead ends: 293 [2019-12-07 17:19:43,060 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 189 GetRequests, 153 SyntacticMatches, 1 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 261 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=195, Invalid=1137, Unknown=0, NotChecked=0, Total=1332 [2019-12-07 17:19:43,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 293 states. [2019-12-07 17:19:43,064 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 293 to 195. [2019-12-07 17:19:43,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 195 states. [2019-12-07 17:19:43,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 202 transitions. [2019-12-07 17:19:43,065 INFO L78 Accepts]: Start accepts. Automaton has 195 states and 202 transitions. Word has length 150 [2019-12-07 17:19:43,065 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:19:43,065 INFO L462 AbstractCegarLoop]: Abstraction has 195 states and 202 transitions. [2019-12-07 17:19:43,066 INFO L463 AbstractCegarLoop]: Interpolant automaton has 22 states. [2019-12-07 17:19:43,066 INFO L276 IsEmpty]: Start isEmpty. Operand 195 states and 202 transitions. [2019-12-07 17:19:43,067 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 192 [2019-12-07 17:19:43,067 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:43,067 INFO L410 BasicCegarLoop]: trace histogram [26, 25, 25, 25, 25, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:43,267 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:43,268 INFO L410 AbstractCegarLoop]: === Iteration 21 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:43,268 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:43,268 INFO L82 PathProgramCache]: Analyzing trace with hash 1382499467, now seen corresponding path program 5 times [2019-12-07 17:19:43,269 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:43,269 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [528652832] [2019-12-07 17:19:43,269 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:19:43,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:43,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:43,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:43,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:43,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:43,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:43,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:43,564 INFO L134 CoverageAnalysis]: Checked inductivity of 1805 backedges. 1058 proven. 272 refuted. 0 times theorem prover too weak. 475 trivial. 0 not checked. [2019-12-07 17:19:43,564 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [528652832] [2019-12-07 17:19:43,564 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [354257922] [2019-12-07 17:19:43,564 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:43,648 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2019-12-07 17:19:43,648 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:19:43,649 INFO L264 TraceCheckSpWp]: Trace formula consists of 467 conjuncts, 18 conjunts are in the unsatisfiable core [2019-12-07 17:19:43,651 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:19:43,820 INFO L134 CoverageAnalysis]: Checked inductivity of 1805 backedges. 1075 proven. 311 refuted. 0 times theorem prover too weak. 419 trivial. 0 not checked. [2019-12-07 17:19:43,820 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:19:43,820 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 17] total 29 [2019-12-07 17:19:43,820 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [511773172] [2019-12-07 17:19:43,821 INFO L442 AbstractCegarLoop]: Interpolant automaton has 29 states [2019-12-07 17:19:43,821 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:19:43,821 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2019-12-07 17:19:43,821 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=125, Invalid=687, Unknown=0, NotChecked=0, Total=812 [2019-12-07 17:19:43,821 INFO L87 Difference]: Start difference. First operand 195 states and 202 transitions. Second operand 29 states. [2019-12-07 17:19:44,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:19:44,763 INFO L93 Difference]: Finished difference Result 331 states and 355 transitions. [2019-12-07 17:19:44,764 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2019-12-07 17:19:44,764 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 191 [2019-12-07 17:19:44,765 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:19:44,769 INFO L225 Difference]: With dead ends: 331 [2019-12-07 17:19:44,769 INFO L226 Difference]: Without dead ends: 325 [2019-12-07 17:19:44,771 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 235 GetRequests, 192 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 367 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=423, Invalid=1557, Unknown=0, NotChecked=0, Total=1980 [2019-12-07 17:19:44,772 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 325 states. [2019-12-07 17:19:44,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 325 to 234. [2019-12-07 17:19:44,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 234 states. [2019-12-07 17:19:44,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 234 states to 234 states and 245 transitions. [2019-12-07 17:19:44,788 INFO L78 Accepts]: Start accepts. Automaton has 234 states and 245 transitions. Word has length 191 [2019-12-07 17:19:44,788 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:19:44,788 INFO L462 AbstractCegarLoop]: Abstraction has 234 states and 245 transitions. [2019-12-07 17:19:44,788 INFO L463 AbstractCegarLoop]: Interpolant automaton has 29 states. [2019-12-07 17:19:44,788 INFO L276 IsEmpty]: Start isEmpty. Operand 234 states and 245 transitions. [2019-12-07 17:19:44,790 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 197 [2019-12-07 17:19:44,790 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:44,790 INFO L410 BasicCegarLoop]: trace histogram [27, 26, 26, 26, 26, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:44,990 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:44,991 INFO L410 AbstractCegarLoop]: === Iteration 22 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:44,991 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:44,992 INFO L82 PathProgramCache]: Analyzing trace with hash 1146107562, now seen corresponding path program 6 times [2019-12-07 17:19:44,992 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:44,992 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1371047494] [2019-12-07 17:19:44,992 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:19:45,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:45,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:45,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:45,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:45,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:45,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:45,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:45,180 INFO L134 CoverageAnalysis]: Checked inductivity of 1937 backedges. 761 proven. 76 refuted. 0 times theorem prover too weak. 1100 trivial. 0 not checked. [2019-12-07 17:19:45,180 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1371047494] [2019-12-07 17:19:45,180 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [985713800] [2019-12-07 17:19:45,180 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:45,256 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2019-12-07 17:19:45,256 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:19:45,258 INFO L264 TraceCheckSpWp]: Trace formula consists of 396 conjuncts, 12 conjunts are in the unsatisfiable core [2019-12-07 17:19:45,260 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:19:45,304 INFO L134 CoverageAnalysis]: Checked inductivity of 1937 backedges. 701 proven. 76 refuted. 0 times theorem prover too weak. 1160 trivial. 0 not checked. [2019-12-07 17:19:45,305 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:19:45,305 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 12] total 20 [2019-12-07 17:19:45,305 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [503265074] [2019-12-07 17:19:45,305 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-12-07 17:19:45,305 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:19:45,305 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-12-07 17:19:45,306 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=89, Invalid=331, Unknown=0, NotChecked=0, Total=420 [2019-12-07 17:19:45,306 INFO L87 Difference]: Start difference. First operand 234 states and 245 transitions. Second operand 21 states. [2019-12-07 17:19:45,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:19:45,732 INFO L93 Difference]: Finished difference Result 367 states and 392 transitions. [2019-12-07 17:19:45,733 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-12-07 17:19:45,733 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 196 [2019-12-07 17:19:45,733 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:19:45,735 INFO L225 Difference]: With dead ends: 367 [2019-12-07 17:19:45,735 INFO L226 Difference]: Without dead ends: 367 [2019-12-07 17:19:45,735 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 239 GetRequests, 206 SyntacticMatches, 0 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 159 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=296, Invalid=894, Unknown=0, NotChecked=0, Total=1190 [2019-12-07 17:19:45,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 367 states. [2019-12-07 17:19:45,742 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 367 to 275. [2019-12-07 17:19:45,742 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 275 states. [2019-12-07 17:19:45,744 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 275 states to 275 states and 287 transitions. [2019-12-07 17:19:45,744 INFO L78 Accepts]: Start accepts. Automaton has 275 states and 287 transitions. Word has length 196 [2019-12-07 17:19:45,744 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:19:45,744 INFO L462 AbstractCegarLoop]: Abstraction has 275 states and 287 transitions. [2019-12-07 17:19:45,744 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-12-07 17:19:45,744 INFO L276 IsEmpty]: Start isEmpty. Operand 275 states and 287 transitions. [2019-12-07 17:19:45,745 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 238 [2019-12-07 17:19:45,745 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:45,746 INFO L410 BasicCegarLoop]: trace histogram [33, 32, 32, 32, 32, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:45,946 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 16 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:45,946 INFO L410 AbstractCegarLoop]: === Iteration 23 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:45,947 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:45,947 INFO L82 PathProgramCache]: Analyzing trace with hash 499852904, now seen corresponding path program 7 times [2019-12-07 17:19:45,947 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:45,948 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [535569373] [2019-12-07 17:19:45,948 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:19:46,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:46,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:46,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:46,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:46,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:46,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:46,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:46,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:46,312 INFO L134 CoverageAnalysis]: Checked inductivity of 2925 backedges. 1581 proven. 381 refuted. 0 times theorem prover too weak. 963 trivial. 0 not checked. [2019-12-07 17:19:46,312 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [535569373] [2019-12-07 17:19:46,312 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [537062721] [2019-12-07 17:19:46,312 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:46,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:46,378 INFO L264 TraceCheckSpWp]: Trace formula consists of 645 conjuncts, 16 conjunts are in the unsatisfiable core [2019-12-07 17:19:46,380 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:19:46,540 INFO L134 CoverageAnalysis]: Checked inductivity of 2925 backedges. 1652 proven. 81 refuted. 0 times theorem prover too weak. 1192 trivial. 0 not checked. [2019-12-07 17:19:46,540 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:19:46,540 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 16] total 28 [2019-12-07 17:19:46,540 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1797238145] [2019-12-07 17:19:46,541 INFO L442 AbstractCegarLoop]: Interpolant automaton has 28 states [2019-12-07 17:19:46,541 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:19:46,541 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2019-12-07 17:19:46,541 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=140, Invalid=616, Unknown=0, NotChecked=0, Total=756 [2019-12-07 17:19:46,541 INFO L87 Difference]: Start difference. First operand 275 states and 287 transitions. Second operand 28 states. [2019-12-07 17:19:46,990 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:19:46,990 INFO L93 Difference]: Finished difference Result 422 states and 455 transitions. [2019-12-07 17:19:46,990 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-12-07 17:19:46,990 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 237 [2019-12-07 17:19:46,991 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:19:46,992 INFO L225 Difference]: With dead ends: 422 [2019-12-07 17:19:46,992 INFO L226 Difference]: Without dead ends: 416 [2019-12-07 17:19:46,993 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 283 GetRequests, 243 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 312 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=389, Invalid=1333, Unknown=0, NotChecked=0, Total=1722 [2019-12-07 17:19:46,993 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 416 states. [2019-12-07 17:19:46,999 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 416 to 285. [2019-12-07 17:19:47,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 285 states. [2019-12-07 17:19:47,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 285 states to 285 states and 297 transitions. [2019-12-07 17:19:47,001 INFO L78 Accepts]: Start accepts. Automaton has 285 states and 297 transitions. Word has length 237 [2019-12-07 17:19:47,001 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:19:47,001 INFO L462 AbstractCegarLoop]: Abstraction has 285 states and 297 transitions. [2019-12-07 17:19:47,001 INFO L463 AbstractCegarLoop]: Interpolant automaton has 28 states. [2019-12-07 17:19:47,001 INFO L276 IsEmpty]: Start isEmpty. Operand 285 states and 297 transitions. [2019-12-07 17:19:47,002 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 248 [2019-12-07 17:19:47,003 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:47,003 INFO L410 BasicCegarLoop]: trace histogram [35, 34, 34, 34, 34, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:47,203 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 17 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:47,203 INFO L410 AbstractCegarLoop]: === Iteration 24 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:47,203 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:47,203 INFO L82 PathProgramCache]: Analyzing trace with hash -300291550, now seen corresponding path program 8 times [2019-12-07 17:19:47,204 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:47,204 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2080810077] [2019-12-07 17:19:47,204 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:19:47,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:47,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:47,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:47,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:47,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:47,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:47,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:47,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:47,439 INFO L134 CoverageAnalysis]: Checked inductivity of 3266 backedges. 1165 proven. 109 refuted. 0 times theorem prover too weak. 1992 trivial. 0 not checked. [2019-12-07 17:19:47,439 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2080810077] [2019-12-07 17:19:47,439 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [431549257] [2019-12-07 17:19:47,439 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:47,507 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 17:19:47,508 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:19:47,509 INFO L264 TraceCheckSpWp]: Trace formula consists of 669 conjuncts, 17 conjunts are in the unsatisfiable core [2019-12-07 17:19:47,511 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:19:47,630 INFO L134 CoverageAnalysis]: Checked inductivity of 3266 backedges. 1047 proven. 119 refuted. 0 times theorem prover too weak. 2100 trivial. 0 not checked. [2019-12-07 17:19:47,630 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:19:47,631 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 9] total 27 [2019-12-07 17:19:47,631 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1968251940] [2019-12-07 17:19:47,631 INFO L442 AbstractCegarLoop]: Interpolant automaton has 28 states [2019-12-07 17:19:47,631 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:19:47,631 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2019-12-07 17:19:47,632 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=110, Invalid=646, Unknown=0, NotChecked=0, Total=756 [2019-12-07 17:19:47,632 INFO L87 Difference]: Start difference. First operand 285 states and 297 transitions. Second operand 28 states. [2019-12-07 17:19:48,390 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:19:48,391 INFO L93 Difference]: Finished difference Result 506 states and 551 transitions. [2019-12-07 17:19:48,391 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2019-12-07 17:19:48,391 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 247 [2019-12-07 17:19:48,392 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:19:48,394 INFO L225 Difference]: With dead ends: 506 [2019-12-07 17:19:48,394 INFO L226 Difference]: Without dead ends: 506 [2019-12-07 17:19:48,395 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 298 GetRequests, 252 SyntacticMatches, 1 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 454 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=276, Invalid=1886, Unknown=0, NotChecked=0, Total=2162 [2019-12-07 17:19:48,396 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 506 states. [2019-12-07 17:19:48,405 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 506 to 336. [2019-12-07 17:19:48,406 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 336 states. [2019-12-07 17:19:48,407 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 336 states to 336 states and 350 transitions. [2019-12-07 17:19:48,407 INFO L78 Accepts]: Start accepts. Automaton has 336 states and 350 transitions. Word has length 247 [2019-12-07 17:19:48,408 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:19:48,408 INFO L462 AbstractCegarLoop]: Abstraction has 336 states and 350 transitions. [2019-12-07 17:19:48,408 INFO L463 AbstractCegarLoop]: Interpolant automaton has 28 states. [2019-12-07 17:19:48,408 INFO L276 IsEmpty]: Start isEmpty. Operand 336 states and 350 transitions. [2019-12-07 17:19:48,410 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 299 [2019-12-07 17:19:48,410 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:48,410 INFO L410 BasicCegarLoop]: trace histogram [43, 42, 42, 42, 42, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:48,610 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 18 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:48,611 INFO L410 AbstractCegarLoop]: === Iteration 25 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:48,611 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:48,611 INFO L82 PathProgramCache]: Analyzing trace with hash -1652634800, now seen corresponding path program 9 times [2019-12-07 17:19:48,611 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:48,611 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [134100855] [2019-12-07 17:19:48,611 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:19:48,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:48,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:48,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:48,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:48,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:48,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:48,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:48,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:48,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:48,939 INFO L134 CoverageAnalysis]: Checked inductivity of 4942 backedges. 2594 proven. 506 refuted. 0 times theorem prover too weak. 1842 trivial. 0 not checked. [2019-12-07 17:19:48,939 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [134100855] [2019-12-07 17:19:48,939 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [831525533] [2019-12-07 17:19:48,939 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:49,057 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2019-12-07 17:19:49,058 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:19:49,059 INFO L264 TraceCheckSpWp]: Trace formula consists of 474 conjuncts, 12 conjunts are in the unsatisfiable core [2019-12-07 17:19:49,064 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:19:49,255 INFO L134 CoverageAnalysis]: Checked inductivity of 4942 backedges. 1491 proven. 156 refuted. 0 times theorem prover too weak. 3295 trivial. 0 not checked. [2019-12-07 17:19:49,256 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:19:49,256 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 11] total 33 [2019-12-07 17:19:49,256 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1367679799] [2019-12-07 17:19:49,257 INFO L442 AbstractCegarLoop]: Interpolant automaton has 33 states [2019-12-07 17:19:49,257 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:19:49,257 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2019-12-07 17:19:49,257 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=179, Invalid=877, Unknown=0, NotChecked=0, Total=1056 [2019-12-07 17:19:49,257 INFO L87 Difference]: Start difference. First operand 336 states and 350 transitions. Second operand 33 states. [2019-12-07 17:19:49,893 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:19:49,893 INFO L93 Difference]: Finished difference Result 594 states and 648 transitions. [2019-12-07 17:19:49,894 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-12-07 17:19:49,894 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 298 [2019-12-07 17:19:49,894 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:19:49,896 INFO L225 Difference]: With dead ends: 594 [2019-12-07 17:19:49,896 INFO L226 Difference]: Without dead ends: 588 [2019-12-07 17:19:49,897 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 351 GetRequests, 303 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 490 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=542, Invalid=1908, Unknown=0, NotChecked=0, Total=2450 [2019-12-07 17:19:49,897 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 588 states. [2019-12-07 17:19:49,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 588 to 346. [2019-12-07 17:19:49,906 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 346 states. [2019-12-07 17:19:49,907 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 346 states to 346 states and 360 transitions. [2019-12-07 17:19:49,907 INFO L78 Accepts]: Start accepts. Automaton has 346 states and 360 transitions. Word has length 298 [2019-12-07 17:19:49,907 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:19:49,907 INFO L462 AbstractCegarLoop]: Abstraction has 346 states and 360 transitions. [2019-12-07 17:19:49,907 INFO L463 AbstractCegarLoop]: Interpolant automaton has 33 states. [2019-12-07 17:19:49,907 INFO L276 IsEmpty]: Start isEmpty. Operand 346 states and 360 transitions. [2019-12-07 17:19:49,909 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 309 [2019-12-07 17:19:49,909 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:49,909 INFO L410 BasicCegarLoop]: trace histogram [45, 44, 44, 44, 44, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:50,110 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 19 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:50,110 INFO L410 AbstractCegarLoop]: === Iteration 26 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:50,110 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:50,110 INFO L82 PathProgramCache]: Analyzing trace with hash 699884682, now seen corresponding path program 10 times [2019-12-07 17:19:50,110 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:50,110 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1805354541] [2019-12-07 17:19:50,111 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:19:50,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:50,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:50,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:50,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:50,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:50,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:50,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:50,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:50,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:50,382 INFO L134 CoverageAnalysis]: Checked inductivity of 5385 backedges. 1903 proven. 157 refuted. 0 times theorem prover too weak. 3325 trivial. 0 not checked. [2019-12-07 17:19:50,382 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1805354541] [2019-12-07 17:19:50,383 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1141251625] [2019-12-07 17:19:50,383 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:50,455 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 17:19:50,455 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:19:50,457 INFO L264 TraceCheckSpWp]: Trace formula consists of 695 conjuncts, 26 conjunts are in the unsatisfiable core [2019-12-07 17:19:50,460 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:19:50,786 INFO L134 CoverageAnalysis]: Checked inductivity of 5385 backedges. 1832 proven. 634 refuted. 0 times theorem prover too weak. 2919 trivial. 0 not checked. [2019-12-07 17:19:50,786 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:19:50,787 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 25] total 38 [2019-12-07 17:19:50,787 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [817285125] [2019-12-07 17:19:50,787 INFO L442 AbstractCegarLoop]: Interpolant automaton has 38 states [2019-12-07 17:19:50,787 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:19:50,787 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2019-12-07 17:19:50,788 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=268, Invalid=1138, Unknown=0, NotChecked=0, Total=1406 [2019-12-07 17:19:50,788 INFO L87 Difference]: Start difference. First operand 346 states and 360 transitions. Second operand 38 states. [2019-12-07 17:19:51,610 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:19:51,611 INFO L93 Difference]: Finished difference Result 543 states and 567 transitions. [2019-12-07 17:19:51,611 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2019-12-07 17:19:51,611 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 308 [2019-12-07 17:19:51,611 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:19:51,613 INFO L225 Difference]: With dead ends: 543 [2019-12-07 17:19:51,613 INFO L226 Difference]: Without dead ends: 543 [2019-12-07 17:19:51,614 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 370 GetRequests, 309 SyntacticMatches, 0 SemanticMatches, 61 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 825 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=769, Invalid=3137, Unknown=0, NotChecked=0, Total=3906 [2019-12-07 17:19:51,614 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 543 states. [2019-12-07 17:19:51,619 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 543 to 473. [2019-12-07 17:19:51,619 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 473 states. [2019-12-07 17:19:51,621 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 473 states to 473 states and 497 transitions. [2019-12-07 17:19:51,621 INFO L78 Accepts]: Start accepts. Automaton has 473 states and 497 transitions. Word has length 308 [2019-12-07 17:19:51,621 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:19:51,621 INFO L462 AbstractCegarLoop]: Abstraction has 473 states and 497 transitions. [2019-12-07 17:19:51,621 INFO L463 AbstractCegarLoop]: Interpolant automaton has 38 states. [2019-12-07 17:19:51,621 INFO L276 IsEmpty]: Start isEmpty. Operand 473 states and 497 transitions. [2019-12-07 17:19:51,623 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 360 [2019-12-07 17:19:51,623 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:51,623 INFO L410 BasicCegarLoop]: trace histogram [53, 52, 52, 52, 52, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:51,823 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 20 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:51,824 INFO L410 AbstractCegarLoop]: === Iteration 27 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:51,824 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:51,824 INFO L82 PathProgramCache]: Analyzing trace with hash -1109948414, now seen corresponding path program 11 times [2019-12-07 17:19:51,825 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:51,825 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [884504199] [2019-12-07 17:19:51,825 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:19:51,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:51,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:51,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:51,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:51,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:51,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:51,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:51,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:51,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:51,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:52,201 INFO L134 CoverageAnalysis]: Checked inductivity of 7490 backedges. 3719 proven. 647 refuted. 0 times theorem prover too weak. 3124 trivial. 0 not checked. [2019-12-07 17:19:52,201 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [884504199] [2019-12-07 17:19:52,201 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1325320858] [2019-12-07 17:19:52,201 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:52,382 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 20 check-sat command(s) [2019-12-07 17:19:52,382 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:19:52,384 INFO L264 TraceCheckSpWp]: Trace formula consists of 890 conjuncts, 24 conjunts are in the unsatisfiable core [2019-12-07 17:19:52,387 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:19:52,714 INFO L134 CoverageAnalysis]: Checked inductivity of 7490 backedges. 3721 proven. 809 refuted. 0 times theorem prover too weak. 2960 trivial. 0 not checked. [2019-12-07 17:19:52,714 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:19:52,715 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 24] total 39 [2019-12-07 17:19:52,715 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [239641164] [2019-12-07 17:19:52,715 INFO L442 AbstractCegarLoop]: Interpolant automaton has 39 states [2019-12-07 17:19:52,715 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:19:52,715 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2019-12-07 17:19:52,716 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=244, Invalid=1238, Unknown=0, NotChecked=0, Total=1482 [2019-12-07 17:19:52,716 INFO L87 Difference]: Start difference. First operand 473 states and 497 transitions. Second operand 39 states. [2019-12-07 17:19:53,641 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:19:53,641 INFO L93 Difference]: Finished difference Result 545 states and 567 transitions. [2019-12-07 17:19:53,642 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2019-12-07 17:19:53,642 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 359 [2019-12-07 17:19:53,642 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:19:53,644 INFO L225 Difference]: With dead ends: 545 [2019-12-07 17:19:53,645 INFO L226 Difference]: Without dead ends: 539 [2019-12-07 17:19:53,646 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 421 GetRequests, 362 SyntacticMatches, 0 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 766 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=793, Invalid=2867, Unknown=0, NotChecked=0, Total=3660 [2019-12-07 17:19:53,647 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 539 states. [2019-12-07 17:19:53,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 539 to 473. [2019-12-07 17:19:53,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 473 states. [2019-12-07 17:19:53,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 473 states to 473 states and 495 transitions. [2019-12-07 17:19:53,655 INFO L78 Accepts]: Start accepts. Automaton has 473 states and 495 transitions. Word has length 359 [2019-12-07 17:19:53,656 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:19:53,656 INFO L462 AbstractCegarLoop]: Abstraction has 473 states and 495 transitions. [2019-12-07 17:19:53,656 INFO L463 AbstractCegarLoop]: Interpolant automaton has 39 states. [2019-12-07 17:19:53,656 INFO L276 IsEmpty]: Start isEmpty. Operand 473 states and 495 transitions. [2019-12-07 17:19:53,658 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 365 [2019-12-07 17:19:53,658 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:53,659 INFO L410 BasicCegarLoop]: trace histogram [54, 53, 53, 53, 53, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:53,859 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 21 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:53,859 INFO L410 AbstractCegarLoop]: === Iteration 28 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:53,859 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:53,860 INFO L82 PathProgramCache]: Analyzing trace with hash -1526039033, now seen corresponding path program 12 times [2019-12-07 17:19:53,860 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:53,860 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1982742419] [2019-12-07 17:19:53,860 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:19:53,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:54,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:54,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:54,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:54,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:54,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:54,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:54,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:54,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:54,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:54,256 INFO L134 CoverageAnalysis]: Checked inductivity of 7760 backedges. 2345 proven. 193 refuted. 0 times theorem prover too weak. 5222 trivial. 0 not checked. [2019-12-07 17:19:54,256 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1982742419] [2019-12-07 17:19:54,256 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [880536220] [2019-12-07 17:19:54,257 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:54,413 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 16 check-sat command(s) [2019-12-07 17:19:54,413 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:19:54,415 INFO L264 TraceCheckSpWp]: Trace formula consists of 807 conjuncts, 15 conjunts are in the unsatisfiable core [2019-12-07 17:19:54,418 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:19:54,512 INFO L134 CoverageAnalysis]: Checked inductivity of 7760 backedges. 2189 proven. 193 refuted. 0 times theorem prover too weak. 5378 trivial. 0 not checked. [2019-12-07 17:19:54,512 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:19:54,512 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 15] total 26 [2019-12-07 17:19:54,512 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1254891960] [2019-12-07 17:19:54,513 INFO L442 AbstractCegarLoop]: Interpolant automaton has 27 states [2019-12-07 17:19:54,513 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:19:54,513 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2019-12-07 17:19:54,513 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=152, Invalid=550, Unknown=0, NotChecked=0, Total=702 [2019-12-07 17:19:54,513 INFO L87 Difference]: Start difference. First operand 473 states and 495 transitions. Second operand 27 states. [2019-12-07 17:19:55,216 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:19:55,216 INFO L93 Difference]: Finished difference Result 600 states and 623 transitions. [2019-12-07 17:19:55,216 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2019-12-07 17:19:55,217 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 364 [2019-12-07 17:19:55,217 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:19:55,219 INFO L225 Difference]: With dead ends: 600 [2019-12-07 17:19:55,219 INFO L226 Difference]: Without dead ends: 600 [2019-12-07 17:19:55,219 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 425 GetRequests, 380 SyntacticMatches, 0 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 306 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=524, Invalid=1638, Unknown=0, NotChecked=0, Total=2162 [2019-12-07 17:19:55,220 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 600 states. [2019-12-07 17:19:55,224 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 600 to 529. [2019-12-07 17:19:55,225 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 529 states. [2019-12-07 17:19:55,226 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 529 states to 529 states and 552 transitions. [2019-12-07 17:19:55,226 INFO L78 Accepts]: Start accepts. Automaton has 529 states and 552 transitions. Word has length 364 [2019-12-07 17:19:55,227 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:19:55,227 INFO L462 AbstractCegarLoop]: Abstraction has 529 states and 552 transitions. [2019-12-07 17:19:55,227 INFO L463 AbstractCegarLoop]: Interpolant automaton has 27 states. [2019-12-07 17:19:55,227 INFO L276 IsEmpty]: Start isEmpty. Operand 529 states and 552 transitions. [2019-12-07 17:19:55,229 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 421 [2019-12-07 17:19:55,229 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:55,229 INFO L410 BasicCegarLoop]: trace histogram [63, 62, 62, 62, 62, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:55,429 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 22 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:55,430 INFO L410 AbstractCegarLoop]: === Iteration 29 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:55,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:55,430 INFO L82 PathProgramCache]: Analyzing trace with hash -645464956, now seen corresponding path program 13 times [2019-12-07 17:19:55,430 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:55,431 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1279631500] [2019-12-07 17:19:55,431 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:19:55,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:55,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:55,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:55,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:55,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:55,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:55,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:55,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:55,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:55,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:55,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:55,870 INFO L134 CoverageAnalysis]: Checked inductivity of 10569 backedges. 4848 proven. 804 refuted. 0 times theorem prover too weak. 4917 trivial. 0 not checked. [2019-12-07 17:19:55,870 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1279631500] [2019-12-07 17:19:55,871 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [183599035] [2019-12-07 17:19:55,871 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:55,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:55,963 INFO L264 TraceCheckSpWp]: Trace formula consists of 1104 conjuncts, 22 conjunts are in the unsatisfiable core [2019-12-07 17:19:55,966 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:19:56,267 INFO L134 CoverageAnalysis]: Checked inductivity of 10569 backedges. 4952 proven. 189 refuted. 0 times theorem prover too weak. 5428 trivial. 0 not checked. [2019-12-07 17:19:56,268 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:19:56,268 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 22] total 37 [2019-12-07 17:19:56,268 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [955448622] [2019-12-07 17:19:56,269 INFO L442 AbstractCegarLoop]: Interpolant automaton has 37 states [2019-12-07 17:19:56,269 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:19:56,269 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2019-12-07 17:19:56,270 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=254, Invalid=1078, Unknown=0, NotChecked=0, Total=1332 [2019-12-07 17:19:56,270 INFO L87 Difference]: Start difference. First operand 529 states and 552 transitions. Second operand 37 states. [2019-12-07 17:19:56,971 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:19:56,971 INFO L93 Difference]: Finished difference Result 615 states and 638 transitions. [2019-12-07 17:19:56,971 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2019-12-07 17:19:56,972 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 420 [2019-12-07 17:19:56,972 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:19:56,974 INFO L225 Difference]: With dead ends: 615 [2019-12-07 17:19:56,974 INFO L226 Difference]: Without dead ends: 609 [2019-12-07 17:19:56,975 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 484 GetRequests, 429 SyntacticMatches, 0 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 657 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=716, Invalid=2476, Unknown=0, NotChecked=0, Total=3192 [2019-12-07 17:19:56,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 609 states. [2019-12-07 17:19:56,981 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 609 to 539. [2019-12-07 17:19:56,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 539 states. [2019-12-07 17:19:56,983 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 539 states to 539 states and 562 transitions. [2019-12-07 17:19:56,983 INFO L78 Accepts]: Start accepts. Automaton has 539 states and 562 transitions. Word has length 420 [2019-12-07 17:19:56,984 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:19:56,984 INFO L462 AbstractCegarLoop]: Abstraction has 539 states and 562 transitions. [2019-12-07 17:19:56,984 INFO L463 AbstractCegarLoop]: Interpolant automaton has 37 states. [2019-12-07 17:19:56,984 INFO L276 IsEmpty]: Start isEmpty. Operand 539 states and 562 transitions. [2019-12-07 17:19:56,987 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 431 [2019-12-07 17:19:56,987 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:56,987 INFO L410 BasicCegarLoop]: trace histogram [65, 64, 64, 64, 64, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:57,187 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 23 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:57,188 INFO L410 AbstractCegarLoop]: === Iteration 30 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:57,188 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:57,188 INFO L82 PathProgramCache]: Analyzing trace with hash -867500726, now seen corresponding path program 14 times [2019-12-07 17:19:57,188 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:57,188 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [442408694] [2019-12-07 17:19:57,188 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:19:57,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:57,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:57,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:57,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:57,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:57,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:57,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:57,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:57,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:57,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:57,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:19:57,578 INFO L134 CoverageAnalysis]: Checked inductivity of 11216 backedges. 3151 proven. 244 refuted. 0 times theorem prover too weak. 7821 trivial. 0 not checked. [2019-12-07 17:19:57,578 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [442408694] [2019-12-07 17:19:57,579 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [680058252] [2019-12-07 17:19:57,579 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:57,686 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 17:19:57,686 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:19:57,689 INFO L264 TraceCheckSpWp]: Trace formula consists of 1128 conjuncts, 23 conjunts are in the unsatisfiable core [2019-12-07 17:19:57,692 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:19:57,923 INFO L134 CoverageAnalysis]: Checked inductivity of 11216 backedges. 2907 proven. 245 refuted. 0 times theorem prover too weak. 8064 trivial. 0 not checked. [2019-12-07 17:19:57,923 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:19:57,923 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 12] total 36 [2019-12-07 17:19:57,924 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [280085586] [2019-12-07 17:19:57,924 INFO L442 AbstractCegarLoop]: Interpolant automaton has 37 states [2019-12-07 17:19:57,924 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:19:57,924 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2019-12-07 17:19:57,925 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=182, Invalid=1150, Unknown=0, NotChecked=0, Total=1332 [2019-12-07 17:19:57,925 INFO L87 Difference]: Start difference. First operand 539 states and 562 transitions. Second operand 37 states. [2019-12-07 17:19:59,771 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:19:59,771 INFO L93 Difference]: Finished difference Result 694 states and 721 transitions. [2019-12-07 17:19:59,771 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2019-12-07 17:19:59,771 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 430 [2019-12-07 17:19:59,772 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:19:59,774 INFO L225 Difference]: With dead ends: 694 [2019-12-07 17:19:59,774 INFO L226 Difference]: Without dead ends: 694 [2019-12-07 17:19:59,775 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 499 GetRequests, 438 SyntacticMatches, 1 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 841 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=420, Invalid=3362, Unknown=0, NotChecked=0, Total=3782 [2019-12-07 17:19:59,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 694 states. [2019-12-07 17:19:59,783 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 694 to 605. [2019-12-07 17:19:59,783 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 605 states. [2019-12-07 17:19:59,786 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 605 states to 605 states and 630 transitions. [2019-12-07 17:19:59,786 INFO L78 Accepts]: Start accepts. Automaton has 605 states and 630 transitions. Word has length 430 [2019-12-07 17:19:59,786 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:19:59,786 INFO L462 AbstractCegarLoop]: Abstraction has 605 states and 630 transitions. [2019-12-07 17:19:59,786 INFO L463 AbstractCegarLoop]: Interpolant automaton has 37 states. [2019-12-07 17:19:59,787 INFO L276 IsEmpty]: Start isEmpty. Operand 605 states and 630 transitions. [2019-12-07 17:19:59,790 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 497 [2019-12-07 17:19:59,790 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:19:59,791 INFO L410 BasicCegarLoop]: trace histogram [76, 75, 75, 75, 75, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:19:59,991 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 24 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:19:59,991 INFO L410 AbstractCegarLoop]: === Iteration 31 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:19:59,991 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:19:59,991 INFO L82 PathProgramCache]: Analyzing trace with hash -1675425945, now seen corresponding path program 15 times [2019-12-07 17:19:59,992 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:19:59,992 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [969126433] [2019-12-07 17:19:59,992 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:20:00,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:00,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:00,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:00,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:00,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:00,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:00,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:00,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:00,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:00,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:00,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:00,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:00,500 INFO L134 CoverageAnalysis]: Checked inductivity of 15310 backedges. 6833 proven. 977 refuted. 0 times theorem prover too weak. 7500 trivial. 0 not checked. [2019-12-07 17:20:00,500 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [969126433] [2019-12-07 17:20:00,500 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1846990026] [2019-12-07 17:20:00,500 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:20:00,617 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2019-12-07 17:20:00,617 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:20:00,619 INFO L264 TraceCheckSpWp]: Trace formula consists of 618 conjuncts, 21 conjunts are in the unsatisfiable core [2019-12-07 17:20:00,622 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:20:01,134 INFO L134 CoverageAnalysis]: Checked inductivity of 15310 backedges. 6173 proven. 828 refuted. 0 times theorem prover too weak. 8309 trivial. 0 not checked. [2019-12-07 17:20:01,135 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:20:01,135 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 20] total 47 [2019-12-07 17:20:01,135 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2128022653] [2019-12-07 17:20:01,136 INFO L442 AbstractCegarLoop]: Interpolant automaton has 47 states [2019-12-07 17:20:01,136 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:20:01,136 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2019-12-07 17:20:01,137 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=319, Invalid=1843, Unknown=0, NotChecked=0, Total=2162 [2019-12-07 17:20:01,137 INFO L87 Difference]: Start difference. First operand 605 states and 630 transitions. Second operand 47 states. [2019-12-07 17:20:02,978 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:20:02,978 INFO L93 Difference]: Finished difference Result 764 states and 791 transitions. [2019-12-07 17:20:02,979 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2019-12-07 17:20:02,979 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 496 [2019-12-07 17:20:02,979 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:20:02,981 INFO L225 Difference]: With dead ends: 764 [2019-12-07 17:20:02,981 INFO L226 Difference]: Without dead ends: 758 [2019-12-07 17:20:02,985 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 600 GetRequests, 499 SyntacticMatches, 0 SemanticMatches, 101 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2578 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=1799, Invalid=8707, Unknown=0, NotChecked=0, Total=10506 [2019-12-07 17:20:02,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 758 states. [2019-12-07 17:20:02,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 758 to 610. [2019-12-07 17:20:02,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 610 states. [2019-12-07 17:20:02,994 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 610 states to 610 states and 634 transitions. [2019-12-07 17:20:02,994 INFO L78 Accepts]: Start accepts. Automaton has 610 states and 634 transitions. Word has length 496 [2019-12-07 17:20:02,995 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:20:02,995 INFO L462 AbstractCegarLoop]: Abstraction has 610 states and 634 transitions. [2019-12-07 17:20:02,995 INFO L463 AbstractCegarLoop]: Interpolant automaton has 47 states. [2019-12-07 17:20:02,995 INFO L276 IsEmpty]: Start isEmpty. Operand 610 states and 634 transitions. [2019-12-07 17:20:02,998 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 502 [2019-12-07 17:20:02,998 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:20:02,998 INFO L410 BasicCegarLoop]: trace histogram [77, 76, 76, 76, 76, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:20:03,199 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 25 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:20:03,199 INFO L410 AbstractCegarLoop]: === Iteration 32 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:20:03,199 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:20:03,200 INFO L82 PathProgramCache]: Analyzing trace with hash -422752958, now seen corresponding path program 16 times [2019-12-07 17:20:03,200 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:20:03,200 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [553216774] [2019-12-07 17:20:03,200 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:20:03,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:03,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:03,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:03,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:03,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:03,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:03,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:03,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:03,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:03,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:03,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:03,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:03,688 INFO L134 CoverageAnalysis]: Checked inductivity of 15697 backedges. 4121 proven. 301 refuted. 0 times theorem prover too weak. 11275 trivial. 0 not checked. [2019-12-07 17:20:03,689 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [553216774] [2019-12-07 17:20:03,689 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1678437766] [2019-12-07 17:20:03,689 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:20:03,893 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 17:20:03,893 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:20:03,896 INFO L264 TraceCheckSpWp]: Trace formula consists of 1305 conjuncts, 25 conjunts are in the unsatisfiable core [2019-12-07 17:20:03,902 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:20:04,209 INFO L134 CoverageAnalysis]: Checked inductivity of 15697 backedges. 3825 proven. 297 refuted. 0 times theorem prover too weak. 11575 trivial. 0 not checked. [2019-12-07 17:20:04,209 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:20:04,209 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 13] total 39 [2019-12-07 17:20:04,209 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1403865748] [2019-12-07 17:20:04,210 INFO L442 AbstractCegarLoop]: Interpolant automaton has 40 states [2019-12-07 17:20:04,210 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:20:04,210 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2019-12-07 17:20:04,211 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=210, Invalid=1350, Unknown=0, NotChecked=0, Total=1560 [2019-12-07 17:20:04,211 INFO L87 Difference]: Start difference. First operand 610 states and 634 transitions. Second operand 40 states. [2019-12-07 17:20:05,506 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:20:05,506 INFO L93 Difference]: Finished difference Result 786 states and 816 transitions. [2019-12-07 17:20:05,506 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2019-12-07 17:20:05,506 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 501 [2019-12-07 17:20:05,507 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:20:05,509 INFO L225 Difference]: With dead ends: 786 [2019-12-07 17:20:05,509 INFO L226 Difference]: Without dead ends: 786 [2019-12-07 17:20:05,509 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 576 GetRequests, 510 SyntacticMatches, 1 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 996 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=474, Invalid=3948, Unknown=0, NotChecked=0, Total=4422 [2019-12-07 17:20:05,510 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 786 states. [2019-12-07 17:20:05,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 786 to 681. [2019-12-07 17:20:05,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 681 states. [2019-12-07 17:20:05,518 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 681 states and 707 transitions. [2019-12-07 17:20:05,518 INFO L78 Accepts]: Start accepts. Automaton has 681 states and 707 transitions. Word has length 501 [2019-12-07 17:20:05,518 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:20:05,518 INFO L462 AbstractCegarLoop]: Abstraction has 681 states and 707 transitions. [2019-12-07 17:20:05,518 INFO L463 AbstractCegarLoop]: Interpolant automaton has 40 states. [2019-12-07 17:20:05,519 INFO L276 IsEmpty]: Start isEmpty. Operand 681 states and 707 transitions. [2019-12-07 17:20:05,523 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 573 [2019-12-07 17:20:05,523 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:20:05,523 INFO L410 BasicCegarLoop]: trace histogram [89, 88, 88, 88, 88, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:20:05,723 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 26 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:20:05,724 INFO L410 AbstractCegarLoop]: === Iteration 33 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:20:05,724 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:20:05,724 INFO L82 PathProgramCache]: Analyzing trace with hash -347201808, now seen corresponding path program 17 times [2019-12-07 17:20:05,724 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:20:05,724 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1357978573] [2019-12-07 17:20:05,724 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:20:05,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:05,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:05,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:05,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:05,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:05,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:05,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:05,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:05,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:05,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:05,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:05,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:05,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:06,319 INFO L134 CoverageAnalysis]: Checked inductivity of 20933 backedges. 8882 proven. 1166 refuted. 0 times theorem prover too weak. 10885 trivial. 0 not checked. [2019-12-07 17:20:06,319 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1357978573] [2019-12-07 17:20:06,320 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1810329661] [2019-12-07 17:20:06,320 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:20:06,723 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 24 check-sat command(s) [2019-12-07 17:20:06,723 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:20:06,728 INFO L264 TraceCheckSpWp]: Trace formula consists of 1421 conjuncts, 30 conjunts are in the unsatisfiable core [2019-12-07 17:20:06,732 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:20:07,282 INFO L134 CoverageAnalysis]: Checked inductivity of 20933 backedges. 8869 proven. 1496 refuted. 0 times theorem prover too weak. 10568 trivial. 0 not checked. [2019-12-07 17:20:07,282 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:20:07,282 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 30] total 48 [2019-12-07 17:20:07,283 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [473085774] [2019-12-07 17:20:07,283 INFO L442 AbstractCegarLoop]: Interpolant automaton has 48 states [2019-12-07 17:20:07,283 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:20:07,283 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2019-12-07 17:20:07,284 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=385, Invalid=1871, Unknown=0, NotChecked=0, Total=2256 [2019-12-07 17:20:07,284 INFO L87 Difference]: Start difference. First operand 681 states and 707 transitions. Second operand 48 states. [2019-12-07 17:20:09,962 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:20:09,962 INFO L93 Difference]: Finished difference Result 794 states and 822 transitions. [2019-12-07 17:20:09,962 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2019-12-07 17:20:09,962 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 572 [2019-12-07 17:20:09,963 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:20:09,965 INFO L225 Difference]: With dead ends: 794 [2019-12-07 17:20:09,966 INFO L226 Difference]: Without dead ends: 788 [2019-12-07 17:20:09,966 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 652 GetRequests, 578 SyntacticMatches, 0 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1270 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=1234, Invalid=4466, Unknown=0, NotChecked=0, Total=5700 [2019-12-07 17:20:09,967 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 788 states. [2019-12-07 17:20:09,973 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 788 to 686. [2019-12-07 17:20:09,973 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 686 states. [2019-12-07 17:20:09,975 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 711 transitions. [2019-12-07 17:20:09,975 INFO L78 Accepts]: Start accepts. Automaton has 686 states and 711 transitions. Word has length 572 [2019-12-07 17:20:09,976 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:20:09,976 INFO L462 AbstractCegarLoop]: Abstraction has 686 states and 711 transitions. [2019-12-07 17:20:09,976 INFO L463 AbstractCegarLoop]: Interpolant automaton has 48 states. [2019-12-07 17:20:09,976 INFO L276 IsEmpty]: Start isEmpty. Operand 686 states and 711 transitions. [2019-12-07 17:20:09,980 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 578 [2019-12-07 17:20:09,980 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:20:09,980 INFO L410 BasicCegarLoop]: trace histogram [90, 89, 89, 89, 89, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:20:10,181 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 27 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:20:10,181 INFO L410 AbstractCegarLoop]: === Iteration 34 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:20:10,182 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:20:10,182 INFO L82 PathProgramCache]: Analyzing trace with hash 35953893, now seen corresponding path program 18 times [2019-12-07 17:20:10,182 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:20:10,183 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [50988934] [2019-12-07 17:20:10,183 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:20:10,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:10,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:10,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:10,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:10,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:10,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:10,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:10,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:10,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:10,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:10,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:10,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:10,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:10,759 INFO L134 CoverageAnalysis]: Checked inductivity of 21386 backedges. 5270 proven. 364 refuted. 0 times theorem prover too weak. 15752 trivial. 0 not checked. [2019-12-07 17:20:10,760 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [50988934] [2019-12-07 17:20:10,760 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1267248314] [2019-12-07 17:20:10,760 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:20:11,168 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 22 check-sat command(s) [2019-12-07 17:20:11,168 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:20:11,172 INFO L264 TraceCheckSpWp]: Trace formula consists of 1362 conjuncts, 18 conjunts are in the unsatisfiable core [2019-12-07 17:20:11,175 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:20:11,396 INFO L134 CoverageAnalysis]: Checked inductivity of 21386 backedges. 4973 proven. 364 refuted. 0 times theorem prover too weak. 16049 trivial. 0 not checked. [2019-12-07 17:20:11,396 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:20:11,396 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 18] total 32 [2019-12-07 17:20:11,396 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [357496206] [2019-12-07 17:20:11,397 INFO L442 AbstractCegarLoop]: Interpolant automaton has 33 states [2019-12-07 17:20:11,397 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:20:11,397 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2019-12-07 17:20:11,397 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=233, Invalid=823, Unknown=0, NotChecked=0, Total=1056 [2019-12-07 17:20:11,397 INFO L87 Difference]: Start difference. First operand 686 states and 711 transitions. Second operand 33 states. [2019-12-07 17:20:12,609 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:20:12,609 INFO L93 Difference]: Finished difference Result 864 states and 893 transitions. [2019-12-07 17:20:12,609 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2019-12-07 17:20:12,609 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 577 [2019-12-07 17:20:12,610 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:20:12,612 INFO L225 Difference]: With dead ends: 864 [2019-12-07 17:20:12,612 INFO L226 Difference]: Without dead ends: 864 [2019-12-07 17:20:12,612 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 656 GetRequests, 599 SyntacticMatches, 0 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 498 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=815, Invalid=2607, Unknown=0, NotChecked=0, Total=3422 [2019-12-07 17:20:12,613 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 864 states. [2019-12-07 17:20:12,618 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 864 to 757. [2019-12-07 17:20:12,618 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 757 states. [2019-12-07 17:20:12,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 757 states to 757 states and 783 transitions. [2019-12-07 17:20:12,620 INFO L78 Accepts]: Start accepts. Automaton has 757 states and 783 transitions. Word has length 577 [2019-12-07 17:20:12,620 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:20:12,620 INFO L462 AbstractCegarLoop]: Abstraction has 757 states and 783 transitions. [2019-12-07 17:20:12,620 INFO L463 AbstractCegarLoop]: Interpolant automaton has 33 states. [2019-12-07 17:20:12,620 INFO L276 IsEmpty]: Start isEmpty. Operand 757 states and 783 transitions. [2019-12-07 17:20:12,625 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 649 [2019-12-07 17:20:12,625 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:20:12,625 INFO L410 BasicCegarLoop]: trace histogram [102, 101, 101, 101, 101, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:20:12,826 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 28 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:20:12,826 INFO L410 AbstractCegarLoop]: === Iteration 35 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:20:12,826 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:20:12,827 INFO L82 PathProgramCache]: Analyzing trace with hash -344385043, now seen corresponding path program 19 times [2019-12-07 17:20:12,827 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:20:12,827 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1726951654] [2019-12-07 17:20:12,828 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:20:12,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:12,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:12,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:13,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:13,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:13,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:13,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:13,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:13,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:13,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:13,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:13,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:13,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:13,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:13,518 INFO L134 CoverageAnalysis]: Checked inductivity of 27438 backedges. 10842 proven. 1371 refuted. 0 times theorem prover too weak. 15225 trivial. 0 not checked. [2019-12-07 17:20:13,518 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1726951654] [2019-12-07 17:20:13,518 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1533709727] [2019-12-07 17:20:13,519 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:20:13,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:13,657 INFO L264 TraceCheckSpWp]: Trace formula consists of 1671 conjuncts, 28 conjunts are in the unsatisfiable core [2019-12-07 17:20:13,661 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:20:14,180 INFO L134 CoverageAnalysis]: Checked inductivity of 27438 backedges. 10979 proven. 342 refuted. 0 times theorem prover too weak. 16117 trivial. 0 not checked. [2019-12-07 17:20:14,181 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:20:14,181 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 28] total 46 [2019-12-07 17:20:14,181 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1163093381] [2019-12-07 17:20:14,182 INFO L442 AbstractCegarLoop]: Interpolant automaton has 46 states [2019-12-07 17:20:14,182 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:20:14,182 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2019-12-07 17:20:14,182 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=404, Invalid=1666, Unknown=0, NotChecked=0, Total=2070 [2019-12-07 17:20:14,182 INFO L87 Difference]: Start difference. First operand 757 states and 783 transitions. Second operand 46 states. [2019-12-07 17:20:16,702 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:20:16,702 INFO L93 Difference]: Finished difference Result 903 states and 935 transitions. [2019-12-07 17:20:16,702 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2019-12-07 17:20:16,702 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 648 [2019-12-07 17:20:16,703 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:20:16,705 INFO L225 Difference]: With dead ends: 903 [2019-12-07 17:20:16,705 INFO L226 Difference]: Without dead ends: 897 [2019-12-07 17:20:16,705 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 730 GetRequests, 660 SyntacticMatches, 0 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1128 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=1142, Invalid=3970, Unknown=0, NotChecked=0, Total=5112 [2019-12-07 17:20:16,706 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 897 states. [2019-12-07 17:20:16,711 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 897 to 767. [2019-12-07 17:20:16,711 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 767 states. [2019-12-07 17:20:16,713 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 767 states to 767 states and 793 transitions. [2019-12-07 17:20:16,713 INFO L78 Accepts]: Start accepts. Automaton has 767 states and 793 transitions. Word has length 648 [2019-12-07 17:20:16,713 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:20:16,713 INFO L462 AbstractCegarLoop]: Abstraction has 767 states and 793 transitions. [2019-12-07 17:20:16,713 INFO L463 AbstractCegarLoop]: Interpolant automaton has 46 states. [2019-12-07 17:20:16,713 INFO L276 IsEmpty]: Start isEmpty. Operand 767 states and 793 transitions. [2019-12-07 17:20:16,717 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 659 [2019-12-07 17:20:16,717 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:20:16,717 INFO L410 BasicCegarLoop]: trace histogram [104, 103, 103, 103, 103, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:20:16,918 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 29 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:20:16,918 INFO L410 AbstractCegarLoop]: === Iteration 36 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:20:16,919 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:20:16,919 INFO L82 PathProgramCache]: Analyzing trace with hash 1104503271, now seen corresponding path program 20 times [2019-12-07 17:20:16,919 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:20:16,920 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [236454473] [2019-12-07 17:20:16,920 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:20:17,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:17,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:17,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:17,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:17,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:17,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:17,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:17,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:17,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:17,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:17,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:17,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:17,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:17,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:17,597 INFO L134 CoverageAnalysis]: Checked inductivity of 28481 backedges. 6613 proven. 433 refuted. 0 times theorem prover too weak. 21435 trivial. 0 not checked. [2019-12-07 17:20:17,597 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [236454473] [2019-12-07 17:20:17,597 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [270925248] [2019-12-07 17:20:17,597 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:20:17,738 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 17:20:17,738 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:20:17,741 INFO L264 TraceCheckSpWp]: Trace formula consists of 1695 conjuncts, 29 conjunts are in the unsatisfiable core [2019-12-07 17:20:17,745 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:20:18,154 INFO L134 CoverageAnalysis]: Checked inductivity of 28481 backedges. 6198 proven. 416 refuted. 0 times theorem prover too weak. 21867 trivial. 0 not checked. [2019-12-07 17:20:18,155 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:20:18,155 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 15] total 45 [2019-12-07 17:20:18,155 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1857224244] [2019-12-07 17:20:18,156 INFO L442 AbstractCegarLoop]: Interpolant automaton has 46 states [2019-12-07 17:20:18,156 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:20:18,156 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2019-12-07 17:20:18,156 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=272, Invalid=1798, Unknown=0, NotChecked=0, Total=2070 [2019-12-07 17:20:18,156 INFO L87 Difference]: Start difference. First operand 767 states and 793 transitions. Second operand 46 states. [2019-12-07 17:20:22,372 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:20:22,372 INFO L93 Difference]: Finished difference Result 1009 states and 1048 transitions. [2019-12-07 17:20:22,372 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2019-12-07 17:20:22,372 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 658 [2019-12-07 17:20:22,373 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:20:22,375 INFO L225 Difference]: With dead ends: 1009 [2019-12-07 17:20:22,375 INFO L226 Difference]: Without dead ends: 1009 [2019-12-07 17:20:22,375 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 745 GetRequests, 669 SyntacticMatches, 1 SemanticMatches, 75 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1345 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=591, Invalid=5261, Unknown=0, NotChecked=0, Total=5852 [2019-12-07 17:20:22,376 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1009 states. [2019-12-07 17:20:22,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1009 to 848. [2019-12-07 17:20:22,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 848 states. [2019-12-07 17:20:22,383 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 848 states to 848 states and 876 transitions. [2019-12-07 17:20:22,383 INFO L78 Accepts]: Start accepts. Automaton has 848 states and 876 transitions. Word has length 658 [2019-12-07 17:20:22,384 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:20:22,384 INFO L462 AbstractCegarLoop]: Abstraction has 848 states and 876 transitions. [2019-12-07 17:20:22,384 INFO L463 AbstractCegarLoop]: Interpolant automaton has 46 states. [2019-12-07 17:20:22,384 INFO L276 IsEmpty]: Start isEmpty. Operand 848 states and 876 transitions. [2019-12-07 17:20:22,388 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 740 [2019-12-07 17:20:22,388 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:20:22,389 INFO L410 BasicCegarLoop]: trace histogram [118, 117, 117, 117, 117, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:20:22,589 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 30 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:20:22,589 INFO L410 AbstractCegarLoop]: === Iteration 37 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:20:22,590 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:20:22,590 INFO L82 PathProgramCache]: Analyzing trace with hash 79086155, now seen corresponding path program 21 times [2019-12-07 17:20:22,590 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:20:22,591 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1499263173] [2019-12-07 17:20:22,591 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:20:22,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:22,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:22,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:22,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:22,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:22,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:22,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:22,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:22,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:22,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:22,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:22,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:22,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:22,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:22,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:23,448 INFO L134 CoverageAnalysis]: Checked inductivity of 36595 backedges. 14114 proven. 1592 refuted. 0 times theorem prover too weak. 20889 trivial. 0 not checked. [2019-12-07 17:20:23,449 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1499263173] [2019-12-07 17:20:23,449 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [697301558] [2019-12-07 17:20:23,449 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:20:23,634 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2019-12-07 17:20:23,634 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:20:23,637 INFO L264 TraceCheckSpWp]: Trace formula consists of 795 conjuncts, 24 conjunts are in the unsatisfiable core [2019-12-07 17:20:23,641 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:20:24,396 INFO L134 CoverageAnalysis]: Checked inductivity of 36595 backedges. 12944 proven. 1368 refuted. 0 times theorem prover too weak. 22283 trivial. 0 not checked. [2019-12-07 17:20:24,396 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:20:24,397 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 23] total 56 [2019-12-07 17:20:24,397 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1458989242] [2019-12-07 17:20:24,397 INFO L442 AbstractCegarLoop]: Interpolant automaton has 56 states [2019-12-07 17:20:24,398 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:20:24,398 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2019-12-07 17:20:24,398 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=481, Invalid=2599, Unknown=0, NotChecked=0, Total=3080 [2019-12-07 17:20:24,398 INFO L87 Difference]: Start difference. First operand 848 states and 876 transitions. Second operand 56 states. [2019-12-07 17:20:28,553 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:20:28,553 INFO L93 Difference]: Finished difference Result 1361 states and 1415 transitions. [2019-12-07 17:20:28,553 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 78 states. [2019-12-07 17:20:28,554 INFO L78 Accepts]: Start accepts. Automaton has 56 states. Word has length 739 [2019-12-07 17:20:28,554 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:20:28,557 INFO L225 Difference]: With dead ends: 1361 [2019-12-07 17:20:28,557 INFO L226 Difference]: Without dead ends: 1355 [2019-12-07 17:20:28,558 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 870 GetRequests, 745 SyntacticMatches, 0 SemanticMatches, 125 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4060 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=2714, Invalid=13288, Unknown=0, NotChecked=0, Total=16002 [2019-12-07 17:20:28,559 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1355 states. [2019-12-07 17:20:28,566 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1355 to 853. [2019-12-07 17:20:28,566 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 853 states. [2019-12-07 17:20:28,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 853 states to 853 states and 880 transitions. [2019-12-07 17:20:28,568 INFO L78 Accepts]: Start accepts. Automaton has 853 states and 880 transitions. Word has length 739 [2019-12-07 17:20:28,568 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:20:28,568 INFO L462 AbstractCegarLoop]: Abstraction has 853 states and 880 transitions. [2019-12-07 17:20:28,568 INFO L463 AbstractCegarLoop]: Interpolant automaton has 56 states. [2019-12-07 17:20:28,568 INFO L276 IsEmpty]: Start isEmpty. Operand 853 states and 880 transitions. [2019-12-07 17:20:28,572 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 745 [2019-12-07 17:20:28,572 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:20:28,572 INFO L410 BasicCegarLoop]: trace histogram [119, 118, 118, 118, 118, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:20:28,773 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 31 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:20:28,773 INFO L410 AbstractCegarLoop]: === Iteration 38 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:20:28,774 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:20:28,774 INFO L82 PathProgramCache]: Analyzing trace with hash 1460105962, now seen corresponding path program 22 times [2019-12-07 17:20:28,774 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:20:28,775 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1171671724] [2019-12-07 17:20:28,775 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:20:28,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:29,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:29,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:29,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:29,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:29,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:29,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:29,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:29,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:29,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:29,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:29,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:29,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:29,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:29,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:29,566 INFO L134 CoverageAnalysis]: Checked inductivity of 37195 backedges. 8165 proven. 508 refuted. 0 times theorem prover too weak. 28522 trivial. 0 not checked. [2019-12-07 17:20:29,567 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1171671724] [2019-12-07 17:20:29,567 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2043878323] [2019-12-07 17:20:29,567 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:20:29,788 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 17:20:29,788 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:20:29,793 INFO L264 TraceCheckSpWp]: Trace formula consists of 1908 conjuncts, 31 conjunts are in the unsatisfiable core [2019-12-07 17:20:29,797 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:20:30,282 INFO L134 CoverageAnalysis]: Checked inductivity of 37195 backedges. 7683 proven. 483 refuted. 0 times theorem prover too weak. 29029 trivial. 0 not checked. [2019-12-07 17:20:30,282 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:20:30,283 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 16] total 48 [2019-12-07 17:20:30,283 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2040401429] [2019-12-07 17:20:30,284 INFO L442 AbstractCegarLoop]: Interpolant automaton has 49 states [2019-12-07 17:20:30,284 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:20:30,284 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2019-12-07 17:20:30,284 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=306, Invalid=2046, Unknown=0, NotChecked=0, Total=2352 [2019-12-07 17:20:30,284 INFO L87 Difference]: Start difference. First operand 853 states and 880 transitions. Second operand 49 states. [2019-12-07 17:20:32,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:20:32,096 INFO L93 Difference]: Finished difference Result 1140 states and 1185 transitions. [2019-12-07 17:20:32,097 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2019-12-07 17:20:32,097 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 744 [2019-12-07 17:20:32,097 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:20:32,100 INFO L225 Difference]: With dead ends: 1140 [2019-12-07 17:20:32,100 INFO L226 Difference]: Without dead ends: 1140 [2019-12-07 17:20:32,100 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 837 GetRequests, 756 SyntacticMatches, 1 SemanticMatches, 80 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1539 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=654, Invalid=5988, Unknown=0, NotChecked=0, Total=6642 [2019-12-07 17:20:32,101 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1140 states. [2019-12-07 17:20:32,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1140 to 939. [2019-12-07 17:20:32,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 939 states. [2019-12-07 17:20:32,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 939 states to 939 states and 968 transitions. [2019-12-07 17:20:32,109 INFO L78 Accepts]: Start accepts. Automaton has 939 states and 968 transitions. Word has length 744 [2019-12-07 17:20:32,109 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:20:32,109 INFO L462 AbstractCegarLoop]: Abstraction has 939 states and 968 transitions. [2019-12-07 17:20:32,109 INFO L463 AbstractCegarLoop]: Interpolant automaton has 49 states. [2019-12-07 17:20:32,110 INFO L276 IsEmpty]: Start isEmpty. Operand 939 states and 968 transitions. [2019-12-07 17:20:32,116 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 831 [2019-12-07 17:20:32,116 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:20:32,116 INFO L410 BasicCegarLoop]: trace histogram [134, 133, 133, 133, 133, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:20:32,317 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 32 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:20:32,317 INFO L410 AbstractCegarLoop]: === Iteration 39 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:20:32,317 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:20:32,318 INFO L82 PathProgramCache]: Analyzing trace with hash 51252807, now seen corresponding path program 23 times [2019-12-07 17:20:32,318 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:20:32,318 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1314571095] [2019-12-07 17:20:32,318 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:20:32,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:32,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:32,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:32,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:32,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:32,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:32,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:32,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:32,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:32,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:32,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:32,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:32,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:32,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:32,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:32,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:33,242 INFO L134 CoverageAnalysis]: Checked inductivity of 47075 backedges. 17357 proven. 1829 refuted. 0 times theorem prover too weak. 27889 trivial. 0 not checked. [2019-12-07 17:20:33,242 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1314571095] [2019-12-07 17:20:33,242 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [844038037] [2019-12-07 17:20:33,242 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:20:33,943 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 27 check-sat command(s) [2019-12-07 17:20:33,943 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:20:33,950 INFO L264 TraceCheckSpWp]: Trace formula consists of 2060 conjuncts, 36 conjunts are in the unsatisfiable core [2019-12-07 17:20:33,955 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:20:34,786 INFO L134 CoverageAnalysis]: Checked inductivity of 47075 backedges. 17329 proven. 2372 refuted. 0 times theorem prover too weak. 27374 trivial. 0 not checked. [2019-12-07 17:20:34,786 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:20:34,786 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 36] total 57 [2019-12-07 17:20:34,786 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1952493521] [2019-12-07 17:20:34,787 INFO L442 AbstractCegarLoop]: Interpolant automaton has 57 states [2019-12-07 17:20:34,787 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:20:34,787 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2019-12-07 17:20:34,788 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=562, Invalid=2630, Unknown=0, NotChecked=0, Total=3192 [2019-12-07 17:20:34,788 INFO L87 Difference]: Start difference. First operand 939 states and 968 transitions. Second operand 57 states. [2019-12-07 17:20:36,698 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:20:36,699 INFO L93 Difference]: Finished difference Result 1160 states and 1203 transitions. [2019-12-07 17:20:36,699 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2019-12-07 17:20:36,699 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 830 [2019-12-07 17:20:36,699 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:20:36,702 INFO L225 Difference]: With dead ends: 1160 [2019-12-07 17:20:36,702 INFO L226 Difference]: Without dead ends: 1154 [2019-12-07 17:20:36,703 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 928 GetRequests, 838 SyntacticMatches, 1 SemanticMatches, 89 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1956 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1774, Invalid=6416, Unknown=0, NotChecked=0, Total=8190 [2019-12-07 17:20:36,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1154 states. [2019-12-07 17:20:36,710 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1154 to 944. [2019-12-07 17:20:36,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 944 states. [2019-12-07 17:20:36,712 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 944 states to 944 states and 972 transitions. [2019-12-07 17:20:36,712 INFO L78 Accepts]: Start accepts. Automaton has 944 states and 972 transitions. Word has length 830 [2019-12-07 17:20:36,713 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:20:36,713 INFO L462 AbstractCegarLoop]: Abstraction has 944 states and 972 transitions. [2019-12-07 17:20:36,713 INFO L463 AbstractCegarLoop]: Interpolant automaton has 57 states. [2019-12-07 17:20:36,713 INFO L276 IsEmpty]: Start isEmpty. Operand 944 states and 972 transitions. [2019-12-07 17:20:36,718 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 836 [2019-12-07 17:20:36,718 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:20:36,718 INFO L410 BasicCegarLoop]: trace histogram [135, 134, 134, 134, 134, 15, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:20:36,919 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 33 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:20:36,919 INFO L410 AbstractCegarLoop]: === Iteration 40 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:20:36,919 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:20:36,920 INFO L82 PathProgramCache]: Analyzing trace with hash 1746428258, now seen corresponding path program 24 times [2019-12-07 17:20:36,920 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:20:36,920 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1170355914] [2019-12-07 17:20:36,921 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:20:37,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:37,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:37,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:37,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:37,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:37,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:37,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:37,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:37,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:37,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:37,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:37,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:37,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:37,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:37,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:37,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:37,845 INFO L134 CoverageAnalysis]: Checked inductivity of 47756 backedges. 9941 proven. 589 refuted. 0 times theorem prover too weak. 37226 trivial. 0 not checked. [2019-12-07 17:20:37,845 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1170355914] [2019-12-07 17:20:37,846 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1655266402] [2019-12-07 17:20:37,846 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:20:38,869 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 28 check-sat command(s) [2019-12-07 17:20:38,870 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:20:38,875 INFO L264 TraceCheckSpWp]: Trace formula consists of 2133 conjuncts, 19 conjunts are in the unsatisfiable core [2019-12-07 17:20:38,880 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:20:39,482 INFO L134 CoverageAnalysis]: Checked inductivity of 47756 backedges. 9387 proven. 555 refuted. 0 times theorem prover too weak. 37814 trivial. 0 not checked. [2019-12-07 17:20:39,482 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:20:39,483 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 18] total 53 [2019-12-07 17:20:39,483 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [932092171] [2019-12-07 17:20:39,484 INFO L442 AbstractCegarLoop]: Interpolant automaton has 54 states [2019-12-07 17:20:39,484 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:20:39,484 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2019-12-07 17:20:39,484 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=453, Invalid=2409, Unknown=0, NotChecked=0, Total=2862 [2019-12-07 17:20:39,484 INFO L87 Difference]: Start difference. First operand 944 states and 972 transitions. Second operand 54 states. [2019-12-07 17:20:41,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:20:41,187 INFO L93 Difference]: Finished difference Result 1284 states and 1336 transitions. [2019-12-07 17:20:41,187 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2019-12-07 17:20:41,187 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 835 [2019-12-07 17:20:41,188 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:20:41,191 INFO L225 Difference]: With dead ends: 1284 [2019-12-07 17:20:41,191 INFO L226 Difference]: Without dead ends: 1284 [2019-12-07 17:20:41,191 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 934 GetRequests, 847 SyntacticMatches, 0 SemanticMatches, 87 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1823 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1310, Invalid=6522, Unknown=0, NotChecked=0, Total=7832 [2019-12-07 17:20:41,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1284 states. [2019-12-07 17:20:41,198 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1284 to 1035. [2019-12-07 17:20:41,199 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1035 states. [2019-12-07 17:20:41,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1035 states to 1035 states and 1065 transitions. [2019-12-07 17:20:41,200 INFO L78 Accepts]: Start accepts. Automaton has 1035 states and 1065 transitions. Word has length 835 [2019-12-07 17:20:41,200 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:20:41,200 INFO L462 AbstractCegarLoop]: Abstraction has 1035 states and 1065 transitions. [2019-12-07 17:20:41,200 INFO L463 AbstractCegarLoop]: Interpolant automaton has 54 states. [2019-12-07 17:20:41,200 INFO L276 IsEmpty]: Start isEmpty. Operand 1035 states and 1065 transitions. [2019-12-07 17:20:41,206 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 927 [2019-12-07 17:20:41,206 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:20:41,206 INFO L410 BasicCegarLoop]: trace histogram [151, 150, 150, 150, 150, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:20:41,406 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 34 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:20:41,407 INFO L410 AbstractCegarLoop]: === Iteration 41 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:20:41,407 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:20:41,407 INFO L82 PathProgramCache]: Analyzing trace with hash -848043632, now seen corresponding path program 25 times [2019-12-07 17:20:41,407 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:20:41,407 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [69550485] [2019-12-07 17:20:41,408 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:20:41,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:41,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:41,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:41,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:41,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:41,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:41,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:41,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:41,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:41,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:41,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:41,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:41,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:41,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:41,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:41,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:41,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:42,499 INFO L134 CoverageAnalysis]: Checked inductivity of 59640 backedges. 21058 proven. 2082 refuted. 0 times theorem prover too weak. 36500 trivial. 0 not checked. [2019-12-07 17:20:42,499 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [69550485] [2019-12-07 17:20:42,499 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [416851294] [2019-12-07 17:20:42,499 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:20:42,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:42,695 INFO L264 TraceCheckSpWp]: Trace formula consists of 2358 conjuncts, 34 conjunts are in the unsatisfiable core [2019-12-07 17:20:42,701 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:20:43,558 INFO L134 CoverageAnalysis]: Checked inductivity of 59640 backedges. 21228 proven. 540 refuted. 0 times theorem prover too weak. 37872 trivial. 0 not checked. [2019-12-07 17:20:43,558 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:20:43,559 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 34] total 55 [2019-12-07 17:20:43,559 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [182776361] [2019-12-07 17:20:43,560 INFO L442 AbstractCegarLoop]: Interpolant automaton has 55 states [2019-12-07 17:20:43,560 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:20:43,560 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2019-12-07 17:20:43,560 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=590, Invalid=2380, Unknown=0, NotChecked=0, Total=2970 [2019-12-07 17:20:43,560 INFO L87 Difference]: Start difference. First operand 1035 states and 1065 transitions. Second operand 55 states. [2019-12-07 17:20:44,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:20:44,761 INFO L93 Difference]: Finished difference Result 1308 states and 1358 transitions. [2019-12-07 17:20:44,761 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2019-12-07 17:20:44,761 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 926 [2019-12-07 17:20:44,762 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:20:44,764 INFO L225 Difference]: With dead ends: 1308 [2019-12-07 17:20:44,764 INFO L226 Difference]: Without dead ends: 1302 [2019-12-07 17:20:44,765 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1026 GetRequests, 941 SyntacticMatches, 0 SemanticMatches, 85 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1725 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=1667, Invalid=5815, Unknown=0, NotChecked=0, Total=7482 [2019-12-07 17:20:44,765 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1302 states. [2019-12-07 17:20:44,772 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1302 to 1040. [2019-12-07 17:20:44,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1040 states. [2019-12-07 17:20:44,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1040 states to 1040 states and 1069 transitions. [2019-12-07 17:20:44,773 INFO L78 Accepts]: Start accepts. Automaton has 1040 states and 1069 transitions. Word has length 926 [2019-12-07 17:20:44,774 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:20:44,774 INFO L462 AbstractCegarLoop]: Abstraction has 1040 states and 1069 transitions. [2019-12-07 17:20:44,774 INFO L463 AbstractCegarLoop]: Interpolant automaton has 55 states. [2019-12-07 17:20:44,774 INFO L276 IsEmpty]: Start isEmpty. Operand 1040 states and 1069 transitions. [2019-12-07 17:20:44,779 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 932 [2019-12-07 17:20:44,779 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:20:44,780 INFO L410 BasicCegarLoop]: trace histogram [152, 151, 151, 151, 151, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:20:44,980 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 35 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:20:44,980 INFO L410 AbstractCegarLoop]: === Iteration 42 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:20:44,981 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:20:44,981 INFO L82 PathProgramCache]: Analyzing trace with hash 401870661, now seen corresponding path program 26 times [2019-12-07 17:20:44,981 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:20:44,981 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1248249127] [2019-12-07 17:20:44,982 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:20:45,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:45,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:45,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:45,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:45,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:45,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:45,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:45,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:45,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:45,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:45,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:45,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:45,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:45,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:45,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:45,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:45,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:46,041 INFO L134 CoverageAnalysis]: Checked inductivity of 60407 backedges. 11956 proven. 676 refuted. 0 times theorem prover too weak. 47775 trivial. 0 not checked. [2019-12-07 17:20:46,041 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1248249127] [2019-12-07 17:20:46,041 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1216854602] [2019-12-07 17:20:46,041 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:20:46,228 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 17:20:46,228 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:20:46,233 INFO L264 TraceCheckSpWp]: Trace formula consists of 2370 conjuncts, 35 conjunts are in the unsatisfiable core [2019-12-07 17:20:46,238 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:20:46,935 INFO L134 CoverageAnalysis]: Checked inductivity of 60407 backedges. 11325 proven. 632 refuted. 0 times theorem prover too weak. 48450 trivial. 0 not checked. [2019-12-07 17:20:46,936 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:20:46,936 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 18] total 54 [2019-12-07 17:20:46,936 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1295553651] [2019-12-07 17:20:46,937 INFO L442 AbstractCegarLoop]: Interpolant automaton has 55 states [2019-12-07 17:20:46,937 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:20:46,937 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2019-12-07 17:20:46,937 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=380, Invalid=2590, Unknown=0, NotChecked=0, Total=2970 [2019-12-07 17:20:46,937 INFO L87 Difference]: Start difference. First operand 1040 states and 1069 transitions. Second operand 55 states. [2019-12-07 17:20:50,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:20:50,375 INFO L93 Difference]: Finished difference Result 1441 states and 1501 transitions. [2019-12-07 17:20:50,376 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2019-12-07 17:20:50,376 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 931 [2019-12-07 17:20:50,377 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:20:50,386 INFO L225 Difference]: With dead ends: 1441 [2019-12-07 17:20:50,386 INFO L226 Difference]: Without dead ends: 1441 [2019-12-07 17:20:50,387 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1036 GetRequests, 945 SyntacticMatches, 1 SemanticMatches, 90 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1966 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=789, Invalid=7583, Unknown=0, NotChecked=0, Total=8372 [2019-12-07 17:20:50,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1441 states. [2019-12-07 17:20:50,404 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1441 to 1136. [2019-12-07 17:20:50,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1136 states. [2019-12-07 17:20:50,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1136 states to 1136 states and 1167 transitions. [2019-12-07 17:20:50,406 INFO L78 Accepts]: Start accepts. Automaton has 1136 states and 1167 transitions. Word has length 931 [2019-12-07 17:20:50,406 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:20:50,407 INFO L462 AbstractCegarLoop]: Abstraction has 1136 states and 1167 transitions. [2019-12-07 17:20:50,407 INFO L463 AbstractCegarLoop]: Interpolant automaton has 55 states. [2019-12-07 17:20:50,407 INFO L276 IsEmpty]: Start isEmpty. Operand 1136 states and 1167 transitions. [2019-12-07 17:20:50,415 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1028 [2019-12-07 17:20:50,415 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:20:50,415 INFO L410 BasicCegarLoop]: trace histogram [169, 168, 168, 168, 168, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:20:50,616 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 36 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:20:50,616 INFO L410 AbstractCegarLoop]: === Iteration 43 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:20:50,616 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:20:50,617 INFO L82 PathProgramCache]: Analyzing trace with hash -697239742, now seen corresponding path program 27 times [2019-12-07 17:20:50,617 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:20:50,617 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1800879561] [2019-12-07 17:20:50,618 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:20:50,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:50,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:50,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:50,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:50,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:50,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:50,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:50,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:50,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:50,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:50,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:50,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:50,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:50,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:50,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:50,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:50,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:51,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:20:51,850 INFO L134 CoverageAnalysis]: Checked inductivity of 74548 backedges. 25247 proven. 2351 refuted. 0 times theorem prover too weak. 46950 trivial. 0 not checked. [2019-12-07 17:20:51,850 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1800879561] [2019-12-07 17:20:51,850 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [339563324] [2019-12-07 17:20:51,850 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:20:52,115 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2019-12-07 17:20:52,115 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:20:52,119 INFO L264 TraceCheckSpWp]: Trace formula consists of 1074 conjuncts, 27 conjunts are in the unsatisfiable core [2019-12-07 17:20:52,124 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:20:53,284 INFO L134 CoverageAnalysis]: Checked inductivity of 74548 backedges. 23423 proven. 2043 refuted. 0 times theorem prover too weak. 49082 trivial. 0 not checked. [2019-12-07 17:20:53,284 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:20:53,284 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 26] total 65 [2019-12-07 17:20:53,285 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [136590239] [2019-12-07 17:20:53,285 INFO L442 AbstractCegarLoop]: Interpolant automaton has 65 states [2019-12-07 17:20:53,285 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:20:53,286 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2019-12-07 17:20:53,286 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=679, Invalid=3481, Unknown=0, NotChecked=0, Total=4160 [2019-12-07 17:20:53,286 INFO L87 Difference]: Start difference. First operand 1136 states and 1167 transitions. Second operand 65 states. [2019-12-07 17:21:01,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:21:01,879 INFO L93 Difference]: Finished difference Result 2165 states and 2273 transitions. [2019-12-07 17:21:01,880 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2019-12-07 17:21:01,880 INFO L78 Accepts]: Start accepts. Automaton has 65 states. Word has length 1027 [2019-12-07 17:21:01,882 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:21:01,896 INFO L225 Difference]: With dead ends: 2165 [2019-12-07 17:21:01,896 INFO L226 Difference]: Without dead ends: 2159 [2019-12-07 17:21:01,897 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1185 GetRequests, 1036 SyntacticMatches, 0 SemanticMatches, 149 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5875 ImplicationChecksByTransitivity, 6.8s TimeCoverageRelationStatistics Valid=3818, Invalid=18832, Unknown=0, NotChecked=0, Total=22650 [2019-12-07 17:21:01,900 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2159 states. [2019-12-07 17:21:01,914 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2159 to 1141. [2019-12-07 17:21:01,914 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1141 states. [2019-12-07 17:21:01,915 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1141 states to 1141 states and 1171 transitions. [2019-12-07 17:21:01,915 INFO L78 Accepts]: Start accepts. Automaton has 1141 states and 1171 transitions. Word has length 1027 [2019-12-07 17:21:01,916 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:21:01,916 INFO L462 AbstractCegarLoop]: Abstraction has 1141 states and 1171 transitions. [2019-12-07 17:21:01,916 INFO L463 AbstractCegarLoop]: Interpolant automaton has 65 states. [2019-12-07 17:21:01,916 INFO L276 IsEmpty]: Start isEmpty. Operand 1141 states and 1171 transitions. [2019-12-07 17:21:01,923 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1033 [2019-12-07 17:21:01,923 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:21:01,924 INFO L410 BasicCegarLoop]: trace histogram [170, 169, 169, 169, 169, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:21:02,125 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 37 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:21:02,125 INFO L410 AbstractCegarLoop]: === Iteration 44 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:21:02,126 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:21:02,126 INFO L82 PathProgramCache]: Analyzing trace with hash 548287687, now seen corresponding path program 28 times [2019-12-07 17:21:02,126 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:21:02,127 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [467867037] [2019-12-07 17:21:02,127 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:21:02,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:02,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:02,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:02,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:02,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:02,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:02,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:02,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:02,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:02,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:02,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:02,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:02,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:02,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:02,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:02,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:02,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:02,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:03,358 INFO L134 CoverageAnalysis]: Checked inductivity of 75406 backedges. 14225 proven. 769 refuted. 0 times theorem prover too weak. 60412 trivial. 0 not checked. [2019-12-07 17:21:03,358 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [467867037] [2019-12-07 17:21:03,359 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [720288926] [2019-12-07 17:21:03,359 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:21:03,870 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 17:21:03,870 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:21:03,878 INFO L264 TraceCheckSpWp]: Trace formula consists of 2619 conjuncts, 37 conjunts are in the unsatisfiable core [2019-12-07 17:21:03,884 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:21:04,679 INFO L134 CoverageAnalysis]: Checked inductivity of 75406 backedges. 13512 proven. 714 refuted. 0 times theorem prover too weak. 61180 trivial. 0 not checked. [2019-12-07 17:21:04,680 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:21:04,680 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 19] total 57 [2019-12-07 17:21:04,680 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1041083811] [2019-12-07 17:21:04,681 INFO L442 AbstractCegarLoop]: Interpolant automaton has 58 states [2019-12-07 17:21:04,681 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:21:04,681 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2019-12-07 17:21:04,682 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=420, Invalid=2886, Unknown=0, NotChecked=0, Total=3306 [2019-12-07 17:21:04,682 INFO L87 Difference]: Start difference. First operand 1141 states and 1171 transitions. Second operand 58 states. [2019-12-07 17:21:08,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:21:08,012 INFO L93 Difference]: Finished difference Result 1611 states and 1680 transitions. [2019-12-07 17:21:08,012 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2019-12-07 17:21:08,012 INFO L78 Accepts]: Start accepts. Automaton has 58 states. Word has length 1032 [2019-12-07 17:21:08,012 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:21:08,016 INFO L225 Difference]: With dead ends: 1611 [2019-12-07 17:21:08,016 INFO L226 Difference]: Without dead ends: 1611 [2019-12-07 17:21:08,016 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1143 GetRequests, 1047 SyntacticMatches, 1 SemanticMatches, 95 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2199 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=861, Invalid=8451, Unknown=0, NotChecked=0, Total=9312 [2019-12-07 17:21:08,017 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1611 states. [2019-12-07 17:21:08,026 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1611 to 1242. [2019-12-07 17:21:08,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1242 states. [2019-12-07 17:21:08,027 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1242 states to 1242 states and 1274 transitions. [2019-12-07 17:21:08,027 INFO L78 Accepts]: Start accepts. Automaton has 1242 states and 1274 transitions. Word has length 1032 [2019-12-07 17:21:08,027 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:21:08,027 INFO L462 AbstractCegarLoop]: Abstraction has 1242 states and 1274 transitions. [2019-12-07 17:21:08,027 INFO L463 AbstractCegarLoop]: Interpolant automaton has 58 states. [2019-12-07 17:21:08,027 INFO L276 IsEmpty]: Start isEmpty. Operand 1242 states and 1274 transitions. [2019-12-07 17:21:08,035 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1134 [2019-12-07 17:21:08,035 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:21:08,036 INFO L410 BasicCegarLoop]: trace histogram [188, 187, 187, 187, 187, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:21:08,236 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 38 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:21:08,236 INFO L410 AbstractCegarLoop]: === Iteration 45 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:21:08,237 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:21:08,237 INFO L82 PathProgramCache]: Analyzing trace with hash -1908118869, now seen corresponding path program 29 times [2019-12-07 17:21:08,237 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:21:08,238 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [849595713] [2019-12-07 17:21:08,238 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:21:08,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:08,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:08,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:08,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:08,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:08,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:08,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:08,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:08,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:08,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:08,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:08,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:08,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:08,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:08,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:08,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:08,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:08,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:08,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:09,646 INFO L134 CoverageAnalysis]: Checked inductivity of 92072 backedges. 29954 proven. 2636 refuted. 0 times theorem prover too weak. 59482 trivial. 0 not checked. [2019-12-07 17:21:09,646 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [849595713] [2019-12-07 17:21:09,646 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [272728984] [2019-12-07 17:21:09,647 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:21:11,152 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 42 check-sat command(s) [2019-12-07 17:21:11,152 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:21:11,166 INFO L264 TraceCheckSpWp]: Trace formula consists of 2807 conjuncts, 42 conjunts are in the unsatisfiable core [2019-12-07 17:21:11,173 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:21:12,476 INFO L134 CoverageAnalysis]: Checked inductivity of 92072 backedges. 29910 proven. 4185 refuted. 0 times theorem prover too weak. 57977 trivial. 0 not checked. [2019-12-07 17:21:12,476 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:21:12,477 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 42] total 67 [2019-12-07 17:21:12,477 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1147647704] [2019-12-07 17:21:12,478 INFO L442 AbstractCegarLoop]: Interpolant automaton has 67 states [2019-12-07 17:21:12,478 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:21:12,478 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2019-12-07 17:21:12,478 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=781, Invalid=3641, Unknown=0, NotChecked=0, Total=4422 [2019-12-07 17:21:12,479 INFO L87 Difference]: Start difference. First operand 1242 states and 1274 transitions. Second operand 67 states. [2019-12-07 17:21:14,959 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:21:14,959 INFO L93 Difference]: Finished difference Result 1731 states and 1862 transitions. [2019-12-07 17:21:14,959 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2019-12-07 17:21:14,959 INFO L78 Accepts]: Start accepts. Automaton has 67 states. Word has length 1133 [2019-12-07 17:21:14,960 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:21:14,965 INFO L225 Difference]: With dead ends: 1731 [2019-12-07 17:21:14,965 INFO L226 Difference]: Without dead ends: 1725 [2019-12-07 17:21:14,966 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1250 GetRequests, 1144 SyntacticMatches, 0 SemanticMatches, 106 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2763 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=2447, Invalid=9109, Unknown=0, NotChecked=0, Total=11556 [2019-12-07 17:21:14,967 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1725 states. [2019-12-07 17:21:14,982 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1725 to 1342. [2019-12-07 17:21:14,982 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1342 states. [2019-12-07 17:21:14,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1342 states to 1342 states and 1388 transitions. [2019-12-07 17:21:14,984 INFO L78 Accepts]: Start accepts. Automaton has 1342 states and 1388 transitions. Word has length 1133 [2019-12-07 17:21:14,985 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:21:14,985 INFO L462 AbstractCegarLoop]: Abstraction has 1342 states and 1388 transitions. [2019-12-07 17:21:14,985 INFO L463 AbstractCegarLoop]: Interpolant automaton has 67 states. [2019-12-07 17:21:14,985 INFO L276 IsEmpty]: Start isEmpty. Operand 1342 states and 1388 transitions. [2019-12-07 17:21:14,994 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1139 [2019-12-07 17:21:14,994 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:21:14,994 INFO L410 BasicCegarLoop]: trace histogram [189, 188, 188, 188, 188, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:21:15,195 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 39 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:21:15,195 INFO L410 AbstractCegarLoop]: === Iteration 46 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:21:15,195 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:21:15,196 INFO L82 PathProgramCache]: Analyzing trace with hash -1485351030, now seen corresponding path program 30 times [2019-12-07 17:21:15,196 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:21:15,196 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1502304514] [2019-12-07 17:21:15,197 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:21:15,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:15,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:15,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:15,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:15,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:15,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:15,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:15,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:15,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:15,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:15,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:15,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:15,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:15,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:15,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:15,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:15,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:15,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:15,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:16,610 INFO L134 CoverageAnalysis]: Checked inductivity of 93026 backedges. 16763 proven. 868 refuted. 0 times theorem prover too weak. 75395 trivial. 0 not checked. [2019-12-07 17:21:16,610 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1502304514] [2019-12-07 17:21:16,610 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2079827695] [2019-12-07 17:21:16,610 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:21:17,613 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 37 check-sat command(s) [2019-12-07 17:21:17,613 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:21:17,619 INFO L264 TraceCheckSpWp]: Trace formula consists of 2154 conjuncts, 22 conjunts are in the unsatisfiable core [2019-12-07 17:21:17,625 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:21:18,587 INFO L134 CoverageAnalysis]: Checked inductivity of 93026 backedges. 15963 proven. 801 refuted. 0 times theorem prover too weak. 76262 trivial. 0 not checked. [2019-12-07 17:21:18,587 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:21:18,588 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 21] total 62 [2019-12-07 17:21:18,588 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [617349888] [2019-12-07 17:21:18,589 INFO L442 AbstractCegarLoop]: Interpolant automaton has 63 states [2019-12-07 17:21:18,589 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:21:18,589 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2019-12-07 17:21:18,590 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=621, Invalid=3285, Unknown=0, NotChecked=0, Total=3906 [2019-12-07 17:21:18,590 INFO L87 Difference]: Start difference. First operand 1342 states and 1388 transitions. Second operand 63 states. [2019-12-07 17:21:21,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:21:21,005 INFO L93 Difference]: Finished difference Result 1878 states and 2029 transitions. [2019-12-07 17:21:21,005 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2019-12-07 17:21:21,005 INFO L78 Accepts]: Start accepts. Automaton has 63 states. Word has length 1138 [2019-12-07 17:21:21,006 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:21:21,013 INFO L225 Difference]: With dead ends: 1878 [2019-12-07 17:21:21,013 INFO L226 Difference]: Without dead ends: 1878 [2019-12-07 17:21:21,014 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1255 GetRequests, 1153 SyntacticMatches, 0 SemanticMatches, 102 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2537 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1778, Invalid=8934, Unknown=0, NotChecked=0, Total=10712 [2019-12-07 17:21:21,015 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1878 states. [2019-12-07 17:21:21,036 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1878 to 1448. [2019-12-07 17:21:21,037 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1448 states. [2019-12-07 17:21:21,039 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1448 states to 1448 states and 1496 transitions. [2019-12-07 17:21:21,039 INFO L78 Accepts]: Start accepts. Automaton has 1448 states and 1496 transitions. Word has length 1138 [2019-12-07 17:21:21,040 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:21:21,040 INFO L462 AbstractCegarLoop]: Abstraction has 1448 states and 1496 transitions. [2019-12-07 17:21:21,040 INFO L463 AbstractCegarLoop]: Interpolant automaton has 63 states. [2019-12-07 17:21:21,040 INFO L276 IsEmpty]: Start isEmpty. Operand 1448 states and 1496 transitions. [2019-12-07 17:21:21,053 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1245 [2019-12-07 17:21:21,053 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:21:21,053 INFO L410 BasicCegarLoop]: trace histogram [208, 207, 207, 207, 207, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:21:21,253 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 40 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:21:21,254 INFO L410 AbstractCegarLoop]: === Iteration 47 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:21:21,254 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:21:21,255 INFO L82 PathProgramCache]: Analyzing trace with hash -1962245081, now seen corresponding path program 31 times [2019-12-07 17:21:21,255 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:21:21,255 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [563161357] [2019-12-07 17:21:21,256 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:21:21,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:21,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:21,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:21,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:21,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:21,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:21,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:21,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:21,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:21,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:21,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:21,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:21,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:21,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:21,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:21,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:21,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:21,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:21,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:21,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:22,885 INFO L134 CoverageAnalysis]: Checked inductivity of 112500 backedges. 35209 proven. 2937 refuted. 0 times theorem prover too weak. 74354 trivial. 0 not checked. [2019-12-07 17:21:22,885 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [563161357] [2019-12-07 17:21:22,886 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1445995301] [2019-12-07 17:21:22,886 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:21:23,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:23,132 INFO L264 TraceCheckSpWp]: Trace formula consists of 3141 conjuncts, 40 conjunts are in the unsatisfiable core [2019-12-07 17:21:23,139 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:21:24,488 INFO L134 CoverageAnalysis]: Checked inductivity of 112500 backedges. 35412 proven. 783 refuted. 0 times theorem prover too weak. 76305 trivial. 0 not checked. [2019-12-07 17:21:24,489 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:21:24,489 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 40] total 64 [2019-12-07 17:21:24,489 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [232480921] [2019-12-07 17:21:24,490 INFO L442 AbstractCegarLoop]: Interpolant automaton has 64 states [2019-12-07 17:21:24,490 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:21:24,491 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2019-12-07 17:21:24,491 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=812, Invalid=3220, Unknown=0, NotChecked=0, Total=4032 [2019-12-07 17:21:24,491 INFO L87 Difference]: Start difference. First operand 1448 states and 1496 transitions. Second operand 64 states. [2019-12-07 17:21:25,951 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:21:25,951 INFO L93 Difference]: Finished difference Result 1914 states and 2063 transitions. [2019-12-07 17:21:25,952 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2019-12-07 17:21:25,952 INFO L78 Accepts]: Start accepts. Automaton has 64 states. Word has length 1244 [2019-12-07 17:21:25,953 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:21:25,958 INFO L225 Difference]: With dead ends: 1914 [2019-12-07 17:21:25,958 INFO L226 Difference]: Without dead ends: 1908 [2019-12-07 17:21:25,958 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1362 GetRequests, 1262 SyntacticMatches, 0 SemanticMatches, 100 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2448 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=2291, Invalid=8011, Unknown=0, NotChecked=0, Total=10302 [2019-12-07 17:21:25,959 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1908 states. [2019-12-07 17:21:25,976 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1908 to 1453. [2019-12-07 17:21:25,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1453 states. [2019-12-07 17:21:25,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1453 states to 1453 states and 1500 transitions. [2019-12-07 17:21:25,978 INFO L78 Accepts]: Start accepts. Automaton has 1453 states and 1500 transitions. Word has length 1244 [2019-12-07 17:21:25,979 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:21:25,979 INFO L462 AbstractCegarLoop]: Abstraction has 1453 states and 1500 transitions. [2019-12-07 17:21:25,979 INFO L463 AbstractCegarLoop]: Interpolant automaton has 64 states. [2019-12-07 17:21:25,979 INFO L276 IsEmpty]: Start isEmpty. Operand 1453 states and 1500 transitions. [2019-12-07 17:21:25,989 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1250 [2019-12-07 17:21:25,989 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:21:25,989 INFO L410 BasicCegarLoop]: trace histogram [209, 208, 208, 208, 208, 19, 19, 19, 18, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:21:26,190 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 41 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:21:26,190 INFO L410 AbstractCegarLoop]: === Iteration 48 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:21:26,190 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:21:26,191 INFO L82 PathProgramCache]: Analyzing trace with hash -1184766334, now seen corresponding path program 32 times [2019-12-07 17:21:26,191 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:21:26,191 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1065182808] [2019-12-07 17:21:26,192 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:21:26,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:26,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:26,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:26,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:26,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:26,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:26,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:26,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:26,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:26,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:26,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:26,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:26,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:26,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:26,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:26,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:26,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:26,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:26,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:27,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:27,813 INFO L134 CoverageAnalysis]: Checked inductivity of 113555 backedges. 19585 proven. 973 refuted. 0 times theorem prover too weak. 92997 trivial. 0 not checked. [2019-12-07 17:21:27,813 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1065182808] [2019-12-07 17:21:27,813 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [641797480] [2019-12-07 17:21:27,813 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:21:28,057 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 17:21:28,057 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:21:28,063 INFO L264 TraceCheckSpWp]: Trace formula consists of 3153 conjuncts, 41 conjunts are in the unsatisfiable core [2019-12-07 17:21:28,070 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:21:29,131 INFO L134 CoverageAnalysis]: Checked inductivity of 113555 backedges. 18693 proven. 893 refuted. 0 times theorem prover too weak. 93969 trivial. 0 not checked. [2019-12-07 17:21:29,131 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:21:29,132 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 21] total 63 [2019-12-07 17:21:29,132 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [888697816] [2019-12-07 17:21:29,133 INFO L442 AbstractCegarLoop]: Interpolant automaton has 64 states [2019-12-07 17:21:29,133 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:21:29,133 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2019-12-07 17:21:29,133 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=506, Invalid=3526, Unknown=0, NotChecked=0, Total=4032 [2019-12-07 17:21:29,133 INFO L87 Difference]: Start difference. First operand 1453 states and 1500 transitions. Second operand 64 states. [2019-12-07 17:21:34,306 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:21:34,306 INFO L93 Difference]: Finished difference Result 2074 states and 2244 transitions. [2019-12-07 17:21:34,307 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2019-12-07 17:21:34,307 INFO L78 Accepts]: Start accepts. Automaton has 64 states. Word has length 1249 [2019-12-07 17:21:34,308 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:21:34,312 INFO L225 Difference]: With dead ends: 2074 [2019-12-07 17:21:34,313 INFO L226 Difference]: Without dead ends: 2074 [2019-12-07 17:21:34,313 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1372 GetRequests, 1266 SyntacticMatches, 1 SemanticMatches, 105 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2704 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=1014, Invalid=10328, Unknown=0, NotChecked=0, Total=11342 [2019-12-07 17:21:34,315 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2074 states. [2019-12-07 17:21:34,329 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2074 to 1564. [2019-12-07 17:21:34,330 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1564 states. [2019-12-07 17:21:34,331 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1564 states to 1564 states and 1613 transitions. [2019-12-07 17:21:34,331 INFO L78 Accepts]: Start accepts. Automaton has 1564 states and 1613 transitions. Word has length 1249 [2019-12-07 17:21:34,332 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:21:34,332 INFO L462 AbstractCegarLoop]: Abstraction has 1564 states and 1613 transitions. [2019-12-07 17:21:34,332 INFO L463 AbstractCegarLoop]: Interpolant automaton has 64 states. [2019-12-07 17:21:34,332 INFO L276 IsEmpty]: Start isEmpty. Operand 1564 states and 1613 transitions. [2019-12-07 17:21:34,343 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1361 [2019-12-07 17:21:34,343 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:21:34,344 INFO L410 BasicCegarLoop]: trace histogram [229, 228, 228, 228, 228, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:21:34,544 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 42 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:21:34,544 INFO L410 AbstractCegarLoop]: === Iteration 49 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:21:34,544 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:21:34,545 INFO L82 PathProgramCache]: Analyzing trace with hash -1077882064, now seen corresponding path program 33 times [2019-12-07 17:21:34,545 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:21:34,545 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [791540478] [2019-12-07 17:21:34,545 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:21:34,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:34,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:34,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:34,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:34,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:34,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:34,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:34,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:34,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:34,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:34,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:34,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:34,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:34,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:34,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:34,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:34,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:34,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:35,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:35,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:35,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:36,366 INFO L134 CoverageAnalysis]: Checked inductivity of 136135 backedges. 41042 proven. 3254 refuted. 0 times theorem prover too weak. 91839 trivial. 0 not checked. [2019-12-07 17:21:36,366 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [791540478] [2019-12-07 17:21:36,366 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1089584407] [2019-12-07 17:21:36,367 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:21:36,819 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2019-12-07 17:21:36,820 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:21:36,824 INFO L264 TraceCheckSpWp]: Trace formula consists of 1461 conjuncts, 30 conjunts are in the unsatisfiable core [2019-12-07 17:21:36,831 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:21:38,513 INFO L134 CoverageAnalysis]: Checked inductivity of 136135 backedges. 38420 proven. 2853 refuted. 0 times theorem prover too weak. 94862 trivial. 0 not checked. [2019-12-07 17:21:38,514 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:21:38,514 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 29] total 74 [2019-12-07 17:21:38,514 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [332901513] [2019-12-07 17:21:38,515 INFO L442 AbstractCegarLoop]: Interpolant automaton has 74 states [2019-12-07 17:21:38,515 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:21:38,516 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 74 interpolants. [2019-12-07 17:21:38,516 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=913, Invalid=4489, Unknown=0, NotChecked=0, Total=5402 [2019-12-07 17:21:38,516 INFO L87 Difference]: Start difference. First operand 1564 states and 1613 transitions. Second operand 74 states. [2019-12-07 17:21:42,471 WARN L192 SmtUtils]: Spent 100.00 ms on a formula simplification. DAG size of input: 24 DAG size of output: 21 [2019-12-07 17:21:47,690 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:21:47,691 INFO L93 Difference]: Finished difference Result 3326 states and 3643 transitions. [2019-12-07 17:21:47,691 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 114 states. [2019-12-07 17:21:47,691 INFO L78 Accepts]: Start accepts. Automaton has 74 states. Word has length 1360 [2019-12-07 17:21:47,693 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:21:47,704 INFO L225 Difference]: With dead ends: 3326 [2019-12-07 17:21:47,705 INFO L226 Difference]: Without dead ends: 3320 [2019-12-07 17:21:47,708 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1545 GetRequests, 1372 SyntacticMatches, 0 SemanticMatches, 173 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8023 ImplicationChecksByTransitivity, 7.8s TimeCoverageRelationStatistics Valid=5111, Invalid=25339, Unknown=0, NotChecked=0, Total=30450 [2019-12-07 17:21:47,711 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3320 states. [2019-12-07 17:21:47,734 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3320 to 1569. [2019-12-07 17:21:47,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1569 states. [2019-12-07 17:21:47,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1569 states to 1569 states and 1617 transitions. [2019-12-07 17:21:47,736 INFO L78 Accepts]: Start accepts. Automaton has 1569 states and 1617 transitions. Word has length 1360 [2019-12-07 17:21:47,736 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:21:47,737 INFO L462 AbstractCegarLoop]: Abstraction has 1569 states and 1617 transitions. [2019-12-07 17:21:47,737 INFO L463 AbstractCegarLoop]: Interpolant automaton has 74 states. [2019-12-07 17:21:47,737 INFO L276 IsEmpty]: Start isEmpty. Operand 1569 states and 1617 transitions. [2019-12-07 17:21:47,748 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1366 [2019-12-07 17:21:47,749 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:21:47,749 INFO L410 BasicCegarLoop]: trace histogram [230, 229, 229, 229, 229, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:21:47,949 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 43 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:21:47,950 INFO L410 AbstractCegarLoop]: === Iteration 50 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:21:47,950 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:21:47,951 INFO L82 PathProgramCache]: Analyzing trace with hash -1160826203, now seen corresponding path program 34 times [2019-12-07 17:21:47,951 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:21:47,951 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1949414801] [2019-12-07 17:21:47,952 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:21:48,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:48,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:48,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:48,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:48,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:48,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:48,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:48,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:48,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:48,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:48,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:48,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:48,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:48,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:48,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:48,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:48,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:48,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:48,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:48,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:48,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:49,777 INFO L134 CoverageAnalysis]: Checked inductivity of 137296 backedges. 22706 proven. 1084 refuted. 0 times theorem prover too weak. 113506 trivial. 0 not checked. [2019-12-07 17:21:49,777 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1949414801] [2019-12-07 17:21:49,777 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [707808503] [2019-12-07 17:21:49,777 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:21:51,594 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 17:21:51,595 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:21:51,606 INFO L264 TraceCheckSpWp]: Trace formula consists of 3438 conjuncts, 43 conjunts are in the unsatisfiable core [2019-12-07 17:21:51,614 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:21:52,850 INFO L134 CoverageAnalysis]: Checked inductivity of 137296 backedges. 21717 proven. 990 refuted. 0 times theorem prover too weak. 114589 trivial. 0 not checked. [2019-12-07 17:21:52,851 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:21:52,851 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 22] total 66 [2019-12-07 17:21:52,851 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [656313970] [2019-12-07 17:21:52,852 INFO L442 AbstractCegarLoop]: Interpolant automaton has 67 states [2019-12-07 17:21:52,852 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:21:52,853 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2019-12-07 17:21:52,853 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=552, Invalid=3870, Unknown=0, NotChecked=0, Total=4422 [2019-12-07 17:21:52,853 INFO L87 Difference]: Start difference. First operand 1569 states and 1617 transitions. Second operand 67 states. [2019-12-07 17:21:57,641 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:21:57,641 INFO L93 Difference]: Finished difference Result 2283 states and 2473 transitions. [2019-12-07 17:21:57,641 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2019-12-07 17:21:57,641 INFO L78 Accepts]: Start accepts. Automaton has 67 states. Word has length 1365 [2019-12-07 17:21:57,642 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:21:57,646 INFO L225 Difference]: With dead ends: 2283 [2019-12-07 17:21:57,646 INFO L226 Difference]: Without dead ends: 2283 [2019-12-07 17:21:57,646 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1494 GetRequests, 1383 SyntacticMatches, 1 SemanticMatches, 110 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2976 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=1095, Invalid=11337, Unknown=0, NotChecked=0, Total=12432 [2019-12-07 17:21:57,648 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2283 states. [2019-12-07 17:21:57,660 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2283 to 1685. [2019-12-07 17:21:57,661 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1685 states. [2019-12-07 17:21:57,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1685 states to 1685 states and 1735 transitions. [2019-12-07 17:21:57,662 INFO L78 Accepts]: Start accepts. Automaton has 1685 states and 1735 transitions. Word has length 1365 [2019-12-07 17:21:57,663 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:21:57,663 INFO L462 AbstractCegarLoop]: Abstraction has 1685 states and 1735 transitions. [2019-12-07 17:21:57,663 INFO L463 AbstractCegarLoop]: Interpolant automaton has 67 states. [2019-12-07 17:21:57,663 INFO L276 IsEmpty]: Start isEmpty. Operand 1685 states and 1735 transitions. [2019-12-07 17:21:57,677 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1482 [2019-12-07 17:21:57,677 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:21:57,677 INFO L410 BasicCegarLoop]: trace histogram [251, 250, 250, 250, 250, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:21:57,878 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 44 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:21:57,878 INFO L410 AbstractCegarLoop]: === Iteration 51 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:21:57,879 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:21:57,879 INFO L82 PathProgramCache]: Analyzing trace with hash -667535262, now seen corresponding path program 35 times [2019-12-07 17:21:57,880 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:21:57,880 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [713186754] [2019-12-07 17:21:57,880 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:21:58,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:58,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:58,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:58,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:58,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:58,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:58,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:58,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:58,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:58,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:58,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:58,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:58,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:58,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:58,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:58,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:58,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:58,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:58,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:58,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:58,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:58,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:21:59,962 INFO L134 CoverageAnalysis]: Checked inductivity of 163295 backedges. 47483 proven. 3587 refuted. 0 times theorem prover too weak. 112225 trivial. 0 not checked. [2019-12-07 17:21:59,962 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [713186754] [2019-12-07 17:21:59,963 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1728587451] [2019-12-07 17:21:59,963 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:22:02,402 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 48 check-sat command(s) [2019-12-07 17:22:02,402 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:22:02,419 INFO L264 TraceCheckSpWp]: Trace formula consists of 3662 conjuncts, 48 conjunts are in the unsatisfiable core [2019-12-07 17:22:02,429 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:22:04,345 INFO L134 CoverageAnalysis]: Checked inductivity of 163295 backedges. 47409 proven. 5742 refuted. 0 times theorem prover too weak. 110144 trivial. 0 not checked. [2019-12-07 17:22:04,345 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:22:04,346 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 48] total 76 [2019-12-07 17:22:04,346 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1614990739] [2019-12-07 17:22:04,347 INFO L442 AbstractCegarLoop]: Interpolant automaton has 76 states [2019-12-07 17:22:04,347 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:22:04,348 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 76 interpolants. [2019-12-07 17:22:04,348 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1030, Invalid=4670, Unknown=0, NotChecked=0, Total=5700 [2019-12-07 17:22:04,348 INFO L87 Difference]: Start difference. First operand 1685 states and 1735 transitions. Second operand 76 states. [2019-12-07 17:22:06,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:22:06,697 INFO L93 Difference]: Finished difference Result 2349 states and 2545 transitions. [2019-12-07 17:22:06,697 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 70 states. [2019-12-07 17:22:06,697 INFO L78 Accepts]: Start accepts. Automaton has 76 states. Word has length 1481 [2019-12-07 17:22:06,698 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:22:06,701 INFO L225 Difference]: With dead ends: 2349 [2019-12-07 17:22:06,701 INFO L226 Difference]: Without dead ends: 2343 [2019-12-07 17:22:06,702 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1616 GetRequests, 1495 SyntacticMatches, 0 SemanticMatches, 121 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3660 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=3188, Invalid=11818, Unknown=0, NotChecked=0, Total=15006 [2019-12-07 17:22:06,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2343 states. [2019-12-07 17:22:06,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2343 to 1716. [2019-12-07 17:22:06,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1716 states. [2019-12-07 17:22:06,719 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1716 states to 1716 states and 1769 transitions. [2019-12-07 17:22:06,719 INFO L78 Accepts]: Start accepts. Automaton has 1716 states and 1769 transitions. Word has length 1481 [2019-12-07 17:22:06,720 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:22:06,720 INFO L462 AbstractCegarLoop]: Abstraction has 1716 states and 1769 transitions. [2019-12-07 17:22:06,720 INFO L463 AbstractCegarLoop]: Interpolant automaton has 76 states. [2019-12-07 17:22:06,720 INFO L276 IsEmpty]: Start isEmpty. Operand 1716 states and 1769 transitions. [2019-12-07 17:22:06,734 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1487 [2019-12-07 17:22:06,734 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:22:06,735 INFO L410 BasicCegarLoop]: trace histogram [252, 251, 251, 251, 251, 21, 21, 21, 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:22:06,935 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 45 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:22:06,935 INFO L410 AbstractCegarLoop]: === Iteration 52 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:22:06,936 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:22:06,936 INFO L82 PathProgramCache]: Analyzing trace with hash 9778855, now seen corresponding path program 36 times [2019-12-07 17:22:06,936 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:22:06,936 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [387277851] [2019-12-07 17:22:06,937 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:22:07,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:07,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:07,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:07,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:07,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:07,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:07,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:07,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:07,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:07,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:07,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:07,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:07,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:07,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:07,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:07,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:07,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:07,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:07,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:07,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:07,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:07,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:09,010 INFO L134 CoverageAnalysis]: Checked inductivity of 164567 backedges. 26141 proven. 1201 refuted. 0 times theorem prover too weak. 137225 trivial. 0 not checked. [2019-12-07 17:22:09,010 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [387277851] [2019-12-07 17:22:09,011 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [406735715] [2019-12-07 17:22:09,011 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:22:11,247 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 43 check-sat command(s) [2019-12-07 17:22:11,247 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:22:11,256 INFO L264 TraceCheckSpWp]: Trace formula consists of 2928 conjuncts, 25 conjunts are in the unsatisfiable core [2019-12-07 17:22:11,265 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:22:12,700 INFO L134 CoverageAnalysis]: Checked inductivity of 164567 backedges. 25050 proven. 1092 refuted. 0 times theorem prover too weak. 138425 trivial. 0 not checked. [2019-12-07 17:22:12,700 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:22:12,701 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 24] total 71 [2019-12-07 17:22:12,701 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [293894199] [2019-12-07 17:22:12,702 INFO L442 AbstractCegarLoop]: Interpolant automaton has 72 states [2019-12-07 17:22:12,702 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:22:12,702 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 72 interpolants. [2019-12-07 17:22:12,703 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=816, Invalid=4296, Unknown=0, NotChecked=0, Total=5112 [2019-12-07 17:22:12,703 INFO L87 Difference]: Start difference. First operand 1716 states and 1769 transitions. Second operand 72 states. [2019-12-07 17:22:17,117 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:22:17,117 INFO L93 Difference]: Finished difference Result 2523 states and 2745 transitions. [2019-12-07 17:22:17,118 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2019-12-07 17:22:17,118 INFO L78 Accepts]: Start accepts. Automaton has 72 states. Word has length 1486 [2019-12-07 17:22:17,118 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:22:17,122 INFO L225 Difference]: With dead ends: 2523 [2019-12-07 17:22:17,123 INFO L226 Difference]: Without dead ends: 2523 [2019-12-07 17:22:17,123 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1621 GetRequests, 1504 SyntacticMatches, 0 SemanticMatches, 117 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3368 ImplicationChecksByTransitivity, 3.5s TimeCoverageRelationStatistics Valid=2318, Invalid=11724, Unknown=0, NotChecked=0, Total=14042 [2019-12-07 17:22:17,125 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2523 states. [2019-12-07 17:22:17,140 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2523 to 1837. [2019-12-07 17:22:17,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1837 states. [2019-12-07 17:22:17,142 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1837 states to 1837 states and 1892 transitions. [2019-12-07 17:22:17,142 INFO L78 Accepts]: Start accepts. Automaton has 1837 states and 1892 transitions. Word has length 1486 [2019-12-07 17:22:17,143 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:22:17,143 INFO L462 AbstractCegarLoop]: Abstraction has 1837 states and 1892 transitions. [2019-12-07 17:22:17,143 INFO L463 AbstractCegarLoop]: Interpolant automaton has 72 states. [2019-12-07 17:22:17,143 INFO L276 IsEmpty]: Start isEmpty. Operand 1837 states and 1892 transitions. [2019-12-07 17:22:17,159 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1608 [2019-12-07 17:22:17,159 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:22:17,160 INFO L410 BasicCegarLoop]: trace histogram [274, 273, 273, 273, 273, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:22:17,360 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 46 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:22:17,360 INFO L410 AbstractCegarLoop]: === Iteration 53 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:22:17,361 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:22:17,361 INFO L82 PathProgramCache]: Analyzing trace with hash -1747254261, now seen corresponding path program 37 times [2019-12-07 17:22:17,362 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:22:17,362 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1360567853] [2019-12-07 17:22:17,362 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:22:17,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:17,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:17,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:17,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:17,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:17,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:17,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:17,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:17,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:17,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:17,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:17,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:17,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:17,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:17,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:17,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:17,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:17,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:17,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:17,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:17,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:17,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:17,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:19,712 INFO L134 CoverageAnalysis]: Checked inductivity of 194313 backedges. 54562 proven. 3936 refuted. 0 times theorem prover too weak. 135815 trivial. 0 not checked. [2019-12-07 17:22:19,712 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1360567853] [2019-12-07 17:22:19,712 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [33958277] [2019-12-07 17:22:19,713 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:22:20,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:20,050 INFO L264 TraceCheckSpWp]: Trace formula consists of 4032 conjuncts, 46 conjunts are in the unsatisfiable core [2019-12-07 17:22:20,059 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:22:22,054 INFO L134 CoverageAnalysis]: Checked inductivity of 194313 backedges. 54798 proven. 1071 refuted. 0 times theorem prover too weak. 138444 trivial. 0 not checked. [2019-12-07 17:22:22,054 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:22:22,055 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [51, 46] total 73 [2019-12-07 17:22:22,055 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1507936666] [2019-12-07 17:22:22,056 INFO L442 AbstractCegarLoop]: Interpolant automaton has 73 states [2019-12-07 17:22:22,056 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:22:22,057 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2019-12-07 17:22:22,057 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1070, Invalid=4186, Unknown=0, NotChecked=0, Total=5256 [2019-12-07 17:22:22,057 INFO L87 Difference]: Start difference. First operand 1837 states and 1892 transitions. Second operand 73 states. [2019-12-07 17:22:24,309 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:22:24,310 INFO L93 Difference]: Finished difference Result 2571 states and 2791 transitions. [2019-12-07 17:22:24,310 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2019-12-07 17:22:24,310 INFO L78 Accepts]: Start accepts. Automaton has 73 states. Word has length 1607 [2019-12-07 17:22:24,311 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:22:24,317 INFO L225 Difference]: With dead ends: 2571 [2019-12-07 17:22:24,317 INFO L226 Difference]: Without dead ends: 2565 [2019-12-07 17:22:24,319 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1743 GetRequests, 1628 SyntacticMatches, 0 SemanticMatches, 115 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3297 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=3014, Invalid=10558, Unknown=0, NotChecked=0, Total=13572 [2019-12-07 17:22:24,321 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2565 states. [2019-12-07 17:22:24,346 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2565 to 1842. [2019-12-07 17:22:24,347 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1842 states. [2019-12-07 17:22:24,348 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1842 states to 1842 states and 1896 transitions. [2019-12-07 17:22:24,349 INFO L78 Accepts]: Start accepts. Automaton has 1842 states and 1896 transitions. Word has length 1607 [2019-12-07 17:22:24,349 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:22:24,349 INFO L462 AbstractCegarLoop]: Abstraction has 1842 states and 1896 transitions. [2019-12-07 17:22:24,349 INFO L463 AbstractCegarLoop]: Interpolant automaton has 73 states. [2019-12-07 17:22:24,349 INFO L276 IsEmpty]: Start isEmpty. Operand 1842 states and 1896 transitions. [2019-12-07 17:22:24,365 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1613 [2019-12-07 17:22:24,365 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:22:24,366 INFO L410 BasicCegarLoop]: trace histogram [275, 274, 274, 274, 274, 22, 22, 22, 21, 21, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:22:24,566 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 47 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:22:24,567 INFO L410 AbstractCegarLoop]: === Iteration 54 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:22:24,567 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:22:24,567 INFO L82 PathProgramCache]: Analyzing trace with hash 318401322, now seen corresponding path program 38 times [2019-12-07 17:22:24,567 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:22:24,567 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [177137830] [2019-12-07 17:22:24,567 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:22:24,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:25,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:25,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:25,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:25,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:25,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:25,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:25,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:25,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:25,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:25,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:25,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:25,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:25,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:25,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:25,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:25,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:25,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:25,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:25,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:25,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:25,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:25,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:26,933 INFO L134 CoverageAnalysis]: Checked inductivity of 195701 backedges. 29905 proven. 1324 refuted. 0 times theorem prover too weak. 164472 trivial. 0 not checked. [2019-12-07 17:22:26,933 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [177137830] [2019-12-07 17:22:26,933 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [227549763] [2019-12-07 17:22:26,933 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:22:27,247 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 17:22:27,247 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:22:27,256 INFO L264 TraceCheckSpWp]: Trace formula consists of 4044 conjuncts, 47 conjunts are in the unsatisfiable core [2019-12-07 17:22:27,264 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:22:28,878 INFO L134 CoverageAnalysis]: Checked inductivity of 195701 backedges. 28707 proven. 1199 refuted. 0 times theorem prover too weak. 165795 trivial. 0 not checked. [2019-12-07 17:22:28,879 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:22:28,879 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 24] total 72 [2019-12-07 17:22:28,879 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1942926224] [2019-12-07 17:22:28,881 INFO L442 AbstractCegarLoop]: Interpolant automaton has 73 states [2019-12-07 17:22:28,881 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:22:28,881 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2019-12-07 17:22:28,881 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=650, Invalid=4606, Unknown=0, NotChecked=0, Total=5256 [2019-12-07 17:22:28,881 INFO L87 Difference]: Start difference. First operand 1842 states and 1896 transitions. Second operand 73 states. [2019-12-07 17:22:40,694 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:22:40,694 INFO L93 Difference]: Finished difference Result 2758 states and 3005 transitions. [2019-12-07 17:22:40,695 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 74 states. [2019-12-07 17:22:40,696 INFO L78 Accepts]: Start accepts. Automaton has 73 states. Word has length 1612 [2019-12-07 17:22:40,698 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:22:40,709 INFO L225 Difference]: With dead ends: 2758 [2019-12-07 17:22:40,710 INFO L226 Difference]: Without dead ends: 2758 [2019-12-07 17:22:40,712 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1753 GetRequests, 1632 SyntacticMatches, 1 SemanticMatches, 120 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3559 ImplicationChecksByTransitivity, 5.5s TimeCoverageRelationStatistics Valid=1266, Invalid=13496, Unknown=0, NotChecked=0, Total=14762 [2019-12-07 17:22:40,715 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2758 states. [2019-12-07 17:22:40,745 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2758 to 1968. [2019-12-07 17:22:40,745 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1968 states. [2019-12-07 17:22:40,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1968 states to 1968 states and 2024 transitions. [2019-12-07 17:22:40,748 INFO L78 Accepts]: Start accepts. Automaton has 1968 states and 2024 transitions. Word has length 1612 [2019-12-07 17:22:40,749 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:22:40,749 INFO L462 AbstractCegarLoop]: Abstraction has 1968 states and 2024 transitions. [2019-12-07 17:22:40,749 INFO L463 AbstractCegarLoop]: Interpolant automaton has 73 states. [2019-12-07 17:22:40,749 INFO L276 IsEmpty]: Start isEmpty. Operand 1968 states and 2024 transitions. [2019-12-07 17:22:40,771 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1739 [2019-12-07 17:22:40,771 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:22:40,771 INFO L410 BasicCegarLoop]: trace histogram [298, 297, 297, 297, 297, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:22:40,972 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 48 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:22:40,972 INFO L410 AbstractCegarLoop]: === Iteration 55 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:22:40,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:22:40,972 INFO L82 PathProgramCache]: Analyzing trace with hash -1675122425, now seen corresponding path program 39 times [2019-12-07 17:22:40,972 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:22:40,972 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [633981971] [2019-12-07 17:22:40,973 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:22:41,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:41,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:41,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:41,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:41,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:41,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:41,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:41,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:41,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:41,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:41,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:41,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:41,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:41,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:41,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:41,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:41,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:41,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:41,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:41,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:41,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:41,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:41,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:41,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:43,607 INFO L134 CoverageAnalysis]: Checked inductivity of 229537 backedges. 62309 proven. 4301 refuted. 0 times theorem prover too weak. 162927 trivial. 0 not checked. [2019-12-07 17:22:43,607 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [633981971] [2019-12-07 17:22:43,607 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [532489115] [2019-12-07 17:22:43,607 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:22:44,499 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2019-12-07 17:22:44,499 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:22:44,504 INFO L264 TraceCheckSpWp]: Trace formula consists of 1956 conjuncts, 27 conjunts are in the unsatisfiable core [2019-12-07 17:22:44,513 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:22:46,475 INFO L134 CoverageAnalysis]: Checked inductivity of 229537 backedges. 32586 proven. 1311 refuted. 0 times theorem prover too weak. 195640 trivial. 0 not checked. [2019-12-07 17:22:46,475 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:22:46,476 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [53, 26] total 78 [2019-12-07 17:22:46,476 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [249848048] [2019-12-07 17:22:46,478 INFO L442 AbstractCegarLoop]: Interpolant automaton has 78 states [2019-12-07 17:22:46,478 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:22:46,478 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 78 interpolants. [2019-12-07 17:22:46,478 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1169, Invalid=4837, Unknown=0, NotChecked=0, Total=6006 [2019-12-07 17:22:46,478 INFO L87 Difference]: Start difference. First operand 1968 states and 2024 transitions. Second operand 78 states. [2019-12-07 17:22:49,348 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:22:49,348 INFO L93 Difference]: Finished difference Result 2930 states and 3201 transitions. [2019-12-07 17:22:49,349 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2019-12-07 17:22:49,349 INFO L78 Accepts]: Start accepts. Automaton has 78 states. Word has length 1738 [2019-12-07 17:22:49,349 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:22:49,353 INFO L225 Difference]: With dead ends: 2930 [2019-12-07 17:22:49,353 INFO L226 Difference]: Without dead ends: 2924 [2019-12-07 17:22:49,354 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1881 GetRequests, 1758 SyntacticMatches, 0 SemanticMatches, 123 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3835 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=3422, Invalid=12078, Unknown=0, NotChecked=0, Total=15500 [2019-12-07 17:22:49,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2924 states. [2019-12-07 17:22:49,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2924 to 1978. [2019-12-07 17:22:49,374 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1978 states. [2019-12-07 17:22:49,375 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1978 states to 1978 states and 2034 transitions. [2019-12-07 17:22:49,376 INFO L78 Accepts]: Start accepts. Automaton has 1978 states and 2034 transitions. Word has length 1738 [2019-12-07 17:22:49,376 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:22:49,376 INFO L462 AbstractCegarLoop]: Abstraction has 1978 states and 2034 transitions. [2019-12-07 17:22:49,376 INFO L463 AbstractCegarLoop]: Interpolant automaton has 78 states. [2019-12-07 17:22:49,376 INFO L276 IsEmpty]: Start isEmpty. Operand 1978 states and 2034 transitions. [2019-12-07 17:22:49,395 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1749 [2019-12-07 17:22:49,395 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:22:49,396 INFO L410 BasicCegarLoop]: trace histogram [300, 299, 299, 299, 299, 23, 23, 23, 22, 22, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:22:49,596 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 49 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:22:49,596 INFO L410 AbstractCegarLoop]: === Iteration 56 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:22:49,596 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:22:49,596 INFO L82 PathProgramCache]: Analyzing trace with hash 1749257613, now seen corresponding path program 40 times [2019-12-07 17:22:49,597 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:22:49,597 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1117627096] [2019-12-07 17:22:49,597 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:22:49,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:50,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:50,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:50,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:50,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:50,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:50,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:50,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:50,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:50,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:50,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:50,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:50,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:50,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:50,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:50,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:50,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:50,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:50,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:50,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:50,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:50,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:50,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:50,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:22:52,137 INFO L134 CoverageAnalysis]: Checked inductivity of 232560 backedges. 35503 proven. 1477 refuted. 0 times theorem prover too weak. 195580 trivial. 0 not checked. [2019-12-07 17:22:52,137 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1117627096] [2019-12-07 17:22:52,137 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1959534692] [2019-12-07 17:22:52,137 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:22:52,433 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 17:22:52,433 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:22:52,442 INFO L264 TraceCheckSpWp]: Trace formula consists of 3695 conjuncts, 56 conjunts are in the unsatisfiable core [2019-12-07 17:22:52,452 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:22:54,923 INFO L134 CoverageAnalysis]: Checked inductivity of 232560 backedges. 35327 proven. 4789 refuted. 0 times theorem prover too weak. 192444 trivial. 0 not checked. [2019-12-07 17:22:54,923 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:22:54,924 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [53, 55] total 83 [2019-12-07 17:22:54,924 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1783791898] [2019-12-07 17:22:54,926 INFO L442 AbstractCegarLoop]: Interpolant automaton has 83 states [2019-12-07 17:22:54,926 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:22:54,926 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 83 interpolants. [2019-12-07 17:22:54,927 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1393, Invalid=5413, Unknown=0, NotChecked=0, Total=6806 [2019-12-07 17:22:54,927 INFO L87 Difference]: Start difference. First operand 1978 states and 2034 transitions. Second operand 83 states. [2019-12-07 17:23:02,446 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:23:02,447 INFO L93 Difference]: Finished difference Result 3000 states and 3258 transitions. [2019-12-07 17:23:02,448 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2019-12-07 17:23:02,448 INFO L78 Accepts]: Start accepts. Automaton has 83 states. Word has length 1748 [2019-12-07 17:23:02,450 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:23:02,459 INFO L225 Difference]: With dead ends: 3000 [2019-12-07 17:23:02,459 INFO L226 Difference]: Without dead ends: 3000 [2019-12-07 17:23:02,462 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1900 GetRequests, 1764 SyntacticMatches, 0 SemanticMatches, 136 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3795 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=4039, Invalid=14867, Unknown=0, NotChecked=0, Total=18906 [2019-12-07 17:23:02,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3000 states. [2019-12-07 17:23:02,494 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3000 to 2624. [2019-12-07 17:23:02,494 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2624 states. [2019-12-07 17:23:02,496 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2624 states to 2624 states and 2770 transitions. [2019-12-07 17:23:02,496 INFO L78 Accepts]: Start accepts. Automaton has 2624 states and 2770 transitions. Word has length 1748 [2019-12-07 17:23:02,497 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:23:02,497 INFO L462 AbstractCegarLoop]: Abstraction has 2624 states and 2770 transitions. [2019-12-07 17:23:02,497 INFO L463 AbstractCegarLoop]: Interpolant automaton has 83 states. [2019-12-07 17:23:02,497 INFO L276 IsEmpty]: Start isEmpty. Operand 2624 states and 2770 transitions. [2019-12-07 17:23:02,518 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1875 [2019-12-07 17:23:02,518 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:23:02,519 INFO L410 BasicCegarLoop]: trace histogram [323, 322, 322, 322, 322, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:23:02,719 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 50 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:23:02,720 INFO L410 AbstractCegarLoop]: === Iteration 57 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:23:02,720 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:23:02,720 INFO L82 PathProgramCache]: Analyzing trace with hash 754168784, now seen corresponding path program 41 times [2019-12-07 17:23:02,721 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:23:02,721 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1210835098] [2019-12-07 17:23:02,722 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:23:02,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:03,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:03,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:03,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:03,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:03,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:03,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:03,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:03,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:03,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:03,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:03,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:03,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:03,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:03,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:03,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:03,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:03,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:03,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:03,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:03,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:03,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:03,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:03,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:03,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:05,724 INFO L134 CoverageAnalysis]: Checked inductivity of 269330 backedges. 70754 proven. 4682 refuted. 0 times theorem prover too weak. 193894 trivial. 0 not checked. [2019-12-07 17:23:05,724 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1210835098] [2019-12-07 17:23:05,724 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1971869718] [2019-12-07 17:23:05,724 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:23:10,216 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 52 check-sat command(s) [2019-12-07 17:23:10,216 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:23:10,241 INFO L264 TraceCheckSpWp]: Trace formula consists of 4625 conjuncts, 54 conjunts are in the unsatisfiable core [2019-12-07 17:23:10,253 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:23:12,970 INFO L134 CoverageAnalysis]: Checked inductivity of 269330 backedges. 70650 proven. 7533 refuted. 0 times theorem prover too weak. 191147 trivial. 0 not checked. [2019-12-07 17:23:12,970 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:23:12,971 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [55, 54] total 85 [2019-12-07 17:23:12,971 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1231062447] [2019-12-07 17:23:12,972 INFO L442 AbstractCegarLoop]: Interpolant automaton has 85 states [2019-12-07 17:23:12,972 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:23:12,973 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 85 interpolants. [2019-12-07 17:23:12,973 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1315, Invalid=5825, Unknown=0, NotChecked=0, Total=7140 [2019-12-07 17:23:12,973 INFO L87 Difference]: Start difference. First operand 2624 states and 2770 transitions. Second operand 85 states. [2019-12-07 17:23:15,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:23:15,868 INFO L93 Difference]: Finished difference Result 3024 states and 3288 transitions. [2019-12-07 17:23:15,868 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 79 states. [2019-12-07 17:23:15,868 INFO L78 Accepts]: Start accepts. Automaton has 85 states. Word has length 1874 [2019-12-07 17:23:15,869 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:23:15,873 INFO L225 Difference]: With dead ends: 3024 [2019-12-07 17:23:15,874 INFO L226 Difference]: Without dead ends: 3018 [2019-12-07 17:23:15,875 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2027 GetRequests, 1891 SyntacticMatches, 0 SemanticMatches, 136 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4683 ImplicationChecksByTransitivity, 3.5s TimeCoverageRelationStatistics Valid=4028, Invalid=14878, Unknown=0, NotChecked=0, Total=18906 [2019-12-07 17:23:15,877 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3018 states. [2019-12-07 17:23:15,900 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3018 to 2645. [2019-12-07 17:23:15,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2645 states. [2019-12-07 17:23:15,903 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2645 states to 2645 states and 2792 transitions. [2019-12-07 17:23:15,903 INFO L78 Accepts]: Start accepts. Automaton has 2645 states and 2792 transitions. Word has length 1874 [2019-12-07 17:23:15,903 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:23:15,903 INFO L462 AbstractCegarLoop]: Abstraction has 2645 states and 2792 transitions. [2019-12-07 17:23:15,903 INFO L463 AbstractCegarLoop]: Interpolant automaton has 85 states. [2019-12-07 17:23:15,903 INFO L276 IsEmpty]: Start isEmpty. Operand 2645 states and 2792 transitions. [2019-12-07 17:23:15,925 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1880 [2019-12-07 17:23:15,925 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:23:15,926 INFO L410 BasicCegarLoop]: trace histogram [324, 323, 323, 323, 323, 24, 24, 24, 23, 23, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:23:16,126 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 51 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:23:16,127 INFO L410 AbstractCegarLoop]: === Iteration 58 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:23:16,127 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:23:16,128 INFO L82 PathProgramCache]: Analyzing trace with hash -1687206139, now seen corresponding path program 42 times [2019-12-07 17:23:16,128 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:23:16,128 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [160431467] [2019-12-07 17:23:16,129 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:23:16,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:17,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:17,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:17,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:17,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:17,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:17,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:17,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:17,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:17,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:17,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:17,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:17,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:17,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:17,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:17,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:17,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:17,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:17,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:17,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:17,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:17,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:17,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:17,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:17,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:19,132 INFO L134 CoverageAnalysis]: Checked inductivity of 270965 backedges. 38480 proven. 1588 refuted. 0 times theorem prover too weak. 230897 trivial. 0 not checked. [2019-12-07 17:23:19,132 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [160431467] [2019-12-07 17:23:19,132 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [25924684] [2019-12-07 17:23:19,133 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:23:28,731 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 49 check-sat command(s) [2019-12-07 17:23:28,731 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:23:28,755 INFO L264 TraceCheckSpWp]: Trace formula consists of 4158 conjuncts, 44 conjunts are in the unsatisfiable core [2019-12-07 17:23:28,766 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:23:31,097 INFO L134 CoverageAnalysis]: Checked inductivity of 270965 backedges. 37053 proven. 2142 refuted. 0 times theorem prover too weak. 231770 trivial. 0 not checked. [2019-12-07 17:23:31,097 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:23:31,098 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 33] total 85 [2019-12-07 17:23:31,098 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1239864956] [2019-12-07 17:23:31,099 INFO L442 AbstractCegarLoop]: Interpolant automaton has 86 states [2019-12-07 17:23:31,099 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:23:31,099 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 86 interpolants. [2019-12-07 17:23:31,099 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1153, Invalid=6157, Unknown=0, NotChecked=0, Total=7310 [2019-12-07 17:23:31,099 INFO L87 Difference]: Start difference. First operand 2645 states and 2792 transitions. Second operand 86 states. [2019-12-07 17:23:38,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:23:38,731 INFO L93 Difference]: Finished difference Result 3165 states and 3432 transitions. [2019-12-07 17:23:38,731 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 80 states. [2019-12-07 17:23:38,731 INFO L78 Accepts]: Start accepts. Automaton has 86 states. Word has length 1879 [2019-12-07 17:23:38,732 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:23:38,736 INFO L225 Difference]: With dead ends: 3165 [2019-12-07 17:23:38,736 INFO L226 Difference]: Without dead ends: 3165 [2019-12-07 17:23:38,737 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2032 GetRequests, 1895 SyntacticMatches, 0 SemanticMatches, 137 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5061 ImplicationChecksByTransitivity, 4.1s TimeCoverageRelationStatistics Valid=3045, Invalid=16137, Unknown=0, NotChecked=0, Total=19182 [2019-12-07 17:23:38,739 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3165 states. [2019-12-07 17:23:38,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3165 to 2781. [2019-12-07 17:23:38,768 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2781 states. [2019-12-07 17:23:38,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2781 states to 2781 states and 2930 transitions. [2019-12-07 17:23:38,772 INFO L78 Accepts]: Start accepts. Automaton has 2781 states and 2930 transitions. Word has length 1879 [2019-12-07 17:23:38,773 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:23:38,773 INFO L462 AbstractCegarLoop]: Abstraction has 2781 states and 2930 transitions. [2019-12-07 17:23:38,773 INFO L463 AbstractCegarLoop]: Interpolant automaton has 86 states. [2019-12-07 17:23:38,773 INFO L276 IsEmpty]: Start isEmpty. Operand 2781 states and 2930 transitions. [2019-12-07 17:23:38,798 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2016 [2019-12-07 17:23:38,798 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:23:38,799 INFO L410 BasicCegarLoop]: trace histogram [349, 348, 348, 348, 348, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:23:39,000 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 52 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:23:39,000 INFO L410 AbstractCegarLoop]: === Iteration 59 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:23:39,000 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:23:39,001 INFO L82 PathProgramCache]: Analyzing trace with hash -2048382334, now seen corresponding path program 43 times [2019-12-07 17:23:39,002 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:23:39,002 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [934071654] [2019-12-07 17:23:39,002 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:23:39,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:39,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:39,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:39,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:39,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:39,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:39,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:39,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:39,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:39,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:39,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:39,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:39,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:39,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:39,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:39,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:39,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:39,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:39,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:39,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:39,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:39,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:39,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:39,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:39,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:39,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:42,349 INFO L134 CoverageAnalysis]: Checked inductivity of 314070 backedges. 79927 proven. 5079 refuted. 0 times theorem prover too weak. 229064 trivial. 0 not checked. [2019-12-07 17:23:42,349 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [934071654] [2019-12-07 17:23:42,349 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1561761140] [2019-12-07 17:23:42,349 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:23:42,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:42,742 INFO L264 TraceCheckSpWp]: Trace formula consists of 5031 conjuncts, 52 conjunts are in the unsatisfiable core [2019-12-07 17:23:42,753 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:23:45,587 INFO L134 CoverageAnalysis]: Checked inductivity of 314070 backedges. 80196 proven. 1404 refuted. 0 times theorem prover too weak. 232470 trivial. 0 not checked. [2019-12-07 17:23:45,587 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:23:45,588 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [57, 52] total 82 [2019-12-07 17:23:45,588 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [200696649] [2019-12-07 17:23:45,588 INFO L442 AbstractCegarLoop]: Interpolant automaton has 82 states [2019-12-07 17:23:45,588 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:23:45,589 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 82 interpolants. [2019-12-07 17:23:45,589 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1364, Invalid=5278, Unknown=0, NotChecked=0, Total=6642 [2019-12-07 17:23:45,589 INFO L87 Difference]: Start difference. First operand 2781 states and 2930 transitions. Second operand 82 states. [2019-12-07 17:23:47,764 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:23:47,764 INFO L93 Difference]: Finished difference Result 3165 states and 3430 transitions. [2019-12-07 17:23:47,764 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 77 states. [2019-12-07 17:23:47,764 INFO L78 Accepts]: Start accepts. Automaton has 82 states. Word has length 2015 [2019-12-07 17:23:47,765 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:23:47,768 INFO L225 Difference]: With dead ends: 3165 [2019-12-07 17:23:47,768 INFO L226 Difference]: Without dead ends: 3159 [2019-12-07 17:23:47,769 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2169 GetRequests, 2039 SyntacticMatches, 0 SemanticMatches, 130 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4272 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=3836, Invalid=13456, Unknown=0, NotChecked=0, Total=17292 [2019-12-07 17:23:47,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3159 states. [2019-12-07 17:23:47,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3159 to 2786. [2019-12-07 17:23:47,789 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2786 states. [2019-12-07 17:23:47,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2786 states to 2786 states and 2934 transitions. [2019-12-07 17:23:47,792 INFO L78 Accepts]: Start accepts. Automaton has 2786 states and 2934 transitions. Word has length 2015 [2019-12-07 17:23:47,793 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:23:47,793 INFO L462 AbstractCegarLoop]: Abstraction has 2786 states and 2934 transitions. [2019-12-07 17:23:47,793 INFO L463 AbstractCegarLoop]: Interpolant automaton has 82 states. [2019-12-07 17:23:47,793 INFO L276 IsEmpty]: Start isEmpty. Operand 2786 states and 2934 transitions. [2019-12-07 17:23:47,815 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2021 [2019-12-07 17:23:47,816 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:23:47,816 INFO L410 BasicCegarLoop]: trace histogram [350, 349, 349, 349, 349, 25, 25, 25, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:23:48,017 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 53 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:23:48,017 INFO L410 AbstractCegarLoop]: === Iteration 60 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:23:48,017 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:23:48,018 INFO L82 PathProgramCache]: Analyzing trace with hash 1794680711, now seen corresponding path program 44 times [2019-12-07 17:23:48,018 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:23:48,018 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [427828233] [2019-12-07 17:23:48,019 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:23:48,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:49,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:49,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:49,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:49,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:49,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:49,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:49,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:49,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:49,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:49,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:49,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:49,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:49,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:49,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:49,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:49,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:49,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:49,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:49,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:49,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:49,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:49,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:49,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:49,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:49,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:23:51,401 INFO L134 CoverageAnalysis]: Checked inductivity of 315836 backedges. 43321 proven. 1729 refuted. 0 times theorem prover too weak. 270786 trivial. 0 not checked. [2019-12-07 17:23:51,401 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [427828233] [2019-12-07 17:23:51,401 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [704351202] [2019-12-07 17:23:51,401 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:23:51,810 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 17:23:51,810 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:23:51,821 INFO L264 TraceCheckSpWp]: Trace formula consists of 5043 conjuncts, 53 conjunts are in the unsatisfiable core [2019-12-07 17:23:51,831 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:23:54,219 INFO L134 CoverageAnalysis]: Checked inductivity of 315836 backedges. 41772 proven. 1550 refuted. 0 times theorem prover too weak. 272514 trivial. 0 not checked. [2019-12-07 17:23:54,219 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:23:54,220 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 27] total 81 [2019-12-07 17:23:54,220 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [502710106] [2019-12-07 17:23:54,221 INFO L442 AbstractCegarLoop]: Interpolant automaton has 82 states [2019-12-07 17:23:54,221 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:23:54,221 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 82 interpolants. [2019-12-07 17:23:54,221 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=812, Invalid=5830, Unknown=0, NotChecked=0, Total=6642 [2019-12-07 17:23:54,221 INFO L87 Difference]: Start difference. First operand 2786 states and 2934 transitions. Second operand 82 states. [2019-12-07 17:24:03,941 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:24:03,941 INFO L93 Difference]: Finished difference Result 3319 states and 3588 transitions. [2019-12-07 17:24:03,941 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 83 states. [2019-12-07 17:24:03,941 INFO L78 Accepts]: Start accepts. Automaton has 82 states. Word has length 2020 [2019-12-07 17:24:03,942 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:24:03,945 INFO L225 Difference]: With dead ends: 3319 [2019-12-07 17:24:03,945 INFO L226 Difference]: Without dead ends: 3319 [2019-12-07 17:24:03,946 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2179 GetRequests, 2043 SyntacticMatches, 1 SemanticMatches, 135 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4531 ImplicationChecksByTransitivity, 3.5s TimeCoverageRelationStatistics Valid=1545, Invalid=17087, Unknown=0, NotChecked=0, Total=18632 [2019-12-07 17:24:03,947 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3319 states. [2019-12-07 17:24:03,965 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3319 to 2927. [2019-12-07 17:24:03,965 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2927 states. [2019-12-07 17:24:03,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2927 states to 2927 states and 3077 transitions. [2019-12-07 17:24:03,968 INFO L78 Accepts]: Start accepts. Automaton has 2927 states and 3077 transitions. Word has length 2020 [2019-12-07 17:24:03,968 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:24:03,968 INFO L462 AbstractCegarLoop]: Abstraction has 2927 states and 3077 transitions. [2019-12-07 17:24:03,968 INFO L463 AbstractCegarLoop]: Interpolant automaton has 82 states. [2019-12-07 17:24:03,968 INFO L276 IsEmpty]: Start isEmpty. Operand 2927 states and 3077 transitions. [2019-12-07 17:24:03,994 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2162 [2019-12-07 17:24:03,994 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:24:03,995 INFO L410 BasicCegarLoop]: trace histogram [376, 375, 375, 375, 375, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:24:04,195 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 54 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:24:04,196 INFO L410 AbstractCegarLoop]: === Iteration 61 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:24:04,196 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:24:04,197 INFO L82 PathProgramCache]: Analyzing trace with hash 567594603, now seen corresponding path program 45 times [2019-12-07 17:24:04,198 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:24:04,198 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [677985356] [2019-12-07 17:24:04,199 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:24:04,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:04,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:04,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:04,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:04,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:04,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:04,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:04,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:04,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:04,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:04,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:04,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:04,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:04,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:04,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:04,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:04,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:04,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:04,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:04,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:04,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:05,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:05,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:05,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:05,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:05,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:05,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:07,955 INFO L134 CoverageAnalysis]: Checked inductivity of 364150 backedges. 89858 proven. 5492 refuted. 0 times theorem prover too weak. 268800 trivial. 0 not checked. [2019-12-07 17:24:07,955 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [677985356] [2019-12-07 17:24:07,955 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [181722603] [2019-12-07 17:24:07,955 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:24:09,409 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) [2019-12-07 17:24:09,410 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:24:09,418 INFO L264 TraceCheckSpWp]: Trace formula consists of 2481 conjuncts, 30 conjunts are in the unsatisfiable core [2019-12-07 17:24:09,429 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:24:12,210 INFO L134 CoverageAnalysis]: Checked inductivity of 364150 backedges. 46743 proven. 1677 refuted. 0 times theorem prover too weak. 315730 trivial. 0 not checked. [2019-12-07 17:24:12,210 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:24:12,211 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 29] total 87 [2019-12-07 17:24:12,211 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [692832642] [2019-12-07 17:24:12,212 INFO L442 AbstractCegarLoop]: Interpolant automaton has 87 states [2019-12-07 17:24:12,212 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:24:12,212 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 87 interpolants. [2019-12-07 17:24:12,212 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1475, Invalid=6007, Unknown=0, NotChecked=0, Total=7482 [2019-12-07 17:24:12,212 INFO L87 Difference]: Start difference. First operand 2927 states and 3077 transitions. Second operand 87 states. [2019-12-07 17:24:17,091 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:24:17,091 INFO L93 Difference]: Finished difference Result 3347 states and 3617 transitions. [2019-12-07 17:24:17,092 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2019-12-07 17:24:17,092 INFO L78 Accepts]: Start accepts. Automaton has 87 states. Word has length 2161 [2019-12-07 17:24:17,095 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:24:17,104 INFO L225 Difference]: With dead ends: 3347 [2019-12-07 17:24:17,104 INFO L226 Difference]: Without dead ends: 3341 [2019-12-07 17:24:17,106 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2322 GetRequests, 2184 SyntacticMatches, 0 SemanticMatches, 138 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4882 ImplicationChecksByTransitivity, 4.2s TimeCoverageRelationStatistics Valid=4295, Invalid=15165, Unknown=0, NotChecked=0, Total=19460 [2019-12-07 17:24:17,110 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3341 states. [2019-12-07 17:24:17,143 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3341 to 2937. [2019-12-07 17:24:17,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2937 states. [2019-12-07 17:24:17,146 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2937 states to 2937 states and 3087 transitions. [2019-12-07 17:24:17,146 INFO L78 Accepts]: Start accepts. Automaton has 2937 states and 3087 transitions. Word has length 2161 [2019-12-07 17:24:17,147 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:24:17,147 INFO L462 AbstractCegarLoop]: Abstraction has 2937 states and 3087 transitions. [2019-12-07 17:24:17,147 INFO L463 AbstractCegarLoop]: Interpolant automaton has 87 states. [2019-12-07 17:24:17,147 INFO L276 IsEmpty]: Start isEmpty. Operand 2937 states and 3087 transitions. [2019-12-07 17:24:17,172 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2172 [2019-12-07 17:24:17,173 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:24:17,173 INFO L410 BasicCegarLoop]: trace histogram [378, 377, 377, 377, 377, 26, 26, 26, 25, 25, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:24:17,374 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 55 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:24:17,374 INFO L410 AbstractCegarLoop]: === Iteration 62 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:24:17,375 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:24:17,376 INFO L82 PathProgramCache]: Analyzing trace with hash 1011103077, now seen corresponding path program 46 times [2019-12-07 17:24:17,376 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:24:17,376 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1066177473] [2019-12-07 17:24:17,377 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:24:17,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:18,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:18,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:18,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:18,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:18,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:18,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:18,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:18,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:18,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:18,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:18,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:18,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:18,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:18,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:18,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:18,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:18,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:18,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:18,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:18,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:18,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:18,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:18,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:18,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:18,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:18,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:21,004 INFO L134 CoverageAnalysis]: Checked inductivity of 367959 backedges. 50431 proven. 1903 refuted. 0 times theorem prover too weak. 315625 trivial. 0 not checked. [2019-12-07 17:24:21,004 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1066177473] [2019-12-07 17:24:21,004 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [877363556] [2019-12-07 17:24:21,004 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:24:21,382 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 17:24:21,383 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:24:21,394 INFO L264 TraceCheckSpWp]: Trace formula consists of 4565 conjuncts, 62 conjunts are in the unsatisfiable core [2019-12-07 17:24:21,406 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:24:24,940 INFO L134 CoverageAnalysis]: Checked inductivity of 367959 backedges. 50234 proven. 6079 refuted. 0 times theorem prover too weak. 311646 trivial. 0 not checked. [2019-12-07 17:24:24,940 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:24:24,941 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 61] total 92 [2019-12-07 17:24:24,941 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [595299242] [2019-12-07 17:24:24,942 INFO L442 AbstractCegarLoop]: Interpolant automaton has 92 states [2019-12-07 17:24:24,942 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:24:24,942 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 92 interpolants. [2019-12-07 17:24:24,942 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1726, Invalid=6646, Unknown=0, NotChecked=0, Total=8372 [2019-12-07 17:24:24,943 INFO L87 Difference]: Start difference. First operand 2937 states and 3087 transitions. Second operand 92 states. [2019-12-07 17:24:31,104 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:24:31,104 INFO L93 Difference]: Finished difference Result 3480 states and 3749 transitions. [2019-12-07 17:24:31,104 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 90 states. [2019-12-07 17:24:31,104 INFO L78 Accepts]: Start accepts. Automaton has 92 states. Word has length 2171 [2019-12-07 17:24:31,105 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:24:31,109 INFO L225 Difference]: With dead ends: 3480 [2019-12-07 17:24:31,109 INFO L226 Difference]: Without dead ends: 3480 [2019-12-07 17:24:31,110 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2341 GetRequests, 2190 SyntacticMatches, 0 SemanticMatches, 151 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4632 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=5017, Invalid=18239, Unknown=0, NotChecked=0, Total=23256 [2019-12-07 17:24:31,111 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3480 states. [2019-12-07 17:24:31,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3480 to 3098. [2019-12-07 17:24:31,130 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3098 states. [2019-12-07 17:24:31,132 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3098 states to 3098 states and 3250 transitions. [2019-12-07 17:24:31,132 INFO L78 Accepts]: Start accepts. Automaton has 3098 states and 3250 transitions. Word has length 2171 [2019-12-07 17:24:31,133 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:24:31,133 INFO L462 AbstractCegarLoop]: Abstraction has 3098 states and 3250 transitions. [2019-12-07 17:24:31,133 INFO L463 AbstractCegarLoop]: Interpolant automaton has 92 states. [2019-12-07 17:24:31,133 INFO L276 IsEmpty]: Start isEmpty. Operand 3098 states and 3250 transitions. [2019-12-07 17:24:31,162 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2313 [2019-12-07 17:24:31,162 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:24:31,163 INFO L410 BasicCegarLoop]: trace histogram [404, 403, 403, 403, 403, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:24:31,363 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 56 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:24:31,364 INFO L410 AbstractCegarLoop]: === Iteration 63 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:24:31,364 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:24:31,365 INFO L82 PathProgramCache]: Analyzing trace with hash 1323482343, now seen corresponding path program 47 times [2019-12-07 17:24:31,365 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:24:31,365 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [943909971] [2019-12-07 17:24:31,366 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:24:31,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:32,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:32,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:32,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:32,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:32,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:32,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:32,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:32,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:32,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:32,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:32,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:32,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:32,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:32,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:32,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:32,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:32,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:32,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:32,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:32,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:32,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:32,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:32,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:32,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:32,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:32,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:32,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:24:35,458 INFO L134 CoverageAnalysis]: Checked inductivity of 419978 backedges. 100577 proven. 5921 refuted. 0 times theorem prover too weak. 313480 trivial. 0 not checked. [2019-12-07 17:24:35,458 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [943909971] [2019-12-07 17:24:35,458 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [959432932] [2019-12-07 17:24:35,458 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:27:09,568 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 59 check-sat command(s) [2019-12-07 17:27:09,569 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:27:09,652 INFO L264 TraceCheckSpWp]: Trace formula consists of 5696 conjuncts, 60 conjunts are in the unsatisfiable core [2019-12-07 17:27:09,667 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:27:13,459 INFO L134 CoverageAnalysis]: Checked inductivity of 419978 backedges. 100443 proven. 9558 refuted. 0 times theorem prover too weak. 309977 trivial. 0 not checked. [2019-12-07 17:27:13,459 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:27:13,460 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [61, 60] total 94 [2019-12-07 17:27:13,460 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2084255794] [2019-12-07 17:27:13,461 INFO L442 AbstractCegarLoop]: Interpolant automaton has 94 states [2019-12-07 17:27:13,461 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:13,461 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 94 interpolants. [2019-12-07 17:27:13,462 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1636, Invalid=7106, Unknown=0, NotChecked=0, Total=8742 [2019-12-07 17:27:13,462 INFO L87 Difference]: Start difference. First operand 3098 states and 3250 transitions. Second operand 94 states. [2019-12-07 17:27:18,769 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:18,769 INFO L93 Difference]: Finished difference Result 3504 states and 3776 transitions. [2019-12-07 17:27:18,770 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 88 states. [2019-12-07 17:27:18,770 INFO L78 Accepts]: Start accepts. Automaton has 94 states. Word has length 2312 [2019-12-07 17:27:18,771 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:18,775 INFO L225 Difference]: With dead ends: 3504 [2019-12-07 17:27:18,775 INFO L226 Difference]: Without dead ends: 3498 [2019-12-07 17:27:18,776 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2483 GetRequests, 2332 SyntacticMatches, 0 SemanticMatches, 151 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5832 ImplicationChecksByTransitivity, 4.2s TimeCoverageRelationStatistics Valid=4967, Invalid=18289, Unknown=0, NotChecked=0, Total=23256 [2019-12-07 17:27:18,778 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3498 states. [2019-12-07 17:27:18,799 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3498 to 3119. [2019-12-07 17:27:18,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3119 states. [2019-12-07 17:27:18,802 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3119 states to 3119 states and 3272 transitions. [2019-12-07 17:27:18,802 INFO L78 Accepts]: Start accepts. Automaton has 3119 states and 3272 transitions. Word has length 2312 [2019-12-07 17:27:18,803 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:18,803 INFO L462 AbstractCegarLoop]: Abstraction has 3119 states and 3272 transitions. [2019-12-07 17:27:18,803 INFO L463 AbstractCegarLoop]: Interpolant automaton has 94 states. [2019-12-07 17:27:18,803 INFO L276 IsEmpty]: Start isEmpty. Operand 3119 states and 3272 transitions. [2019-12-07 17:27:18,832 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2318 [2019-12-07 17:27:18,833 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:18,833 INFO L410 BasicCegarLoop]: trace histogram [405, 404, 404, 404, 404, 27, 27, 27, 26, 26, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:19,034 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 57 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:27:19,034 INFO L410 AbstractCegarLoop]: === Iteration 64 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:27:19,035 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:19,035 INFO L82 PathProgramCache]: Analyzing trace with hash 1696940994, now seen corresponding path program 48 times [2019-12-07 17:27:19,036 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:19,036 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [961410069] [2019-12-07 17:27:19,037 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:19,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:20,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:20,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:20,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:20,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:20,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:20,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:20,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:20,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:20,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:20,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:20,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:20,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:20,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:20,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:20,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:20,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:20,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:20,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:20,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:20,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:20,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:20,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:20,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:20,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:20,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:20,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:20,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:23,187 INFO L134 CoverageAnalysis]: Checked inductivity of 422021 backedges. 54185 proven. 2029 refuted. 0 times theorem prover too weak. 365807 trivial. 0 not checked. [2019-12-07 17:27:23,187 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [961410069] [2019-12-07 17:27:23,187 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [455639077] [2019-12-07 17:27:23,187 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:27:35,897 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 49 check-sat command(s) [2019-12-07 17:27:35,898 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:27:35,922 INFO L264 TraceCheckSpWp]: Trace formula consists of 4245 conjuncts, 33 conjunts are in the unsatisfiable core [2019-12-07 17:27:35,936 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:27:38,303 INFO L134 CoverageAnalysis]: Checked inductivity of 422021 backedges. 52508 proven. 2029 refuted. 0 times theorem prover too weak. 367484 trivial. 0 not checked. [2019-12-07 17:27:38,303 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:27:38,304 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 33] total 62 [2019-12-07 17:27:38,304 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [745076632] [2019-12-07 17:27:38,305 INFO L442 AbstractCegarLoop]: Interpolant automaton has 63 states [2019-12-07 17:27:38,305 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:38,305 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2019-12-07 17:27:38,305 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=908, Invalid=2998, Unknown=0, NotChecked=0, Total=3906 [2019-12-07 17:27:38,305 INFO L87 Difference]: Start difference. First operand 3119 states and 3272 transitions. Second operand 63 states. [2019-12-07 17:27:43,487 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:43,487 INFO L93 Difference]: Finished difference Result 3645 states and 3918 transitions. [2019-12-07 17:27:43,488 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 86 states. [2019-12-07 17:27:43,488 INFO L78 Accepts]: Start accepts. Automaton has 63 states. Word has length 2317 [2019-12-07 17:27:43,489 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:43,493 INFO L225 Difference]: With dead ends: 3645 [2019-12-07 17:27:43,493 INFO L226 Difference]: Without dead ends: 3645 [2019-12-07 17:27:43,494 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2486 GetRequests, 2369 SyntacticMatches, 0 SemanticMatches, 117 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2133 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=3215, Invalid=10827, Unknown=0, NotChecked=0, Total=14042 [2019-12-07 17:27:43,495 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3645 states. [2019-12-07 17:27:43,517 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3645 to 3265. [2019-12-07 17:27:43,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3265 states. [2019-12-07 17:27:43,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3265 states to 3265 states and 3419 transitions. [2019-12-07 17:27:43,520 INFO L78 Accepts]: Start accepts. Automaton has 3265 states and 3419 transitions. Word has length 2317 [2019-12-07 17:27:43,521 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:43,521 INFO L462 AbstractCegarLoop]: Abstraction has 3265 states and 3419 transitions. [2019-12-07 17:27:43,521 INFO L463 AbstractCegarLoop]: Interpolant automaton has 63 states. [2019-12-07 17:27:43,521 INFO L276 IsEmpty]: Start isEmpty. Operand 3265 states and 3419 transitions. [2019-12-07 17:27:43,553 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2464 [2019-12-07 17:27:43,554 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:43,554 INFO L410 BasicCegarLoop]: trace histogram [432, 431, 431, 431, 431, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:43,755 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 58 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:27:43,755 INFO L410 AbstractCegarLoop]: === Iteration 65 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:27:43,756 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:43,757 INFO L82 PathProgramCache]: Analyzing trace with hash 177571039, now seen corresponding path program 49 times [2019-12-07 17:27:43,758 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:43,758 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [934401598] [2019-12-07 17:27:43,759 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:44,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:44,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:44,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:44,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:44,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:44,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:44,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:44,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:44,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:44,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:44,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:44,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:44,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:44,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:44,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:44,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:44,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:44,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:44,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:44,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:44,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:44,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:44,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:44,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:44,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:44,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:44,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:44,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:44,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:48,330 INFO L134 CoverageAnalysis]: Checked inductivity of 479793 backedges. 110067 proven. 6366 refuted. 0 times theorem prover too weak. 363360 trivial. 0 not checked. [2019-12-07 17:27:48,331 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [934401598] [2019-12-07 17:27:48,331 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2054461274] [2019-12-07 17:27:48,331 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:27:48,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:48,819 INFO L264 TraceCheckSpWp]: Trace formula consists of 6126 conjuncts, 58 conjunts are in the unsatisfiable core [2019-12-07 17:27:48,833 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:27:52,751 INFO L134 CoverageAnalysis]: Checked inductivity of 479793 backedges. 110369 proven. 1782 refuted. 0 times theorem prover too weak. 367642 trivial. 0 not checked. [2019-12-07 17:27:52,751 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:27:52,752 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [63, 58] total 91 [2019-12-07 17:27:52,752 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1832018803] [2019-12-07 17:27:52,753 INFO L442 AbstractCegarLoop]: Interpolant automaton has 91 states [2019-12-07 17:27:52,753 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:52,753 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 91 interpolants. [2019-12-07 17:27:52,754 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1694, Invalid=6496, Unknown=0, NotChecked=0, Total=8190 [2019-12-07 17:27:52,754 INFO L87 Difference]: Start difference. First operand 3265 states and 3419 transitions. Second operand 91 states. [2019-12-07 17:27:56,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:56,850 INFO L93 Difference]: Finished difference Result 3660 states and 3933 transitions. [2019-12-07 17:27:56,850 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 86 states. [2019-12-07 17:27:56,851 INFO L78 Accepts]: Start accepts. Automaton has 91 states. Word has length 2463 [2019-12-07 17:27:56,852 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:56,860 INFO L225 Difference]: With dead ends: 3660 [2019-12-07 17:27:56,860 INFO L226 Difference]: Without dead ends: 3654 [2019-12-07 17:27:56,861 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2635 GetRequests, 2490 SyntacticMatches, 0 SemanticMatches, 145 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5373 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=4757, Invalid=16705, Unknown=0, NotChecked=0, Total=21462 [2019-12-07 17:27:56,864 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3654 states. [2019-12-07 17:27:56,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3654 to 3275. [2019-12-07 17:27:56,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3275 states. [2019-12-07 17:27:56,896 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3275 states to 3275 states and 3429 transitions. [2019-12-07 17:27:56,896 INFO L78 Accepts]: Start accepts. Automaton has 3275 states and 3429 transitions. Word has length 2463 [2019-12-07 17:27:56,897 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:56,897 INFO L462 AbstractCegarLoop]: Abstraction has 3275 states and 3429 transitions. [2019-12-07 17:27:56,897 INFO L463 AbstractCegarLoop]: Interpolant automaton has 91 states. [2019-12-07 17:27:56,897 INFO L276 IsEmpty]: Start isEmpty. Operand 3275 states and 3429 transitions. [2019-12-07 17:27:56,930 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2474 [2019-12-07 17:27:56,930 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:56,931 INFO L410 BasicCegarLoop]: trace histogram [434, 433, 433, 433, 433, 28, 28, 28, 27, 27, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:57,131 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 59 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:27:57,132 INFO L410 AbstractCegarLoop]: === Iteration 66 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:27:57,132 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:57,132 INFO L82 PathProgramCache]: Analyzing trace with hash -169898907, now seen corresponding path program 50 times [2019-12-07 17:27:57,132 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:57,132 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [704832363] [2019-12-07 17:27:57,132 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:57,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:58,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:58,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:58,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:58,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:58,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:58,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:58,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:58,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:58,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:58,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:58,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:58,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:58,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:58,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:58,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:58,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:58,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:58,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:58,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:58,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:58,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:58,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:58,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:58,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:58,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:58,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:58,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:58,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:01,727 INFO L134 CoverageAnalysis]: Checked inductivity of 484166 backedges. 60238 proven. 2188 refuted. 0 times theorem prover too weak. 421740 trivial. 0 not checked. [2019-12-07 17:28:01,727 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [704832363] [2019-12-07 17:28:01,727 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1484487465] [2019-12-07 17:28:01,727 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:28:02,210 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 17:28:02,210 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:28:02,224 INFO L264 TraceCheckSpWp]: Trace formula consists of 6150 conjuncts, 59 conjunts are in the unsatisfiable core [2019-12-07 17:28:02,237 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:28:05,547 INFO L134 CoverageAnalysis]: Checked inductivity of 484166 backedges. 58293 proven. 1946 refuted. 0 times theorem prover too weak. 423927 trivial. 0 not checked. [2019-12-07 17:28:05,547 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:28:05,549 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 30] total 90 [2019-12-07 17:28:05,549 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1661911183] [2019-12-07 17:28:05,549 INFO L442 AbstractCegarLoop]: Interpolant automaton has 91 states [2019-12-07 17:28:05,549 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:28:05,550 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 91 interpolants. [2019-12-07 17:28:05,550 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=992, Invalid=7198, Unknown=0, NotChecked=0, Total=8190 [2019-12-07 17:28:05,550 INFO L87 Difference]: Start difference. First operand 3275 states and 3429 transitions. Second operand 91 states. [2019-12-07 17:28:17,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:28:17,126 INFO L93 Difference]: Finished difference Result 3829 states and 4106 transitions. [2019-12-07 17:28:17,126 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 92 states. [2019-12-07 17:28:17,126 INFO L78 Accepts]: Start accepts. Automaton has 91 states. Word has length 2473 [2019-12-07 17:28:17,127 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:28:17,131 INFO L225 Difference]: With dead ends: 3829 [2019-12-07 17:28:17,131 INFO L226 Difference]: Without dead ends: 3829 [2019-12-07 17:28:17,132 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2650 GetRequests, 2499 SyntacticMatches, 1 SemanticMatches, 150 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5620 ImplicationChecksByTransitivity, 3.8s TimeCoverageRelationStatistics Valid=1851, Invalid=21101, Unknown=0, NotChecked=0, Total=22952 [2019-12-07 17:28:17,133 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3829 states. [2019-12-07 17:28:17,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3829 to 3431. [2019-12-07 17:28:17,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3431 states. [2019-12-07 17:28:17,156 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3431 states to 3431 states and 3587 transitions. [2019-12-07 17:28:17,156 INFO L78 Accepts]: Start accepts. Automaton has 3431 states and 3587 transitions. Word has length 2473 [2019-12-07 17:28:17,157 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:28:17,157 INFO L462 AbstractCegarLoop]: Abstraction has 3431 states and 3587 transitions. [2019-12-07 17:28:17,157 INFO L463 AbstractCegarLoop]: Interpolant automaton has 91 states. [2019-12-07 17:28:17,157 INFO L276 IsEmpty]: Start isEmpty. Operand 3431 states and 3587 transitions. [2019-12-07 17:28:17,194 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2630 [2019-12-07 17:28:17,194 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:28:17,195 INFO L410 BasicCegarLoop]: trace histogram [463, 462, 462, 462, 462, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:28:17,395 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 60 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:28:17,396 INFO L410 AbstractCegarLoop]: === Iteration 67 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:28:17,396 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:28:17,397 INFO L82 PathProgramCache]: Analyzing trace with hash 1430424994, now seen corresponding path program 51 times [2019-12-07 17:28:17,397 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:28:17,398 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [256393855] [2019-12-07 17:28:17,398 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:28:17,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:18,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:18,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:18,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:18,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:18,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:18,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:18,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:18,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:18,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:18,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:18,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:18,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:18,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:18,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:18,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:18,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:18,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:18,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:18,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:18,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:18,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:18,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:18,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:18,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:18,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:18,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:18,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:18,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:18,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:22,478 INFO L134 CoverageAnalysis]: Checked inductivity of 550585 backedges. 124499 proven. 6827 refuted. 0 times theorem prover too weak. 419259 trivial. 0 not checked. [2019-12-07 17:28:22,478 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [256393855] [2019-12-07 17:28:22,478 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1038851310] [2019-12-07 17:28:22,478 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:28:25,588 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) [2019-12-07 17:28:25,588 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:28:25,598 INFO L264 TraceCheckSpWp]: Trace formula consists of 2985 conjuncts, 39 conjunts are in the unsatisfiable core [2019-12-07 17:28:25,613 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:28:30,224 INFO L134 CoverageAnalysis]: Checked inductivity of 550585 backedges. 118619 proven. 6093 refuted. 0 times theorem prover too weak. 425873 trivial. 0 not checked. [2019-12-07 17:28:30,225 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:28:30,226 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [65, 38] total 101 [2019-12-07 17:28:30,226 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1515778578] [2019-12-07 17:28:30,227 INFO L442 AbstractCegarLoop]: Interpolant automaton has 101 states [2019-12-07 17:28:30,227 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:28:30,227 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 101 interpolants. [2019-12-07 17:28:30,227 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1831, Invalid=8269, Unknown=0, NotChecked=0, Total=10100 [2019-12-07 17:28:30,228 INFO L87 Difference]: Start difference. First operand 3431 states and 3587 transitions. Second operand 101 states. [2019-12-07 17:28:37,597 WARN L192 SmtUtils]: Spent 107.00 ms on a formula simplification. DAG size of input: 23 DAG size of output: 21 [2019-12-07 17:28:42,117 WARN L192 SmtUtils]: Spent 113.00 ms on a formula simplification. DAG size of input: 24 DAG size of output: 21 [2019-12-07 17:28:45,085 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:28:45,086 INFO L93 Difference]: Finished difference Result 3989 states and 4266 transitions. [2019-12-07 17:28:45,087 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 150 states. [2019-12-07 17:28:45,087 INFO L78 Accepts]: Start accepts. Automaton has 101 states. Word has length 2629 [2019-12-07 17:28:45,088 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:28:45,093 INFO L225 Difference]: With dead ends: 3989 [2019-12-07 17:28:45,093 INFO L226 Difference]: Without dead ends: 3983 [2019-12-07 17:28:45,096 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2895 GetRequests, 2650 SyntacticMatches, 0 SemanticMatches, 245 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16465 ImplicationChecksByTransitivity, 14.0s TimeCoverageRelationStatistics Valid=10124, Invalid=50638, Unknown=0, NotChecked=0, Total=60762 [2019-12-07 17:28:45,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3983 states. [2019-12-07 17:28:45,123 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3983 to 3436. [2019-12-07 17:28:45,124 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3436 states. [2019-12-07 17:28:45,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3436 states to 3436 states and 3591 transitions. [2019-12-07 17:28:45,127 INFO L78 Accepts]: Start accepts. Automaton has 3436 states and 3591 transitions. Word has length 2629 [2019-12-07 17:28:45,127 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:28:45,127 INFO L462 AbstractCegarLoop]: Abstraction has 3436 states and 3591 transitions. [2019-12-07 17:28:45,127 INFO L463 AbstractCegarLoop]: Interpolant automaton has 101 states. [2019-12-07 17:28:45,127 INFO L276 IsEmpty]: Start isEmpty. Operand 3436 states and 3591 transitions. [2019-12-07 17:28:45,165 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2635 [2019-12-07 17:28:45,165 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:28:45,166 INFO L410 BasicCegarLoop]: trace histogram [464, 463, 463, 463, 463, 29, 29, 29, 28, 28, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:28:45,366 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 61 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:28:45,367 INFO L410 AbstractCegarLoop]: === Iteration 68 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:28:45,367 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:28:45,368 INFO L82 PathProgramCache]: Analyzing trace with hash 2134165351, now seen corresponding path program 52 times [2019-12-07 17:28:45,368 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:28:45,368 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1389607068] [2019-12-07 17:28:45,369 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:28:45,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:46,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:46,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:46,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:46,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:46,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:46,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:46,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:46,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:46,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:46,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:46,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:46,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:46,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:46,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:47,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:47,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:47,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:47,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:47,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:47,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:47,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:47,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:47,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:47,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:47,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:47,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:47,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:47,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:47,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:28:50,453 INFO L134 CoverageAnalysis]: Checked inductivity of 552925 backedges. 66725 proven. 2353 refuted. 0 times theorem prover too weak. 483847 trivial. 0 not checked. [2019-12-07 17:28:50,453 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1389607068] [2019-12-07 17:28:50,454 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1979549093] [2019-12-07 17:28:50,454 INFO L92 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:28:51,689 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-12-07 17:28:51,689 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:28:51,715 INFO L264 TraceCheckSpWp]: Trace formula consists of 6543 conjuncts, 61 conjunts are in the unsatisfiable core [2019-12-07 17:28:51,732 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:28:55,442 INFO L134 CoverageAnalysis]: Checked inductivity of 552925 backedges. 64638 proven. 2088 refuted. 0 times theorem prover too weak. 486199 trivial. 0 not checked. [2019-12-07 17:28:55,442 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:28:55,443 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 31] total 93 [2019-12-07 17:28:55,443 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1828083785] [2019-12-07 17:28:55,444 INFO L442 AbstractCegarLoop]: Interpolant automaton has 94 states [2019-12-07 17:28:55,444 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:28:55,444 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 94 interpolants. [2019-12-07 17:28:55,445 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1056, Invalid=7686, Unknown=0, NotChecked=0, Total=8742 [2019-12-07 17:28:55,445 INFO L87 Difference]: Start difference. First operand 3436 states and 3591 transitions. Second operand 94 states. [2019-12-07 17:29:06,485 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:29:06,485 INFO L93 Difference]: Finished difference Result 4011 states and 4291 transitions. [2019-12-07 17:29:06,485 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 95 states. [2019-12-07 17:29:06,485 INFO L78 Accepts]: Start accepts. Automaton has 94 states. Word has length 2634 [2019-12-07 17:29:06,486 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:29:06,490 INFO L225 Difference]: With dead ends: 4011 [2019-12-07 17:29:06,490 INFO L226 Difference]: Without dead ends: 4011 [2019-12-07 17:29:06,491 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2817 GetRequests, 2661 SyntacticMatches, 1 SemanticMatches, 155 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6009 ImplicationChecksByTransitivity, 4.0s TimeCoverageRelationStatistics Valid=1959, Invalid=22533, Unknown=0, NotChecked=0, Total=24492 [2019-12-07 17:29:06,493 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4011 states. [2019-12-07 17:29:06,513 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4011 to 3597. [2019-12-07 17:29:06,513 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3597 states. [2019-12-07 17:29:06,516 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3597 states to 3597 states and 3754 transitions. [2019-12-07 17:29:06,516 INFO L78 Accepts]: Start accepts. Automaton has 3597 states and 3754 transitions. Word has length 2634 [2019-12-07 17:29:06,517 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:29:06,517 INFO L462 AbstractCegarLoop]: Abstraction has 3597 states and 3754 transitions. [2019-12-07 17:29:06,517 INFO L463 AbstractCegarLoop]: Interpolant automaton has 94 states. [2019-12-07 17:29:06,517 INFO L276 IsEmpty]: Start isEmpty. Operand 3597 states and 3754 transitions. [2019-12-07 17:29:06,563 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2796 [2019-12-07 17:29:06,563 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:29:06,564 INFO L410 BasicCegarLoop]: trace histogram [494, 493, 493, 493, 493, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:06,764 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 62 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:29:06,765 INFO L410 AbstractCegarLoop]: === Iteration 69 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:29:06,765 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:06,766 INFO L82 PathProgramCache]: Analyzing trace with hash 945686987, now seen corresponding path program 53 times [2019-12-07 17:29:06,766 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:06,766 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [794748523] [2019-12-07 17:29:06,767 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:07,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:07,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:07,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:07,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:07,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:07,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:07,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:07,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:07,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:07,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:07,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:07,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:07,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:07,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:07,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:07,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:07,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:07,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:07,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:07,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:07,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:07,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:07,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:07,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:07,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:07,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:07,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:07,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:07,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:07,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:07,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:12,411 INFO L134 CoverageAnalysis]: Checked inductivity of 626255 backedges. 137762 proven. 7304 refuted. 0 times theorem prover too weak. 481189 trivial. 0 not checked. [2019-12-07 17:29:12,412 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [794748523] [2019-12-07 17:29:12,412 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1251945295] [2019-12-07 17:29:12,412 INFO L92 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:29:42,350 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 77 check-sat command(s) [2019-12-07 17:29:42,350 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:29:42,405 INFO L264 TraceCheckSpWp]: Trace formula consists of 6875 conjuncts, 66 conjunts are in the unsatisfiable core [2019-12-07 17:29:42,423 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:29:47,507 INFO L134 CoverageAnalysis]: Checked inductivity of 626255 backedges. 137762 proven. 7304 refuted. 0 times theorem prover too weak. 481189 trivial. 0 not checked. [2019-12-07 17:29:47,508 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:29:47,509 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [67, 66] total 100 [2019-12-07 17:29:47,509 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [666200902] [2019-12-07 17:29:47,509 INFO L442 AbstractCegarLoop]: Interpolant automaton has 100 states [2019-12-07 17:29:47,510 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:29:47,510 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 100 interpolants. [2019-12-07 17:29:47,510 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1979, Invalid=7921, Unknown=0, NotChecked=0, Total=9900 [2019-12-07 17:29:47,510 INFO L87 Difference]: Start difference. First operand 3597 states and 3754 transitions. Second operand 100 states. [2019-12-07 17:29:53,702 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:29:53,702 INFO L93 Difference]: Finished difference Result 4019 states and 4297 transitions. [2019-12-07 17:29:53,702 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 92 states. [2019-12-07 17:29:53,702 INFO L78 Accepts]: Start accepts. Automaton has 100 states. Word has length 2795 [2019-12-07 17:29:53,703 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:29:53,706 INFO L225 Difference]: With dead ends: 4019 [2019-12-07 17:29:53,706 INFO L226 Difference]: Without dead ends: 4013 [2019-12-07 17:29:53,707 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2979 GetRequests, 2821 SyntacticMatches, 0 SemanticMatches, 158 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6481 ImplicationChecksByTransitivity, 5.3s TimeCoverageRelationStatistics Valid=5647, Invalid=19793, Unknown=0, NotChecked=0, Total=25440 [2019-12-07 17:29:53,709 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4013 states. [2019-12-07 17:29:53,728 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4013 to 3602. [2019-12-07 17:29:53,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3602 states. [2019-12-07 17:29:53,732 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3602 states to 3602 states and 3758 transitions. [2019-12-07 17:29:53,732 INFO L78 Accepts]: Start accepts. Automaton has 3602 states and 3758 transitions. Word has length 2795 [2019-12-07 17:29:53,732 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:29:53,732 INFO L462 AbstractCegarLoop]: Abstraction has 3602 states and 3758 transitions. [2019-12-07 17:29:53,732 INFO L463 AbstractCegarLoop]: Interpolant automaton has 100 states. [2019-12-07 17:29:53,733 INFO L276 IsEmpty]: Start isEmpty. Operand 3602 states and 3758 transitions. [2019-12-07 17:29:53,773 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2801 [2019-12-07 17:29:53,773 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:29:53,774 INFO L410 BasicCegarLoop]: trace histogram [495, 494, 494, 494, 494, 30, 30, 30, 29, 29, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:29:53,974 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 63 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:29:53,975 INFO L410 AbstractCegarLoop]: === Iteration 70 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:29:53,975 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:29:53,976 INFO L82 PathProgramCache]: Analyzing trace with hash 601825130, now seen corresponding path program 54 times [2019-12-07 17:29:53,976 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:29:53,976 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1597201265] [2019-12-07 17:29:53,977 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:29:54,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:55,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:55,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:55,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:55,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:55,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:55,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:55,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:55,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:55,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:55,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:55,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:55,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:55,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:55,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:55,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:55,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:55,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:55,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:55,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:55,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:55,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:55,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:55,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:56,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:56,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:56,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:56,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:56,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:56,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:56,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:29:59,871 INFO L134 CoverageAnalysis]: Checked inductivity of 628751 backedges. 73661 proven. 2524 refuted. 0 times theorem prover too weak. 552566 trivial. 0 not checked. [2019-12-07 17:29:59,871 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1597201265] [2019-12-07 17:29:59,871 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2026140171] [2019-12-07 17:29:59,872 INFO L92 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:30:17,023 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 61 check-sat command(s) [2019-12-07 17:30:17,023 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:30:17,054 INFO L264 TraceCheckSpWp]: Trace formula consists of 4896 conjuncts, 34 conjunts are in the unsatisfiable core [2019-12-07 17:30:17,066 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:30:21,168 INFO L134 CoverageAnalysis]: Checked inductivity of 628751 backedges. 71427 proven. 2235 refuted. 0 times theorem prover too weak. 555089 trivial. 0 not checked. [2019-12-07 17:30:21,168 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:30:21,169 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 33] total 98 [2019-12-07 17:30:21,170 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1543346036] [2019-12-07 17:30:21,170 INFO L442 AbstractCegarLoop]: Interpolant automaton has 99 states [2019-12-07 17:30:21,170 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:30:21,170 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 99 interpolants. [2019-12-07 17:30:21,171 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1563, Invalid=8139, Unknown=0, NotChecked=0, Total=9702 [2019-12-07 17:30:21,171 INFO L87 Difference]: Start difference. First operand 3602 states and 3758 transitions. Second operand 99 states. [2019-12-07 17:30:32,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:30:32,503 INFO L93 Difference]: Finished difference Result 4206 states and 4490 transitions. [2019-12-07 17:30:32,504 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 98 states. [2019-12-07 17:30:32,504 INFO L78 Accepts]: Start accepts. Automaton has 99 states. Word has length 2800 [2019-12-07 17:30:32,507 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:30:32,515 INFO L225 Difference]: With dead ends: 4206 [2019-12-07 17:30:32,515 INFO L226 Difference]: Without dead ends: 4206 [2019-12-07 17:30:32,517 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2989 GetRequests, 2827 SyntacticMatches, 0 SemanticMatches, 162 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6563 ImplicationChecksByTransitivity, 9.1s TimeCoverageRelationStatistics Valid=4370, Invalid=22362, Unknown=0, NotChecked=0, Total=26732 [2019-12-07 17:30:32,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4206 states. [2019-12-07 17:30:32,544 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4206 to 3768. [2019-12-07 17:30:32,545 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3768 states. [2019-12-07 17:30:32,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3768 states to 3768 states and 3926 transitions. [2019-12-07 17:30:32,548 INFO L78 Accepts]: Start accepts. Automaton has 3768 states and 3926 transitions. Word has length 2800 [2019-12-07 17:30:32,549 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:30:32,549 INFO L462 AbstractCegarLoop]: Abstraction has 3768 states and 3926 transitions. [2019-12-07 17:30:32,549 INFO L463 AbstractCegarLoop]: Interpolant automaton has 99 states. [2019-12-07 17:30:32,549 INFO L276 IsEmpty]: Start isEmpty. Operand 3768 states and 3926 transitions. [2019-12-07 17:30:32,594 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2967 [2019-12-07 17:30:32,594 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:30:32,594 INFO L410 BasicCegarLoop]: trace histogram [526, 525, 525, 525, 525, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:30:32,795 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 64 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:30:32,795 INFO L410 AbstractCegarLoop]: === Iteration 71 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:30:32,796 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:30:32,796 INFO L82 PathProgramCache]: Analyzing trace with hash -643366969, now seen corresponding path program 55 times [2019-12-07 17:30:32,797 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:30:32,797 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [89696506] [2019-12-07 17:30:32,797 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:30:33,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:33,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:33,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:33,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:33,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:33,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:33,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:33,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:33,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:33,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:33,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:33,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:33,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:33,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:33,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:33,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:33,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:33,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:33,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:33,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:33,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:33,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:33,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:33,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:33,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:33,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:33,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:34,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:34,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:34,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:34,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:34,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:39,022 INFO L134 CoverageAnalysis]: Checked inductivity of 709455 backedges. 151933 proven. 7797 refuted. 0 times theorem prover too weak. 549725 trivial. 0 not checked. [2019-12-07 17:30:39,022 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [89696506] [2019-12-07 17:30:39,022 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1956110729] [2019-12-07 17:30:39,022 INFO L92 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:30:39,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:39,650 INFO L264 TraceCheckSpWp]: Trace formula consists of 7353 conjuncts, 64 conjunts are in the unsatisfiable core [2019-12-07 17:30:39,662 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:30:45,085 INFO L134 CoverageAnalysis]: Checked inductivity of 709455 backedges. 152268 proven. 2205 refuted. 0 times theorem prover too weak. 554982 trivial. 0 not checked. [2019-12-07 17:30:45,085 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:30:45,086 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [69, 64] total 100 [2019-12-07 17:30:45,086 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1006154033] [2019-12-07 17:30:45,087 INFO L442 AbstractCegarLoop]: Interpolant automaton has 100 states [2019-12-07 17:30:45,087 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:30:45,087 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 100 interpolants. [2019-12-07 17:30:45,087 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2060, Invalid=7840, Unknown=0, NotChecked=0, Total=9900 [2019-12-07 17:30:45,088 INFO L87 Difference]: Start difference. First operand 3768 states and 3926 transitions. Second operand 100 states. [2019-12-07 17:30:48,622 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:30:48,622 INFO L93 Difference]: Finished difference Result 4218 states and 4500 transitions. [2019-12-07 17:30:48,622 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 95 states. [2019-12-07 17:30:48,622 INFO L78 Accepts]: Start accepts. Automaton has 100 states. Word has length 2966 [2019-12-07 17:30:48,623 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:30:48,627 INFO L225 Difference]: With dead ends: 4218 [2019-12-07 17:30:48,627 INFO L226 Difference]: Without dead ends: 4212 [2019-12-07 17:30:48,628 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3156 GetRequests, 2996 SyntacticMatches, 0 SemanticMatches, 160 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6600 ImplicationChecksByTransitivity, 4.3s TimeCoverageRelationStatistics Valid=5777, Invalid=20305, Unknown=0, NotChecked=0, Total=26082 [2019-12-07 17:30:48,630 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4212 states. [2019-12-07 17:30:48,650 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4212 to 3773. [2019-12-07 17:30:48,651 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3773 states. [2019-12-07 17:30:48,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3773 states to 3773 states and 3930 transitions. [2019-12-07 17:30:48,654 INFO L78 Accepts]: Start accepts. Automaton has 3773 states and 3930 transitions. Word has length 2966 [2019-12-07 17:30:48,655 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:30:48,655 INFO L462 AbstractCegarLoop]: Abstraction has 3773 states and 3930 transitions. [2019-12-07 17:30:48,655 INFO L463 AbstractCegarLoop]: Interpolant automaton has 100 states. [2019-12-07 17:30:48,655 INFO L276 IsEmpty]: Start isEmpty. Operand 3773 states and 3930 transitions. [2019-12-07 17:30:48,700 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2972 [2019-12-07 17:30:48,700 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:30:48,700 INFO L410 BasicCegarLoop]: trace histogram [527, 526, 526, 526, 526, 31, 31, 31, 30, 30, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:30:48,901 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 65 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:30:48,901 INFO L410 AbstractCegarLoop]: === Iteration 72 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:30:48,902 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:30:48,903 INFO L82 PathProgramCache]: Analyzing trace with hash 428252130, now seen corresponding path program 56 times [2019-12-07 17:30:48,903 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:30:48,903 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1708806073] [2019-12-07 17:30:48,904 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:30:49,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:50,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:50,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:50,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:50,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:50,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:50,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:50,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:50,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:50,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:50,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:50,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:50,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:50,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:50,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:50,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:50,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:50,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:50,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:50,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:50,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:50,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:50,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:50,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:50,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:50,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:51,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:51,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:51,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:51,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:51,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:51,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:30:55,222 INFO L134 CoverageAnalysis]: Checked inductivity of 712112 backedges. 81061 proven. 2701 refuted. 0 times theorem prover too weak. 628350 trivial. 0 not checked. [2019-12-07 17:30:55,223 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1708806073] [2019-12-07 17:30:55,223 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [960182107] [2019-12-07 17:30:55,223 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:30:55,811 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2019-12-07 17:30:55,812 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:30:55,829 INFO L264 TraceCheckSpWp]: Trace formula consists of 7365 conjuncts, 65 conjunts are in the unsatisfiable core [2019-12-07 17:30:55,840 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:31:00,418 INFO L134 CoverageAnalysis]: Checked inductivity of 712112 backedges. 78675 proven. 2387 refuted. 0 times theorem prover too weak. 631050 trivial. 0 not checked. [2019-12-07 17:31:00,418 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:31:00,419 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 33] total 99 [2019-12-07 17:31:00,420 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [825201183] [2019-12-07 17:31:00,420 INFO L442 AbstractCegarLoop]: Interpolant automaton has 100 states [2019-12-07 17:31:00,420 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:31:00,420 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 100 interpolants. [2019-12-07 17:31:00,421 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=1190, Invalid=8710, Unknown=0, NotChecked=0, Total=9900 [2019-12-07 17:31:00,421 INFO L87 Difference]: Start difference. First operand 3773 states and 3930 transitions. Second operand 100 states. [2019-12-07 17:31:12,704 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:31:12,704 INFO L93 Difference]: Finished difference Result 4414 states and 4703 transitions. [2019-12-07 17:31:12,705 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 101 states. [2019-12-07 17:31:12,705 INFO L78 Accepts]: Start accepts. Automaton has 100 states. Word has length 2971 [2019-12-07 17:31:12,706 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:31:12,710 INFO L225 Difference]: With dead ends: 4414 [2019-12-07 17:31:12,710 INFO L226 Difference]: Without dead ends: 4414 [2019-12-07 17:31:12,711 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3166 GetRequests, 3000 SyntacticMatches, 1 SemanticMatches, 165 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6826 ImplicationChecksByTransitivity, 4.8s TimeCoverageRelationStatistics Valid=2184, Invalid=25538, Unknown=0, NotChecked=0, Total=27722 [2019-12-07 17:31:12,713 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4414 states. [2019-12-07 17:31:12,736 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4414 to 3944. [2019-12-07 17:31:12,736 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3944 states. [2019-12-07 17:31:12,739 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3944 states to 3944 states and 4103 transitions. [2019-12-07 17:31:12,739 INFO L78 Accepts]: Start accepts. Automaton has 3944 states and 4103 transitions. Word has length 2971 [2019-12-07 17:31:12,740 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:31:12,740 INFO L462 AbstractCegarLoop]: Abstraction has 3944 states and 4103 transitions. [2019-12-07 17:31:12,740 INFO L463 AbstractCegarLoop]: Interpolant automaton has 100 states. [2019-12-07 17:31:12,740 INFO L276 IsEmpty]: Start isEmpty. Operand 3944 states and 4103 transitions. [2019-12-07 17:31:12,790 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3143 [2019-12-07 17:31:12,790 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:31:12,791 INFO L410 BasicCegarLoop]: trace histogram [559, 558, 558, 558, 558, 32, 32, 32, 31, 31, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:31:12,991 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 66 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:31:12,991 INFO L410 AbstractCegarLoop]: === Iteration 73 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:31:12,992 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:31:12,992 INFO L82 PathProgramCache]: Analyzing trace with hash -1867759088, now seen corresponding path program 57 times [2019-12-07 17:31:12,993 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:31:12,993 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [307839051] [2019-12-07 17:31:12,993 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:31:13,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:14,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:31:19,833 INFO L134 CoverageAnalysis]: Checked inductivity of 800668 backedges. 167042 proven. 8306 refuted. 0 times theorem prover too weak. 625320 trivial. 0 not checked. [2019-12-07 17:31:19,833 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [307839051] [2019-12-07 17:31:19,833 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [229126553] [2019-12-07 17:31:19,833 INFO L92 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/z3 Starting monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:31:22,678 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 33 check-sat command(s) [2019-12-07 17:31:22,678 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-12-07 17:31:22,692 INFO L264 TraceCheckSpWp]: Trace formula consists of 3489 conjuncts, 42 conjunts are in the unsatisfiable core [2019-12-07 17:31:22,703 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 17:31:28,858 INFO L134 CoverageAnalysis]: Checked inductivity of 800668 backedges. 159788 proven. 7443 refuted. 0 times theorem prover too weak. 633437 trivial. 0 not checked. [2019-12-07 17:31:28,858 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 17:31:28,860 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [71, 41] total 110 [2019-12-07 17:31:28,860 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [297921842] [2019-12-07 17:31:28,860 INFO L442 AbstractCegarLoop]: Interpolant automaton has 110 states [2019-12-07 17:31:28,861 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:31:28,861 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 110 interpolants. [2019-12-07 17:31:28,861 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=2209, Invalid=9781, Unknown=0, NotChecked=0, Total=11990 [2019-12-07 17:31:28,861 INFO L87 Difference]: Start difference. First operand 3944 states and 4103 transitions. Second operand 110 states. [2019-12-07 17:31:45,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:31:45,880 INFO L93 Difference]: Finished difference Result 5111 states and 5415 transitions. [2019-12-07 17:31:45,880 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 168 states. [2019-12-07 17:31:45,880 INFO L78 Accepts]: Start accepts. Automaton has 110 states. Word has length 3142 [2019-12-07 17:31:45,882 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:31:45,886 INFO L225 Difference]: With dead ends: 5111 [2019-12-07 17:31:45,886 INFO L226 Difference]: Without dead ends: 5105 [2019-12-07 17:31:45,889 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3435 GetRequests, 3166 SyntacticMatches, 0 SemanticMatches, 269 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19945 ImplicationChecksByTransitivity, 14.1s TimeCoverageRelationStatistics Valid=12173, Invalid=60997, Unknown=0, NotChecked=0, Total=73170 [2019-12-07 17:31:45,892 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5105 states. [2019-12-07 17:31:45,916 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5105 to 3949. [2019-12-07 17:31:45,916 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3949 states. [2019-12-07 17:31:45,919 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3949 states to 3949 states and 4107 transitions. [2019-12-07 17:31:45,919 INFO L78 Accepts]: Start accepts. Automaton has 3949 states and 4107 transitions. Word has length 3142 [2019-12-07 17:31:45,920 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:31:45,920 INFO L462 AbstractCegarLoop]: Abstraction has 3949 states and 4107 transitions. [2019-12-07 17:31:45,920 INFO L463 AbstractCegarLoop]: Interpolant automaton has 110 states. [2019-12-07 17:31:45,921 INFO L276 IsEmpty]: Start isEmpty. Operand 3949 states and 4107 transitions. [2019-12-07 17:31:45,971 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3148 [2019-12-07 17:31:45,971 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:31:45,972 INFO L410 BasicCegarLoop]: trace histogram [560, 559, 559, 559, 559, 32, 32, 32, 31, 31, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:31:46,172 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 67 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 17:31:46,172 INFO L410 AbstractCegarLoop]: === Iteration 74 === [fooErr1REQUIRES_VIOLATION, fooErr0ASSERT_VIOLATIONARRAY_INDEX, fooErr2REQUIRES_VIOLATION, mainErr2REQUIRES_VIOLATION, mainErr3REQUIRES_VIOLATION, mainErr4ENSURES_VIOLATIONMEMORY_LEAK, mainErr0REQUIRES_VIOLATION, mainErr1REQUIRES_VIOLATION]=== [2019-12-07 17:31:46,174 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:31:46,175 INFO L82 PathProgramCache]: Analyzing trace with hash -486718779, now seen corresponding path program 58 times [2019-12-07 17:31:46,175 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:31:46,175 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [382215121] [2019-12-07 17:31:46,175 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:31:48,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:31:50,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:31:50,680 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 17:31:50,680 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 17:31:51,014 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 05:31:51 BoogieIcfgContainer [2019-12-07 17:31:51,014 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 17:31:51,014 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 17:31:51,014 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 17:31:51,014 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 17:31:51,015 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:19:32" (3/4) ... [2019-12-07 17:31:51,016 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 17:31:51,266 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_afd20105-c5f5-4cde-99a9-e7844d683eb5/bin/uautomizer/witness.graphml [2019-12-07 17:31:51,266 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 17:31:51,267 INFO L168 Benchmark]: Toolchain (without parser) took 739483.48 ms. Allocated memory was 1.0 GB in the beginning and 4.6 GB in the end (delta: 3.6 GB). Free memory was 947.9 MB in the beginning and 2.1 GB in the end (delta: -1.1 GB). Peak memory consumption was 2.5 GB. Max. memory is 11.5 GB. [2019-12-07 17:31:51,267 INFO L168 Benchmark]: CDTParser took 0.18 ms. Allocated memory is still 1.0 GB. Free memory is still 964.0 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 17:31:51,267 INFO L168 Benchmark]: CACSL2BoogieTranslator took 189.36 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 99.6 MB). Free memory was 947.9 MB in the beginning and 1.1 GB in the end (delta: -145.4 MB). Peak memory consumption was 23.4 MB. Max. memory is 11.5 GB. [2019-12-07 17:31:51,267 INFO L168 Benchmark]: Boogie Preprocessor took 23.87 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 17:31:51,268 INFO L168 Benchmark]: RCFGBuilder took 200.40 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 21.9 MB). Peak memory consumption was 21.9 MB. Max. memory is 11.5 GB. [2019-12-07 17:31:51,268 INFO L168 Benchmark]: TraceAbstraction took 738815.11 ms. Allocated memory was 1.1 GB in the beginning and 4.6 GB in the end (delta: 3.5 GB). Free memory was 1.1 GB in the beginning and 2.2 GB in the end (delta: -1.2 GB). Peak memory consumption was 2.3 GB. Max. memory is 11.5 GB. [2019-12-07 17:31:51,268 INFO L168 Benchmark]: Witness Printer took 251.87 ms. Allocated memory is still 4.6 GB. Free memory was 2.2 GB in the beginning and 2.1 GB in the end (delta: 174.3 MB). Peak memory consumption was 174.3 MB. Max. memory is 11.5 GB. [2019-12-07 17:31:51,269 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18 ms. Allocated memory is still 1.0 GB. Free memory is still 964.0 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 189.36 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 99.6 MB). Free memory was 947.9 MB in the beginning and 1.1 GB in the end (delta: -145.4 MB). Peak memory consumption was 23.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 23.87 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 200.40 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 21.9 MB). Peak memory consumption was 21.9 MB. Max. memory is 11.5 GB. * TraceAbstraction took 738815.11 ms. Allocated memory was 1.1 GB in the beginning and 4.6 GB in the end (delta: 3.5 GB). Free memory was 1.1 GB in the beginning and 2.2 GB in the end (delta: -1.2 GB). Peak memory consumption was 2.3 GB. Max. memory is 11.5 GB. * Witness Printer took 251.87 ms. Allocated memory is still 4.6 GB. Free memory was 2.2 GB in the beginning and 2.1 GB in the end (delta: 174.3 MB). Peak memory consumption was 174.3 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 18]: array index can be out of bounds array index can be out of bounds We found a FailurePath: [L24] int i, b[32]; [L25] char mask[32]; [L26] i = 0 VAL [b={33:0}, i=0, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=0, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=1, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=1, b={34:0}, b={34:0}, i=0, size=1] [L17] COND TRUE i <= size VAL [\old(size)=1, b={34:0}, b={34:0}, i=0, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={34:0}, b={34:0}, i=0, size=1] [L18] EXPR b[i] VAL [\old(size)=1, b={34:0}, b={34:0}, b[i]=147, i=0, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={34:0}, b={34:0}, i=1, size=1] [L17] COND TRUE i <= size VAL [\old(size)=1, b={34:0}, b={34:0}, i=1, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={34:0}, b={34:0}, i=1, size=1] [L18] EXPR b[i] VAL [\old(size)=1, b={34:0}, b={34:0}, b[i]=160, i=1, size=1] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=1, b={34:0}, b={34:0}, i=2, size=1] [L17] COND FALSE !(i <= size) VAL [\old(size)=1, b={34:0}, b={34:0}, i=2, size=1] [L20] return i; VAL [\old(size)=1, \result=2, b={34:0}, b={34:0}, i=2, size=1] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=2, i=0, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=2, i=0, mask={34:0}] [L26] i++ VAL [b={33:0}, i=1, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=1, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=2, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=2, b={34:0}, b={34:0}, i=0, size=2] [L17] COND TRUE i <= size VAL [\old(size)=2, b={34:0}, b={34:0}, i=0, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={34:0}, b={34:0}, i=0, size=2] [L18] EXPR b[i] VAL [\old(size)=2, b={34:0}, b={34:0}, b[i]=147, i=0, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={34:0}, b={34:0}, i=1, size=2] [L17] COND TRUE i <= size VAL [\old(size)=2, b={34:0}, b={34:0}, i=1, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={34:0}, b={34:0}, i=1, size=2] [L18] EXPR b[i] VAL [\old(size)=2, b={34:0}, b={34:0}, b[i]=160, i=1, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={34:0}, b={34:0}, i=2, size=2] [L17] COND TRUE i <= size VAL [\old(size)=2, b={34:0}, b={34:0}, i=2, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={34:0}, b={34:0}, i=2, size=2] [L18] EXPR b[i] VAL [\old(size)=2, b={34:0}, b={34:0}, b[i]=130, i=2, size=2] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=2, b={34:0}, b={34:0}, i=3, size=2] [L17] COND FALSE !(i <= size) VAL [\old(size)=2, b={34:0}, b={34:0}, i=3, size=2] [L20] return i; VAL [\old(size)=2, \result=3, b={34:0}, b={34:0}, i=3, size=2] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=3, i=1, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=3, i=1, mask={34:0}] [L26] i++ VAL [b={33:0}, i=2, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=2, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=3, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=3, b={34:0}, b={34:0}, i=0, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={34:0}, b={34:0}, i=0, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={34:0}, b={34:0}, i=0, size=3] [L18] EXPR b[i] VAL [\old(size)=3, b={34:0}, b={34:0}, b[i]=147, i=0, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={34:0}, b={34:0}, i=1, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={34:0}, b={34:0}, i=1, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={34:0}, b={34:0}, i=1, size=3] [L18] EXPR b[i] VAL [\old(size)=3, b={34:0}, b={34:0}, b[i]=160, i=1, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={34:0}, b={34:0}, i=2, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={34:0}, b={34:0}, i=2, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={34:0}, b={34:0}, i=2, size=3] [L18] EXPR b[i] VAL [\old(size)=3, b={34:0}, b={34:0}, b[i]=130, i=2, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={34:0}, b={34:0}, i=3, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={34:0}, b={34:0}, i=3, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={34:0}, b={34:0}, i=3, size=3] [L18] EXPR b[i] VAL [\old(size)=3, b={34:0}, b={34:0}, b[i]=132, i=3, size=3] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=3, b={34:0}, b={34:0}, i=4, size=3] [L17] COND FALSE !(i <= size) VAL [\old(size)=3, b={34:0}, b={34:0}, i=4, size=3] [L20] return i; VAL [\old(size)=3, \result=4, b={34:0}, b={34:0}, i=4, size=3] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=4, i=2, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=4, i=2, mask={34:0}] [L26] i++ VAL [b={33:0}, i=3, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=3, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=4, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=4, b={34:0}, b={34:0}, i=0, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={34:0}, b={34:0}, i=0, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={34:0}, b={34:0}, i=0, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={34:0}, b={34:0}, b[i]=147, i=0, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={34:0}, b={34:0}, i=1, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={34:0}, b={34:0}, i=1, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={34:0}, b={34:0}, i=1, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={34:0}, b={34:0}, b[i]=160, i=1, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={34:0}, b={34:0}, i=2, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={34:0}, b={34:0}, i=2, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={34:0}, b={34:0}, i=2, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={34:0}, b={34:0}, b[i]=130, i=2, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={34:0}, b={34:0}, i=3, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={34:0}, b={34:0}, i=3, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={34:0}, b={34:0}, i=3, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={34:0}, b={34:0}, b[i]=132, i=3, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={34:0}, b={34:0}, i=4, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={34:0}, b={34:0}, i=4, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={34:0}, b={34:0}, i=4, size=4] [L18] EXPR b[i] VAL [\old(size)=4, b={34:0}, b={34:0}, b[i]=131, i=4, size=4] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=4, b={34:0}, b={34:0}, i=5, size=4] [L17] COND FALSE !(i <= size) VAL [\old(size)=4, b={34:0}, b={34:0}, i=5, size=4] [L20] return i; VAL [\old(size)=4, \result=5, b={34:0}, b={34:0}, i=5, size=4] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=5, i=3, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=5, i=3, mask={34:0}] [L26] i++ VAL [b={33:0}, i=4, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=4, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=5, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=5, b={34:0}, b={34:0}, i=0, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={34:0}, b={34:0}, i=0, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={34:0}, b={34:0}, i=0, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={34:0}, b={34:0}, b[i]=147, i=0, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={34:0}, b={34:0}, i=1, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={34:0}, b={34:0}, i=1, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={34:0}, b={34:0}, i=1, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={34:0}, b={34:0}, b[i]=160, i=1, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={34:0}, b={34:0}, i=2, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={34:0}, b={34:0}, i=2, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={34:0}, b={34:0}, i=2, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={34:0}, b={34:0}, b[i]=130, i=2, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={34:0}, b={34:0}, i=3, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={34:0}, b={34:0}, i=3, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={34:0}, b={34:0}, i=3, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={34:0}, b={34:0}, b[i]=132, i=3, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={34:0}, b={34:0}, i=4, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={34:0}, b={34:0}, i=4, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={34:0}, b={34:0}, i=4, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={34:0}, b={34:0}, b[i]=131, i=4, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={34:0}, b={34:0}, i=5, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={34:0}, b={34:0}, i=5, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={34:0}, b={34:0}, i=5, size=5] [L18] EXPR b[i] VAL [\old(size)=5, b={34:0}, b={34:0}, b[i]=140, i=5, size=5] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=5, b={34:0}, b={34:0}, i=6, size=5] [L17] COND FALSE !(i <= size) VAL [\old(size)=5, b={34:0}, b={34:0}, i=6, size=5] [L20] return i; VAL [\old(size)=5, \result=6, b={34:0}, b={34:0}, i=6, size=5] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=6, i=4, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=6, i=4, mask={34:0}] [L26] i++ VAL [b={33:0}, i=5, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=5, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=6, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=6, b={34:0}, b={34:0}, i=0, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={34:0}, b={34:0}, i=0, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={34:0}, b={34:0}, i=0, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={34:0}, b={34:0}, b[i]=147, i=0, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={34:0}, b={34:0}, i=1, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={34:0}, b={34:0}, i=1, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={34:0}, b={34:0}, i=1, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={34:0}, b={34:0}, b[i]=160, i=1, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={34:0}, b={34:0}, i=2, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={34:0}, b={34:0}, i=2, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={34:0}, b={34:0}, i=2, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={34:0}, b={34:0}, b[i]=130, i=2, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={34:0}, b={34:0}, i=3, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={34:0}, b={34:0}, i=3, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={34:0}, b={34:0}, i=3, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={34:0}, b={34:0}, b[i]=132, i=3, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={34:0}, b={34:0}, i=4, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={34:0}, b={34:0}, i=4, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={34:0}, b={34:0}, i=4, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={34:0}, b={34:0}, b[i]=131, i=4, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={34:0}, b={34:0}, i=5, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={34:0}, b={34:0}, i=5, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={34:0}, b={34:0}, i=5, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={34:0}, b={34:0}, b[i]=140, i=5, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={34:0}, b={34:0}, i=6, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={34:0}, b={34:0}, i=6, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={34:0}, b={34:0}, i=6, size=6] [L18] EXPR b[i] VAL [\old(size)=6, b={34:0}, b={34:0}, b[i]=129, i=6, size=6] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=6, b={34:0}, b={34:0}, i=7, size=6] [L17] COND FALSE !(i <= size) VAL [\old(size)=6, b={34:0}, b={34:0}, i=7, size=6] [L20] return i; VAL [\old(size)=6, \result=7, b={34:0}, b={34:0}, i=7, size=6] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=7, i=5, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=7, i=5, mask={34:0}] [L26] i++ VAL [b={33:0}, i=6, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=6, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=7, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=7, b={34:0}, b={34:0}, i=0, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={34:0}, b={34:0}, i=0, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={34:0}, b={34:0}, i=0, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={34:0}, b={34:0}, b[i]=147, i=0, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={34:0}, b={34:0}, i=1, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={34:0}, b={34:0}, i=1, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={34:0}, b={34:0}, i=1, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={34:0}, b={34:0}, b[i]=160, i=1, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={34:0}, b={34:0}, i=2, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={34:0}, b={34:0}, i=2, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={34:0}, b={34:0}, i=2, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={34:0}, b={34:0}, b[i]=130, i=2, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={34:0}, b={34:0}, i=3, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={34:0}, b={34:0}, i=3, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={34:0}, b={34:0}, i=3, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={34:0}, b={34:0}, b[i]=132, i=3, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={34:0}, b={34:0}, i=4, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={34:0}, b={34:0}, i=4, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={34:0}, b={34:0}, i=4, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={34:0}, b={34:0}, b[i]=131, i=4, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={34:0}, b={34:0}, i=5, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={34:0}, b={34:0}, i=5, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={34:0}, b={34:0}, i=5, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={34:0}, b={34:0}, b[i]=140, i=5, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={34:0}, b={34:0}, i=6, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={34:0}, b={34:0}, i=6, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={34:0}, b={34:0}, i=6, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={34:0}, b={34:0}, b[i]=129, i=6, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={34:0}, b={34:0}, i=7, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={34:0}, b={34:0}, i=7, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={34:0}, b={34:0}, i=7, size=7] [L18] EXPR b[i] VAL [\old(size)=7, b={34:0}, b={34:0}, b[i]=148, i=7, size=7] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=7, b={34:0}, b={34:0}, i=8, size=7] [L17] COND FALSE !(i <= size) VAL [\old(size)=7, b={34:0}, b={34:0}, i=8, size=7] [L20] return i; VAL [\old(size)=7, \result=8, b={34:0}, b={34:0}, i=8, size=7] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=8, i=6, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=8, i=6, mask={34:0}] [L26] i++ VAL [b={33:0}, i=7, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=7, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=8, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=8, b={34:0}, b={34:0}, i=0, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={34:0}, b={34:0}, i=0, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={34:0}, b={34:0}, i=0, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={34:0}, b={34:0}, b[i]=147, i=0, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={34:0}, b={34:0}, i=1, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={34:0}, b={34:0}, i=1, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={34:0}, b={34:0}, i=1, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={34:0}, b={34:0}, b[i]=160, i=1, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={34:0}, b={34:0}, i=2, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={34:0}, b={34:0}, i=2, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={34:0}, b={34:0}, i=2, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={34:0}, b={34:0}, b[i]=130, i=2, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={34:0}, b={34:0}, i=3, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={34:0}, b={34:0}, i=3, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={34:0}, b={34:0}, i=3, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={34:0}, b={34:0}, b[i]=132, i=3, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={34:0}, b={34:0}, i=4, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={34:0}, b={34:0}, i=4, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={34:0}, b={34:0}, i=4, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={34:0}, b={34:0}, b[i]=131, i=4, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={34:0}, b={34:0}, i=5, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={34:0}, b={34:0}, i=5, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={34:0}, b={34:0}, i=5, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={34:0}, b={34:0}, b[i]=140, i=5, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={34:0}, b={34:0}, i=6, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={34:0}, b={34:0}, i=6, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={34:0}, b={34:0}, i=6, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={34:0}, b={34:0}, b[i]=129, i=6, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={34:0}, b={34:0}, i=7, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={34:0}, b={34:0}, i=7, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={34:0}, b={34:0}, i=7, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={34:0}, b={34:0}, b[i]=148, i=7, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={34:0}, b={34:0}, i=8, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={34:0}, b={34:0}, i=8, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={34:0}, b={34:0}, i=8, size=8] [L18] EXPR b[i] VAL [\old(size)=8, b={34:0}, b={34:0}, b[i]=154, i=8, size=8] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=8, b={34:0}, b={34:0}, i=9, size=8] [L17] COND FALSE !(i <= size) VAL [\old(size)=8, b={34:0}, b={34:0}, i=9, size=8] [L20] return i; VAL [\old(size)=8, \result=9, b={34:0}, b={34:0}, i=9, size=8] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=9, i=7, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=9, i=7, mask={34:0}] [L26] i++ VAL [b={33:0}, i=8, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=8, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=9, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=9, b={34:0}, b={34:0}, i=0, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={34:0}, b={34:0}, i=0, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={34:0}, b={34:0}, i=0, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={34:0}, b={34:0}, b[i]=147, i=0, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={34:0}, b={34:0}, i=1, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={34:0}, b={34:0}, i=1, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={34:0}, b={34:0}, i=1, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={34:0}, b={34:0}, b[i]=160, i=1, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={34:0}, b={34:0}, i=2, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={34:0}, b={34:0}, i=2, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={34:0}, b={34:0}, i=2, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={34:0}, b={34:0}, b[i]=130, i=2, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={34:0}, b={34:0}, i=3, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={34:0}, b={34:0}, i=3, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={34:0}, b={34:0}, i=3, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={34:0}, b={34:0}, b[i]=132, i=3, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={34:0}, b={34:0}, i=4, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={34:0}, b={34:0}, i=4, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={34:0}, b={34:0}, i=4, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={34:0}, b={34:0}, b[i]=131, i=4, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={34:0}, b={34:0}, i=5, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={34:0}, b={34:0}, i=5, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={34:0}, b={34:0}, i=5, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={34:0}, b={34:0}, b[i]=140, i=5, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={34:0}, b={34:0}, i=6, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={34:0}, b={34:0}, i=6, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={34:0}, b={34:0}, i=6, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={34:0}, b={34:0}, b[i]=129, i=6, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={34:0}, b={34:0}, i=7, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={34:0}, b={34:0}, i=7, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={34:0}, b={34:0}, i=7, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={34:0}, b={34:0}, b[i]=148, i=7, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={34:0}, b={34:0}, i=8, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={34:0}, b={34:0}, i=8, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={34:0}, b={34:0}, i=8, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={34:0}, b={34:0}, b[i]=154, i=8, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={34:0}, b={34:0}, i=9, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={34:0}, b={34:0}, i=9, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={34:0}, b={34:0}, i=9, size=9] [L18] EXPR b[i] VAL [\old(size)=9, b={34:0}, b={34:0}, b[i]=136, i=9, size=9] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=9, b={34:0}, b={34:0}, i=10, size=9] [L17] COND FALSE !(i <= size) VAL [\old(size)=9, b={34:0}, b={34:0}, i=10, size=9] [L20] return i; VAL [\old(size)=9, \result=10, b={34:0}, b={34:0}, i=10, size=9] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=10, i=8, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=10, i=8, mask={34:0}] [L26] i++ VAL [b={33:0}, i=9, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=9, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=10, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=10, b={34:0}, b={34:0}, i=0, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={34:0}, b={34:0}, i=0, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={34:0}, b={34:0}, i=0, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={34:0}, b={34:0}, b[i]=147, i=0, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={34:0}, b={34:0}, i=1, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={34:0}, b={34:0}, i=1, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={34:0}, b={34:0}, i=1, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={34:0}, b={34:0}, b[i]=160, i=1, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={34:0}, b={34:0}, i=2, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={34:0}, b={34:0}, i=2, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={34:0}, b={34:0}, i=2, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={34:0}, b={34:0}, b[i]=130, i=2, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={34:0}, b={34:0}, i=3, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={34:0}, b={34:0}, i=3, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={34:0}, b={34:0}, i=3, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={34:0}, b={34:0}, b[i]=132, i=3, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={34:0}, b={34:0}, i=4, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={34:0}, b={34:0}, i=4, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={34:0}, b={34:0}, i=4, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={34:0}, b={34:0}, b[i]=131, i=4, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={34:0}, b={34:0}, i=5, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={34:0}, b={34:0}, i=5, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={34:0}, b={34:0}, i=5, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={34:0}, b={34:0}, b[i]=140, i=5, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={34:0}, b={34:0}, i=6, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={34:0}, b={34:0}, i=6, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={34:0}, b={34:0}, i=6, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={34:0}, b={34:0}, b[i]=129, i=6, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={34:0}, b={34:0}, i=7, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={34:0}, b={34:0}, i=7, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={34:0}, b={34:0}, i=7, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={34:0}, b={34:0}, b[i]=148, i=7, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={34:0}, b={34:0}, i=8, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={34:0}, b={34:0}, i=8, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={34:0}, b={34:0}, i=8, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={34:0}, b={34:0}, b[i]=154, i=8, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={34:0}, b={34:0}, i=9, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={34:0}, b={34:0}, i=9, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={34:0}, b={34:0}, i=9, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={34:0}, b={34:0}, b[i]=136, i=9, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={34:0}, b={34:0}, i=10, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={34:0}, b={34:0}, i=10, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={34:0}, b={34:0}, i=10, size=10] [L18] EXPR b[i] VAL [\old(size)=10, b={34:0}, b={34:0}, b[i]=149, i=10, size=10] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=10, b={34:0}, b={34:0}, i=11, size=10] [L17] COND FALSE !(i <= size) VAL [\old(size)=10, b={34:0}, b={34:0}, i=11, size=10] [L20] return i; VAL [\old(size)=10, \result=11, b={34:0}, b={34:0}, i=11, size=10] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=11, i=9, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=11, i=9, mask={34:0}] [L26] i++ VAL [b={33:0}, i=10, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=10, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=11, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=11, b={34:0}, b={34:0}, i=0, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={34:0}, b={34:0}, i=0, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={34:0}, b={34:0}, i=0, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={34:0}, b={34:0}, b[i]=147, i=0, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={34:0}, b={34:0}, i=1, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={34:0}, b={34:0}, i=1, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={34:0}, b={34:0}, i=1, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={34:0}, b={34:0}, b[i]=160, i=1, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={34:0}, b={34:0}, i=2, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={34:0}, b={34:0}, i=2, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={34:0}, b={34:0}, i=2, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={34:0}, b={34:0}, b[i]=130, i=2, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={34:0}, b={34:0}, i=3, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={34:0}, b={34:0}, i=3, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={34:0}, b={34:0}, i=3, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={34:0}, b={34:0}, b[i]=132, i=3, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={34:0}, b={34:0}, i=4, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={34:0}, b={34:0}, i=4, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={34:0}, b={34:0}, i=4, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={34:0}, b={34:0}, b[i]=131, i=4, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={34:0}, b={34:0}, i=5, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={34:0}, b={34:0}, i=5, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={34:0}, b={34:0}, i=5, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={34:0}, b={34:0}, b[i]=140, i=5, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={34:0}, b={34:0}, i=6, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={34:0}, b={34:0}, i=6, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={34:0}, b={34:0}, i=6, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={34:0}, b={34:0}, b[i]=129, i=6, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={34:0}, b={34:0}, i=7, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={34:0}, b={34:0}, i=7, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={34:0}, b={34:0}, i=7, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={34:0}, b={34:0}, b[i]=148, i=7, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={34:0}, b={34:0}, i=8, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={34:0}, b={34:0}, i=8, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={34:0}, b={34:0}, i=8, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={34:0}, b={34:0}, b[i]=154, i=8, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={34:0}, b={34:0}, i=9, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={34:0}, b={34:0}, i=9, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={34:0}, b={34:0}, i=9, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={34:0}, b={34:0}, b[i]=136, i=9, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={34:0}, b={34:0}, i=10, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={34:0}, b={34:0}, i=10, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={34:0}, b={34:0}, i=10, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={34:0}, b={34:0}, b[i]=149, i=10, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={34:0}, b={34:0}, i=11, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={34:0}, b={34:0}, i=11, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={34:0}, b={34:0}, i=11, size=11] [L18] EXPR b[i] VAL [\old(size)=11, b={34:0}, b={34:0}, b[i]=145, i=11, size=11] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=11, b={34:0}, b={34:0}, i=12, size=11] [L17] COND FALSE !(i <= size) VAL [\old(size)=11, b={34:0}, b={34:0}, i=12, size=11] [L20] return i; VAL [\old(size)=11, \result=12, b={34:0}, b={34:0}, i=12, size=11] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=12, i=10, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=12, i=10, mask={34:0}] [L26] i++ VAL [b={33:0}, i=11, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=11, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=12, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=12, b={34:0}, b={34:0}, i=0, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={34:0}, b={34:0}, i=0, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={34:0}, b={34:0}, i=0, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={34:0}, b={34:0}, b[i]=147, i=0, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={34:0}, b={34:0}, i=1, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={34:0}, b={34:0}, i=1, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={34:0}, b={34:0}, i=1, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={34:0}, b={34:0}, b[i]=160, i=1, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={34:0}, b={34:0}, i=2, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={34:0}, b={34:0}, i=2, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={34:0}, b={34:0}, i=2, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={34:0}, b={34:0}, b[i]=130, i=2, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={34:0}, b={34:0}, i=3, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={34:0}, b={34:0}, i=3, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={34:0}, b={34:0}, i=3, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={34:0}, b={34:0}, b[i]=132, i=3, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={34:0}, b={34:0}, i=4, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={34:0}, b={34:0}, i=4, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={34:0}, b={34:0}, i=4, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={34:0}, b={34:0}, b[i]=131, i=4, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={34:0}, b={34:0}, i=5, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={34:0}, b={34:0}, i=5, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={34:0}, b={34:0}, i=5, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={34:0}, b={34:0}, b[i]=140, i=5, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={34:0}, b={34:0}, i=6, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={34:0}, b={34:0}, i=6, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={34:0}, b={34:0}, i=6, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={34:0}, b={34:0}, b[i]=129, i=6, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={34:0}, b={34:0}, i=7, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={34:0}, b={34:0}, i=7, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={34:0}, b={34:0}, i=7, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={34:0}, b={34:0}, b[i]=148, i=7, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={34:0}, b={34:0}, i=8, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={34:0}, b={34:0}, i=8, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={34:0}, b={34:0}, i=8, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={34:0}, b={34:0}, b[i]=154, i=8, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={34:0}, b={34:0}, i=9, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={34:0}, b={34:0}, i=9, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={34:0}, b={34:0}, i=9, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={34:0}, b={34:0}, b[i]=136, i=9, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={34:0}, b={34:0}, i=10, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={34:0}, b={34:0}, i=10, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={34:0}, b={34:0}, i=10, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={34:0}, b={34:0}, b[i]=149, i=10, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={34:0}, b={34:0}, i=11, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={34:0}, b={34:0}, i=11, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={34:0}, b={34:0}, i=11, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={34:0}, b={34:0}, b[i]=145, i=11, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={34:0}, b={34:0}, i=12, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={34:0}, b={34:0}, i=12, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={34:0}, b={34:0}, i=12, size=12] [L18] EXPR b[i] VAL [\old(size)=12, b={34:0}, b={34:0}, b[i]=150, i=12, size=12] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=12, b={34:0}, b={34:0}, i=13, size=12] [L17] COND FALSE !(i <= size) VAL [\old(size)=12, b={34:0}, b={34:0}, i=13, size=12] [L20] return i; VAL [\old(size)=12, \result=13, b={34:0}, b={34:0}, i=13, size=12] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=13, i=11, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=13, i=11, mask={34:0}] [L26] i++ VAL [b={33:0}, i=12, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=12, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=13, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=13, b={34:0}, b={34:0}, i=0, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={34:0}, b={34:0}, i=0, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={34:0}, b={34:0}, i=0, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={34:0}, b={34:0}, b[i]=147, i=0, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={34:0}, b={34:0}, i=1, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={34:0}, b={34:0}, i=1, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={34:0}, b={34:0}, i=1, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={34:0}, b={34:0}, b[i]=160, i=1, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={34:0}, b={34:0}, i=2, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={34:0}, b={34:0}, i=2, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={34:0}, b={34:0}, i=2, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={34:0}, b={34:0}, b[i]=130, i=2, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={34:0}, b={34:0}, i=3, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={34:0}, b={34:0}, i=3, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={34:0}, b={34:0}, i=3, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={34:0}, b={34:0}, b[i]=132, i=3, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={34:0}, b={34:0}, i=4, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={34:0}, b={34:0}, i=4, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={34:0}, b={34:0}, i=4, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={34:0}, b={34:0}, b[i]=131, i=4, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={34:0}, b={34:0}, i=5, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={34:0}, b={34:0}, i=5, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={34:0}, b={34:0}, i=5, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={34:0}, b={34:0}, b[i]=140, i=5, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={34:0}, b={34:0}, i=6, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={34:0}, b={34:0}, i=6, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={34:0}, b={34:0}, i=6, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={34:0}, b={34:0}, b[i]=129, i=6, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={34:0}, b={34:0}, i=7, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={34:0}, b={34:0}, i=7, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={34:0}, b={34:0}, i=7, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={34:0}, b={34:0}, b[i]=148, i=7, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={34:0}, b={34:0}, i=8, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={34:0}, b={34:0}, i=8, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={34:0}, b={34:0}, i=8, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={34:0}, b={34:0}, b[i]=154, i=8, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={34:0}, b={34:0}, i=9, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={34:0}, b={34:0}, i=9, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={34:0}, b={34:0}, i=9, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={34:0}, b={34:0}, b[i]=136, i=9, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={34:0}, b={34:0}, i=10, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={34:0}, b={34:0}, i=10, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={34:0}, b={34:0}, i=10, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={34:0}, b={34:0}, b[i]=149, i=10, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={34:0}, b={34:0}, i=11, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={34:0}, b={34:0}, i=11, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={34:0}, b={34:0}, i=11, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={34:0}, b={34:0}, b[i]=145, i=11, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={34:0}, b={34:0}, i=12, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={34:0}, b={34:0}, i=12, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={34:0}, b={34:0}, i=12, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={34:0}, b={34:0}, b[i]=150, i=12, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={34:0}, b={34:0}, i=13, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={34:0}, b={34:0}, i=13, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={34:0}, b={34:0}, i=13, size=13] [L18] EXPR b[i] VAL [\old(size)=13, b={34:0}, b={34:0}, b[i]=156, i=13, size=13] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=13, b={34:0}, b={34:0}, i=14, size=13] [L17] COND FALSE !(i <= size) VAL [\old(size)=13, b={34:0}, b={34:0}, i=14, size=13] [L20] return i; VAL [\old(size)=13, \result=14, b={34:0}, b={34:0}, i=14, size=13] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=14, i=12, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=14, i=12, mask={34:0}] [L26] i++ VAL [b={33:0}, i=13, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=13, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=14, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=14, b={34:0}, b={34:0}, i=0, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={34:0}, b={34:0}, i=0, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={34:0}, b={34:0}, i=0, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={34:0}, b={34:0}, b[i]=147, i=0, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={34:0}, b={34:0}, i=1, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={34:0}, b={34:0}, i=1, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={34:0}, b={34:0}, i=1, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={34:0}, b={34:0}, b[i]=160, i=1, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={34:0}, b={34:0}, i=2, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={34:0}, b={34:0}, i=2, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={34:0}, b={34:0}, i=2, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={34:0}, b={34:0}, b[i]=130, i=2, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={34:0}, b={34:0}, i=3, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={34:0}, b={34:0}, i=3, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={34:0}, b={34:0}, i=3, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={34:0}, b={34:0}, b[i]=132, i=3, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={34:0}, b={34:0}, i=4, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={34:0}, b={34:0}, i=4, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={34:0}, b={34:0}, i=4, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={34:0}, b={34:0}, b[i]=131, i=4, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={34:0}, b={34:0}, i=5, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={34:0}, b={34:0}, i=5, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={34:0}, b={34:0}, i=5, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={34:0}, b={34:0}, b[i]=140, i=5, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={34:0}, b={34:0}, i=6, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={34:0}, b={34:0}, i=6, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={34:0}, b={34:0}, i=6, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={34:0}, b={34:0}, b[i]=129, i=6, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={34:0}, b={34:0}, i=7, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={34:0}, b={34:0}, i=7, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={34:0}, b={34:0}, i=7, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={34:0}, b={34:0}, b[i]=148, i=7, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={34:0}, b={34:0}, i=8, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={34:0}, b={34:0}, i=8, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={34:0}, b={34:0}, i=8, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={34:0}, b={34:0}, b[i]=154, i=8, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={34:0}, b={34:0}, i=9, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={34:0}, b={34:0}, i=9, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={34:0}, b={34:0}, i=9, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={34:0}, b={34:0}, b[i]=136, i=9, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={34:0}, b={34:0}, i=10, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={34:0}, b={34:0}, i=10, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={34:0}, b={34:0}, i=10, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={34:0}, b={34:0}, b[i]=149, i=10, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={34:0}, b={34:0}, i=11, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={34:0}, b={34:0}, i=11, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={34:0}, b={34:0}, i=11, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={34:0}, b={34:0}, b[i]=145, i=11, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={34:0}, b={34:0}, i=12, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={34:0}, b={34:0}, i=12, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={34:0}, b={34:0}, i=12, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={34:0}, b={34:0}, b[i]=150, i=12, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={34:0}, b={34:0}, i=13, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={34:0}, b={34:0}, i=13, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={34:0}, b={34:0}, i=13, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={34:0}, b={34:0}, b[i]=156, i=13, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={34:0}, b={34:0}, i=14, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={34:0}, b={34:0}, i=14, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={34:0}, b={34:0}, i=14, size=14] [L18] EXPR b[i] VAL [\old(size)=14, b={34:0}, b={34:0}, b[i]=153, i=14, size=14] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=14, b={34:0}, b={34:0}, i=15, size=14] [L17] COND FALSE !(i <= size) VAL [\old(size)=14, b={34:0}, b={34:0}, i=15, size=14] [L20] return i; VAL [\old(size)=14, \result=15, b={34:0}, b={34:0}, i=15, size=14] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=15, i=13, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=15, i=13, mask={34:0}] [L26] i++ VAL [b={33:0}, i=14, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=14, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=15, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=15, b={34:0}, b={34:0}, i=0, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={34:0}, b={34:0}, i=0, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={34:0}, b={34:0}, i=0, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={34:0}, b={34:0}, b[i]=147, i=0, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={34:0}, b={34:0}, i=1, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={34:0}, b={34:0}, i=1, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={34:0}, b={34:0}, i=1, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={34:0}, b={34:0}, b[i]=160, i=1, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={34:0}, b={34:0}, i=2, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={34:0}, b={34:0}, i=2, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={34:0}, b={34:0}, i=2, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={34:0}, b={34:0}, b[i]=130, i=2, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={34:0}, b={34:0}, i=3, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={34:0}, b={34:0}, i=3, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={34:0}, b={34:0}, i=3, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={34:0}, b={34:0}, b[i]=132, i=3, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={34:0}, b={34:0}, i=4, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={34:0}, b={34:0}, i=4, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={34:0}, b={34:0}, i=4, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={34:0}, b={34:0}, b[i]=131, i=4, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={34:0}, b={34:0}, i=5, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={34:0}, b={34:0}, i=5, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={34:0}, b={34:0}, i=5, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={34:0}, b={34:0}, b[i]=140, i=5, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={34:0}, b={34:0}, i=6, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={34:0}, b={34:0}, i=6, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={34:0}, b={34:0}, i=6, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={34:0}, b={34:0}, b[i]=129, i=6, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={34:0}, b={34:0}, i=7, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={34:0}, b={34:0}, i=7, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={34:0}, b={34:0}, i=7, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={34:0}, b={34:0}, b[i]=148, i=7, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={34:0}, b={34:0}, i=8, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={34:0}, b={34:0}, i=8, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={34:0}, b={34:0}, i=8, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={34:0}, b={34:0}, b[i]=154, i=8, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={34:0}, b={34:0}, i=9, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={34:0}, b={34:0}, i=9, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={34:0}, b={34:0}, i=9, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={34:0}, b={34:0}, b[i]=136, i=9, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={34:0}, b={34:0}, i=10, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={34:0}, b={34:0}, i=10, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={34:0}, b={34:0}, i=10, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={34:0}, b={34:0}, b[i]=149, i=10, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={34:0}, b={34:0}, i=11, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={34:0}, b={34:0}, i=11, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={34:0}, b={34:0}, i=11, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={34:0}, b={34:0}, b[i]=145, i=11, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={34:0}, b={34:0}, i=12, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={34:0}, b={34:0}, i=12, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={34:0}, b={34:0}, i=12, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={34:0}, b={34:0}, b[i]=150, i=12, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={34:0}, b={34:0}, i=13, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={34:0}, b={34:0}, i=13, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={34:0}, b={34:0}, i=13, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={34:0}, b={34:0}, b[i]=156, i=13, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={34:0}, b={34:0}, i=14, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={34:0}, b={34:0}, i=14, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={34:0}, b={34:0}, i=14, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={34:0}, b={34:0}, b[i]=153, i=14, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={34:0}, b={34:0}, i=15, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={34:0}, b={34:0}, i=15, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={34:0}, b={34:0}, i=15, size=15] [L18] EXPR b[i] VAL [\old(size)=15, b={34:0}, b={34:0}, b[i]=137, i=15, size=15] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=15, b={34:0}, b={34:0}, i=16, size=15] [L17] COND FALSE !(i <= size) VAL [\old(size)=15, b={34:0}, b={34:0}, i=16, size=15] [L20] return i; VAL [\old(size)=15, \result=16, b={34:0}, b={34:0}, i=16, size=15] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=16, i=14, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=16, i=14, mask={34:0}] [L26] i++ VAL [b={33:0}, i=15, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=15, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=16, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=16, b={34:0}, b={34:0}, i=0, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={34:0}, b={34:0}, i=0, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={34:0}, b={34:0}, i=0, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={34:0}, b={34:0}, b[i]=147, i=0, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={34:0}, b={34:0}, i=1, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={34:0}, b={34:0}, i=1, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={34:0}, b={34:0}, i=1, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={34:0}, b={34:0}, b[i]=160, i=1, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={34:0}, b={34:0}, i=2, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={34:0}, b={34:0}, i=2, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={34:0}, b={34:0}, i=2, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={34:0}, b={34:0}, b[i]=130, i=2, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={34:0}, b={34:0}, i=3, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={34:0}, b={34:0}, i=3, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={34:0}, b={34:0}, i=3, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={34:0}, b={34:0}, b[i]=132, i=3, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={34:0}, b={34:0}, i=4, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={34:0}, b={34:0}, i=4, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={34:0}, b={34:0}, i=4, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={34:0}, b={34:0}, b[i]=131, i=4, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={34:0}, b={34:0}, i=5, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={34:0}, b={34:0}, i=5, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={34:0}, b={34:0}, i=5, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={34:0}, b={34:0}, b[i]=140, i=5, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={34:0}, b={34:0}, i=6, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={34:0}, b={34:0}, i=6, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={34:0}, b={34:0}, i=6, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={34:0}, b={34:0}, b[i]=129, i=6, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={34:0}, b={34:0}, i=7, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={34:0}, b={34:0}, i=7, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={34:0}, b={34:0}, i=7, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={34:0}, b={34:0}, b[i]=148, i=7, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={34:0}, b={34:0}, i=8, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={34:0}, b={34:0}, i=8, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={34:0}, b={34:0}, i=8, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={34:0}, b={34:0}, b[i]=154, i=8, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={34:0}, b={34:0}, i=9, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={34:0}, b={34:0}, i=9, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={34:0}, b={34:0}, i=9, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={34:0}, b={34:0}, b[i]=136, i=9, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={34:0}, b={34:0}, i=10, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={34:0}, b={34:0}, i=10, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={34:0}, b={34:0}, i=10, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={34:0}, b={34:0}, b[i]=149, i=10, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={34:0}, b={34:0}, i=11, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={34:0}, b={34:0}, i=11, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={34:0}, b={34:0}, i=11, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={34:0}, b={34:0}, b[i]=145, i=11, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={34:0}, b={34:0}, i=12, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={34:0}, b={34:0}, i=12, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={34:0}, b={34:0}, i=12, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={34:0}, b={34:0}, b[i]=150, i=12, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={34:0}, b={34:0}, i=13, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={34:0}, b={34:0}, i=13, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={34:0}, b={34:0}, i=13, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={34:0}, b={34:0}, b[i]=156, i=13, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={34:0}, b={34:0}, i=14, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={34:0}, b={34:0}, i=14, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={34:0}, b={34:0}, i=14, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={34:0}, b={34:0}, b[i]=153, i=14, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={34:0}, b={34:0}, i=15, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={34:0}, b={34:0}, i=15, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={34:0}, b={34:0}, i=15, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={34:0}, b={34:0}, b[i]=137, i=15, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={34:0}, b={34:0}, i=16, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={34:0}, b={34:0}, i=16, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={34:0}, b={34:0}, i=16, size=16] [L18] EXPR b[i] VAL [\old(size)=16, b={34:0}, b={34:0}, b[i]=139, i=16, size=16] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=16, b={34:0}, b={34:0}, i=17, size=16] [L17] COND FALSE !(i <= size) VAL [\old(size)=16, b={34:0}, b={34:0}, i=17, size=16] [L20] return i; VAL [\old(size)=16, \result=17, b={34:0}, b={34:0}, i=17, size=16] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=17, i=15, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=17, i=15, mask={34:0}] [L26] i++ VAL [b={33:0}, i=16, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=16, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=17, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=17, b={34:0}, b={34:0}, i=0, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={34:0}, b={34:0}, i=0, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={34:0}, b={34:0}, i=0, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={34:0}, b={34:0}, b[i]=147, i=0, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={34:0}, b={34:0}, i=1, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={34:0}, b={34:0}, i=1, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={34:0}, b={34:0}, i=1, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={34:0}, b={34:0}, b[i]=160, i=1, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={34:0}, b={34:0}, i=2, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={34:0}, b={34:0}, i=2, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={34:0}, b={34:0}, i=2, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={34:0}, b={34:0}, b[i]=130, i=2, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={34:0}, b={34:0}, i=3, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={34:0}, b={34:0}, i=3, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={34:0}, b={34:0}, i=3, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={34:0}, b={34:0}, b[i]=132, i=3, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={34:0}, b={34:0}, i=4, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={34:0}, b={34:0}, i=4, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={34:0}, b={34:0}, i=4, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={34:0}, b={34:0}, b[i]=131, i=4, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={34:0}, b={34:0}, i=5, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={34:0}, b={34:0}, i=5, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={34:0}, b={34:0}, i=5, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={34:0}, b={34:0}, b[i]=140, i=5, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={34:0}, b={34:0}, i=6, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={34:0}, b={34:0}, i=6, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={34:0}, b={34:0}, i=6, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={34:0}, b={34:0}, b[i]=129, i=6, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={34:0}, b={34:0}, i=7, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={34:0}, b={34:0}, i=7, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={34:0}, b={34:0}, i=7, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={34:0}, b={34:0}, b[i]=148, i=7, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={34:0}, b={34:0}, i=8, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={34:0}, b={34:0}, i=8, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={34:0}, b={34:0}, i=8, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={34:0}, b={34:0}, b[i]=154, i=8, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={34:0}, b={34:0}, i=9, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={34:0}, b={34:0}, i=9, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={34:0}, b={34:0}, i=9, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={34:0}, b={34:0}, b[i]=136, i=9, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={34:0}, b={34:0}, i=10, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={34:0}, b={34:0}, i=10, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={34:0}, b={34:0}, i=10, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={34:0}, b={34:0}, b[i]=149, i=10, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={34:0}, b={34:0}, i=11, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={34:0}, b={34:0}, i=11, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={34:0}, b={34:0}, i=11, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={34:0}, b={34:0}, b[i]=145, i=11, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={34:0}, b={34:0}, i=12, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={34:0}, b={34:0}, i=12, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={34:0}, b={34:0}, i=12, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={34:0}, b={34:0}, b[i]=150, i=12, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={34:0}, b={34:0}, i=13, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={34:0}, b={34:0}, i=13, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={34:0}, b={34:0}, i=13, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={34:0}, b={34:0}, b[i]=156, i=13, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={34:0}, b={34:0}, i=14, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={34:0}, b={34:0}, i=14, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={34:0}, b={34:0}, i=14, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={34:0}, b={34:0}, b[i]=153, i=14, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={34:0}, b={34:0}, i=15, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={34:0}, b={34:0}, i=15, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={34:0}, b={34:0}, i=15, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={34:0}, b={34:0}, b[i]=137, i=15, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={34:0}, b={34:0}, i=16, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={34:0}, b={34:0}, i=16, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={34:0}, b={34:0}, i=16, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={34:0}, b={34:0}, b[i]=139, i=16, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={34:0}, b={34:0}, i=17, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={34:0}, b={34:0}, i=17, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={34:0}, b={34:0}, i=17, size=17] [L18] EXPR b[i] VAL [\old(size)=17, b={34:0}, b={34:0}, b[i]=151, i=17, size=17] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=17, b={34:0}, b={34:0}, i=18, size=17] [L17] COND FALSE !(i <= size) VAL [\old(size)=17, b={34:0}, b={34:0}, i=18, size=17] [L20] return i; VAL [\old(size)=17, \result=18, b={34:0}, b={34:0}, i=18, size=17] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=18, i=16, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=18, i=16, mask={34:0}] [L26] i++ VAL [b={33:0}, i=17, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=17, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=18, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=18, b={34:0}, b={34:0}, i=0, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={34:0}, b={34:0}, i=0, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={34:0}, b={34:0}, i=0, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={34:0}, b={34:0}, b[i]=147, i=0, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={34:0}, b={34:0}, i=1, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={34:0}, b={34:0}, i=1, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={34:0}, b={34:0}, i=1, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={34:0}, b={34:0}, b[i]=160, i=1, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={34:0}, b={34:0}, i=2, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={34:0}, b={34:0}, i=2, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={34:0}, b={34:0}, i=2, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={34:0}, b={34:0}, b[i]=130, i=2, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={34:0}, b={34:0}, i=3, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={34:0}, b={34:0}, i=3, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={34:0}, b={34:0}, i=3, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={34:0}, b={34:0}, b[i]=132, i=3, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={34:0}, b={34:0}, i=4, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={34:0}, b={34:0}, i=4, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={34:0}, b={34:0}, i=4, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={34:0}, b={34:0}, b[i]=131, i=4, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={34:0}, b={34:0}, i=5, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={34:0}, b={34:0}, i=5, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={34:0}, b={34:0}, i=5, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={34:0}, b={34:0}, b[i]=140, i=5, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={34:0}, b={34:0}, i=6, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={34:0}, b={34:0}, i=6, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={34:0}, b={34:0}, i=6, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={34:0}, b={34:0}, b[i]=129, i=6, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={34:0}, b={34:0}, i=7, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={34:0}, b={34:0}, i=7, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={34:0}, b={34:0}, i=7, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={34:0}, b={34:0}, b[i]=148, i=7, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={34:0}, b={34:0}, i=8, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={34:0}, b={34:0}, i=8, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={34:0}, b={34:0}, i=8, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={34:0}, b={34:0}, b[i]=154, i=8, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={34:0}, b={34:0}, i=9, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={34:0}, b={34:0}, i=9, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={34:0}, b={34:0}, i=9, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={34:0}, b={34:0}, b[i]=136, i=9, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={34:0}, b={34:0}, i=10, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={34:0}, b={34:0}, i=10, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={34:0}, b={34:0}, i=10, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={34:0}, b={34:0}, b[i]=149, i=10, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={34:0}, b={34:0}, i=11, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={34:0}, b={34:0}, i=11, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={34:0}, b={34:0}, i=11, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={34:0}, b={34:0}, b[i]=145, i=11, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={34:0}, b={34:0}, i=12, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={34:0}, b={34:0}, i=12, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={34:0}, b={34:0}, i=12, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={34:0}, b={34:0}, b[i]=150, i=12, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={34:0}, b={34:0}, i=13, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={34:0}, b={34:0}, i=13, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={34:0}, b={34:0}, i=13, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={34:0}, b={34:0}, b[i]=156, i=13, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={34:0}, b={34:0}, i=14, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={34:0}, b={34:0}, i=14, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={34:0}, b={34:0}, i=14, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={34:0}, b={34:0}, b[i]=153, i=14, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={34:0}, b={34:0}, i=15, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={34:0}, b={34:0}, i=15, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={34:0}, b={34:0}, i=15, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={34:0}, b={34:0}, b[i]=137, i=15, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={34:0}, b={34:0}, i=16, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={34:0}, b={34:0}, i=16, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={34:0}, b={34:0}, i=16, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={34:0}, b={34:0}, b[i]=139, i=16, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={34:0}, b={34:0}, i=17, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={34:0}, b={34:0}, i=17, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={34:0}, b={34:0}, i=17, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={34:0}, b={34:0}, b[i]=151, i=17, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={34:0}, b={34:0}, i=18, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={34:0}, b={34:0}, i=18, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={34:0}, b={34:0}, i=18, size=18] [L18] EXPR b[i] VAL [\old(size)=18, b={34:0}, b={34:0}, b[i]=141, i=18, size=18] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=18, b={34:0}, b={34:0}, i=19, size=18] [L17] COND FALSE !(i <= size) VAL [\old(size)=18, b={34:0}, b={34:0}, i=19, size=18] [L20] return i; VAL [\old(size)=18, \result=19, b={34:0}, b={34:0}, i=19, size=18] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=19, i=17, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=19, i=17, mask={34:0}] [L26] i++ VAL [b={33:0}, i=18, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=18, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=19, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=19, b={34:0}, b={34:0}, i=0, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={34:0}, b={34:0}, i=0, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={34:0}, b={34:0}, i=0, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={34:0}, b={34:0}, b[i]=147, i=0, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={34:0}, b={34:0}, i=1, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={34:0}, b={34:0}, i=1, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={34:0}, b={34:0}, i=1, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={34:0}, b={34:0}, b[i]=160, i=1, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={34:0}, b={34:0}, i=2, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={34:0}, b={34:0}, i=2, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={34:0}, b={34:0}, i=2, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={34:0}, b={34:0}, b[i]=130, i=2, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={34:0}, b={34:0}, i=3, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={34:0}, b={34:0}, i=3, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={34:0}, b={34:0}, i=3, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={34:0}, b={34:0}, b[i]=132, i=3, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={34:0}, b={34:0}, i=4, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={34:0}, b={34:0}, i=4, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={34:0}, b={34:0}, i=4, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={34:0}, b={34:0}, b[i]=131, i=4, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={34:0}, b={34:0}, i=5, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={34:0}, b={34:0}, i=5, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={34:0}, b={34:0}, i=5, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={34:0}, b={34:0}, b[i]=140, i=5, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={34:0}, b={34:0}, i=6, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={34:0}, b={34:0}, i=6, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={34:0}, b={34:0}, i=6, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={34:0}, b={34:0}, b[i]=129, i=6, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={34:0}, b={34:0}, i=7, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={34:0}, b={34:0}, i=7, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={34:0}, b={34:0}, i=7, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={34:0}, b={34:0}, b[i]=148, i=7, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={34:0}, b={34:0}, i=8, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={34:0}, b={34:0}, i=8, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={34:0}, b={34:0}, i=8, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={34:0}, b={34:0}, b[i]=154, i=8, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={34:0}, b={34:0}, i=9, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={34:0}, b={34:0}, i=9, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={34:0}, b={34:0}, i=9, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={34:0}, b={34:0}, b[i]=136, i=9, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={34:0}, b={34:0}, i=10, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={34:0}, b={34:0}, i=10, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={34:0}, b={34:0}, i=10, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={34:0}, b={34:0}, b[i]=149, i=10, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={34:0}, b={34:0}, i=11, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={34:0}, b={34:0}, i=11, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={34:0}, b={34:0}, i=11, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={34:0}, b={34:0}, b[i]=145, i=11, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={34:0}, b={34:0}, i=12, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={34:0}, b={34:0}, i=12, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={34:0}, b={34:0}, i=12, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={34:0}, b={34:0}, b[i]=150, i=12, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={34:0}, b={34:0}, i=13, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={34:0}, b={34:0}, i=13, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={34:0}, b={34:0}, i=13, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={34:0}, b={34:0}, b[i]=156, i=13, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={34:0}, b={34:0}, i=14, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={34:0}, b={34:0}, i=14, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={34:0}, b={34:0}, i=14, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={34:0}, b={34:0}, b[i]=153, i=14, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={34:0}, b={34:0}, i=15, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={34:0}, b={34:0}, i=15, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={34:0}, b={34:0}, i=15, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={34:0}, b={34:0}, b[i]=137, i=15, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={34:0}, b={34:0}, i=16, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={34:0}, b={34:0}, i=16, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={34:0}, b={34:0}, i=16, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={34:0}, b={34:0}, b[i]=139, i=16, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={34:0}, b={34:0}, i=17, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={34:0}, b={34:0}, i=17, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={34:0}, b={34:0}, i=17, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={34:0}, b={34:0}, b[i]=151, i=17, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={34:0}, b={34:0}, i=18, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={34:0}, b={34:0}, i=18, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={34:0}, b={34:0}, i=18, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={34:0}, b={34:0}, b[i]=141, i=18, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={34:0}, b={34:0}, i=19, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={34:0}, b={34:0}, i=19, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={34:0}, b={34:0}, i=19, size=19] [L18] EXPR b[i] VAL [\old(size)=19, b={34:0}, b={34:0}, b[i]=133, i=19, size=19] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=19, b={34:0}, b={34:0}, i=20, size=19] [L17] COND FALSE !(i <= size) VAL [\old(size)=19, b={34:0}, b={34:0}, i=20, size=19] [L20] return i; VAL [\old(size)=19, \result=20, b={34:0}, b={34:0}, i=20, size=19] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=20, i=18, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=20, i=18, mask={34:0}] [L26] i++ VAL [b={33:0}, i=19, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=19, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=20, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=20, b={34:0}, b={34:0}, i=0, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={34:0}, b={34:0}, i=0, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={34:0}, b={34:0}, i=0, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={34:0}, b={34:0}, b[i]=147, i=0, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={34:0}, b={34:0}, i=1, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={34:0}, b={34:0}, i=1, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={34:0}, b={34:0}, i=1, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={34:0}, b={34:0}, b[i]=160, i=1, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={34:0}, b={34:0}, i=2, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={34:0}, b={34:0}, i=2, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={34:0}, b={34:0}, i=2, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={34:0}, b={34:0}, b[i]=130, i=2, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={34:0}, b={34:0}, i=3, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={34:0}, b={34:0}, i=3, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={34:0}, b={34:0}, i=3, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={34:0}, b={34:0}, b[i]=132, i=3, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={34:0}, b={34:0}, i=4, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={34:0}, b={34:0}, i=4, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={34:0}, b={34:0}, i=4, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={34:0}, b={34:0}, b[i]=131, i=4, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={34:0}, b={34:0}, i=5, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={34:0}, b={34:0}, i=5, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={34:0}, b={34:0}, i=5, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={34:0}, b={34:0}, b[i]=140, i=5, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={34:0}, b={34:0}, i=6, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={34:0}, b={34:0}, i=6, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={34:0}, b={34:0}, i=6, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={34:0}, b={34:0}, b[i]=129, i=6, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={34:0}, b={34:0}, i=7, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={34:0}, b={34:0}, i=7, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={34:0}, b={34:0}, i=7, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={34:0}, b={34:0}, b[i]=148, i=7, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={34:0}, b={34:0}, i=8, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={34:0}, b={34:0}, i=8, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={34:0}, b={34:0}, i=8, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={34:0}, b={34:0}, b[i]=154, i=8, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={34:0}, b={34:0}, i=9, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={34:0}, b={34:0}, i=9, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={34:0}, b={34:0}, i=9, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={34:0}, b={34:0}, b[i]=136, i=9, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={34:0}, b={34:0}, i=10, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={34:0}, b={34:0}, i=10, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={34:0}, b={34:0}, i=10, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={34:0}, b={34:0}, b[i]=149, i=10, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={34:0}, b={34:0}, i=11, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={34:0}, b={34:0}, i=11, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={34:0}, b={34:0}, i=11, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={34:0}, b={34:0}, b[i]=145, i=11, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={34:0}, b={34:0}, i=12, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={34:0}, b={34:0}, i=12, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={34:0}, b={34:0}, i=12, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={34:0}, b={34:0}, b[i]=150, i=12, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={34:0}, b={34:0}, i=13, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={34:0}, b={34:0}, i=13, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={34:0}, b={34:0}, i=13, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={34:0}, b={34:0}, b[i]=156, i=13, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={34:0}, b={34:0}, i=14, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={34:0}, b={34:0}, i=14, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={34:0}, b={34:0}, i=14, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={34:0}, b={34:0}, b[i]=153, i=14, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={34:0}, b={34:0}, i=15, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={34:0}, b={34:0}, i=15, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={34:0}, b={34:0}, i=15, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={34:0}, b={34:0}, b[i]=137, i=15, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={34:0}, b={34:0}, i=16, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={34:0}, b={34:0}, i=16, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={34:0}, b={34:0}, i=16, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={34:0}, b={34:0}, b[i]=139, i=16, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={34:0}, b={34:0}, i=17, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={34:0}, b={34:0}, i=17, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={34:0}, b={34:0}, i=17, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={34:0}, b={34:0}, b[i]=151, i=17, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={34:0}, b={34:0}, i=18, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={34:0}, b={34:0}, i=18, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={34:0}, b={34:0}, i=18, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={34:0}, b={34:0}, b[i]=141, i=18, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={34:0}, b={34:0}, i=19, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={34:0}, b={34:0}, i=19, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={34:0}, b={34:0}, i=19, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={34:0}, b={34:0}, b[i]=133, i=19, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={34:0}, b={34:0}, i=20, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={34:0}, b={34:0}, i=20, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={34:0}, b={34:0}, i=20, size=20] [L18] EXPR b[i] VAL [\old(size)=20, b={34:0}, b={34:0}, b[i]=134, i=20, size=20] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=20, b={34:0}, b={34:0}, i=21, size=20] [L17] COND FALSE !(i <= size) VAL [\old(size)=20, b={34:0}, b={34:0}, i=21, size=20] [L20] return i; VAL [\old(size)=20, \result=21, b={34:0}, b={34:0}, i=21, size=20] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=21, i=19, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=21, i=19, mask={34:0}] [L26] i++ VAL [b={33:0}, i=20, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=20, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=21, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=21, b={34:0}, b={34:0}, i=0, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={34:0}, b={34:0}, i=0, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={34:0}, b={34:0}, i=0, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={34:0}, b={34:0}, b[i]=147, i=0, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={34:0}, b={34:0}, i=1, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={34:0}, b={34:0}, i=1, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={34:0}, b={34:0}, i=1, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={34:0}, b={34:0}, b[i]=160, i=1, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={34:0}, b={34:0}, i=2, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={34:0}, b={34:0}, i=2, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={34:0}, b={34:0}, i=2, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={34:0}, b={34:0}, b[i]=130, i=2, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={34:0}, b={34:0}, i=3, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={34:0}, b={34:0}, i=3, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={34:0}, b={34:0}, i=3, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={34:0}, b={34:0}, b[i]=132, i=3, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={34:0}, b={34:0}, i=4, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={34:0}, b={34:0}, i=4, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={34:0}, b={34:0}, i=4, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={34:0}, b={34:0}, b[i]=131, i=4, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={34:0}, b={34:0}, i=5, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={34:0}, b={34:0}, i=5, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={34:0}, b={34:0}, i=5, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={34:0}, b={34:0}, b[i]=140, i=5, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={34:0}, b={34:0}, i=6, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={34:0}, b={34:0}, i=6, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={34:0}, b={34:0}, i=6, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={34:0}, b={34:0}, b[i]=129, i=6, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={34:0}, b={34:0}, i=7, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={34:0}, b={34:0}, i=7, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={34:0}, b={34:0}, i=7, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={34:0}, b={34:0}, b[i]=148, i=7, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={34:0}, b={34:0}, i=8, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={34:0}, b={34:0}, i=8, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={34:0}, b={34:0}, i=8, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={34:0}, b={34:0}, b[i]=154, i=8, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={34:0}, b={34:0}, i=9, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={34:0}, b={34:0}, i=9, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={34:0}, b={34:0}, i=9, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={34:0}, b={34:0}, b[i]=136, i=9, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={34:0}, b={34:0}, i=10, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={34:0}, b={34:0}, i=10, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={34:0}, b={34:0}, i=10, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={34:0}, b={34:0}, b[i]=149, i=10, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={34:0}, b={34:0}, i=11, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={34:0}, b={34:0}, i=11, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={34:0}, b={34:0}, i=11, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={34:0}, b={34:0}, b[i]=145, i=11, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={34:0}, b={34:0}, i=12, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={34:0}, b={34:0}, i=12, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={34:0}, b={34:0}, i=12, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={34:0}, b={34:0}, b[i]=150, i=12, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={34:0}, b={34:0}, i=13, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={34:0}, b={34:0}, i=13, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={34:0}, b={34:0}, i=13, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={34:0}, b={34:0}, b[i]=156, i=13, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={34:0}, b={34:0}, i=14, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={34:0}, b={34:0}, i=14, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={34:0}, b={34:0}, i=14, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={34:0}, b={34:0}, b[i]=153, i=14, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={34:0}, b={34:0}, i=15, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={34:0}, b={34:0}, i=15, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={34:0}, b={34:0}, i=15, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={34:0}, b={34:0}, b[i]=137, i=15, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={34:0}, b={34:0}, i=16, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={34:0}, b={34:0}, i=16, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={34:0}, b={34:0}, i=16, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={34:0}, b={34:0}, b[i]=139, i=16, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={34:0}, b={34:0}, i=17, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={34:0}, b={34:0}, i=17, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={34:0}, b={34:0}, i=17, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={34:0}, b={34:0}, b[i]=151, i=17, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={34:0}, b={34:0}, i=18, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={34:0}, b={34:0}, i=18, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={34:0}, b={34:0}, i=18, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={34:0}, b={34:0}, b[i]=141, i=18, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={34:0}, b={34:0}, i=19, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={34:0}, b={34:0}, i=19, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={34:0}, b={34:0}, i=19, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={34:0}, b={34:0}, b[i]=133, i=19, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={34:0}, b={34:0}, i=20, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={34:0}, b={34:0}, i=20, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={34:0}, b={34:0}, i=20, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={34:0}, b={34:0}, b[i]=134, i=20, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={34:0}, b={34:0}, i=21, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={34:0}, b={34:0}, i=21, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={34:0}, b={34:0}, i=21, size=21] [L18] EXPR b[i] VAL [\old(size)=21, b={34:0}, b={34:0}, b[i]=138, i=21, size=21] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=21, b={34:0}, b={34:0}, i=22, size=21] [L17] COND FALSE !(i <= size) VAL [\old(size)=21, b={34:0}, b={34:0}, i=22, size=21] [L20] return i; VAL [\old(size)=21, \result=22, b={34:0}, b={34:0}, i=22, size=21] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=22, i=20, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=22, i=20, mask={34:0}] [L26] i++ VAL [b={33:0}, i=21, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=21, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=22, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=22, b={34:0}, b={34:0}, i=0, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={34:0}, b={34:0}, i=0, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={34:0}, b={34:0}, i=0, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={34:0}, b={34:0}, b[i]=147, i=0, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={34:0}, b={34:0}, i=1, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={34:0}, b={34:0}, i=1, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={34:0}, b={34:0}, i=1, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={34:0}, b={34:0}, b[i]=160, i=1, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={34:0}, b={34:0}, i=2, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={34:0}, b={34:0}, i=2, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={34:0}, b={34:0}, i=2, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={34:0}, b={34:0}, b[i]=130, i=2, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={34:0}, b={34:0}, i=3, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={34:0}, b={34:0}, i=3, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={34:0}, b={34:0}, i=3, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={34:0}, b={34:0}, b[i]=132, i=3, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={34:0}, b={34:0}, i=4, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={34:0}, b={34:0}, i=4, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={34:0}, b={34:0}, i=4, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={34:0}, b={34:0}, b[i]=131, i=4, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={34:0}, b={34:0}, i=5, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={34:0}, b={34:0}, i=5, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={34:0}, b={34:0}, i=5, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={34:0}, b={34:0}, b[i]=140, i=5, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={34:0}, b={34:0}, i=6, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={34:0}, b={34:0}, i=6, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={34:0}, b={34:0}, i=6, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={34:0}, b={34:0}, b[i]=129, i=6, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={34:0}, b={34:0}, i=7, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={34:0}, b={34:0}, i=7, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={34:0}, b={34:0}, i=7, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={34:0}, b={34:0}, b[i]=148, i=7, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={34:0}, b={34:0}, i=8, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={34:0}, b={34:0}, i=8, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={34:0}, b={34:0}, i=8, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={34:0}, b={34:0}, b[i]=154, i=8, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={34:0}, b={34:0}, i=9, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={34:0}, b={34:0}, i=9, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={34:0}, b={34:0}, i=9, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={34:0}, b={34:0}, b[i]=136, i=9, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={34:0}, b={34:0}, i=10, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={34:0}, b={34:0}, i=10, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={34:0}, b={34:0}, i=10, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={34:0}, b={34:0}, b[i]=149, i=10, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={34:0}, b={34:0}, i=11, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={34:0}, b={34:0}, i=11, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={34:0}, b={34:0}, i=11, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={34:0}, b={34:0}, b[i]=145, i=11, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={34:0}, b={34:0}, i=12, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={34:0}, b={34:0}, i=12, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={34:0}, b={34:0}, i=12, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={34:0}, b={34:0}, b[i]=150, i=12, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={34:0}, b={34:0}, i=13, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={34:0}, b={34:0}, i=13, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={34:0}, b={34:0}, i=13, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={34:0}, b={34:0}, b[i]=156, i=13, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={34:0}, b={34:0}, i=14, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={34:0}, b={34:0}, i=14, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={34:0}, b={34:0}, i=14, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={34:0}, b={34:0}, b[i]=153, i=14, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={34:0}, b={34:0}, i=15, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={34:0}, b={34:0}, i=15, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={34:0}, b={34:0}, i=15, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={34:0}, b={34:0}, b[i]=137, i=15, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={34:0}, b={34:0}, i=16, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={34:0}, b={34:0}, i=16, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={34:0}, b={34:0}, i=16, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={34:0}, b={34:0}, b[i]=139, i=16, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={34:0}, b={34:0}, i=17, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={34:0}, b={34:0}, i=17, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={34:0}, b={34:0}, i=17, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={34:0}, b={34:0}, b[i]=151, i=17, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={34:0}, b={34:0}, i=18, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={34:0}, b={34:0}, i=18, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={34:0}, b={34:0}, i=18, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={34:0}, b={34:0}, b[i]=141, i=18, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={34:0}, b={34:0}, i=19, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={34:0}, b={34:0}, i=19, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={34:0}, b={34:0}, i=19, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={34:0}, b={34:0}, b[i]=133, i=19, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={34:0}, b={34:0}, i=20, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={34:0}, b={34:0}, i=20, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={34:0}, b={34:0}, i=20, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={34:0}, b={34:0}, b[i]=134, i=20, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={34:0}, b={34:0}, i=21, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={34:0}, b={34:0}, i=21, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={34:0}, b={34:0}, i=21, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={34:0}, b={34:0}, b[i]=138, i=21, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={34:0}, b={34:0}, i=22, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={34:0}, b={34:0}, i=22, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={34:0}, b={34:0}, i=22, size=22] [L18] EXPR b[i] VAL [\old(size)=22, b={34:0}, b={34:0}, b[i]=157, i=22, size=22] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=22, b={34:0}, b={34:0}, i=23, size=22] [L17] COND FALSE !(i <= size) VAL [\old(size)=22, b={34:0}, b={34:0}, i=23, size=22] [L20] return i; VAL [\old(size)=22, \result=23, b={34:0}, b={34:0}, i=23, size=22] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=23, i=21, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=23, i=21, mask={34:0}] [L26] i++ VAL [b={33:0}, i=22, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=22, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=23, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=23, b={34:0}, b={34:0}, i=0, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={34:0}, b={34:0}, i=0, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={34:0}, b={34:0}, i=0, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={34:0}, b={34:0}, b[i]=147, i=0, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={34:0}, b={34:0}, i=1, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={34:0}, b={34:0}, i=1, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={34:0}, b={34:0}, i=1, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={34:0}, b={34:0}, b[i]=160, i=1, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={34:0}, b={34:0}, i=2, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={34:0}, b={34:0}, i=2, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={34:0}, b={34:0}, i=2, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={34:0}, b={34:0}, b[i]=130, i=2, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={34:0}, b={34:0}, i=3, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={34:0}, b={34:0}, i=3, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={34:0}, b={34:0}, i=3, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={34:0}, b={34:0}, b[i]=132, i=3, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={34:0}, b={34:0}, i=4, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={34:0}, b={34:0}, i=4, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={34:0}, b={34:0}, i=4, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={34:0}, b={34:0}, b[i]=131, i=4, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={34:0}, b={34:0}, i=5, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={34:0}, b={34:0}, i=5, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={34:0}, b={34:0}, i=5, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={34:0}, b={34:0}, b[i]=140, i=5, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={34:0}, b={34:0}, i=6, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={34:0}, b={34:0}, i=6, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={34:0}, b={34:0}, i=6, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={34:0}, b={34:0}, b[i]=129, i=6, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={34:0}, b={34:0}, i=7, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={34:0}, b={34:0}, i=7, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={34:0}, b={34:0}, i=7, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={34:0}, b={34:0}, b[i]=148, i=7, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={34:0}, b={34:0}, i=8, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={34:0}, b={34:0}, i=8, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={34:0}, b={34:0}, i=8, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={34:0}, b={34:0}, b[i]=154, i=8, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={34:0}, b={34:0}, i=9, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={34:0}, b={34:0}, i=9, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={34:0}, b={34:0}, i=9, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={34:0}, b={34:0}, b[i]=136, i=9, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={34:0}, b={34:0}, i=10, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={34:0}, b={34:0}, i=10, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={34:0}, b={34:0}, i=10, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={34:0}, b={34:0}, b[i]=149, i=10, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={34:0}, b={34:0}, i=11, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={34:0}, b={34:0}, i=11, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={34:0}, b={34:0}, i=11, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={34:0}, b={34:0}, b[i]=145, i=11, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={34:0}, b={34:0}, i=12, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={34:0}, b={34:0}, i=12, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={34:0}, b={34:0}, i=12, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={34:0}, b={34:0}, b[i]=150, i=12, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={34:0}, b={34:0}, i=13, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={34:0}, b={34:0}, i=13, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={34:0}, b={34:0}, i=13, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={34:0}, b={34:0}, b[i]=156, i=13, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={34:0}, b={34:0}, i=14, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={34:0}, b={34:0}, i=14, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={34:0}, b={34:0}, i=14, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={34:0}, b={34:0}, b[i]=153, i=14, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={34:0}, b={34:0}, i=15, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={34:0}, b={34:0}, i=15, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={34:0}, b={34:0}, i=15, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={34:0}, b={34:0}, b[i]=137, i=15, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={34:0}, b={34:0}, i=16, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={34:0}, b={34:0}, i=16, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={34:0}, b={34:0}, i=16, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={34:0}, b={34:0}, b[i]=139, i=16, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={34:0}, b={34:0}, i=17, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={34:0}, b={34:0}, i=17, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={34:0}, b={34:0}, i=17, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={34:0}, b={34:0}, b[i]=151, i=17, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={34:0}, b={34:0}, i=18, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={34:0}, b={34:0}, i=18, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={34:0}, b={34:0}, i=18, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={34:0}, b={34:0}, b[i]=141, i=18, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={34:0}, b={34:0}, i=19, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={34:0}, b={34:0}, i=19, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={34:0}, b={34:0}, i=19, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={34:0}, b={34:0}, b[i]=133, i=19, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={34:0}, b={34:0}, i=20, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={34:0}, b={34:0}, i=20, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={34:0}, b={34:0}, i=20, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={34:0}, b={34:0}, b[i]=134, i=20, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={34:0}, b={34:0}, i=21, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={34:0}, b={34:0}, i=21, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={34:0}, b={34:0}, i=21, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={34:0}, b={34:0}, b[i]=138, i=21, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={34:0}, b={34:0}, i=22, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={34:0}, b={34:0}, i=22, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={34:0}, b={34:0}, i=22, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={34:0}, b={34:0}, b[i]=157, i=22, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={34:0}, b={34:0}, i=23, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={34:0}, b={34:0}, i=23, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={34:0}, b={34:0}, i=23, size=23] [L18] EXPR b[i] VAL [\old(size)=23, b={34:0}, b={34:0}, b[i]=161, i=23, size=23] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=23, b={34:0}, b={34:0}, i=24, size=23] [L17] COND FALSE !(i <= size) VAL [\old(size)=23, b={34:0}, b={34:0}, i=24, size=23] [L20] return i; VAL [\old(size)=23, \result=24, b={34:0}, b={34:0}, i=24, size=23] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=24, i=22, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=24, i=22, mask={34:0}] [L26] i++ VAL [b={33:0}, i=23, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=23, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=24, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=24, b={34:0}, b={34:0}, i=0, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={34:0}, b={34:0}, i=0, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={34:0}, b={34:0}, i=0, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={34:0}, b={34:0}, b[i]=147, i=0, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={34:0}, b={34:0}, i=1, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={34:0}, b={34:0}, i=1, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={34:0}, b={34:0}, i=1, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={34:0}, b={34:0}, b[i]=160, i=1, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={34:0}, b={34:0}, i=2, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={34:0}, b={34:0}, i=2, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={34:0}, b={34:0}, i=2, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={34:0}, b={34:0}, b[i]=130, i=2, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={34:0}, b={34:0}, i=3, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={34:0}, b={34:0}, i=3, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={34:0}, b={34:0}, i=3, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={34:0}, b={34:0}, b[i]=132, i=3, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={34:0}, b={34:0}, i=4, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={34:0}, b={34:0}, i=4, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={34:0}, b={34:0}, i=4, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={34:0}, b={34:0}, b[i]=131, i=4, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={34:0}, b={34:0}, i=5, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={34:0}, b={34:0}, i=5, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={34:0}, b={34:0}, i=5, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={34:0}, b={34:0}, b[i]=140, i=5, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={34:0}, b={34:0}, i=6, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={34:0}, b={34:0}, i=6, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={34:0}, b={34:0}, i=6, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={34:0}, b={34:0}, b[i]=129, i=6, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={34:0}, b={34:0}, i=7, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={34:0}, b={34:0}, i=7, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={34:0}, b={34:0}, i=7, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={34:0}, b={34:0}, b[i]=148, i=7, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={34:0}, b={34:0}, i=8, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={34:0}, b={34:0}, i=8, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={34:0}, b={34:0}, i=8, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={34:0}, b={34:0}, b[i]=154, i=8, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={34:0}, b={34:0}, i=9, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={34:0}, b={34:0}, i=9, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={34:0}, b={34:0}, i=9, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={34:0}, b={34:0}, b[i]=136, i=9, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={34:0}, b={34:0}, i=10, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={34:0}, b={34:0}, i=10, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={34:0}, b={34:0}, i=10, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={34:0}, b={34:0}, b[i]=149, i=10, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={34:0}, b={34:0}, i=11, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={34:0}, b={34:0}, i=11, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={34:0}, b={34:0}, i=11, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={34:0}, b={34:0}, b[i]=145, i=11, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={34:0}, b={34:0}, i=12, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={34:0}, b={34:0}, i=12, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={34:0}, b={34:0}, i=12, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={34:0}, b={34:0}, b[i]=150, i=12, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={34:0}, b={34:0}, i=13, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={34:0}, b={34:0}, i=13, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={34:0}, b={34:0}, i=13, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={34:0}, b={34:0}, b[i]=156, i=13, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={34:0}, b={34:0}, i=14, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={34:0}, b={34:0}, i=14, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={34:0}, b={34:0}, i=14, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={34:0}, b={34:0}, b[i]=153, i=14, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={34:0}, b={34:0}, i=15, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={34:0}, b={34:0}, i=15, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={34:0}, b={34:0}, i=15, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={34:0}, b={34:0}, b[i]=137, i=15, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={34:0}, b={34:0}, i=16, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={34:0}, b={34:0}, i=16, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={34:0}, b={34:0}, i=16, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={34:0}, b={34:0}, b[i]=139, i=16, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={34:0}, b={34:0}, i=17, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={34:0}, b={34:0}, i=17, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={34:0}, b={34:0}, i=17, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={34:0}, b={34:0}, b[i]=151, i=17, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={34:0}, b={34:0}, i=18, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={34:0}, b={34:0}, i=18, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={34:0}, b={34:0}, i=18, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={34:0}, b={34:0}, b[i]=141, i=18, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={34:0}, b={34:0}, i=19, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={34:0}, b={34:0}, i=19, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={34:0}, b={34:0}, i=19, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={34:0}, b={34:0}, b[i]=133, i=19, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={34:0}, b={34:0}, i=20, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={34:0}, b={34:0}, i=20, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={34:0}, b={34:0}, i=20, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={34:0}, b={34:0}, b[i]=134, i=20, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={34:0}, b={34:0}, i=21, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={34:0}, b={34:0}, i=21, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={34:0}, b={34:0}, i=21, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={34:0}, b={34:0}, b[i]=138, i=21, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={34:0}, b={34:0}, i=22, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={34:0}, b={34:0}, i=22, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={34:0}, b={34:0}, i=22, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={34:0}, b={34:0}, b[i]=157, i=22, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={34:0}, b={34:0}, i=23, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={34:0}, b={34:0}, i=23, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={34:0}, b={34:0}, i=23, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={34:0}, b={34:0}, b[i]=161, i=23, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={34:0}, b={34:0}, i=24, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={34:0}, b={34:0}, i=24, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={34:0}, b={34:0}, i=24, size=24] [L18] EXPR b[i] VAL [\old(size)=24, b={34:0}, b={34:0}, b[i]=143, i=24, size=24] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=24, b={34:0}, b={34:0}, i=25, size=24] [L17] COND FALSE !(i <= size) VAL [\old(size)=24, b={34:0}, b={34:0}, i=25, size=24] [L20] return i; VAL [\old(size)=24, \result=25, b={34:0}, b={34:0}, i=25, size=24] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=25, i=23, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=25, i=23, mask={34:0}] [L26] i++ VAL [b={33:0}, i=24, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=24, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=25, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=25, b={34:0}, b={34:0}, i=0, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={34:0}, b={34:0}, i=0, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={34:0}, b={34:0}, i=0, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={34:0}, b={34:0}, b[i]=147, i=0, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={34:0}, b={34:0}, i=1, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={34:0}, b={34:0}, i=1, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={34:0}, b={34:0}, i=1, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={34:0}, b={34:0}, b[i]=160, i=1, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={34:0}, b={34:0}, i=2, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={34:0}, b={34:0}, i=2, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={34:0}, b={34:0}, i=2, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={34:0}, b={34:0}, b[i]=130, i=2, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={34:0}, b={34:0}, i=3, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={34:0}, b={34:0}, i=3, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={34:0}, b={34:0}, i=3, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={34:0}, b={34:0}, b[i]=132, i=3, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={34:0}, b={34:0}, i=4, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={34:0}, b={34:0}, i=4, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={34:0}, b={34:0}, i=4, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={34:0}, b={34:0}, b[i]=131, i=4, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={34:0}, b={34:0}, i=5, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={34:0}, b={34:0}, i=5, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={34:0}, b={34:0}, i=5, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={34:0}, b={34:0}, b[i]=140, i=5, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={34:0}, b={34:0}, i=6, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={34:0}, b={34:0}, i=6, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={34:0}, b={34:0}, i=6, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={34:0}, b={34:0}, b[i]=129, i=6, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={34:0}, b={34:0}, i=7, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={34:0}, b={34:0}, i=7, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={34:0}, b={34:0}, i=7, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={34:0}, b={34:0}, b[i]=148, i=7, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={34:0}, b={34:0}, i=8, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={34:0}, b={34:0}, i=8, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={34:0}, b={34:0}, i=8, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={34:0}, b={34:0}, b[i]=154, i=8, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={34:0}, b={34:0}, i=9, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={34:0}, b={34:0}, i=9, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={34:0}, b={34:0}, i=9, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={34:0}, b={34:0}, b[i]=136, i=9, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={34:0}, b={34:0}, i=10, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={34:0}, b={34:0}, i=10, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={34:0}, b={34:0}, i=10, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={34:0}, b={34:0}, b[i]=149, i=10, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={34:0}, b={34:0}, i=11, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={34:0}, b={34:0}, i=11, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={34:0}, b={34:0}, i=11, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={34:0}, b={34:0}, b[i]=145, i=11, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={34:0}, b={34:0}, i=12, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={34:0}, b={34:0}, i=12, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={34:0}, b={34:0}, i=12, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={34:0}, b={34:0}, b[i]=150, i=12, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={34:0}, b={34:0}, i=13, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={34:0}, b={34:0}, i=13, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={34:0}, b={34:0}, i=13, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={34:0}, b={34:0}, b[i]=156, i=13, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={34:0}, b={34:0}, i=14, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={34:0}, b={34:0}, i=14, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={34:0}, b={34:0}, i=14, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={34:0}, b={34:0}, b[i]=153, i=14, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={34:0}, b={34:0}, i=15, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={34:0}, b={34:0}, i=15, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={34:0}, b={34:0}, i=15, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={34:0}, b={34:0}, b[i]=137, i=15, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={34:0}, b={34:0}, i=16, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={34:0}, b={34:0}, i=16, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={34:0}, b={34:0}, i=16, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={34:0}, b={34:0}, b[i]=139, i=16, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={34:0}, b={34:0}, i=17, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={34:0}, b={34:0}, i=17, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={34:0}, b={34:0}, i=17, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={34:0}, b={34:0}, b[i]=151, i=17, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={34:0}, b={34:0}, i=18, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={34:0}, b={34:0}, i=18, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={34:0}, b={34:0}, i=18, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={34:0}, b={34:0}, b[i]=141, i=18, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={34:0}, b={34:0}, i=19, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={34:0}, b={34:0}, i=19, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={34:0}, b={34:0}, i=19, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={34:0}, b={34:0}, b[i]=133, i=19, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={34:0}, b={34:0}, i=20, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={34:0}, b={34:0}, i=20, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={34:0}, b={34:0}, i=20, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={34:0}, b={34:0}, b[i]=134, i=20, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={34:0}, b={34:0}, i=21, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={34:0}, b={34:0}, i=21, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={34:0}, b={34:0}, i=21, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={34:0}, b={34:0}, b[i]=138, i=21, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={34:0}, b={34:0}, i=22, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={34:0}, b={34:0}, i=22, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={34:0}, b={34:0}, i=22, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={34:0}, b={34:0}, b[i]=157, i=22, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={34:0}, b={34:0}, i=23, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={34:0}, b={34:0}, i=23, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={34:0}, b={34:0}, i=23, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={34:0}, b={34:0}, b[i]=161, i=23, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={34:0}, b={34:0}, i=24, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={34:0}, b={34:0}, i=24, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={34:0}, b={34:0}, i=24, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={34:0}, b={34:0}, b[i]=143, i=24, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={34:0}, b={34:0}, i=25, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={34:0}, b={34:0}, i=25, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={34:0}, b={34:0}, i=25, size=25] [L18] EXPR b[i] VAL [\old(size)=25, b={34:0}, b={34:0}, b[i]=152, i=25, size=25] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=25, b={34:0}, b={34:0}, i=26, size=25] [L17] COND FALSE !(i <= size) VAL [\old(size)=25, b={34:0}, b={34:0}, i=26, size=25] [L20] return i; VAL [\old(size)=25, \result=26, b={34:0}, b={34:0}, i=26, size=25] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=26, i=24, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=26, i=24, mask={34:0}] [L26] i++ VAL [b={33:0}, i=25, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=25, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=26, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=26, b={34:0}, b={34:0}, i=0, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={34:0}, b={34:0}, i=0, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={34:0}, b={34:0}, i=0, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={34:0}, b={34:0}, b[i]=147, i=0, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={34:0}, b={34:0}, i=1, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={34:0}, b={34:0}, i=1, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={34:0}, b={34:0}, i=1, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={34:0}, b={34:0}, b[i]=160, i=1, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={34:0}, b={34:0}, i=2, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={34:0}, b={34:0}, i=2, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={34:0}, b={34:0}, i=2, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={34:0}, b={34:0}, b[i]=130, i=2, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={34:0}, b={34:0}, i=3, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={34:0}, b={34:0}, i=3, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={34:0}, b={34:0}, i=3, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={34:0}, b={34:0}, b[i]=132, i=3, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={34:0}, b={34:0}, i=4, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={34:0}, b={34:0}, i=4, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={34:0}, b={34:0}, i=4, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={34:0}, b={34:0}, b[i]=131, i=4, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={34:0}, b={34:0}, i=5, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={34:0}, b={34:0}, i=5, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={34:0}, b={34:0}, i=5, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={34:0}, b={34:0}, b[i]=140, i=5, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={34:0}, b={34:0}, i=6, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={34:0}, b={34:0}, i=6, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={34:0}, b={34:0}, i=6, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={34:0}, b={34:0}, b[i]=129, i=6, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={34:0}, b={34:0}, i=7, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={34:0}, b={34:0}, i=7, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={34:0}, b={34:0}, i=7, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={34:0}, b={34:0}, b[i]=148, i=7, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={34:0}, b={34:0}, i=8, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={34:0}, b={34:0}, i=8, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={34:0}, b={34:0}, i=8, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={34:0}, b={34:0}, b[i]=154, i=8, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={34:0}, b={34:0}, i=9, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={34:0}, b={34:0}, i=9, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={34:0}, b={34:0}, i=9, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={34:0}, b={34:0}, b[i]=136, i=9, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={34:0}, b={34:0}, i=10, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={34:0}, b={34:0}, i=10, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={34:0}, b={34:0}, i=10, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={34:0}, b={34:0}, b[i]=149, i=10, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={34:0}, b={34:0}, i=11, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={34:0}, b={34:0}, i=11, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={34:0}, b={34:0}, i=11, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={34:0}, b={34:0}, b[i]=145, i=11, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={34:0}, b={34:0}, i=12, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={34:0}, b={34:0}, i=12, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={34:0}, b={34:0}, i=12, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={34:0}, b={34:0}, b[i]=150, i=12, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={34:0}, b={34:0}, i=13, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={34:0}, b={34:0}, i=13, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={34:0}, b={34:0}, i=13, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={34:0}, b={34:0}, b[i]=156, i=13, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={34:0}, b={34:0}, i=14, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={34:0}, b={34:0}, i=14, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={34:0}, b={34:0}, i=14, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={34:0}, b={34:0}, b[i]=153, i=14, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={34:0}, b={34:0}, i=15, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={34:0}, b={34:0}, i=15, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={34:0}, b={34:0}, i=15, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={34:0}, b={34:0}, b[i]=137, i=15, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={34:0}, b={34:0}, i=16, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={34:0}, b={34:0}, i=16, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={34:0}, b={34:0}, i=16, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={34:0}, b={34:0}, b[i]=139, i=16, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={34:0}, b={34:0}, i=17, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={34:0}, b={34:0}, i=17, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={34:0}, b={34:0}, i=17, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={34:0}, b={34:0}, b[i]=151, i=17, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={34:0}, b={34:0}, i=18, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={34:0}, b={34:0}, i=18, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={34:0}, b={34:0}, i=18, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={34:0}, b={34:0}, b[i]=141, i=18, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={34:0}, b={34:0}, i=19, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={34:0}, b={34:0}, i=19, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={34:0}, b={34:0}, i=19, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={34:0}, b={34:0}, b[i]=133, i=19, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={34:0}, b={34:0}, i=20, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={34:0}, b={34:0}, i=20, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={34:0}, b={34:0}, i=20, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={34:0}, b={34:0}, b[i]=134, i=20, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={34:0}, b={34:0}, i=21, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={34:0}, b={34:0}, i=21, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={34:0}, b={34:0}, i=21, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={34:0}, b={34:0}, b[i]=138, i=21, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={34:0}, b={34:0}, i=22, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={34:0}, b={34:0}, i=22, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={34:0}, b={34:0}, i=22, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={34:0}, b={34:0}, b[i]=157, i=22, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={34:0}, b={34:0}, i=23, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={34:0}, b={34:0}, i=23, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={34:0}, b={34:0}, i=23, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={34:0}, b={34:0}, b[i]=161, i=23, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={34:0}, b={34:0}, i=24, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={34:0}, b={34:0}, i=24, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={34:0}, b={34:0}, i=24, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={34:0}, b={34:0}, b[i]=143, i=24, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={34:0}, b={34:0}, i=25, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={34:0}, b={34:0}, i=25, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={34:0}, b={34:0}, i=25, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={34:0}, b={34:0}, b[i]=152, i=25, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={34:0}, b={34:0}, i=26, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={34:0}, b={34:0}, i=26, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={34:0}, b={34:0}, i=26, size=26] [L18] EXPR b[i] VAL [\old(size)=26, b={34:0}, b={34:0}, b[i]=144, i=26, size=26] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=26, b={34:0}, b={34:0}, i=27, size=26] [L17] COND FALSE !(i <= size) VAL [\old(size)=26, b={34:0}, b={34:0}, i=27, size=26] [L20] return i; VAL [\old(size)=26, \result=27, b={34:0}, b={34:0}, i=27, size=26] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=27, i=25, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=27, i=25, mask={34:0}] [L26] i++ VAL [b={33:0}, i=26, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=26, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=27, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=27, b={34:0}, b={34:0}, i=0, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={34:0}, b={34:0}, i=0, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={34:0}, b={34:0}, i=0, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={34:0}, b={34:0}, b[i]=147, i=0, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={34:0}, b={34:0}, i=1, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={34:0}, b={34:0}, i=1, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={34:0}, b={34:0}, i=1, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={34:0}, b={34:0}, b[i]=160, i=1, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={34:0}, b={34:0}, i=2, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={34:0}, b={34:0}, i=2, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={34:0}, b={34:0}, i=2, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={34:0}, b={34:0}, b[i]=130, i=2, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={34:0}, b={34:0}, i=3, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={34:0}, b={34:0}, i=3, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={34:0}, b={34:0}, i=3, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={34:0}, b={34:0}, b[i]=132, i=3, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={34:0}, b={34:0}, i=4, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={34:0}, b={34:0}, i=4, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={34:0}, b={34:0}, i=4, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={34:0}, b={34:0}, b[i]=131, i=4, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={34:0}, b={34:0}, i=5, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={34:0}, b={34:0}, i=5, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={34:0}, b={34:0}, i=5, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={34:0}, b={34:0}, b[i]=140, i=5, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={34:0}, b={34:0}, i=6, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={34:0}, b={34:0}, i=6, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={34:0}, b={34:0}, i=6, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={34:0}, b={34:0}, b[i]=129, i=6, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={34:0}, b={34:0}, i=7, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={34:0}, b={34:0}, i=7, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={34:0}, b={34:0}, i=7, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={34:0}, b={34:0}, b[i]=148, i=7, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={34:0}, b={34:0}, i=8, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={34:0}, b={34:0}, i=8, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={34:0}, b={34:0}, i=8, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={34:0}, b={34:0}, b[i]=154, i=8, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={34:0}, b={34:0}, i=9, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={34:0}, b={34:0}, i=9, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={34:0}, b={34:0}, i=9, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={34:0}, b={34:0}, b[i]=136, i=9, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={34:0}, b={34:0}, i=10, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={34:0}, b={34:0}, i=10, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={34:0}, b={34:0}, i=10, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={34:0}, b={34:0}, b[i]=149, i=10, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={34:0}, b={34:0}, i=11, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={34:0}, b={34:0}, i=11, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={34:0}, b={34:0}, i=11, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={34:0}, b={34:0}, b[i]=145, i=11, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={34:0}, b={34:0}, i=12, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={34:0}, b={34:0}, i=12, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={34:0}, b={34:0}, i=12, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={34:0}, b={34:0}, b[i]=150, i=12, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={34:0}, b={34:0}, i=13, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={34:0}, b={34:0}, i=13, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={34:0}, b={34:0}, i=13, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={34:0}, b={34:0}, b[i]=156, i=13, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={34:0}, b={34:0}, i=14, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={34:0}, b={34:0}, i=14, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={34:0}, b={34:0}, i=14, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={34:0}, b={34:0}, b[i]=153, i=14, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={34:0}, b={34:0}, i=15, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={34:0}, b={34:0}, i=15, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={34:0}, b={34:0}, i=15, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={34:0}, b={34:0}, b[i]=137, i=15, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={34:0}, b={34:0}, i=16, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={34:0}, b={34:0}, i=16, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={34:0}, b={34:0}, i=16, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={34:0}, b={34:0}, b[i]=139, i=16, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={34:0}, b={34:0}, i=17, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={34:0}, b={34:0}, i=17, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={34:0}, b={34:0}, i=17, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={34:0}, b={34:0}, b[i]=151, i=17, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={34:0}, b={34:0}, i=18, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={34:0}, b={34:0}, i=18, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={34:0}, b={34:0}, i=18, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={34:0}, b={34:0}, b[i]=141, i=18, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={34:0}, b={34:0}, i=19, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={34:0}, b={34:0}, i=19, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={34:0}, b={34:0}, i=19, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={34:0}, b={34:0}, b[i]=133, i=19, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={34:0}, b={34:0}, i=20, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={34:0}, b={34:0}, i=20, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={34:0}, b={34:0}, i=20, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={34:0}, b={34:0}, b[i]=134, i=20, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={34:0}, b={34:0}, i=21, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={34:0}, b={34:0}, i=21, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={34:0}, b={34:0}, i=21, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={34:0}, b={34:0}, b[i]=138, i=21, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={34:0}, b={34:0}, i=22, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={34:0}, b={34:0}, i=22, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={34:0}, b={34:0}, i=22, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={34:0}, b={34:0}, b[i]=157, i=22, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={34:0}, b={34:0}, i=23, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={34:0}, b={34:0}, i=23, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={34:0}, b={34:0}, i=23, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={34:0}, b={34:0}, b[i]=161, i=23, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={34:0}, b={34:0}, i=24, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={34:0}, b={34:0}, i=24, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={34:0}, b={34:0}, i=24, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={34:0}, b={34:0}, b[i]=143, i=24, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={34:0}, b={34:0}, i=25, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={34:0}, b={34:0}, i=25, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={34:0}, b={34:0}, i=25, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={34:0}, b={34:0}, b[i]=152, i=25, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={34:0}, b={34:0}, i=26, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={34:0}, b={34:0}, i=26, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={34:0}, b={34:0}, i=26, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={34:0}, b={34:0}, b[i]=144, i=26, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={34:0}, b={34:0}, i=27, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={34:0}, b={34:0}, i=27, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={34:0}, b={34:0}, i=27, size=27] [L18] EXPR b[i] VAL [\old(size)=27, b={34:0}, b={34:0}, b[i]=162, i=27, size=27] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=27, b={34:0}, b={34:0}, i=28, size=27] [L17] COND FALSE !(i <= size) VAL [\old(size)=27, b={34:0}, b={34:0}, i=28, size=27] [L20] return i; VAL [\old(size)=27, \result=28, b={34:0}, b={34:0}, i=28, size=27] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=28, i=26, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=28, i=26, mask={34:0}] [L26] i++ VAL [b={33:0}, i=27, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=27, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=28, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=28, b={34:0}, b={34:0}, i=0, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={34:0}, b={34:0}, i=0, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={34:0}, b={34:0}, i=0, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={34:0}, b={34:0}, b[i]=147, i=0, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={34:0}, b={34:0}, i=1, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={34:0}, b={34:0}, i=1, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={34:0}, b={34:0}, i=1, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={34:0}, b={34:0}, b[i]=160, i=1, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={34:0}, b={34:0}, i=2, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={34:0}, b={34:0}, i=2, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={34:0}, b={34:0}, i=2, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={34:0}, b={34:0}, b[i]=130, i=2, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={34:0}, b={34:0}, i=3, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={34:0}, b={34:0}, i=3, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={34:0}, b={34:0}, i=3, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={34:0}, b={34:0}, b[i]=132, i=3, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={34:0}, b={34:0}, i=4, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={34:0}, b={34:0}, i=4, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={34:0}, b={34:0}, i=4, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={34:0}, b={34:0}, b[i]=131, i=4, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={34:0}, b={34:0}, i=5, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={34:0}, b={34:0}, i=5, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={34:0}, b={34:0}, i=5, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={34:0}, b={34:0}, b[i]=140, i=5, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={34:0}, b={34:0}, i=6, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={34:0}, b={34:0}, i=6, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={34:0}, b={34:0}, i=6, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={34:0}, b={34:0}, b[i]=129, i=6, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={34:0}, b={34:0}, i=7, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={34:0}, b={34:0}, i=7, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={34:0}, b={34:0}, i=7, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={34:0}, b={34:0}, b[i]=148, i=7, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={34:0}, b={34:0}, i=8, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={34:0}, b={34:0}, i=8, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={34:0}, b={34:0}, i=8, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={34:0}, b={34:0}, b[i]=154, i=8, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={34:0}, b={34:0}, i=9, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={34:0}, b={34:0}, i=9, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={34:0}, b={34:0}, i=9, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={34:0}, b={34:0}, b[i]=136, i=9, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={34:0}, b={34:0}, i=10, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={34:0}, b={34:0}, i=10, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={34:0}, b={34:0}, i=10, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={34:0}, b={34:0}, b[i]=149, i=10, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={34:0}, b={34:0}, i=11, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={34:0}, b={34:0}, i=11, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={34:0}, b={34:0}, i=11, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={34:0}, b={34:0}, b[i]=145, i=11, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={34:0}, b={34:0}, i=12, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={34:0}, b={34:0}, i=12, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={34:0}, b={34:0}, i=12, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={34:0}, b={34:0}, b[i]=150, i=12, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={34:0}, b={34:0}, i=13, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={34:0}, b={34:0}, i=13, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={34:0}, b={34:0}, i=13, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={34:0}, b={34:0}, b[i]=156, i=13, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={34:0}, b={34:0}, i=14, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={34:0}, b={34:0}, i=14, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={34:0}, b={34:0}, i=14, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={34:0}, b={34:0}, b[i]=153, i=14, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={34:0}, b={34:0}, i=15, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={34:0}, b={34:0}, i=15, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={34:0}, b={34:0}, i=15, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={34:0}, b={34:0}, b[i]=137, i=15, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={34:0}, b={34:0}, i=16, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={34:0}, b={34:0}, i=16, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={34:0}, b={34:0}, i=16, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={34:0}, b={34:0}, b[i]=139, i=16, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={34:0}, b={34:0}, i=17, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={34:0}, b={34:0}, i=17, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={34:0}, b={34:0}, i=17, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={34:0}, b={34:0}, b[i]=151, i=17, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={34:0}, b={34:0}, i=18, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={34:0}, b={34:0}, i=18, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={34:0}, b={34:0}, i=18, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={34:0}, b={34:0}, b[i]=141, i=18, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={34:0}, b={34:0}, i=19, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={34:0}, b={34:0}, i=19, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={34:0}, b={34:0}, i=19, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={34:0}, b={34:0}, b[i]=133, i=19, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={34:0}, b={34:0}, i=20, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={34:0}, b={34:0}, i=20, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={34:0}, b={34:0}, i=20, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={34:0}, b={34:0}, b[i]=134, i=20, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={34:0}, b={34:0}, i=21, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={34:0}, b={34:0}, i=21, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={34:0}, b={34:0}, i=21, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={34:0}, b={34:0}, b[i]=138, i=21, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={34:0}, b={34:0}, i=22, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={34:0}, b={34:0}, i=22, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={34:0}, b={34:0}, i=22, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={34:0}, b={34:0}, b[i]=157, i=22, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={34:0}, b={34:0}, i=23, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={34:0}, b={34:0}, i=23, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={34:0}, b={34:0}, i=23, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={34:0}, b={34:0}, b[i]=161, i=23, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={34:0}, b={34:0}, i=24, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={34:0}, b={34:0}, i=24, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={34:0}, b={34:0}, i=24, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={34:0}, b={34:0}, b[i]=143, i=24, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={34:0}, b={34:0}, i=25, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={34:0}, b={34:0}, i=25, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={34:0}, b={34:0}, i=25, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={34:0}, b={34:0}, b[i]=152, i=25, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={34:0}, b={34:0}, i=26, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={34:0}, b={34:0}, i=26, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={34:0}, b={34:0}, i=26, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={34:0}, b={34:0}, b[i]=144, i=26, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={34:0}, b={34:0}, i=27, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={34:0}, b={34:0}, i=27, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={34:0}, b={34:0}, i=27, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={34:0}, b={34:0}, b[i]=162, i=27, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={34:0}, b={34:0}, i=28, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={34:0}, b={34:0}, i=28, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={34:0}, b={34:0}, i=28, size=28] [L18] EXPR b[i] VAL [\old(size)=28, b={34:0}, b={34:0}, b[i]=158, i=28, size=28] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=28, b={34:0}, b={34:0}, i=29, size=28] [L17] COND FALSE !(i <= size) VAL [\old(size)=28, b={34:0}, b={34:0}, i=29, size=28] [L20] return i; VAL [\old(size)=28, \result=29, b={34:0}, b={34:0}, i=29, size=28] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=29, i=27, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=29, i=27, mask={34:0}] [L26] i++ VAL [b={33:0}, i=28, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=28, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=29, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=29, b={34:0}, b={34:0}, i=0, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={34:0}, b={34:0}, i=0, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={34:0}, b={34:0}, i=0, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={34:0}, b={34:0}, b[i]=147, i=0, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={34:0}, b={34:0}, i=1, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={34:0}, b={34:0}, i=1, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={34:0}, b={34:0}, i=1, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={34:0}, b={34:0}, b[i]=160, i=1, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={34:0}, b={34:0}, i=2, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={34:0}, b={34:0}, i=2, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={34:0}, b={34:0}, i=2, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={34:0}, b={34:0}, b[i]=130, i=2, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={34:0}, b={34:0}, i=3, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={34:0}, b={34:0}, i=3, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={34:0}, b={34:0}, i=3, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={34:0}, b={34:0}, b[i]=132, i=3, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={34:0}, b={34:0}, i=4, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={34:0}, b={34:0}, i=4, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={34:0}, b={34:0}, i=4, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={34:0}, b={34:0}, b[i]=131, i=4, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={34:0}, b={34:0}, i=5, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={34:0}, b={34:0}, i=5, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={34:0}, b={34:0}, i=5, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={34:0}, b={34:0}, b[i]=140, i=5, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={34:0}, b={34:0}, i=6, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={34:0}, b={34:0}, i=6, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={34:0}, b={34:0}, i=6, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={34:0}, b={34:0}, b[i]=129, i=6, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={34:0}, b={34:0}, i=7, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={34:0}, b={34:0}, i=7, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={34:0}, b={34:0}, i=7, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={34:0}, b={34:0}, b[i]=148, i=7, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={34:0}, b={34:0}, i=8, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={34:0}, b={34:0}, i=8, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={34:0}, b={34:0}, i=8, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={34:0}, b={34:0}, b[i]=154, i=8, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={34:0}, b={34:0}, i=9, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={34:0}, b={34:0}, i=9, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={34:0}, b={34:0}, i=9, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={34:0}, b={34:0}, b[i]=136, i=9, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={34:0}, b={34:0}, i=10, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={34:0}, b={34:0}, i=10, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={34:0}, b={34:0}, i=10, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={34:0}, b={34:0}, b[i]=149, i=10, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={34:0}, b={34:0}, i=11, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={34:0}, b={34:0}, i=11, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={34:0}, b={34:0}, i=11, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={34:0}, b={34:0}, b[i]=145, i=11, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={34:0}, b={34:0}, i=12, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={34:0}, b={34:0}, i=12, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={34:0}, b={34:0}, i=12, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={34:0}, b={34:0}, b[i]=150, i=12, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={34:0}, b={34:0}, i=13, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={34:0}, b={34:0}, i=13, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={34:0}, b={34:0}, i=13, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={34:0}, b={34:0}, b[i]=156, i=13, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={34:0}, b={34:0}, i=14, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={34:0}, b={34:0}, i=14, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={34:0}, b={34:0}, i=14, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={34:0}, b={34:0}, b[i]=153, i=14, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={34:0}, b={34:0}, i=15, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={34:0}, b={34:0}, i=15, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={34:0}, b={34:0}, i=15, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={34:0}, b={34:0}, b[i]=137, i=15, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={34:0}, b={34:0}, i=16, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={34:0}, b={34:0}, i=16, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={34:0}, b={34:0}, i=16, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={34:0}, b={34:0}, b[i]=139, i=16, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={34:0}, b={34:0}, i=17, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={34:0}, b={34:0}, i=17, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={34:0}, b={34:0}, i=17, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={34:0}, b={34:0}, b[i]=151, i=17, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={34:0}, b={34:0}, i=18, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={34:0}, b={34:0}, i=18, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={34:0}, b={34:0}, i=18, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={34:0}, b={34:0}, b[i]=141, i=18, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={34:0}, b={34:0}, i=19, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={34:0}, b={34:0}, i=19, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={34:0}, b={34:0}, i=19, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={34:0}, b={34:0}, b[i]=133, i=19, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={34:0}, b={34:0}, i=20, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={34:0}, b={34:0}, i=20, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={34:0}, b={34:0}, i=20, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={34:0}, b={34:0}, b[i]=134, i=20, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={34:0}, b={34:0}, i=21, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={34:0}, b={34:0}, i=21, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={34:0}, b={34:0}, i=21, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={34:0}, b={34:0}, b[i]=138, i=21, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={34:0}, b={34:0}, i=22, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={34:0}, b={34:0}, i=22, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={34:0}, b={34:0}, i=22, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={34:0}, b={34:0}, b[i]=157, i=22, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={34:0}, b={34:0}, i=23, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={34:0}, b={34:0}, i=23, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={34:0}, b={34:0}, i=23, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={34:0}, b={34:0}, b[i]=161, i=23, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={34:0}, b={34:0}, i=24, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={34:0}, b={34:0}, i=24, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={34:0}, b={34:0}, i=24, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={34:0}, b={34:0}, b[i]=143, i=24, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={34:0}, b={34:0}, i=25, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={34:0}, b={34:0}, i=25, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={34:0}, b={34:0}, i=25, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={34:0}, b={34:0}, b[i]=152, i=25, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={34:0}, b={34:0}, i=26, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={34:0}, b={34:0}, i=26, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={34:0}, b={34:0}, i=26, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={34:0}, b={34:0}, b[i]=144, i=26, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={34:0}, b={34:0}, i=27, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={34:0}, b={34:0}, i=27, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={34:0}, b={34:0}, i=27, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={34:0}, b={34:0}, b[i]=162, i=27, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={34:0}, b={34:0}, i=28, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={34:0}, b={34:0}, i=28, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={34:0}, b={34:0}, i=28, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={34:0}, b={34:0}, b[i]=158, i=28, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={34:0}, b={34:0}, i=29, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={34:0}, b={34:0}, i=29, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={34:0}, b={34:0}, i=29, size=29] [L18] EXPR b[i] VAL [\old(size)=29, b={34:0}, b={34:0}, b[i]=142, i=29, size=29] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=29, b={34:0}, b={34:0}, i=30, size=29] [L17] COND FALSE !(i <= size) VAL [\old(size)=29, b={34:0}, b={34:0}, i=30, size=29] [L20] return i; VAL [\old(size)=29, \result=30, b={34:0}, b={34:0}, i=30, size=29] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=30, i=28, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=30, i=28, mask={34:0}] [L26] i++ VAL [b={33:0}, i=29, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=29, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=30, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=30, b={34:0}, b={34:0}, i=0, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=0, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=0, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=147, i=0, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=1, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=1, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=1, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=160, i=1, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=2, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=2, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=2, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=130, i=2, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=3, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=3, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=3, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=132, i=3, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=4, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=4, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=4, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=131, i=4, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=5, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=5, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=5, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=140, i=5, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=6, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=6, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=6, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=129, i=6, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=7, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=7, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=7, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=148, i=7, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=8, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=8, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=8, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=154, i=8, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=9, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=9, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=9, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=136, i=9, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=10, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=10, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=10, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=149, i=10, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=11, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=11, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=11, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=145, i=11, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=12, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=12, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=12, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=150, i=12, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=13, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=13, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=13, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=156, i=13, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=14, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=14, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=14, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=153, i=14, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=15, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=15, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=15, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=137, i=15, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=16, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=16, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=16, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=139, i=16, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=17, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=17, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=17, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=151, i=17, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=18, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=18, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=18, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=141, i=18, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=19, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=19, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=19, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=133, i=19, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=20, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=20, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=20, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=134, i=20, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=21, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=21, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=21, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=138, i=21, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=22, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=22, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=22, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=157, i=22, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=23, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=23, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=23, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=161, i=23, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=24, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=24, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=24, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=143, i=24, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=25, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=25, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=25, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=152, i=25, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=26, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=26, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=26, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=144, i=26, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=27, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=27, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=27, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=162, i=27, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=28, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=28, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=28, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=158, i=28, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=29, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=29, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=29, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=142, i=29, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=30, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={34:0}, b={34:0}, i=30, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={34:0}, b={34:0}, i=30, size=30] [L18] EXPR b[i] VAL [\old(size)=30, b={34:0}, b={34:0}, b[i]=159, i=30, size=30] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=30, b={34:0}, b={34:0}, i=31, size=30] [L17] COND FALSE !(i <= size) VAL [\old(size)=30, b={34:0}, b={34:0}, i=31, size=30] [L20] return i; VAL [\old(size)=30, \result=31, b={34:0}, b={34:0}, i=31, size=30] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=31, i=29, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=31, i=29, mask={34:0}] [L26] i++ VAL [b={33:0}, i=30, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=30, mask={34:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=31, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=31, b={34:0}, b={34:0}, i=0, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=0, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=0, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=147, i=0, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=1, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=1, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=1, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=160, i=1, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=2, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=2, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=2, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=130, i=2, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=3, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=3, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=3, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=132, i=3, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=4, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=4, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=4, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=131, i=4, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=5, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=5, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=5, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=140, i=5, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=6, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=6, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=6, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=129, i=6, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=7, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=7, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=7, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=148, i=7, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=8, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=8, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=8, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=154, i=8, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=9, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=9, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=9, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=136, i=9, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=10, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=10, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=10, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=149, i=10, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=11, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=11, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=11, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=145, i=11, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=12, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=12, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=12, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=150, i=12, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=13, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=13, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=13, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=156, i=13, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=14, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=14, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=14, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=153, i=14, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=15, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=15, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=15, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=137, i=15, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=16, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=16, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=16, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=139, i=16, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=17, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=17, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=17, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=151, i=17, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=18, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=18, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=18, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=141, i=18, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=19, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=19, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=19, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=133, i=19, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=20, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=20, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=20, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=134, i=20, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=21, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=21, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=21, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=138, i=21, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=22, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=22, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=22, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=157, i=22, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=23, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=23, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=23, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=161, i=23, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=24, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=24, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=24, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=143, i=24, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=25, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=25, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=25, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=152, i=25, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=26, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=26, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=26, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=144, i=26, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=27, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=27, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=27, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=162, i=27, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=28, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=28, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=28, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=158, i=28, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=29, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=29, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=29, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=142, i=29, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=30, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=30, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=30, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=159, i=30, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=31, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={34:0}, b={34:0}, i=31, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={34:0}, b={34:0}, i=31, size=31] [L18] EXPR b[i] VAL [\old(size)=31, b={34:0}, b={34:0}, b[i]=135, i=31, size=31] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=31, b={34:0}, b={34:0}, i=32, size=31] [L17] COND FALSE !(i <= size) VAL [\old(size)=31, b={34:0}, b={34:0}, i=32, size=31] [L20] return i; VAL [\old(size)=31, \result=32, b={34:0}, b={34:0}, i=32, size=31] [L27] RET, EXPR foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=32, i=30, mask={34:0}] [L27] b[i] = foo(mask, i + 1) VAL [b={33:0}, foo(mask, i + 1)=32, i=30, mask={34:0}] [L26] i++ VAL [b={33:0}, i=31, mask={34:0}] [L26] COND TRUE i < sizeof(mask) VAL [b={33:0}, i=31, mask={34:0}] [L27] CALL foo(mask, i + 1) VAL [\old(size)=32, b={34:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=32, b={34:0}, b={34:0}, i=0, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=0, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=0, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=147, i=0, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=1, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=1, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=1, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=160, i=1, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=2, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=2, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=2, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=130, i=2, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=3, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=3, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=3, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=132, i=3, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=4, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=4, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=4, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=131, i=4, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=5, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=5, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=5, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=140, i=5, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=6, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=6, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=6, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=129, i=6, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=7, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=7, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=7, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=148, i=7, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=8, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=8, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=8, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=154, i=8, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=9, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=9, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=9, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=136, i=9, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=10, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=10, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=10, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=149, i=10, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=11, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=11, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=11, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=145, i=11, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=12, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=12, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=12, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=150, i=12, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=13, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=13, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=13, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=156, i=13, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=14, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=14, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=14, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=153, i=14, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=15, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=15, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=15, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=137, i=15, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=16, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=16, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=16, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=139, i=16, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=17, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=17, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=17, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=151, i=17, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=18, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=18, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=18, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=141, i=18, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=19, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=19, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=19, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=133, i=19, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=20, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=20, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=20, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=134, i=20, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=21, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=21, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=21, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=138, i=21, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=22, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=22, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=22, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=157, i=22, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=23, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=23, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=23, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=161, i=23, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=24, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=24, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=24, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=143, i=24, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=25, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=25, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=25, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=152, i=25, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=26, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=26, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=26, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=144, i=26, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=27, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=27, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=27, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=162, i=27, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=28, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=28, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=28, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=158, i=28, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=29, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=29, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=29, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=142, i=29, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=30, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=30, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=30, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=159, i=30, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=31, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=31, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=31, size=32] [L18] EXPR b[i] VAL [\old(size)=32, b={34:0}, b={34:0}, b[i]=135, i=31, size=32] [L18] a[i] = b[i] [L17] i++ VAL [\old(size)=32, b={34:0}, b={34:0}, i=32, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={34:0}, b={34:0}, i=32, size=32] [L18] a[i] VAL [\old(size)=32, b={34:0}, b={34:0}, i=32, size=32] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 40 locations, 8 error locations. Result: UNSAFE, OverallTime: 738.4s, OverallIterations: 74, TraceHistogramMax: 560, AutomataDifference: 245.1s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 2756 SDtfs, 53041 SDslu, 25194 SDs, 0 SdLazy, 199175 SolverSat, 9236 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 105.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 80413 GetRequests, 74201 SyntacticMatches, 45 SemanticMatches, 6167 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 194502 ImplicationChecksByTransitivity, 173.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=3949occurred in iteration=73, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 1.1s AutomataMinimizationTime, 73 MinimizatonAttempts, 21395 StatesRemovedByMinimization, 68 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 4.3s SsaConstructionTime, 264.6s SatisfiabilityAnalysisTime, 138.2s InterpolantComputationTime, 149901 NumberOfCodeBlocks, 138615 NumberOfCodeBlocksAsserted, 1000 NumberOfCheckSat, 146615 ConstructedInterpolants, 320 QuantifiedInterpolants, 398158109 SizeOfPredicates, 136 NumberOfNonLiveVariables, 156934 ConjunctsInSsa, 2029 ConjunctsInUnsatCore, 139 InterpolantComputations, 10 PerfectInterpolantSequences, 21336974/21564779 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...