./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/kundu1.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_c090ccfd-27a8-4b2b-8f26-42053f434841/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_c090ccfd-27a8-4b2b-8f26-42053f434841/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_c090ccfd-27a8-4b2b-8f26-42053f434841/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_c090ccfd-27a8-4b2b-8f26-42053f434841/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/kundu1.cil.c -s /tmp/vcloud-vcloud-master/worker/run_dir_c090ccfd-27a8-4b2b-8f26-42053f434841/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_c090ccfd-27a8-4b2b-8f26-42053f434841/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 532163d21d7e473fbfa4a073427e9fd2a45c7337 ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 14:48:15,957 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 14:48:15,958 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 14:48:15,967 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 14:48:15,967 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 14:48:15,968 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 14:48:15,969 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 14:48:15,971 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 14:48:15,973 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 14:48:15,973 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 14:48:15,974 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 14:48:15,975 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 14:48:15,975 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 14:48:15,976 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 14:48:15,976 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 14:48:15,977 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 14:48:15,978 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 14:48:15,979 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 14:48:15,980 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 14:48:15,982 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 14:48:15,983 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 14:48:15,984 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 14:48:15,985 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 14:48:15,985 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 14:48:15,987 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 14:48:15,987 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 14:48:15,987 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 14:48:15,988 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 14:48:15,988 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 14:48:15,989 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 14:48:15,989 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 14:48:15,989 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 14:48:15,990 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 14:48:15,990 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 14:48:15,991 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 14:48:15,991 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 14:48:15,992 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 14:48:15,992 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 14:48:15,992 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 14:48:15,993 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 14:48:15,994 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 14:48:15,994 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_c090ccfd-27a8-4b2b-8f26-42053f434841/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 14:48:16,007 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 14:48:16,007 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 14:48:16,008 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 14:48:16,008 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 14:48:16,008 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 14:48:16,008 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 14:48:16,008 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 14:48:16,008 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 14:48:16,008 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 14:48:16,009 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 14:48:16,009 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 14:48:16,009 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 14:48:16,009 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 14:48:16,009 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 14:48:16,010 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 14:48:16,010 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 14:48:16,010 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 14:48:16,010 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 14:48:16,010 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 14:48:16,010 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 14:48:16,010 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 14:48:16,010 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 14:48:16,011 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 14:48:16,011 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 14:48:16,011 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 14:48:16,011 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 14:48:16,011 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 14:48:16,011 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 14:48:16,011 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 14:48:16,011 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_c090ccfd-27a8-4b2b-8f26-42053f434841/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 532163d21d7e473fbfa4a073427e9fd2a45c7337 [2019-12-07 14:48:16,119 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 14:48:16,129 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 14:48:16,132 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 14:48:16,133 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 14:48:16,133 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 14:48:16,134 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_c090ccfd-27a8-4b2b-8f26-42053f434841/bin/uautomizer/../../sv-benchmarks/c/systemc/kundu1.cil.c [2019-12-07 14:48:16,174 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_c090ccfd-27a8-4b2b-8f26-42053f434841/bin/uautomizer/data/f7d375cdc/fce33fe88399479fbb57a8b090f2d3fd/FLAG40a841c8d [2019-12-07 14:48:16,609 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 14:48:16,610 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_c090ccfd-27a8-4b2b-8f26-42053f434841/sv-benchmarks/c/systemc/kundu1.cil.c [2019-12-07 14:48:16,616 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_c090ccfd-27a8-4b2b-8f26-42053f434841/bin/uautomizer/data/f7d375cdc/fce33fe88399479fbb57a8b090f2d3fd/FLAG40a841c8d [2019-12-07 14:48:16,624 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_c090ccfd-27a8-4b2b-8f26-42053f434841/bin/uautomizer/data/f7d375cdc/fce33fe88399479fbb57a8b090f2d3fd [2019-12-07 14:48:16,626 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 14:48:16,627 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 14:48:16,628 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 14:48:16,628 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 14:48:16,630 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 14:48:16,631 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 02:48:16" (1/1) ... [2019-12-07 14:48:16,632 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@29414edc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:48:16, skipping insertion in model container [2019-12-07 14:48:16,633 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 02:48:16" (1/1) ... [2019-12-07 14:48:16,637 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 14:48:16,659 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 14:48:16,816 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 14:48:16,819 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 14:48:16,842 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 14:48:16,854 INFO L208 MainTranslator]: Completed translation [2019-12-07 14:48:16,855 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:48:16 WrapperNode [2019-12-07 14:48:16,855 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 14:48:16,855 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 14:48:16,855 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 14:48:16,855 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 14:48:16,860 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:48:16" (1/1) ... [2019-12-07 14:48:16,866 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:48:16" (1/1) ... [2019-12-07 14:48:16,886 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 14:48:16,886 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 14:48:16,886 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 14:48:16,886 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 14:48:16,892 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:48:16" (1/1) ... [2019-12-07 14:48:16,892 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:48:16" (1/1) ... [2019-12-07 14:48:16,894 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:48:16" (1/1) ... [2019-12-07 14:48:16,894 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:48:16" (1/1) ... [2019-12-07 14:48:16,898 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:48:16" (1/1) ... [2019-12-07 14:48:16,904 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:48:16" (1/1) ... [2019-12-07 14:48:16,905 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:48:16" (1/1) ... [2019-12-07 14:48:16,907 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 14:48:16,908 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 14:48:16,908 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 14:48:16,908 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 14:48:16,908 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:48:16" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_c090ccfd-27a8-4b2b-8f26-42053f434841/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 14:48:16,954 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 14:48:16,954 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 14:48:17,246 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 14:48:17,247 INFO L287 CfgBuilder]: Removed 72 assume(true) statements. [2019-12-07 14:48:17,247 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 02:48:17 BoogieIcfgContainer [2019-12-07 14:48:17,248 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 14:48:17,248 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 14:48:17,248 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 14:48:17,250 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 14:48:17,250 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 02:48:16" (1/3) ... [2019-12-07 14:48:17,251 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@ef7bd29 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 02:48:17, skipping insertion in model container [2019-12-07 14:48:17,251 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:48:16" (2/3) ... [2019-12-07 14:48:17,251 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@ef7bd29 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 02:48:17, skipping insertion in model container [2019-12-07 14:48:17,251 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 02:48:17" (3/3) ... [2019-12-07 14:48:17,252 INFO L109 eAbstractionObserver]: Analyzing ICFG kundu1.cil.c [2019-12-07 14:48:17,258 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 14:48:17,263 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 3 error locations. [2019-12-07 14:48:17,270 INFO L249 AbstractCegarLoop]: Starting to check reachability of 3 error locations. [2019-12-07 14:48:17,286 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 14:48:17,286 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 14:48:17,286 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 14:48:17,286 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 14:48:17,286 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 14:48:17,286 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 14:48:17,286 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 14:48:17,287 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 14:48:17,299 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states. [2019-12-07 14:48:17,304 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-12-07 14:48:17,304 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:48:17,304 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:48:17,305 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:48:17,308 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:48:17,309 INFO L82 PathProgramCache]: Analyzing trace with hash 1913091172, now seen corresponding path program 1 times [2019-12-07 14:48:17,314 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:48:17,314 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2103548927] [2019-12-07 14:48:17,315 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:48:17,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:48:17,416 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:48:17,416 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2103548927] [2019-12-07 14:48:17,417 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:48:17,417 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 14:48:17,418 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [897275554] [2019-12-07 14:48:17,421 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:48:17,421 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:48:17,429 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:48:17,430 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:48:17,431 INFO L87 Difference]: Start difference. First operand 117 states. Second operand 3 states. [2019-12-07 14:48:17,460 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:48:17,460 INFO L93 Difference]: Finished difference Result 228 states and 346 transitions. [2019-12-07 14:48:17,461 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:48:17,461 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 33 [2019-12-07 14:48:17,462 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:48:17,469 INFO L225 Difference]: With dead ends: 228 [2019-12-07 14:48:17,469 INFO L226 Difference]: Without dead ends: 112 [2019-12-07 14:48:17,471 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:48:17,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2019-12-07 14:48:17,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 112. [2019-12-07 14:48:17,499 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112 states. [2019-12-07 14:48:17,501 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 162 transitions. [2019-12-07 14:48:17,502 INFO L78 Accepts]: Start accepts. Automaton has 112 states and 162 transitions. Word has length 33 [2019-12-07 14:48:17,502 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:48:17,502 INFO L462 AbstractCegarLoop]: Abstraction has 112 states and 162 transitions. [2019-12-07 14:48:17,502 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:48:17,502 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 162 transitions. [2019-12-07 14:48:17,503 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-12-07 14:48:17,503 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:48:17,503 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:48:17,503 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:48:17,504 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:48:17,504 INFO L82 PathProgramCache]: Analyzing trace with hash 526887778, now seen corresponding path program 1 times [2019-12-07 14:48:17,504 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:48:17,504 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [588248106] [2019-12-07 14:48:17,504 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:48:17,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:48:17,533 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:48:17,534 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [588248106] [2019-12-07 14:48:17,534 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:48:17,534 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 14:48:17,534 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1337391954] [2019-12-07 14:48:17,536 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:48:17,536 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:48:17,536 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:48:17,536 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:48:17,537 INFO L87 Difference]: Start difference. First operand 112 states and 162 transitions. Second operand 3 states. [2019-12-07 14:48:17,578 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:48:17,578 INFO L93 Difference]: Finished difference Result 305 states and 441 transitions. [2019-12-07 14:48:17,578 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:48:17,578 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 33 [2019-12-07 14:48:17,579 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:48:17,580 INFO L225 Difference]: With dead ends: 305 [2019-12-07 14:48:17,580 INFO L226 Difference]: Without dead ends: 200 [2019-12-07 14:48:17,581 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:48:17,582 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 200 states. [2019-12-07 14:48:17,595 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 200 to 190. [2019-12-07 14:48:17,595 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 190 states. [2019-12-07 14:48:17,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190 states to 190 states and 275 transitions. [2019-12-07 14:48:17,597 INFO L78 Accepts]: Start accepts. Automaton has 190 states and 275 transitions. Word has length 33 [2019-12-07 14:48:17,597 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:48:17,597 INFO L462 AbstractCegarLoop]: Abstraction has 190 states and 275 transitions. [2019-12-07 14:48:17,597 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:48:17,597 INFO L276 IsEmpty]: Start isEmpty. Operand 190 states and 275 transitions. [2019-12-07 14:48:17,598 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-12-07 14:48:17,598 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:48:17,598 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:48:17,598 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:48:17,599 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:48:17,599 INFO L82 PathProgramCache]: Analyzing trace with hash -1145629853, now seen corresponding path program 1 times [2019-12-07 14:48:17,599 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:48:17,599 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1350030535] [2019-12-07 14:48:17,599 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:48:17,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:48:17,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:48:17,627 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1350030535] [2019-12-07 14:48:17,627 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:48:17,627 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 14:48:17,627 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [994706729] [2019-12-07 14:48:17,628 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:48:17,628 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:48:17,628 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:48:17,628 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:48:17,629 INFO L87 Difference]: Start difference. First operand 190 states and 275 transitions. Second operand 3 states. [2019-12-07 14:48:17,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:48:17,682 INFO L93 Difference]: Finished difference Result 527 states and 762 transitions. [2019-12-07 14:48:17,682 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:48:17,682 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 33 [2019-12-07 14:48:17,682 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:48:17,684 INFO L225 Difference]: With dead ends: 527 [2019-12-07 14:48:17,684 INFO L226 Difference]: Without dead ends: 350 [2019-12-07 14:48:17,686 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:48:17,687 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 350 states. [2019-12-07 14:48:17,702 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 350 to 328. [2019-12-07 14:48:17,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 328 states. [2019-12-07 14:48:17,703 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 328 states to 328 states and 462 transitions. [2019-12-07 14:48:17,703 INFO L78 Accepts]: Start accepts. Automaton has 328 states and 462 transitions. Word has length 33 [2019-12-07 14:48:17,704 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:48:17,704 INFO L462 AbstractCegarLoop]: Abstraction has 328 states and 462 transitions. [2019-12-07 14:48:17,704 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:48:17,704 INFO L276 IsEmpty]: Start isEmpty. Operand 328 states and 462 transitions. [2019-12-07 14:48:17,705 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 14:48:17,705 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:48:17,705 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:48:17,705 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:48:17,705 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:48:17,705 INFO L82 PathProgramCache]: Analyzing trace with hash -1045714737, now seen corresponding path program 1 times [2019-12-07 14:48:17,705 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:48:17,705 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1042960106] [2019-12-07 14:48:17,706 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:48:17,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:48:17,755 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:48:17,755 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1042960106] [2019-12-07 14:48:17,755 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:48:17,756 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 14:48:17,756 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [267620712] [2019-12-07 14:48:17,756 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 14:48:17,756 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:48:17,757 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 14:48:17,757 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:48:17,757 INFO L87 Difference]: Start difference. First operand 328 states and 462 transitions. Second operand 5 states. [2019-12-07 14:48:17,841 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:48:17,842 INFO L93 Difference]: Finished difference Result 1045 states and 1489 transitions. [2019-12-07 14:48:17,842 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 14:48:17,842 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 34 [2019-12-07 14:48:17,842 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:48:17,845 INFO L225 Difference]: With dead ends: 1045 [2019-12-07 14:48:17,845 INFO L226 Difference]: Without dead ends: 728 [2019-12-07 14:48:17,846 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 14:48:17,847 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 728 states. [2019-12-07 14:48:17,864 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 728 to 340. [2019-12-07 14:48:17,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 340 states. [2019-12-07 14:48:17,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 340 states to 340 states and 469 transitions. [2019-12-07 14:48:17,866 INFO L78 Accepts]: Start accepts. Automaton has 340 states and 469 transitions. Word has length 34 [2019-12-07 14:48:17,866 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:48:17,866 INFO L462 AbstractCegarLoop]: Abstraction has 340 states and 469 transitions. [2019-12-07 14:48:17,866 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 14:48:17,866 INFO L276 IsEmpty]: Start isEmpty. Operand 340 states and 469 transitions. [2019-12-07 14:48:17,867 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 14:48:17,867 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:48:17,867 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:48:17,867 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:48:17,867 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:48:17,867 INFO L82 PathProgramCache]: Analyzing trace with hash -1179728243, now seen corresponding path program 1 times [2019-12-07 14:48:17,867 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:48:17,868 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [5906920] [2019-12-07 14:48:17,868 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:48:17,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:48:17,911 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:48:17,911 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [5906920] [2019-12-07 14:48:17,911 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:48:17,911 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 14:48:17,911 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [310128127] [2019-12-07 14:48:17,912 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 14:48:17,912 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:48:17,912 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 14:48:17,912 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:48:17,912 INFO L87 Difference]: Start difference. First operand 340 states and 469 transitions. Second operand 5 states. [2019-12-07 14:48:18,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:48:18,018 INFO L93 Difference]: Finished difference Result 1046 states and 1465 transitions. [2019-12-07 14:48:18,018 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 14:48:18,018 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 34 [2019-12-07 14:48:18,019 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:48:18,023 INFO L225 Difference]: With dead ends: 1046 [2019-12-07 14:48:18,023 INFO L226 Difference]: Without dead ends: 724 [2019-12-07 14:48:18,024 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 14:48:18,025 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 724 states. [2019-12-07 14:48:18,047 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 724 to 352. [2019-12-07 14:48:18,047 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 352 states. [2019-12-07 14:48:18,048 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 352 states to 352 states and 476 transitions. [2019-12-07 14:48:18,048 INFO L78 Accepts]: Start accepts. Automaton has 352 states and 476 transitions. Word has length 34 [2019-12-07 14:48:18,048 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:48:18,048 INFO L462 AbstractCegarLoop]: Abstraction has 352 states and 476 transitions. [2019-12-07 14:48:18,049 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 14:48:18,049 INFO L276 IsEmpty]: Start isEmpty. Operand 352 states and 476 transitions. [2019-12-07 14:48:18,049 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 14:48:18,050 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:48:18,050 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:48:18,050 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:48:18,050 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:48:18,050 INFO L82 PathProgramCache]: Analyzing trace with hash 1526891151, now seen corresponding path program 1 times [2019-12-07 14:48:18,050 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:48:18,050 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [616979635] [2019-12-07 14:48:18,051 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:48:18,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:48:18,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:48:18,089 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [616979635] [2019-12-07 14:48:18,090 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:48:18,090 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 14:48:18,090 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1685653233] [2019-12-07 14:48:18,090 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 14:48:18,091 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:48:18,091 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 14:48:18,091 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 14:48:18,091 INFO L87 Difference]: Start difference. First operand 352 states and 476 transitions. Second operand 4 states. [2019-12-07 14:48:18,196 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:48:18,197 INFO L93 Difference]: Finished difference Result 1638 states and 2239 transitions. [2019-12-07 14:48:18,197 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 14:48:18,197 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 34 [2019-12-07 14:48:18,197 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:48:18,203 INFO L225 Difference]: With dead ends: 1638 [2019-12-07 14:48:18,203 INFO L226 Difference]: Without dead ends: 1304 [2019-12-07 14:48:18,204 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:48:18,205 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1304 states. [2019-12-07 14:48:18,248 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1304 to 662. [2019-12-07 14:48:18,248 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 662 states. [2019-12-07 14:48:18,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 662 states to 662 states and 900 transitions. [2019-12-07 14:48:18,250 INFO L78 Accepts]: Start accepts. Automaton has 662 states and 900 transitions. Word has length 34 [2019-12-07 14:48:18,250 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:48:18,250 INFO L462 AbstractCegarLoop]: Abstraction has 662 states and 900 transitions. [2019-12-07 14:48:18,250 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 14:48:18,250 INFO L276 IsEmpty]: Start isEmpty. Operand 662 states and 900 transitions. [2019-12-07 14:48:18,251 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2019-12-07 14:48:18,251 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:48:18,251 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:48:18,251 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:48:18,251 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:48:18,252 INFO L82 PathProgramCache]: Analyzing trace with hash -1026068075, now seen corresponding path program 1 times [2019-12-07 14:48:18,252 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:48:18,252 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1507954903] [2019-12-07 14:48:18,252 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:48:18,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:48:18,281 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:48:18,281 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1507954903] [2019-12-07 14:48:18,281 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:48:18,282 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 14:48:18,282 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [231177211] [2019-12-07 14:48:18,282 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 14:48:18,282 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:48:18,282 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 14:48:18,283 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 14:48:18,283 INFO L87 Difference]: Start difference. First operand 662 states and 900 transitions. Second operand 4 states. [2019-12-07 14:48:18,339 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:48:18,339 INFO L93 Difference]: Finished difference Result 1626 states and 2222 transitions. [2019-12-07 14:48:18,339 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 14:48:18,339 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 41 [2019-12-07 14:48:18,340 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:48:18,344 INFO L225 Difference]: With dead ends: 1626 [2019-12-07 14:48:18,344 INFO L226 Difference]: Without dead ends: 982 [2019-12-07 14:48:18,345 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 14:48:18,346 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 982 states. [2019-12-07 14:48:18,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 982 to 972. [2019-12-07 14:48:18,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 972 states. [2019-12-07 14:48:18,385 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 972 states to 972 states and 1324 transitions. [2019-12-07 14:48:18,385 INFO L78 Accepts]: Start accepts. Automaton has 972 states and 1324 transitions. Word has length 41 [2019-12-07 14:48:18,385 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:48:18,385 INFO L462 AbstractCegarLoop]: Abstraction has 972 states and 1324 transitions. [2019-12-07 14:48:18,385 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 14:48:18,385 INFO L276 IsEmpty]: Start isEmpty. Operand 972 states and 1324 transitions. [2019-12-07 14:48:18,386 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2019-12-07 14:48:18,386 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:48:18,386 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:48:18,387 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:48:18,387 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:48:18,387 INFO L82 PathProgramCache]: Analyzing trace with hash -305826283, now seen corresponding path program 1 times [2019-12-07 14:48:18,387 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:48:18,387 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [426825035] [2019-12-07 14:48:18,388 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:48:18,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:48:18,428 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:48:18,428 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [426825035] [2019-12-07 14:48:18,428 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:48:18,428 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 14:48:18,428 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1037791964] [2019-12-07 14:48:18,429 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 14:48:18,429 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:48:18,429 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 14:48:18,429 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2019-12-07 14:48:18,430 INFO L87 Difference]: Start difference. First operand 972 states and 1324 transitions. Second operand 6 states. [2019-12-07 14:48:18,624 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:48:18,624 INFO L93 Difference]: Finished difference Result 3850 states and 5260 transitions. [2019-12-07 14:48:18,624 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 14:48:18,624 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 44 [2019-12-07 14:48:18,625 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:48:18,636 INFO L225 Difference]: With dead ends: 3850 [2019-12-07 14:48:18,636 INFO L226 Difference]: Without dead ends: 2896 [2019-12-07 14:48:18,638 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2019-12-07 14:48:18,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2896 states. [2019-12-07 14:48:18,716 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2896 to 1606. [2019-12-07 14:48:18,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1606 states. [2019-12-07 14:48:18,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1606 states to 1606 states and 2192 transitions. [2019-12-07 14:48:18,721 INFO L78 Accepts]: Start accepts. Automaton has 1606 states and 2192 transitions. Word has length 44 [2019-12-07 14:48:18,721 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:48:18,721 INFO L462 AbstractCegarLoop]: Abstraction has 1606 states and 2192 transitions. [2019-12-07 14:48:18,721 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 14:48:18,721 INFO L276 IsEmpty]: Start isEmpty. Operand 1606 states and 2192 transitions. [2019-12-07 14:48:18,722 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2019-12-07 14:48:18,722 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:48:18,722 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:48:18,722 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:48:18,723 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:48:18,723 INFO L82 PathProgramCache]: Analyzing trace with hash -1702134670, now seen corresponding path program 1 times [2019-12-07 14:48:18,723 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:48:18,723 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1687882515] [2019-12-07 14:48:18,723 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:48:18,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:48:18,747 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2019-12-07 14:48:18,747 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1687882515] [2019-12-07 14:48:18,747 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:48:18,747 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 14:48:18,747 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1163711854] [2019-12-07 14:48:18,748 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:48:18,748 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:48:18,748 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:48:18,748 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:48:18,748 INFO L87 Difference]: Start difference. First operand 1606 states and 2192 transitions. Second operand 3 states. [2019-12-07 14:48:18,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:48:18,917 INFO L93 Difference]: Finished difference Result 4614 states and 6233 transitions. [2019-12-07 14:48:18,918 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:48:18,918 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 46 [2019-12-07 14:48:18,918 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:48:18,929 INFO L225 Difference]: With dead ends: 4614 [2019-12-07 14:48:18,929 INFO L226 Difference]: Without dead ends: 3026 [2019-12-07 14:48:18,932 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:48:18,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3026 states. [2019-12-07 14:48:19,053 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3026 to 3022. [2019-12-07 14:48:19,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3022 states. [2019-12-07 14:48:19,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3022 states to 3022 states and 3978 transitions. [2019-12-07 14:48:19,061 INFO L78 Accepts]: Start accepts. Automaton has 3022 states and 3978 transitions. Word has length 46 [2019-12-07 14:48:19,061 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:48:19,061 INFO L462 AbstractCegarLoop]: Abstraction has 3022 states and 3978 transitions. [2019-12-07 14:48:19,061 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:48:19,062 INFO L276 IsEmpty]: Start isEmpty. Operand 3022 states and 3978 transitions. [2019-12-07 14:48:19,062 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2019-12-07 14:48:19,062 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:48:19,062 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:48:19,063 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:48:19,063 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:48:19,063 INFO L82 PathProgramCache]: Analyzing trace with hash 1664931104, now seen corresponding path program 1 times [2019-12-07 14:48:19,063 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:48:19,063 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [865261879] [2019-12-07 14:48:19,063 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:48:19,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:48:19,081 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:48:19,081 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [865261879] [2019-12-07 14:48:19,081 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:48:19,081 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 14:48:19,081 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [479406716] [2019-12-07 14:48:19,081 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:48:19,082 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:48:19,082 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:48:19,082 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:48:19,082 INFO L87 Difference]: Start difference. First operand 3022 states and 3978 transitions. Second operand 3 states. [2019-12-07 14:48:19,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:48:19,357 INFO L93 Difference]: Finished difference Result 8013 states and 10530 transitions. [2019-12-07 14:48:19,358 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:48:19,358 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2019-12-07 14:48:19,358 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:48:19,376 INFO L225 Difference]: With dead ends: 8013 [2019-12-07 14:48:19,376 INFO L226 Difference]: Without dead ends: 5023 [2019-12-07 14:48:19,379 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:48:19,384 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5023 states. [2019-12-07 14:48:19,557 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5023 to 4273. [2019-12-07 14:48:19,557 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4273 states. [2019-12-07 14:48:19,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4273 states to 4273 states and 5593 transitions. [2019-12-07 14:48:19,567 INFO L78 Accepts]: Start accepts. Automaton has 4273 states and 5593 transitions. Word has length 48 [2019-12-07 14:48:19,567 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:48:19,567 INFO L462 AbstractCegarLoop]: Abstraction has 4273 states and 5593 transitions. [2019-12-07 14:48:19,567 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:48:19,568 INFO L276 IsEmpty]: Start isEmpty. Operand 4273 states and 5593 transitions. [2019-12-07 14:48:19,568 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2019-12-07 14:48:19,568 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:48:19,568 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:48:19,569 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:48:19,569 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:48:19,569 INFO L82 PathProgramCache]: Analyzing trace with hash 403090641, now seen corresponding path program 1 times [2019-12-07 14:48:19,569 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:48:19,569 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [550590219] [2019-12-07 14:48:19,569 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:48:19,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:48:19,586 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:48:19,586 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [550590219] [2019-12-07 14:48:19,586 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:48:19,587 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 14:48:19,587 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [635442523] [2019-12-07 14:48:19,587 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:48:19,587 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:48:19,587 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:48:19,587 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:48:19,587 INFO L87 Difference]: Start difference. First operand 4273 states and 5593 transitions. Second operand 3 states. [2019-12-07 14:48:19,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:48:19,791 INFO L93 Difference]: Finished difference Result 8516 states and 11154 transitions. [2019-12-07 14:48:19,791 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:48:19,791 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2019-12-07 14:48:19,792 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:48:19,806 INFO L225 Difference]: With dead ends: 8516 [2019-12-07 14:48:19,806 INFO L226 Difference]: Without dead ends: 4275 [2019-12-07 14:48:19,811 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:48:19,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4275 states. [2019-12-07 14:48:19,980 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4275 to 4273. [2019-12-07 14:48:19,980 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4273 states. [2019-12-07 14:48:19,989 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4273 states to 4273 states and 5518 transitions. [2019-12-07 14:48:19,989 INFO L78 Accepts]: Start accepts. Automaton has 4273 states and 5518 transitions. Word has length 48 [2019-12-07 14:48:19,989 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:48:19,989 INFO L462 AbstractCegarLoop]: Abstraction has 4273 states and 5518 transitions. [2019-12-07 14:48:19,989 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:48:19,989 INFO L276 IsEmpty]: Start isEmpty. Operand 4273 states and 5518 transitions. [2019-12-07 14:48:19,990 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2019-12-07 14:48:19,990 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:48:19,990 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:48:19,990 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:48:19,990 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:48:19,990 INFO L82 PathProgramCache]: Analyzing trace with hash 57108908, now seen corresponding path program 1 times [2019-12-07 14:48:19,991 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:48:19,991 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1666985459] [2019-12-07 14:48:19,991 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:48:19,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:48:20,007 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:48:20,007 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1666985459] [2019-12-07 14:48:20,007 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:48:20,007 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 14:48:20,008 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1685598500] [2019-12-07 14:48:20,008 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:48:20,008 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:48:20,008 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:48:20,008 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:48:20,008 INFO L87 Difference]: Start difference. First operand 4273 states and 5518 transitions. Second operand 3 states. [2019-12-07 14:48:20,201 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:48:20,201 INFO L93 Difference]: Finished difference Result 7967 states and 10312 transitions. [2019-12-07 14:48:20,201 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:48:20,202 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 49 [2019-12-07 14:48:20,202 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:48:20,214 INFO L225 Difference]: With dead ends: 7967 [2019-12-07 14:48:20,214 INFO L226 Difference]: Without dead ends: 3610 [2019-12-07 14:48:20,219 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:48:20,222 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3610 states. [2019-12-07 14:48:20,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3610 to 3465. [2019-12-07 14:48:20,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3465 states. [2019-12-07 14:48:20,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3465 states to 3465 states and 4400 transitions. [2019-12-07 14:48:20,377 INFO L78 Accepts]: Start accepts. Automaton has 3465 states and 4400 transitions. Word has length 49 [2019-12-07 14:48:20,377 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:48:20,377 INFO L462 AbstractCegarLoop]: Abstraction has 3465 states and 4400 transitions. [2019-12-07 14:48:20,377 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:48:20,377 INFO L276 IsEmpty]: Start isEmpty. Operand 3465 states and 4400 transitions. [2019-12-07 14:48:20,379 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2019-12-07 14:48:20,379 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:48:20,379 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:48:20,379 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:48:20,379 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:48:20,379 INFO L82 PathProgramCache]: Analyzing trace with hash 652914839, now seen corresponding path program 1 times [2019-12-07 14:48:20,380 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:48:20,380 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1837211403] [2019-12-07 14:48:20,380 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:48:20,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:48:20,405 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 19 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-12-07 14:48:20,406 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1837211403] [2019-12-07 14:48:20,406 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:48:20,406 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 14:48:20,406 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [884939821] [2019-12-07 14:48:20,406 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:48:20,406 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:48:20,406 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:48:20,407 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:48:20,407 INFO L87 Difference]: Start difference. First operand 3465 states and 4400 transitions. Second operand 3 states. [2019-12-07 14:48:20,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:48:20,536 INFO L93 Difference]: Finished difference Result 6369 states and 8143 transitions. [2019-12-07 14:48:20,536 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:48:20,536 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 83 [2019-12-07 14:48:20,536 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:48:20,547 INFO L225 Difference]: With dead ends: 6369 [2019-12-07 14:48:20,547 INFO L226 Difference]: Without dead ends: 3465 [2019-12-07 14:48:20,550 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:48:20,553 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3465 states. [2019-12-07 14:48:20,680 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3465 to 3465. [2019-12-07 14:48:20,681 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3465 states. [2019-12-07 14:48:20,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3465 states to 3465 states and 4336 transitions. [2019-12-07 14:48:20,684 INFO L78 Accepts]: Start accepts. Automaton has 3465 states and 4336 transitions. Word has length 83 [2019-12-07 14:48:20,684 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:48:20,684 INFO L462 AbstractCegarLoop]: Abstraction has 3465 states and 4336 transitions. [2019-12-07 14:48:20,684 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:48:20,684 INFO L276 IsEmpty]: Start isEmpty. Operand 3465 states and 4336 transitions. [2019-12-07 14:48:20,686 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2019-12-07 14:48:20,686 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:48:20,686 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:48:20,686 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:48:20,686 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:48:20,686 INFO L82 PathProgramCache]: Analyzing trace with hash -608848062, now seen corresponding path program 1 times [2019-12-07 14:48:20,686 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:48:20,686 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [383211478] [2019-12-07 14:48:20,686 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:48:20,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:48:20,708 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 25 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:48:20,708 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [383211478] [2019-12-07 14:48:20,708 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:48:20,708 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 14:48:20,708 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [338364364] [2019-12-07 14:48:20,709 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:48:20,709 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:48:20,709 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:48:20,709 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:48:20,709 INFO L87 Difference]: Start difference. First operand 3465 states and 4336 transitions. Second operand 3 states. [2019-12-07 14:48:20,909 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:48:20,909 INFO L93 Difference]: Finished difference Result 7371 states and 9260 transitions. [2019-12-07 14:48:20,910 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:48:20,910 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 84 [2019-12-07 14:48:20,910 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:48:20,917 INFO L225 Difference]: With dead ends: 7371 [2019-12-07 14:48:20,917 INFO L226 Difference]: Without dead ends: 4154 [2019-12-07 14:48:20,920 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:48:20,924 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4154 states. [2019-12-07 14:48:21,070 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4154 to 3700. [2019-12-07 14:48:21,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3700 states. [2019-12-07 14:48:21,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3700 states to 3700 states and 4553 transitions. [2019-12-07 14:48:21,074 INFO L78 Accepts]: Start accepts. Automaton has 3700 states and 4553 transitions. Word has length 84 [2019-12-07 14:48:21,074 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:48:21,074 INFO L462 AbstractCegarLoop]: Abstraction has 3700 states and 4553 transitions. [2019-12-07 14:48:21,074 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:48:21,075 INFO L276 IsEmpty]: Start isEmpty. Operand 3700 states and 4553 transitions. [2019-12-07 14:48:21,076 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2019-12-07 14:48:21,076 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:48:21,076 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:48:21,076 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:48:21,076 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:48:21,076 INFO L82 PathProgramCache]: Analyzing trace with hash 885528412, now seen corresponding path program 1 times [2019-12-07 14:48:21,076 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:48:21,076 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [223592123] [2019-12-07 14:48:21,077 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:48:21,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:48:21,102 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-12-07 14:48:21,102 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [223592123] [2019-12-07 14:48:21,102 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:48:21,102 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 14:48:21,103 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1036375130] [2019-12-07 14:48:21,103 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:48:21,103 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:48:21,103 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:48:21,103 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:48:21,103 INFO L87 Difference]: Start difference. First operand 3700 states and 4553 transitions. Second operand 3 states. [2019-12-07 14:48:21,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:48:21,310 INFO L93 Difference]: Finished difference Result 7674 states and 9427 transitions. [2019-12-07 14:48:21,310 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:48:21,310 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 86 [2019-12-07 14:48:21,310 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:48:21,317 INFO L225 Difference]: With dead ends: 7674 [2019-12-07 14:48:21,317 INFO L226 Difference]: Without dead ends: 4176 [2019-12-07 14:48:21,321 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:48:21,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4176 states. [2019-12-07 14:48:21,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4176 to 4174. [2019-12-07 14:48:21,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4174 states. [2019-12-07 14:48:21,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4174 states to 4174 states and 5092 transitions. [2019-12-07 14:48:21,530 INFO L78 Accepts]: Start accepts. Automaton has 4174 states and 5092 transitions. Word has length 86 [2019-12-07 14:48:21,530 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:48:21,530 INFO L462 AbstractCegarLoop]: Abstraction has 4174 states and 5092 transitions. [2019-12-07 14:48:21,530 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:48:21,530 INFO L276 IsEmpty]: Start isEmpty. Operand 4174 states and 5092 transitions. [2019-12-07 14:48:21,532 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2019-12-07 14:48:21,532 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:48:21,532 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:48:21,532 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:48:21,532 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:48:21,532 INFO L82 PathProgramCache]: Analyzing trace with hash 1836340184, now seen corresponding path program 1 times [2019-12-07 14:48:21,532 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:48:21,532 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1591284338] [2019-12-07 14:48:21,532 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:48:21,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:48:21,559 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 27 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:48:21,559 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1591284338] [2019-12-07 14:48:21,559 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:48:21,559 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 14:48:21,559 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [159241260] [2019-12-07 14:48:21,560 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:48:21,560 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:48:21,560 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:48:21,560 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:48:21,560 INFO L87 Difference]: Start difference. First operand 4174 states and 5092 transitions. Second operand 3 states. [2019-12-07 14:48:21,708 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:48:21,709 INFO L93 Difference]: Finished difference Result 7056 states and 8680 transitions. [2019-12-07 14:48:21,709 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:48:21,709 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 98 [2019-12-07 14:48:21,709 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:48:21,713 INFO L225 Difference]: With dead ends: 7056 [2019-12-07 14:48:21,713 INFO L226 Difference]: Without dead ends: 3227 [2019-12-07 14:48:21,717 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:48:21,719 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3227 states. [2019-12-07 14:48:21,842 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3227 to 3223. [2019-12-07 14:48:21,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3223 states. [2019-12-07 14:48:21,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3223 states to 3223 states and 3862 transitions. [2019-12-07 14:48:21,846 INFO L78 Accepts]: Start accepts. Automaton has 3223 states and 3862 transitions. Word has length 98 [2019-12-07 14:48:21,846 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:48:21,846 INFO L462 AbstractCegarLoop]: Abstraction has 3223 states and 3862 transitions. [2019-12-07 14:48:21,846 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:48:21,846 INFO L276 IsEmpty]: Start isEmpty. Operand 3223 states and 3862 transitions. [2019-12-07 14:48:21,847 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2019-12-07 14:48:21,847 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:48:21,848 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:48:21,848 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:48:21,848 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:48:21,848 INFO L82 PathProgramCache]: Analyzing trace with hash 1328739563, now seen corresponding path program 1 times [2019-12-07 14:48:21,848 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:48:21,848 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [660433573] [2019-12-07 14:48:21,848 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:48:21,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:48:21,872 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-12-07 14:48:21,872 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [660433573] [2019-12-07 14:48:21,873 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:48:21,873 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 14:48:21,873 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1738827494] [2019-12-07 14:48:21,873 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:48:21,873 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:48:21,873 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:48:21,873 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:48:21,873 INFO L87 Difference]: Start difference. First operand 3223 states and 3862 transitions. Second operand 3 states. [2019-12-07 14:48:21,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:48:21,995 INFO L93 Difference]: Finished difference Result 5622 states and 6780 transitions. [2019-12-07 14:48:21,996 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:48:21,996 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 99 [2019-12-07 14:48:21,996 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:48:21,999 INFO L225 Difference]: With dead ends: 5622 [2019-12-07 14:48:21,999 INFO L226 Difference]: Without dead ends: 3075 [2019-12-07 14:48:22,001 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:48:22,003 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3075 states. [2019-12-07 14:48:22,128 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3075 to 3075. [2019-12-07 14:48:22,128 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3075 states. [2019-12-07 14:48:22,131 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3075 states to 3075 states and 3691 transitions. [2019-12-07 14:48:22,132 INFO L78 Accepts]: Start accepts. Automaton has 3075 states and 3691 transitions. Word has length 99 [2019-12-07 14:48:22,132 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:48:22,132 INFO L462 AbstractCegarLoop]: Abstraction has 3075 states and 3691 transitions. [2019-12-07 14:48:22,132 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:48:22,132 INFO L276 IsEmpty]: Start isEmpty. Operand 3075 states and 3691 transitions. [2019-12-07 14:48:22,133 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2019-12-07 14:48:22,133 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:48:22,133 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:48:22,133 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:48:22,134 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:48:22,134 INFO L82 PathProgramCache]: Analyzing trace with hash -472369520, now seen corresponding path program 1 times [2019-12-07 14:48:22,134 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:48:22,134 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1746143439] [2019-12-07 14:48:22,134 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:48:22,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:48:22,179 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 23 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2019-12-07 14:48:22,180 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1746143439] [2019-12-07 14:48:22,180 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:48:22,180 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 14:48:22,180 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1507369556] [2019-12-07 14:48:22,181 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 14:48:22,181 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:48:22,181 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 14:48:22,181 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2019-12-07 14:48:22,181 INFO L87 Difference]: Start difference. First operand 3075 states and 3691 transitions. Second operand 8 states. [2019-12-07 14:48:22,358 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:48:22,358 INFO L93 Difference]: Finished difference Result 5286 states and 6380 transitions. [2019-12-07 14:48:22,359 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 14:48:22,359 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 104 [2019-12-07 14:48:22,359 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:48:22,362 INFO L225 Difference]: With dead ends: 5286 [2019-12-07 14:48:22,362 INFO L226 Difference]: Without dead ends: 2229 [2019-12-07 14:48:22,364 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=80, Unknown=0, NotChecked=0, Total=110 [2019-12-07 14:48:22,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2229 states. [2019-12-07 14:48:22,447 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2229 to 1920. [2019-12-07 14:48:22,447 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1920 states. [2019-12-07 14:48:22,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1920 states to 1920 states and 2325 transitions. [2019-12-07 14:48:22,449 INFO L78 Accepts]: Start accepts. Automaton has 1920 states and 2325 transitions. Word has length 104 [2019-12-07 14:48:22,449 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:48:22,449 INFO L462 AbstractCegarLoop]: Abstraction has 1920 states and 2325 transitions. [2019-12-07 14:48:22,449 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 14:48:22,449 INFO L276 IsEmpty]: Start isEmpty. Operand 1920 states and 2325 transitions. [2019-12-07 14:48:22,450 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2019-12-07 14:48:22,450 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:48:22,450 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:48:22,450 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:48:22,450 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:48:22,450 INFO L82 PathProgramCache]: Analyzing trace with hash 663738500, now seen corresponding path program 1 times [2019-12-07 14:48:22,450 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:48:22,450 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1064626272] [2019-12-07 14:48:22,451 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:48:22,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:48:22,480 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-12-07 14:48:22,480 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1064626272] [2019-12-07 14:48:22,480 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:48:22,480 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 14:48:22,480 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [792412893] [2019-12-07 14:48:22,481 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 14:48:22,481 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:48:22,481 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 14:48:22,481 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 14:48:22,481 INFO L87 Difference]: Start difference. First operand 1920 states and 2325 transitions. Second operand 4 states. [2019-12-07 14:48:22,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:48:22,603 INFO L93 Difference]: Finished difference Result 4180 states and 5082 transitions. [2019-12-07 14:48:22,603 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 14:48:22,603 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 107 [2019-12-07 14:48:22,603 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:48:22,606 INFO L225 Difference]: With dead ends: 4180 [2019-12-07 14:48:22,606 INFO L226 Difference]: Without dead ends: 2423 [2019-12-07 14:48:22,608 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 14:48:22,611 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2423 states. [2019-12-07 14:48:22,721 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2423 to 2324. [2019-12-07 14:48:22,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2324 states. [2019-12-07 14:48:22,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2324 states to 2324 states and 2802 transitions. [2019-12-07 14:48:22,724 INFO L78 Accepts]: Start accepts. Automaton has 2324 states and 2802 transitions. Word has length 107 [2019-12-07 14:48:22,724 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:48:22,724 INFO L462 AbstractCegarLoop]: Abstraction has 2324 states and 2802 transitions. [2019-12-07 14:48:22,724 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 14:48:22,724 INFO L276 IsEmpty]: Start isEmpty. Operand 2324 states and 2802 transitions. [2019-12-07 14:48:22,725 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2019-12-07 14:48:22,725 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:48:22,725 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:48:22,725 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:48:22,725 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:48:22,725 INFO L82 PathProgramCache]: Analyzing trace with hash -1105184803, now seen corresponding path program 1 times [2019-12-07 14:48:22,725 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:48:22,725 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1540616966] [2019-12-07 14:48:22,725 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:48:22,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:48:22,749 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:48:22,749 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1540616966] [2019-12-07 14:48:22,749 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:48:22,750 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 14:48:22,750 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1718368015] [2019-12-07 14:48:22,750 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:48:22,750 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:48:22,750 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:48:22,750 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:48:22,750 INFO L87 Difference]: Start difference. First operand 2324 states and 2802 transitions. Second operand 3 states. [2019-12-07 14:48:22,853 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:48:22,853 INFO L93 Difference]: Finished difference Result 3902 states and 4743 transitions. [2019-12-07 14:48:22,854 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:48:22,854 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 113 [2019-12-07 14:48:22,854 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:48:22,856 INFO L225 Difference]: With dead ends: 3902 [2019-12-07 14:48:22,856 INFO L226 Difference]: Without dead ends: 1655 [2019-12-07 14:48:22,859 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:48:22,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1655 states. [2019-12-07 14:48:22,962 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1655 to 1653. [2019-12-07 14:48:22,962 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1653 states. [2019-12-07 14:48:22,964 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1653 states to 1653 states and 1933 transitions. [2019-12-07 14:48:22,964 INFO L78 Accepts]: Start accepts. Automaton has 1653 states and 1933 transitions. Word has length 113 [2019-12-07 14:48:22,964 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:48:22,964 INFO L462 AbstractCegarLoop]: Abstraction has 1653 states and 1933 transitions. [2019-12-07 14:48:22,964 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:48:22,964 INFO L276 IsEmpty]: Start isEmpty. Operand 1653 states and 1933 transitions. [2019-12-07 14:48:22,965 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2019-12-07 14:48:22,965 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:48:22,965 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:48:22,965 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:48:22,966 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:48:22,966 INFO L82 PathProgramCache]: Analyzing trace with hash 1508765653, now seen corresponding path program 1 times [2019-12-07 14:48:22,966 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:48:22,966 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [335818782] [2019-12-07 14:48:22,966 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:48:22,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:48:23,028 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-12-07 14:48:23,028 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [335818782] [2019-12-07 14:48:23,028 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:48:23,028 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 14:48:23,028 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [319771170] [2019-12-07 14:48:23,029 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 14:48:23,029 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:48:23,029 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 14:48:23,029 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:48:23,029 INFO L87 Difference]: Start difference. First operand 1653 states and 1933 transitions. Second operand 5 states. [2019-12-07 14:48:23,222 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:48:23,222 INFO L93 Difference]: Finished difference Result 4188 states and 4920 transitions. [2019-12-07 14:48:23,222 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 14:48:23,222 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 114 [2019-12-07 14:48:23,223 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:48:23,224 INFO L225 Difference]: With dead ends: 4188 [2019-12-07 14:48:23,225 INFO L226 Difference]: Without dead ends: 2940 [2019-12-07 14:48:23,226 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 14:48:23,228 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2940 states. [2019-12-07 14:48:23,324 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2940 to 1905. [2019-12-07 14:48:23,324 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1905 states. [2019-12-07 14:48:23,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1905 states to 1905 states and 2228 transitions. [2019-12-07 14:48:23,326 INFO L78 Accepts]: Start accepts. Automaton has 1905 states and 2228 transitions. Word has length 114 [2019-12-07 14:48:23,326 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:48:23,326 INFO L462 AbstractCegarLoop]: Abstraction has 1905 states and 2228 transitions. [2019-12-07 14:48:23,326 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 14:48:23,326 INFO L276 IsEmpty]: Start isEmpty. Operand 1905 states and 2228 transitions. [2019-12-07 14:48:23,327 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2019-12-07 14:48:23,327 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:48:23,327 INFO L410 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:48:23,328 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:48:23,328 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:48:23,328 INFO L82 PathProgramCache]: Analyzing trace with hash -1919382230, now seen corresponding path program 1 times [2019-12-07 14:48:23,328 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:48:23,328 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1218085441] [2019-12-07 14:48:23,328 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:48:23,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:48:23,386 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 0 proven. 35 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-12-07 14:48:23,387 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1218085441] [2019-12-07 14:48:23,387 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1604597164] [2019-12-07 14:48:23,387 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_c090ccfd-27a8-4b2b-8f26-42053f434841/bin/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 14:48:23,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:48:23,445 INFO L264 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 9 conjunts are in the unsatisfiable core [2019-12-07 14:48:23,451 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 14:48:23,475 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 0 proven. 35 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2019-12-07 14:48:23,475 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 14:48:23,475 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 5 [2019-12-07 14:48:23,475 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1605204740] [2019-12-07 14:48:23,476 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 14:48:23,476 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:48:23,476 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 14:48:23,476 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:48:23,476 INFO L87 Difference]: Start difference. First operand 1905 states and 2228 transitions. Second operand 5 states. [2019-12-07 14:48:23,708 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:48:23,708 INFO L93 Difference]: Finished difference Result 4107 states and 4811 transitions. [2019-12-07 14:48:23,708 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 14:48:23,708 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 118 [2019-12-07 14:48:23,709 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:48:23,716 INFO L225 Difference]: With dead ends: 4107 [2019-12-07 14:48:23,716 INFO L226 Difference]: Without dead ends: 3084 [2019-12-07 14:48:23,718 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 125 GetRequests, 119 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 14:48:23,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3084 states. [2019-12-07 14:48:23,830 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3084 to 2067. [2019-12-07 14:48:23,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2067 states. [2019-12-07 14:48:23,832 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2067 states to 2067 states and 2410 transitions. [2019-12-07 14:48:23,832 INFO L78 Accepts]: Start accepts. Automaton has 2067 states and 2410 transitions. Word has length 118 [2019-12-07 14:48:23,832 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:48:23,832 INFO L462 AbstractCegarLoop]: Abstraction has 2067 states and 2410 transitions. [2019-12-07 14:48:23,832 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 14:48:23,832 INFO L276 IsEmpty]: Start isEmpty. Operand 2067 states and 2410 transitions. [2019-12-07 14:48:23,835 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 173 [2019-12-07 14:48:23,835 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:48:23,835 INFO L410 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:48:24,036 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 14:48:24,036 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:48:24,036 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:48:24,036 INFO L82 PathProgramCache]: Analyzing trace with hash -2045968037, now seen corresponding path program 1 times [2019-12-07 14:48:24,036 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:48:24,037 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [866076419] [2019-12-07 14:48:24,037 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:48:24,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:48:24,072 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 129 proven. 0 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2019-12-07 14:48:24,073 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [866076419] [2019-12-07 14:48:24,073 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:48:24,073 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 14:48:24,073 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2141533024] [2019-12-07 14:48:24,073 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:48:24,073 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:48:24,073 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:48:24,074 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:48:24,074 INFO L87 Difference]: Start difference. First operand 2067 states and 2410 transitions. Second operand 3 states. [2019-12-07 14:48:24,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:48:24,242 INFO L93 Difference]: Finished difference Result 5041 states and 5868 transitions. [2019-12-07 14:48:24,242 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:48:24,243 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 172 [2019-12-07 14:48:24,243 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:48:24,246 INFO L225 Difference]: With dead ends: 5041 [2019-12-07 14:48:24,246 INFO L226 Difference]: Without dead ends: 3137 [2019-12-07 14:48:24,248 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:48:24,251 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3137 states. [2019-12-07 14:48:24,405 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3137 to 3087. [2019-12-07 14:48:24,406 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3087 states. [2019-12-07 14:48:24,408 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3087 states to 3087 states and 3575 transitions. [2019-12-07 14:48:24,408 INFO L78 Accepts]: Start accepts. Automaton has 3087 states and 3575 transitions. Word has length 172 [2019-12-07 14:48:24,408 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:48:24,408 INFO L462 AbstractCegarLoop]: Abstraction has 3087 states and 3575 transitions. [2019-12-07 14:48:24,408 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:48:24,409 INFO L276 IsEmpty]: Start isEmpty. Operand 3087 states and 3575 transitions. [2019-12-07 14:48:24,411 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 173 [2019-12-07 14:48:24,411 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:48:24,411 INFO L410 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:48:24,411 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:48:24,411 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:48:24,412 INFO L82 PathProgramCache]: Analyzing trace with hash 1191161181, now seen corresponding path program 1 times [2019-12-07 14:48:24,412 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:48:24,412 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [120281621] [2019-12-07 14:48:24,412 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:48:24,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:48:24,440 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 99 proven. 0 refuted. 0 times theorem prover too weak. 57 trivial. 0 not checked. [2019-12-07 14:48:24,440 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [120281621] [2019-12-07 14:48:24,440 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:48:24,440 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 14:48:24,440 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [243905729] [2019-12-07 14:48:24,441 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:48:24,441 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:48:24,441 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:48:24,441 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:48:24,441 INFO L87 Difference]: Start difference. First operand 3087 states and 3575 transitions. Second operand 3 states. [2019-12-07 14:48:24,537 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:48:24,537 INFO L93 Difference]: Finished difference Result 4589 states and 5331 transitions. [2019-12-07 14:48:24,538 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:48:24,538 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 172 [2019-12-07 14:48:24,538 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:48:24,540 INFO L225 Difference]: With dead ends: 4589 [2019-12-07 14:48:24,541 INFO L226 Difference]: Without dead ends: 1619 [2019-12-07 14:48:24,543 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:48:24,545 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1619 states. [2019-12-07 14:48:24,632 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1619 to 1619. [2019-12-07 14:48:24,632 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1619 states. [2019-12-07 14:48:24,633 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1619 states to 1619 states and 1839 transitions. [2019-12-07 14:48:24,634 INFO L78 Accepts]: Start accepts. Automaton has 1619 states and 1839 transitions. Word has length 172 [2019-12-07 14:48:24,634 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:48:24,634 INFO L462 AbstractCegarLoop]: Abstraction has 1619 states and 1839 transitions. [2019-12-07 14:48:24,634 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:48:24,634 INFO L276 IsEmpty]: Start isEmpty. Operand 1619 states and 1839 transitions. [2019-12-07 14:48:24,635 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 191 [2019-12-07 14:48:24,636 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:48:24,636 INFO L410 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:48:24,636 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:48:24,636 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:48:24,636 INFO L82 PathProgramCache]: Analyzing trace with hash 1404970223, now seen corresponding path program 1 times [2019-12-07 14:48:24,636 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:48:24,636 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [96514183] [2019-12-07 14:48:24,636 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:48:24,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 14:48:24,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 14:48:24,705 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 14:48:24,705 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 14:48:24,796 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 02:48:24 BoogieIcfgContainer [2019-12-07 14:48:24,797 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 14:48:24,797 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 14:48:24,797 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 14:48:24,797 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 14:48:24,797 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 02:48:17" (3/4) ... [2019-12-07 14:48:24,799 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 14:48:24,890 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_c090ccfd-27a8-4b2b-8f26-42053f434841/bin/uautomizer/witness.graphml [2019-12-07 14:48:24,890 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 14:48:24,892 INFO L168 Benchmark]: Toolchain (without parser) took 8263.95 ms. Allocated memory was 1.0 GB in the beginning and 1.8 GB in the end (delta: 752.9 MB). Free memory was 940.6 MB in the beginning and 1.2 GB in the end (delta: -279.3 MB). Peak memory consumption was 473.6 MB. Max. memory is 11.5 GB. [2019-12-07 14:48:24,892 INFO L168 Benchmark]: CDTParser took 0.20 ms. Allocated memory is still 1.0 GB. Free memory is still 959.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 14:48:24,892 INFO L168 Benchmark]: CACSL2BoogieTranslator took 227.04 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 101.7 MB). Free memory was 940.6 MB in the beginning and 1.1 GB in the end (delta: -156.0 MB). Peak memory consumption was 20.7 MB. Max. memory is 11.5 GB. [2019-12-07 14:48:24,892 INFO L168 Benchmark]: Boogie Procedure Inliner took 30.56 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2019-12-07 14:48:24,892 INFO L168 Benchmark]: Boogie Preprocessor took 21.64 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2019-12-07 14:48:24,893 INFO L168 Benchmark]: RCFGBuilder took 339.90 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 38.9 MB). Peak memory consumption was 38.9 MB. Max. memory is 11.5 GB. [2019-12-07 14:48:24,893 INFO L168 Benchmark]: TraceAbstraction took 7548.51 ms. Allocated memory was 1.1 GB in the beginning and 1.8 GB in the end (delta: 651.2 MB). Free memory was 1.1 GB in the beginning and 1.2 GB in the end (delta: -192.3 MB). Peak memory consumption was 458.9 MB. Max. memory is 11.5 GB. [2019-12-07 14:48:24,893 INFO L168 Benchmark]: Witness Printer took 93.29 ms. Allocated memory is still 1.8 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 24.8 MB). Peak memory consumption was 24.8 MB. Max. memory is 11.5 GB. [2019-12-07 14:48:24,894 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20 ms. Allocated memory is still 1.0 GB. Free memory is still 959.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 227.04 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 101.7 MB). Free memory was 940.6 MB in the beginning and 1.1 GB in the end (delta: -156.0 MB). Peak memory consumption was 20.7 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 30.56 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 21.64 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 339.90 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 38.9 MB). Peak memory consumption was 38.9 MB. Max. memory is 11.5 GB. * TraceAbstraction took 7548.51 ms. Allocated memory was 1.1 GB in the beginning and 1.8 GB in the end (delta: 651.2 MB). Free memory was 1.1 GB in the beginning and 1.2 GB in the end (delta: -192.3 MB). Peak memory consumption was 458.9 MB. Max. memory is 11.5 GB. * Witness Printer took 93.29 ms. Allocated memory is still 1.8 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 24.8 MB). Peak memory consumption was 24.8 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 9]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int max_loop ; [L16] int num ; [L17] int i ; [L18] int e ; [L19] int timer ; [L20] char data_0 ; [L21] char data_1 ; [L64] int P_1_pc; [L65] int P_1_st ; [L66] int P_1_i ; [L67] int P_1_ev ; [L122] int C_1_pc ; [L123] int C_1_st ; [L124] int C_1_i ; [L125] int C_1_ev ; [L126] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, timer=0] [L490] int count ; [L491] int __retres2 ; [L495] num = 0 [L496] i = 0 [L497] max_loop = 2 [L499] timer = 0 [L500] P_1_pc = 0 [L501] C_1_pc = 0 [L503] count = 0 [L483] P_1_i = 1 [L484] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L421] int kernel_st ; [L422] int tmp ; [L423] int tmp___0 ; [L427] kernel_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L226] COND TRUE (int )P_1_i == 1 [L227] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L231] COND TRUE (int )C_1_i == 1 [L232] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; [L104] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L107] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L117] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L119] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L371] tmp = is_P_1_triggered() [L373] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L186] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L189] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L199] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L209] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L211] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L435] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L438] kernel_st = 1 [L262] int tmp ; [L263] int tmp___0 ; [L264] int tmp___1 ; [L265] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L269] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L241] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L258] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L294] COND TRUE (int )C_1_st == 0 [L296] tmp___1 = __VERIFIER_nondet_int() [L298] COND TRUE \read(tmp___1) [L300] C_1_st = 1 [L128] char c ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L131] COND TRUE (int )C_1_pc == 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L146] COND TRUE i < max_loop VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=0] [L148] COND TRUE num == 0 [L149] timer = 1 [L150] i += 1 [L151] C_1_pc = 1 [L152] C_1_st = 2 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L269] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L258] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, timer=1] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND TRUE \read(tmp) [L285] P_1_st = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L72] COND TRUE (int )P_1_pc == 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L83] COND TRUE i < max_loop VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=0, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L49] COND TRUE i___0 == 0 [L50] data_0 = c VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, timer=1] [L87] num += 1 [L88] P_1_pc = 1 [L89] P_1_st = 2 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L294] COND FALSE !((int )C_1_st == 0) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L269] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND FALSE !(\read(tmp___2)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L442] kernel_st = 2 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L446] kernel_st = 3 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; [L104] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND FALSE !((int )P_1_ev == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L117] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L186] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L190] COND FALSE !((int )e == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L209] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L211] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L452] tmp = exists_runnable_thread() [L454] COND TRUE tmp == 0 [L456] kernel_st = 4 [L336] C_1_ev = 1 [L338] P_1_ev = 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; [L104] int __retres1 ; VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND TRUE (int )P_1_ev == 1 [L109] __retres1 = 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND TRUE \read(tmp) [L374] P_1_st = 0 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L186] int __retres1 ; VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L190] COND FALSE !((int )e == 1) VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L209] __retres1 = 0 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L211] return (__retres1); VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L350] COND TRUE (int )P_1_ev == 1 [L351] P_1_ev = 2 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L355] COND TRUE (int )C_1_ev == 1 [L356] C_1_ev = 2 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L402] int tmp ; [L403] int __retres2 ; [L241] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] tmp = exists_runnable_thread() [L409] COND TRUE \read(tmp) [L410] __retres2 = 0 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L417] return (__retres2); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L465] tmp___0 = stop_simulation() [L467] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L435] COND TRUE 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L438] kernel_st = 1 [L262] int tmp ; [L263] int tmp___0 ; [L264] int tmp___1 ; [L265] int tmp___2 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L269] COND TRUE 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND TRUE \read(tmp) [L285] P_1_st = 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L72] COND FALSE !((int )P_1_pc == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L75] COND TRUE (int )P_1_pc == 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L83] COND TRUE i < max_loop VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L49] COND FALSE !(i___0 == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=0, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L52] COND TRUE i___0 == 1 [L53] data_1 = c VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L87] num += 1 [L88] P_1_pc = 1 [L89] P_1_st = 2 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L294] COND FALSE !((int )C_1_st == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L269] COND TRUE 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND FALSE !(\read(tmp___2)) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L442] kernel_st = 2 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L446] kernel_st = 3 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; [L104] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND FALSE !((int )P_1_ev == 1) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L117] __retres1 = 0 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND FALSE !(\read(tmp)) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L186] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L190] COND FALSE !((int )e == 1) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L209] __retres1 = 0 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L211] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L241] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L244] COND FALSE !((int )P_1_st == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L248] COND FALSE !((int )C_1_st == 0) [L256] __retres1 = 0 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L258] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L452] tmp = exists_runnable_thread() [L454] COND TRUE tmp == 0 [L456] kernel_st = 4 [L336] C_1_ev = 1 [L338] P_1_ev = 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L365] int tmp ; [L366] int tmp___0 ; [L367] int tmp___1 ; [L104] int __retres1 ; VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L107] COND TRUE (int )P_1_pc == 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L108] COND TRUE (int )P_1_ev == 1 [L109] __retres1 = 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L119] return (__retres1); VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, timer=1] [L371] tmp = is_P_1_triggered() [L373] COND TRUE \read(tmp) [L374] P_1_st = 0 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L186] int __retres1 ; VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L189] COND TRUE (int )C_1_pc == 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L190] COND FALSE !((int )e == 1) VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L199] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L209] __retres1 = 0 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L211] return (__retres1); VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L379] tmp___1 = is_C_1_triggered() [L381] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L350] COND TRUE (int )P_1_ev == 1 [L351] P_1_ev = 2 VAL [C_1_ev=1, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L355] COND TRUE (int )C_1_ev == 1 [L356] C_1_ev = 2 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L402] int tmp ; [L403] int __retres2 ; [L241] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L407] tmp = exists_runnable_thread() [L409] COND TRUE \read(tmp) [L410] __retres2 = 0 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L417] return (__retres2); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L465] tmp___0 = stop_simulation() [L467] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L435] COND TRUE 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L438] kernel_st = 1 [L262] int tmp ; [L263] int tmp___0 ; [L264] int tmp___1 ; [L265] int tmp___2 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L269] COND TRUE 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L241] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L244] COND TRUE (int )P_1_st == 0 [L245] __retres1 = 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L258] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L272] tmp___2 = exists_runnable_thread() [L274] COND TRUE \read(tmp___2) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, timer=1] [L279] COND TRUE (int )P_1_st == 0 [L281] tmp = __VERIFIER_nondet_int() [L283] COND TRUE \read(tmp) [L285] P_1_st = 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L72] COND FALSE !((int )P_1_pc == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L75] COND TRUE (int )P_1_pc == 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L83] COND TRUE i < max_loop VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L49] COND FALSE !(i___0 == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L52] COND FALSE !(i___0 == 1) VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] [L9] __VERIFIER_error() VAL [C_1_ev=2, C_1_i=1, C_1_pc=1, C_1_pr=0, C_1_st=2, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, timer=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 117 locations, 3 error locations. Result: UNSAFE, OverallTime: 7.4s, OverallIterations: 25, TraceHistogramMax: 6, AutomataDifference: 3.6s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 4775 SDtfs, 4830 SDslu, 6046 SDs, 0 SdLazy, 568 SolverSat, 139 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.3s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 232 GetRequests, 169 SyntacticMatches, 3 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=4273occurred in iteration=10, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 2.4s AutomataMinimizationTime, 24 MinimizatonAttempts, 6607 StatesRemovedByMinimization, 20 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.1s SatisfiabilityAnalysisTime, 0.5s InterpolantComputationTime, 2135 NumberOfCodeBlocks, 2135 NumberOfCodeBlocksAsserted, 26 NumberOfCheckSat, 1920 ConstructedInterpolants, 0 QuantifiedInterpolants, 350700 SizeOfPredicates, 2 NumberOfNonLiveVariables, 344 ConjunctsInSsa, 9 ConjunctsInUnsatCore, 25 InterpolantComputations, 23 PerfectInterpolantSequences, 619/689 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...