./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/kundu2.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_6bd400ac-a770-40b7-b3e4-36092e5a6e9a/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_6bd400ac-a770-40b7-b3e4-36092e5a6e9a/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_6bd400ac-a770-40b7-b3e4-36092e5a6e9a/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_6bd400ac-a770-40b7-b3e4-36092e5a6e9a/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/systemc/kundu2.cil.c -s /tmp/vcloud-vcloud-master/worker/run_dir_6bd400ac-a770-40b7-b3e4-36092e5a6e9a/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_6bd400ac-a770-40b7-b3e4-36092e5a6e9a/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 2559ce56d5bdfaeec5255956226223494fe099f5 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 11:35:38,861 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 11:35:38,863 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 11:35:38,870 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 11:35:38,871 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 11:35:38,871 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 11:35:38,872 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 11:35:38,874 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 11:35:38,875 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 11:35:38,876 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 11:35:38,876 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 11:35:38,877 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 11:35:38,877 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 11:35:38,878 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 11:35:38,879 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 11:35:38,880 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 11:35:38,880 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 11:35:38,881 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 11:35:38,883 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 11:35:38,884 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 11:35:38,885 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 11:35:38,886 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 11:35:38,886 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 11:35:38,887 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 11:35:38,888 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 11:35:38,888 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 11:35:38,889 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 11:35:38,889 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 11:35:38,889 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 11:35:38,890 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 11:35:38,890 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 11:35:38,891 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 11:35:38,891 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 11:35:38,892 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 11:35:38,893 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 11:35:38,893 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 11:35:38,893 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 11:35:38,894 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 11:35:38,894 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 11:35:38,894 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 11:35:38,895 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 11:35:38,896 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_6bd400ac-a770-40b7-b3e4-36092e5a6e9a/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 11:35:38,908 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 11:35:38,908 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 11:35:38,909 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 11:35:38,909 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 11:35:38,910 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 11:35:38,910 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 11:35:38,910 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 11:35:38,910 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 11:35:38,910 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 11:35:38,911 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 11:35:38,911 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 11:35:38,911 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 11:35:38,911 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 11:35:38,911 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 11:35:38,911 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 11:35:38,912 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 11:35:38,912 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 11:35:38,912 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 11:35:38,912 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 11:35:38,912 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 11:35:38,913 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 11:35:38,913 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 11:35:38,913 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 11:35:38,913 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 11:35:38,913 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 11:35:38,913 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 11:35:38,914 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 11:35:38,914 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 11:35:38,914 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 11:35:38,914 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_6bd400ac-a770-40b7-b3e4-36092e5a6e9a/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2559ce56d5bdfaeec5255956226223494fe099f5 [2019-12-07 11:35:39,014 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 11:35:39,025 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 11:35:39,027 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 11:35:39,029 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 11:35:39,029 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 11:35:39,030 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_6bd400ac-a770-40b7-b3e4-36092e5a6e9a/bin/uautomizer/../../sv-benchmarks/c/systemc/kundu2.cil.c [2019-12-07 11:35:39,076 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_6bd400ac-a770-40b7-b3e4-36092e5a6e9a/bin/uautomizer/data/164cdda01/9ee0e786e70c46e590ac6e015c22e26e/FLAG44ee046fd [2019-12-07 11:35:39,406 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 11:35:39,406 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_6bd400ac-a770-40b7-b3e4-36092e5a6e9a/sv-benchmarks/c/systemc/kundu2.cil.c [2019-12-07 11:35:39,412 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_6bd400ac-a770-40b7-b3e4-36092e5a6e9a/bin/uautomizer/data/164cdda01/9ee0e786e70c46e590ac6e015c22e26e/FLAG44ee046fd [2019-12-07 11:35:39,836 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_6bd400ac-a770-40b7-b3e4-36092e5a6e9a/bin/uautomizer/data/164cdda01/9ee0e786e70c46e590ac6e015c22e26e [2019-12-07 11:35:39,837 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 11:35:39,838 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 11:35:39,839 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 11:35:39,839 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 11:35:39,841 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 11:35:39,842 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 11:35:39" (1/1) ... [2019-12-07 11:35:39,843 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5a1e11ee and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:35:39, skipping insertion in model container [2019-12-07 11:35:39,843 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 11:35:39" (1/1) ... [2019-12-07 11:35:39,848 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 11:35:39,870 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 11:35:40,027 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 11:35:40,030 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 11:35:40,056 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 11:35:40,069 INFO L208 MainTranslator]: Completed translation [2019-12-07 11:35:40,070 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:35:40 WrapperNode [2019-12-07 11:35:40,070 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 11:35:40,070 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 11:35:40,070 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 11:35:40,071 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 11:35:40,076 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:35:40" (1/1) ... [2019-12-07 11:35:40,081 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:35:40" (1/1) ... [2019-12-07 11:35:40,104 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 11:35:40,104 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 11:35:40,104 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 11:35:40,104 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 11:35:40,110 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:35:40" (1/1) ... [2019-12-07 11:35:40,110 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:35:40" (1/1) ... [2019-12-07 11:35:40,112 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:35:40" (1/1) ... [2019-12-07 11:35:40,112 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:35:40" (1/1) ... [2019-12-07 11:35:40,118 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:35:40" (1/1) ... [2019-12-07 11:35:40,124 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:35:40" (1/1) ... [2019-12-07 11:35:40,126 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:35:40" (1/1) ... [2019-12-07 11:35:40,130 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 11:35:40,130 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 11:35:40,130 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 11:35:40,130 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 11:35:40,131 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:35:40" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6bd400ac-a770-40b7-b3e4-36092e5a6e9a/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 11:35:40,169 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 11:35:40,169 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 11:35:40,523 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 11:35:40,523 INFO L287 CfgBuilder]: Removed 95 assume(true) statements. [2019-12-07 11:35:40,524 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 11:35:40 BoogieIcfgContainer [2019-12-07 11:35:40,524 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 11:35:40,525 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 11:35:40,525 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 11:35:40,527 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 11:35:40,527 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 11:35:39" (1/3) ... [2019-12-07 11:35:40,528 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@13a980e9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 11:35:40, skipping insertion in model container [2019-12-07 11:35:40,528 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 11:35:40" (2/3) ... [2019-12-07 11:35:40,528 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@13a980e9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 11:35:40, skipping insertion in model container [2019-12-07 11:35:40,528 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 11:35:40" (3/3) ... [2019-12-07 11:35:40,529 INFO L109 eAbstractionObserver]: Analyzing ICFG kundu2.cil.c [2019-12-07 11:35:40,536 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 11:35:40,540 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 4 error locations. [2019-12-07 11:35:40,549 INFO L249 AbstractCegarLoop]: Starting to check reachability of 4 error locations. [2019-12-07 11:35:40,566 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 11:35:40,566 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 11:35:40,567 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 11:35:40,567 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 11:35:40,567 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 11:35:40,567 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 11:35:40,567 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 11:35:40,567 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 11:35:40,581 INFO L276 IsEmpty]: Start isEmpty. Operand 180 states. [2019-12-07 11:35:40,586 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2019-12-07 11:35:40,586 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:35:40,586 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:35:40,587 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:35:40,590 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:35:40,590 INFO L82 PathProgramCache]: Analyzing trace with hash 805260304, now seen corresponding path program 1 times [2019-12-07 11:35:40,596 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:35:40,596 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [287058752] [2019-12-07 11:35:40,596 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:35:40,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:35:40,696 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:35:40,696 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [287058752] [2019-12-07 11:35:40,696 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:35:40,697 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:35:40,698 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1397080774] [2019-12-07 11:35:40,701 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:35:40,701 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:35:40,709 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:35:40,710 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:35:40,711 INFO L87 Difference]: Start difference. First operand 180 states. Second operand 3 states. [2019-12-07 11:35:40,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:35:40,748 INFO L93 Difference]: Finished difference Result 354 states and 540 transitions. [2019-12-07 11:35:40,749 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:35:40,750 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 40 [2019-12-07 11:35:40,750 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:35:40,759 INFO L225 Difference]: With dead ends: 354 [2019-12-07 11:35:40,759 INFO L226 Difference]: Without dead ends: 175 [2019-12-07 11:35:40,762 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:35:40,774 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 175 states. [2019-12-07 11:35:40,798 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 175 to 175. [2019-12-07 11:35:40,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 175 states. [2019-12-07 11:35:40,801 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 175 states to 175 states and 257 transitions. [2019-12-07 11:35:40,801 INFO L78 Accepts]: Start accepts. Automaton has 175 states and 257 transitions. Word has length 40 [2019-12-07 11:35:40,802 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:35:40,802 INFO L462 AbstractCegarLoop]: Abstraction has 175 states and 257 transitions. [2019-12-07 11:35:40,802 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:35:40,802 INFO L276 IsEmpty]: Start isEmpty. Operand 175 states and 257 transitions. [2019-12-07 11:35:40,803 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2019-12-07 11:35:40,803 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:35:40,803 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:35:40,803 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:35:40,804 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:35:40,804 INFO L82 PathProgramCache]: Analyzing trace with hash 1199627090, now seen corresponding path program 1 times [2019-12-07 11:35:40,804 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:35:40,804 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1098234108] [2019-12-07 11:35:40,804 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:35:40,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:35:40,840 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:35:40,840 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1098234108] [2019-12-07 11:35:40,840 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:35:40,840 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:35:40,841 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [649007606] [2019-12-07 11:35:40,842 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:35:40,842 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:35:40,842 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:35:40,842 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:35:40,843 INFO L87 Difference]: Start difference. First operand 175 states and 257 transitions. Second operand 3 states. [2019-12-07 11:35:40,889 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:35:40,889 INFO L93 Difference]: Finished difference Result 477 states and 700 transitions. [2019-12-07 11:35:40,889 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:35:40,890 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 40 [2019-12-07 11:35:40,890 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:35:40,892 INFO L225 Difference]: With dead ends: 477 [2019-12-07 11:35:40,892 INFO L226 Difference]: Without dead ends: 317 [2019-12-07 11:35:40,893 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:35:40,894 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 317 states. [2019-12-07 11:35:40,916 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 317 to 294. [2019-12-07 11:35:40,916 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 294 states. [2019-12-07 11:35:40,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 294 states to 294 states and 434 transitions. [2019-12-07 11:35:40,917 INFO L78 Accepts]: Start accepts. Automaton has 294 states and 434 transitions. Word has length 40 [2019-12-07 11:35:40,917 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:35:40,917 INFO L462 AbstractCegarLoop]: Abstraction has 294 states and 434 transitions. [2019-12-07 11:35:40,917 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:35:40,917 INFO L276 IsEmpty]: Start isEmpty. Operand 294 states and 434 transitions. [2019-12-07 11:35:40,918 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2019-12-07 11:35:40,918 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:35:40,919 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:35:40,919 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:35:40,919 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:35:40,919 INFO L82 PathProgramCache]: Analyzing trace with hash -472890541, now seen corresponding path program 1 times [2019-12-07 11:35:40,919 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:35:40,919 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1289871133] [2019-12-07 11:35:40,919 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:35:40,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:35:40,951 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:35:40,951 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1289871133] [2019-12-07 11:35:40,951 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:35:40,951 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:35:40,952 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [736042281] [2019-12-07 11:35:40,952 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:35:40,952 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:35:40,952 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:35:40,952 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:35:40,952 INFO L87 Difference]: Start difference. First operand 294 states and 434 transitions. Second operand 3 states. [2019-12-07 11:35:41,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:35:41,005 INFO L93 Difference]: Finished difference Result 821 states and 1211 transitions. [2019-12-07 11:35:41,005 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:35:41,005 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 40 [2019-12-07 11:35:41,005 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:35:41,008 INFO L225 Difference]: With dead ends: 821 [2019-12-07 11:35:41,008 INFO L226 Difference]: Without dead ends: 548 [2019-12-07 11:35:41,010 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:35:41,011 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 548 states. [2019-12-07 11:35:41,035 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 548 to 524. [2019-12-07 11:35:41,035 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 524 states. [2019-12-07 11:35:41,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 524 states to 524 states and 761 transitions. [2019-12-07 11:35:41,038 INFO L78 Accepts]: Start accepts. Automaton has 524 states and 761 transitions. Word has length 40 [2019-12-07 11:35:41,038 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:35:41,038 INFO L462 AbstractCegarLoop]: Abstraction has 524 states and 761 transitions. [2019-12-07 11:35:41,038 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:35:41,038 INFO L276 IsEmpty]: Start isEmpty. Operand 524 states and 761 transitions. [2019-12-07 11:35:41,040 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2019-12-07 11:35:41,040 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:35:41,040 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:35:41,040 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:35:41,040 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:35:41,041 INFO L82 PathProgramCache]: Analyzing trace with hash -2040159492, now seen corresponding path program 1 times [2019-12-07 11:35:41,041 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:35:41,041 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2022625210] [2019-12-07 11:35:41,041 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:35:41,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:35:41,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:35:41,100 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2022625210] [2019-12-07 11:35:41,101 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:35:41,101 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 11:35:41,101 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [965709928] [2019-12-07 11:35:41,101 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 11:35:41,101 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:35:41,102 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 11:35:41,102 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:35:41,102 INFO L87 Difference]: Start difference. First operand 524 states and 761 transitions. Second operand 5 states. [2019-12-07 11:35:41,237 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:35:41,238 INFO L93 Difference]: Finished difference Result 1952 states and 2826 transitions. [2019-12-07 11:35:41,238 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 11:35:41,238 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 41 [2019-12-07 11:35:41,238 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:35:41,244 INFO L225 Difference]: With dead ends: 1952 [2019-12-07 11:35:41,244 INFO L226 Difference]: Without dead ends: 1441 [2019-12-07 11:35:41,246 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 11:35:41,248 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1441 states. [2019-12-07 11:35:41,279 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1441 to 563. [2019-12-07 11:35:41,279 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 563 states. [2019-12-07 11:35:41,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 563 states and 800 transitions. [2019-12-07 11:35:41,281 INFO L78 Accepts]: Start accepts. Automaton has 563 states and 800 transitions. Word has length 41 [2019-12-07 11:35:41,281 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:35:41,281 INFO L462 AbstractCegarLoop]: Abstraction has 563 states and 800 transitions. [2019-12-07 11:35:41,281 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 11:35:41,281 INFO L276 IsEmpty]: Start isEmpty. Operand 563 states and 800 transitions. [2019-12-07 11:35:41,282 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2019-12-07 11:35:41,283 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:35:41,283 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:35:41,283 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:35:41,283 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:35:41,284 INFO L82 PathProgramCache]: Analyzing trace with hash -2017527238, now seen corresponding path program 1 times [2019-12-07 11:35:41,284 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:35:41,284 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1884912906] [2019-12-07 11:35:41,284 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:35:41,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:35:41,341 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:35:41,341 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1884912906] [2019-12-07 11:35:41,341 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:35:41,341 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 11:35:41,342 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1787160581] [2019-12-07 11:35:41,342 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 11:35:41,342 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:35:41,342 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 11:35:41,342 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:35:41,342 INFO L87 Difference]: Start difference. First operand 563 states and 800 transitions. Second operand 5 states. [2019-12-07 11:35:41,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:35:41,463 INFO L93 Difference]: Finished difference Result 1778 states and 2558 transitions. [2019-12-07 11:35:41,463 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 11:35:41,463 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 41 [2019-12-07 11:35:41,464 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:35:41,469 INFO L225 Difference]: With dead ends: 1778 [2019-12-07 11:35:41,470 INFO L226 Difference]: Without dead ends: 1237 [2019-12-07 11:35:41,471 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 11:35:41,473 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1237 states. [2019-12-07 11:35:41,505 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1237 to 581. [2019-12-07 11:35:41,505 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 581 states. [2019-12-07 11:35:41,507 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 581 states to 581 states and 813 transitions. [2019-12-07 11:35:41,507 INFO L78 Accepts]: Start accepts. Automaton has 581 states and 813 transitions. Word has length 41 [2019-12-07 11:35:41,508 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:35:41,508 INFO L462 AbstractCegarLoop]: Abstraction has 581 states and 813 transitions. [2019-12-07 11:35:41,508 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 11:35:41,508 INFO L276 IsEmpty]: Start isEmpty. Operand 581 states and 813 transitions. [2019-12-07 11:35:41,509 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2019-12-07 11:35:41,509 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:35:41,509 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:35:41,510 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:35:41,510 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:35:41,510 INFO L82 PathProgramCache]: Analyzing trace with hash 2143426552, now seen corresponding path program 1 times [2019-12-07 11:35:41,510 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:35:41,510 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2049092215] [2019-12-07 11:35:41,511 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:35:41,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:35:41,570 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:35:41,570 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2049092215] [2019-12-07 11:35:41,570 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:35:41,570 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 11:35:41,571 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1508826809] [2019-12-07 11:35:41,571 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 11:35:41,571 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:35:41,571 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 11:35:41,571 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:35:41,571 INFO L87 Difference]: Start difference. First operand 581 states and 813 transitions. Second operand 5 states. [2019-12-07 11:35:41,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:35:41,685 INFO L93 Difference]: Finished difference Result 1776 states and 2524 transitions. [2019-12-07 11:35:41,685 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 11:35:41,685 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 41 [2019-12-07 11:35:41,685 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:35:41,690 INFO L225 Difference]: With dead ends: 1776 [2019-12-07 11:35:41,690 INFO L226 Difference]: Without dead ends: 1224 [2019-12-07 11:35:41,692 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 11:35:41,693 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1224 states. [2019-12-07 11:35:41,721 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1224 to 596. [2019-12-07 11:35:41,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 596 states. [2019-12-07 11:35:41,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 596 states to 596 states and 822 transitions. [2019-12-07 11:35:41,723 INFO L78 Accepts]: Start accepts. Automaton has 596 states and 822 transitions. Word has length 41 [2019-12-07 11:35:41,723 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:35:41,723 INFO L462 AbstractCegarLoop]: Abstraction has 596 states and 822 transitions. [2019-12-07 11:35:41,723 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 11:35:41,723 INFO L276 IsEmpty]: Start isEmpty. Operand 596 states and 822 transitions. [2019-12-07 11:35:41,724 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2019-12-07 11:35:41,724 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:35:41,724 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:35:41,724 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:35:41,725 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:35:41,725 INFO L82 PathProgramCache]: Analyzing trace with hash 555078650, now seen corresponding path program 1 times [2019-12-07 11:35:41,725 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:35:41,725 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1541763496] [2019-12-07 11:35:41,725 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:35:41,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:35:41,768 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:35:41,769 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1541763496] [2019-12-07 11:35:41,769 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:35:41,769 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 11:35:41,769 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [655380391] [2019-12-07 11:35:41,770 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 11:35:41,770 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:35:41,770 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 11:35:41,770 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 11:35:41,770 INFO L87 Difference]: Start difference. First operand 596 states and 822 transitions. Second operand 4 states. [2019-12-07 11:35:41,904 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:35:41,905 INFO L93 Difference]: Finished difference Result 2598 states and 3612 transitions. [2019-12-07 11:35:41,905 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 11:35:41,905 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 41 [2019-12-07 11:35:41,905 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:35:41,913 INFO L225 Difference]: With dead ends: 2598 [2019-12-07 11:35:41,913 INFO L226 Difference]: Without dead ends: 2031 [2019-12-07 11:35:41,914 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:35:41,917 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2031 states. [2019-12-07 11:35:41,966 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2031 to 1038. [2019-12-07 11:35:41,966 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1038 states. [2019-12-07 11:35:41,968 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1038 states to 1038 states and 1438 transitions. [2019-12-07 11:35:41,969 INFO L78 Accepts]: Start accepts. Automaton has 1038 states and 1438 transitions. Word has length 41 [2019-12-07 11:35:41,969 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:35:41,969 INFO L462 AbstractCegarLoop]: Abstraction has 1038 states and 1438 transitions. [2019-12-07 11:35:41,969 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 11:35:41,969 INFO L276 IsEmpty]: Start isEmpty. Operand 1038 states and 1438 transitions. [2019-12-07 11:35:41,970 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2019-12-07 11:35:41,970 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:35:41,970 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:35:41,970 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:35:41,971 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:35:41,971 INFO L82 PathProgramCache]: Analyzing trace with hash 2112971018, now seen corresponding path program 1 times [2019-12-07 11:35:41,971 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:35:41,971 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1152643840] [2019-12-07 11:35:41,971 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:35:41,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:35:42,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:35:42,030 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1152643840] [2019-12-07 11:35:42,030 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:35:42,030 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 11:35:42,031 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1535326898] [2019-12-07 11:35:42,031 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 11:35:42,031 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:35:42,031 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 11:35:42,031 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:35:42,031 INFO L87 Difference]: Start difference. First operand 1038 states and 1438 transitions. Second operand 5 states. [2019-12-07 11:35:42,341 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:35:42,341 INFO L93 Difference]: Finished difference Result 5034 states and 7008 transitions. [2019-12-07 11:35:42,341 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 11:35:42,341 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 48 [2019-12-07 11:35:42,341 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:35:42,356 INFO L225 Difference]: With dead ends: 5034 [2019-12-07 11:35:42,356 INFO L226 Difference]: Without dead ends: 4025 [2019-12-07 11:35:42,358 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 11:35:42,362 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4025 states. [2019-12-07 11:35:42,462 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4025 to 2045. [2019-12-07 11:35:42,462 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2045 states. [2019-12-07 11:35:42,467 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2045 states to 2045 states and 2840 transitions. [2019-12-07 11:35:42,467 INFO L78 Accepts]: Start accepts. Automaton has 2045 states and 2840 transitions. Word has length 48 [2019-12-07 11:35:42,467 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:35:42,467 INFO L462 AbstractCegarLoop]: Abstraction has 2045 states and 2840 transitions. [2019-12-07 11:35:42,467 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 11:35:42,467 INFO L276 IsEmpty]: Start isEmpty. Operand 2045 states and 2840 transitions. [2019-12-07 11:35:42,468 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2019-12-07 11:35:42,468 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:35:42,468 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:35:42,468 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:35:42,468 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:35:42,468 INFO L82 PathProgramCache]: Analyzing trace with hash 1420212558, now seen corresponding path program 1 times [2019-12-07 11:35:42,468 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:35:42,469 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [386922069] [2019-12-07 11:35:42,469 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:35:42,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:35:42,488 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:35:42,489 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [386922069] [2019-12-07 11:35:42,489 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:35:42,489 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:35:42,489 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1619579257] [2019-12-07 11:35:42,489 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:35:42,489 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:35:42,489 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:35:42,490 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:35:42,490 INFO L87 Difference]: Start difference. First operand 2045 states and 2840 transitions. Second operand 3 states. [2019-12-07 11:35:42,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:35:42,697 INFO L93 Difference]: Finished difference Result 5767 states and 7979 transitions. [2019-12-07 11:35:42,698 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:35:42,698 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 52 [2019-12-07 11:35:42,698 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:35:42,711 INFO L225 Difference]: With dead ends: 5767 [2019-12-07 11:35:42,711 INFO L226 Difference]: Without dead ends: 3751 [2019-12-07 11:35:42,713 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:35:42,717 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3751 states. [2019-12-07 11:35:42,890 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3751 to 3699. [2019-12-07 11:35:42,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3699 states. [2019-12-07 11:35:42,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3699 states to 3699 states and 5050 transitions. [2019-12-07 11:35:42,898 INFO L78 Accepts]: Start accepts. Automaton has 3699 states and 5050 transitions. Word has length 52 [2019-12-07 11:35:42,898 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:35:42,899 INFO L462 AbstractCegarLoop]: Abstraction has 3699 states and 5050 transitions. [2019-12-07 11:35:42,899 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:35:42,899 INFO L276 IsEmpty]: Start isEmpty. Operand 3699 states and 5050 transitions. [2019-12-07 11:35:42,899 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2019-12-07 11:35:42,899 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:35:42,900 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:35:42,900 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:35:42,900 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:35:42,900 INFO L82 PathProgramCache]: Analyzing trace with hash -1475283929, now seen corresponding path program 1 times [2019-12-07 11:35:42,900 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:35:42,900 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [752506475] [2019-12-07 11:35:42,900 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:35:42,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:35:42,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:35:42,939 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [752506475] [2019-12-07 11:35:42,940 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:35:42,940 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 11:35:42,940 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [78117680] [2019-12-07 11:35:42,940 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 11:35:42,940 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:35:42,940 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 11:35:42,940 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2019-12-07 11:35:42,940 INFO L87 Difference]: Start difference. First operand 3699 states and 5050 transitions. Second operand 6 states. [2019-12-07 11:35:43,401 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:35:43,401 INFO L93 Difference]: Finished difference Result 12040 states and 16437 transitions. [2019-12-07 11:35:43,402 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 11:35:43,402 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 53 [2019-12-07 11:35:43,402 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:35:43,430 INFO L225 Difference]: With dead ends: 12040 [2019-12-07 11:35:43,430 INFO L226 Difference]: Without dead ends: 8370 [2019-12-07 11:35:43,435 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2019-12-07 11:35:43,442 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8370 states. [2019-12-07 11:35:43,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8370 to 5490. [2019-12-07 11:35:43,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5490 states. [2019-12-07 11:35:43,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5490 states to 5490 states and 7504 transitions. [2019-12-07 11:35:43,766 INFO L78 Accepts]: Start accepts. Automaton has 5490 states and 7504 transitions. Word has length 53 [2019-12-07 11:35:43,766 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:35:43,766 INFO L462 AbstractCegarLoop]: Abstraction has 5490 states and 7504 transitions. [2019-12-07 11:35:43,766 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 11:35:43,766 INFO L276 IsEmpty]: Start isEmpty. Operand 5490 states and 7504 transitions. [2019-12-07 11:35:43,767 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2019-12-07 11:35:43,767 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:35:43,767 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:35:43,767 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:35:43,767 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:35:43,767 INFO L82 PathProgramCache]: Analyzing trace with hash 1170295472, now seen corresponding path program 1 times [2019-12-07 11:35:43,767 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:35:43,768 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [205491043] [2019-12-07 11:35:43,768 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:35:43,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:35:43,785 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2019-12-07 11:35:43,786 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [205491043] [2019-12-07 11:35:43,786 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:35:43,786 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:35:43,786 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1588824343] [2019-12-07 11:35:43,786 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:35:43,786 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:35:43,786 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:35:43,787 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:35:43,787 INFO L87 Difference]: Start difference. First operand 5490 states and 7504 transitions. Second operand 3 states. [2019-12-07 11:35:44,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:35:44,286 INFO L93 Difference]: Finished difference Result 15843 states and 21496 transitions. [2019-12-07 11:35:44,287 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:35:44,287 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 57 [2019-12-07 11:35:44,287 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:35:44,309 INFO L225 Difference]: With dead ends: 15843 [2019-12-07 11:35:44,309 INFO L226 Difference]: Without dead ends: 10382 [2019-12-07 11:35:44,313 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:35:44,321 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10382 states. [2019-12-07 11:35:44,800 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10382 to 10376. [2019-12-07 11:35:44,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10376 states. [2019-12-07 11:35:44,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10376 states to 10376 states and 13831 transitions. [2019-12-07 11:35:44,813 INFO L78 Accepts]: Start accepts. Automaton has 10376 states and 13831 transitions. Word has length 57 [2019-12-07 11:35:44,813 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:35:44,813 INFO L462 AbstractCegarLoop]: Abstraction has 10376 states and 13831 transitions. [2019-12-07 11:35:44,813 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:35:44,813 INFO L276 IsEmpty]: Start isEmpty. Operand 10376 states and 13831 transitions. [2019-12-07 11:35:44,815 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2019-12-07 11:35:44,815 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:35:44,815 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:35:44,815 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:35:44,815 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:35:44,815 INFO L82 PathProgramCache]: Analyzing trace with hash 171117839, now seen corresponding path program 1 times [2019-12-07 11:35:44,815 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:35:44,816 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1292771974] [2019-12-07 11:35:44,816 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:35:44,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:35:44,851 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:35:44,851 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1292771974] [2019-12-07 11:35:44,851 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:35:44,851 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 11:35:44,852 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [147813074] [2019-12-07 11:35:44,852 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 11:35:44,852 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:35:44,852 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 11:35:44,853 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:35:44,853 INFO L87 Difference]: Start difference. First operand 10376 states and 13831 transitions. Second operand 5 states. [2019-12-07 11:35:45,548 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:35:45,548 INFO L93 Difference]: Finished difference Result 24226 states and 32344 transitions. [2019-12-07 11:35:45,549 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 11:35:45,549 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 58 [2019-12-07 11:35:45,549 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:35:45,566 INFO L225 Difference]: With dead ends: 24226 [2019-12-07 11:35:45,566 INFO L226 Difference]: Without dead ends: 13904 [2019-12-07 11:35:45,575 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:35:45,587 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13904 states. [2019-12-07 11:35:46,225 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13904 to 13830. [2019-12-07 11:35:46,225 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13830 states. [2019-12-07 11:35:46,239 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13830 states to 13830 states and 18427 transitions. [2019-12-07 11:35:46,239 INFO L78 Accepts]: Start accepts. Automaton has 13830 states and 18427 transitions. Word has length 58 [2019-12-07 11:35:46,239 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:35:46,239 INFO L462 AbstractCegarLoop]: Abstraction has 13830 states and 18427 transitions. [2019-12-07 11:35:46,239 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 11:35:46,239 INFO L276 IsEmpty]: Start isEmpty. Operand 13830 states and 18427 transitions. [2019-12-07 11:35:46,241 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2019-12-07 11:35:46,241 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:35:46,241 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:35:46,241 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:35:46,241 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:35:46,241 INFO L82 PathProgramCache]: Analyzing trace with hash 1927952390, now seen corresponding path program 1 times [2019-12-07 11:35:46,241 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:35:46,241 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1838476781] [2019-12-07 11:35:46,242 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:35:46,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:35:46,259 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:35:46,259 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1838476781] [2019-12-07 11:35:46,260 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:35:46,260 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:35:46,260 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1685656667] [2019-12-07 11:35:46,260 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:35:46,260 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:35:46,260 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:35:46,260 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:35:46,260 INFO L87 Difference]: Start difference. First operand 13830 states and 18427 transitions. Second operand 3 states. [2019-12-07 11:35:47,383 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:35:47,383 INFO L93 Difference]: Finished difference Result 36085 states and 48046 transitions. [2019-12-07 11:35:47,384 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:35:47,384 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 59 [2019-12-07 11:35:47,384 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:35:47,403 INFO L225 Difference]: With dead ends: 36085 [2019-12-07 11:35:47,403 INFO L226 Difference]: Without dead ends: 22309 [2019-12-07 11:35:47,412 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:35:47,428 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22309 states. [2019-12-07 11:35:48,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22309 to 19285. [2019-12-07 11:35:48,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19285 states. [2019-12-07 11:35:48,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19285 states to 19285 states and 25656 transitions. [2019-12-07 11:35:48,339 INFO L78 Accepts]: Start accepts. Automaton has 19285 states and 25656 transitions. Word has length 59 [2019-12-07 11:35:48,339 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:35:48,339 INFO L462 AbstractCegarLoop]: Abstraction has 19285 states and 25656 transitions. [2019-12-07 11:35:48,340 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:35:48,340 INFO L276 IsEmpty]: Start isEmpty. Operand 19285 states and 25656 transitions. [2019-12-07 11:35:48,342 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2019-12-07 11:35:48,342 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:35:48,342 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:35:48,343 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:35:48,343 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:35:48,343 INFO L82 PathProgramCache]: Analyzing trace with hash -348509553, now seen corresponding path program 1 times [2019-12-07 11:35:48,343 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:35:48,343 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1176929589] [2019-12-07 11:35:48,343 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:35:48,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:35:48,397 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:35:48,398 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1176929589] [2019-12-07 11:35:48,398 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:35:48,398 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 11:35:48,398 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [251696429] [2019-12-07 11:35:48,398 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 11:35:48,398 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:35:48,398 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 11:35:48,399 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 11:35:48,399 INFO L87 Difference]: Start difference. First operand 19285 states and 25656 transitions. Second operand 6 states. [2019-12-07 11:35:50,796 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:35:50,796 INFO L93 Difference]: Finished difference Result 64295 states and 85620 transitions. [2019-12-07 11:35:50,796 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 11:35:50,797 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 61 [2019-12-07 11:35:50,797 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:35:50,834 INFO L225 Difference]: With dead ends: 64295 [2019-12-07 11:35:50,834 INFO L226 Difference]: Without dead ends: 47099 [2019-12-07 11:35:50,853 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2019-12-07 11:35:50,886 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47099 states. [2019-12-07 11:35:52,279 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47099 to 25501. [2019-12-07 11:35:52,279 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25501 states. [2019-12-07 11:35:52,303 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25501 states to 25501 states and 34022 transitions. [2019-12-07 11:35:52,304 INFO L78 Accepts]: Start accepts. Automaton has 25501 states and 34022 transitions. Word has length 61 [2019-12-07 11:35:52,304 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:35:52,304 INFO L462 AbstractCegarLoop]: Abstraction has 25501 states and 34022 transitions. [2019-12-07 11:35:52,304 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 11:35:52,304 INFO L276 IsEmpty]: Start isEmpty. Operand 25501 states and 34022 transitions. [2019-12-07 11:35:52,307 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 11:35:52,307 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:35:52,307 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:35:52,307 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:35:52,307 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:35:52,307 INFO L82 PathProgramCache]: Analyzing trace with hash 807662601, now seen corresponding path program 1 times [2019-12-07 11:35:52,307 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:35:52,308 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [391156040] [2019-12-07 11:35:52,308 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:35:52,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:35:52,334 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:35:52,334 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [391156040] [2019-12-07 11:35:52,334 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:35:52,334 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:35:52,334 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1443319984] [2019-12-07 11:35:52,334 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:35:52,334 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:35:52,335 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:35:52,335 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:35:52,335 INFO L87 Difference]: Start difference. First operand 25501 states and 34022 transitions. Second operand 3 states. [2019-12-07 11:35:53,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:35:53,642 INFO L93 Difference]: Finished difference Result 50906 states and 67931 transitions. [2019-12-07 11:35:53,643 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:35:53,643 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 65 [2019-12-07 11:35:53,643 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:35:53,663 INFO L225 Difference]: With dead ends: 50906 [2019-12-07 11:35:53,663 INFO L226 Difference]: Without dead ends: 25505 [2019-12-07 11:35:53,679 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:35:53,696 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25505 states. [2019-12-07 11:35:55,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25505 to 25501. [2019-12-07 11:35:55,103 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25501 states. [2019-12-07 11:35:55,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25501 states to 25501 states and 33819 transitions. [2019-12-07 11:35:55,127 INFO L78 Accepts]: Start accepts. Automaton has 25501 states and 33819 transitions. Word has length 65 [2019-12-07 11:35:55,127 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:35:55,127 INFO L462 AbstractCegarLoop]: Abstraction has 25501 states and 33819 transitions. [2019-12-07 11:35:55,127 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:35:55,127 INFO L276 IsEmpty]: Start isEmpty. Operand 25501 states and 33819 transitions. [2019-12-07 11:35:55,130 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 11:35:55,130 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:35:55,130 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:35:55,130 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:35:55,130 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:35:55,130 INFO L82 PathProgramCache]: Analyzing trace with hash 1009486535, now seen corresponding path program 1 times [2019-12-07 11:35:55,130 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:35:55,130 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1572861024] [2019-12-07 11:35:55,130 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:35:55,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:35:55,153 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2019-12-07 11:35:55,153 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1572861024] [2019-12-07 11:35:55,153 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:35:55,153 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:35:55,154 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1530263079] [2019-12-07 11:35:55,154 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:35:55,154 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:35:55,154 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:35:55,154 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:35:55,154 INFO L87 Difference]: Start difference. First operand 25501 states and 33819 transitions. Second operand 3 states. [2019-12-07 11:35:56,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:35:56,375 INFO L93 Difference]: Finished difference Result 27414 states and 36203 transitions. [2019-12-07 11:35:56,376 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:35:56,376 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 65 [2019-12-07 11:35:56,376 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:35:56,396 INFO L225 Difference]: With dead ends: 27414 [2019-12-07 11:35:56,396 INFO L226 Difference]: Without dead ends: 25455 [2019-12-07 11:35:56,402 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:35:56,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25455 states. [2019-12-07 11:35:57,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25455 to 25455. [2019-12-07 11:35:57,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25455 states. [2019-12-07 11:35:57,739 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25455 states to 25455 states and 33765 transitions. [2019-12-07 11:35:57,739 INFO L78 Accepts]: Start accepts. Automaton has 25455 states and 33765 transitions. Word has length 65 [2019-12-07 11:35:57,739 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:35:57,739 INFO L462 AbstractCegarLoop]: Abstraction has 25455 states and 33765 transitions. [2019-12-07 11:35:57,739 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:35:57,739 INFO L276 IsEmpty]: Start isEmpty. Operand 25455 states and 33765 transitions. [2019-12-07 11:35:57,741 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 11:35:57,742 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:35:57,742 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:35:57,742 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:35:57,742 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:35:57,742 INFO L82 PathProgramCache]: Analyzing trace with hash 1172878516, now seen corresponding path program 1 times [2019-12-07 11:35:57,742 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:35:57,742 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [883387758] [2019-12-07 11:35:57,742 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:35:57,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:35:57,766 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:35:57,766 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [883387758] [2019-12-07 11:35:57,766 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:35:57,766 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:35:57,766 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [585394902] [2019-12-07 11:35:57,766 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:35:57,767 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:35:57,767 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:35:57,767 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:35:57,767 INFO L87 Difference]: Start difference. First operand 25455 states and 33765 transitions. Second operand 3 states. [2019-12-07 11:35:59,163 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:35:59,164 INFO L93 Difference]: Finished difference Result 50862 states and 67472 transitions. [2019-12-07 11:35:59,164 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:35:59,164 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 66 [2019-12-07 11:35:59,164 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:35:59,187 INFO L225 Difference]: With dead ends: 50862 [2019-12-07 11:35:59,187 INFO L226 Difference]: Without dead ends: 25461 [2019-12-07 11:35:59,205 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:35:59,223 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25461 states. [2019-12-07 11:36:00,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25461 to 25455. [2019-12-07 11:36:00,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25455 states. [2019-12-07 11:36:00,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25455 states to 25455 states and 33293 transitions. [2019-12-07 11:36:00,592 INFO L78 Accepts]: Start accepts. Automaton has 25455 states and 33293 transitions. Word has length 66 [2019-12-07 11:36:00,592 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:36:00,592 INFO L462 AbstractCegarLoop]: Abstraction has 25455 states and 33293 transitions. [2019-12-07 11:36:00,592 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:36:00,592 INFO L276 IsEmpty]: Start isEmpty. Operand 25455 states and 33293 transitions. [2019-12-07 11:36:00,594 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 11:36:00,594 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:36:00,594 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:36:00,594 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:36:00,594 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:36:00,595 INFO L82 PathProgramCache]: Analyzing trace with hash 2075083770, now seen corresponding path program 1 times [2019-12-07 11:36:00,595 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:36:00,595 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [909681963] [2019-12-07 11:36:00,595 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:36:00,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:36:00,622 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:36:00,623 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [909681963] [2019-12-07 11:36:00,623 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:36:00,623 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:36:00,623 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [779591833] [2019-12-07 11:36:00,623 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:36:00,623 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:36:00,623 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:36:00,623 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:36:00,624 INFO L87 Difference]: Start difference. First operand 25455 states and 33293 transitions. Second operand 3 states. [2019-12-07 11:36:01,998 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:36:01,998 INFO L93 Difference]: Finished difference Result 50862 states and 66528 transitions. [2019-12-07 11:36:01,999 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:36:01,999 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 68 [2019-12-07 11:36:01,999 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:36:02,019 INFO L225 Difference]: With dead ends: 50862 [2019-12-07 11:36:02,020 INFO L226 Difference]: Without dead ends: 25461 [2019-12-07 11:36:02,031 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:36:02,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25461 states. [2019-12-07 11:36:03,317 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25461 to 25455. [2019-12-07 11:36:03,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25455 states. [2019-12-07 11:36:03,342 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25455 states to 25455 states and 32998 transitions. [2019-12-07 11:36:03,342 INFO L78 Accepts]: Start accepts. Automaton has 25455 states and 32998 transitions. Word has length 68 [2019-12-07 11:36:03,342 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:36:03,342 INFO L462 AbstractCegarLoop]: Abstraction has 25455 states and 32998 transitions. [2019-12-07 11:36:03,342 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:36:03,342 INFO L276 IsEmpty]: Start isEmpty. Operand 25455 states and 32998 transitions. [2019-12-07 11:36:03,344 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2019-12-07 11:36:03,344 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:36:03,344 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:36:03,344 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:36:03,344 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:36:03,344 INFO L82 PathProgramCache]: Analyzing trace with hash 556975009, now seen corresponding path program 1 times [2019-12-07 11:36:03,344 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:36:03,345 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1517801386] [2019-12-07 11:36:03,345 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:36:03,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:36:03,375 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:36:03,375 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1517801386] [2019-12-07 11:36:03,375 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:36:03,375 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 11:36:03,375 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [984232689] [2019-12-07 11:36:03,376 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 11:36:03,376 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:36:03,376 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 11:36:03,376 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:36:03,376 INFO L87 Difference]: Start difference. First operand 25455 states and 32998 transitions. Second operand 5 states. [2019-12-07 11:36:06,955 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:36:06,955 INFO L93 Difference]: Finished difference Result 84936 states and 110351 transitions. [2019-12-07 11:36:06,955 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 11:36:06,955 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 69 [2019-12-07 11:36:06,956 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:36:07,009 INFO L225 Difference]: With dead ends: 84936 [2019-12-07 11:36:07,010 INFO L226 Difference]: Without dead ends: 62320 [2019-12-07 11:36:07,029 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 11:36:07,073 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62320 states. [2019-12-07 11:36:08,817 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62320 to 28711. [2019-12-07 11:36:08,817 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28711 states. [2019-12-07 11:36:08,844 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28711 states to 28711 states and 37166 transitions. [2019-12-07 11:36:08,844 INFO L78 Accepts]: Start accepts. Automaton has 28711 states and 37166 transitions. Word has length 69 [2019-12-07 11:36:08,844 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:36:08,844 INFO L462 AbstractCegarLoop]: Abstraction has 28711 states and 37166 transitions. [2019-12-07 11:36:08,844 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 11:36:08,844 INFO L276 IsEmpty]: Start isEmpty. Operand 28711 states and 37166 transitions. [2019-12-07 11:36:08,847 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2019-12-07 11:36:08,847 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:36:08,847 INFO L410 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:36:08,847 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:36:08,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:36:08,847 INFO L82 PathProgramCache]: Analyzing trace with hash -636342002, now seen corresponding path program 1 times [2019-12-07 11:36:08,848 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:36:08,848 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1741453803] [2019-12-07 11:36:08,848 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:36:08,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:36:08,865 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:36:08,865 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1741453803] [2019-12-07 11:36:08,865 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:36:08,865 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:36:08,865 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1389033538] [2019-12-07 11:36:08,865 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:36:08,865 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:36:08,866 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:36:08,866 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:36:08,866 INFO L87 Difference]: Start difference. First operand 28711 states and 37166 transitions. Second operand 3 states. [2019-12-07 11:36:12,094 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:36:12,094 INFO L93 Difference]: Finished difference Result 75115 states and 97570 transitions. [2019-12-07 11:36:12,095 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:36:12,095 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 85 [2019-12-07 11:36:12,095 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:36:12,142 INFO L225 Difference]: With dead ends: 75115 [2019-12-07 11:36:12,142 INFO L226 Difference]: Without dead ends: 53157 [2019-12-07 11:36:12,159 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:36:12,194 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53157 states. [2019-12-07 11:36:14,920 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53157 to 47161. [2019-12-07 11:36:14,920 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47161 states. [2019-12-07 11:36:14,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47161 states to 47161 states and 61368 transitions. [2019-12-07 11:36:14,961 INFO L78 Accepts]: Start accepts. Automaton has 47161 states and 61368 transitions. Word has length 85 [2019-12-07 11:36:14,961 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:36:14,961 INFO L462 AbstractCegarLoop]: Abstraction has 47161 states and 61368 transitions. [2019-12-07 11:36:14,961 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:36:14,962 INFO L276 IsEmpty]: Start isEmpty. Operand 47161 states and 61368 transitions. [2019-12-07 11:36:14,966 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2019-12-07 11:36:14,966 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:36:14,966 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:36:14,967 INFO L410 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:36:14,967 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:36:14,967 INFO L82 PathProgramCache]: Analyzing trace with hash 929392569, now seen corresponding path program 1 times [2019-12-07 11:36:14,967 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:36:14,967 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [102373483] [2019-12-07 11:36:14,967 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:36:14,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:36:14,989 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2019-12-07 11:36:14,989 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [102373483] [2019-12-07 11:36:14,989 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:36:14,990 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:36:14,990 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [961064622] [2019-12-07 11:36:14,990 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:36:14,990 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:36:14,990 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:36:14,990 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:36:14,990 INFO L87 Difference]: Start difference. First operand 47161 states and 61368 transitions. Second operand 3 states. [2019-12-07 11:36:19,039 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:36:19,040 INFO L93 Difference]: Finished difference Result 112587 states and 145748 transitions. [2019-12-07 11:36:19,040 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:36:19,040 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 98 [2019-12-07 11:36:19,040 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:36:19,107 INFO L225 Difference]: With dead ends: 112587 [2019-12-07 11:36:19,107 INFO L226 Difference]: Without dead ends: 65448 [2019-12-07 11:36:19,144 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:36:19,291 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65448 states. [2019-12-07 11:36:23,078 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65448 to 65440. [2019-12-07 11:36:23,079 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 65440 states. [2019-12-07 11:36:23,146 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65440 states to 65440 states and 84104 transitions. [2019-12-07 11:36:23,146 INFO L78 Accepts]: Start accepts. Automaton has 65440 states and 84104 transitions. Word has length 98 [2019-12-07 11:36:23,146 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:36:23,146 INFO L462 AbstractCegarLoop]: Abstraction has 65440 states and 84104 transitions. [2019-12-07 11:36:23,147 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:36:23,147 INFO L276 IsEmpty]: Start isEmpty. Operand 65440 states and 84104 transitions. [2019-12-07 11:36:23,207 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2019-12-07 11:36:23,207 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:36:23,207 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:36:23,207 INFO L410 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:36:23,207 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:36:23,207 INFO L82 PathProgramCache]: Analyzing trace with hash 1073423074, now seen corresponding path program 1 times [2019-12-07 11:36:23,207 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:36:23,208 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [880118047] [2019-12-07 11:36:23,208 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:36:23,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:36:23,229 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-12-07 11:36:23,229 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [880118047] [2019-12-07 11:36:23,229 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:36:23,229 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:36:23,229 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [262570123] [2019-12-07 11:36:23,229 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:36:23,230 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:36:23,230 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:36:23,230 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:36:23,230 INFO L87 Difference]: Start difference. First operand 65440 states and 84104 transitions. Second operand 3 states. [2019-12-07 11:36:30,567 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:36:30,568 INFO L93 Difference]: Finished difference Result 173122 states and 223241 transitions. [2019-12-07 11:36:30,568 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:36:30,568 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 100 [2019-12-07 11:36:30,568 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:36:30,678 INFO L225 Difference]: With dead ends: 173122 [2019-12-07 11:36:30,678 INFO L226 Difference]: Without dead ends: 111862 [2019-12-07 11:36:30,715 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:36:30,795 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111862 states. [2019-12-07 11:36:37,051 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111862 to 105898. [2019-12-07 11:36:37,051 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105898 states. [2019-12-07 11:36:37,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105898 states to 105898 states and 136054 transitions. [2019-12-07 11:36:37,163 INFO L78 Accepts]: Start accepts. Automaton has 105898 states and 136054 transitions. Word has length 100 [2019-12-07 11:36:37,163 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:36:37,163 INFO L462 AbstractCegarLoop]: Abstraction has 105898 states and 136054 transitions. [2019-12-07 11:36:37,163 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:36:37,163 INFO L276 IsEmpty]: Start isEmpty. Operand 105898 states and 136054 transitions. [2019-12-07 11:36:37,168 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 102 [2019-12-07 11:36:37,169 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:36:37,169 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:36:37,169 INFO L410 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:36:37,169 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:36:37,169 INFO L82 PathProgramCache]: Analyzing trace with hash 569307248, now seen corresponding path program 1 times [2019-12-07 11:36:37,169 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:36:37,169 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [562795662] [2019-12-07 11:36:37,169 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:36:37,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:36:37,192 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 27 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:36:37,193 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [562795662] [2019-12-07 11:36:37,193 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:36:37,193 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:36:37,193 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1332589150] [2019-12-07 11:36:37,193 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:36:37,193 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:36:37,193 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:36:37,193 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:36:37,194 INFO L87 Difference]: Start difference. First operand 105898 states and 136054 transitions. Second operand 3 states. [2019-12-07 11:36:46,760 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:36:46,760 INFO L93 Difference]: Finished difference Result 257532 states and 329708 transitions. [2019-12-07 11:36:46,761 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:36:46,761 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 101 [2019-12-07 11:36:46,761 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:36:46,917 INFO L225 Difference]: With dead ends: 257532 [2019-12-07 11:36:46,917 INFO L226 Difference]: Without dead ends: 155814 [2019-12-07 11:36:46,976 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:36:47,090 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 155814 states. [2019-12-07 11:36:56,006 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 155814 to 143891. [2019-12-07 11:36:56,006 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 143891 states. [2019-12-07 11:36:56,151 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143891 states to 143891 states and 180995 transitions. [2019-12-07 11:36:56,152 INFO L78 Accepts]: Start accepts. Automaton has 143891 states and 180995 transitions. Word has length 101 [2019-12-07 11:36:56,152 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:36:56,152 INFO L462 AbstractCegarLoop]: Abstraction has 143891 states and 180995 transitions. [2019-12-07 11:36:56,152 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:36:56,152 INFO L276 IsEmpty]: Start isEmpty. Operand 143891 states and 180995 transitions. [2019-12-07 11:36:56,158 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2019-12-07 11:36:56,159 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:36:56,159 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:36:56,159 INFO L410 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:36:56,159 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:36:56,159 INFO L82 PathProgramCache]: Analyzing trace with hash -1656587422, now seen corresponding path program 1 times [2019-12-07 11:36:56,159 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:36:56,159 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1152865446] [2019-12-07 11:36:56,159 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:36:56,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:36:56,185 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 22 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-12-07 11:36:56,185 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1152865446] [2019-12-07 11:36:56,185 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:36:56,185 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:36:56,185 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1306031472] [2019-12-07 11:36:56,185 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:36:56,186 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:36:56,186 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:36:56,186 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:36:56,186 INFO L87 Difference]: Start difference. First operand 143891 states and 180995 transitions. Second operand 3 states. [2019-12-07 11:37:02,914 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:37:02,914 INFO L93 Difference]: Finished difference Result 240647 states and 303782 transitions. [2019-12-07 11:37:02,915 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:37:02,915 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 110 [2019-12-07 11:37:02,915 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:37:03,027 INFO L225 Difference]: With dead ends: 240647 [2019-12-07 11:37:03,027 INFO L226 Difference]: Without dead ends: 108025 [2019-12-07 11:37:03,088 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:37:03,166 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108025 states. [2019-12-07 11:37:10,896 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108025 to 108021. [2019-12-07 11:37:10,897 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 108021 states. [2019-12-07 11:37:11,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108021 states to 108021 states and 136527 transitions. [2019-12-07 11:37:11,010 INFO L78 Accepts]: Start accepts. Automaton has 108021 states and 136527 transitions. Word has length 110 [2019-12-07 11:37:11,010 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:37:11,010 INFO L462 AbstractCegarLoop]: Abstraction has 108021 states and 136527 transitions. [2019-12-07 11:37:11,010 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:37:11,010 INFO L276 IsEmpty]: Start isEmpty. Operand 108021 states and 136527 transitions. [2019-12-07 11:37:11,016 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2019-12-07 11:37:11,016 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:37:11,017 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:37:11,017 INFO L410 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:37:11,017 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:37:11,017 INFO L82 PathProgramCache]: Analyzing trace with hash 352710502, now seen corresponding path program 1 times [2019-12-07 11:37:11,017 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:37:11,017 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [102532801] [2019-12-07 11:37:11,017 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:37:11,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:37:11,044 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 28 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:37:11,044 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [102532801] [2019-12-07 11:37:11,044 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:37:11,045 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:37:11,045 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [508699782] [2019-12-07 11:37:11,045 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:37:11,045 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:37:11,045 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:37:11,045 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:37:11,045 INFO L87 Difference]: Start difference. First operand 108021 states and 136527 transitions. Second operand 3 states. [2019-12-07 11:37:17,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:37:17,170 INFO L93 Difference]: Finished difference Result 193374 states and 244947 transitions. [2019-12-07 11:37:17,170 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:37:17,170 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 113 [2019-12-07 11:37:17,170 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:37:17,256 INFO L225 Difference]: With dead ends: 193374 [2019-12-07 11:37:17,257 INFO L226 Difference]: Without dead ends: 97661 [2019-12-07 11:37:17,301 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:37:17,369 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97661 states. [2019-12-07 11:37:23,236 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97661 to 97193. [2019-12-07 11:37:23,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97193 states. [2019-12-07 11:37:23,332 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97193 states to 97193 states and 120812 transitions. [2019-12-07 11:37:23,332 INFO L78 Accepts]: Start accepts. Automaton has 97193 states and 120812 transitions. Word has length 113 [2019-12-07 11:37:23,332 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:37:23,332 INFO L462 AbstractCegarLoop]: Abstraction has 97193 states and 120812 transitions. [2019-12-07 11:37:23,332 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:37:23,332 INFO L276 IsEmpty]: Start isEmpty. Operand 97193 states and 120812 transitions. [2019-12-07 11:37:23,338 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2019-12-07 11:37:23,338 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:37:23,338 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:37:23,338 INFO L410 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:37:23,338 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:37:23,339 INFO L82 PathProgramCache]: Analyzing trace with hash -1416017638, now seen corresponding path program 1 times [2019-12-07 11:37:23,339 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:37:23,339 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [577310463] [2019-12-07 11:37:23,339 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:37:23,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:37:23,370 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 22 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-12-07 11:37:23,370 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [577310463] [2019-12-07 11:37:23,370 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:37:23,370 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 11:37:23,370 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1105877148] [2019-12-07 11:37:23,371 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:37:23,371 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:37:23,371 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:37:23,371 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:37:23,371 INFO L87 Difference]: Start difference. First operand 97193 states and 120812 transitions. Second operand 3 states. [2019-12-07 11:37:29,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:37:29,158 INFO L93 Difference]: Finished difference Result 184993 states and 230622 transitions. [2019-12-07 11:37:29,158 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:37:29,158 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 114 [2019-12-07 11:37:29,158 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:37:29,239 INFO L225 Difference]: With dead ends: 184993 [2019-12-07 11:37:29,239 INFO L226 Difference]: Without dead ends: 91890 [2019-12-07 11:37:29,279 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:37:29,344 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91890 states. [2019-12-07 11:37:34,840 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91890 to 91886. [2019-12-07 11:37:34,840 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 91886 states. [2019-12-07 11:37:34,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91886 states to 91886 states and 114627 transitions. [2019-12-07 11:37:34,930 INFO L78 Accepts]: Start accepts. Automaton has 91886 states and 114627 transitions. Word has length 114 [2019-12-07 11:37:34,930 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:37:34,930 INFO L462 AbstractCegarLoop]: Abstraction has 91886 states and 114627 transitions. [2019-12-07 11:37:34,930 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:37:34,930 INFO L276 IsEmpty]: Start isEmpty. Operand 91886 states and 114627 transitions. [2019-12-07 11:37:34,938 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2019-12-07 11:37:34,938 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:37:34,938 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:37:34,939 INFO L410 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:37:34,939 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:37:34,939 INFO L82 PathProgramCache]: Analyzing trace with hash -1511556233, now seen corresponding path program 1 times [2019-12-07 11:37:34,939 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:37:34,939 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2016067932] [2019-12-07 11:37:34,939 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:37:34,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:37:34,962 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 29 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:37:34,962 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2016067932] [2019-12-07 11:37:34,962 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:37:34,962 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:37:34,962 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1923631936] [2019-12-07 11:37:34,962 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:37:34,962 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:37:34,963 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:37:34,963 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:37:34,963 INFO L87 Difference]: Start difference. First operand 91886 states and 114627 transitions. Second operand 3 states. [2019-12-07 11:37:43,634 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:37:43,634 INFO L93 Difference]: Finished difference Result 229239 states and 285158 transitions. [2019-12-07 11:37:43,635 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:37:43,635 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 132 [2019-12-07 11:37:43,635 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:37:43,770 INFO L225 Difference]: With dead ends: 229239 [2019-12-07 11:37:43,770 INFO L226 Difference]: Without dead ends: 137401 [2019-12-07 11:37:43,825 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:37:43,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 137401 states. [2019-12-07 11:37:52,336 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 137401 to 136767. [2019-12-07 11:37:52,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 136767 states. [2019-12-07 11:37:52,474 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136767 states to 136767 states and 167094 transitions. [2019-12-07 11:37:52,474 INFO L78 Accepts]: Start accepts. Automaton has 136767 states and 167094 transitions. Word has length 132 [2019-12-07 11:37:52,475 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:37:52,475 INFO L462 AbstractCegarLoop]: Abstraction has 136767 states and 167094 transitions. [2019-12-07 11:37:52,475 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:37:52,475 INFO L276 IsEmpty]: Start isEmpty. Operand 136767 states and 167094 transitions. [2019-12-07 11:37:52,487 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2019-12-07 11:37:52,487 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:37:52,487 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:37:52,487 INFO L410 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:37:52,487 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:37:52,487 INFO L82 PathProgramCache]: Analyzing trace with hash -888283752, now seen corresponding path program 1 times [2019-12-07 11:37:52,488 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:37:52,488 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1790712685] [2019-12-07 11:37:52,488 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:37:52,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:37:52,535 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2019-12-07 11:37:52,535 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1790712685] [2019-12-07 11:37:52,535 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:37:52,535 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 11:37:52,536 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1383721151] [2019-12-07 11:37:52,536 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 11:37:52,536 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:37:52,536 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 11:37:52,536 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2019-12-07 11:37:52,536 INFO L87 Difference]: Start difference. First operand 136767 states and 167094 transitions. Second operand 8 states. [2019-12-07 11:37:58,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:37:58,727 INFO L93 Difference]: Finished difference Result 226325 states and 277277 transitions. [2019-12-07 11:37:58,728 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 11:37:58,728 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 134 [2019-12-07 11:37:58,728 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:37:58,807 INFO L225 Difference]: With dead ends: 226325 [2019-12-07 11:37:58,807 INFO L226 Difference]: Without dead ends: 89640 [2019-12-07 11:37:58,866 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=80, Unknown=0, NotChecked=0, Total=110 [2019-12-07 11:37:58,930 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89640 states. [2019-12-07 11:38:05,123 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89640 to 75226. [2019-12-07 11:38:05,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 75226 states. [2019-12-07 11:38:05,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75226 states to 75226 states and 91793 transitions. [2019-12-07 11:38:05,191 INFO L78 Accepts]: Start accepts. Automaton has 75226 states and 91793 transitions. Word has length 134 [2019-12-07 11:38:05,191 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:38:05,191 INFO L462 AbstractCegarLoop]: Abstraction has 75226 states and 91793 transitions. [2019-12-07 11:38:05,191 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 11:38:05,191 INFO L276 IsEmpty]: Start isEmpty. Operand 75226 states and 91793 transitions. [2019-12-07 11:38:05,195 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2019-12-07 11:38:05,196 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:38:05,196 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:38:05,196 INFO L410 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:38:05,196 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:38:05,196 INFO L82 PathProgramCache]: Analyzing trace with hash -470383885, now seen corresponding path program 1 times [2019-12-07 11:38:05,196 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:38:05,196 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1141865797] [2019-12-07 11:38:05,197 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:38:05,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:38:05,236 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-12-07 11:38:05,236 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1141865797] [2019-12-07 11:38:05,236 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:38:05,237 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 11:38:05,237 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [44172175] [2019-12-07 11:38:05,237 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 11:38:05,237 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:38:05,237 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 11:38:05,237 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 11:38:05,237 INFO L87 Difference]: Start difference. First operand 75226 states and 91793 transitions. Second operand 4 states. [2019-12-07 11:38:10,556 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:38:10,557 INFO L93 Difference]: Finished difference Result 152953 states and 187147 transitions. [2019-12-07 11:38:10,557 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 11:38:10,557 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 140 [2019-12-07 11:38:10,557 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:38:10,625 INFO L225 Difference]: With dead ends: 152953 [2019-12-07 11:38:10,625 INFO L226 Difference]: Without dead ends: 79293 [2019-12-07 11:38:10,658 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 11:38:10,713 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79293 states. [2019-12-07 11:38:15,728 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79293 to 76025. [2019-12-07 11:38:15,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 76025 states. [2019-12-07 11:38:15,801 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76025 states to 76025 states and 92768 transitions. [2019-12-07 11:38:15,801 INFO L78 Accepts]: Start accepts. Automaton has 76025 states and 92768 transitions. Word has length 140 [2019-12-07 11:38:15,801 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:38:15,802 INFO L462 AbstractCegarLoop]: Abstraction has 76025 states and 92768 transitions. [2019-12-07 11:38:15,802 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 11:38:15,802 INFO L276 IsEmpty]: Start isEmpty. Operand 76025 states and 92768 transitions. [2019-12-07 11:38:15,805 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2019-12-07 11:38:15,805 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:38:15,805 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:38:15,805 INFO L410 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:38:15,805 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:38:15,805 INFO L82 PathProgramCache]: Analyzing trace with hash -1484774257, now seen corresponding path program 1 times [2019-12-07 11:38:15,805 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:38:15,805 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1923029917] [2019-12-07 11:38:15,806 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:38:15,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:38:15,823 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2019-12-07 11:38:15,823 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1923029917] [2019-12-07 11:38:15,823 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:38:15,823 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:38:15,823 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1039708541] [2019-12-07 11:38:15,823 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:38:15,823 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:38:15,824 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:38:15,824 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:38:15,824 INFO L87 Difference]: Start difference. First operand 76025 states and 92768 transitions. Second operand 3 states. [2019-12-07 11:38:20,493 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:38:20,494 INFO L93 Difference]: Finished difference Result 142140 states and 173698 transitions. [2019-12-07 11:38:20,494 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:38:20,494 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 140 [2019-12-07 11:38:20,494 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:38:20,555 INFO L225 Difference]: With dead ends: 142140 [2019-12-07 11:38:20,555 INFO L226 Difference]: Without dead ends: 67631 [2019-12-07 11:38:20,594 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:38:20,644 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67631 states. [2019-12-07 11:38:25,283 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67631 to 67631. [2019-12-07 11:38:25,283 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 67631 states. [2019-12-07 11:38:25,345 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67631 states to 67631 states and 82609 transitions. [2019-12-07 11:38:25,345 INFO L78 Accepts]: Start accepts. Automaton has 67631 states and 82609 transitions. Word has length 140 [2019-12-07 11:38:25,346 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:38:25,346 INFO L462 AbstractCegarLoop]: Abstraction has 67631 states and 82609 transitions. [2019-12-07 11:38:25,346 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:38:25,346 INFO L276 IsEmpty]: Start isEmpty. Operand 67631 states and 82609 transitions. [2019-12-07 11:38:25,348 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 148 [2019-12-07 11:38:25,348 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:38:25,348 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:38:25,348 INFO L410 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:38:25,348 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:38:25,348 INFO L82 PathProgramCache]: Analyzing trace with hash -2075136958, now seen corresponding path program 1 times [2019-12-07 11:38:25,348 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:38:25,348 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [9027463] [2019-12-07 11:38:25,349 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:38:25,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:38:25,373 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 11:38:25,373 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [9027463] [2019-12-07 11:38:25,373 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:38:25,373 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:38:25,373 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [669408477] [2019-12-07 11:38:25,373 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:38:25,373 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:38:25,374 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:38:25,374 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:38:25,374 INFO L87 Difference]: Start difference. First operand 67631 states and 82609 transitions. Second operand 3 states. [2019-12-07 11:38:28,318 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:38:28,319 INFO L93 Difference]: Finished difference Result 108238 states and 132962 transitions. [2019-12-07 11:38:28,319 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:38:28,319 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 147 [2019-12-07 11:38:28,320 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:38:28,354 INFO L225 Difference]: With dead ends: 108238 [2019-12-07 11:38:28,354 INFO L226 Difference]: Without dead ends: 41247 [2019-12-07 11:38:28,394 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:38:28,424 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41247 states. [2019-12-07 11:38:31,225 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41247 to 41005. [2019-12-07 11:38:31,225 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41005 states. [2019-12-07 11:38:31,261 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41005 states to 41005 states and 48915 transitions. [2019-12-07 11:38:31,261 INFO L78 Accepts]: Start accepts. Automaton has 41005 states and 48915 transitions. Word has length 147 [2019-12-07 11:38:31,261 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:38:31,261 INFO L462 AbstractCegarLoop]: Abstraction has 41005 states and 48915 transitions. [2019-12-07 11:38:31,261 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:38:31,261 INFO L276 IsEmpty]: Start isEmpty. Operand 41005 states and 48915 transitions. [2019-12-07 11:38:31,263 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 149 [2019-12-07 11:38:31,263 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:38:31,263 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:38:31,263 INFO L410 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:38:31,263 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:38:31,264 INFO L82 PathProgramCache]: Analyzing trace with hash 1229732974, now seen corresponding path program 1 times [2019-12-07 11:38:31,264 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:38:31,264 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [81908021] [2019-12-07 11:38:31,264 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:38:31,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:38:31,316 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-12-07 11:38:31,316 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [81908021] [2019-12-07 11:38:31,316 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:38:31,316 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 11:38:31,317 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1473809861] [2019-12-07 11:38:31,317 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 11:38:31,317 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:38:31,317 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 11:38:31,317 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:38:31,317 INFO L87 Difference]: Start difference. First operand 41005 states and 48915 transitions. Second operand 5 states. [2019-12-07 11:38:36,321 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:38:36,321 INFO L93 Difference]: Finished difference Result 109406 states and 130636 transitions. [2019-12-07 11:38:36,322 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 11:38:36,322 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 148 [2019-12-07 11:38:36,322 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:38:36,383 INFO L225 Difference]: With dead ends: 109406 [2019-12-07 11:38:36,383 INFO L226 Difference]: Without dead ends: 70714 [2019-12-07 11:38:36,410 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-12-07 11:38:36,461 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70714 states. [2019-12-07 11:38:39,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70714 to 41498. [2019-12-07 11:38:39,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41498 states. [2019-12-07 11:38:39,564 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41498 states to 41498 states and 49378 transitions. [2019-12-07 11:38:39,564 INFO L78 Accepts]: Start accepts. Automaton has 41498 states and 49378 transitions. Word has length 148 [2019-12-07 11:38:39,564 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:38:39,564 INFO L462 AbstractCegarLoop]: Abstraction has 41498 states and 49378 transitions. [2019-12-07 11:38:39,564 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 11:38:39,565 INFO L276 IsEmpty]: Start isEmpty. Operand 41498 states and 49378 transitions. [2019-12-07 11:38:39,566 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 154 [2019-12-07 11:38:39,566 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:38:39,566 INFO L410 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:38:39,566 INFO L410 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:38:39,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:38:39,567 INFO L82 PathProgramCache]: Analyzing trace with hash 550899351, now seen corresponding path program 1 times [2019-12-07 11:38:39,567 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:38:39,567 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [751974770] [2019-12-07 11:38:39,567 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:38:39,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:38:39,591 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 45 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-12-07 11:38:39,591 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [751974770] [2019-12-07 11:38:39,591 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:38:39,591 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 11:38:39,591 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1142559708] [2019-12-07 11:38:39,592 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 11:38:39,592 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:38:39,592 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 11:38:39,592 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:38:39,592 INFO L87 Difference]: Start difference. First operand 41498 states and 49378 transitions. Second operand 3 states. [2019-12-07 11:38:42,534 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:38:42,535 INFO L93 Difference]: Finished difference Result 71698 states and 85402 transitions. [2019-12-07 11:38:42,535 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 11:38:42,535 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 153 [2019-12-07 11:38:42,535 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:38:42,568 INFO L225 Difference]: With dead ends: 71698 [2019-12-07 11:38:42,568 INFO L226 Difference]: Without dead ends: 40772 [2019-12-07 11:38:42,585 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 11:38:42,612 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40772 states. [2019-12-07 11:38:45,555 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40772 to 40586. [2019-12-07 11:38:45,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40586 states. [2019-12-07 11:38:45,589 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40586 states to 40586 states and 48280 transitions. [2019-12-07 11:38:45,589 INFO L78 Accepts]: Start accepts. Automaton has 40586 states and 48280 transitions. Word has length 153 [2019-12-07 11:38:45,589 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:38:45,589 INFO L462 AbstractCegarLoop]: Abstraction has 40586 states and 48280 transitions. [2019-12-07 11:38:45,590 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 11:38:45,590 INFO L276 IsEmpty]: Start isEmpty. Operand 40586 states and 48280 transitions. [2019-12-07 11:38:45,591 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 156 [2019-12-07 11:38:45,591 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:38:45,591 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:38:45,591 INFO L410 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:38:45,591 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:38:45,591 INFO L82 PathProgramCache]: Analyzing trace with hash -1029751779, now seen corresponding path program 1 times [2019-12-07 11:38:45,592 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:38:45,592 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [125835360] [2019-12-07 11:38:45,592 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:38:45,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:38:45,638 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 27 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-12-07 11:38:45,638 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [125835360] [2019-12-07 11:38:45,638 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 11:38:45,639 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 11:38:45,639 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2083527646] [2019-12-07 11:38:45,639 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 11:38:45,639 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:38:45,639 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 11:38:45,639 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 11:38:45,639 INFO L87 Difference]: Start difference. First operand 40586 states and 48280 transitions. Second operand 5 states. [2019-12-07 11:38:49,893 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:38:49,893 INFO L93 Difference]: Finished difference Result 96499 states and 114656 transitions. [2019-12-07 11:38:49,894 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 11:38:49,894 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 155 [2019-12-07 11:38:49,894 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:38:49,941 INFO L225 Difference]: With dead ends: 96499 [2019-12-07 11:38:49,941 INFO L226 Difference]: Without dead ends: 56844 [2019-12-07 11:38:49,959 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 5 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 11:38:49,995 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56844 states. [2019-12-07 11:38:52,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56844 to 39836. [2019-12-07 11:38:52,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39836 states. [2019-12-07 11:38:52,994 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39836 states to 39836 states and 46862 transitions. [2019-12-07 11:38:52,994 INFO L78 Accepts]: Start accepts. Automaton has 39836 states and 46862 transitions. Word has length 155 [2019-12-07 11:38:52,994 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:38:52,994 INFO L462 AbstractCegarLoop]: Abstraction has 39836 states and 46862 transitions. [2019-12-07 11:38:52,994 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 11:38:52,995 INFO L276 IsEmpty]: Start isEmpty. Operand 39836 states and 46862 transitions. [2019-12-07 11:38:52,996 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 157 [2019-12-07 11:38:52,996 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:38:52,996 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:38:52,996 INFO L410 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:38:52,996 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:38:52,997 INFO L82 PathProgramCache]: Analyzing trace with hash -1611315100, now seen corresponding path program 1 times [2019-12-07 11:38:52,997 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:38:52,997 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [651973477] [2019-12-07 11:38:52,997 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:38:53,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:38:53,070 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 27 proven. 1 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2019-12-07 11:38:53,070 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [651973477] [2019-12-07 11:38:53,070 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1835457250] [2019-12-07 11:38:53,070 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_6bd400ac-a770-40b7-b3e4-36092e5a6e9a/bin/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:38:53,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 11:38:53,129 INFO L264 TraceCheckSpWp]: Trace formula consists of 455 conjuncts, 11 conjunts are in the unsatisfiable core [2019-12-07 11:38:53,139 INFO L287 TraceCheckSpWp]: Computing forward predicates... [2019-12-07 11:38:53,206 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 9 proven. 17 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2019-12-07 11:38:53,206 INFO L220 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2019-12-07 11:38:53,206 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 9 [2019-12-07 11:38:53,207 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2090415434] [2019-12-07 11:38:53,207 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-12-07 11:38:53,208 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 11:38:53,208 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 11:38:53,208 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2019-12-07 11:38:53,208 INFO L87 Difference]: Start difference. First operand 39836 states and 46862 transitions. Second operand 9 states. [2019-12-07 11:38:57,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 11:38:57,251 INFO L93 Difference]: Finished difference Result 84451 states and 99413 transitions. [2019-12-07 11:38:57,251 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 11:38:57,252 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 156 [2019-12-07 11:38:57,252 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 11:38:57,352 INFO L225 Difference]: With dead ends: 84451 [2019-12-07 11:38:57,353 INFO L226 Difference]: Without dead ends: 47246 [2019-12-07 11:38:57,374 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 175 GetRequests, 159 SyntacticMatches, 2 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 37 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=81, Invalid=159, Unknown=0, NotChecked=0, Total=240 [2019-12-07 11:38:57,416 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47246 states. [2019-12-07 11:39:00,147 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47246 to 32382. [2019-12-07 11:39:00,147 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32382 states. [2019-12-07 11:39:00,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32382 states to 32382 states and 38037 transitions. [2019-12-07 11:39:00,173 INFO L78 Accepts]: Start accepts. Automaton has 32382 states and 38037 transitions. Word has length 156 [2019-12-07 11:39:00,173 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 11:39:00,173 INFO L462 AbstractCegarLoop]: Abstraction has 32382 states and 38037 transitions. [2019-12-07 11:39:00,173 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-12-07 11:39:00,173 INFO L276 IsEmpty]: Start isEmpty. Operand 32382 states and 38037 transitions. [2019-12-07 11:39:00,177 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 158 [2019-12-07 11:39:00,177 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 11:39:00,177 INFO L410 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 11:39:00,378 WARN L499 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2019-12-07 11:39:00,379 INFO L410 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 11:39:00,379 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 11:39:00,379 INFO L82 PathProgramCache]: Analyzing trace with hash -1576610856, now seen corresponding path program 1 times [2019-12-07 11:39:00,379 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 11:39:00,379 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1447255208] [2019-12-07 11:39:00,379 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 11:39:00,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 11:39:00,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 11:39:00,467 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 11:39:00,467 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 11:39:00,590 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 11:39:00 BoogieIcfgContainer [2019-12-07 11:39:00,590 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 11:39:00,590 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 11:39:00,590 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 11:39:00,591 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 11:39:00,591 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 11:35:40" (3/4) ... [2019-12-07 11:39:00,592 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 11:39:00,685 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_6bd400ac-a770-40b7-b3e4-36092e5a6e9a/bin/uautomizer/witness.graphml [2019-12-07 11:39:00,685 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 11:39:00,687 INFO L168 Benchmark]: Toolchain (without parser) took 200848.35 ms. Allocated memory was 1.0 GB in the beginning and 6.5 GB in the end (delta: 5.5 GB). Free memory was 944.7 MB in the beginning and 2.4 GB in the end (delta: -1.4 GB). Peak memory consumption was 4.0 GB. Max. memory is 11.5 GB. [2019-12-07 11:39:00,688 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 960.8 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 11:39:00,688 INFO L168 Benchmark]: CACSL2BoogieTranslator took 231.18 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 103.8 MB). Free memory was 944.7 MB in the beginning and 1.1 GB in the end (delta: -154.0 MB). Peak memory consumption was 22.9 MB. Max. memory is 11.5 GB. [2019-12-07 11:39:00,688 INFO L168 Benchmark]: Boogie Procedure Inliner took 33.32 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. [2019-12-07 11:39:00,688 INFO L168 Benchmark]: Boogie Preprocessor took 26.06 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 11:39:00,689 INFO L168 Benchmark]: RCFGBuilder took 394.46 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 49.2 MB). Peak memory consumption was 49.2 MB. Max. memory is 11.5 GB. [2019-12-07 11:39:00,689 INFO L168 Benchmark]: TraceAbstraction took 200065.13 ms. Allocated memory was 1.1 GB in the beginning and 6.5 GB in the end (delta: 5.4 GB). Free memory was 1.0 GB in the beginning and 2.5 GB in the end (delta: -1.4 GB). Peak memory consumption was 3.9 GB. Max. memory is 11.5 GB. [2019-12-07 11:39:00,689 INFO L168 Benchmark]: Witness Printer took 95.07 ms. Allocated memory is still 6.5 GB. Free memory was 2.5 GB in the beginning and 2.4 GB in the end (delta: 103.3 MB). Peak memory consumption was 103.3 MB. Max. memory is 11.5 GB. [2019-12-07 11:39:00,690 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 960.8 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 231.18 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 103.8 MB). Free memory was 944.7 MB in the beginning and 1.1 GB in the end (delta: -154.0 MB). Peak memory consumption was 22.9 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 33.32 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 26.06 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 394.46 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 49.2 MB). Peak memory consumption was 49.2 MB. Max. memory is 11.5 GB. * TraceAbstraction took 200065.13 ms. Allocated memory was 1.1 GB in the beginning and 6.5 GB in the end (delta: 5.4 GB). Free memory was 1.0 GB in the beginning and 2.5 GB in the end (delta: -1.4 GB). Peak memory consumption was 3.9 GB. Max. memory is 11.5 GB. * Witness Printer took 95.07 ms. Allocated memory is still 6.5 GB. Free memory was 2.5 GB in the beginning and 2.4 GB in the end (delta: 103.3 MB). Peak memory consumption was 103.3 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 9]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int max_loop ; [L16] int num ; [L17] int i ; [L18] int e ; [L19] int timer ; [L20] char data_0 ; [L21] char data_1 ; [L64] int P_1_pc; [L65] int P_1_st ; [L66] int P_1_i ; [L67] int P_1_ev ; [L122] int P_2_pc ; [L123] int P_2_st ; [L124] int P_2_i ; [L125] int P_2_ev ; [L190] int C_1_pc ; [L191] int C_1_st ; [L192] int C_1_i ; [L193] int C_1_ev ; [L194] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=0, P_2_pc=0, P_2_st=0, timer=0] [L593] int count ; [L594] int __retres2 ; [L598] num = 0 [L599] i = 0 [L600] max_loop = 2 [L602] timer = 0 [L603] P_1_pc = 0 [L604] P_2_pc = 0 [L605] C_1_pc = 0 [L607] count = 0 [L585] P_1_i = 1 [L586] P_2_i = 1 [L587] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L523] int kernel_st ; [L524] int tmp ; [L525] int tmp___0 ; [L529] kernel_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L294] COND TRUE (int )P_1_i == 1 [L295] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L299] COND TRUE (int )P_2_i == 1 [L300] P_2_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L304] COND TRUE (int )C_1_i == 1 [L305] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L459] int tmp ; [L460] int tmp___0 ; [L461] int tmp___1 ; [L104] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L107] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L117] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L119] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L465] tmp = is_P_1_triggered() [L467] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L172] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L175] COND FALSE !((int )P_2_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L185] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L187] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L473] tmp___0 = is_P_2_triggered() [L475] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L254] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L257] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L267] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L277] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L279] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L481] tmp___1 = is_C_1_triggered() [L483] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L537] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L540] kernel_st = 1 [L339] int tmp ; [L340] int tmp___0 ; [L341] int tmp___1 ; [L342] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L346] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L314] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L317] COND TRUE (int )P_1_st == 0 [L318] __retres1 = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L335] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L349] tmp___2 = exists_runnable_thread() [L351] COND TRUE \read(tmp___2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L356] COND TRUE (int )P_1_st == 0 [L358] tmp = __VERIFIER_nondet_int() [L360] COND TRUE \read(tmp) [L362] P_1_st = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L72] COND TRUE (int )P_1_pc == 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L83] COND TRUE i < max_loop VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L49] COND TRUE i___0 == 0 [L50] data_0 = c VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=65, data_1=0, e=0, i=0, max_loop=2, num=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=1, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L87] num += 1 [L88] P_1_pc = 1 [L89] P_1_st = 2 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=65, data_1=0, e=0, i=0, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, timer=0] [L371] COND TRUE (int )P_2_st == 0 [L373] tmp___0 = __VERIFIER_nondet_int() [L375] COND TRUE \read(tmp___0) [L377] P_2_st = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=65, data_1=0, e=0, i=0, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=1, timer=0] [L130] COND TRUE (int )P_2_pc == 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=65, data_1=0, e=0, i=0, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=1, timer=0] [L141] COND TRUE i < max_loop VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=65, data_1=0, e=0, i=0, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=1, timer=0] [L49] COND FALSE !(i___0 == 0) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=65, data_1=0, e=0, i=0, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=1, timer=0] [L52] COND TRUE i___0 == 1 [L53] data_1 = c VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=65, data_1=66, e=0, i=0, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=1, timer=0] [L145] num += 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=65, data_1=66, e=0, i=0, max_loop=2, num=2, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=1, timer=0] [L147] COND FALSE !(\read(timer)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=65, data_1=66, e=0, i=0, max_loop=2, num=2, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=1, timer=0] [L157] P_2_pc = 1 [L158] P_2_st = 2 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, data_0=65, data_1=66, e=0, i=0, max_loop=2, num=2, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L386] COND TRUE (int )C_1_st == 0 [L388] tmp___1 = __VERIFIER_nondet_int() [L390] COND TRUE \read(tmp___1) [L392] C_1_st = 1 [L196] char c ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=65, data_1=66, e=0, i=0, max_loop=2, num=2, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L199] COND TRUE (int )C_1_pc == 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=65, data_1=66, e=0, i=0, max_loop=2, num=2, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L214] COND TRUE i < max_loop VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=65, data_1=66, e=0, i=0, max_loop=2, num=2, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L216] COND FALSE !(num == 0) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=65, data_1=66, e=0, i=0, max_loop=2, num=2, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L227] num -= 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=65, data_1=66, e=0, i=0, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L228] COND FALSE !(! (num >= 0)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=65, data_1=66, e=0, i=0, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L23] char c ; [L24] char __retres3 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=65, data_1=66, e=0, i=0, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L27] COND FALSE !(i___0 == 0) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=65, data_1=66, e=0, i=0, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L31] COND TRUE i___0 == 1 [L32] __retres3 = data_1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=65, data_1=66, e=0, i=0, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L42] return (__retres3); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=1, data_0=65, data_1=66, e=0, i=0, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L236] c = read_data(num) [L237] i += 1 [L238] C_1_pc = 2 [L239] C_1_st = 2 VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L346] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L314] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L317] COND FALSE !((int )P_1_st == 0) VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L321] COND FALSE !((int )P_2_st == 0) VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L325] COND FALSE !((int )C_1_st == 0) [L333] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L335] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L349] tmp___2 = exists_runnable_thread() [L351] COND FALSE !(\read(tmp___2)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L544] kernel_st = 2 VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L548] kernel_st = 3 VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L459] int tmp ; [L460] int tmp___0 ; [L461] int tmp___1 ; [L104] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L107] COND TRUE (int )P_1_pc == 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L108] COND FALSE !((int )P_1_ev == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L117] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L119] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L465] tmp = is_P_1_triggered() [L467] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L172] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L175] COND TRUE (int )P_2_pc == 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L176] COND FALSE !((int )P_2_ev == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L185] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L187] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L473] tmp___0 = is_P_2_triggered() [L475] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L254] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L257] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L267] COND TRUE (int )C_1_pc == 2 VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L268] COND FALSE !((int )C_1_ev == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L277] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L279] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L481] tmp___1 = is_C_1_triggered() [L483] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L314] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L317] COND FALSE !((int )P_1_st == 0) VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L321] COND FALSE !((int )P_2_st == 0) VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L325] COND FALSE !((int )C_1_st == 0) [L333] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L335] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=0, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=0, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L554] tmp = exists_runnable_thread() [L556] COND TRUE tmp == 0 [L558] kernel_st = 4 [L428] C_1_ev = 1 [L429] P_1_ev = 1 [L430] P_2_ev = 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=1, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L459] int tmp ; [L460] int tmp___0 ; [L461] int tmp___1 ; [L104] int __retres1 ; VAL [C_1_ev=1, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=1, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L107] COND TRUE (int )P_1_pc == 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=1, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L108] COND TRUE (int )P_1_ev == 1 [L109] __retres1 = 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=1, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L119] return (__retres1); VAL [C_1_ev=1, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=1, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L465] tmp = is_P_1_triggered() [L467] COND TRUE \read(tmp) [L468] P_1_st = 0 VAL [C_1_ev=1, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, P_2_ev=1, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L172] int __retres1 ; VAL [C_1_ev=1, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, P_2_ev=1, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L175] COND TRUE (int )P_2_pc == 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, P_2_ev=1, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L176] COND TRUE (int )P_2_ev == 1 [L177] __retres1 = 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, P_2_ev=1, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L187] return (__retres1); VAL [C_1_ev=1, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, P_2_ev=1, P_2_i=1, P_2_pc=1, P_2_st=2, timer=0] [L473] tmp___0 = is_P_2_triggered() [L475] COND TRUE \read(tmp___0) [L476] P_2_st = 0 VAL [C_1_ev=1, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, P_2_ev=1, P_2_i=1, P_2_pc=1, P_2_st=0, timer=0] [L254] int __retres1 ; VAL [C_1_ev=1, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, P_2_ev=1, P_2_i=1, P_2_pc=1, P_2_st=0, timer=0] [L257] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=1, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, P_2_ev=1, P_2_i=1, P_2_pc=1, P_2_st=0, timer=0] [L267] COND TRUE (int )C_1_pc == 2 VAL [C_1_ev=1, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, P_2_ev=1, P_2_i=1, P_2_pc=1, P_2_st=0, timer=0] [L268] COND TRUE (int )C_1_ev == 1 [L269] __retres1 = 1 VAL [C_1_ev=1, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, P_2_ev=1, P_2_i=1, P_2_pc=1, P_2_st=0, timer=0] [L279] return (__retres1); VAL [C_1_ev=1, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=2, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, P_2_ev=1, P_2_i=1, P_2_pc=1, P_2_st=0, timer=0] [L481] tmp___1 = is_C_1_triggered() [L483] COND TRUE \read(tmp___1) [L484] C_1_st = 0 VAL [C_1_ev=1, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=1, P_1_i=1, P_1_pc=1, P_1_st=0, P_2_ev=1, P_2_i=1, P_2_pc=1, P_2_st=0, timer=0] [L439] COND TRUE (int )P_1_ev == 1 [L440] P_1_ev = 2 VAL [C_1_ev=1, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, P_2_ev=1, P_2_i=1, P_2_pc=1, P_2_st=0, timer=0] [L444] COND TRUE (int )P_2_ev == 1 [L445] P_2_ev = 2 VAL [C_1_ev=1, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, P_2_ev=2, P_2_i=1, P_2_pc=1, P_2_st=0, timer=0] [L449] COND TRUE (int )C_1_ev == 1 [L450] C_1_ev = 2 VAL [C_1_ev=2, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, P_2_ev=2, P_2_i=1, P_2_pc=1, P_2_st=0, timer=0] [L504] int tmp ; [L505] int __retres2 ; [L314] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, P_2_ev=2, P_2_i=1, P_2_pc=1, P_2_st=0, timer=0] [L317] COND TRUE (int )P_1_st == 0 [L318] __retres1 = 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, P_2_ev=2, P_2_i=1, P_2_pc=1, P_2_st=0, timer=0] [L335] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, P_2_ev=2, P_2_i=1, P_2_pc=1, P_2_st=0, timer=0] [L509] tmp = exists_runnable_thread() [L511] COND TRUE \read(tmp) [L512] __retres2 = 0 VAL [C_1_ev=2, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, P_2_ev=2, P_2_i=1, P_2_pc=1, P_2_st=0, timer=0] [L519] return (__retres2); VAL [C_1_ev=2, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, P_2_ev=2, P_2_i=1, P_2_pc=1, P_2_st=0, timer=0] [L567] tmp___0 = stop_simulation() [L569] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=2, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, P_2_ev=2, P_2_i=1, P_2_pc=1, P_2_st=0, timer=0] [L537] COND TRUE 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, P_2_ev=2, P_2_i=1, P_2_pc=1, P_2_st=0, timer=0] [L540] kernel_st = 1 [L339] int tmp ; [L340] int tmp___0 ; [L341] int tmp___1 ; [L342] int tmp___2 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, P_2_ev=2, P_2_i=1, P_2_pc=1, P_2_st=0, timer=0] [L346] COND TRUE 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, P_2_ev=2, P_2_i=1, P_2_pc=1, P_2_st=0, timer=0] [L314] int __retres1 ; VAL [C_1_ev=2, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, P_2_ev=2, P_2_i=1, P_2_pc=1, P_2_st=0, timer=0] [L317] COND TRUE (int )P_1_st == 0 [L318] __retres1 = 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, P_2_ev=2, P_2_i=1, P_2_pc=1, P_2_st=0, timer=0] [L335] return (__retres1); VAL [C_1_ev=2, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, P_2_ev=2, P_2_i=1, P_2_pc=1, P_2_st=0, timer=0] [L349] tmp___2 = exists_runnable_thread() [L351] COND TRUE \read(tmp___2) VAL [C_1_ev=2, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=0, P_2_ev=2, P_2_i=1, P_2_pc=1, P_2_st=0, timer=0] [L356] COND TRUE (int )P_1_st == 0 [L358] tmp = __VERIFIER_nondet_int() [L360] COND TRUE \read(tmp) [L362] P_1_st = 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, P_2_ev=2, P_2_i=1, P_2_pc=1, P_2_st=0, timer=0] [L72] COND FALSE !((int )P_1_pc == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, P_2_ev=2, P_2_i=1, P_2_pc=1, P_2_st=0, timer=0] [L75] COND TRUE (int )P_1_pc == 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, P_2_ev=2, P_2_i=1, P_2_pc=1, P_2_st=0, timer=0] [L83] COND TRUE i < max_loop VAL [C_1_ev=2, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, P_2_ev=2, P_2_i=1, P_2_pc=1, P_2_st=0, timer=0] [L49] COND FALSE !(i___0 == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=66, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, P_2_ev=2, P_2_i=1, P_2_pc=1, P_2_st=0, timer=0] [L52] COND TRUE i___0 == 1 [L53] data_1 = c VAL [C_1_ev=2, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=1, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=1, P_2_ev=2, P_2_i=1, P_2_pc=1, P_2_st=0, timer=0] [L87] num += 1 [L88] P_1_pc = 1 [L89] P_1_st = 2 VAL [C_1_ev=2, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=2, P_2_i=1, P_2_pc=1, P_2_st=0, timer=0] [L371] COND TRUE (int )P_2_st == 0 [L373] tmp___0 = __VERIFIER_nondet_int() [L375] COND TRUE \read(tmp___0) [L377] P_2_st = 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=2, P_2_i=1, P_2_pc=1, P_2_st=1, timer=0] [L130] COND FALSE !((int )P_2_pc == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=2, P_2_i=1, P_2_pc=1, P_2_st=1, timer=0] [L133] COND TRUE (int )P_2_pc == 1 VAL [C_1_ev=2, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=2, P_2_i=1, P_2_pc=1, P_2_st=1, timer=0] [L141] COND TRUE i < max_loop VAL [C_1_ev=2, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=2, P_2_i=1, P_2_pc=1, P_2_st=1, timer=0] [L49] COND FALSE !(i___0 == 0) VAL [C_1_ev=2, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=2, P_2_i=1, P_2_pc=1, P_2_st=1, timer=0] [L52] COND FALSE !(i___0 == 1) VAL [C_1_ev=2, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=2, P_2_i=1, P_2_pc=1, P_2_st=1, timer=0] [L9] __VERIFIER_error() VAL [C_1_ev=2, C_1_i=1, C_1_pc=2, C_1_pr=0, C_1_st=0, data_0=65, data_1=65, e=0, i=1, max_loop=2, num=2, P_1_ev=2, P_1_i=1, P_1_pc=1, P_1_st=2, P_2_ev=2, P_2_i=1, P_2_pc=1, P_2_st=1, timer=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 180 locations, 4 error locations. Result: UNSAFE, OverallTime: 199.9s, OverallIterations: 36, TraceHistogramMax: 4, AutomataDifference: 104.4s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 13318 SDtfs, 14332 SDslu, 20822 SDs, 0 SdLazy, 1423 SolverSat, 299 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.8s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 349 GetRequests, 237 SyntacticMatches, 8 SemanticMatches, 104 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 61 ImplicationChecksByTransitivity, 0.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=143891occurred in iteration=23, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 93.4s AutomataMinimizationTime, 35 MinimizatonAttempts, 170640 StatesRemovedByMinimization, 32 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 0.8s InterpolantComputationTime, 3344 NumberOfCodeBlocks, 3344 NumberOfCodeBlocksAsserted, 37 NumberOfCheckSat, 3151 ConstructedInterpolants, 0 QuantifiedInterpolants, 632881 SizeOfPredicates, 2 NumberOfNonLiveVariables, 455 ConjunctsInSsa, 11 ConjunctsInUnsatCore, 36 InterpolantComputations, 34 PerfectInterpolantSequences, 572/590 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...