./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/mix015_rmo.oepc.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_54fef296-034f-44e2-bf8e-ffda9e4a5496/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_54fef296-034f-44e2-bf8e-ffda9e4a5496/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_54fef296-034f-44e2-bf8e-ffda9e4a5496/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_54fef296-034f-44e2-bf8e-ffda9e4a5496/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/mix015_rmo.oepc.i -s /tmp/vcloud-vcloud-master/worker/run_dir_54fef296-034f-44e2-bf8e-ffda9e4a5496/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_54fef296-034f-44e2-bf8e-ffda9e4a5496/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 6857cc75dda71c1f64c8be08af4d2b2fe8753f19 ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 17:26:03,771 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 17:26:03,773 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 17:26:03,780 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 17:26:03,780 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 17:26:03,781 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 17:26:03,782 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 17:26:03,783 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 17:26:03,785 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 17:26:03,785 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 17:26:03,786 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 17:26:03,786 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 17:26:03,787 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 17:26:03,787 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 17:26:03,788 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 17:26:03,789 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 17:26:03,789 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 17:26:03,790 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 17:26:03,791 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 17:26:03,793 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 17:26:03,794 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 17:26:03,795 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 17:26:03,795 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 17:26:03,796 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 17:26:03,797 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 17:26:03,798 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 17:26:03,798 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 17:26:03,798 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 17:26:03,798 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 17:26:03,799 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 17:26:03,799 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 17:26:03,799 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 17:26:03,800 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 17:26:03,800 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 17:26:03,801 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 17:26:03,801 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 17:26:03,801 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 17:26:03,801 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 17:26:03,802 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 17:26:03,802 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 17:26:03,803 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 17:26:03,803 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_54fef296-034f-44e2-bf8e-ffda9e4a5496/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 17:26:03,813 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 17:26:03,813 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 17:26:03,814 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 17:26:03,814 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 17:26:03,814 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 17:26:03,814 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 17:26:03,814 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 17:26:03,814 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 17:26:03,815 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 17:26:03,815 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 17:26:03,815 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 17:26:03,815 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 17:26:03,815 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 17:26:03,815 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 17:26:03,815 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 17:26:03,815 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 17:26:03,816 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 17:26:03,816 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 17:26:03,816 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 17:26:03,816 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 17:26:03,816 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 17:26:03,816 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 17:26:03,816 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 17:26:03,816 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 17:26:03,817 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 17:26:03,817 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 17:26:03,817 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 17:26:03,817 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 17:26:03,817 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 17:26:03,817 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_54fef296-034f-44e2-bf8e-ffda9e4a5496/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 6857cc75dda71c1f64c8be08af4d2b2fe8753f19 [2019-12-07 17:26:03,918 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 17:26:03,928 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 17:26:03,931 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 17:26:03,932 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 17:26:03,932 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 17:26:03,932 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_54fef296-034f-44e2-bf8e-ffda9e4a5496/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/mix015_rmo.oepc.i [2019-12-07 17:26:03,972 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_54fef296-034f-44e2-bf8e-ffda9e4a5496/bin/uautomizer/data/88626835c/37a4ba2f95d4438686af5c9c2b745534/FLAGcb515f6f3 [2019-12-07 17:26:04,422 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 17:26:04,422 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_54fef296-034f-44e2-bf8e-ffda9e4a5496/sv-benchmarks/c/pthread-wmm/mix015_rmo.oepc.i [2019-12-07 17:26:04,432 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_54fef296-034f-44e2-bf8e-ffda9e4a5496/bin/uautomizer/data/88626835c/37a4ba2f95d4438686af5c9c2b745534/FLAGcb515f6f3 [2019-12-07 17:26:04,443 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_54fef296-034f-44e2-bf8e-ffda9e4a5496/bin/uautomizer/data/88626835c/37a4ba2f95d4438686af5c9c2b745534 [2019-12-07 17:26:04,445 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 17:26:04,446 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 17:26:04,447 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 17:26:04,447 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 17:26:04,450 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 17:26:04,450 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 05:26:04" (1/1) ... [2019-12-07 17:26:04,453 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5a2ff042 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:26:04, skipping insertion in model container [2019-12-07 17:26:04,453 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 05:26:04" (1/1) ... [2019-12-07 17:26:04,458 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 17:26:04,490 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 17:26:04,738 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 17:26:04,746 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 17:26:04,790 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 17:26:04,836 INFO L208 MainTranslator]: Completed translation [2019-12-07 17:26:04,836 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:26:04 WrapperNode [2019-12-07 17:26:04,836 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 17:26:04,837 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 17:26:04,837 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 17:26:04,837 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 17:26:04,843 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:26:04" (1/1) ... [2019-12-07 17:26:04,857 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:26:04" (1/1) ... [2019-12-07 17:26:04,876 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 17:26:04,876 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 17:26:04,876 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 17:26:04,877 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 17:26:04,883 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:26:04" (1/1) ... [2019-12-07 17:26:04,883 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:26:04" (1/1) ... [2019-12-07 17:26:04,887 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:26:04" (1/1) ... [2019-12-07 17:26:04,887 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:26:04" (1/1) ... [2019-12-07 17:26:04,894 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:26:04" (1/1) ... [2019-12-07 17:26:04,897 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:26:04" (1/1) ... [2019-12-07 17:26:04,900 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:26:04" (1/1) ... [2019-12-07 17:26:04,903 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 17:26:04,904 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 17:26:04,904 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 17:26:04,904 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 17:26:04,904 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:26:04" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_54fef296-034f-44e2-bf8e-ffda9e4a5496/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 17:26:04,947 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 17:26:04,947 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 17:26:04,947 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 17:26:04,947 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 17:26:04,947 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 17:26:04,947 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 17:26:04,947 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 17:26:04,947 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 17:26:04,947 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 17:26:04,948 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 17:26:04,948 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 17:26:04,948 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 17:26:04,948 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 17:26:04,949 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 17:26:05,316 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 17:26:05,316 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 17:26:05,317 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:26:05 BoogieIcfgContainer [2019-12-07 17:26:05,317 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 17:26:05,318 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 17:26:05,318 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 17:26:05,320 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 17:26:05,320 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 05:26:04" (1/3) ... [2019-12-07 17:26:05,321 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2eddd685 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 05:26:05, skipping insertion in model container [2019-12-07 17:26:05,321 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:26:04" (2/3) ... [2019-12-07 17:26:05,321 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2eddd685 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 05:26:05, skipping insertion in model container [2019-12-07 17:26:05,321 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:26:05" (3/3) ... [2019-12-07 17:26:05,322 INFO L109 eAbstractionObserver]: Analyzing ICFG mix015_rmo.oepc.i [2019-12-07 17:26:05,328 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 17:26:05,328 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 17:26:05,333 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 17:26:05,334 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 17:26:05,359 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,359 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,359 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,359 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,359 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,359 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,360 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,360 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,360 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,360 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,360 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,360 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,360 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,361 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,361 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,361 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,361 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,361 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,361 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,361 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,361 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,362 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,362 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,362 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,362 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,362 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,362 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,362 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,363 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,363 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,363 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,363 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,363 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,363 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,364 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,364 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,364 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,364 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,365 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,365 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,365 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,365 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,365 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,366 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,366 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,366 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,366 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,366 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,367 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,367 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,367 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,367 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,367 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,367 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,367 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,367 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,368 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,368 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,368 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,368 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,368 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,368 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,368 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,369 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,370 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,370 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,370 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,370 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,370 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,370 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,370 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,370 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,371 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,371 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,371 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,371 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,371 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,371 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,371 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,371 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,371 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,372 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,372 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,372 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,372 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,372 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,372 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,373 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,373 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,373 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,373 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,373 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,373 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,373 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,373 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,374 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,374 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,374 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,374 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,374 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,374 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,375 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,375 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,375 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,375 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,375 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,375 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,376 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,376 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,376 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,376 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,376 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,376 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,377 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,377 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,377 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,377 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,377 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,377 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,377 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,377 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,377 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,377 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,378 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,378 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,378 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,378 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,378 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,378 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,378 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,379 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,379 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,379 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,379 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,379 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,379 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,379 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,380 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,380 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,380 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,380 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,380 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,380 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,380 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,380 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,380 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,380 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,381 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,381 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,381 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,381 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,381 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,381 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,381 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,381 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,381 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,381 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,382 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,382 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,382 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,382 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,382 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,382 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,382 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,382 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,382 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,382 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,383 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,383 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,383 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,383 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,383 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,383 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,383 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,384 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,384 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,384 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,384 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,384 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,384 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,384 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,384 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:26:05,397 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 17:26:05,410 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 17:26:05,411 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 17:26:05,411 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 17:26:05,411 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 17:26:05,411 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 17:26:05,411 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 17:26:05,411 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 17:26:05,411 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 17:26:05,424 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 179 places, 216 transitions [2019-12-07 17:26:05,425 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 179 places, 216 transitions [2019-12-07 17:26:05,490 INFO L134 PetriNetUnfolder]: 47/213 cut-off events. [2019-12-07 17:26:05,490 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 17:26:05,501 INFO L76 FinitePrefix]: Finished finitePrefix Result has 223 conditions, 213 events. 47/213 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 685 event pairs. 9/173 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 17:26:05,518 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 179 places, 216 transitions [2019-12-07 17:26:05,557 INFO L134 PetriNetUnfolder]: 47/213 cut-off events. [2019-12-07 17:26:05,557 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 17:26:05,563 INFO L76 FinitePrefix]: Finished finitePrefix Result has 223 conditions, 213 events. 47/213 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 685 event pairs. 9/173 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 17:26:05,580 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 19004 [2019-12-07 17:26:05,581 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 17:26:08,389 WARN L192 SmtUtils]: Spent 155.00 ms on a formula simplification. DAG size of input: 97 DAG size of output: 95 [2019-12-07 17:26:08,707 WARN L192 SmtUtils]: Spent 197.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 47 [2019-12-07 17:26:08,735 INFO L206 etLargeBlockEncoding]: Checked pairs total: 80759 [2019-12-07 17:26:08,736 INFO L214 etLargeBlockEncoding]: Total number of compositions: 116 [2019-12-07 17:26:08,738 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 94 places, 102 transitions [2019-12-07 17:26:23,371 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 118022 states. [2019-12-07 17:26:23,373 INFO L276 IsEmpty]: Start isEmpty. Operand 118022 states. [2019-12-07 17:26:23,376 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-12-07 17:26:23,376 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:26:23,377 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-12-07 17:26:23,377 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:26:23,381 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:26:23,445 INFO L82 PathProgramCache]: Analyzing trace with hash 922782, now seen corresponding path program 1 times [2019-12-07 17:26:23,451 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:26:23,451 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1508257706] [2019-12-07 17:26:23,452 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:26:23,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:26:23,581 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:26:23,582 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1508257706] [2019-12-07 17:26:23,582 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:26:23,583 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 17:26:23,583 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1002935875] [2019-12-07 17:26:23,586 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:26:23,586 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:26:23,595 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:26:23,595 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:26:23,597 INFO L87 Difference]: Start difference. First operand 118022 states. Second operand 3 states. [2019-12-07 17:26:24,355 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:26:24,356 INFO L93 Difference]: Finished difference Result 116858 states and 495582 transitions. [2019-12-07 17:26:24,356 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:26:24,357 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2019-12-07 17:26:24,357 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:26:24,858 INFO L225 Difference]: With dead ends: 116858 [2019-12-07 17:26:24,858 INFO L226 Difference]: Without dead ends: 110138 [2019-12-07 17:26:24,859 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:26:29,112 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110138 states. [2019-12-07 17:26:31,765 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110138 to 110138. [2019-12-07 17:26:31,766 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 110138 states. [2019-12-07 17:26:32,135 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110138 states to 110138 states and 466462 transitions. [2019-12-07 17:26:32,136 INFO L78 Accepts]: Start accepts. Automaton has 110138 states and 466462 transitions. Word has length 3 [2019-12-07 17:26:32,136 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:26:32,136 INFO L462 AbstractCegarLoop]: Abstraction has 110138 states and 466462 transitions. [2019-12-07 17:26:32,136 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:26:32,136 INFO L276 IsEmpty]: Start isEmpty. Operand 110138 states and 466462 transitions. [2019-12-07 17:26:32,139 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-12-07 17:26:32,139 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:26:32,139 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:26:32,139 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:26:32,139 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:26:32,139 INFO L82 PathProgramCache]: Analyzing trace with hash 228105342, now seen corresponding path program 1 times [2019-12-07 17:26:32,139 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:26:32,139 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2127940153] [2019-12-07 17:26:32,140 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:26:32,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:26:32,200 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:26:32,200 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2127940153] [2019-12-07 17:26:32,200 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:26:32,201 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:26:32,201 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1186813049] [2019-12-07 17:26:32,202 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:26:32,202 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:26:32,202 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:26:32,202 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:26:32,202 INFO L87 Difference]: Start difference. First operand 110138 states and 466462 transitions. Second operand 4 states. [2019-12-07 17:26:33,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:26:33,352 INFO L93 Difference]: Finished difference Result 170904 states and 695583 transitions. [2019-12-07 17:26:33,353 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:26:33,353 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-12-07 17:26:33,353 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:26:33,780 INFO L225 Difference]: With dead ends: 170904 [2019-12-07 17:26:33,780 INFO L226 Difference]: Without dead ends: 170855 [2019-12-07 17:26:33,781 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:26:38,644 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 170855 states. [2019-12-07 17:26:42,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 170855 to 156295. [2019-12-07 17:26:42,309 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 156295 states. [2019-12-07 17:26:42,744 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156295 states to 156295 states and 644009 transitions. [2019-12-07 17:26:42,744 INFO L78 Accepts]: Start accepts. Automaton has 156295 states and 644009 transitions. Word has length 11 [2019-12-07 17:26:42,744 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:26:42,745 INFO L462 AbstractCegarLoop]: Abstraction has 156295 states and 644009 transitions. [2019-12-07 17:26:42,745 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:26:42,745 INFO L276 IsEmpty]: Start isEmpty. Operand 156295 states and 644009 transitions. [2019-12-07 17:26:42,753 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 17:26:42,753 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:26:42,753 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:26:42,753 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:26:42,754 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:26:42,754 INFO L82 PathProgramCache]: Analyzing trace with hash 891607686, now seen corresponding path program 1 times [2019-12-07 17:26:42,754 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:26:42,754 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1002760707] [2019-12-07 17:26:42,754 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:26:42,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:26:42,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:26:42,799 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1002760707] [2019-12-07 17:26:42,799 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:26:42,799 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:26:42,800 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1115074373] [2019-12-07 17:26:42,800 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:26:42,800 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:26:42,800 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:26:42,800 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:26:42,800 INFO L87 Difference]: Start difference. First operand 156295 states and 644009 transitions. Second operand 3 states. [2019-12-07 17:26:43,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:26:43,188 INFO L93 Difference]: Finished difference Result 33673 states and 108735 transitions. [2019-12-07 17:26:43,189 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:26:43,189 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 13 [2019-12-07 17:26:43,189 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:26:43,237 INFO L225 Difference]: With dead ends: 33673 [2019-12-07 17:26:43,238 INFO L226 Difference]: Without dead ends: 33673 [2019-12-07 17:26:43,238 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:26:43,413 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33673 states. [2019-12-07 17:26:43,702 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33673 to 33673. [2019-12-07 17:26:43,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33673 states. [2019-12-07 17:26:43,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33673 states to 33673 states and 108735 transitions. [2019-12-07 17:26:43,758 INFO L78 Accepts]: Start accepts. Automaton has 33673 states and 108735 transitions. Word has length 13 [2019-12-07 17:26:43,758 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:26:43,758 INFO L462 AbstractCegarLoop]: Abstraction has 33673 states and 108735 transitions. [2019-12-07 17:26:43,758 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:26:43,758 INFO L276 IsEmpty]: Start isEmpty. Operand 33673 states and 108735 transitions. [2019-12-07 17:26:43,760 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2019-12-07 17:26:43,760 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:26:43,760 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:26:43,760 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:26:43,760 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:26:43,761 INFO L82 PathProgramCache]: Analyzing trace with hash -1993825600, now seen corresponding path program 1 times [2019-12-07 17:26:43,761 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:26:43,761 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [991903355] [2019-12-07 17:26:43,761 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:26:43,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:26:43,808 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:26:43,809 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [991903355] [2019-12-07 17:26:43,809 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:26:43,809 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:26:43,809 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2129228299] [2019-12-07 17:26:43,809 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:26:43,810 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:26:43,810 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:26:43,810 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:26:43,810 INFO L87 Difference]: Start difference. First operand 33673 states and 108735 transitions. Second operand 4 states. [2019-12-07 17:26:44,037 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:26:44,038 INFO L93 Difference]: Finished difference Result 42056 states and 135369 transitions. [2019-12-07 17:26:44,038 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:26:44,038 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2019-12-07 17:26:44,039 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:26:44,097 INFO L225 Difference]: With dead ends: 42056 [2019-12-07 17:26:44,097 INFO L226 Difference]: Without dead ends: 42056 [2019-12-07 17:26:44,097 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:26:44,292 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42056 states. [2019-12-07 17:26:44,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42056 to 37770. [2019-12-07 17:26:44,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37770 states. [2019-12-07 17:26:44,720 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37770 states to 37770 states and 121950 transitions. [2019-12-07 17:26:44,720 INFO L78 Accepts]: Start accepts. Automaton has 37770 states and 121950 transitions. Word has length 16 [2019-12-07 17:26:44,721 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:26:44,721 INFO L462 AbstractCegarLoop]: Abstraction has 37770 states and 121950 transitions. [2019-12-07 17:26:44,721 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:26:44,721 INFO L276 IsEmpty]: Start isEmpty. Operand 37770 states and 121950 transitions. [2019-12-07 17:26:44,726 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2019-12-07 17:26:44,726 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:26:44,726 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:26:44,726 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:26:44,726 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:26:44,727 INFO L82 PathProgramCache]: Analyzing trace with hash 674854723, now seen corresponding path program 1 times [2019-12-07 17:26:44,727 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:26:44,727 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1908243474] [2019-12-07 17:26:44,727 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:26:44,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:26:44,802 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:26:44,802 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1908243474] [2019-12-07 17:26:44,803 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:26:44,803 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:26:44,803 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [57627051] [2019-12-07 17:26:44,803 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:26:44,803 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:26:44,804 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:26:44,804 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:26:44,804 INFO L87 Difference]: Start difference. First operand 37770 states and 121950 transitions. Second operand 5 states. [2019-12-07 17:26:45,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:26:45,188 INFO L93 Difference]: Finished difference Result 48537 states and 154193 transitions. [2019-12-07 17:26:45,189 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 17:26:45,189 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 22 [2019-12-07 17:26:45,189 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:26:45,253 INFO L225 Difference]: With dead ends: 48537 [2019-12-07 17:26:45,253 INFO L226 Difference]: Without dead ends: 48530 [2019-12-07 17:26:45,253 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 17:26:45,461 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48530 states. [2019-12-07 17:26:45,865 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48530 to 37459. [2019-12-07 17:26:45,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37459 states. [2019-12-07 17:26:45,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37459 states to 37459 states and 120776 transitions. [2019-12-07 17:26:45,946 INFO L78 Accepts]: Start accepts. Automaton has 37459 states and 120776 transitions. Word has length 22 [2019-12-07 17:26:45,946 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:26:45,946 INFO L462 AbstractCegarLoop]: Abstraction has 37459 states and 120776 transitions. [2019-12-07 17:26:45,946 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:26:45,946 INFO L276 IsEmpty]: Start isEmpty. Operand 37459 states and 120776 transitions. [2019-12-07 17:26:45,956 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 17:26:45,956 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:26:45,956 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:26:45,956 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:26:45,956 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:26:45,956 INFO L82 PathProgramCache]: Analyzing trace with hash 332765886, now seen corresponding path program 1 times [2019-12-07 17:26:45,956 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:26:45,957 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2016950657] [2019-12-07 17:26:45,957 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:26:45,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:26:46,025 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:26:46,026 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2016950657] [2019-12-07 17:26:46,026 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:26:46,026 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:26:46,026 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1386489224] [2019-12-07 17:26:46,027 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:26:46,027 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:26:46,027 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:26:46,027 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:26:46,027 INFO L87 Difference]: Start difference. First operand 37459 states and 120776 transitions. Second operand 5 states. [2019-12-07 17:26:46,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:26:46,692 INFO L93 Difference]: Finished difference Result 51888 states and 163997 transitions. [2019-12-07 17:26:46,693 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 17:26:46,693 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 25 [2019-12-07 17:26:46,693 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:26:46,768 INFO L225 Difference]: With dead ends: 51888 [2019-12-07 17:26:46,768 INFO L226 Difference]: Without dead ends: 51875 [2019-12-07 17:26:46,768 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:26:46,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51875 states. [2019-12-07 17:26:47,425 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51875 to 43351. [2019-12-07 17:26:47,425 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 43351 states. [2019-12-07 17:26:47,496 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43351 states to 43351 states and 139193 transitions. [2019-12-07 17:26:47,497 INFO L78 Accepts]: Start accepts. Automaton has 43351 states and 139193 transitions. Word has length 25 [2019-12-07 17:26:47,497 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:26:47,497 INFO L462 AbstractCegarLoop]: Abstraction has 43351 states and 139193 transitions. [2019-12-07 17:26:47,497 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:26:47,497 INFO L276 IsEmpty]: Start isEmpty. Operand 43351 states and 139193 transitions. [2019-12-07 17:26:47,508 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 17:26:47,508 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:26:47,508 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:26:47,508 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:26:47,508 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:26:47,508 INFO L82 PathProgramCache]: Analyzing trace with hash 445555351, now seen corresponding path program 1 times [2019-12-07 17:26:47,508 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:26:47,508 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [901147619] [2019-12-07 17:26:47,508 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:26:47,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:26:47,537 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:26:47,537 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [901147619] [2019-12-07 17:26:47,538 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:26:47,538 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:26:47,538 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [597391444] [2019-12-07 17:26:47,538 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:26:47,538 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:26:47,539 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:26:47,539 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:26:47,539 INFO L87 Difference]: Start difference. First operand 43351 states and 139193 transitions. Second operand 3 states. [2019-12-07 17:26:47,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:26:47,728 INFO L93 Difference]: Finished difference Result 67737 states and 216583 transitions. [2019-12-07 17:26:47,728 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:26:47,728 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-12-07 17:26:47,728 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:26:47,829 INFO L225 Difference]: With dead ends: 67737 [2019-12-07 17:26:47,830 INFO L226 Difference]: Without dead ends: 67737 [2019-12-07 17:26:47,830 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:26:48,077 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67737 states. [2019-12-07 17:26:48,666 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67737 to 51736. [2019-12-07 17:26:48,666 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51736 states. [2019-12-07 17:26:48,763 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51736 states to 51736 states and 166463 transitions. [2019-12-07 17:26:48,763 INFO L78 Accepts]: Start accepts. Automaton has 51736 states and 166463 transitions. Word has length 27 [2019-12-07 17:26:48,763 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:26:48,763 INFO L462 AbstractCegarLoop]: Abstraction has 51736 states and 166463 transitions. [2019-12-07 17:26:48,764 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:26:48,764 INFO L276 IsEmpty]: Start isEmpty. Operand 51736 states and 166463 transitions. [2019-12-07 17:26:48,778 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 17:26:48,778 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:26:48,778 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:26:48,778 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:26:48,778 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:26:48,778 INFO L82 PathProgramCache]: Analyzing trace with hash 1217095067, now seen corresponding path program 1 times [2019-12-07 17:26:48,778 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:26:48,778 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [778233003] [2019-12-07 17:26:48,779 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:26:48,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:26:48,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:26:48,800 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [778233003] [2019-12-07 17:26:48,800 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:26:48,800 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:26:48,800 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2112182629] [2019-12-07 17:26:48,800 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:26:48,800 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:26:48,800 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:26:48,801 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:26:48,801 INFO L87 Difference]: Start difference. First operand 51736 states and 166463 transitions. Second operand 3 states. [2019-12-07 17:26:48,993 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:26:48,993 INFO L93 Difference]: Finished difference Result 67737 states and 213366 transitions. [2019-12-07 17:26:48,994 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:26:48,994 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-12-07 17:26:48,994 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:26:49,094 INFO L225 Difference]: With dead ends: 67737 [2019-12-07 17:26:49,095 INFO L226 Difference]: Without dead ends: 67737 [2019-12-07 17:26:49,095 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:26:49,442 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67737 states. [2019-12-07 17:26:49,974 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67737 to 51736. [2019-12-07 17:26:49,974 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51736 states. [2019-12-07 17:26:50,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51736 states to 51736 states and 163246 transitions. [2019-12-07 17:26:50,068 INFO L78 Accepts]: Start accepts. Automaton has 51736 states and 163246 transitions. Word has length 27 [2019-12-07 17:26:50,068 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:26:50,068 INFO L462 AbstractCegarLoop]: Abstraction has 51736 states and 163246 transitions. [2019-12-07 17:26:50,068 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:26:50,068 INFO L276 IsEmpty]: Start isEmpty. Operand 51736 states and 163246 transitions. [2019-12-07 17:26:50,082 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 17:26:50,082 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:26:50,082 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:26:50,082 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:26:50,083 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:26:50,083 INFO L82 PathProgramCache]: Analyzing trace with hash 1361870049, now seen corresponding path program 1 times [2019-12-07 17:26:50,083 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:26:50,083 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [505203690] [2019-12-07 17:26:50,083 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:26:50,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:26:50,130 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:26:50,130 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [505203690] [2019-12-07 17:26:50,130 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:26:50,130 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 17:26:50,131 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [770364028] [2019-12-07 17:26:50,131 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:26:50,131 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:26:50,131 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:26:50,131 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:26:50,132 INFO L87 Difference]: Start difference. First operand 51736 states and 163246 transitions. Second operand 6 states. [2019-12-07 17:26:50,728 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:26:50,728 INFO L93 Difference]: Finished difference Result 97116 states and 305877 transitions. [2019-12-07 17:26:50,729 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 17:26:50,729 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 27 [2019-12-07 17:26:50,729 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:26:50,872 INFO L225 Difference]: With dead ends: 97116 [2019-12-07 17:26:50,872 INFO L226 Difference]: Without dead ends: 97097 [2019-12-07 17:26:50,872 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=47, Unknown=0, NotChecked=0, Total=72 [2019-12-07 17:26:51,191 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97097 states. [2019-12-07 17:26:51,956 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97097 to 56317. [2019-12-07 17:26:51,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 56317 states. [2019-12-07 17:26:52,057 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56317 states to 56317 states and 177413 transitions. [2019-12-07 17:26:52,057 INFO L78 Accepts]: Start accepts. Automaton has 56317 states and 177413 transitions. Word has length 27 [2019-12-07 17:26:52,057 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:26:52,057 INFO L462 AbstractCegarLoop]: Abstraction has 56317 states and 177413 transitions. [2019-12-07 17:26:52,058 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:26:52,058 INFO L276 IsEmpty]: Start isEmpty. Operand 56317 states and 177413 transitions. [2019-12-07 17:26:52,075 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-12-07 17:26:52,075 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:26:52,075 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:26:52,075 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:26:52,075 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:26:52,075 INFO L82 PathProgramCache]: Analyzing trace with hash -2015671980, now seen corresponding path program 1 times [2019-12-07 17:26:52,075 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:26:52,075 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1235261253] [2019-12-07 17:26:52,076 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:26:52,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:26:52,125 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:26:52,125 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1235261253] [2019-12-07 17:26:52,125 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:26:52,125 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 17:26:52,125 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [55577216] [2019-12-07 17:26:52,125 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:26:52,125 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:26:52,125 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:26:52,126 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:26:52,126 INFO L87 Difference]: Start difference. First operand 56317 states and 177413 transitions. Second operand 6 states. [2019-12-07 17:26:52,698 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:26:52,698 INFO L93 Difference]: Finished difference Result 92170 states and 288131 transitions. [2019-12-07 17:26:52,698 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 17:26:52,699 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 28 [2019-12-07 17:26:52,699 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:26:52,848 INFO L225 Difference]: With dead ends: 92170 [2019-12-07 17:26:52,848 INFO L226 Difference]: Without dead ends: 92148 [2019-12-07 17:26:52,849 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=47, Unknown=0, NotChecked=0, Total=72 [2019-12-07 17:26:53,295 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92148 states. [2019-12-07 17:26:53,975 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92148 to 55804. [2019-12-07 17:26:53,975 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 55804 states. [2019-12-07 17:26:54,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55804 states to 55804 states and 175723 transitions. [2019-12-07 17:26:54,074 INFO L78 Accepts]: Start accepts. Automaton has 55804 states and 175723 transitions. Word has length 28 [2019-12-07 17:26:54,074 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:26:54,074 INFO L462 AbstractCegarLoop]: Abstraction has 55804 states and 175723 transitions. [2019-12-07 17:26:54,074 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:26:54,074 INFO L276 IsEmpty]: Start isEmpty. Operand 55804 states and 175723 transitions. [2019-12-07 17:26:54,091 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-12-07 17:26:54,091 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:26:54,092 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:26:54,092 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:26:54,092 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:26:54,092 INFO L82 PathProgramCache]: Analyzing trace with hash -1692206128, now seen corresponding path program 1 times [2019-12-07 17:26:54,092 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:26:54,092 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [417666778] [2019-12-07 17:26:54,092 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:26:54,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:26:54,141 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:26:54,141 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [417666778] [2019-12-07 17:26:54,141 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:26:54,141 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:26:54,141 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [415098658] [2019-12-07 17:26:54,142 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:26:54,142 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:26:54,142 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:26:54,142 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:26:54,142 INFO L87 Difference]: Start difference. First operand 55804 states and 175723 transitions. Second operand 5 states. [2019-12-07 17:26:54,660 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:26:54,660 INFO L93 Difference]: Finished difference Result 77000 states and 239966 transitions. [2019-12-07 17:26:54,661 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 17:26:54,661 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 28 [2019-12-07 17:26:54,661 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:26:54,770 INFO L225 Difference]: With dead ends: 77000 [2019-12-07 17:26:54,771 INFO L226 Difference]: Without dead ends: 77000 [2019-12-07 17:26:54,771 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:26:55,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77000 states. [2019-12-07 17:26:55,775 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77000 to 67374. [2019-12-07 17:26:55,775 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 67374 states. [2019-12-07 17:26:55,896 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67374 states to 67374 states and 211767 transitions. [2019-12-07 17:26:55,896 INFO L78 Accepts]: Start accepts. Automaton has 67374 states and 211767 transitions. Word has length 28 [2019-12-07 17:26:55,896 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:26:55,896 INFO L462 AbstractCegarLoop]: Abstraction has 67374 states and 211767 transitions. [2019-12-07 17:26:55,896 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:26:55,896 INFO L276 IsEmpty]: Start isEmpty. Operand 67374 states and 211767 transitions. [2019-12-07 17:26:55,916 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-12-07 17:26:55,916 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:26:55,916 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:26:55,917 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:26:55,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:26:55,917 INFO L82 PathProgramCache]: Analyzing trace with hash 46100818, now seen corresponding path program 1 times [2019-12-07 17:26:55,917 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:26:55,917 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [210655319] [2019-12-07 17:26:55,917 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:26:55,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:26:55,987 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:26:55,987 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [210655319] [2019-12-07 17:26:55,987 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:26:55,987 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:26:55,987 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [840235430] [2019-12-07 17:26:55,987 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:26:55,987 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:26:55,988 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:26:55,988 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:26:55,988 INFO L87 Difference]: Start difference. First operand 67374 states and 211767 transitions. Second operand 5 states. [2019-12-07 17:26:56,582 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:26:56,582 INFO L93 Difference]: Finished difference Result 90697 states and 281988 transitions. [2019-12-07 17:26:56,583 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 17:26:56,583 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 29 [2019-12-07 17:26:56,583 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:26:56,716 INFO L225 Difference]: With dead ends: 90697 [2019-12-07 17:26:56,716 INFO L226 Difference]: Without dead ends: 90690 [2019-12-07 17:26:56,716 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:26:57,138 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90690 states. [2019-12-07 17:26:57,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90690 to 72515. [2019-12-07 17:26:57,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72515 states. [2019-12-07 17:26:58,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72515 states to 72515 states and 228160 transitions. [2019-12-07 17:26:58,003 INFO L78 Accepts]: Start accepts. Automaton has 72515 states and 228160 transitions. Word has length 29 [2019-12-07 17:26:58,003 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:26:58,003 INFO L462 AbstractCegarLoop]: Abstraction has 72515 states and 228160 transitions. [2019-12-07 17:26:58,003 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:26:58,003 INFO L276 IsEmpty]: Start isEmpty. Operand 72515 states and 228160 transitions. [2019-12-07 17:26:58,024 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-12-07 17:26:58,024 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:26:58,024 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:26:58,024 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:26:58,024 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:26:58,024 INFO L82 PathProgramCache]: Analyzing trace with hash -238960576, now seen corresponding path program 1 times [2019-12-07 17:26:58,025 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:26:58,025 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1026328772] [2019-12-07 17:26:58,025 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:26:58,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:26:58,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:26:58,055 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1026328772] [2019-12-07 17:26:58,055 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:26:58,055 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 17:26:58,055 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [277152486] [2019-12-07 17:26:58,056 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:26:58,056 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:26:58,056 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:26:58,056 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:26:58,056 INFO L87 Difference]: Start difference. First operand 72515 states and 228160 transitions. Second operand 3 states. [2019-12-07 17:26:58,250 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:26:58,251 INFO L93 Difference]: Finished difference Result 72456 states and 227984 transitions. [2019-12-07 17:26:58,251 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:26:58,251 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 29 [2019-12-07 17:26:58,251 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:26:58,355 INFO L225 Difference]: With dead ends: 72456 [2019-12-07 17:26:58,355 INFO L226 Difference]: Without dead ends: 72456 [2019-12-07 17:26:58,355 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:26:58,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72456 states. [2019-12-07 17:26:59,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72456 to 72456. [2019-12-07 17:26:59,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72456 states. [2019-12-07 17:26:59,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72456 states to 72456 states and 227984 transitions. [2019-12-07 17:26:59,448 INFO L78 Accepts]: Start accepts. Automaton has 72456 states and 227984 transitions. Word has length 29 [2019-12-07 17:26:59,448 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:26:59,448 INFO L462 AbstractCegarLoop]: Abstraction has 72456 states and 227984 transitions. [2019-12-07 17:26:59,448 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:26:59,448 INFO L276 IsEmpty]: Start isEmpty. Operand 72456 states and 227984 transitions. [2019-12-07 17:26:59,476 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2019-12-07 17:26:59,476 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:26:59,476 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:26:59,476 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:26:59,476 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:26:59,476 INFO L82 PathProgramCache]: Analyzing trace with hash 1610566857, now seen corresponding path program 1 times [2019-12-07 17:26:59,477 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:26:59,477 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [957289700] [2019-12-07 17:26:59,477 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:26:59,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:26:59,509 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:26:59,509 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [957289700] [2019-12-07 17:26:59,509 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:26:59,510 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:26:59,510 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [130647066] [2019-12-07 17:26:59,510 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:26:59,510 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:26:59,510 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:26:59,510 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:26:59,510 INFO L87 Difference]: Start difference. First operand 72456 states and 227984 transitions. Second operand 4 states. [2019-12-07 17:26:59,600 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:26:59,600 INFO L93 Difference]: Finished difference Result 31700 states and 94383 transitions. [2019-12-07 17:26:59,600 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 17:26:59,600 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 30 [2019-12-07 17:26:59,600 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:26:59,637 INFO L225 Difference]: With dead ends: 31700 [2019-12-07 17:26:59,637 INFO L226 Difference]: Without dead ends: 31700 [2019-12-07 17:26:59,637 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:26:59,731 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31700 states. [2019-12-07 17:27:00,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31700 to 29568. [2019-12-07 17:27:00,015 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29568 states. [2019-12-07 17:27:00,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29568 states to 29568 states and 88189 transitions. [2019-12-07 17:27:00,061 INFO L78 Accepts]: Start accepts. Automaton has 29568 states and 88189 transitions. Word has length 30 [2019-12-07 17:27:00,061 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:00,062 INFO L462 AbstractCegarLoop]: Abstraction has 29568 states and 88189 transitions. [2019-12-07 17:27:00,062 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:27:00,062 INFO L276 IsEmpty]: Start isEmpty. Operand 29568 states and 88189 transitions. [2019-12-07 17:27:00,081 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-12-07 17:27:00,081 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:00,081 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:00,081 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:00,081 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:00,081 INFO L82 PathProgramCache]: Analyzing trace with hash 405285854, now seen corresponding path program 1 times [2019-12-07 17:27:00,081 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:00,081 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [23720081] [2019-12-07 17:27:00,081 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:00,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:00,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:00,113 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [23720081] [2019-12-07 17:27:00,113 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:00,113 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:27:00,113 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1496357937] [2019-12-07 17:27:00,113 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:27:00,113 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:00,113 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:27:00,114 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:27:00,114 INFO L87 Difference]: Start difference. First operand 29568 states and 88189 transitions. Second operand 5 states. [2019-12-07 17:27:00,386 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:00,386 INFO L93 Difference]: Finished difference Result 33239 states and 98209 transitions. [2019-12-07 17:27:00,386 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 17:27:00,386 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 33 [2019-12-07 17:27:00,386 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:00,423 INFO L225 Difference]: With dead ends: 33239 [2019-12-07 17:27:00,423 INFO L226 Difference]: Without dead ends: 33239 [2019-12-07 17:27:00,424 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:27:00,521 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33239 states. [2019-12-07 17:27:00,843 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33239 to 29892. [2019-12-07 17:27:00,843 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29892 states. [2019-12-07 17:27:00,888 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29892 states to 29892 states and 89113 transitions. [2019-12-07 17:27:00,888 INFO L78 Accepts]: Start accepts. Automaton has 29892 states and 89113 transitions. Word has length 33 [2019-12-07 17:27:00,888 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:00,889 INFO L462 AbstractCegarLoop]: Abstraction has 29892 states and 89113 transitions. [2019-12-07 17:27:00,889 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:27:00,889 INFO L276 IsEmpty]: Start isEmpty. Operand 29892 states and 89113 transitions. [2019-12-07 17:27:00,907 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-12-07 17:27:00,907 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:00,908 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:00,908 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:00,908 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:00,908 INFO L82 PathProgramCache]: Analyzing trace with hash -1258895234, now seen corresponding path program 2 times [2019-12-07 17:27:00,908 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:00,908 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1365743469] [2019-12-07 17:27:00,908 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:00,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:00,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:00,961 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1365743469] [2019-12-07 17:27:00,961 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:00,961 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:27:00,961 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2051824160] [2019-12-07 17:27:00,961 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 17:27:00,962 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:00,962 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 17:27:00,962 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:27:00,962 INFO L87 Difference]: Start difference. First operand 29892 states and 89113 transitions. Second operand 7 states. [2019-12-07 17:27:01,896 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:01,896 INFO L93 Difference]: Finished difference Result 54635 states and 161134 transitions. [2019-12-07 17:27:01,897 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 17:27:01,897 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 33 [2019-12-07 17:27:01,897 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:01,973 INFO L225 Difference]: With dead ends: 54635 [2019-12-07 17:27:01,973 INFO L226 Difference]: Without dead ends: 54635 [2019-12-07 17:27:01,973 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 62 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=89, Invalid=253, Unknown=0, NotChecked=0, Total=342 [2019-12-07 17:27:02,114 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54635 states. [2019-12-07 17:27:02,513 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54635 to 31452. [2019-12-07 17:27:02,513 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31452 states. [2019-12-07 17:27:02,562 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31452 states to 31452 states and 93851 transitions. [2019-12-07 17:27:02,562 INFO L78 Accepts]: Start accepts. Automaton has 31452 states and 93851 transitions. Word has length 33 [2019-12-07 17:27:02,562 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:02,562 INFO L462 AbstractCegarLoop]: Abstraction has 31452 states and 93851 transitions. [2019-12-07 17:27:02,562 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 17:27:02,563 INFO L276 IsEmpty]: Start isEmpty. Operand 31452 states and 93851 transitions. [2019-12-07 17:27:02,582 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-12-07 17:27:02,582 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:02,582 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:02,582 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:02,582 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:02,582 INFO L82 PathProgramCache]: Analyzing trace with hash -454706214, now seen corresponding path program 3 times [2019-12-07 17:27:02,582 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:02,582 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [103941616] [2019-12-07 17:27:02,583 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:02,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:02,644 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:02,644 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [103941616] [2019-12-07 17:27:02,644 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:02,645 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 17:27:02,645 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [715355507] [2019-12-07 17:27:02,645 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 17:27:02,645 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:02,645 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 17:27:02,645 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2019-12-07 17:27:02,645 INFO L87 Difference]: Start difference. First operand 31452 states and 93851 transitions. Second operand 8 states. [2019-12-07 17:27:04,104 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:04,104 INFO L93 Difference]: Finished difference Result 68549 states and 199949 transitions. [2019-12-07 17:27:04,104 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2019-12-07 17:27:04,104 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 33 [2019-12-07 17:27:04,104 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:04,189 INFO L225 Difference]: With dead ends: 68549 [2019-12-07 17:27:04,189 INFO L226 Difference]: Without dead ends: 68549 [2019-12-07 17:27:04,190 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 154 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=161, Invalid=489, Unknown=0, NotChecked=0, Total=650 [2019-12-07 17:27:04,355 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68549 states. [2019-12-07 17:27:04,830 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68549 to 31447. [2019-12-07 17:27:04,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31447 states. [2019-12-07 17:27:04,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31447 states to 31447 states and 93881 transitions. [2019-12-07 17:27:04,881 INFO L78 Accepts]: Start accepts. Automaton has 31447 states and 93881 transitions. Word has length 33 [2019-12-07 17:27:04,881 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:04,881 INFO L462 AbstractCegarLoop]: Abstraction has 31447 states and 93881 transitions. [2019-12-07 17:27:04,881 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 17:27:04,881 INFO L276 IsEmpty]: Start isEmpty. Operand 31447 states and 93881 transitions. [2019-12-07 17:27:04,902 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 17:27:04,902 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:04,902 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:04,902 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:04,902 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:04,902 INFO L82 PathProgramCache]: Analyzing trace with hash -1655017129, now seen corresponding path program 1 times [2019-12-07 17:27:04,903 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:04,903 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1372766171] [2019-12-07 17:27:04,903 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:04,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:04,969 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:04,969 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1372766171] [2019-12-07 17:27:04,970 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:04,970 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:27:04,970 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1134752915] [2019-12-07 17:27:04,970 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 17:27:04,970 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:04,970 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 17:27:04,970 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:27:04,970 INFO L87 Difference]: Start difference. First operand 31447 states and 93881 transitions. Second operand 7 states. [2019-12-07 17:27:05,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:05,777 INFO L93 Difference]: Finished difference Result 53332 states and 156834 transitions. [2019-12-07 17:27:05,778 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 17:27:05,778 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 34 [2019-12-07 17:27:05,778 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:05,839 INFO L225 Difference]: With dead ends: 53332 [2019-12-07 17:27:05,839 INFO L226 Difference]: Without dead ends: 53332 [2019-12-07 17:27:05,839 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 1 SyntacticMatches, 3 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 62 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=89, Invalid=253, Unknown=0, NotChecked=0, Total=342 [2019-12-07 17:27:05,970 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53332 states. [2019-12-07 17:27:06,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53332 to 30638. [2019-12-07 17:27:06,370 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30638 states. [2019-12-07 17:27:06,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30638 states to 30638 states and 91448 transitions. [2019-12-07 17:27:06,419 INFO L78 Accepts]: Start accepts. Automaton has 30638 states and 91448 transitions. Word has length 34 [2019-12-07 17:27:06,419 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:06,419 INFO L462 AbstractCegarLoop]: Abstraction has 30638 states and 91448 transitions. [2019-12-07 17:27:06,419 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 17:27:06,419 INFO L276 IsEmpty]: Start isEmpty. Operand 30638 states and 91448 transitions. [2019-12-07 17:27:06,439 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 17:27:06,439 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:06,439 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:06,439 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:06,439 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:06,439 INFO L82 PathProgramCache]: Analyzing trace with hash 2107636055, now seen corresponding path program 2 times [2019-12-07 17:27:06,439 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:06,439 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1562614576] [2019-12-07 17:27:06,440 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:06,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:06,494 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:06,494 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1562614576] [2019-12-07 17:27:06,494 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:06,495 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 17:27:06,495 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [569481088] [2019-12-07 17:27:06,495 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 17:27:06,495 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:06,495 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 17:27:06,495 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2019-12-07 17:27:06,496 INFO L87 Difference]: Start difference. First operand 30638 states and 91448 transitions. Second operand 8 states. [2019-12-07 17:27:08,821 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:08,822 INFO L93 Difference]: Finished difference Result 63692 states and 185351 transitions. [2019-12-07 17:27:08,822 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2019-12-07 17:27:08,822 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 34 [2019-12-07 17:27:08,822 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:08,899 INFO L225 Difference]: With dead ends: 63692 [2019-12-07 17:27:08,900 INFO L226 Difference]: Without dead ends: 63692 [2019-12-07 17:27:08,900 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 148 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=161, Invalid=489, Unknown=0, NotChecked=0, Total=650 [2019-12-07 17:27:09,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63692 states. [2019-12-07 17:27:09,501 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63692 to 30398. [2019-12-07 17:27:09,502 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30398 states. [2019-12-07 17:27:09,551 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30398 states to 30398 states and 90676 transitions. [2019-12-07 17:27:09,552 INFO L78 Accepts]: Start accepts. Automaton has 30398 states and 90676 transitions. Word has length 34 [2019-12-07 17:27:09,552 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:09,552 INFO L462 AbstractCegarLoop]: Abstraction has 30398 states and 90676 transitions. [2019-12-07 17:27:09,552 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 17:27:09,552 INFO L276 IsEmpty]: Start isEmpty. Operand 30398 states and 90676 transitions. [2019-12-07 17:27:09,579 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2019-12-07 17:27:09,579 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:09,579 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:09,580 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:09,580 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:09,580 INFO L82 PathProgramCache]: Analyzing trace with hash -1078981085, now seen corresponding path program 1 times [2019-12-07 17:27:09,580 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:09,580 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1004449959] [2019-12-07 17:27:09,580 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:09,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:09,638 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:09,638 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1004449959] [2019-12-07 17:27:09,638 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:09,638 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 17:27:09,638 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1000562475] [2019-12-07 17:27:09,639 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:27:09,639 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:09,639 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:27:09,639 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:27:09,639 INFO L87 Difference]: Start difference. First operand 30398 states and 90676 transitions. Second operand 6 states. [2019-12-07 17:27:10,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:10,375 INFO L93 Difference]: Finished difference Result 40164 states and 117722 transitions. [2019-12-07 17:27:10,376 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 17:27:10,376 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 40 [2019-12-07 17:27:10,376 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:10,419 INFO L225 Difference]: With dead ends: 40164 [2019-12-07 17:27:10,420 INFO L226 Difference]: Without dead ends: 40164 [2019-12-07 17:27:10,420 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 8 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2019-12-07 17:27:10,528 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40164 states. [2019-12-07 17:27:10,850 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40164 to 31265. [2019-12-07 17:27:10,851 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31265 states. [2019-12-07 17:27:10,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31265 states to 31265 states and 93247 transitions. [2019-12-07 17:27:10,900 INFO L78 Accepts]: Start accepts. Automaton has 31265 states and 93247 transitions. Word has length 40 [2019-12-07 17:27:10,900 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:10,900 INFO L462 AbstractCegarLoop]: Abstraction has 31265 states and 93247 transitions. [2019-12-07 17:27:10,900 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:27:10,900 INFO L276 IsEmpty]: Start isEmpty. Operand 31265 states and 93247 transitions. [2019-12-07 17:27:10,927 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2019-12-07 17:27:10,927 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:10,927 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:10,928 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:10,928 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:10,928 INFO L82 PathProgramCache]: Analyzing trace with hash -1549595633, now seen corresponding path program 2 times [2019-12-07 17:27:10,928 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:10,928 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [217777343] [2019-12-07 17:27:10,928 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:10,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:10,956 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:10,956 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [217777343] [2019-12-07 17:27:10,956 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:10,956 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:27:10,956 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1917153462] [2019-12-07 17:27:10,956 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:27:10,957 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:10,957 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:27:10,957 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:27:10,957 INFO L87 Difference]: Start difference. First operand 31265 states and 93247 transitions. Second operand 3 states. [2019-12-07 17:27:11,037 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:11,038 INFO L93 Difference]: Finished difference Result 31177 states and 92975 transitions. [2019-12-07 17:27:11,038 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:27:11,038 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 40 [2019-12-07 17:27:11,038 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:11,075 INFO L225 Difference]: With dead ends: 31177 [2019-12-07 17:27:11,076 INFO L226 Difference]: Without dead ends: 31177 [2019-12-07 17:27:11,076 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:27:11,166 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31177 states. [2019-12-07 17:27:11,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31177 to 25414. [2019-12-07 17:27:11,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25414 states. [2019-12-07 17:27:11,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25414 states to 25414 states and 76561 transitions. [2019-12-07 17:27:11,476 INFO L78 Accepts]: Start accepts. Automaton has 25414 states and 76561 transitions. Word has length 40 [2019-12-07 17:27:11,476 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:11,476 INFO L462 AbstractCegarLoop]: Abstraction has 25414 states and 76561 transitions. [2019-12-07 17:27:11,476 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:27:11,476 INFO L276 IsEmpty]: Start isEmpty. Operand 25414 states and 76561 transitions. [2019-12-07 17:27:11,496 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2019-12-07 17:27:11,496 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:11,497 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:11,497 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:11,497 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:11,497 INFO L82 PathProgramCache]: Analyzing trace with hash 1591146573, now seen corresponding path program 1 times [2019-12-07 17:27:11,497 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:11,497 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [544820297] [2019-12-07 17:27:11,497 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:11,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:11,547 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:11,547 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [544820297] [2019-12-07 17:27:11,547 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:11,548 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:27:11,548 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [218525736] [2019-12-07 17:27:11,548 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:27:11,548 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:11,548 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:27:11,548 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:27:11,548 INFO L87 Difference]: Start difference. First operand 25414 states and 76561 transitions. Second operand 4 states. [2019-12-07 17:27:11,674 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:11,674 INFO L93 Difference]: Finished difference Result 46314 states and 139627 transitions. [2019-12-07 17:27:11,674 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:27:11,674 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 41 [2019-12-07 17:27:11,674 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:11,723 INFO L225 Difference]: With dead ends: 46314 [2019-12-07 17:27:11,723 INFO L226 Difference]: Without dead ends: 42149 [2019-12-07 17:27:11,723 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:27:11,836 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42149 states. [2019-12-07 17:27:12,232 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42149 to 40787. [2019-12-07 17:27:12,232 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40787 states. [2019-12-07 17:27:12,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40787 states to 40787 states and 122778 transitions. [2019-12-07 17:27:12,296 INFO L78 Accepts]: Start accepts. Automaton has 40787 states and 122778 transitions. Word has length 41 [2019-12-07 17:27:12,296 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:12,297 INFO L462 AbstractCegarLoop]: Abstraction has 40787 states and 122778 transitions. [2019-12-07 17:27:12,297 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:27:12,297 INFO L276 IsEmpty]: Start isEmpty. Operand 40787 states and 122778 transitions. [2019-12-07 17:27:12,333 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2019-12-07 17:27:12,334 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:12,334 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:12,334 INFO L410 AbstractCegarLoop]: === Iteration 23 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:12,334 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:12,334 INFO L82 PathProgramCache]: Analyzing trace with hash 2015159781, now seen corresponding path program 2 times [2019-12-07 17:27:12,334 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:12,334 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [640359264] [2019-12-07 17:27:12,334 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:12,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:12,366 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:12,366 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [640359264] [2019-12-07 17:27:12,366 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:12,367 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 17:27:12,367 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [701542566] [2019-12-07 17:27:12,367 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:27:12,367 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:12,367 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:27:12,367 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:27:12,368 INFO L87 Difference]: Start difference. First operand 40787 states and 122778 transitions. Second operand 5 states. [2019-12-07 17:27:12,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:12,471 INFO L93 Difference]: Finished difference Result 38363 states and 117541 transitions. [2019-12-07 17:27:12,471 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:27:12,471 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 41 [2019-12-07 17:27:12,471 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:12,517 INFO L225 Difference]: With dead ends: 38363 [2019-12-07 17:27:12,517 INFO L226 Difference]: Without dead ends: 37807 [2019-12-07 17:27:12,518 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:27:12,625 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37807 states. [2019-12-07 17:27:12,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37807 to 21814. [2019-12-07 17:27:12,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21814 states. [2019-12-07 17:27:12,994 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21814 states to 21814 states and 67085 transitions. [2019-12-07 17:27:12,994 INFO L78 Accepts]: Start accepts. Automaton has 21814 states and 67085 transitions. Word has length 41 [2019-12-07 17:27:12,994 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:12,994 INFO L462 AbstractCegarLoop]: Abstraction has 21814 states and 67085 transitions. [2019-12-07 17:27:12,994 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:27:12,994 INFO L276 IsEmpty]: Start isEmpty. Operand 21814 states and 67085 transitions. [2019-12-07 17:27:13,010 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 17:27:13,010 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:13,010 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:13,010 INFO L410 AbstractCegarLoop]: === Iteration 24 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:13,011 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:13,011 INFO L82 PathProgramCache]: Analyzing trace with hash -961209461, now seen corresponding path program 1 times [2019-12-07 17:27:13,011 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:13,011 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [374608580] [2019-12-07 17:27:13,011 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:13,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:13,048 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:13,048 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [374608580] [2019-12-07 17:27:13,048 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:13,049 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:27:13,049 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [712080398] [2019-12-07 17:27:13,049 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:27:13,049 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:13,049 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:27:13,049 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:27:13,049 INFO L87 Difference]: Start difference. First operand 21814 states and 67085 transitions. Second operand 3 states. [2019-12-07 17:27:13,134 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:13,134 INFO L93 Difference]: Finished difference Result 25003 states and 77044 transitions. [2019-12-07 17:27:13,134 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:27:13,135 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 65 [2019-12-07 17:27:13,135 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:13,165 INFO L225 Difference]: With dead ends: 25003 [2019-12-07 17:27:13,165 INFO L226 Difference]: Without dead ends: 25003 [2019-12-07 17:27:13,165 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:27:13,242 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25003 states. [2019-12-07 17:27:13,443 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25003 to 21008. [2019-12-07 17:27:13,443 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21008 states. [2019-12-07 17:27:13,474 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21008 states to 21008 states and 64974 transitions. [2019-12-07 17:27:13,474 INFO L78 Accepts]: Start accepts. Automaton has 21008 states and 64974 transitions. Word has length 65 [2019-12-07 17:27:13,474 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:13,474 INFO L462 AbstractCegarLoop]: Abstraction has 21008 states and 64974 transitions. [2019-12-07 17:27:13,474 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:27:13,474 INFO L276 IsEmpty]: Start isEmpty. Operand 21008 states and 64974 transitions. [2019-12-07 17:27:13,491 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:27:13,491 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:13,491 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:13,491 INFO L410 AbstractCegarLoop]: === Iteration 25 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:13,491 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:13,491 INFO L82 PathProgramCache]: Analyzing trace with hash -2050011334, now seen corresponding path program 1 times [2019-12-07 17:27:13,491 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:13,492 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2135112839] [2019-12-07 17:27:13,492 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:13,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:13,555 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:13,555 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2135112839] [2019-12-07 17:27:13,555 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:13,555 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 17:27:13,555 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [243219397] [2019-12-07 17:27:13,556 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 17:27:13,556 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:13,556 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 17:27:13,556 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:27:13,556 INFO L87 Difference]: Start difference. First operand 21008 states and 64974 transitions. Second operand 7 states. [2019-12-07 17:27:14,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:14,403 INFO L93 Difference]: Finished difference Result 36128 states and 109047 transitions. [2019-12-07 17:27:14,403 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2019-12-07 17:27:14,404 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 66 [2019-12-07 17:27:14,404 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:14,443 INFO L225 Difference]: With dead ends: 36128 [2019-12-07 17:27:14,443 INFO L226 Difference]: Without dead ends: 36128 [2019-12-07 17:27:14,443 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 13 SyntacticMatches, 1 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 42 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=81, Invalid=225, Unknown=0, NotChecked=0, Total=306 [2019-12-07 17:27:14,541 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36128 states. [2019-12-07 17:27:14,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36128 to 21806. [2019-12-07 17:27:14,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21806 states. [2019-12-07 17:27:14,838 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21806 states to 21806 states and 67377 transitions. [2019-12-07 17:27:14,838 INFO L78 Accepts]: Start accepts. Automaton has 21806 states and 67377 transitions. Word has length 66 [2019-12-07 17:27:14,838 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:14,838 INFO L462 AbstractCegarLoop]: Abstraction has 21806 states and 67377 transitions. [2019-12-07 17:27:14,838 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 17:27:14,838 INFO L276 IsEmpty]: Start isEmpty. Operand 21806 states and 67377 transitions. [2019-12-07 17:27:14,857 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:27:14,857 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:14,857 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:14,857 INFO L410 AbstractCegarLoop]: === Iteration 26 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:14,857 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:14,857 INFO L82 PathProgramCache]: Analyzing trace with hash -1443128569, now seen corresponding path program 1 times [2019-12-07 17:27:14,857 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:14,858 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [604690442] [2019-12-07 17:27:14,858 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:14,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:14,990 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:14,991 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [604690442] [2019-12-07 17:27:14,991 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:14,991 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 17:27:14,991 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1782798282] [2019-12-07 17:27:14,991 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 17:27:14,991 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:14,991 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 17:27:14,991 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=58, Unknown=0, NotChecked=0, Total=90 [2019-12-07 17:27:14,991 INFO L87 Difference]: Start difference. First operand 21806 states and 67377 transitions. Second operand 10 states. [2019-12-07 17:27:15,567 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:15,567 INFO L93 Difference]: Finished difference Result 55700 states and 170099 transitions. [2019-12-07 17:27:15,568 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2019-12-07 17:27:15,568 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 66 [2019-12-07 17:27:15,568 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:15,591 INFO L225 Difference]: With dead ends: 55700 [2019-12-07 17:27:15,591 INFO L226 Difference]: Without dead ends: 18467 [2019-12-07 17:27:15,591 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 35 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=84, Invalid=156, Unknown=0, NotChecked=0, Total=240 [2019-12-07 17:27:15,655 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18467 states. [2019-12-07 17:27:15,814 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18467 to 18467. [2019-12-07 17:27:15,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18467 states. [2019-12-07 17:27:15,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18467 states to 18467 states and 57293 transitions. [2019-12-07 17:27:15,842 INFO L78 Accepts]: Start accepts. Automaton has 18467 states and 57293 transitions. Word has length 66 [2019-12-07 17:27:15,842 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:15,842 INFO L462 AbstractCegarLoop]: Abstraction has 18467 states and 57293 transitions. [2019-12-07 17:27:15,842 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 17:27:15,842 INFO L276 IsEmpty]: Start isEmpty. Operand 18467 states and 57293 transitions. [2019-12-07 17:27:15,857 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:27:15,857 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:15,857 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:15,857 INFO L410 AbstractCegarLoop]: === Iteration 27 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:15,858 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:15,858 INFO L82 PathProgramCache]: Analyzing trace with hash 1904298335, now seen corresponding path program 2 times [2019-12-07 17:27:15,858 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:15,858 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1671188602] [2019-12-07 17:27:15,858 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:15,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:15,898 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:15,899 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1671188602] [2019-12-07 17:27:15,899 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:15,899 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:27:15,899 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1078561796] [2019-12-07 17:27:15,899 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:27:15,899 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:15,899 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:27:15,899 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:27:15,900 INFO L87 Difference]: Start difference. First operand 18467 states and 57293 transitions. Second operand 4 states. [2019-12-07 17:27:15,981 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:15,981 INFO L93 Difference]: Finished difference Result 32902 states and 102517 transitions. [2019-12-07 17:27:15,981 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 17:27:15,981 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 66 [2019-12-07 17:27:15,982 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:15,998 INFO L225 Difference]: With dead ends: 32902 [2019-12-07 17:27:15,998 INFO L226 Difference]: Without dead ends: 15700 [2019-12-07 17:27:15,999 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:27:16,057 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15700 states. [2019-12-07 17:27:16,185 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15700 to 15700. [2019-12-07 17:27:16,185 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15700 states. [2019-12-07 17:27:16,207 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15700 states to 15700 states and 48816 transitions. [2019-12-07 17:27:16,207 INFO L78 Accepts]: Start accepts. Automaton has 15700 states and 48816 transitions. Word has length 66 [2019-12-07 17:27:16,207 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:16,207 INFO L462 AbstractCegarLoop]: Abstraction has 15700 states and 48816 transitions. [2019-12-07 17:27:16,207 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:27:16,208 INFO L276 IsEmpty]: Start isEmpty. Operand 15700 states and 48816 transitions. [2019-12-07 17:27:16,220 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:27:16,220 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:16,220 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:16,221 INFO L410 AbstractCegarLoop]: === Iteration 28 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:16,221 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:16,221 INFO L82 PathProgramCache]: Analyzing trace with hash -1283449633, now seen corresponding path program 3 times [2019-12-07 17:27:16,221 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:16,221 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [514513364] [2019-12-07 17:27:16,221 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:16,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:16,275 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:16,275 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [514513364] [2019-12-07 17:27:16,275 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:16,276 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 17:27:16,276 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [301928804] [2019-12-07 17:27:16,276 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 17:27:16,276 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:16,276 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 17:27:16,276 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:27:16,277 INFO L87 Difference]: Start difference. First operand 15700 states and 48816 transitions. Second operand 7 states. [2019-12-07 17:27:16,468 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:16,468 INFO L93 Difference]: Finished difference Result 28353 states and 86761 transitions. [2019-12-07 17:27:16,468 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 17:27:16,468 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 66 [2019-12-07 17:27:16,468 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:16,490 INFO L225 Difference]: With dead ends: 28353 [2019-12-07 17:27:16,490 INFO L226 Difference]: Without dead ends: 20394 [2019-12-07 17:27:16,491 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=34, Invalid=98, Unknown=0, NotChecked=0, Total=132 [2019-12-07 17:27:16,559 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20394 states. [2019-12-07 17:27:16,732 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20394 to 17643. [2019-12-07 17:27:16,732 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17643 states. [2019-12-07 17:27:16,759 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17643 states to 17643 states and 54279 transitions. [2019-12-07 17:27:16,759 INFO L78 Accepts]: Start accepts. Automaton has 17643 states and 54279 transitions. Word has length 66 [2019-12-07 17:27:16,759 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:16,759 INFO L462 AbstractCegarLoop]: Abstraction has 17643 states and 54279 transitions. [2019-12-07 17:27:16,759 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 17:27:16,759 INFO L276 IsEmpty]: Start isEmpty. Operand 17643 states and 54279 transitions. [2019-12-07 17:27:16,773 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:27:16,774 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:16,774 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:16,774 INFO L410 AbstractCegarLoop]: === Iteration 29 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:16,774 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:16,774 INFO L82 PathProgramCache]: Analyzing trace with hash -599347457, now seen corresponding path program 4 times [2019-12-07 17:27:16,774 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:16,774 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1138933845] [2019-12-07 17:27:16,774 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:16,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:16,977 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:16,977 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1138933845] [2019-12-07 17:27:16,977 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:16,977 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 17:27:16,977 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [128148750] [2019-12-07 17:27:16,977 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 17:27:16,977 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:16,978 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 17:27:16,978 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=126, Unknown=0, NotChecked=0, Total=156 [2019-12-07 17:27:16,978 INFO L87 Difference]: Start difference. First operand 17643 states and 54279 transitions. Second operand 13 states. [2019-12-07 17:27:17,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:17,984 INFO L93 Difference]: Finished difference Result 30791 states and 92786 transitions. [2019-12-07 17:27:17,984 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-12-07 17:27:17,984 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 66 [2019-12-07 17:27:17,984 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:18,007 INFO L225 Difference]: With dead ends: 30791 [2019-12-07 17:27:18,008 INFO L226 Difference]: Without dead ends: 21424 [2019-12-07 17:27:18,008 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 9 SyntacticMatches, 2 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 122 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=136, Invalid=620, Unknown=0, NotChecked=0, Total=756 [2019-12-07 17:27:18,077 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21424 states. [2019-12-07 17:27:18,248 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21424 to 19440. [2019-12-07 17:27:18,248 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19440 states. [2019-12-07 17:27:18,277 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19440 states to 19440 states and 59532 transitions. [2019-12-07 17:27:18,277 INFO L78 Accepts]: Start accepts. Automaton has 19440 states and 59532 transitions. Word has length 66 [2019-12-07 17:27:18,277 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:18,277 INFO L462 AbstractCegarLoop]: Abstraction has 19440 states and 59532 transitions. [2019-12-07 17:27:18,277 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 17:27:18,278 INFO L276 IsEmpty]: Start isEmpty. Operand 19440 states and 59532 transitions. [2019-12-07 17:27:18,293 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:27:18,293 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:18,293 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:18,293 INFO L410 AbstractCegarLoop]: === Iteration 30 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:18,293 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:18,294 INFO L82 PathProgramCache]: Analyzing trace with hash -1212898232, now seen corresponding path program 2 times [2019-12-07 17:27:18,294 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:18,294 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [110560585] [2019-12-07 17:27:18,294 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:18,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:18,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:18,333 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [110560585] [2019-12-07 17:27:18,333 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:18,333 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:27:18,334 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [988542005] [2019-12-07 17:27:18,334 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:27:18,334 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:18,334 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:27:18,334 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:27:18,334 INFO L87 Difference]: Start difference. First operand 19440 states and 59532 transitions. Second operand 4 states. [2019-12-07 17:27:18,418 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:18,418 INFO L93 Difference]: Finished difference Result 19278 states and 58818 transitions. [2019-12-07 17:27:18,419 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 17:27:18,419 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 66 [2019-12-07 17:27:18,419 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:18,439 INFO L225 Difference]: With dead ends: 19278 [2019-12-07 17:27:18,439 INFO L226 Difference]: Without dead ends: 19278 [2019-12-07 17:27:18,440 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:27:18,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19278 states. [2019-12-07 17:27:18,697 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19278 to 17177. [2019-12-07 17:27:18,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17177 states. [2019-12-07 17:27:18,722 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17177 states to 17177 states and 52587 transitions. [2019-12-07 17:27:18,722 INFO L78 Accepts]: Start accepts. Automaton has 17177 states and 52587 transitions. Word has length 66 [2019-12-07 17:27:18,722 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:18,722 INFO L462 AbstractCegarLoop]: Abstraction has 17177 states and 52587 transitions. [2019-12-07 17:27:18,722 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:27:18,722 INFO L276 IsEmpty]: Start isEmpty. Operand 17177 states and 52587 transitions. [2019-12-07 17:27:18,737 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:27:18,737 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:18,737 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:18,737 INFO L410 AbstractCegarLoop]: === Iteration 31 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:18,738 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:18,738 INFO L82 PathProgramCache]: Analyzing trace with hash -691728939, now seen corresponding path program 5 times [2019-12-07 17:27:18,738 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:18,738 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [219858281] [2019-12-07 17:27:18,738 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:18,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:18,937 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:18,937 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [219858281] [2019-12-07 17:27:18,937 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:18,937 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 17:27:18,937 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [773795523] [2019-12-07 17:27:18,937 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 17:27:18,937 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:18,938 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 17:27:18,938 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=126, Unknown=0, NotChecked=0, Total=156 [2019-12-07 17:27:18,938 INFO L87 Difference]: Start difference. First operand 17177 states and 52587 transitions. Second operand 13 states. [2019-12-07 17:27:20,045 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:20,045 INFO L93 Difference]: Finished difference Result 27510 states and 82403 transitions. [2019-12-07 17:27:20,046 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2019-12-07 17:27:20,046 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 66 [2019-12-07 17:27:20,046 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:20,078 INFO L225 Difference]: With dead ends: 27510 [2019-12-07 17:27:20,078 INFO L226 Difference]: Without dead ends: 20148 [2019-12-07 17:27:20,079 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 9 SyntacticMatches, 2 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 231 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=223, Invalid=899, Unknown=0, NotChecked=0, Total=1122 [2019-12-07 17:27:20,146 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20148 states. [2019-12-07 17:27:20,301 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20148 to 17099. [2019-12-07 17:27:20,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17099 states. [2019-12-07 17:27:20,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17099 states to 17099 states and 52395 transitions. [2019-12-07 17:27:20,328 INFO L78 Accepts]: Start accepts. Automaton has 17099 states and 52395 transitions. Word has length 66 [2019-12-07 17:27:20,328 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:20,328 INFO L462 AbstractCegarLoop]: Abstraction has 17099 states and 52395 transitions. [2019-12-07 17:27:20,328 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 17:27:20,328 INFO L276 IsEmpty]: Start isEmpty. Operand 17099 states and 52395 transitions. [2019-12-07 17:27:20,342 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:27:20,342 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:20,343 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:20,343 INFO L410 AbstractCegarLoop]: === Iteration 32 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:20,343 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:20,343 INFO L82 PathProgramCache]: Analyzing trace with hash 1866390297, now seen corresponding path program 6 times [2019-12-07 17:27:20,343 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:20,343 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1473924688] [2019-12-07 17:27:20,343 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:20,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:20,427 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:20,427 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1473924688] [2019-12-07 17:27:20,427 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:20,427 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 17:27:20,427 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1014351235] [2019-12-07 17:27:20,427 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 17:27:20,427 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:20,427 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 17:27:20,428 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2019-12-07 17:27:20,428 INFO L87 Difference]: Start difference. First operand 17099 states and 52395 transitions. Second operand 8 states. [2019-12-07 17:27:21,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:21,346 INFO L93 Difference]: Finished difference Result 34472 states and 103904 transitions. [2019-12-07 17:27:21,346 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 17:27:21,346 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 66 [2019-12-07 17:27:21,347 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:21,385 INFO L225 Difference]: With dead ends: 34472 [2019-12-07 17:27:21,386 INFO L226 Difference]: Without dead ends: 34472 [2019-12-07 17:27:21,386 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 6 SyntacticMatches, 1 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 54 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=93, Invalid=249, Unknown=0, NotChecked=0, Total=342 [2019-12-07 17:27:21,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34472 states. [2019-12-07 17:27:21,720 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34472 to 17123. [2019-12-07 17:27:21,720 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17123 states. [2019-12-07 17:27:21,747 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17123 states to 17123 states and 52463 transitions. [2019-12-07 17:27:21,747 INFO L78 Accepts]: Start accepts. Automaton has 17123 states and 52463 transitions. Word has length 66 [2019-12-07 17:27:21,748 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:21,748 INFO L462 AbstractCegarLoop]: Abstraction has 17123 states and 52463 transitions. [2019-12-07 17:27:21,748 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 17:27:21,748 INFO L276 IsEmpty]: Start isEmpty. Operand 17123 states and 52463 transitions. [2019-12-07 17:27:21,762 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:27:21,762 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:21,762 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:21,763 INFO L410 AbstractCegarLoop]: === Iteration 33 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:21,763 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:21,763 INFO L82 PathProgramCache]: Analyzing trace with hash -1129852765, now seen corresponding path program 7 times [2019-12-07 17:27:21,763 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:21,763 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1438189788] [2019-12-07 17:27:21,763 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:21,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:21,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:21,852 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1438189788] [2019-12-07 17:27:21,852 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:21,852 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 17:27:21,852 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [986969896] [2019-12-07 17:27:21,852 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-12-07 17:27:21,852 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:21,852 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 17:27:21,853 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2019-12-07 17:27:21,853 INFO L87 Difference]: Start difference. First operand 17123 states and 52463 transitions. Second operand 9 states. [2019-12-07 17:27:22,589 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:22,589 INFO L93 Difference]: Finished difference Result 28994 states and 87498 transitions. [2019-12-07 17:27:22,589 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-12-07 17:27:22,589 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 66 [2019-12-07 17:27:22,589 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:22,620 INFO L225 Difference]: With dead ends: 28994 [2019-12-07 17:27:22,620 INFO L226 Difference]: Without dead ends: 28994 [2019-12-07 17:27:22,620 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=70, Invalid=170, Unknown=0, NotChecked=0, Total=240 [2019-12-07 17:27:22,705 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28994 states. [2019-12-07 17:27:22,915 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28994 to 17099. [2019-12-07 17:27:22,915 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17099 states. [2019-12-07 17:27:22,942 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17099 states to 17099 states and 52395 transitions. [2019-12-07 17:27:22,942 INFO L78 Accepts]: Start accepts. Automaton has 17099 states and 52395 transitions. Word has length 66 [2019-12-07 17:27:22,942 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:22,942 INFO L462 AbstractCegarLoop]: Abstraction has 17099 states and 52395 transitions. [2019-12-07 17:27:22,942 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-12-07 17:27:22,942 INFO L276 IsEmpty]: Start isEmpty. Operand 17099 states and 52395 transitions. [2019-12-07 17:27:22,956 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:27:22,956 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:22,956 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:22,957 INFO L410 AbstractCegarLoop]: === Iteration 34 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:22,957 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:22,957 INFO L82 PathProgramCache]: Analyzing trace with hash -995601251, now seen corresponding path program 8 times [2019-12-07 17:27:22,957 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:22,957 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1469094508] [2019-12-07 17:27:22,957 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:22,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:23,282 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:23,282 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1469094508] [2019-12-07 17:27:23,282 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:23,283 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [16] imperfect sequences [] total 16 [2019-12-07 17:27:23,283 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [515957120] [2019-12-07 17:27:23,283 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 17:27:23,283 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:23,283 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 17:27:23,283 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=230, Unknown=0, NotChecked=0, Total=272 [2019-12-07 17:27:23,283 INFO L87 Difference]: Start difference. First operand 17099 states and 52395 transitions. Second operand 17 states. [2019-12-07 17:27:28,552 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:28,553 INFO L93 Difference]: Finished difference Result 50731 states and 151655 transitions. [2019-12-07 17:27:28,553 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 70 states. [2019-12-07 17:27:28,553 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 66 [2019-12-07 17:27:28,553 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:28,608 INFO L225 Difference]: With dead ends: 50731 [2019-12-07 17:27:28,608 INFO L226 Difference]: Without dead ends: 47884 [2019-12-07 17:27:28,609 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 92 GetRequests, 20 SyntacticMatches, 1 SemanticMatches, 71 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1743 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=874, Invalid=4382, Unknown=0, NotChecked=0, Total=5256 [2019-12-07 17:27:28,737 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47884 states. [2019-12-07 17:27:29,092 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47884 to 17595. [2019-12-07 17:27:29,092 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17595 states. [2019-12-07 17:27:29,117 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17595 states to 17595 states and 53967 transitions. [2019-12-07 17:27:29,117 INFO L78 Accepts]: Start accepts. Automaton has 17595 states and 53967 transitions. Word has length 66 [2019-12-07 17:27:29,117 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:29,117 INFO L462 AbstractCegarLoop]: Abstraction has 17595 states and 53967 transitions. [2019-12-07 17:27:29,117 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 17:27:29,117 INFO L276 IsEmpty]: Start isEmpty. Operand 17595 states and 53967 transitions. [2019-12-07 17:27:29,131 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:27:29,131 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:29,131 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:29,131 INFO L410 AbstractCegarLoop]: === Iteration 35 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:29,131 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:29,131 INFO L82 PathProgramCache]: Analyzing trace with hash -956789547, now seen corresponding path program 9 times [2019-12-07 17:27:29,131 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:29,132 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [248064452] [2019-12-07 17:27:29,132 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:29,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:29,159 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:29,159 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [248064452] [2019-12-07 17:27:29,159 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:29,159 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:27:29,159 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2006255953] [2019-12-07 17:27:29,159 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:27:29,160 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:29,160 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:27:29,160 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:27:29,160 INFO L87 Difference]: Start difference. First operand 17595 states and 53967 transitions. Second operand 3 states. [2019-12-07 17:27:29,192 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:29,192 INFO L93 Difference]: Finished difference Result 12326 states and 37013 transitions. [2019-12-07 17:27:29,193 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:27:29,193 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 66 [2019-12-07 17:27:29,193 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:29,205 INFO L225 Difference]: With dead ends: 12326 [2019-12-07 17:27:29,205 INFO L226 Difference]: Without dead ends: 12326 [2019-12-07 17:27:29,206 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:27:29,254 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12326 states. [2019-12-07 17:27:29,351 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12326 to 12039. [2019-12-07 17:27:29,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12039 states. [2019-12-07 17:27:29,368 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12039 states to 12039 states and 36180 transitions. [2019-12-07 17:27:29,368 INFO L78 Accepts]: Start accepts. Automaton has 12039 states and 36180 transitions. Word has length 66 [2019-12-07 17:27:29,369 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:29,369 INFO L462 AbstractCegarLoop]: Abstraction has 12039 states and 36180 transitions. [2019-12-07 17:27:29,369 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:27:29,369 INFO L276 IsEmpty]: Start isEmpty. Operand 12039 states and 36180 transitions. [2019-12-07 17:27:29,378 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:27:29,378 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:29,378 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:29,379 INFO L410 AbstractCegarLoop]: === Iteration 36 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:29,379 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:29,379 INFO L82 PathProgramCache]: Analyzing trace with hash 2078724657, now seen corresponding path program 1 times [2019-12-07 17:27:29,379 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:29,379 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1599589439] [2019-12-07 17:27:29,379 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:29,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:29,640 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:29,640 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1599589439] [2019-12-07 17:27:29,640 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:29,640 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 17:27:29,640 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [794269154] [2019-12-07 17:27:29,640 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 17:27:29,640 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:29,641 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 17:27:29,641 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=146, Unknown=0, NotChecked=0, Total=182 [2019-12-07 17:27:29,641 INFO L87 Difference]: Start difference. First operand 12039 states and 36180 transitions. Second operand 14 states. [2019-12-07 17:27:30,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:30,789 INFO L93 Difference]: Finished difference Result 18329 states and 53999 transitions. [2019-12-07 17:27:30,789 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2019-12-07 17:27:30,789 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 67 [2019-12-07 17:27:30,789 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:30,804 INFO L225 Difference]: With dead ends: 18329 [2019-12-07 17:27:30,804 INFO L226 Difference]: Without dead ends: 15264 [2019-12-07 17:27:30,804 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 192 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=161, Invalid=769, Unknown=0, NotChecked=0, Total=930 [2019-12-07 17:27:30,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15264 states. [2019-12-07 17:27:30,967 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15264 to 12413. [2019-12-07 17:27:30,967 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12413 states. [2019-12-07 17:27:30,986 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12413 states to 12413 states and 37133 transitions. [2019-12-07 17:27:30,986 INFO L78 Accepts]: Start accepts. Automaton has 12413 states and 37133 transitions. Word has length 67 [2019-12-07 17:27:30,986 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:30,986 INFO L462 AbstractCegarLoop]: Abstraction has 12413 states and 37133 transitions. [2019-12-07 17:27:30,986 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 17:27:30,986 INFO L276 IsEmpty]: Start isEmpty. Operand 12413 states and 37133 transitions. [2019-12-07 17:27:30,997 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:27:30,997 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:30,997 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:30,997 INFO L410 AbstractCegarLoop]: === Iteration 37 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:30,997 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:30,997 INFO L82 PathProgramCache]: Analyzing trace with hash 888958687, now seen corresponding path program 2 times [2019-12-07 17:27:30,997 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:30,997 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1607018597] [2019-12-07 17:27:30,998 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:31,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:31,230 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:31,230 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1607018597] [2019-12-07 17:27:31,230 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:31,230 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 17:27:31,230 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [382752695] [2019-12-07 17:27:31,230 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 17:27:31,230 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:31,230 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 17:27:31,231 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=147, Unknown=0, NotChecked=0, Total=182 [2019-12-07 17:27:31,231 INFO L87 Difference]: Start difference. First operand 12413 states and 37133 transitions. Second operand 14 states. [2019-12-07 17:27:33,467 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:33,467 INFO L93 Difference]: Finished difference Result 23363 states and 68529 transitions. [2019-12-07 17:27:33,467 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2019-12-07 17:27:33,467 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 67 [2019-12-07 17:27:33,468 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:33,484 INFO L225 Difference]: With dead ends: 23363 [2019-12-07 17:27:33,484 INFO L226 Difference]: Without dead ends: 17274 [2019-12-07 17:27:33,484 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 477 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=291, Invalid=1515, Unknown=0, NotChecked=0, Total=1806 [2019-12-07 17:27:33,541 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17274 states. [2019-12-07 17:27:33,658 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17274 to 12554. [2019-12-07 17:27:33,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12554 states. [2019-12-07 17:27:33,678 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12554 states to 12554 states and 37386 transitions. [2019-12-07 17:27:33,678 INFO L78 Accepts]: Start accepts. Automaton has 12554 states and 37386 transitions. Word has length 67 [2019-12-07 17:27:33,678 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:33,678 INFO L462 AbstractCegarLoop]: Abstraction has 12554 states and 37386 transitions. [2019-12-07 17:27:33,678 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 17:27:33,678 INFO L276 IsEmpty]: Start isEmpty. Operand 12554 states and 37386 transitions. [2019-12-07 17:27:33,689 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:27:33,689 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:33,689 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:33,689 INFO L410 AbstractCegarLoop]: === Iteration 38 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:33,689 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:33,690 INFO L82 PathProgramCache]: Analyzing trace with hash 721495091, now seen corresponding path program 3 times [2019-12-07 17:27:33,690 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:33,690 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [808846793] [2019-12-07 17:27:33,690 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:33,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:34,062 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:34,062 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [808846793] [2019-12-07 17:27:34,062 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:34,063 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2019-12-07 17:27:34,063 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1263440866] [2019-12-07 17:27:34,063 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 17:27:34,063 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:34,063 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 17:27:34,063 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=196, Unknown=0, NotChecked=0, Total=240 [2019-12-07 17:27:34,063 INFO L87 Difference]: Start difference. First operand 12554 states and 37386 transitions. Second operand 16 states. [2019-12-07 17:27:37,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:37,692 INFO L93 Difference]: Finished difference Result 17540 states and 51340 transitions. [2019-12-07 17:27:37,693 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2019-12-07 17:27:37,693 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 67 [2019-12-07 17:27:37,693 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:37,718 INFO L225 Difference]: With dead ends: 17540 [2019-12-07 17:27:37,718 INFO L226 Difference]: Without dead ends: 15121 [2019-12-07 17:27:37,719 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 215 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=212, Invalid=1120, Unknown=0, NotChecked=0, Total=1332 [2019-12-07 17:27:37,774 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15121 states. [2019-12-07 17:27:37,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15121 to 12840. [2019-12-07 17:27:37,888 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12840 states. [2019-12-07 17:27:37,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12840 states to 12840 states and 38067 transitions. [2019-12-07 17:27:37,908 INFO L78 Accepts]: Start accepts. Automaton has 12840 states and 38067 transitions. Word has length 67 [2019-12-07 17:27:37,908 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:37,908 INFO L462 AbstractCegarLoop]: Abstraction has 12840 states and 38067 transitions. [2019-12-07 17:27:37,908 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 17:27:37,908 INFO L276 IsEmpty]: Start isEmpty. Operand 12840 states and 38067 transitions. [2019-12-07 17:27:37,919 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:27:37,920 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:37,920 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:37,920 INFO L410 AbstractCegarLoop]: === Iteration 39 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:37,920 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:37,920 INFO L82 PathProgramCache]: Analyzing trace with hash -468270879, now seen corresponding path program 4 times [2019-12-07 17:27:37,920 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:37,920 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1444845549] [2019-12-07 17:27:37,920 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:37,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:38,294 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:38,294 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1444845549] [2019-12-07 17:27:38,294 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:38,294 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2019-12-07 17:27:38,294 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [536797154] [2019-12-07 17:27:38,294 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 17:27:38,294 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:38,295 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 17:27:38,295 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=47, Invalid=225, Unknown=0, NotChecked=0, Total=272 [2019-12-07 17:27:38,295 INFO L87 Difference]: Start difference. First operand 12840 states and 38067 transitions. Second operand 17 states. [2019-12-07 17:27:40,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:40,806 INFO L93 Difference]: Finished difference Result 19448 states and 57075 transitions. [2019-12-07 17:27:40,807 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2019-12-07 17:27:40,807 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 67 [2019-12-07 17:27:40,807 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:40,823 INFO L225 Difference]: With dead ends: 19448 [2019-12-07 17:27:40,823 INFO L226 Difference]: Without dead ends: 16765 [2019-12-07 17:27:40,823 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 266 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=245, Invalid=1315, Unknown=0, NotChecked=0, Total=1560 [2019-12-07 17:27:40,879 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16765 states. [2019-12-07 17:27:41,000 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16765 to 13086. [2019-12-07 17:27:41,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13086 states. [2019-12-07 17:27:41,020 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13086 states to 13086 states and 38782 transitions. [2019-12-07 17:27:41,021 INFO L78 Accepts]: Start accepts. Automaton has 13086 states and 38782 transitions. Word has length 67 [2019-12-07 17:27:41,021 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:41,021 INFO L462 AbstractCegarLoop]: Abstraction has 13086 states and 38782 transitions. [2019-12-07 17:27:41,021 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 17:27:41,021 INFO L276 IsEmpty]: Start isEmpty. Operand 13086 states and 38782 transitions. [2019-12-07 17:27:41,032 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:27:41,032 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:41,032 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:41,032 INFO L410 AbstractCegarLoop]: === Iteration 40 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:41,032 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:41,032 INFO L82 PathProgramCache]: Analyzing trace with hash -1716057561, now seen corresponding path program 5 times [2019-12-07 17:27:41,032 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:41,033 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [404824452] [2019-12-07 17:27:41,033 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:41,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:41,188 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:41,188 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [404824452] [2019-12-07 17:27:41,188 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:41,188 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 17:27:41,188 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1548330499] [2019-12-07 17:27:41,188 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 17:27:41,188 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:41,188 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 17:27:41,189 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2019-12-07 17:27:41,189 INFO L87 Difference]: Start difference. First operand 13086 states and 38782 transitions. Second operand 11 states. [2019-12-07 17:27:41,805 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:41,805 INFO L93 Difference]: Finished difference Result 18997 states and 56120 transitions. [2019-12-07 17:27:41,806 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 17:27:41,806 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 67 [2019-12-07 17:27:41,806 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:41,832 INFO L225 Difference]: With dead ends: 18997 [2019-12-07 17:27:41,832 INFO L226 Difference]: Without dead ends: 17978 [2019-12-07 17:27:41,833 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 63 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=95, Invalid=411, Unknown=0, NotChecked=0, Total=506 [2019-12-07 17:27:41,892 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17978 states. [2019-12-07 17:27:42,035 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17978 to 15575. [2019-12-07 17:27:42,035 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15575 states. [2019-12-07 17:27:42,058 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15575 states to 15575 states and 46254 transitions. [2019-12-07 17:27:42,059 INFO L78 Accepts]: Start accepts. Automaton has 15575 states and 46254 transitions. Word has length 67 [2019-12-07 17:27:42,059 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:42,059 INFO L462 AbstractCegarLoop]: Abstraction has 15575 states and 46254 transitions. [2019-12-07 17:27:42,059 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 17:27:42,059 INFO L276 IsEmpty]: Start isEmpty. Operand 15575 states and 46254 transitions. [2019-12-07 17:27:42,072 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:27:42,072 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:42,072 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:42,072 INFO L410 AbstractCegarLoop]: === Iteration 41 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:42,072 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:42,072 INFO L82 PathProgramCache]: Analyzing trace with hash 1403489409, now seen corresponding path program 6 times [2019-12-07 17:27:42,072 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:42,073 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [778519704] [2019-12-07 17:27:42,073 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:42,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:42,178 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:42,178 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [778519704] [2019-12-07 17:27:42,178 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:42,178 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 17:27:42,179 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [986370875] [2019-12-07 17:27:42,179 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 17:27:42,179 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:42,179 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 17:27:42,179 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2019-12-07 17:27:42,179 INFO L87 Difference]: Start difference. First operand 15575 states and 46254 transitions. Second operand 10 states. [2019-12-07 17:27:42,740 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:42,740 INFO L93 Difference]: Finished difference Result 23618 states and 69313 transitions. [2019-12-07 17:27:42,740 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2019-12-07 17:27:42,740 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 67 [2019-12-07 17:27:42,741 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:42,758 INFO L225 Difference]: With dead ends: 23618 [2019-12-07 17:27:42,758 INFO L226 Difference]: Without dead ends: 16051 [2019-12-07 17:27:42,758 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 152 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=148, Invalid=608, Unknown=0, NotChecked=0, Total=756 [2019-12-07 17:27:42,814 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16051 states. [2019-12-07 17:27:42,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16051 to 12641. [2019-12-07 17:27:42,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12641 states. [2019-12-07 17:27:42,949 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12641 states to 12641 states and 37541 transitions. [2019-12-07 17:27:42,949 INFO L78 Accepts]: Start accepts. Automaton has 12641 states and 37541 transitions. Word has length 67 [2019-12-07 17:27:42,949 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:42,949 INFO L462 AbstractCegarLoop]: Abstraction has 12641 states and 37541 transitions. [2019-12-07 17:27:42,949 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 17:27:42,949 INFO L276 IsEmpty]: Start isEmpty. Operand 12641 states and 37541 transitions. [2019-12-07 17:27:42,960 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:27:42,960 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:42,960 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:42,960 INFO L410 AbstractCegarLoop]: === Iteration 42 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:42,960 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:42,960 INFO L82 PathProgramCache]: Analyzing trace with hash 88464887, now seen corresponding path program 7 times [2019-12-07 17:27:42,960 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:42,960 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1162910184] [2019-12-07 17:27:42,961 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:42,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:43,095 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:43,095 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1162910184] [2019-12-07 17:27:43,095 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:43,096 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 17:27:43,096 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1066050880] [2019-12-07 17:27:43,096 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 17:27:43,096 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:43,096 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 17:27:43,096 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2019-12-07 17:27:43,096 INFO L87 Difference]: Start difference. First operand 12641 states and 37541 transitions. Second operand 11 states. [2019-12-07 17:27:43,562 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:43,562 INFO L93 Difference]: Finished difference Result 20093 states and 59549 transitions. [2019-12-07 17:27:43,562 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-12-07 17:27:43,563 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 67 [2019-12-07 17:27:43,563 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:43,580 INFO L225 Difference]: With dead ends: 20093 [2019-12-07 17:27:43,581 INFO L226 Difference]: Without dead ends: 19074 [2019-12-07 17:27:43,581 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 140 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=139, Invalid=617, Unknown=0, NotChecked=0, Total=756 [2019-12-07 17:27:43,642 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19074 states. [2019-12-07 17:27:43,805 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19074 to 17020. [2019-12-07 17:27:43,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17020 states. [2019-12-07 17:27:43,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17020 states to 17020 states and 50707 transitions. [2019-12-07 17:27:43,830 INFO L78 Accepts]: Start accepts. Automaton has 17020 states and 50707 transitions. Word has length 67 [2019-12-07 17:27:43,830 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:43,830 INFO L462 AbstractCegarLoop]: Abstraction has 17020 states and 50707 transitions. [2019-12-07 17:27:43,830 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 17:27:43,830 INFO L276 IsEmpty]: Start isEmpty. Operand 17020 states and 50707 transitions. [2019-12-07 17:27:43,843 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:27:43,843 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:43,843 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:43,844 INFO L410 AbstractCegarLoop]: === Iteration 43 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:43,844 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:43,844 INFO L82 PathProgramCache]: Analyzing trace with hash 324937045, now seen corresponding path program 8 times [2019-12-07 17:27:43,844 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:43,844 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1004750715] [2019-12-07 17:27:43,844 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:43,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:43,955 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:43,955 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1004750715] [2019-12-07 17:27:43,955 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:43,955 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 17:27:43,955 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1204457747] [2019-12-07 17:27:43,955 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 17:27:43,955 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:43,956 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 17:27:43,956 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2019-12-07 17:27:43,956 INFO L87 Difference]: Start difference. First operand 17020 states and 50707 transitions. Second operand 11 states. [2019-12-07 17:27:44,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:44,399 INFO L93 Difference]: Finished difference Result 19906 states and 58258 transitions. [2019-12-07 17:27:44,400 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2019-12-07 17:27:44,400 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 67 [2019-12-07 17:27:44,400 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:44,414 INFO L225 Difference]: With dead ends: 19906 [2019-12-07 17:27:44,415 INFO L226 Difference]: Without dead ends: 15102 [2019-12-07 17:27:44,415 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 127 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=132, Invalid=570, Unknown=0, NotChecked=0, Total=702 [2019-12-07 17:27:44,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15102 states. [2019-12-07 17:27:44,578 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15102 to 12775. [2019-12-07 17:27:44,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12775 states. [2019-12-07 17:27:44,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12775 states to 12775 states and 37736 transitions. [2019-12-07 17:27:44,597 INFO L78 Accepts]: Start accepts. Automaton has 12775 states and 37736 transitions. Word has length 67 [2019-12-07 17:27:44,597 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:44,598 INFO L462 AbstractCegarLoop]: Abstraction has 12775 states and 37736 transitions. [2019-12-07 17:27:44,598 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 17:27:44,598 INFO L276 IsEmpty]: Start isEmpty. Operand 12775 states and 37736 transitions. [2019-12-07 17:27:44,608 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:27:44,609 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:44,609 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:44,609 INFO L410 AbstractCegarLoop]: === Iteration 44 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:44,609 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:44,609 INFO L82 PathProgramCache]: Analyzing trace with hash 975038819, now seen corresponding path program 9 times [2019-12-07 17:27:44,609 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:44,609 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [221027920] [2019-12-07 17:27:44,609 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:44,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:44,891 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:44,891 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [221027920] [2019-12-07 17:27:44,891 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:44,892 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 17:27:44,892 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [646027350] [2019-12-07 17:27:44,892 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 17:27:44,892 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:44,892 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 17:27:44,892 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=172, Unknown=0, NotChecked=0, Total=210 [2019-12-07 17:27:44,892 INFO L87 Difference]: Start difference. First operand 12775 states and 37736 transitions. Second operand 15 states. [2019-12-07 17:27:46,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:46,148 INFO L93 Difference]: Finished difference Result 15318 states and 44524 transitions. [2019-12-07 17:27:46,148 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2019-12-07 17:27:46,148 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 67 [2019-12-07 17:27:46,148 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:46,163 INFO L225 Difference]: With dead ends: 15318 [2019-12-07 17:27:46,163 INFO L226 Difference]: Without dead ends: 14837 [2019-12-07 17:27:46,164 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 0 SyntacticMatches, 3 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 329 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=235, Invalid=1171, Unknown=0, NotChecked=0, Total=1406 [2019-12-07 17:27:46,216 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14837 states. [2019-12-07 17:27:46,326 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14837 to 12783. [2019-12-07 17:27:46,326 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12783 states. [2019-12-07 17:27:46,345 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12783 states to 12783 states and 37750 transitions. [2019-12-07 17:27:46,345 INFO L78 Accepts]: Start accepts. Automaton has 12783 states and 37750 transitions. Word has length 67 [2019-12-07 17:27:46,345 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:46,345 INFO L462 AbstractCegarLoop]: Abstraction has 12783 states and 37750 transitions. [2019-12-07 17:27:46,345 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 17:27:46,345 INFO L276 IsEmpty]: Start isEmpty. Operand 12783 states and 37750 transitions. [2019-12-07 17:27:46,356 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:27:46,356 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:46,356 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:46,356 INFO L410 AbstractCegarLoop]: === Iteration 45 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:46,356 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:46,356 INFO L82 PathProgramCache]: Analyzing trace with hash -478785703, now seen corresponding path program 10 times [2019-12-07 17:27:46,357 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:46,357 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [724580290] [2019-12-07 17:27:46,357 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:46,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:46,623 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:46,624 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [724580290] [2019-12-07 17:27:46,624 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:46,624 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2019-12-07 17:27:46,624 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [878347499] [2019-12-07 17:27:46,624 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 17:27:46,624 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:46,624 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 17:27:46,625 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=198, Unknown=0, NotChecked=0, Total=240 [2019-12-07 17:27:46,625 INFO L87 Difference]: Start difference. First operand 12783 states and 37750 transitions. Second operand 16 states. [2019-12-07 17:27:49,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:49,346 INFO L93 Difference]: Finished difference Result 15202 states and 44228 transitions. [2019-12-07 17:27:49,347 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2019-12-07 17:27:49,347 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 67 [2019-12-07 17:27:49,348 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:49,371 INFO L225 Difference]: With dead ends: 15202 [2019-12-07 17:27:49,371 INFO L226 Difference]: Without dead ends: 14859 [2019-12-07 17:27:49,372 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 286 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=203, Invalid=1057, Unknown=0, NotChecked=0, Total=1260 [2019-12-07 17:27:49,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14859 states. [2019-12-07 17:27:49,539 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14859 to 12775. [2019-12-07 17:27:49,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12775 states. [2019-12-07 17:27:49,559 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12775 states to 12775 states and 37728 transitions. [2019-12-07 17:27:49,559 INFO L78 Accepts]: Start accepts. Automaton has 12775 states and 37728 transitions. Word has length 67 [2019-12-07 17:27:49,559 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:49,559 INFO L462 AbstractCegarLoop]: Abstraction has 12775 states and 37728 transitions. [2019-12-07 17:27:49,559 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 17:27:49,559 INFO L276 IsEmpty]: Start isEmpty. Operand 12775 states and 37728 transitions. [2019-12-07 17:27:49,570 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:27:49,570 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:49,570 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:49,570 INFO L410 AbstractCegarLoop]: === Iteration 46 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:49,570 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:49,571 INFO L82 PathProgramCache]: Analyzing trace with hash -1516551711, now seen corresponding path program 11 times [2019-12-07 17:27:49,571 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:49,571 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1641730745] [2019-12-07 17:27:49,571 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:49,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:49,933 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:49,933 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1641730745] [2019-12-07 17:27:49,933 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:49,933 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2019-12-07 17:27:49,933 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [567510794] [2019-12-07 17:27:49,933 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 17:27:49,934 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:49,934 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 17:27:49,934 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=226, Unknown=0, NotChecked=0, Total=272 [2019-12-07 17:27:49,934 INFO L87 Difference]: Start difference. First operand 12775 states and 37728 transitions. Second operand 17 states. [2019-12-07 17:27:51,529 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:51,529 INFO L93 Difference]: Finished difference Result 16046 states and 46493 transitions. [2019-12-07 17:27:51,530 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2019-12-07 17:27:51,530 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 67 [2019-12-07 17:27:51,530 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:51,545 INFO L225 Difference]: With dead ends: 16046 [2019-12-07 17:27:51,545 INFO L226 Difference]: Without dead ends: 15603 [2019-12-07 17:27:51,546 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 0 SyntacticMatches, 3 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 482 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=329, Invalid=1563, Unknown=0, NotChecked=0, Total=1892 [2019-12-07 17:27:51,599 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15603 states. [2019-12-07 17:27:51,713 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15603 to 12697. [2019-12-07 17:27:51,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12697 states. [2019-12-07 17:27:51,732 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12697 states to 12697 states and 37532 transitions. [2019-12-07 17:27:51,732 INFO L78 Accepts]: Start accepts. Automaton has 12697 states and 37532 transitions. Word has length 67 [2019-12-07 17:27:51,732 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:51,732 INFO L462 AbstractCegarLoop]: Abstraction has 12697 states and 37532 transitions. [2019-12-07 17:27:51,732 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 17:27:51,732 INFO L276 IsEmpty]: Start isEmpty. Operand 12697 states and 37532 transitions. [2019-12-07 17:27:51,743 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:27:51,743 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:51,743 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:51,743 INFO L410 AbstractCegarLoop]: === Iteration 47 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:51,743 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:51,743 INFO L82 PathProgramCache]: Analyzing trace with hash -962576569, now seen corresponding path program 12 times [2019-12-07 17:27:51,743 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:51,743 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [257352320] [2019-12-07 17:27:51,744 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:51,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:51,860 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:51,860 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [257352320] [2019-12-07 17:27:51,860 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:51,860 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 17:27:51,860 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [956542003] [2019-12-07 17:27:51,860 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 17:27:51,860 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:51,861 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 17:27:51,861 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2019-12-07 17:27:51,861 INFO L87 Difference]: Start difference. First operand 12697 states and 37532 transitions. Second operand 10 states. [2019-12-07 17:27:52,795 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:52,795 INFO L93 Difference]: Finished difference Result 15915 states and 45923 transitions. [2019-12-07 17:27:52,796 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 17:27:52,796 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 67 [2019-12-07 17:27:52,796 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:52,813 INFO L225 Difference]: With dead ends: 15915 [2019-12-07 17:27:52,813 INFO L226 Difference]: Without dead ends: 14782 [2019-12-07 17:27:52,814 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 53 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=75, Invalid=345, Unknown=0, NotChecked=0, Total=420 [2019-12-07 17:27:52,869 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14782 states. [2019-12-07 17:27:52,974 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14782 to 12277. [2019-12-07 17:27:52,975 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12277 states. [2019-12-07 17:27:52,992 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12277 states to 12277 states and 36367 transitions. [2019-12-07 17:27:52,992 INFO L78 Accepts]: Start accepts. Automaton has 12277 states and 36367 transitions. Word has length 67 [2019-12-07 17:27:52,992 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:52,993 INFO L462 AbstractCegarLoop]: Abstraction has 12277 states and 36367 transitions. [2019-12-07 17:27:52,993 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 17:27:52,993 INFO L276 IsEmpty]: Start isEmpty. Operand 12277 states and 36367 transitions. [2019-12-07 17:27:53,002 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:27:53,002 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:53,002 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:53,002 INFO L410 AbstractCegarLoop]: === Iteration 48 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:53,003 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:53,003 INFO L82 PathProgramCache]: Analyzing trace with hash 764043865, now seen corresponding path program 13 times [2019-12-07 17:27:53,003 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:53,003 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [700083230] [2019-12-07 17:27:53,003 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:53,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:27:53,122 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:27:53,123 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [700083230] [2019-12-07 17:27:53,123 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:27:53,123 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 17:27:53,123 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2050516364] [2019-12-07 17:27:53,123 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 17:27:53,123 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:27:53,123 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 17:27:53,123 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2019-12-07 17:27:53,123 INFO L87 Difference]: Start difference. First operand 12277 states and 36367 transitions. Second operand 11 states. [2019-12-07 17:27:53,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:27:53,888 INFO L93 Difference]: Finished difference Result 15289 states and 44537 transitions. [2019-12-07 17:27:53,888 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 17:27:53,888 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 67 [2019-12-07 17:27:53,888 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:27:53,902 INFO L225 Difference]: With dead ends: 15289 [2019-12-07 17:27:53,902 INFO L226 Difference]: Without dead ends: 14918 [2019-12-07 17:27:53,903 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 67 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=87, Invalid=419, Unknown=0, NotChecked=0, Total=506 [2019-12-07 17:27:53,956 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14918 states. [2019-12-07 17:27:54,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14918 to 12093. [2019-12-07 17:27:54,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12093 states. [2019-12-07 17:27:54,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12093 states to 12093 states and 35901 transitions. [2019-12-07 17:27:54,080 INFO L78 Accepts]: Start accepts. Automaton has 12093 states and 35901 transitions. Word has length 67 [2019-12-07 17:27:54,081 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:27:54,081 INFO L462 AbstractCegarLoop]: Abstraction has 12093 states and 35901 transitions. [2019-12-07 17:27:54,081 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 17:27:54,081 INFO L276 IsEmpty]: Start isEmpty. Operand 12093 states and 35901 transitions. [2019-12-07 17:27:54,090 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:27:54,090 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:27:54,090 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:27:54,090 INFO L410 AbstractCegarLoop]: === Iteration 49 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:27:54,090 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:27:54,091 INFO L82 PathProgramCache]: Analyzing trace with hash -494782975, now seen corresponding path program 14 times [2019-12-07 17:27:54,091 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:27:54,091 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [712749778] [2019-12-07 17:27:54,091 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:27:54,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:27:54,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:27:54,152 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 17:27:54,152 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 17:27:54,155 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [904] [904] ULTIMATE.startENTRY-->L837: Formula: (let ((.cse0 (store |v_#valid_64| 0 0))) (and (= 0 v_~weak$$choice0~0_10) (= v_~a$r_buff1_thd0~0_132 0) (= 0 v_~a$w_buff0_used~0_689) (= |v_ULTIMATE.start_main_~#t397~0.offset_22| 0) (= 0 v_~a$w_buff1_used~0_376) (= v_~a$r_buff0_thd3~0_328 0) (= |v_#NULL.offset_6| 0) (= v_~y~0_79 0) (= 0 v_~a$r_buff1_thd1~0_125) (= 0 v_~__unbuffered_p0_EAX~0_92) (= 0 v_~__unbuffered_p1_EAX~0_37) (= v_~x~0_69 0) (= 0 v_~a$r_buff1_thd2~0_129) (< 0 |v_#StackHeapBarrier_17|) (= v_~__unbuffered_p0_EBX~0_92 0) (= v_~a$flush_delayed~0_23 0) (= v_~a$r_buff1_thd3~0_224 0) (= v_~__unbuffered_p2_EBX~0_38 0) (= 0 v_~__unbuffered_cnt~0_98) (= v_~main$tmp_guard0~0_28 0) (= 0 v_~a$r_buff0_thd2~0_124) (= v_~a~0_181 0) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t397~0.base_29|) (= 0 |v_#NULL.base_6|) (= (select .cse0 |v_ULTIMATE.start_main_~#t397~0.base_29|) 0) (= 0 v_~__unbuffered_p2_EAX~0_33) (= |v_#valid_62| (store .cse0 |v_ULTIMATE.start_main_~#t397~0.base_29| 1)) (= 0 v_~a$r_buff0_thd1~0_195) (= v_~a$mem_tmp~0_12 0) (= v_~main$tmp_guard1~0_36 0) (= 0 v_~a$w_buff1~0_172) (= v_~a$r_buff0_thd0~0_144 0) (= v_~a$w_buff0~0_228 0) (= (store |v_#memory_int_22| |v_ULTIMATE.start_main_~#t397~0.base_29| (store (select |v_#memory_int_22| |v_ULTIMATE.start_main_~#t397~0.base_29|) |v_ULTIMATE.start_main_~#t397~0.offset_22| 0)) |v_#memory_int_21|) (= v_~weak$$choice2~0_107 0) (= v_~z~0_20 0) (= |v_#length_23| (store |v_#length_24| |v_ULTIMATE.start_main_~#t397~0.base_29| 4)) (= 0 v_~a$read_delayed~0_6) (= v_~a$read_delayed_var~0.offset_6 0) (= 0 v_~a$read_delayed_var~0.base_6))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_64|, #memory_int=|v_#memory_int_22|, #length=|v_#length_24|} OutVars{~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_129, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_51|, #NULL.offset=|v_#NULL.offset_6|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_281|, ~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_144, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_31|, ~a~0=v_~a~0_181, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_67|, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_92, ULTIMATE.start_main_~#t398~0.base=|v_ULTIMATE.start_main_~#t398~0.base_29|, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_37, #length=|v_#length_23|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_33, ULTIMATE.start_main_~#t397~0.offset=|v_ULTIMATE.start_main_~#t397~0.offset_22|, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_38, ~__unbuffered_p0_EBX~0=v_~__unbuffered_p0_EBX~0_92, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_10|, ~a$r_buff1_thd3~0=v_~a$r_buff1_thd3~0_224, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_689, ~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_195, ~weak$$choice0~0=v_~weak$$choice0~0_10, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ~a$read_delayed_var~0.offset=v_~a$read_delayed_var~0.offset_6, ~a$w_buff0~0=v_~a$w_buff0~0_228, ~a$r_buff1_thd0~0=v_~a$r_buff1_thd0~0_132, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_98, ~x~0=v_~x~0_69, ~a$read_delayed~0=v_~a$read_delayed~0_6, ~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_124, ULTIMATE.start_main_~#t397~0.base=|v_ULTIMATE.start_main_~#t397~0.base_29|, ULTIMATE.start_main_~#t398~0.offset=|v_ULTIMATE.start_main_~#t398~0.offset_22|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_36, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_55|, ~a$mem_tmp~0=v_~a$mem_tmp~0_12, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_45|, ~a$w_buff1~0=v_~a$w_buff1~0_172, ~y~0=v_~y~0_79, ULTIMATE.start_main_~#t399~0.base=|v_ULTIMATE.start_main_~#t399~0.base_17|, ULTIMATE.start_main_#t~nondet46=|v_ULTIMATE.start_main_#t~nondet46_27|, ULTIMATE.start_main_~#t399~0.offset=|v_ULTIMATE.start_main_~#t399~0.offset_15|, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_9|, ~a$r_buff1_thd1~0=v_~a$r_buff1_thd1~0_125, ~a$r_buff0_thd3~0=v_~a$r_buff0_thd3~0_328, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_28, #NULL.base=|v_#NULL.base_6|, ~a$flush_delayed~0=v_~a$flush_delayed~0_23, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, #valid=|v_#valid_62|, #memory_int=|v_#memory_int_21|, ~z~0=v_~z~0_20, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_376, ~weak$$choice2~0=v_~weak$$choice2~0_107, ~a$read_delayed_var~0.base=v_~a$read_delayed_var~0.base_6} AuxVars[] AssignedVars[~a$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite49, ~a$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite50, ~a~0, ULTIMATE.start_main_#t~ite52, ~__unbuffered_p0_EAX~0, ULTIMATE.start_main_~#t398~0.base, ~__unbuffered_p1_EAX~0, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_~#t397~0.offset, ~__unbuffered_p2_EBX~0, ~__unbuffered_p0_EBX~0, ULTIMATE.start_main_#t~nondet45, ~a$r_buff1_thd3~0, ~a$w_buff0_used~0, ~a$r_buff0_thd1~0, ~weak$$choice0~0, ~a$read_delayed_var~0.offset, ~a$w_buff0~0, ~a$r_buff1_thd0~0, ~__unbuffered_cnt~0, ~x~0, ~a$read_delayed~0, ~a$r_buff0_thd2~0, ULTIMATE.start_main_~#t397~0.base, ULTIMATE.start_main_~#t398~0.offset, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite48, ~a$mem_tmp~0, ULTIMATE.start_main_#t~ite51, ~a$w_buff1~0, ~y~0, ULTIMATE.start_main_~#t399~0.base, ULTIMATE.start_main_#t~nondet46, ULTIMATE.start_main_~#t399~0.offset, ULTIMATE.start_main_#t~nondet44, ~a$r_buff1_thd1~0, ~a$r_buff0_thd3~0, ~main$tmp_guard0~0, #NULL.base, ~a$flush_delayed~0, ULTIMATE.start_main_#res, #valid, #memory_int, ~z~0, ~a$w_buff1_used~0, ~weak$$choice2~0, ~a$read_delayed_var~0.base] because there is no mapped edge [2019-12-07 17:27:54,155 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [865] [865] L837-1-->L839: Formula: (and (= (store |v_#valid_35| |v_ULTIMATE.start_main_~#t398~0.base_12| 1) |v_#valid_34|) (not (= |v_ULTIMATE.start_main_~#t398~0.base_12| 0)) (= |v_ULTIMATE.start_main_~#t398~0.offset_10| 0) (< |v_#StackHeapBarrier_9| |v_ULTIMATE.start_main_~#t398~0.base_12|) (= |v_#length_13| (store |v_#length_14| |v_ULTIMATE.start_main_~#t398~0.base_12| 4)) (= 0 (select |v_#valid_35| |v_ULTIMATE.start_main_~#t398~0.base_12|)) (= (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t398~0.base_12| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t398~0.base_12|) |v_ULTIMATE.start_main_~#t398~0.offset_10| 1)) |v_#memory_int_11|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_12|, #length=|v_#length_14|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_9|, ULTIMATE.start_main_~#t398~0.base=|v_ULTIMATE.start_main_~#t398~0.base_12|, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_4|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_11|, ULTIMATE.start_main_~#t398~0.offset=|v_ULTIMATE.start_main_~#t398~0.offset_10|, #length=|v_#length_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t398~0.base, ULTIMATE.start_main_#t~nondet44, #valid, #memory_int, ULTIMATE.start_main_~#t398~0.offset, #length] because there is no mapped edge [2019-12-07 17:27:54,156 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [876] [876] L839-1-->L841: Formula: (and (= 0 (select |v_#valid_37| |v_ULTIMATE.start_main_~#t399~0.base_13|)) (not (= 0 |v_ULTIMATE.start_main_~#t399~0.base_13|)) (= |v_ULTIMATE.start_main_~#t399~0.offset_11| 0) (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t399~0.base_13|) (= |v_#memory_int_13| (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t399~0.base_13| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t399~0.base_13|) |v_ULTIMATE.start_main_~#t399~0.offset_11| 2))) (= (store |v_#length_16| |v_ULTIMATE.start_main_~#t399~0.base_13| 4) |v_#length_15|) (= |v_#valid_36| (store |v_#valid_37| |v_ULTIMATE.start_main_~#t399~0.base_13| 1))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_37|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{ULTIMATE.start_main_~#t399~0.base=|v_ULTIMATE.start_main_~#t399~0.base_13|, #StackHeapBarrier=|v_#StackHeapBarrier_10|, ULTIMATE.start_main_~#t399~0.offset=|v_ULTIMATE.start_main_~#t399~0.offset_11|, #valid=|v_#valid_36|, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_6|, #memory_int=|v_#memory_int_13|, #length=|v_#length_15|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t399~0.base, ULTIMATE.start_main_~#t399~0.offset, #valid, ULTIMATE.start_main_#t~nondet45, #memory_int, #length] because there is no mapped edge [2019-12-07 17:27:54,156 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [881] [881] L4-->L758: Formula: (and (= ~x~0_Out-1421356120 1) (= ~a$r_buff0_thd0~0_In-1421356120 ~a$r_buff1_thd0~0_Out-1421356120) (= ~a$r_buff1_thd2~0_Out-1421356120 ~a$r_buff0_thd2~0_In-1421356120) (= ~x~0_Out-1421356120 ~__unbuffered_p0_EAX~0_Out-1421356120) (not (= P0Thread1of1ForFork1___VERIFIER_assert_~expression_In-1421356120 0)) (= ~a$r_buff0_thd1~0_Out-1421356120 1) (= ~a$r_buff0_thd3~0_In-1421356120 ~a$r_buff1_thd3~0_Out-1421356120) (= ~a$r_buff1_thd1~0_Out-1421356120 ~a$r_buff0_thd1~0_In-1421356120) (= ~__unbuffered_p0_EBX~0_Out-1421356120 ~y~0_In-1421356120)) InVars {~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In-1421356120, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1421356120, P0Thread1of1ForFork1___VERIFIER_assert_~expression=P0Thread1of1ForFork1___VERIFIER_assert_~expression_In-1421356120, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In-1421356120, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In-1421356120, ~y~0=~y~0_In-1421356120} OutVars{~__unbuffered_p0_EBX~0=~__unbuffered_p0_EBX~0_Out-1421356120, ~a$r_buff1_thd1~0=~a$r_buff1_thd1~0_Out-1421356120, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_Out-1421356120, ~a$r_buff1_thd2~0=~a$r_buff1_thd2~0_Out-1421356120, ~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In-1421356120, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1421356120, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_Out-1421356120, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In-1421356120, ~__unbuffered_p0_EAX~0=~__unbuffered_p0_EAX~0_Out-1421356120, ~a$r_buff1_thd0~0=~a$r_buff1_thd0~0_Out-1421356120, P0Thread1of1ForFork1___VERIFIER_assert_~expression=P0Thread1of1ForFork1___VERIFIER_assert_~expression_In-1421356120, ~y~0=~y~0_In-1421356120, ~x~0=~x~0_Out-1421356120} AuxVars[] AssignedVars[~__unbuffered_p0_EAX~0, ~__unbuffered_p0_EBX~0, ~a$r_buff1_thd1~0, ~a$r_buff1_thd3~0, ~a$r_buff1_thd2~0, ~a$r_buff1_thd0~0, ~a$r_buff0_thd1~0, ~x~0] because there is no mapped edge [2019-12-07 17:27:54,158 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [842] [842] L759-->L759-2: Formula: (let ((.cse0 (= (mod ~a$w_buff0_used~0_In1824585213 256) 0)) (.cse1 (= (mod ~a$r_buff0_thd1~0_In1824585213 256) 0))) (or (and (not .cse0) (not .cse1) (= |P0Thread1of1ForFork1_#t~ite5_Out1824585213| 0)) (and (= ~a$w_buff0_used~0_In1824585213 |P0Thread1of1ForFork1_#t~ite5_Out1824585213|) (or .cse0 .cse1)))) InVars {~a$w_buff0_used~0=~a$w_buff0_used~0_In1824585213, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In1824585213} OutVars{P0Thread1of1ForFork1_#t~ite5=|P0Thread1of1ForFork1_#t~ite5_Out1824585213|, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1824585213, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In1824585213} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite5] because there is no mapped edge [2019-12-07 17:27:54,159 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [840] [840] L760-->L760-2: Formula: (let ((.cse3 (= 0 (mod ~a$w_buff0_used~0_In1050417585 256))) (.cse2 (= (mod ~a$r_buff0_thd1~0_In1050417585 256) 0)) (.cse1 (= 0 (mod ~a$w_buff1_used~0_In1050417585 256))) (.cse0 (= 0 (mod ~a$r_buff1_thd1~0_In1050417585 256)))) (or (and (= |P0Thread1of1ForFork1_#t~ite6_Out1050417585| ~a$w_buff1_used~0_In1050417585) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |P0Thread1of1ForFork1_#t~ite6_Out1050417585| 0) (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0)))))) InVars {~a$r_buff1_thd1~0=~a$r_buff1_thd1~0_In1050417585, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1050417585, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In1050417585, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1050417585} OutVars{P0Thread1of1ForFork1_#t~ite6=|P0Thread1of1ForFork1_#t~ite6_Out1050417585|, ~a$r_buff1_thd1~0=~a$r_buff1_thd1~0_In1050417585, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1050417585, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In1050417585, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1050417585} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite6] because there is no mapped edge [2019-12-07 17:27:54,159 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [829] [829] L778-2-->L778-4: Formula: (let ((.cse1 (= 0 (mod ~a$r_buff1_thd2~0_In-759837036 256))) (.cse0 (= (mod ~a$w_buff1_used~0_In-759837036 256) 0))) (or (and (not .cse0) (not .cse1) (= |P1Thread1of1ForFork2_#t~ite9_Out-759837036| ~a$w_buff1~0_In-759837036)) (and (= |P1Thread1of1ForFork2_#t~ite9_Out-759837036| ~a~0_In-759837036) (or .cse1 .cse0)))) InVars {~a~0=~a~0_In-759837036, ~a$w_buff1~0=~a$w_buff1~0_In-759837036, ~a$r_buff1_thd2~0=~a$r_buff1_thd2~0_In-759837036, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-759837036} OutVars{~a~0=~a~0_In-759837036, P1Thread1of1ForFork2_#t~ite9=|P1Thread1of1ForFork2_#t~ite9_Out-759837036|, ~a$w_buff1~0=~a$w_buff1~0_In-759837036, ~a$r_buff1_thd2~0=~a$r_buff1_thd2~0_In-759837036, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-759837036} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite9] because there is no mapped edge [2019-12-07 17:27:54,159 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L778-4-->L779: Formula: (= |v_P1Thread1of1ForFork2_#t~ite9_10| v_~a~0_28) InVars {P1Thread1of1ForFork2_#t~ite9=|v_P1Thread1of1ForFork2_#t~ite9_10|} OutVars{~a~0=v_~a~0_28, P1Thread1of1ForFork2_#t~ite9=|v_P1Thread1of1ForFork2_#t~ite9_9|, P1Thread1of1ForFork2_#t~ite10=|v_P1Thread1of1ForFork2_#t~ite10_13|} AuxVars[] AssignedVars[~a~0, P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite10] because there is no mapped edge [2019-12-07 17:27:54,159 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [836] [836] L761-->L762: Formula: (let ((.cse1 (= (mod ~a$w_buff0_used~0_In-1355021593 256) 0)) (.cse0 (= 0 (mod ~a$r_buff0_thd1~0_In-1355021593 256))) (.cse2 (= ~a$r_buff0_thd1~0_In-1355021593 ~a$r_buff0_thd1~0_Out-1355021593))) (or (and (not .cse0) (not .cse1) (= 0 ~a$r_buff0_thd1~0_Out-1355021593)) (and .cse2 .cse1) (and .cse0 .cse2))) InVars {~a$w_buff0_used~0=~a$w_buff0_used~0_In-1355021593, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In-1355021593} OutVars{P0Thread1of1ForFork1_#t~ite7=|P0Thread1of1ForFork1_#t~ite7_Out-1355021593|, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1355021593, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_Out-1355021593} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite7, ~a$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 17:27:54,159 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [850] [850] L762-->L762-2: Formula: (let ((.cse2 (= (mod ~a$w_buff0_used~0_In-854895123 256) 0)) (.cse3 (= 0 (mod ~a$r_buff0_thd1~0_In-854895123 256))) (.cse0 (= (mod ~a$w_buff1_used~0_In-854895123 256) 0)) (.cse1 (= 0 (mod ~a$r_buff1_thd1~0_In-854895123 256)))) (or (and (= |P0Thread1of1ForFork1_#t~ite8_Out-854895123| ~a$r_buff1_thd1~0_In-854895123) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P0Thread1of1ForFork1_#t~ite8_Out-854895123|) (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1)))))) InVars {~a$r_buff1_thd1~0=~a$r_buff1_thd1~0_In-854895123, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-854895123, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In-854895123, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-854895123} OutVars{P0Thread1of1ForFork1_#t~ite8=|P0Thread1of1ForFork1_#t~ite8_Out-854895123|, ~a$r_buff1_thd1~0=~a$r_buff1_thd1~0_In-854895123, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-854895123, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In-854895123, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-854895123} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite8] because there is no mapped edge [2019-12-07 17:27:54,160 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [860] [860] L762-2-->P0EXIT: Formula: (and (= 0 |v_P0Thread1of1ForFork1_#res.base_3|) (= v_~__unbuffered_cnt~0_49 (+ v_~__unbuffered_cnt~0_50 1)) (= 0 |v_P0Thread1of1ForFork1_#res.offset_3|) (= v_~a$r_buff1_thd1~0_63 |v_P0Thread1of1ForFork1_#t~ite8_34|)) InVars {P0Thread1of1ForFork1_#t~ite8=|v_P0Thread1of1ForFork1_#t~ite8_34|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_50} OutVars{P0Thread1of1ForFork1_#t~ite8=|v_P0Thread1of1ForFork1_#t~ite8_33|, P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_3|, ~a$r_buff1_thd1~0=v_~a$r_buff1_thd1~0_63, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_49} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite8, P0Thread1of1ForFork1_#res.offset, ~a$r_buff1_thd1~0, P0Thread1of1ForFork1_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 17:27:54,160 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [846] [846] L779-->L779-2: Formula: (let ((.cse1 (= 0 (mod ~a$w_buff0_used~0_In769446604 256))) (.cse0 (= (mod ~a$r_buff0_thd2~0_In769446604 256) 0))) (or (and (= ~a$w_buff0_used~0_In769446604 |P1Thread1of1ForFork2_#t~ite11_Out769446604|) (or .cse0 .cse1)) (and (not .cse1) (= |P1Thread1of1ForFork2_#t~ite11_Out769446604| 0) (not .cse0)))) InVars {~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In769446604, ~a$w_buff0_used~0=~a$w_buff0_used~0_In769446604} OutVars{~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In769446604, ~a$w_buff0_used~0=~a$w_buff0_used~0_In769446604, P1Thread1of1ForFork2_#t~ite11=|P1Thread1of1ForFork2_#t~ite11_Out769446604|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite11] because there is no mapped edge [2019-12-07 17:27:54,160 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [880] [880] L803-->L803-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-1766244926 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite20_In-1766244926| |P2Thread1of1ForFork0_#t~ite20_Out-1766244926|) (= |P2Thread1of1ForFork0_#t~ite21_Out-1766244926| ~a$w_buff0~0_In-1766244926) (not .cse0)) (and .cse0 (let ((.cse1 (= 0 (mod ~a$r_buff0_thd3~0_In-1766244926 256)))) (or (and (= 0 (mod ~a$w_buff1_used~0_In-1766244926 256)) .cse1) (and .cse1 (= (mod ~a$r_buff1_thd3~0_In-1766244926 256) 0)) (= 0 (mod ~a$w_buff0_used~0_In-1766244926 256)))) (= |P2Thread1of1ForFork0_#t~ite20_Out-1766244926| ~a$w_buff0~0_In-1766244926) (= |P2Thread1of1ForFork0_#t~ite21_Out-1766244926| |P2Thread1of1ForFork0_#t~ite20_Out-1766244926|)))) InVars {~a$w_buff0~0=~a$w_buff0~0_In-1766244926, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In-1766244926, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1766244926, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1766244926, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1766244926, P2Thread1of1ForFork0_#t~ite20=|P2Thread1of1ForFork0_#t~ite20_In-1766244926|, ~weak$$choice2~0=~weak$$choice2~0_In-1766244926} OutVars{P2Thread1of1ForFork0_#t~ite21=|P2Thread1of1ForFork0_#t~ite21_Out-1766244926|, ~a$w_buff0~0=~a$w_buff0~0_In-1766244926, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In-1766244926, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1766244926, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1766244926, P2Thread1of1ForFork0_#t~ite20=|P2Thread1of1ForFork0_#t~ite20_Out-1766244926|, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1766244926, ~weak$$choice2~0=~weak$$choice2~0_In-1766244926} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite21, P2Thread1of1ForFork0_#t~ite20] because there is no mapped edge [2019-12-07 17:27:54,160 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [884] [884] L804-->L804-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In1445510027 256) 0))) (or (and (not .cse0) (= |P2Thread1of1ForFork0_#t~ite23_In1445510027| |P2Thread1of1ForFork0_#t~ite23_Out1445510027|) (= ~a$w_buff1~0_In1445510027 |P2Thread1of1ForFork0_#t~ite24_Out1445510027|)) (and (let ((.cse1 (= 0 (mod ~a$r_buff0_thd3~0_In1445510027 256)))) (or (= (mod ~a$w_buff0_used~0_In1445510027 256) 0) (and .cse1 (= (mod ~a$r_buff1_thd3~0_In1445510027 256) 0)) (and .cse1 (= 0 (mod ~a$w_buff1_used~0_In1445510027 256))))) (= |P2Thread1of1ForFork0_#t~ite23_Out1445510027| ~a$w_buff1~0_In1445510027) .cse0 (= |P2Thread1of1ForFork0_#t~ite23_Out1445510027| |P2Thread1of1ForFork0_#t~ite24_Out1445510027|)))) InVars {~a$w_buff1~0=~a$w_buff1~0_In1445510027, P2Thread1of1ForFork0_#t~ite23=|P2Thread1of1ForFork0_#t~ite23_In1445510027|, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In1445510027, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1445510027, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In1445510027, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1445510027, ~weak$$choice2~0=~weak$$choice2~0_In1445510027} OutVars{~a$w_buff1~0=~a$w_buff1~0_In1445510027, P2Thread1of1ForFork0_#t~ite23=|P2Thread1of1ForFork0_#t~ite23_Out1445510027|, P2Thread1of1ForFork0_#t~ite24=|P2Thread1of1ForFork0_#t~ite24_Out1445510027|, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In1445510027, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1445510027, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In1445510027, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1445510027, ~weak$$choice2~0=~weak$$choice2~0_In1445510027} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite23, P2Thread1of1ForFork0_#t~ite24] because there is no mapped edge [2019-12-07 17:27:54,161 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [883] [883] L805-->L805-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In1851040903 256)))) (or (and .cse0 (let ((.cse1 (= 0 (mod ~a$r_buff0_thd3~0_In1851040903 256)))) (or (= (mod ~a$w_buff0_used~0_In1851040903 256) 0) (and .cse1 (= (mod ~a$r_buff1_thd3~0_In1851040903 256) 0)) (and (= (mod ~a$w_buff1_used~0_In1851040903 256) 0) .cse1))) (= |P2Thread1of1ForFork0_#t~ite26_Out1851040903| |P2Thread1of1ForFork0_#t~ite27_Out1851040903|) (= |P2Thread1of1ForFork0_#t~ite26_Out1851040903| ~a$w_buff0_used~0_In1851040903)) (and (= |P2Thread1of1ForFork0_#t~ite26_In1851040903| |P2Thread1of1ForFork0_#t~ite26_Out1851040903|) (= |P2Thread1of1ForFork0_#t~ite27_Out1851040903| ~a$w_buff0_used~0_In1851040903) (not .cse0)))) InVars {P2Thread1of1ForFork0_#t~ite26=|P2Thread1of1ForFork0_#t~ite26_In1851040903|, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In1851040903, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1851040903, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In1851040903, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1851040903, ~weak$$choice2~0=~weak$$choice2~0_In1851040903} OutVars{P2Thread1of1ForFork0_#t~ite26=|P2Thread1of1ForFork0_#t~ite26_Out1851040903|, P2Thread1of1ForFork0_#t~ite27=|P2Thread1of1ForFork0_#t~ite27_Out1851040903|, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In1851040903, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1851040903, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In1851040903, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1851040903, ~weak$$choice2~0=~weak$$choice2~0_In1851040903} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite26, P2Thread1of1ForFork0_#t~ite27] because there is no mapped edge [2019-12-07 17:27:54,162 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [768] [768] L807-->L808: Formula: (and (= v_~a$r_buff0_thd3~0_53 v_~a$r_buff0_thd3~0_52) (not (= 0 (mod v_~weak$$choice2~0_17 256)))) InVars {~a$r_buff0_thd3~0=v_~a$r_buff0_thd3~0_53, ~weak$$choice2~0=v_~weak$$choice2~0_17} OutVars{P2Thread1of1ForFork0_#t~ite33=|v_P2Thread1of1ForFork0_#t~ite33_5|, P2Thread1of1ForFork0_#t~ite32=|v_P2Thread1of1ForFork0_#t~ite32_5|, ~a$r_buff0_thd3~0=v_~a$r_buff0_thd3~0_52, P2Thread1of1ForFork0_#t~ite31=|v_P2Thread1of1ForFork0_#t~ite31_5|, ~weak$$choice2~0=v_~weak$$choice2~0_17} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite33, P2Thread1of1ForFork0_#t~ite32, ~a$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite31] because there is no mapped edge [2019-12-07 17:27:54,163 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L810-->L814: Formula: (and (not (= (mod v_~a$flush_delayed~0_7 256) 0)) (= v_~a~0_16 v_~a$mem_tmp~0_4) (= v_~a$flush_delayed~0_6 0)) InVars {~a$mem_tmp~0=v_~a$mem_tmp~0_4, ~a$flush_delayed~0=v_~a$flush_delayed~0_7} OutVars{P2Thread1of1ForFork0_#t~ite37=|v_P2Thread1of1ForFork0_#t~ite37_5|, ~a~0=v_~a~0_16, ~a$mem_tmp~0=v_~a$mem_tmp~0_4, ~a$flush_delayed~0=v_~a$flush_delayed~0_6} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite37, ~a~0, ~a$flush_delayed~0] because there is no mapped edge [2019-12-07 17:27:54,163 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [849] [849] L814-2-->L814-4: Formula: (let ((.cse1 (= 0 (mod ~a$w_buff1_used~0_In-1463141438 256))) (.cse0 (= (mod ~a$r_buff1_thd3~0_In-1463141438 256) 0))) (or (and (not .cse0) (= |P2Thread1of1ForFork0_#t~ite38_Out-1463141438| ~a$w_buff1~0_In-1463141438) (not .cse1)) (and (= |P2Thread1of1ForFork0_#t~ite38_Out-1463141438| ~a~0_In-1463141438) (or .cse1 .cse0)))) InVars {~a~0=~a~0_In-1463141438, ~a$w_buff1~0=~a$w_buff1~0_In-1463141438, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In-1463141438, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1463141438} OutVars{~a~0=~a~0_In-1463141438, P2Thread1of1ForFork0_#t~ite38=|P2Thread1of1ForFork0_#t~ite38_Out-1463141438|, ~a$w_buff1~0=~a$w_buff1~0_In-1463141438, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In-1463141438, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1463141438} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite38] because there is no mapped edge [2019-12-07 17:27:54,163 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [783] [783] L814-4-->L815: Formula: (= v_~a~0_36 |v_P2Thread1of1ForFork0_#t~ite38_8|) InVars {P2Thread1of1ForFork0_#t~ite38=|v_P2Thread1of1ForFork0_#t~ite38_8|} OutVars{~a~0=v_~a~0_36, P2Thread1of1ForFork0_#t~ite39=|v_P2Thread1of1ForFork0_#t~ite39_11|, P2Thread1of1ForFork0_#t~ite38=|v_P2Thread1of1ForFork0_#t~ite38_7|} AuxVars[] AssignedVars[~a~0, P2Thread1of1ForFork0_#t~ite39, P2Thread1of1ForFork0_#t~ite38] because there is no mapped edge [2019-12-07 17:27:54,163 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [851] [851] L815-->L815-2: Formula: (let ((.cse1 (= 0 (mod ~a$r_buff0_thd3~0_In1887932965 256))) (.cse0 (= 0 (mod ~a$w_buff0_used~0_In1887932965 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite40_Out1887932965| 0) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= ~a$w_buff0_used~0_In1887932965 |P2Thread1of1ForFork0_#t~ite40_Out1887932965|)))) InVars {~a$w_buff0_used~0=~a$w_buff0_used~0_In1887932965, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In1887932965} OutVars{P2Thread1of1ForFork0_#t~ite40=|P2Thread1of1ForFork0_#t~ite40_Out1887932965|, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1887932965, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In1887932965} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite40] because there is no mapped edge [2019-12-07 17:27:54,164 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [825] [825] L816-->L816-2: Formula: (let ((.cse1 (= (mod ~a$w_buff1_used~0_In-1754616751 256) 0)) (.cse0 (= (mod ~a$r_buff1_thd3~0_In-1754616751 256) 0)) (.cse2 (= (mod ~a$r_buff0_thd3~0_In-1754616751 256) 0)) (.cse3 (= (mod ~a$w_buff0_used~0_In-1754616751 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P2Thread1of1ForFork0_#t~ite41_Out-1754616751| ~a$w_buff1_used~0_In-1754616751)) (and (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork0_#t~ite41_Out-1754616751| 0)))) InVars {~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In-1754616751, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1754616751, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1754616751, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1754616751} OutVars{~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In-1754616751, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1754616751, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1754616751, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1754616751, P2Thread1of1ForFork0_#t~ite41=|P2Thread1of1ForFork0_#t~ite41_Out-1754616751|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite41] because there is no mapped edge [2019-12-07 17:27:54,164 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [844] [844] L817-->L817-2: Formula: (let ((.cse0 (= (mod ~a$w_buff0_used~0_In1812785205 256) 0)) (.cse1 (= 0 (mod ~a$r_buff0_thd3~0_In1812785205 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite42_Out1812785205| ~a$r_buff0_thd3~0_In1812785205) (or .cse0 .cse1)) (and (not .cse0) (= |P2Thread1of1ForFork0_#t~ite42_Out1812785205| 0) (not .cse1)))) InVars {~a$w_buff0_used~0=~a$w_buff0_used~0_In1812785205, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In1812785205} OutVars{~a$w_buff0_used~0=~a$w_buff0_used~0_In1812785205, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In1812785205, P2Thread1of1ForFork0_#t~ite42=|P2Thread1of1ForFork0_#t~ite42_Out1812785205|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite42] because there is no mapped edge [2019-12-07 17:27:54,164 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [828] [828] L818-->L818-2: Formula: (let ((.cse0 (= 0 (mod ~a$w_buff0_used~0_In-1998862099 256))) (.cse1 (= (mod ~a$r_buff0_thd3~0_In-1998862099 256) 0)) (.cse3 (= 0 (mod ~a$r_buff1_thd3~0_In-1998862099 256))) (.cse2 (= 0 (mod ~a$w_buff1_used~0_In-1998862099 256)))) (or (and (= ~a$r_buff1_thd3~0_In-1998862099 |P2Thread1of1ForFork0_#t~ite43_Out-1998862099|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P2Thread1of1ForFork0_#t~ite43_Out-1998862099|) (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2)))))) InVars {~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In-1998862099, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1998862099, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1998862099, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1998862099} OutVars{P2Thread1of1ForFork0_#t~ite43=|P2Thread1of1ForFork0_#t~ite43_Out-1998862099|, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In-1998862099, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1998862099, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1998862099, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1998862099} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite43] because there is no mapped edge [2019-12-07 17:27:54,165 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [848] [848] L780-->L780-2: Formula: (let ((.cse0 (= (mod ~a$r_buff1_thd2~0_In2020321206 256) 0)) (.cse1 (= 0 (mod ~a$w_buff1_used~0_In2020321206 256))) (.cse2 (= (mod ~a$r_buff0_thd2~0_In2020321206 256) 0)) (.cse3 (= (mod ~a$w_buff0_used~0_In2020321206 256) 0))) (or (and (= ~a$w_buff1_used~0_In2020321206 |P1Thread1of1ForFork2_#t~ite12_Out2020321206|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P1Thread1of1ForFork2_#t~ite12_Out2020321206|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~a$r_buff1_thd2~0=~a$r_buff1_thd2~0_In2020321206, ~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In2020321206, ~a$w_buff0_used~0=~a$w_buff0_used~0_In2020321206, ~a$w_buff1_used~0=~a$w_buff1_used~0_In2020321206} OutVars{~a$r_buff1_thd2~0=~a$r_buff1_thd2~0_In2020321206, ~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In2020321206, ~a$w_buff0_used~0=~a$w_buff0_used~0_In2020321206, P1Thread1of1ForFork2_#t~ite12=|P1Thread1of1ForFork2_#t~ite12_Out2020321206|, ~a$w_buff1_used~0=~a$w_buff1_used~0_In2020321206} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite12] because there is no mapped edge [2019-12-07 17:27:54,165 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [838] [838] L781-->L781-2: Formula: (let ((.cse1 (= 0 (mod ~a$r_buff0_thd2~0_In1723010159 256))) (.cse0 (= 0 (mod ~a$w_buff0_used~0_In1723010159 256)))) (or (and (not .cse0) (= 0 |P1Thread1of1ForFork2_#t~ite13_Out1723010159|) (not .cse1)) (and (or .cse1 .cse0) (= ~a$r_buff0_thd2~0_In1723010159 |P1Thread1of1ForFork2_#t~ite13_Out1723010159|)))) InVars {~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In1723010159, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1723010159} OutVars{~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In1723010159, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1723010159, P1Thread1of1ForFork2_#t~ite13=|P1Thread1of1ForFork2_#t~ite13_Out1723010159|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite13] because there is no mapped edge [2019-12-07 17:27:54,166 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [837] [837] L782-->L782-2: Formula: (let ((.cse2 (= (mod ~a$r_buff0_thd2~0_In924026070 256) 0)) (.cse3 (= (mod ~a$w_buff0_used~0_In924026070 256) 0)) (.cse0 (= 0 (mod ~a$r_buff1_thd2~0_In924026070 256))) (.cse1 (= (mod ~a$w_buff1_used~0_In924026070 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork2_#t~ite14_Out924026070| 0)) (and (or .cse2 .cse3) (or .cse0 .cse1) (= |P1Thread1of1ForFork2_#t~ite14_Out924026070| ~a$r_buff1_thd2~0_In924026070)))) InVars {~a$r_buff1_thd2~0=~a$r_buff1_thd2~0_In924026070, ~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In924026070, ~a$w_buff0_used~0=~a$w_buff0_used~0_In924026070, ~a$w_buff1_used~0=~a$w_buff1_used~0_In924026070} OutVars{~a$r_buff1_thd2~0=~a$r_buff1_thd2~0_In924026070, ~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In924026070, ~a$w_buff0_used~0=~a$w_buff0_used~0_In924026070, ~a$w_buff1_used~0=~a$w_buff1_used~0_In924026070, P1Thread1of1ForFork2_#t~ite14=|P1Thread1of1ForFork2_#t~ite14_Out924026070|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite14] because there is no mapped edge [2019-12-07 17:27:54,166 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [863] [863] L818-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= (+ v_~__unbuffered_cnt~0_56 1) v_~__unbuffered_cnt~0_55) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0) (= v_~a$r_buff1_thd3~0_123 |v_P2Thread1of1ForFork0_#t~ite43_32|)) InVars {P2Thread1of1ForFork0_#t~ite43=|v_P2Thread1of1ForFork0_#t~ite43_32|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_56} OutVars{P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, P2Thread1of1ForFork0_#t~ite43=|v_P2Thread1of1ForFork0_#t~ite43_31|, ~a$r_buff1_thd3~0=v_~a$r_buff1_thd3~0_123, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#res.base, P2Thread1of1ForFork0_#t~ite43, ~a$r_buff1_thd3~0, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 17:27:54,166 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [879] [879] L782-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= |v_P1Thread1of1ForFork2_#t~ite14_42| v_~a$r_buff1_thd2~0_99) (= (+ v_~__unbuffered_cnt~0_83 1) v_~__unbuffered_cnt~0_82)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_83, P1Thread1of1ForFork2_#t~ite14=|v_P1Thread1of1ForFork2_#t~ite14_42|} OutVars{P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_99, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_82, P1Thread1of1ForFork2_#t~ite14=|v_P1Thread1of1ForFork2_#t~ite14_41|, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#res.offset, ~a$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#t~ite14, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-12-07 17:27:54,166 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [799] [799] L841-1-->L847: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_9 256))) (= v_~main$tmp_guard0~0_9 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_36) 1 0)) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_36} OutVars{ULTIMATE.start_main_#t~nondet46=|v_ULTIMATE.start_main_#t~nondet46_7|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_36, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_9} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet46, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 17:27:54,166 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [832] [832] L847-2-->L847-4: Formula: (let ((.cse0 (= 0 (mod ~a$w_buff1_used~0_In139527943 256))) (.cse1 (= 0 (mod ~a$r_buff1_thd0~0_In139527943 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite47_Out139527943| ~a$w_buff1~0_In139527943) (not .cse1)) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite47_Out139527943| ~a~0_In139527943)))) InVars {~a~0=~a~0_In139527943, ~a$w_buff1~0=~a$w_buff1~0_In139527943, ~a$r_buff1_thd0~0=~a$r_buff1_thd0~0_In139527943, ~a$w_buff1_used~0=~a$w_buff1_used~0_In139527943} OutVars{~a~0=~a~0_In139527943, ~a$w_buff1~0=~a$w_buff1~0_In139527943, ULTIMATE.start_main_#t~ite47=|ULTIMATE.start_main_#t~ite47_Out139527943|, ~a$r_buff1_thd0~0=~a$r_buff1_thd0~0_In139527943, ~a$w_buff1_used~0=~a$w_buff1_used~0_In139527943} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47] because there is no mapped edge [2019-12-07 17:27:54,166 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [796] [796] L847-4-->L848: Formula: (= v_~a~0_44 |v_ULTIMATE.start_main_#t~ite47_19|) InVars {ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_19|} OutVars{~a~0=v_~a~0_44, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_18|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_16|} AuxVars[] AssignedVars[~a~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 17:27:54,166 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [826] [826] L848-->L848-2: Formula: (let ((.cse1 (= (mod ~a$r_buff0_thd0~0_In478269014 256) 0)) (.cse0 (= 0 (mod ~a$w_buff0_used~0_In478269014 256)))) (or (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite49_Out478269014| 0)) (and (or .cse1 .cse0) (= |ULTIMATE.start_main_#t~ite49_Out478269014| ~a$w_buff0_used~0_In478269014)))) InVars {~a$w_buff0_used~0=~a$w_buff0_used~0_In478269014, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In478269014} OutVars{~a$w_buff0_used~0=~a$w_buff0_used~0_In478269014, ULTIMATE.start_main_#t~ite49=|ULTIMATE.start_main_#t~ite49_Out478269014|, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In478269014} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite49] because there is no mapped edge [2019-12-07 17:27:54,167 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [831] [831] L849-->L849-2: Formula: (let ((.cse1 (= 0 (mod ~a$w_buff0_used~0_In-1332291971 256))) (.cse0 (= 0 (mod ~a$r_buff0_thd0~0_In-1332291971 256))) (.cse3 (= 0 (mod ~a$w_buff1_used~0_In-1332291971 256))) (.cse2 (= 0 (mod ~a$r_buff1_thd0~0_In-1332291971 256)))) (or (and (= |ULTIMATE.start_main_#t~ite50_Out-1332291971| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (or .cse3 .cse2) (= |ULTIMATE.start_main_#t~ite50_Out-1332291971| ~a$w_buff1_used~0_In-1332291971)))) InVars {~a$r_buff1_thd0~0=~a$r_buff1_thd0~0_In-1332291971, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1332291971, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In-1332291971, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1332291971} OutVars{ULTIMATE.start_main_#t~ite50=|ULTIMATE.start_main_#t~ite50_Out-1332291971|, ~a$r_buff1_thd0~0=~a$r_buff1_thd0~0_In-1332291971, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1332291971, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In-1332291971, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1332291971} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite50] because there is no mapped edge [2019-12-07 17:27:54,167 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [830] [830] L850-->L850-2: Formula: (let ((.cse0 (= (mod ~a$w_buff0_used~0_In-202766565 256) 0)) (.cse1 (= (mod ~a$r_buff0_thd0~0_In-202766565 256) 0))) (or (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite51_Out-202766565| 0)) (and (or .cse0 .cse1) (= ~a$r_buff0_thd0~0_In-202766565 |ULTIMATE.start_main_#t~ite51_Out-202766565|)))) InVars {~a$w_buff0_used~0=~a$w_buff0_used~0_In-202766565, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In-202766565} OutVars{ULTIMATE.start_main_#t~ite51=|ULTIMATE.start_main_#t~ite51_Out-202766565|, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-202766565, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In-202766565} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite51] because there is no mapped edge [2019-12-07 17:27:54,168 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [841] [841] L851-->L851-2: Formula: (let ((.cse3 (= (mod ~a$r_buff0_thd0~0_In976259507 256) 0)) (.cse2 (= 0 (mod ~a$w_buff0_used~0_In976259507 256))) (.cse1 (= 0 (mod ~a$r_buff1_thd0~0_In976259507 256))) (.cse0 (= 0 (mod ~a$w_buff1_used~0_In976259507 256)))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite52_Out976259507| ~a$r_buff1_thd0~0_In976259507) (or .cse2 .cse3)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0))) (= |ULTIMATE.start_main_#t~ite52_Out976259507| 0)))) InVars {~a$r_buff1_thd0~0=~a$r_buff1_thd0~0_In976259507, ~a$w_buff0_used~0=~a$w_buff0_used~0_In976259507, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In976259507, ~a$w_buff1_used~0=~a$w_buff1_used~0_In976259507} OutVars{ULTIMATE.start_main_#t~ite52=|ULTIMATE.start_main_#t~ite52_Out976259507|, ~a$r_buff1_thd0~0=~a$r_buff1_thd0~0_In976259507, ~a$w_buff0_used~0=~a$w_buff0_used~0_In976259507, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In976259507, ~a$w_buff1_used~0=~a$w_buff1_used~0_In976259507} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52] because there is no mapped edge [2019-12-07 17:27:54,168 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [899] [899] L851-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_~a$r_buff1_thd0~0_125 |v_ULTIMATE.start_main_#t~ite52_55|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_22 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_16|) (= (mod v_~main$tmp_guard1~0_29 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_16|) (= v_~main$tmp_guard1~0_29 (ite (= (ite (not (and (= v_~__unbuffered_p2_EBX~0_29 0) (= 0 v_~__unbuffered_p1_EAX~0_28) (= 1 v_~__unbuffered_p2_EAX~0_26) (= v_~__unbuffered_p0_EBX~0_85 0) (= 1 v_~__unbuffered_p0_EAX~0_85))) 1 0) 0) 0 1)) (= v_ULTIMATE.start___VERIFIER_assert_~expression_22 0)) InVars {~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_85, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_55|, ~__unbuffered_p0_EBX~0=v_~__unbuffered_p0_EBX~0_85, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_29, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_28, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_26} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_85, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_54|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_22, ~__unbuffered_p0_EBX~0=v_~__unbuffered_p0_EBX~0_85, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_29, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_28, ~a$r_buff1_thd0~0=v_~a$r_buff1_thd0~0_125, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_29, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_26, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_16|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start___VERIFIER_assert_~expression, ~a$r_buff1_thd0~0, ~main$tmp_guard1~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 17:27:54,219 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 05:27:54 BasicIcfg [2019-12-07 17:27:54,219 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 17:27:54,220 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 17:27:54,220 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 17:27:54,220 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 17:27:54,220 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:26:05" (3/4) ... [2019-12-07 17:27:54,222 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 17:27:54,222 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [904] [904] ULTIMATE.startENTRY-->L837: Formula: (let ((.cse0 (store |v_#valid_64| 0 0))) (and (= 0 v_~weak$$choice0~0_10) (= v_~a$r_buff1_thd0~0_132 0) (= 0 v_~a$w_buff0_used~0_689) (= |v_ULTIMATE.start_main_~#t397~0.offset_22| 0) (= 0 v_~a$w_buff1_used~0_376) (= v_~a$r_buff0_thd3~0_328 0) (= |v_#NULL.offset_6| 0) (= v_~y~0_79 0) (= 0 v_~a$r_buff1_thd1~0_125) (= 0 v_~__unbuffered_p0_EAX~0_92) (= 0 v_~__unbuffered_p1_EAX~0_37) (= v_~x~0_69 0) (= 0 v_~a$r_buff1_thd2~0_129) (< 0 |v_#StackHeapBarrier_17|) (= v_~__unbuffered_p0_EBX~0_92 0) (= v_~a$flush_delayed~0_23 0) (= v_~a$r_buff1_thd3~0_224 0) (= v_~__unbuffered_p2_EBX~0_38 0) (= 0 v_~__unbuffered_cnt~0_98) (= v_~main$tmp_guard0~0_28 0) (= 0 v_~a$r_buff0_thd2~0_124) (= v_~a~0_181 0) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t397~0.base_29|) (= 0 |v_#NULL.base_6|) (= (select .cse0 |v_ULTIMATE.start_main_~#t397~0.base_29|) 0) (= 0 v_~__unbuffered_p2_EAX~0_33) (= |v_#valid_62| (store .cse0 |v_ULTIMATE.start_main_~#t397~0.base_29| 1)) (= 0 v_~a$r_buff0_thd1~0_195) (= v_~a$mem_tmp~0_12 0) (= v_~main$tmp_guard1~0_36 0) (= 0 v_~a$w_buff1~0_172) (= v_~a$r_buff0_thd0~0_144 0) (= v_~a$w_buff0~0_228 0) (= (store |v_#memory_int_22| |v_ULTIMATE.start_main_~#t397~0.base_29| (store (select |v_#memory_int_22| |v_ULTIMATE.start_main_~#t397~0.base_29|) |v_ULTIMATE.start_main_~#t397~0.offset_22| 0)) |v_#memory_int_21|) (= v_~weak$$choice2~0_107 0) (= v_~z~0_20 0) (= |v_#length_23| (store |v_#length_24| |v_ULTIMATE.start_main_~#t397~0.base_29| 4)) (= 0 v_~a$read_delayed~0_6) (= v_~a$read_delayed_var~0.offset_6 0) (= 0 v_~a$read_delayed_var~0.base_6))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_64|, #memory_int=|v_#memory_int_22|, #length=|v_#length_24|} OutVars{~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_129, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_51|, #NULL.offset=|v_#NULL.offset_6|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_281|, ~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_144, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_31|, ~a~0=v_~a~0_181, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_67|, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_92, ULTIMATE.start_main_~#t398~0.base=|v_ULTIMATE.start_main_~#t398~0.base_29|, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_37, #length=|v_#length_23|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_33, ULTIMATE.start_main_~#t397~0.offset=|v_ULTIMATE.start_main_~#t397~0.offset_22|, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_38, ~__unbuffered_p0_EBX~0=v_~__unbuffered_p0_EBX~0_92, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_10|, ~a$r_buff1_thd3~0=v_~a$r_buff1_thd3~0_224, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_689, ~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_195, ~weak$$choice0~0=v_~weak$$choice0~0_10, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ~a$read_delayed_var~0.offset=v_~a$read_delayed_var~0.offset_6, ~a$w_buff0~0=v_~a$w_buff0~0_228, ~a$r_buff1_thd0~0=v_~a$r_buff1_thd0~0_132, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_98, ~x~0=v_~x~0_69, ~a$read_delayed~0=v_~a$read_delayed~0_6, ~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_124, ULTIMATE.start_main_~#t397~0.base=|v_ULTIMATE.start_main_~#t397~0.base_29|, ULTIMATE.start_main_~#t398~0.offset=|v_ULTIMATE.start_main_~#t398~0.offset_22|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_36, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_55|, ~a$mem_tmp~0=v_~a$mem_tmp~0_12, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_45|, ~a$w_buff1~0=v_~a$w_buff1~0_172, ~y~0=v_~y~0_79, ULTIMATE.start_main_~#t399~0.base=|v_ULTIMATE.start_main_~#t399~0.base_17|, ULTIMATE.start_main_#t~nondet46=|v_ULTIMATE.start_main_#t~nondet46_27|, ULTIMATE.start_main_~#t399~0.offset=|v_ULTIMATE.start_main_~#t399~0.offset_15|, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_9|, ~a$r_buff1_thd1~0=v_~a$r_buff1_thd1~0_125, ~a$r_buff0_thd3~0=v_~a$r_buff0_thd3~0_328, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_28, #NULL.base=|v_#NULL.base_6|, ~a$flush_delayed~0=v_~a$flush_delayed~0_23, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, #valid=|v_#valid_62|, #memory_int=|v_#memory_int_21|, ~z~0=v_~z~0_20, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_376, ~weak$$choice2~0=v_~weak$$choice2~0_107, ~a$read_delayed_var~0.base=v_~a$read_delayed_var~0.base_6} AuxVars[] AssignedVars[~a$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite49, ~a$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite50, ~a~0, ULTIMATE.start_main_#t~ite52, ~__unbuffered_p0_EAX~0, ULTIMATE.start_main_~#t398~0.base, ~__unbuffered_p1_EAX~0, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_~#t397~0.offset, ~__unbuffered_p2_EBX~0, ~__unbuffered_p0_EBX~0, ULTIMATE.start_main_#t~nondet45, ~a$r_buff1_thd3~0, ~a$w_buff0_used~0, ~a$r_buff0_thd1~0, ~weak$$choice0~0, ~a$read_delayed_var~0.offset, ~a$w_buff0~0, ~a$r_buff1_thd0~0, ~__unbuffered_cnt~0, ~x~0, ~a$read_delayed~0, ~a$r_buff0_thd2~0, ULTIMATE.start_main_~#t397~0.base, ULTIMATE.start_main_~#t398~0.offset, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite48, ~a$mem_tmp~0, ULTIMATE.start_main_#t~ite51, ~a$w_buff1~0, ~y~0, ULTIMATE.start_main_~#t399~0.base, ULTIMATE.start_main_#t~nondet46, ULTIMATE.start_main_~#t399~0.offset, ULTIMATE.start_main_#t~nondet44, ~a$r_buff1_thd1~0, ~a$r_buff0_thd3~0, ~main$tmp_guard0~0, #NULL.base, ~a$flush_delayed~0, ULTIMATE.start_main_#res, #valid, #memory_int, ~z~0, ~a$w_buff1_used~0, ~weak$$choice2~0, ~a$read_delayed_var~0.base] because there is no mapped edge [2019-12-07 17:27:54,222 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [865] [865] L837-1-->L839: Formula: (and (= (store |v_#valid_35| |v_ULTIMATE.start_main_~#t398~0.base_12| 1) |v_#valid_34|) (not (= |v_ULTIMATE.start_main_~#t398~0.base_12| 0)) (= |v_ULTIMATE.start_main_~#t398~0.offset_10| 0) (< |v_#StackHeapBarrier_9| |v_ULTIMATE.start_main_~#t398~0.base_12|) (= |v_#length_13| (store |v_#length_14| |v_ULTIMATE.start_main_~#t398~0.base_12| 4)) (= 0 (select |v_#valid_35| |v_ULTIMATE.start_main_~#t398~0.base_12|)) (= (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t398~0.base_12| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t398~0.base_12|) |v_ULTIMATE.start_main_~#t398~0.offset_10| 1)) |v_#memory_int_11|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_12|, #length=|v_#length_14|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_9|, ULTIMATE.start_main_~#t398~0.base=|v_ULTIMATE.start_main_~#t398~0.base_12|, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_4|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_11|, ULTIMATE.start_main_~#t398~0.offset=|v_ULTIMATE.start_main_~#t398~0.offset_10|, #length=|v_#length_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t398~0.base, ULTIMATE.start_main_#t~nondet44, #valid, #memory_int, ULTIMATE.start_main_~#t398~0.offset, #length] because there is no mapped edge [2019-12-07 17:27:54,223 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [876] [876] L839-1-->L841: Formula: (and (= 0 (select |v_#valid_37| |v_ULTIMATE.start_main_~#t399~0.base_13|)) (not (= 0 |v_ULTIMATE.start_main_~#t399~0.base_13|)) (= |v_ULTIMATE.start_main_~#t399~0.offset_11| 0) (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t399~0.base_13|) (= |v_#memory_int_13| (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t399~0.base_13| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t399~0.base_13|) |v_ULTIMATE.start_main_~#t399~0.offset_11| 2))) (= (store |v_#length_16| |v_ULTIMATE.start_main_~#t399~0.base_13| 4) |v_#length_15|) (= |v_#valid_36| (store |v_#valid_37| |v_ULTIMATE.start_main_~#t399~0.base_13| 1))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_37|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{ULTIMATE.start_main_~#t399~0.base=|v_ULTIMATE.start_main_~#t399~0.base_13|, #StackHeapBarrier=|v_#StackHeapBarrier_10|, ULTIMATE.start_main_~#t399~0.offset=|v_ULTIMATE.start_main_~#t399~0.offset_11|, #valid=|v_#valid_36|, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_6|, #memory_int=|v_#memory_int_13|, #length=|v_#length_15|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t399~0.base, ULTIMATE.start_main_~#t399~0.offset, #valid, ULTIMATE.start_main_#t~nondet45, #memory_int, #length] because there is no mapped edge [2019-12-07 17:27:54,223 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [881] [881] L4-->L758: Formula: (and (= ~x~0_Out-1421356120 1) (= ~a$r_buff0_thd0~0_In-1421356120 ~a$r_buff1_thd0~0_Out-1421356120) (= ~a$r_buff1_thd2~0_Out-1421356120 ~a$r_buff0_thd2~0_In-1421356120) (= ~x~0_Out-1421356120 ~__unbuffered_p0_EAX~0_Out-1421356120) (not (= P0Thread1of1ForFork1___VERIFIER_assert_~expression_In-1421356120 0)) (= ~a$r_buff0_thd1~0_Out-1421356120 1) (= ~a$r_buff0_thd3~0_In-1421356120 ~a$r_buff1_thd3~0_Out-1421356120) (= ~a$r_buff1_thd1~0_Out-1421356120 ~a$r_buff0_thd1~0_In-1421356120) (= ~__unbuffered_p0_EBX~0_Out-1421356120 ~y~0_In-1421356120)) InVars {~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In-1421356120, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1421356120, P0Thread1of1ForFork1___VERIFIER_assert_~expression=P0Thread1of1ForFork1___VERIFIER_assert_~expression_In-1421356120, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In-1421356120, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In-1421356120, ~y~0=~y~0_In-1421356120} OutVars{~__unbuffered_p0_EBX~0=~__unbuffered_p0_EBX~0_Out-1421356120, ~a$r_buff1_thd1~0=~a$r_buff1_thd1~0_Out-1421356120, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_Out-1421356120, ~a$r_buff1_thd2~0=~a$r_buff1_thd2~0_Out-1421356120, ~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In-1421356120, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1421356120, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_Out-1421356120, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In-1421356120, ~__unbuffered_p0_EAX~0=~__unbuffered_p0_EAX~0_Out-1421356120, ~a$r_buff1_thd0~0=~a$r_buff1_thd0~0_Out-1421356120, P0Thread1of1ForFork1___VERIFIER_assert_~expression=P0Thread1of1ForFork1___VERIFIER_assert_~expression_In-1421356120, ~y~0=~y~0_In-1421356120, ~x~0=~x~0_Out-1421356120} AuxVars[] AssignedVars[~__unbuffered_p0_EAX~0, ~__unbuffered_p0_EBX~0, ~a$r_buff1_thd1~0, ~a$r_buff1_thd3~0, ~a$r_buff1_thd2~0, ~a$r_buff1_thd0~0, ~a$r_buff0_thd1~0, ~x~0] because there is no mapped edge [2019-12-07 17:27:54,225 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [842] [842] L759-->L759-2: Formula: (let ((.cse0 (= (mod ~a$w_buff0_used~0_In1824585213 256) 0)) (.cse1 (= (mod ~a$r_buff0_thd1~0_In1824585213 256) 0))) (or (and (not .cse0) (not .cse1) (= |P0Thread1of1ForFork1_#t~ite5_Out1824585213| 0)) (and (= ~a$w_buff0_used~0_In1824585213 |P0Thread1of1ForFork1_#t~ite5_Out1824585213|) (or .cse0 .cse1)))) InVars {~a$w_buff0_used~0=~a$w_buff0_used~0_In1824585213, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In1824585213} OutVars{P0Thread1of1ForFork1_#t~ite5=|P0Thread1of1ForFork1_#t~ite5_Out1824585213|, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1824585213, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In1824585213} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite5] because there is no mapped edge [2019-12-07 17:27:54,226 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [840] [840] L760-->L760-2: Formula: (let ((.cse3 (= 0 (mod ~a$w_buff0_used~0_In1050417585 256))) (.cse2 (= (mod ~a$r_buff0_thd1~0_In1050417585 256) 0)) (.cse1 (= 0 (mod ~a$w_buff1_used~0_In1050417585 256))) (.cse0 (= 0 (mod ~a$r_buff1_thd1~0_In1050417585 256)))) (or (and (= |P0Thread1of1ForFork1_#t~ite6_Out1050417585| ~a$w_buff1_used~0_In1050417585) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |P0Thread1of1ForFork1_#t~ite6_Out1050417585| 0) (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0)))))) InVars {~a$r_buff1_thd1~0=~a$r_buff1_thd1~0_In1050417585, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1050417585, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In1050417585, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1050417585} OutVars{P0Thread1of1ForFork1_#t~ite6=|P0Thread1of1ForFork1_#t~ite6_Out1050417585|, ~a$r_buff1_thd1~0=~a$r_buff1_thd1~0_In1050417585, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1050417585, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In1050417585, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1050417585} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite6] because there is no mapped edge [2019-12-07 17:27:54,226 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [829] [829] L778-2-->L778-4: Formula: (let ((.cse1 (= 0 (mod ~a$r_buff1_thd2~0_In-759837036 256))) (.cse0 (= (mod ~a$w_buff1_used~0_In-759837036 256) 0))) (or (and (not .cse0) (not .cse1) (= |P1Thread1of1ForFork2_#t~ite9_Out-759837036| ~a$w_buff1~0_In-759837036)) (and (= |P1Thread1of1ForFork2_#t~ite9_Out-759837036| ~a~0_In-759837036) (or .cse1 .cse0)))) InVars {~a~0=~a~0_In-759837036, ~a$w_buff1~0=~a$w_buff1~0_In-759837036, ~a$r_buff1_thd2~0=~a$r_buff1_thd2~0_In-759837036, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-759837036} OutVars{~a~0=~a~0_In-759837036, P1Thread1of1ForFork2_#t~ite9=|P1Thread1of1ForFork2_#t~ite9_Out-759837036|, ~a$w_buff1~0=~a$w_buff1~0_In-759837036, ~a$r_buff1_thd2~0=~a$r_buff1_thd2~0_In-759837036, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-759837036} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite9] because there is no mapped edge [2019-12-07 17:27:54,226 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L778-4-->L779: Formula: (= |v_P1Thread1of1ForFork2_#t~ite9_10| v_~a~0_28) InVars {P1Thread1of1ForFork2_#t~ite9=|v_P1Thread1of1ForFork2_#t~ite9_10|} OutVars{~a~0=v_~a~0_28, P1Thread1of1ForFork2_#t~ite9=|v_P1Thread1of1ForFork2_#t~ite9_9|, P1Thread1of1ForFork2_#t~ite10=|v_P1Thread1of1ForFork2_#t~ite10_13|} AuxVars[] AssignedVars[~a~0, P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite10] because there is no mapped edge [2019-12-07 17:27:54,226 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [836] [836] L761-->L762: Formula: (let ((.cse1 (= (mod ~a$w_buff0_used~0_In-1355021593 256) 0)) (.cse0 (= 0 (mod ~a$r_buff0_thd1~0_In-1355021593 256))) (.cse2 (= ~a$r_buff0_thd1~0_In-1355021593 ~a$r_buff0_thd1~0_Out-1355021593))) (or (and (not .cse0) (not .cse1) (= 0 ~a$r_buff0_thd1~0_Out-1355021593)) (and .cse2 .cse1) (and .cse0 .cse2))) InVars {~a$w_buff0_used~0=~a$w_buff0_used~0_In-1355021593, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In-1355021593} OutVars{P0Thread1of1ForFork1_#t~ite7=|P0Thread1of1ForFork1_#t~ite7_Out-1355021593|, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1355021593, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_Out-1355021593} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite7, ~a$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 17:27:54,226 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [850] [850] L762-->L762-2: Formula: (let ((.cse2 (= (mod ~a$w_buff0_used~0_In-854895123 256) 0)) (.cse3 (= 0 (mod ~a$r_buff0_thd1~0_In-854895123 256))) (.cse0 (= (mod ~a$w_buff1_used~0_In-854895123 256) 0)) (.cse1 (= 0 (mod ~a$r_buff1_thd1~0_In-854895123 256)))) (or (and (= |P0Thread1of1ForFork1_#t~ite8_Out-854895123| ~a$r_buff1_thd1~0_In-854895123) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P0Thread1of1ForFork1_#t~ite8_Out-854895123|) (or (and (not .cse2) (not .cse3)) (and (not .cse0) (not .cse1)))))) InVars {~a$r_buff1_thd1~0=~a$r_buff1_thd1~0_In-854895123, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-854895123, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In-854895123, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-854895123} OutVars{P0Thread1of1ForFork1_#t~ite8=|P0Thread1of1ForFork1_#t~ite8_Out-854895123|, ~a$r_buff1_thd1~0=~a$r_buff1_thd1~0_In-854895123, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-854895123, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In-854895123, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-854895123} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite8] because there is no mapped edge [2019-12-07 17:27:54,226 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [860] [860] L762-2-->P0EXIT: Formula: (and (= 0 |v_P0Thread1of1ForFork1_#res.base_3|) (= v_~__unbuffered_cnt~0_49 (+ v_~__unbuffered_cnt~0_50 1)) (= 0 |v_P0Thread1of1ForFork1_#res.offset_3|) (= v_~a$r_buff1_thd1~0_63 |v_P0Thread1of1ForFork1_#t~ite8_34|)) InVars {P0Thread1of1ForFork1_#t~ite8=|v_P0Thread1of1ForFork1_#t~ite8_34|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_50} OutVars{P0Thread1of1ForFork1_#t~ite8=|v_P0Thread1of1ForFork1_#t~ite8_33|, P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_3|, ~a$r_buff1_thd1~0=v_~a$r_buff1_thd1~0_63, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_49} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite8, P0Thread1of1ForFork1_#res.offset, ~a$r_buff1_thd1~0, P0Thread1of1ForFork1_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 17:27:54,227 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [846] [846] L779-->L779-2: Formula: (let ((.cse1 (= 0 (mod ~a$w_buff0_used~0_In769446604 256))) (.cse0 (= (mod ~a$r_buff0_thd2~0_In769446604 256) 0))) (or (and (= ~a$w_buff0_used~0_In769446604 |P1Thread1of1ForFork2_#t~ite11_Out769446604|) (or .cse0 .cse1)) (and (not .cse1) (= |P1Thread1of1ForFork2_#t~ite11_Out769446604| 0) (not .cse0)))) InVars {~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In769446604, ~a$w_buff0_used~0=~a$w_buff0_used~0_In769446604} OutVars{~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In769446604, ~a$w_buff0_used~0=~a$w_buff0_used~0_In769446604, P1Thread1of1ForFork2_#t~ite11=|P1Thread1of1ForFork2_#t~ite11_Out769446604|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite11] because there is no mapped edge [2019-12-07 17:27:54,227 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [880] [880] L803-->L803-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In-1766244926 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite20_In-1766244926| |P2Thread1of1ForFork0_#t~ite20_Out-1766244926|) (= |P2Thread1of1ForFork0_#t~ite21_Out-1766244926| ~a$w_buff0~0_In-1766244926) (not .cse0)) (and .cse0 (let ((.cse1 (= 0 (mod ~a$r_buff0_thd3~0_In-1766244926 256)))) (or (and (= 0 (mod ~a$w_buff1_used~0_In-1766244926 256)) .cse1) (and .cse1 (= (mod ~a$r_buff1_thd3~0_In-1766244926 256) 0)) (= 0 (mod ~a$w_buff0_used~0_In-1766244926 256)))) (= |P2Thread1of1ForFork0_#t~ite20_Out-1766244926| ~a$w_buff0~0_In-1766244926) (= |P2Thread1of1ForFork0_#t~ite21_Out-1766244926| |P2Thread1of1ForFork0_#t~ite20_Out-1766244926|)))) InVars {~a$w_buff0~0=~a$w_buff0~0_In-1766244926, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In-1766244926, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1766244926, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1766244926, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1766244926, P2Thread1of1ForFork0_#t~ite20=|P2Thread1of1ForFork0_#t~ite20_In-1766244926|, ~weak$$choice2~0=~weak$$choice2~0_In-1766244926} OutVars{P2Thread1of1ForFork0_#t~ite21=|P2Thread1of1ForFork0_#t~ite21_Out-1766244926|, ~a$w_buff0~0=~a$w_buff0~0_In-1766244926, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In-1766244926, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1766244926, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1766244926, P2Thread1of1ForFork0_#t~ite20=|P2Thread1of1ForFork0_#t~ite20_Out-1766244926|, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1766244926, ~weak$$choice2~0=~weak$$choice2~0_In-1766244926} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite21, P2Thread1of1ForFork0_#t~ite20] because there is no mapped edge [2019-12-07 17:27:54,227 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [884] [884] L804-->L804-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In1445510027 256) 0))) (or (and (not .cse0) (= |P2Thread1of1ForFork0_#t~ite23_In1445510027| |P2Thread1of1ForFork0_#t~ite23_Out1445510027|) (= ~a$w_buff1~0_In1445510027 |P2Thread1of1ForFork0_#t~ite24_Out1445510027|)) (and (let ((.cse1 (= 0 (mod ~a$r_buff0_thd3~0_In1445510027 256)))) (or (= (mod ~a$w_buff0_used~0_In1445510027 256) 0) (and .cse1 (= (mod ~a$r_buff1_thd3~0_In1445510027 256) 0)) (and .cse1 (= 0 (mod ~a$w_buff1_used~0_In1445510027 256))))) (= |P2Thread1of1ForFork0_#t~ite23_Out1445510027| ~a$w_buff1~0_In1445510027) .cse0 (= |P2Thread1of1ForFork0_#t~ite23_Out1445510027| |P2Thread1of1ForFork0_#t~ite24_Out1445510027|)))) InVars {~a$w_buff1~0=~a$w_buff1~0_In1445510027, P2Thread1of1ForFork0_#t~ite23=|P2Thread1of1ForFork0_#t~ite23_In1445510027|, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In1445510027, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1445510027, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In1445510027, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1445510027, ~weak$$choice2~0=~weak$$choice2~0_In1445510027} OutVars{~a$w_buff1~0=~a$w_buff1~0_In1445510027, P2Thread1of1ForFork0_#t~ite23=|P2Thread1of1ForFork0_#t~ite23_Out1445510027|, P2Thread1of1ForFork0_#t~ite24=|P2Thread1of1ForFork0_#t~ite24_Out1445510027|, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In1445510027, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1445510027, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In1445510027, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1445510027, ~weak$$choice2~0=~weak$$choice2~0_In1445510027} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite23, P2Thread1of1ForFork0_#t~ite24] because there is no mapped edge [2019-12-07 17:27:54,228 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [883] [883] L805-->L805-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In1851040903 256)))) (or (and .cse0 (let ((.cse1 (= 0 (mod ~a$r_buff0_thd3~0_In1851040903 256)))) (or (= (mod ~a$w_buff0_used~0_In1851040903 256) 0) (and .cse1 (= (mod ~a$r_buff1_thd3~0_In1851040903 256) 0)) (and (= (mod ~a$w_buff1_used~0_In1851040903 256) 0) .cse1))) (= |P2Thread1of1ForFork0_#t~ite26_Out1851040903| |P2Thread1of1ForFork0_#t~ite27_Out1851040903|) (= |P2Thread1of1ForFork0_#t~ite26_Out1851040903| ~a$w_buff0_used~0_In1851040903)) (and (= |P2Thread1of1ForFork0_#t~ite26_In1851040903| |P2Thread1of1ForFork0_#t~ite26_Out1851040903|) (= |P2Thread1of1ForFork0_#t~ite27_Out1851040903| ~a$w_buff0_used~0_In1851040903) (not .cse0)))) InVars {P2Thread1of1ForFork0_#t~ite26=|P2Thread1of1ForFork0_#t~ite26_In1851040903|, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In1851040903, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1851040903, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In1851040903, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1851040903, ~weak$$choice2~0=~weak$$choice2~0_In1851040903} OutVars{P2Thread1of1ForFork0_#t~ite26=|P2Thread1of1ForFork0_#t~ite26_Out1851040903|, P2Thread1of1ForFork0_#t~ite27=|P2Thread1of1ForFork0_#t~ite27_Out1851040903|, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In1851040903, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1851040903, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In1851040903, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1851040903, ~weak$$choice2~0=~weak$$choice2~0_In1851040903} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite26, P2Thread1of1ForFork0_#t~ite27] because there is no mapped edge [2019-12-07 17:27:54,229 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [768] [768] L807-->L808: Formula: (and (= v_~a$r_buff0_thd3~0_53 v_~a$r_buff0_thd3~0_52) (not (= 0 (mod v_~weak$$choice2~0_17 256)))) InVars {~a$r_buff0_thd3~0=v_~a$r_buff0_thd3~0_53, ~weak$$choice2~0=v_~weak$$choice2~0_17} OutVars{P2Thread1of1ForFork0_#t~ite33=|v_P2Thread1of1ForFork0_#t~ite33_5|, P2Thread1of1ForFork0_#t~ite32=|v_P2Thread1of1ForFork0_#t~ite32_5|, ~a$r_buff0_thd3~0=v_~a$r_buff0_thd3~0_52, P2Thread1of1ForFork0_#t~ite31=|v_P2Thread1of1ForFork0_#t~ite31_5|, ~weak$$choice2~0=v_~weak$$choice2~0_17} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite33, P2Thread1of1ForFork0_#t~ite32, ~a$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite31] because there is no mapped edge [2019-12-07 17:27:54,229 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L810-->L814: Formula: (and (not (= (mod v_~a$flush_delayed~0_7 256) 0)) (= v_~a~0_16 v_~a$mem_tmp~0_4) (= v_~a$flush_delayed~0_6 0)) InVars {~a$mem_tmp~0=v_~a$mem_tmp~0_4, ~a$flush_delayed~0=v_~a$flush_delayed~0_7} OutVars{P2Thread1of1ForFork0_#t~ite37=|v_P2Thread1of1ForFork0_#t~ite37_5|, ~a~0=v_~a~0_16, ~a$mem_tmp~0=v_~a$mem_tmp~0_4, ~a$flush_delayed~0=v_~a$flush_delayed~0_6} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite37, ~a~0, ~a$flush_delayed~0] because there is no mapped edge [2019-12-07 17:27:54,230 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [849] [849] L814-2-->L814-4: Formula: (let ((.cse1 (= 0 (mod ~a$w_buff1_used~0_In-1463141438 256))) (.cse0 (= (mod ~a$r_buff1_thd3~0_In-1463141438 256) 0))) (or (and (not .cse0) (= |P2Thread1of1ForFork0_#t~ite38_Out-1463141438| ~a$w_buff1~0_In-1463141438) (not .cse1)) (and (= |P2Thread1of1ForFork0_#t~ite38_Out-1463141438| ~a~0_In-1463141438) (or .cse1 .cse0)))) InVars {~a~0=~a~0_In-1463141438, ~a$w_buff1~0=~a$w_buff1~0_In-1463141438, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In-1463141438, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1463141438} OutVars{~a~0=~a~0_In-1463141438, P2Thread1of1ForFork0_#t~ite38=|P2Thread1of1ForFork0_#t~ite38_Out-1463141438|, ~a$w_buff1~0=~a$w_buff1~0_In-1463141438, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In-1463141438, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1463141438} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite38] because there is no mapped edge [2019-12-07 17:27:54,230 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [783] [783] L814-4-->L815: Formula: (= v_~a~0_36 |v_P2Thread1of1ForFork0_#t~ite38_8|) InVars {P2Thread1of1ForFork0_#t~ite38=|v_P2Thread1of1ForFork0_#t~ite38_8|} OutVars{~a~0=v_~a~0_36, P2Thread1of1ForFork0_#t~ite39=|v_P2Thread1of1ForFork0_#t~ite39_11|, P2Thread1of1ForFork0_#t~ite38=|v_P2Thread1of1ForFork0_#t~ite38_7|} AuxVars[] AssignedVars[~a~0, P2Thread1of1ForFork0_#t~ite39, P2Thread1of1ForFork0_#t~ite38] because there is no mapped edge [2019-12-07 17:27:54,230 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [851] [851] L815-->L815-2: Formula: (let ((.cse1 (= 0 (mod ~a$r_buff0_thd3~0_In1887932965 256))) (.cse0 (= 0 (mod ~a$w_buff0_used~0_In1887932965 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite40_Out1887932965| 0) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= ~a$w_buff0_used~0_In1887932965 |P2Thread1of1ForFork0_#t~ite40_Out1887932965|)))) InVars {~a$w_buff0_used~0=~a$w_buff0_used~0_In1887932965, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In1887932965} OutVars{P2Thread1of1ForFork0_#t~ite40=|P2Thread1of1ForFork0_#t~ite40_Out1887932965|, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1887932965, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In1887932965} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite40] because there is no mapped edge [2019-12-07 17:27:54,230 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [825] [825] L816-->L816-2: Formula: (let ((.cse1 (= (mod ~a$w_buff1_used~0_In-1754616751 256) 0)) (.cse0 (= (mod ~a$r_buff1_thd3~0_In-1754616751 256) 0)) (.cse2 (= (mod ~a$r_buff0_thd3~0_In-1754616751 256) 0)) (.cse3 (= (mod ~a$w_buff0_used~0_In-1754616751 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P2Thread1of1ForFork0_#t~ite41_Out-1754616751| ~a$w_buff1_used~0_In-1754616751)) (and (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork0_#t~ite41_Out-1754616751| 0)))) InVars {~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In-1754616751, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1754616751, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1754616751, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1754616751} OutVars{~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In-1754616751, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1754616751, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1754616751, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1754616751, P2Thread1of1ForFork0_#t~ite41=|P2Thread1of1ForFork0_#t~ite41_Out-1754616751|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite41] because there is no mapped edge [2019-12-07 17:27:54,231 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [844] [844] L817-->L817-2: Formula: (let ((.cse0 (= (mod ~a$w_buff0_used~0_In1812785205 256) 0)) (.cse1 (= 0 (mod ~a$r_buff0_thd3~0_In1812785205 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite42_Out1812785205| ~a$r_buff0_thd3~0_In1812785205) (or .cse0 .cse1)) (and (not .cse0) (= |P2Thread1of1ForFork0_#t~ite42_Out1812785205| 0) (not .cse1)))) InVars {~a$w_buff0_used~0=~a$w_buff0_used~0_In1812785205, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In1812785205} OutVars{~a$w_buff0_used~0=~a$w_buff0_used~0_In1812785205, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In1812785205, P2Thread1of1ForFork0_#t~ite42=|P2Thread1of1ForFork0_#t~ite42_Out1812785205|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite42] because there is no mapped edge [2019-12-07 17:27:54,231 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [828] [828] L818-->L818-2: Formula: (let ((.cse0 (= 0 (mod ~a$w_buff0_used~0_In-1998862099 256))) (.cse1 (= (mod ~a$r_buff0_thd3~0_In-1998862099 256) 0)) (.cse3 (= 0 (mod ~a$r_buff1_thd3~0_In-1998862099 256))) (.cse2 (= 0 (mod ~a$w_buff1_used~0_In-1998862099 256)))) (or (and (= ~a$r_buff1_thd3~0_In-1998862099 |P2Thread1of1ForFork0_#t~ite43_Out-1998862099|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P2Thread1of1ForFork0_#t~ite43_Out-1998862099|) (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2)))))) InVars {~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In-1998862099, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1998862099, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1998862099, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1998862099} OutVars{P2Thread1of1ForFork0_#t~ite43=|P2Thread1of1ForFork0_#t~ite43_Out-1998862099|, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In-1998862099, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1998862099, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1998862099, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1998862099} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite43] because there is no mapped edge [2019-12-07 17:27:54,232 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [848] [848] L780-->L780-2: Formula: (let ((.cse0 (= (mod ~a$r_buff1_thd2~0_In2020321206 256) 0)) (.cse1 (= 0 (mod ~a$w_buff1_used~0_In2020321206 256))) (.cse2 (= (mod ~a$r_buff0_thd2~0_In2020321206 256) 0)) (.cse3 (= (mod ~a$w_buff0_used~0_In2020321206 256) 0))) (or (and (= ~a$w_buff1_used~0_In2020321206 |P1Thread1of1ForFork2_#t~ite12_Out2020321206|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P1Thread1of1ForFork2_#t~ite12_Out2020321206|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~a$r_buff1_thd2~0=~a$r_buff1_thd2~0_In2020321206, ~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In2020321206, ~a$w_buff0_used~0=~a$w_buff0_used~0_In2020321206, ~a$w_buff1_used~0=~a$w_buff1_used~0_In2020321206} OutVars{~a$r_buff1_thd2~0=~a$r_buff1_thd2~0_In2020321206, ~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In2020321206, ~a$w_buff0_used~0=~a$w_buff0_used~0_In2020321206, P1Thread1of1ForFork2_#t~ite12=|P1Thread1of1ForFork2_#t~ite12_Out2020321206|, ~a$w_buff1_used~0=~a$w_buff1_used~0_In2020321206} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite12] because there is no mapped edge [2019-12-07 17:27:54,232 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [838] [838] L781-->L781-2: Formula: (let ((.cse1 (= 0 (mod ~a$r_buff0_thd2~0_In1723010159 256))) (.cse0 (= 0 (mod ~a$w_buff0_used~0_In1723010159 256)))) (or (and (not .cse0) (= 0 |P1Thread1of1ForFork2_#t~ite13_Out1723010159|) (not .cse1)) (and (or .cse1 .cse0) (= ~a$r_buff0_thd2~0_In1723010159 |P1Thread1of1ForFork2_#t~ite13_Out1723010159|)))) InVars {~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In1723010159, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1723010159} OutVars{~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In1723010159, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1723010159, P1Thread1of1ForFork2_#t~ite13=|P1Thread1of1ForFork2_#t~ite13_Out1723010159|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite13] because there is no mapped edge [2019-12-07 17:27:54,232 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [837] [837] L782-->L782-2: Formula: (let ((.cse2 (= (mod ~a$r_buff0_thd2~0_In924026070 256) 0)) (.cse3 (= (mod ~a$w_buff0_used~0_In924026070 256) 0)) (.cse0 (= 0 (mod ~a$r_buff1_thd2~0_In924026070 256))) (.cse1 (= (mod ~a$w_buff1_used~0_In924026070 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork2_#t~ite14_Out924026070| 0)) (and (or .cse2 .cse3) (or .cse0 .cse1) (= |P1Thread1of1ForFork2_#t~ite14_Out924026070| ~a$r_buff1_thd2~0_In924026070)))) InVars {~a$r_buff1_thd2~0=~a$r_buff1_thd2~0_In924026070, ~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In924026070, ~a$w_buff0_used~0=~a$w_buff0_used~0_In924026070, ~a$w_buff1_used~0=~a$w_buff1_used~0_In924026070} OutVars{~a$r_buff1_thd2~0=~a$r_buff1_thd2~0_In924026070, ~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In924026070, ~a$w_buff0_used~0=~a$w_buff0_used~0_In924026070, ~a$w_buff1_used~0=~a$w_buff1_used~0_In924026070, P1Thread1of1ForFork2_#t~ite14=|P1Thread1of1ForFork2_#t~ite14_Out924026070|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite14] because there is no mapped edge [2019-12-07 17:27:54,232 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [863] [863] L818-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= (+ v_~__unbuffered_cnt~0_56 1) v_~__unbuffered_cnt~0_55) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0) (= v_~a$r_buff1_thd3~0_123 |v_P2Thread1of1ForFork0_#t~ite43_32|)) InVars {P2Thread1of1ForFork0_#t~ite43=|v_P2Thread1of1ForFork0_#t~ite43_32|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_56} OutVars{P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, P2Thread1of1ForFork0_#t~ite43=|v_P2Thread1of1ForFork0_#t~ite43_31|, ~a$r_buff1_thd3~0=v_~a$r_buff1_thd3~0_123, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#res.base, P2Thread1of1ForFork0_#t~ite43, ~a$r_buff1_thd3~0, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 17:27:54,233 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [879] [879] L782-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= |v_P1Thread1of1ForFork2_#t~ite14_42| v_~a$r_buff1_thd2~0_99) (= (+ v_~__unbuffered_cnt~0_83 1) v_~__unbuffered_cnt~0_82)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_83, P1Thread1of1ForFork2_#t~ite14=|v_P1Thread1of1ForFork2_#t~ite14_42|} OutVars{P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_99, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_82, P1Thread1of1ForFork2_#t~ite14=|v_P1Thread1of1ForFork2_#t~ite14_41|, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#res.offset, ~a$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#t~ite14, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-12-07 17:27:54,233 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [799] [799] L841-1-->L847: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_9 256))) (= v_~main$tmp_guard0~0_9 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_36) 1 0)) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_36} OutVars{ULTIMATE.start_main_#t~nondet46=|v_ULTIMATE.start_main_#t~nondet46_7|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_36, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_9} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet46, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 17:27:54,233 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [832] [832] L847-2-->L847-4: Formula: (let ((.cse0 (= 0 (mod ~a$w_buff1_used~0_In139527943 256))) (.cse1 (= 0 (mod ~a$r_buff1_thd0~0_In139527943 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite47_Out139527943| ~a$w_buff1~0_In139527943) (not .cse1)) (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite47_Out139527943| ~a~0_In139527943)))) InVars {~a~0=~a~0_In139527943, ~a$w_buff1~0=~a$w_buff1~0_In139527943, ~a$r_buff1_thd0~0=~a$r_buff1_thd0~0_In139527943, ~a$w_buff1_used~0=~a$w_buff1_used~0_In139527943} OutVars{~a~0=~a~0_In139527943, ~a$w_buff1~0=~a$w_buff1~0_In139527943, ULTIMATE.start_main_#t~ite47=|ULTIMATE.start_main_#t~ite47_Out139527943|, ~a$r_buff1_thd0~0=~a$r_buff1_thd0~0_In139527943, ~a$w_buff1_used~0=~a$w_buff1_used~0_In139527943} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47] because there is no mapped edge [2019-12-07 17:27:54,233 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [796] [796] L847-4-->L848: Formula: (= v_~a~0_44 |v_ULTIMATE.start_main_#t~ite47_19|) InVars {ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_19|} OutVars{~a~0=v_~a~0_44, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_18|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_16|} AuxVars[] AssignedVars[~a~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 17:27:54,233 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [826] [826] L848-->L848-2: Formula: (let ((.cse1 (= (mod ~a$r_buff0_thd0~0_In478269014 256) 0)) (.cse0 (= 0 (mod ~a$w_buff0_used~0_In478269014 256)))) (or (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite49_Out478269014| 0)) (and (or .cse1 .cse0) (= |ULTIMATE.start_main_#t~ite49_Out478269014| ~a$w_buff0_used~0_In478269014)))) InVars {~a$w_buff0_used~0=~a$w_buff0_used~0_In478269014, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In478269014} OutVars{~a$w_buff0_used~0=~a$w_buff0_used~0_In478269014, ULTIMATE.start_main_#t~ite49=|ULTIMATE.start_main_#t~ite49_Out478269014|, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In478269014} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite49] because there is no mapped edge [2019-12-07 17:27:54,234 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [831] [831] L849-->L849-2: Formula: (let ((.cse1 (= 0 (mod ~a$w_buff0_used~0_In-1332291971 256))) (.cse0 (= 0 (mod ~a$r_buff0_thd0~0_In-1332291971 256))) (.cse3 (= 0 (mod ~a$w_buff1_used~0_In-1332291971 256))) (.cse2 (= 0 (mod ~a$r_buff1_thd0~0_In-1332291971 256)))) (or (and (= |ULTIMATE.start_main_#t~ite50_Out-1332291971| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (or .cse3 .cse2) (= |ULTIMATE.start_main_#t~ite50_Out-1332291971| ~a$w_buff1_used~0_In-1332291971)))) InVars {~a$r_buff1_thd0~0=~a$r_buff1_thd0~0_In-1332291971, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1332291971, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In-1332291971, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1332291971} OutVars{ULTIMATE.start_main_#t~ite50=|ULTIMATE.start_main_#t~ite50_Out-1332291971|, ~a$r_buff1_thd0~0=~a$r_buff1_thd0~0_In-1332291971, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1332291971, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In-1332291971, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1332291971} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite50] because there is no mapped edge [2019-12-07 17:27:54,234 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [830] [830] L850-->L850-2: Formula: (let ((.cse0 (= (mod ~a$w_buff0_used~0_In-202766565 256) 0)) (.cse1 (= (mod ~a$r_buff0_thd0~0_In-202766565 256) 0))) (or (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite51_Out-202766565| 0)) (and (or .cse0 .cse1) (= ~a$r_buff0_thd0~0_In-202766565 |ULTIMATE.start_main_#t~ite51_Out-202766565|)))) InVars {~a$w_buff0_used~0=~a$w_buff0_used~0_In-202766565, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In-202766565} OutVars{ULTIMATE.start_main_#t~ite51=|ULTIMATE.start_main_#t~ite51_Out-202766565|, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-202766565, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In-202766565} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite51] because there is no mapped edge [2019-12-07 17:27:54,234 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [841] [841] L851-->L851-2: Formula: (let ((.cse3 (= (mod ~a$r_buff0_thd0~0_In976259507 256) 0)) (.cse2 (= 0 (mod ~a$w_buff0_used~0_In976259507 256))) (.cse1 (= 0 (mod ~a$r_buff1_thd0~0_In976259507 256))) (.cse0 (= 0 (mod ~a$w_buff1_used~0_In976259507 256)))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite52_Out976259507| ~a$r_buff1_thd0~0_In976259507) (or .cse2 .cse3)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0))) (= |ULTIMATE.start_main_#t~ite52_Out976259507| 0)))) InVars {~a$r_buff1_thd0~0=~a$r_buff1_thd0~0_In976259507, ~a$w_buff0_used~0=~a$w_buff0_used~0_In976259507, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In976259507, ~a$w_buff1_used~0=~a$w_buff1_used~0_In976259507} OutVars{ULTIMATE.start_main_#t~ite52=|ULTIMATE.start_main_#t~ite52_Out976259507|, ~a$r_buff1_thd0~0=~a$r_buff1_thd0~0_In976259507, ~a$w_buff0_used~0=~a$w_buff0_used~0_In976259507, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In976259507, ~a$w_buff1_used~0=~a$w_buff1_used~0_In976259507} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52] because there is no mapped edge [2019-12-07 17:27:54,235 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [899] [899] L851-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_~a$r_buff1_thd0~0_125 |v_ULTIMATE.start_main_#t~ite52_55|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_22 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_16|) (= (mod v_~main$tmp_guard1~0_29 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_16|) (= v_~main$tmp_guard1~0_29 (ite (= (ite (not (and (= v_~__unbuffered_p2_EBX~0_29 0) (= 0 v_~__unbuffered_p1_EAX~0_28) (= 1 v_~__unbuffered_p2_EAX~0_26) (= v_~__unbuffered_p0_EBX~0_85 0) (= 1 v_~__unbuffered_p0_EAX~0_85))) 1 0) 0) 0 1)) (= v_ULTIMATE.start___VERIFIER_assert_~expression_22 0)) InVars {~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_85, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_55|, ~__unbuffered_p0_EBX~0=v_~__unbuffered_p0_EBX~0_85, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_29, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_28, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_26} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_85, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_54|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_22, ~__unbuffered_p0_EBX~0=v_~__unbuffered_p0_EBX~0_85, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_29, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_28, ~a$r_buff1_thd0~0=v_~a$r_buff1_thd0~0_125, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_29, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_26, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_16|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start___VERIFIER_assert_~expression, ~a$r_buff1_thd0~0, ~main$tmp_guard1~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 17:27:54,285 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_54fef296-034f-44e2-bf8e-ffda9e4a5496/bin/uautomizer/witness.graphml [2019-12-07 17:27:54,285 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 17:27:54,286 INFO L168 Benchmark]: Toolchain (without parser) took 109840.30 ms. Allocated memory was 1.0 GB in the beginning and 6.6 GB in the end (delta: 5.5 GB). Free memory was 940.8 MB in the beginning and 3.8 GB in the end (delta: -2.8 GB). Peak memory consumption was 2.7 GB. Max. memory is 11.5 GB. [2019-12-07 17:27:54,286 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 960.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 17:27:54,287 INFO L168 Benchmark]: CACSL2BoogieTranslator took 389.45 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 103.3 MB). Free memory was 940.8 MB in the beginning and 1.1 GB in the end (delta: -130.1 MB). Peak memory consumption was 18.6 MB. Max. memory is 11.5 GB. [2019-12-07 17:27:54,287 INFO L168 Benchmark]: Boogie Procedure Inliner took 39.55 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 17:27:54,287 INFO L168 Benchmark]: Boogie Preprocessor took 27.04 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 17:27:54,287 INFO L168 Benchmark]: RCFGBuilder took 413.80 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 62.7 MB). Peak memory consumption was 62.7 MB. Max. memory is 11.5 GB. [2019-12-07 17:27:54,288 INFO L168 Benchmark]: TraceAbstraction took 108901.57 ms. Allocated memory was 1.1 GB in the beginning and 6.6 GB in the end (delta: 5.4 GB). Free memory was 1.0 GB in the beginning and 3.8 GB in the end (delta: -2.8 GB). Peak memory consumption was 2.6 GB. Max. memory is 11.5 GB. [2019-12-07 17:27:54,288 INFO L168 Benchmark]: Witness Printer took 65.41 ms. Allocated memory is still 6.6 GB. Free memory was 3.8 GB in the beginning and 3.8 GB in the end (delta: 20.7 MB). Peak memory consumption was 20.7 MB. Max. memory is 11.5 GB. [2019-12-07 17:27:54,289 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 960.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 389.45 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 103.3 MB). Free memory was 940.8 MB in the beginning and 1.1 GB in the end (delta: -130.1 MB). Peak memory consumption was 18.6 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 39.55 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 27.04 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 413.80 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 62.7 MB). Peak memory consumption was 62.7 MB. Max. memory is 11.5 GB. * TraceAbstraction took 108901.57 ms. Allocated memory was 1.1 GB in the beginning and 6.6 GB in the end (delta: 5.4 GB). Free memory was 1.0 GB in the beginning and 3.8 GB in the end (delta: -2.8 GB). Peak memory consumption was 2.6 GB. Max. memory is 11.5 GB. * Witness Printer took 65.41 ms. Allocated memory is still 6.6 GB. Free memory was 3.8 GB in the beginning and 3.8 GB in the end (delta: 20.7 MB). Peak memory consumption was 20.7 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.3s, 179 ProgramPointsBefore, 94 ProgramPointsAfterwards, 216 TransitionsBefore, 102 TransitionsAfterwards, 19004 CoEnabledTransitionPairs, 7 FixpointIterations, 36 TrivialSequentialCompositions, 48 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 32 ConcurrentYvCompositions, 33 ChoiceCompositions, 7151 VarBasedMoverChecksPositive, 221 VarBasedMoverChecksNegative, 29 SemBasedMoverChecksPositive, 258 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.8s, 0 MoverChecksTotal, 80759 CheckedPairsTotal, 116 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L837] FCALL, FORK 0 pthread_create(&t397, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff0_thd3=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$r_buff1_thd3=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0] [L839] FCALL, FORK 0 pthread_create(&t398, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff0_thd3=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$r_buff1_thd3=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0] [L841] FCALL, FORK 0 pthread_create(&t399, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff0_thd3=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$r_buff1_thd3=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0] [L737] 1 a$w_buff1 = a$w_buff0 [L738] 1 a$w_buff0 = 1 [L739] 1 a$w_buff1_used = a$w_buff0_used [L740] 1 a$w_buff0_used = (_Bool)1 [L758] EXPR 1 a$w_buff0_used && a$r_buff0_thd1 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd1 ? a$w_buff1 : a) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff0_thd3=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$r_buff1_thd3=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0] [L772] 2 y = 1 [L775] 2 __unbuffered_p1_EAX = z VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff0_thd3=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$r_buff1_thd3=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=0] [L778] 2 a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd2 ? a$w_buff1 : a) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff0_thd3=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$r_buff1_thd3=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=0] [L792] 3 z = 1 [L795] 3 __unbuffered_p2_EAX = z [L798] 3 weak$$choice0 = __VERIFIER_nondet_bool() [L799] 3 weak$$choice2 = __VERIFIER_nondet_bool() [L800] 3 a$flush_delayed = weak$$choice2 [L801] 3 a$mem_tmp = a VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff0_thd3=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$r_buff1_thd3=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=1] [L802] EXPR 3 !a$w_buff0_used || !a$r_buff0_thd3 && !a$w_buff1_used || !a$r_buff0_thd3 && !a$r_buff1_thd3 ? a : (a$w_buff0_used && a$r_buff0_thd3 ? a$w_buff0 : a$w_buff1) VAL [!a$w_buff0_used || !a$r_buff0_thd3 && !a$w_buff1_used || !a$r_buff0_thd3 && !a$r_buff1_thd3 ? a : (a$w_buff0_used && a$r_buff0_thd3 ? a$w_buff0 : a$w_buff1)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff0_thd3=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$r_buff1_thd3=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=1] [L758] 1 a = a$w_buff0_used && a$r_buff0_thd1 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd1 ? a$w_buff1 : a) [L759] 1 a$w_buff0_used = a$w_buff0_used && a$r_buff0_thd1 ? (_Bool)0 : a$w_buff0_used [L760] 1 a$w_buff1_used = a$w_buff0_used && a$r_buff0_thd1 || a$w_buff1_used && a$r_buff1_thd1 ? (_Bool)0 : a$w_buff1_used [L802] 3 a = !a$w_buff0_used || !a$r_buff0_thd3 && !a$w_buff1_used || !a$r_buff0_thd3 && !a$r_buff1_thd3 ? a : (a$w_buff0_used && a$r_buff0_thd3 ? a$w_buff0 : a$w_buff1) [L803] 3 a$w_buff0 = weak$$choice2 ? a$w_buff0 : (!a$w_buff0_used || !a$r_buff0_thd3 && !a$w_buff1_used || !a$r_buff0_thd3 && !a$r_buff1_thd3 ? a$w_buff0 : (a$w_buff0_used && a$r_buff0_thd3 ? a$w_buff0 : a$w_buff0)) [L804] 3 a$w_buff1 = weak$$choice2 ? a$w_buff1 : (!a$w_buff0_used || !a$r_buff0_thd3 && !a$w_buff1_used || !a$r_buff0_thd3 && !a$r_buff1_thd3 ? a$w_buff1 : (a$w_buff0_used && a$r_buff0_thd3 ? a$w_buff1 : a$w_buff1)) [L805] 3 a$w_buff0_used = weak$$choice2 ? a$w_buff0_used : (!a$w_buff0_used || !a$r_buff0_thd3 && !a$w_buff1_used || !a$r_buff0_thd3 && !a$r_buff1_thd3 ? a$w_buff0_used : (a$w_buff0_used && a$r_buff0_thd3 ? (_Bool)0 : a$w_buff0_used)) [L806] EXPR 3 weak$$choice2 ? a$w_buff1_used : (!a$w_buff0_used || !a$r_buff0_thd3 && !a$w_buff1_used || !a$r_buff0_thd3 && !a$r_buff1_thd3 ? a$w_buff1_used : (a$w_buff0_used && a$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff0_thd3=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$r_buff1_thd3=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, weak$$choice2 ? a$w_buff1_used : (!a$w_buff0_used || !a$r_buff0_thd3 && !a$w_buff1_used || !a$r_buff0_thd3 && !a$r_buff1_thd3 ? a$w_buff1_used : (a$w_buff0_used && a$r_buff0_thd3 ? (_Bool)0 : (_Bool)0))=0, x=1, y=1, z=1] [L806] 3 a$w_buff1_used = weak$$choice2 ? a$w_buff1_used : (!a$w_buff0_used || !a$r_buff0_thd3 && !a$w_buff1_used || !a$r_buff0_thd3 && !a$r_buff1_thd3 ? a$w_buff1_used : (a$w_buff0_used && a$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) [L808] EXPR 3 weak$$choice2 ? a$r_buff1_thd3 : (!a$w_buff0_used || !a$r_buff0_thd3 && !a$w_buff1_used || !a$r_buff0_thd3 && !a$r_buff1_thd3 ? a$r_buff1_thd3 : (a$w_buff0_used && a$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff0_thd3=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$r_buff1_thd3=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, weak$$choice2 ? a$r_buff1_thd3 : (!a$w_buff0_used || !a$r_buff0_thd3 && !a$w_buff1_used || !a$r_buff0_thd3 && !a$r_buff1_thd3 ? a$r_buff1_thd3 : (a$w_buff0_used && a$r_buff0_thd3 ? (_Bool)0 : (_Bool)0))=0, x=1, y=1, z=1] [L808] 3 a$r_buff1_thd3 = weak$$choice2 ? a$r_buff1_thd3 : (!a$w_buff0_used || !a$r_buff0_thd3 && !a$w_buff1_used || !a$r_buff0_thd3 && !a$r_buff1_thd3 ? a$r_buff1_thd3 : (a$w_buff0_used && a$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) [L809] 3 __unbuffered_p2_EBX = a VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff0_thd3=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$r_buff1_thd3=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=1] [L814] 3 a$w_buff0_used && a$r_buff0_thd3 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd3 ? a$w_buff1 : a) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff0_thd3=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$r_buff1_thd3=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=1] [L815] 3 a$w_buff0_used = a$w_buff0_used && a$r_buff0_thd3 ? (_Bool)0 : a$w_buff0_used [L816] 3 a$w_buff1_used = a$w_buff0_used && a$r_buff0_thd3 || a$w_buff1_used && a$r_buff1_thd3 ? (_Bool)0 : a$w_buff1_used [L817] 3 a$r_buff0_thd3 = a$w_buff0_used && a$r_buff0_thd3 ? (_Bool)0 : a$r_buff0_thd3 [L779] 2 a$w_buff0_used = a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$w_buff0_used [L780] 2 a$w_buff1_used = a$w_buff0_used && a$r_buff0_thd2 || a$w_buff1_used && a$r_buff1_thd2 ? (_Bool)0 : a$w_buff1_used [L781] 2 a$r_buff0_thd2 = a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$r_buff0_thd2 [L847] 0 a$w_buff0_used && a$r_buff0_thd0 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd0 ? a$w_buff1 : a) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff0_thd3=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$r_buff1_thd3=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=1] [L848] 0 a$w_buff0_used = a$w_buff0_used && a$r_buff0_thd0 ? (_Bool)0 : a$w_buff0_used [L849] 0 a$w_buff1_used = a$w_buff0_used && a$r_buff0_thd0 || a$w_buff1_used && a$r_buff1_thd0 ? (_Bool)0 : a$w_buff1_used [L850] 0 a$r_buff0_thd0 = a$w_buff0_used && a$r_buff0_thd0 ? (_Bool)0 : a$r_buff0_thd0 - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 170 locations, 2 error locations. Result: UNSAFE, OverallTime: 108.7s, OverallIterations: 49, TraceHistogramMax: 1, AutomataDifference: 46.3s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 11358 SDtfs, 18758 SDslu, 41009 SDs, 0 SdLazy, 37065 SolverSat, 1291 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 23.8s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 916 GetRequests, 117 SyntacticMatches, 46 SemanticMatches, 753 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5562 ImplicationChecksByTransitivity, 10.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=156295occurred in iteration=2, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 38.0s AutomataMinimizationTime, 48 MinimizatonAttempts, 453258 StatesRemovedByMinimization, 43 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.4s SatisfiabilityAnalysisTime, 4.5s InterpolantComputationTime, 2373 NumberOfCodeBlocks, 2373 NumberOfCodeBlocksAsserted, 49 NumberOfCheckSat, 2258 ConstructedInterpolants, 0 QuantifiedInterpolants, 1147815 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 48 InterpolantComputations, 48 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...