./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/mix015_tso.oepc.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_19f73177-67ff-40c3-8153-5de86a4e2c20/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_19f73177-67ff-40c3-8153-5de86a4e2c20/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_19f73177-67ff-40c3-8153-5de86a4e2c20/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_19f73177-67ff-40c3-8153-5de86a4e2c20/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/mix015_tso.oepc.i -s /tmp/vcloud-vcloud-master/worker/run_dir_19f73177-67ff-40c3-8153-5de86a4e2c20/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_19f73177-67ff-40c3-8153-5de86a4e2c20/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ceb9e9320cf1a16017a1b06564d05ef37577775e ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 13:47:07,833 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 13:47:07,834 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 13:47:07,842 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 13:47:07,842 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 13:47:07,843 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 13:47:07,844 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 13:47:07,845 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 13:47:07,847 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 13:47:07,847 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 13:47:07,848 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 13:47:07,849 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 13:47:07,849 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 13:47:07,850 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 13:47:07,850 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 13:47:07,851 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 13:47:07,852 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 13:47:07,852 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 13:47:07,854 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 13:47:07,856 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 13:47:07,857 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 13:47:07,858 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 13:47:07,858 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 13:47:07,859 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 13:47:07,861 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 13:47:07,861 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 13:47:07,861 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 13:47:07,862 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 13:47:07,862 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 13:47:07,863 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 13:47:07,863 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 13:47:07,863 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 13:47:07,864 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 13:47:07,864 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 13:47:07,865 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 13:47:07,865 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 13:47:07,865 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 13:47:07,865 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 13:47:07,866 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 13:47:07,866 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 13:47:07,866 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 13:47:07,867 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_19f73177-67ff-40c3-8153-5de86a4e2c20/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 13:47:07,876 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 13:47:07,877 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 13:47:07,877 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 13:47:07,877 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 13:47:07,878 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 13:47:07,878 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 13:47:07,878 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 13:47:07,878 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 13:47:07,878 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 13:47:07,878 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 13:47:07,878 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 13:47:07,879 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 13:47:07,879 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 13:47:07,879 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 13:47:07,879 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 13:47:07,879 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 13:47:07,879 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 13:47:07,879 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 13:47:07,879 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 13:47:07,880 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 13:47:07,880 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 13:47:07,880 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 13:47:07,880 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 13:47:07,880 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 13:47:07,880 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 13:47:07,880 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 13:47:07,881 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 13:47:07,881 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 13:47:07,881 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 13:47:07,881 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_19f73177-67ff-40c3-8153-5de86a4e2c20/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ceb9e9320cf1a16017a1b06564d05ef37577775e [2019-12-07 13:47:07,980 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 13:47:07,990 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 13:47:07,993 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 13:47:07,994 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 13:47:07,995 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 13:47:07,995 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_19f73177-67ff-40c3-8153-5de86a4e2c20/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/mix015_tso.oepc.i [2019-12-07 13:47:08,045 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_19f73177-67ff-40c3-8153-5de86a4e2c20/bin/uautomizer/data/6a9fc1d1b/fe2c609bd9cf410093dfe319518d616c/FLAGe7c864ae8 [2019-12-07 13:47:08,428 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 13:47:08,428 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_19f73177-67ff-40c3-8153-5de86a4e2c20/sv-benchmarks/c/pthread-wmm/mix015_tso.oepc.i [2019-12-07 13:47:08,438 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_19f73177-67ff-40c3-8153-5de86a4e2c20/bin/uautomizer/data/6a9fc1d1b/fe2c609bd9cf410093dfe319518d616c/FLAGe7c864ae8 [2019-12-07 13:47:08,805 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_19f73177-67ff-40c3-8153-5de86a4e2c20/bin/uautomizer/data/6a9fc1d1b/fe2c609bd9cf410093dfe319518d616c [2019-12-07 13:47:08,807 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 13:47:08,808 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 13:47:08,808 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 13:47:08,809 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 13:47:08,812 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 13:47:08,813 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 01:47:08" (1/1) ... [2019-12-07 13:47:08,815 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@296938c1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:47:08, skipping insertion in model container [2019-12-07 13:47:08,815 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 01:47:08" (1/1) ... [2019-12-07 13:47:08,822 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 13:47:08,855 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 13:47:09,105 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 13:47:09,113 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 13:47:09,155 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 13:47:09,198 INFO L208 MainTranslator]: Completed translation [2019-12-07 13:47:09,199 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:47:09 WrapperNode [2019-12-07 13:47:09,199 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 13:47:09,199 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 13:47:09,199 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 13:47:09,199 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 13:47:09,205 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:47:09" (1/1) ... [2019-12-07 13:47:09,217 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:47:09" (1/1) ... [2019-12-07 13:47:09,235 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 13:47:09,235 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 13:47:09,236 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 13:47:09,236 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 13:47:09,242 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:47:09" (1/1) ... [2019-12-07 13:47:09,242 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:47:09" (1/1) ... [2019-12-07 13:47:09,245 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:47:09" (1/1) ... [2019-12-07 13:47:09,245 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:47:09" (1/1) ... [2019-12-07 13:47:09,252 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:47:09" (1/1) ... [2019-12-07 13:47:09,255 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:47:09" (1/1) ... [2019-12-07 13:47:09,257 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:47:09" (1/1) ... [2019-12-07 13:47:09,260 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 13:47:09,261 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 13:47:09,261 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 13:47:09,261 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 13:47:09,261 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:47:09" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_19f73177-67ff-40c3-8153-5de86a4e2c20/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 13:47:09,306 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 13:47:09,306 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 13:47:09,306 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 13:47:09,306 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 13:47:09,306 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 13:47:09,307 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 13:47:09,307 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 13:47:09,307 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 13:47:09,307 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 13:47:09,307 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 13:47:09,307 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 13:47:09,307 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 13:47:09,307 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 13:47:09,309 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 13:47:09,675 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 13:47:09,675 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 13:47:09,676 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 01:47:09 BoogieIcfgContainer [2019-12-07 13:47:09,676 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 13:47:09,677 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 13:47:09,677 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 13:47:09,679 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 13:47:09,679 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 01:47:08" (1/3) ... [2019-12-07 13:47:09,679 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7c433280 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 01:47:09, skipping insertion in model container [2019-12-07 13:47:09,680 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 01:47:09" (2/3) ... [2019-12-07 13:47:09,680 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7c433280 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 01:47:09, skipping insertion in model container [2019-12-07 13:47:09,680 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 01:47:09" (3/3) ... [2019-12-07 13:47:09,681 INFO L109 eAbstractionObserver]: Analyzing ICFG mix015_tso.oepc.i [2019-12-07 13:47:09,688 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 13:47:09,688 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 13:47:09,693 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 13:47:09,694 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 13:47:09,724 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,724 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,724 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,724 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,724 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,724 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,725 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,725 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,725 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,725 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,726 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,726 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,726 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,726 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,726 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,726 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,727 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,727 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,727 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,727 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,727 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,728 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,728 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,728 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,728 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,728 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,728 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,729 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,729 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,729 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,729 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,729 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,730 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,730 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,730 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,730 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,731 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,731 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,731 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,731 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,731 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,731 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,732 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,732 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,732 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,732 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,733 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,733 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,733 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,733 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,733 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,733 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,734 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,734 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,734 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,734 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,734 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,734 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,735 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,735 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,735 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,735 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,735 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,735 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,736 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,737 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,737 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,737 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,737 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,737 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,737 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,737 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,738 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,738 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,738 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,738 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,738 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,738 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,739 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,739 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,739 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,739 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,739 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,739 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,740 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,740 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,740 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,740 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,740 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,741 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,741 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,741 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,741 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,741 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,741 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,741 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,742 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,742 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,742 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,742 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,742 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,743 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,743 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,743 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,743 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,743 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,743 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,744 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,744 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,744 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,744 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,744 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,744 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,745 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,745 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,745 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,745 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,745 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,745 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,745 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,746 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,746 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,746 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,746 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,746 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,746 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,747 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,747 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,747 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,747 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,747 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,747 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,747 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,748 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,748 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,748 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,748 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,748 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,748 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,749 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,749 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,749 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,749 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,749 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,749 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,750 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,750 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,750 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,750 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,750 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,750 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,750 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,751 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,751 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,751 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,751 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,751 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,751 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,751 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,752 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,752 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,752 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,752 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,752 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,752 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,753 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,753 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,753 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,753 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,753 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,753 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,753 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,754 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,754 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,754 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,754 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,754 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,754 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,755 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,755 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,755 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,755 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 13:47:09,771 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 13:47:09,784 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 13:47:09,784 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 13:47:09,784 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 13:47:09,784 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 13:47:09,784 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 13:47:09,784 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 13:47:09,784 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 13:47:09,785 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 13:47:09,795 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 179 places, 216 transitions [2019-12-07 13:47:09,796 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 179 places, 216 transitions [2019-12-07 13:47:09,861 INFO L134 PetriNetUnfolder]: 47/213 cut-off events. [2019-12-07 13:47:09,861 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 13:47:09,871 INFO L76 FinitePrefix]: Finished finitePrefix Result has 223 conditions, 213 events. 47/213 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 685 event pairs. 9/173 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 13:47:09,887 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 179 places, 216 transitions [2019-12-07 13:47:09,928 INFO L134 PetriNetUnfolder]: 47/213 cut-off events. [2019-12-07 13:47:09,928 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 13:47:09,936 INFO L76 FinitePrefix]: Finished finitePrefix Result has 223 conditions, 213 events. 47/213 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 685 event pairs. 9/173 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 13:47:09,952 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 19004 [2019-12-07 13:47:09,953 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 13:47:12,778 WARN L192 SmtUtils]: Spent 160.00 ms on a formula simplification. DAG size of input: 97 DAG size of output: 95 [2019-12-07 13:47:13,039 WARN L192 SmtUtils]: Spent 143.00 ms on a formula simplification. DAG size of input: 51 DAG size of output: 47 [2019-12-07 13:47:13,067 INFO L206 etLargeBlockEncoding]: Checked pairs total: 80759 [2019-12-07 13:47:13,067 INFO L214 etLargeBlockEncoding]: Total number of compositions: 116 [2019-12-07 13:47:13,070 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 94 places, 102 transitions [2019-12-07 13:47:28,003 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 118022 states. [2019-12-07 13:47:28,004 INFO L276 IsEmpty]: Start isEmpty. Operand 118022 states. [2019-12-07 13:47:28,008 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-12-07 13:47:28,008 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:47:28,009 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-12-07 13:47:28,009 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:47:28,013 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:47:28,013 INFO L82 PathProgramCache]: Analyzing trace with hash 922782, now seen corresponding path program 1 times [2019-12-07 13:47:28,018 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:47:28,018 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1704824240] [2019-12-07 13:47:28,019 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:47:28,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:47:28,164 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:47:28,165 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1704824240] [2019-12-07 13:47:28,165 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:47:28,166 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 13:47:28,166 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [402646722] [2019-12-07 13:47:28,170 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 13:47:28,170 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:47:28,179 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:47:28,179 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:47:28,181 INFO L87 Difference]: Start difference. First operand 118022 states. Second operand 3 states. [2019-12-07 13:47:29,024 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:47:29,024 INFO L93 Difference]: Finished difference Result 116858 states and 495582 transitions. [2019-12-07 13:47:29,025 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:47:29,026 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2019-12-07 13:47:29,026 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:47:29,516 INFO L225 Difference]: With dead ends: 116858 [2019-12-07 13:47:29,516 INFO L226 Difference]: Without dead ends: 110138 [2019-12-07 13:47:29,517 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:47:35,064 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110138 states. [2019-12-07 13:47:36,627 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110138 to 110138. [2019-12-07 13:47:36,628 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 110138 states. [2019-12-07 13:47:36,981 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110138 states to 110138 states and 466462 transitions. [2019-12-07 13:47:36,982 INFO L78 Accepts]: Start accepts. Automaton has 110138 states and 466462 transitions. Word has length 3 [2019-12-07 13:47:36,982 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:47:36,982 INFO L462 AbstractCegarLoop]: Abstraction has 110138 states and 466462 transitions. [2019-12-07 13:47:36,983 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 13:47:36,983 INFO L276 IsEmpty]: Start isEmpty. Operand 110138 states and 466462 transitions. [2019-12-07 13:47:36,985 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-12-07 13:47:36,985 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:47:36,985 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:47:36,985 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:47:36,986 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:47:36,986 INFO L82 PathProgramCache]: Analyzing trace with hash 228105342, now seen corresponding path program 1 times [2019-12-07 13:47:36,986 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:47:36,986 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2005384711] [2019-12-07 13:47:36,986 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:47:37,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:47:37,046 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:47:37,047 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2005384711] [2019-12-07 13:47:37,047 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:47:37,047 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 13:47:37,047 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1801018462] [2019-12-07 13:47:37,048 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 13:47:37,048 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:47:37,049 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 13:47:37,049 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 13:47:37,049 INFO L87 Difference]: Start difference. First operand 110138 states and 466462 transitions. Second operand 4 states. [2019-12-07 13:47:37,912 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:47:37,912 INFO L93 Difference]: Finished difference Result 170904 states and 695583 transitions. [2019-12-07 13:47:37,912 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 13:47:37,912 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-12-07 13:47:37,912 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:47:38,396 INFO L225 Difference]: With dead ends: 170904 [2019-12-07 13:47:38,396 INFO L226 Difference]: Without dead ends: 170855 [2019-12-07 13:47:38,397 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:47:45,986 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 170855 states. [2019-12-07 13:47:47,982 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 170855 to 156295. [2019-12-07 13:47:47,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 156295 states. [2019-12-07 13:47:48,649 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156295 states to 156295 states and 644009 transitions. [2019-12-07 13:47:48,650 INFO L78 Accepts]: Start accepts. Automaton has 156295 states and 644009 transitions. Word has length 11 [2019-12-07 13:47:48,650 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:47:48,650 INFO L462 AbstractCegarLoop]: Abstraction has 156295 states and 644009 transitions. [2019-12-07 13:47:48,650 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 13:47:48,650 INFO L276 IsEmpty]: Start isEmpty. Operand 156295 states and 644009 transitions. [2019-12-07 13:47:48,656 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 13:47:48,656 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:47:48,656 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:47:48,656 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:47:48,657 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:47:48,657 INFO L82 PathProgramCache]: Analyzing trace with hash 891607686, now seen corresponding path program 1 times [2019-12-07 13:47:48,657 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:47:48,657 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2088664872] [2019-12-07 13:47:48,657 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:47:48,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:47:48,694 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:47:48,695 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2088664872] [2019-12-07 13:47:48,695 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:47:48,695 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 13:47:48,695 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1324755891] [2019-12-07 13:47:48,695 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 13:47:48,695 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:47:48,695 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:47:48,695 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:47:48,695 INFO L87 Difference]: Start difference. First operand 156295 states and 644009 transitions. Second operand 3 states. [2019-12-07 13:47:48,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:47:48,791 INFO L93 Difference]: Finished difference Result 33673 states and 108735 transitions. [2019-12-07 13:47:48,791 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:47:48,791 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 13 [2019-12-07 13:47:48,792 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:47:48,842 INFO L225 Difference]: With dead ends: 33673 [2019-12-07 13:47:48,842 INFO L226 Difference]: Without dead ends: 33673 [2019-12-07 13:47:48,843 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:47:49,049 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33673 states. [2019-12-07 13:47:49,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33673 to 33673. [2019-12-07 13:47:49,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33673 states. [2019-12-07 13:47:49,418 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33673 states to 33673 states and 108735 transitions. [2019-12-07 13:47:49,419 INFO L78 Accepts]: Start accepts. Automaton has 33673 states and 108735 transitions. Word has length 13 [2019-12-07 13:47:49,419 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:47:49,419 INFO L462 AbstractCegarLoop]: Abstraction has 33673 states and 108735 transitions. [2019-12-07 13:47:49,419 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 13:47:49,419 INFO L276 IsEmpty]: Start isEmpty. Operand 33673 states and 108735 transitions. [2019-12-07 13:47:49,421 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2019-12-07 13:47:49,421 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:47:49,421 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:47:49,421 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:47:49,422 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:47:49,422 INFO L82 PathProgramCache]: Analyzing trace with hash -1993825600, now seen corresponding path program 1 times [2019-12-07 13:47:49,422 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:47:49,422 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [508653693] [2019-12-07 13:47:49,422 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:47:49,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:47:49,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:47:49,470 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [508653693] [2019-12-07 13:47:49,470 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:47:49,470 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 13:47:49,471 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1017820165] [2019-12-07 13:47:49,471 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 13:47:49,471 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:47:49,471 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 13:47:49,471 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 13:47:49,472 INFO L87 Difference]: Start difference. First operand 33673 states and 108735 transitions. Second operand 4 states. [2019-12-07 13:47:49,690 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:47:49,690 INFO L93 Difference]: Finished difference Result 42056 states and 135369 transitions. [2019-12-07 13:47:49,691 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 13:47:49,691 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2019-12-07 13:47:49,691 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:47:49,751 INFO L225 Difference]: With dead ends: 42056 [2019-12-07 13:47:49,751 INFO L226 Difference]: Without dead ends: 42056 [2019-12-07 13:47:49,752 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:47:49,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42056 states. [2019-12-07 13:47:50,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42056 to 37770. [2019-12-07 13:47:50,363 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37770 states. [2019-12-07 13:47:50,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37770 states to 37770 states and 121950 transitions. [2019-12-07 13:47:50,429 INFO L78 Accepts]: Start accepts. Automaton has 37770 states and 121950 transitions. Word has length 16 [2019-12-07 13:47:50,430 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:47:50,430 INFO L462 AbstractCegarLoop]: Abstraction has 37770 states and 121950 transitions. [2019-12-07 13:47:50,430 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 13:47:50,430 INFO L276 IsEmpty]: Start isEmpty. Operand 37770 states and 121950 transitions. [2019-12-07 13:47:50,436 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2019-12-07 13:47:50,436 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:47:50,436 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:47:50,436 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:47:50,437 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:47:50,437 INFO L82 PathProgramCache]: Analyzing trace with hash 674854723, now seen corresponding path program 1 times [2019-12-07 13:47:50,437 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:47:50,437 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [560370098] [2019-12-07 13:47:50,437 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:47:50,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:47:50,487 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:47:50,488 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [560370098] [2019-12-07 13:47:50,488 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:47:50,488 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:47:50,488 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [787563323] [2019-12-07 13:47:50,488 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 13:47:50,488 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:47:50,488 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 13:47:50,489 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:47:50,489 INFO L87 Difference]: Start difference. First operand 37770 states and 121950 transitions. Second operand 5 states. [2019-12-07 13:47:50,866 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:47:50,867 INFO L93 Difference]: Finished difference Result 48537 states and 154193 transitions. [2019-12-07 13:47:50,867 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 13:47:50,867 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 22 [2019-12-07 13:47:50,867 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:47:50,934 INFO L225 Difference]: With dead ends: 48537 [2019-12-07 13:47:50,934 INFO L226 Difference]: Without dead ends: 48530 [2019-12-07 13:47:50,934 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 13:47:51,177 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48530 states. [2019-12-07 13:47:51,881 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48530 to 37459. [2019-12-07 13:47:51,881 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37459 states. [2019-12-07 13:47:51,944 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37459 states to 37459 states and 120776 transitions. [2019-12-07 13:47:51,944 INFO L78 Accepts]: Start accepts. Automaton has 37459 states and 120776 transitions. Word has length 22 [2019-12-07 13:47:51,944 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:47:51,944 INFO L462 AbstractCegarLoop]: Abstraction has 37459 states and 120776 transitions. [2019-12-07 13:47:51,944 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 13:47:51,944 INFO L276 IsEmpty]: Start isEmpty. Operand 37459 states and 120776 transitions. [2019-12-07 13:47:51,954 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 13:47:51,954 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:47:51,954 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:47:51,954 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:47:51,954 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:47:51,954 INFO L82 PathProgramCache]: Analyzing trace with hash 332765886, now seen corresponding path program 1 times [2019-12-07 13:47:51,954 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:47:51,954 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1739579165] [2019-12-07 13:47:51,954 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:47:51,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:47:52,008 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:47:52,009 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1739579165] [2019-12-07 13:47:52,009 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:47:52,009 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:47:52,009 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [553721649] [2019-12-07 13:47:52,010 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 13:47:52,010 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:47:52,010 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 13:47:52,010 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:47:52,010 INFO L87 Difference]: Start difference. First operand 37459 states and 120776 transitions. Second operand 5 states. [2019-12-07 13:47:52,385 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:47:52,385 INFO L93 Difference]: Finished difference Result 51888 states and 163997 transitions. [2019-12-07 13:47:52,385 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 13:47:52,386 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 25 [2019-12-07 13:47:52,386 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:47:52,465 INFO L225 Difference]: With dead ends: 51888 [2019-12-07 13:47:52,465 INFO L226 Difference]: Without dead ends: 51875 [2019-12-07 13:47:52,465 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 13:47:52,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51875 states. [2019-12-07 13:47:53,192 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51875 to 43351. [2019-12-07 13:47:53,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 43351 states. [2019-12-07 13:47:53,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43351 states to 43351 states and 139193 transitions. [2019-12-07 13:47:53,268 INFO L78 Accepts]: Start accepts. Automaton has 43351 states and 139193 transitions. Word has length 25 [2019-12-07 13:47:53,269 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:47:53,269 INFO L462 AbstractCegarLoop]: Abstraction has 43351 states and 139193 transitions. [2019-12-07 13:47:53,269 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 13:47:53,269 INFO L276 IsEmpty]: Start isEmpty. Operand 43351 states and 139193 transitions. [2019-12-07 13:47:53,280 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 13:47:53,280 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:47:53,280 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:47:53,281 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:47:53,281 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:47:53,281 INFO L82 PathProgramCache]: Analyzing trace with hash 445555351, now seen corresponding path program 1 times [2019-12-07 13:47:53,281 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:47:53,281 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [682734597] [2019-12-07 13:47:53,281 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:47:53,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:47:53,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:47:53,314 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [682734597] [2019-12-07 13:47:53,314 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:47:53,314 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:47:53,314 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1245934896] [2019-12-07 13:47:53,315 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 13:47:53,315 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:47:53,315 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:47:53,315 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:47:53,315 INFO L87 Difference]: Start difference. First operand 43351 states and 139193 transitions. Second operand 3 states. [2019-12-07 13:47:53,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:47:53,509 INFO L93 Difference]: Finished difference Result 67737 states and 216583 transitions. [2019-12-07 13:47:53,509 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:47:53,509 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-12-07 13:47:53,509 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:47:53,614 INFO L225 Difference]: With dead ends: 67737 [2019-12-07 13:47:53,614 INFO L226 Difference]: Without dead ends: 67737 [2019-12-07 13:47:53,615 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:47:53,904 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67737 states. [2019-12-07 13:47:54,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67737 to 51736. [2019-12-07 13:47:54,523 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51736 states. [2019-12-07 13:47:54,622 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51736 states to 51736 states and 166463 transitions. [2019-12-07 13:47:54,622 INFO L78 Accepts]: Start accepts. Automaton has 51736 states and 166463 transitions. Word has length 27 [2019-12-07 13:47:54,622 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:47:54,622 INFO L462 AbstractCegarLoop]: Abstraction has 51736 states and 166463 transitions. [2019-12-07 13:47:54,622 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 13:47:54,623 INFO L276 IsEmpty]: Start isEmpty. Operand 51736 states and 166463 transitions. [2019-12-07 13:47:54,638 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 13:47:54,638 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:47:54,638 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:47:54,638 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:47:54,638 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:47:54,638 INFO L82 PathProgramCache]: Analyzing trace with hash 1217095067, now seen corresponding path program 1 times [2019-12-07 13:47:54,638 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:47:54,639 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1867082367] [2019-12-07 13:47:54,639 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:47:54,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:47:54,669 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:47:54,669 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1867082367] [2019-12-07 13:47:54,669 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:47:54,670 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:47:54,670 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [226195447] [2019-12-07 13:47:54,670 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 13:47:54,670 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:47:54,670 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:47:54,671 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:47:54,671 INFO L87 Difference]: Start difference. First operand 51736 states and 166463 transitions. Second operand 3 states. [2019-12-07 13:47:54,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:47:54,880 INFO L93 Difference]: Finished difference Result 67737 states and 213366 transitions. [2019-12-07 13:47:54,880 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:47:54,881 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-12-07 13:47:54,881 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:47:54,989 INFO L225 Difference]: With dead ends: 67737 [2019-12-07 13:47:54,989 INFO L226 Difference]: Without dead ends: 67737 [2019-12-07 13:47:54,989 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:47:55,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67737 states. [2019-12-07 13:47:55,999 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67737 to 51736. [2019-12-07 13:47:55,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51736 states. [2019-12-07 13:47:56,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51736 states to 51736 states and 163246 transitions. [2019-12-07 13:47:56,096 INFO L78 Accepts]: Start accepts. Automaton has 51736 states and 163246 transitions. Word has length 27 [2019-12-07 13:47:56,096 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:47:56,096 INFO L462 AbstractCegarLoop]: Abstraction has 51736 states and 163246 transitions. [2019-12-07 13:47:56,096 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 13:47:56,096 INFO L276 IsEmpty]: Start isEmpty. Operand 51736 states and 163246 transitions. [2019-12-07 13:47:56,111 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 13:47:56,111 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:47:56,112 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:47:56,112 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:47:56,112 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:47:56,112 INFO L82 PathProgramCache]: Analyzing trace with hash 1361870049, now seen corresponding path program 1 times [2019-12-07 13:47:56,112 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:47:56,112 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1184932302] [2019-12-07 13:47:56,112 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:47:56,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:47:56,159 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:47:56,159 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1184932302] [2019-12-07 13:47:56,159 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:47:56,159 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 13:47:56,159 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1740047564] [2019-12-07 13:47:56,160 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 13:47:56,160 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:47:56,160 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 13:47:56,160 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 13:47:56,160 INFO L87 Difference]: Start difference. First operand 51736 states and 163246 transitions. Second operand 6 states. [2019-12-07 13:47:56,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:47:56,726 INFO L93 Difference]: Finished difference Result 97116 states and 305877 transitions. [2019-12-07 13:47:56,726 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 13:47:56,726 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 27 [2019-12-07 13:47:56,726 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:47:56,871 INFO L225 Difference]: With dead ends: 97116 [2019-12-07 13:47:56,871 INFO L226 Difference]: Without dead ends: 97097 [2019-12-07 13:47:56,872 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=47, Unknown=0, NotChecked=0, Total=72 [2019-12-07 13:47:57,241 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97097 states. [2019-12-07 13:47:58,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97097 to 56317. [2019-12-07 13:47:58,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 56317 states. [2019-12-07 13:47:58,138 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56317 states to 56317 states and 177413 transitions. [2019-12-07 13:47:58,138 INFO L78 Accepts]: Start accepts. Automaton has 56317 states and 177413 transitions. Word has length 27 [2019-12-07 13:47:58,138 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:47:58,138 INFO L462 AbstractCegarLoop]: Abstraction has 56317 states and 177413 transitions. [2019-12-07 13:47:58,138 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 13:47:58,138 INFO L276 IsEmpty]: Start isEmpty. Operand 56317 states and 177413 transitions. [2019-12-07 13:47:58,157 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-12-07 13:47:58,157 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:47:58,157 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:47:58,157 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:47:58,157 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:47:58,157 INFO L82 PathProgramCache]: Analyzing trace with hash -2015671980, now seen corresponding path program 1 times [2019-12-07 13:47:58,157 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:47:58,157 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1337497391] [2019-12-07 13:47:58,157 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:47:58,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:47:58,213 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:47:58,213 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1337497391] [2019-12-07 13:47:58,213 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:47:58,213 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 13:47:58,214 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2024104828] [2019-12-07 13:47:58,214 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 13:47:58,214 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:47:58,214 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 13:47:58,214 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 13:47:58,214 INFO L87 Difference]: Start difference. First operand 56317 states and 177413 transitions. Second operand 6 states. [2019-12-07 13:47:58,800 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:47:58,800 INFO L93 Difference]: Finished difference Result 92170 states and 288131 transitions. [2019-12-07 13:47:58,801 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 13:47:58,801 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 28 [2019-12-07 13:47:58,801 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:47:58,937 INFO L225 Difference]: With dead ends: 92170 [2019-12-07 13:47:58,937 INFO L226 Difference]: Without dead ends: 92148 [2019-12-07 13:47:58,937 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=47, Unknown=0, NotChecked=0, Total=72 [2019-12-07 13:47:59,293 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92148 states. [2019-12-07 13:48:00,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92148 to 55804. [2019-12-07 13:48:00,152 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 55804 states. [2019-12-07 13:48:00,255 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55804 states to 55804 states and 175723 transitions. [2019-12-07 13:48:00,255 INFO L78 Accepts]: Start accepts. Automaton has 55804 states and 175723 transitions. Word has length 28 [2019-12-07 13:48:00,255 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:48:00,255 INFO L462 AbstractCegarLoop]: Abstraction has 55804 states and 175723 transitions. [2019-12-07 13:48:00,255 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 13:48:00,255 INFO L276 IsEmpty]: Start isEmpty. Operand 55804 states and 175723 transitions. [2019-12-07 13:48:00,273 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-12-07 13:48:00,274 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:48:00,274 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:48:00,274 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:48:00,274 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:48:00,274 INFO L82 PathProgramCache]: Analyzing trace with hash -1692206128, now seen corresponding path program 1 times [2019-12-07 13:48:00,274 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:48:00,274 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1431801594] [2019-12-07 13:48:00,274 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:48:00,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:48:00,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:48:00,330 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1431801594] [2019-12-07 13:48:00,330 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:48:00,330 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 13:48:00,331 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [407828028] [2019-12-07 13:48:00,331 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 13:48:00,331 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:48:00,331 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 13:48:00,331 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:48:00,331 INFO L87 Difference]: Start difference. First operand 55804 states and 175723 transitions. Second operand 5 states. [2019-12-07 13:48:00,853 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:48:00,854 INFO L93 Difference]: Finished difference Result 77000 states and 239966 transitions. [2019-12-07 13:48:00,854 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 13:48:00,854 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 28 [2019-12-07 13:48:00,854 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:48:00,966 INFO L225 Difference]: With dead ends: 77000 [2019-12-07 13:48:00,967 INFO L226 Difference]: Without dead ends: 77000 [2019-12-07 13:48:00,967 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 13:48:01,291 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77000 states. [2019-12-07 13:48:02,053 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77000 to 67374. [2019-12-07 13:48:02,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 67374 states. [2019-12-07 13:48:02,181 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67374 states to 67374 states and 211767 transitions. [2019-12-07 13:48:02,181 INFO L78 Accepts]: Start accepts. Automaton has 67374 states and 211767 transitions. Word has length 28 [2019-12-07 13:48:02,181 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:48:02,181 INFO L462 AbstractCegarLoop]: Abstraction has 67374 states and 211767 transitions. [2019-12-07 13:48:02,181 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 13:48:02,181 INFO L276 IsEmpty]: Start isEmpty. Operand 67374 states and 211767 transitions. [2019-12-07 13:48:02,203 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-12-07 13:48:02,203 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:48:02,203 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:48:02,204 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:48:02,204 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:48:02,204 INFO L82 PathProgramCache]: Analyzing trace with hash 46100818, now seen corresponding path program 1 times [2019-12-07 13:48:02,204 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:48:02,204 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1030218476] [2019-12-07 13:48:02,204 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:48:02,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:48:02,232 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:48:02,232 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1030218476] [2019-12-07 13:48:02,233 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:48:02,233 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 13:48:02,233 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [53382588] [2019-12-07 13:48:02,233 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 13:48:02,233 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:48:02,233 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:48:02,233 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:48:02,233 INFO L87 Difference]: Start difference. First operand 67374 states and 211767 transitions. Second operand 3 states. [2019-12-07 13:48:02,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:48:02,408 INFO L93 Difference]: Finished difference Result 64907 states and 202241 transitions. [2019-12-07 13:48:02,408 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:48:02,409 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 29 [2019-12-07 13:48:02,409 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:48:02,499 INFO L225 Difference]: With dead ends: 64907 [2019-12-07 13:48:02,499 INFO L226 Difference]: Without dead ends: 64907 [2019-12-07 13:48:02,499 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:48:02,778 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64907 states. [2019-12-07 13:48:03,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64907 to 59183. [2019-12-07 13:48:03,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 59183 states. [2019-12-07 13:48:03,509 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59183 states to 59183 states and 184969 transitions. [2019-12-07 13:48:03,509 INFO L78 Accepts]: Start accepts. Automaton has 59183 states and 184969 transitions. Word has length 29 [2019-12-07 13:48:03,509 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:48:03,509 INFO L462 AbstractCegarLoop]: Abstraction has 59183 states and 184969 transitions. [2019-12-07 13:48:03,509 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 13:48:03,509 INFO L276 IsEmpty]: Start isEmpty. Operand 59183 states and 184969 transitions. [2019-12-07 13:48:03,528 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2019-12-07 13:48:03,528 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:48:03,528 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:48:03,529 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:48:03,529 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:48:03,529 INFO L82 PathProgramCache]: Analyzing trace with hash -238960576, now seen corresponding path program 1 times [2019-12-07 13:48:03,529 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:48:03,529 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [160185505] [2019-12-07 13:48:03,529 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:48:03,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:48:03,560 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:48:03,560 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [160185505] [2019-12-07 13:48:03,560 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:48:03,560 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:48:03,560 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1198835840] [2019-12-07 13:48:03,560 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 13:48:03,560 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:48:03,561 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 13:48:03,561 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 13:48:03,561 INFO L87 Difference]: Start difference. First operand 59183 states and 184969 transitions. Second operand 4 states. [2019-12-07 13:48:03,625 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:48:03,625 INFO L93 Difference]: Finished difference Result 23861 states and 71561 transitions. [2019-12-07 13:48:03,625 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 13:48:03,625 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 29 [2019-12-07 13:48:03,625 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:48:03,653 INFO L225 Difference]: With dead ends: 23861 [2019-12-07 13:48:03,653 INFO L226 Difference]: Without dead ends: 23861 [2019-12-07 13:48:03,653 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 13:48:03,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23861 states. [2019-12-07 13:48:04,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23861 to 22762. [2019-12-07 13:48:04,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22762 states. [2019-12-07 13:48:04,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22762 states to 22762 states and 68309 transitions. [2019-12-07 13:48:04,082 INFO L78 Accepts]: Start accepts. Automaton has 22762 states and 68309 transitions. Word has length 29 [2019-12-07 13:48:04,083 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:48:04,083 INFO L462 AbstractCegarLoop]: Abstraction has 22762 states and 68309 transitions. [2019-12-07 13:48:04,083 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 13:48:04,083 INFO L276 IsEmpty]: Start isEmpty. Operand 22762 states and 68309 transitions. [2019-12-07 13:48:04,099 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-12-07 13:48:04,100 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:48:04,100 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:48:04,100 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:48:04,100 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:48:04,100 INFO L82 PathProgramCache]: Analyzing trace with hash 405285854, now seen corresponding path program 1 times [2019-12-07 13:48:04,100 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:48:04,100 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1508762513] [2019-12-07 13:48:04,100 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:48:04,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:48:04,138 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:48:04,139 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1508762513] [2019-12-07 13:48:04,139 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:48:04,139 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:48:04,139 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [407494512] [2019-12-07 13:48:04,139 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 13:48:04,139 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:48:04,139 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 13:48:04,139 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:48:04,140 INFO L87 Difference]: Start difference. First operand 22762 states and 68309 transitions. Second operand 5 states. [2019-12-07 13:48:04,383 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:48:04,383 INFO L93 Difference]: Finished difference Result 25420 states and 75593 transitions. [2019-12-07 13:48:04,383 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 13:48:04,383 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 33 [2019-12-07 13:48:04,383 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:48:04,413 INFO L225 Difference]: With dead ends: 25420 [2019-12-07 13:48:04,413 INFO L226 Difference]: Without dead ends: 25420 [2019-12-07 13:48:04,413 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 13:48:04,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25420 states. [2019-12-07 13:48:04,721 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25420 to 22818. [2019-12-07 13:48:04,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22818 states. [2019-12-07 13:48:04,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22818 states to 22818 states and 68469 transitions. [2019-12-07 13:48:04,757 INFO L78 Accepts]: Start accepts. Automaton has 22818 states and 68469 transitions. Word has length 33 [2019-12-07 13:48:04,757 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:48:04,757 INFO L462 AbstractCegarLoop]: Abstraction has 22818 states and 68469 transitions. [2019-12-07 13:48:04,757 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 13:48:04,757 INFO L276 IsEmpty]: Start isEmpty. Operand 22818 states and 68469 transitions. [2019-12-07 13:48:04,774 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-12-07 13:48:04,774 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:48:04,774 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:48:04,774 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:48:04,774 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:48:04,774 INFO L82 PathProgramCache]: Analyzing trace with hash -1258895234, now seen corresponding path program 2 times [2019-12-07 13:48:04,774 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:48:04,775 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [406271404] [2019-12-07 13:48:04,775 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:48:04,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:48:04,845 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:48:04,845 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [406271404] [2019-12-07 13:48:04,845 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:48:04,845 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 13:48:04,845 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1928641083] [2019-12-07 13:48:04,845 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 13:48:04,845 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:48:04,845 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 13:48:04,846 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 13:48:04,846 INFO L87 Difference]: Start difference. First operand 22818 states and 68469 transitions. Second operand 7 states. [2019-12-07 13:48:05,629 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:48:05,629 INFO L93 Difference]: Finished difference Result 42045 states and 124974 transitions. [2019-12-07 13:48:05,630 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 13:48:05,630 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 33 [2019-12-07 13:48:05,630 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:48:05,678 INFO L225 Difference]: With dead ends: 42045 [2019-12-07 13:48:05,679 INFO L226 Difference]: Without dead ends: 42045 [2019-12-07 13:48:05,679 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 1 SyntacticMatches, 3 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 64 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=89, Invalid=253, Unknown=0, NotChecked=0, Total=342 [2019-12-07 13:48:05,810 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42045 states. [2019-12-07 13:48:06,113 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42045 to 23141. [2019-12-07 13:48:06,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23141 states. [2019-12-07 13:48:06,149 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23141 states to 23141 states and 69482 transitions. [2019-12-07 13:48:06,149 INFO L78 Accepts]: Start accepts. Automaton has 23141 states and 69482 transitions. Word has length 33 [2019-12-07 13:48:06,150 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:48:06,150 INFO L462 AbstractCegarLoop]: Abstraction has 23141 states and 69482 transitions. [2019-12-07 13:48:06,150 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 13:48:06,150 INFO L276 IsEmpty]: Start isEmpty. Operand 23141 states and 69482 transitions. [2019-12-07 13:48:06,165 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-12-07 13:48:06,166 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:48:06,166 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:48:06,166 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:48:06,166 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:48:06,166 INFO L82 PathProgramCache]: Analyzing trace with hash -454706214, now seen corresponding path program 3 times [2019-12-07 13:48:06,166 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:48:06,166 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2092297757] [2019-12-07 13:48:06,166 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:48:06,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:48:06,226 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:48:06,227 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2092297757] [2019-12-07 13:48:06,227 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:48:06,227 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 13:48:06,227 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1127554923] [2019-12-07 13:48:06,227 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 13:48:06,227 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:48:06,228 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 13:48:06,228 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2019-12-07 13:48:06,228 INFO L87 Difference]: Start difference. First operand 23141 states and 69482 transitions. Second operand 8 states. [2019-12-07 13:48:07,598 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:48:07,599 INFO L93 Difference]: Finished difference Result 50931 states and 149428 transitions. [2019-12-07 13:48:07,599 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2019-12-07 13:48:07,600 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 33 [2019-12-07 13:48:07,600 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:48:07,670 INFO L225 Difference]: With dead ends: 50931 [2019-12-07 13:48:07,670 INFO L226 Difference]: Without dead ends: 50931 [2019-12-07 13:48:07,671 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 154 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=161, Invalid=489, Unknown=0, NotChecked=0, Total=650 [2019-12-07 13:48:07,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50931 states. [2019-12-07 13:48:08,178 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50931 to 23016. [2019-12-07 13:48:08,178 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23016 states. [2019-12-07 13:48:08,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23016 states to 23016 states and 69097 transitions. [2019-12-07 13:48:08,217 INFO L78 Accepts]: Start accepts. Automaton has 23016 states and 69097 transitions. Word has length 33 [2019-12-07 13:48:08,217 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:48:08,218 INFO L462 AbstractCegarLoop]: Abstraction has 23016 states and 69097 transitions. [2019-12-07 13:48:08,218 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 13:48:08,218 INFO L276 IsEmpty]: Start isEmpty. Operand 23016 states and 69097 transitions. [2019-12-07 13:48:08,236 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 13:48:08,236 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:48:08,236 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:48:08,236 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:48:08,236 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:48:08,236 INFO L82 PathProgramCache]: Analyzing trace with hash -1655017129, now seen corresponding path program 1 times [2019-12-07 13:48:08,237 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:48:08,237 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1665106750] [2019-12-07 13:48:08,237 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:48:08,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:48:08,303 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:48:08,303 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1665106750] [2019-12-07 13:48:08,304 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:48:08,304 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 13:48:08,304 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [590566217] [2019-12-07 13:48:08,304 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 13:48:08,304 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:48:08,304 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 13:48:08,304 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 13:48:08,304 INFO L87 Difference]: Start difference. First operand 23016 states and 69097 transitions. Second operand 7 states. [2019-12-07 13:48:09,632 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:48:09,632 INFO L93 Difference]: Finished difference Result 38884 states and 115110 transitions. [2019-12-07 13:48:09,632 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 13:48:09,632 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 34 [2019-12-07 13:48:09,632 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:48:09,687 INFO L225 Difference]: With dead ends: 38884 [2019-12-07 13:48:09,687 INFO L226 Difference]: Without dead ends: 38884 [2019-12-07 13:48:09,687 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 61 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=89, Invalid=253, Unknown=0, NotChecked=0, Total=342 [2019-12-07 13:48:09,812 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38884 states. [2019-12-07 13:48:10,114 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38884 to 22737. [2019-12-07 13:48:10,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22737 states. [2019-12-07 13:48:10,150 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22737 states to 22737 states and 68261 transitions. [2019-12-07 13:48:10,150 INFO L78 Accepts]: Start accepts. Automaton has 22737 states and 68261 transitions. Word has length 34 [2019-12-07 13:48:10,150 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:48:10,150 INFO L462 AbstractCegarLoop]: Abstraction has 22737 states and 68261 transitions. [2019-12-07 13:48:10,151 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 13:48:10,151 INFO L276 IsEmpty]: Start isEmpty. Operand 22737 states and 68261 transitions. [2019-12-07 13:48:10,167 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 13:48:10,167 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:48:10,167 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:48:10,167 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:48:10,168 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:48:10,168 INFO L82 PathProgramCache]: Analyzing trace with hash 2107636055, now seen corresponding path program 2 times [2019-12-07 13:48:10,168 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:48:10,168 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1284053492] [2019-12-07 13:48:10,168 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:48:10,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:48:10,252 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:48:10,252 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1284053492] [2019-12-07 13:48:10,252 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:48:10,252 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 13:48:10,253 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1337780138] [2019-12-07 13:48:10,253 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-12-07 13:48:10,253 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:48:10,253 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 13:48:10,253 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2019-12-07 13:48:10,253 INFO L87 Difference]: Start difference. First operand 22737 states and 68261 transitions. Second operand 9 states. [2019-12-07 13:48:12,007 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:48:12,007 INFO L93 Difference]: Finished difference Result 42206 states and 124556 transitions. [2019-12-07 13:48:12,008 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-12-07 13:48:12,008 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 34 [2019-12-07 13:48:12,008 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:48:12,061 INFO L225 Difference]: With dead ends: 42206 [2019-12-07 13:48:12,061 INFO L226 Difference]: Without dead ends: 42206 [2019-12-07 13:48:12,062 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 105 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=129, Invalid=377, Unknown=0, NotChecked=0, Total=506 [2019-12-07 13:48:12,191 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42206 states. [2019-12-07 13:48:12,484 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42206 to 22505. [2019-12-07 13:48:12,484 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22505 states. [2019-12-07 13:48:12,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22505 states to 22505 states and 67597 transitions. [2019-12-07 13:48:12,521 INFO L78 Accepts]: Start accepts. Automaton has 22505 states and 67597 transitions. Word has length 34 [2019-12-07 13:48:12,522 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:48:12,522 INFO L462 AbstractCegarLoop]: Abstraction has 22505 states and 67597 transitions. [2019-12-07 13:48:12,522 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-12-07 13:48:12,522 INFO L276 IsEmpty]: Start isEmpty. Operand 22505 states and 67597 transitions. [2019-12-07 13:48:12,542 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2019-12-07 13:48:12,542 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:48:12,542 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:48:12,542 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:48:12,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:48:12,542 INFO L82 PathProgramCache]: Analyzing trace with hash -1063261264, now seen corresponding path program 1 times [2019-12-07 13:48:12,543 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:48:12,543 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1957283852] [2019-12-07 13:48:12,543 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:48:12,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:48:12,598 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:48:12,599 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1957283852] [2019-12-07 13:48:12,599 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:48:12,599 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 13:48:12,599 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1078501588] [2019-12-07 13:48:12,599 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 13:48:12,599 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:48:12,599 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 13:48:12,599 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 13:48:12,600 INFO L87 Difference]: Start difference. First operand 22505 states and 67597 transitions. Second operand 4 states. [2019-12-07 13:48:12,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:48:12,657 INFO L93 Difference]: Finished difference Result 22503 states and 67593 transitions. [2019-12-07 13:48:12,657 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 13:48:12,657 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 40 [2019-12-07 13:48:12,657 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:48:12,681 INFO L225 Difference]: With dead ends: 22503 [2019-12-07 13:48:12,682 INFO L226 Difference]: Without dead ends: 22503 [2019-12-07 13:48:12,682 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 13:48:12,768 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22503 states. [2019-12-07 13:48:12,956 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22503 to 22503. [2019-12-07 13:48:12,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22503 states. [2019-12-07 13:48:12,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22503 states to 22503 states and 67593 transitions. [2019-12-07 13:48:12,990 INFO L78 Accepts]: Start accepts. Automaton has 22503 states and 67593 transitions. Word has length 40 [2019-12-07 13:48:12,990 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:48:12,990 INFO L462 AbstractCegarLoop]: Abstraction has 22503 states and 67593 transitions. [2019-12-07 13:48:12,991 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 13:48:12,991 INFO L276 IsEmpty]: Start isEmpty. Operand 22503 states and 67593 transitions. [2019-12-07 13:48:13,011 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2019-12-07 13:48:13,011 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:48:13,011 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:48:13,011 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:48:13,011 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:48:13,011 INFO L82 PathProgramCache]: Analyzing trace with hash 1591146573, now seen corresponding path program 1 times [2019-12-07 13:48:13,012 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:48:13,012 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2105164908] [2019-12-07 13:48:13,012 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:48:13,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:48:13,056 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:48:13,056 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2105164908] [2019-12-07 13:48:13,056 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:48:13,056 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 13:48:13,056 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [632132418] [2019-12-07 13:48:13,057 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 13:48:13,057 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:48:13,057 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 13:48:13,057 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:48:13,057 INFO L87 Difference]: Start difference. First operand 22503 states and 67593 transitions. Second operand 5 states. [2019-12-07 13:48:13,124 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:48:13,125 INFO L93 Difference]: Finished difference Result 20948 states and 64234 transitions. [2019-12-07 13:48:13,125 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 13:48:13,125 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 41 [2019-12-07 13:48:13,125 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:48:13,150 INFO L225 Difference]: With dead ends: 20948 [2019-12-07 13:48:13,150 INFO L226 Difference]: Without dead ends: 20948 [2019-12-07 13:48:13,150 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:48:13,235 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20948 states. [2019-12-07 13:48:13,410 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20948 to 19488. [2019-12-07 13:48:13,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19488 states. [2019-12-07 13:48:13,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19488 states to 19488 states and 59983 transitions. [2019-12-07 13:48:13,439 INFO L78 Accepts]: Start accepts. Automaton has 19488 states and 59983 transitions. Word has length 41 [2019-12-07 13:48:13,439 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:48:13,439 INFO L462 AbstractCegarLoop]: Abstraction has 19488 states and 59983 transitions. [2019-12-07 13:48:13,439 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 13:48:13,439 INFO L276 IsEmpty]: Start isEmpty. Operand 19488 states and 59983 transitions. [2019-12-07 13:48:13,456 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 13:48:13,456 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:48:13,456 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:48:13,457 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:48:13,457 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:48:13,457 INFO L82 PathProgramCache]: Analyzing trace with hash -961209461, now seen corresponding path program 1 times [2019-12-07 13:48:13,457 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:48:13,457 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [790171544] [2019-12-07 13:48:13,457 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:48:13,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:48:13,493 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:48:13,494 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [790171544] [2019-12-07 13:48:13,494 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:48:13,494 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 13:48:13,494 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [122440063] [2019-12-07 13:48:13,494 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 13:48:13,494 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:48:13,494 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:48:13,494 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:48:13,494 INFO L87 Difference]: Start difference. First operand 19488 states and 59983 transitions. Second operand 3 states. [2019-12-07 13:48:13,578 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:48:13,578 INFO L93 Difference]: Finished difference Result 22941 states and 70714 transitions. [2019-12-07 13:48:13,579 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:48:13,579 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 65 [2019-12-07 13:48:13,579 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:48:13,604 INFO L225 Difference]: With dead ends: 22941 [2019-12-07 13:48:13,604 INFO L226 Difference]: Without dead ends: 22941 [2019-12-07 13:48:13,605 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:48:13,693 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22941 states. [2019-12-07 13:48:13,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22941 to 19107. [2019-12-07 13:48:13,883 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19107 states. [2019-12-07 13:48:13,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19107 states to 19107 states and 59183 transitions. [2019-12-07 13:48:13,914 INFO L78 Accepts]: Start accepts. Automaton has 19107 states and 59183 transitions. Word has length 65 [2019-12-07 13:48:13,914 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:48:13,914 INFO L462 AbstractCegarLoop]: Abstraction has 19107 states and 59183 transitions. [2019-12-07 13:48:13,914 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 13:48:13,914 INFO L276 IsEmpty]: Start isEmpty. Operand 19107 states and 59183 transitions. [2019-12-07 13:48:13,930 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 13:48:13,930 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:48:13,931 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:48:13,931 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:48:13,931 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:48:13,931 INFO L82 PathProgramCache]: Analyzing trace with hash -2050011334, now seen corresponding path program 1 times [2019-12-07 13:48:13,931 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:48:13,931 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [153660485] [2019-12-07 13:48:13,931 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:48:13,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:48:13,994 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:48:13,994 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [153660485] [2019-12-07 13:48:13,995 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:48:13,995 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 13:48:13,995 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1762621403] [2019-12-07 13:48:13,995 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 13:48:13,995 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:48:13,995 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 13:48:13,995 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 13:48:13,995 INFO L87 Difference]: Start difference. First operand 19107 states and 59183 transitions. Second operand 7 states. [2019-12-07 13:48:14,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:48:14,952 INFO L93 Difference]: Finished difference Result 33639 states and 101808 transitions. [2019-12-07 13:48:14,953 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2019-12-07 13:48:14,953 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 66 [2019-12-07 13:48:14,953 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:48:14,990 INFO L225 Difference]: With dead ends: 33639 [2019-12-07 13:48:14,990 INFO L226 Difference]: Without dead ends: 33639 [2019-12-07 13:48:14,990 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 13 SyntacticMatches, 1 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 42 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=81, Invalid=225, Unknown=0, NotChecked=0, Total=306 [2019-12-07 13:48:15,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33639 states. [2019-12-07 13:48:15,342 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33639 to 18773. [2019-12-07 13:48:15,343 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18773 states. [2019-12-07 13:48:15,374 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18773 states to 18773 states and 58430 transitions. [2019-12-07 13:48:15,374 INFO L78 Accepts]: Start accepts. Automaton has 18773 states and 58430 transitions. Word has length 66 [2019-12-07 13:48:15,374 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:48:15,375 INFO L462 AbstractCegarLoop]: Abstraction has 18773 states and 58430 transitions. [2019-12-07 13:48:15,375 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 13:48:15,375 INFO L276 IsEmpty]: Start isEmpty. Operand 18773 states and 58430 transitions. [2019-12-07 13:48:15,392 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 13:48:15,392 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:48:15,392 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:48:15,392 INFO L410 AbstractCegarLoop]: === Iteration 23 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:48:15,392 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:48:15,393 INFO L82 PathProgramCache]: Analyzing trace with hash -1986512930, now seen corresponding path program 1 times [2019-12-07 13:48:15,393 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:48:15,393 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1767611732] [2019-12-07 13:48:15,393 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:48:15,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:48:15,440 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:48:15,440 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1767611732] [2019-12-07 13:48:15,441 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:48:15,441 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 13:48:15,441 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1220689143] [2019-12-07 13:48:15,441 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 13:48:15,441 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:48:15,441 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 13:48:15,442 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 13:48:15,442 INFO L87 Difference]: Start difference. First operand 18773 states and 58430 transitions. Second operand 4 states. [2019-12-07 13:48:15,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:48:15,528 INFO L93 Difference]: Finished difference Result 18555 states and 57550 transitions. [2019-12-07 13:48:15,529 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 13:48:15,529 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 66 [2019-12-07 13:48:15,529 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:48:15,549 INFO L225 Difference]: With dead ends: 18555 [2019-12-07 13:48:15,549 INFO L226 Difference]: Without dead ends: 18555 [2019-12-07 13:48:15,549 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:48:15,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18555 states. [2019-12-07 13:48:15,785 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18555 to 16539. [2019-12-07 13:48:15,785 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16539 states. [2019-12-07 13:48:15,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16539 states to 16539 states and 51316 transitions. [2019-12-07 13:48:15,812 INFO L78 Accepts]: Start accepts. Automaton has 16539 states and 51316 transitions. Word has length 66 [2019-12-07 13:48:15,812 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:48:15,812 INFO L462 AbstractCegarLoop]: Abstraction has 16539 states and 51316 transitions. [2019-12-07 13:48:15,812 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 13:48:15,813 INFO L276 IsEmpty]: Start isEmpty. Operand 16539 states and 51316 transitions. [2019-12-07 13:48:15,827 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 13:48:15,827 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:48:15,828 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:48:15,828 INFO L410 AbstractCegarLoop]: === Iteration 24 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:48:15,828 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:48:15,828 INFO L82 PathProgramCache]: Analyzing trace with hash -1443128569, now seen corresponding path program 1 times [2019-12-07 13:48:15,828 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:48:15,828 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [344430230] [2019-12-07 13:48:15,828 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:48:15,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:48:15,913 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:48:15,913 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [344430230] [2019-12-07 13:48:15,913 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:48:15,913 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 13:48:15,913 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [431935185] [2019-12-07 13:48:15,914 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 13:48:15,914 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:48:15,914 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 13:48:15,914 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:48:15,914 INFO L87 Difference]: Start difference. First operand 16539 states and 51316 transitions. Second operand 5 states. [2019-12-07 13:48:16,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:48:16,004 INFO L93 Difference]: Finished difference Result 28083 states and 87496 transitions. [2019-12-07 13:48:16,004 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 13:48:16,004 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 66 [2019-12-07 13:48:16,004 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:48:16,020 INFO L225 Difference]: With dead ends: 28083 [2019-12-07 13:48:16,020 INFO L226 Difference]: Without dead ends: 13020 [2019-12-07 13:48:16,020 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2019-12-07 13:48:16,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13020 states. [2019-12-07 13:48:16,196 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13020 to 13020. [2019-12-07 13:48:16,196 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13020 states. [2019-12-07 13:48:16,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13020 states to 13020 states and 40555 transitions. [2019-12-07 13:48:16,218 INFO L78 Accepts]: Start accepts. Automaton has 13020 states and 40555 transitions. Word has length 66 [2019-12-07 13:48:16,218 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:48:16,218 INFO L462 AbstractCegarLoop]: Abstraction has 13020 states and 40555 transitions. [2019-12-07 13:48:16,218 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 13:48:16,218 INFO L276 IsEmpty]: Start isEmpty. Operand 13020 states and 40555 transitions. [2019-12-07 13:48:16,231 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 13:48:16,231 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:48:16,231 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:48:16,231 INFO L410 AbstractCegarLoop]: === Iteration 25 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:48:16,231 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:48:16,231 INFO L82 PathProgramCache]: Analyzing trace with hash 1904298335, now seen corresponding path program 2 times [2019-12-07 13:48:16,232 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:48:16,232 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [570216989] [2019-12-07 13:48:16,232 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:48:16,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:48:16,303 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:48:16,304 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [570216989] [2019-12-07 13:48:16,304 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:48:16,304 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 13:48:16,304 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [72920328] [2019-12-07 13:48:16,304 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 13:48:16,304 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:48:16,305 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 13:48:16,305 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-07 13:48:16,305 INFO L87 Difference]: Start difference. First operand 13020 states and 40555 transitions. Second operand 5 states. [2019-12-07 13:48:16,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:48:16,366 INFO L93 Difference]: Finished difference Result 22639 states and 70890 transitions. [2019-12-07 13:48:16,366 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 13:48:16,366 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 66 [2019-12-07 13:48:16,366 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:48:16,378 INFO L225 Difference]: With dead ends: 22639 [2019-12-07 13:48:16,378 INFO L226 Difference]: Without dead ends: 10512 [2019-12-07 13:48:16,378 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2019-12-07 13:48:16,436 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10512 states. [2019-12-07 13:48:16,525 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10512 to 10512. [2019-12-07 13:48:16,525 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10512 states. [2019-12-07 13:48:16,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10512 states to 10512 states and 32874 transitions. [2019-12-07 13:48:16,543 INFO L78 Accepts]: Start accepts. Automaton has 10512 states and 32874 transitions. Word has length 66 [2019-12-07 13:48:16,543 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:48:16,543 INFO L462 AbstractCegarLoop]: Abstraction has 10512 states and 32874 transitions. [2019-12-07 13:48:16,543 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 13:48:16,544 INFO L276 IsEmpty]: Start isEmpty. Operand 10512 states and 32874 transitions. [2019-12-07 13:48:16,553 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 13:48:16,553 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:48:16,553 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:48:16,553 INFO L410 AbstractCegarLoop]: === Iteration 26 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:48:16,554 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:48:16,554 INFO L82 PathProgramCache]: Analyzing trace with hash -1283449633, now seen corresponding path program 3 times [2019-12-07 13:48:16,554 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:48:16,554 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [173917434] [2019-12-07 13:48:16,554 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:48:16,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:48:16,593 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:48:16,594 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [173917434] [2019-12-07 13:48:16,594 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:48:16,594 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 13:48:16,594 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1390181964] [2019-12-07 13:48:16,594 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 13:48:16,594 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:48:16,594 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 13:48:16,594 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:48:16,595 INFO L87 Difference]: Start difference. First operand 10512 states and 32874 transitions. Second operand 3 states. [2019-12-07 13:48:16,622 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:48:16,622 INFO L93 Difference]: Finished difference Result 9730 states and 29711 transitions. [2019-12-07 13:48:16,622 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 13:48:16,622 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 66 [2019-12-07 13:48:16,623 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:48:16,632 INFO L225 Difference]: With dead ends: 9730 [2019-12-07 13:48:16,632 INFO L226 Difference]: Without dead ends: 9730 [2019-12-07 13:48:16,632 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 13:48:16,687 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9730 states. [2019-12-07 13:48:16,778 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9730 to 9508. [2019-12-07 13:48:16,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9508 states. [2019-12-07 13:48:16,791 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9508 states to 9508 states and 29065 transitions. [2019-12-07 13:48:16,791 INFO L78 Accepts]: Start accepts. Automaton has 9508 states and 29065 transitions. Word has length 66 [2019-12-07 13:48:16,791 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:48:16,791 INFO L462 AbstractCegarLoop]: Abstraction has 9508 states and 29065 transitions. [2019-12-07 13:48:16,791 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 13:48:16,791 INFO L276 IsEmpty]: Start isEmpty. Operand 9508 states and 29065 transitions. [2019-12-07 13:48:16,798 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 13:48:16,799 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:48:16,799 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:48:16,799 INFO L410 AbstractCegarLoop]: === Iteration 27 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:48:16,799 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:48:16,799 INFO L82 PathProgramCache]: Analyzing trace with hash -1197749059, now seen corresponding path program 1 times [2019-12-07 13:48:16,799 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:48:16,799 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [24896607] [2019-12-07 13:48:16,799 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:48:16,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:48:16,850 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:48:16,851 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [24896607] [2019-12-07 13:48:16,851 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:48:16,851 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 13:48:16,851 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [271393770] [2019-12-07 13:48:16,851 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 13:48:16,851 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:48:16,852 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 13:48:16,852 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2019-12-07 13:48:16,852 INFO L87 Difference]: Start difference. First operand 9508 states and 29065 transitions. Second operand 7 states. [2019-12-07 13:48:17,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:48:17,014 INFO L93 Difference]: Finished difference Result 18092 states and 54144 transitions. [2019-12-07 13:48:17,014 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 13:48:17,014 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 67 [2019-12-07 13:48:17,014 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:48:17,027 INFO L225 Difference]: With dead ends: 18092 [2019-12-07 13:48:17,027 INFO L226 Difference]: Without dead ends: 12981 [2019-12-07 13:48:17,027 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=34, Invalid=98, Unknown=0, NotChecked=0, Total=132 [2019-12-07 13:48:17,087 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12981 states. [2019-12-07 13:48:17,201 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12981 to 10998. [2019-12-07 13:48:17,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10998 states. [2019-12-07 13:48:17,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10998 states to 10998 states and 33228 transitions. [2019-12-07 13:48:17,217 INFO L78 Accepts]: Start accepts. Automaton has 10998 states and 33228 transitions. Word has length 67 [2019-12-07 13:48:17,217 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:48:17,217 INFO L462 AbstractCegarLoop]: Abstraction has 10998 states and 33228 transitions. [2019-12-07 13:48:17,217 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 13:48:17,217 INFO L276 IsEmpty]: Start isEmpty. Operand 10998 states and 33228 transitions. [2019-12-07 13:48:17,226 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 13:48:17,226 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:48:17,226 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:48:17,226 INFO L410 AbstractCegarLoop]: === Iteration 28 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:48:17,226 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:48:17,226 INFO L82 PathProgramCache]: Analyzing trace with hash 2078724657, now seen corresponding path program 2 times [2019-12-07 13:48:17,226 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:48:17,226 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1468471989] [2019-12-07 13:48:17,227 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:48:17,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:48:17,345 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:48:17,346 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1468471989] [2019-12-07 13:48:17,346 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:48:17,346 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 13:48:17,346 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1523099835] [2019-12-07 13:48:17,346 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-12-07 13:48:17,346 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:48:17,346 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 13:48:17,346 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=56, Unknown=0, NotChecked=0, Total=72 [2019-12-07 13:48:17,346 INFO L87 Difference]: Start difference. First operand 10998 states and 33228 transitions. Second operand 9 states. [2019-12-07 13:48:18,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:48:18,364 INFO L93 Difference]: Finished difference Result 20805 states and 61926 transitions. [2019-12-07 13:48:18,365 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2019-12-07 13:48:18,365 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 67 [2019-12-07 13:48:18,365 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:48:18,390 INFO L225 Difference]: With dead ends: 20805 [2019-12-07 13:48:18,390 INFO L226 Difference]: Without dead ends: 15106 [2019-12-07 13:48:18,390 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 43 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=67, Invalid=275, Unknown=0, NotChecked=0, Total=342 [2019-12-07 13:48:18,458 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15106 states. [2019-12-07 13:48:18,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15106 to 11621. [2019-12-07 13:48:18,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11621 states. [2019-12-07 13:48:18,585 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11621 states to 11621 states and 34761 transitions. [2019-12-07 13:48:18,586 INFO L78 Accepts]: Start accepts. Automaton has 11621 states and 34761 transitions. Word has length 67 [2019-12-07 13:48:18,586 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:48:18,586 INFO L462 AbstractCegarLoop]: Abstraction has 11621 states and 34761 transitions. [2019-12-07 13:48:18,586 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-12-07 13:48:18,586 INFO L276 IsEmpty]: Start isEmpty. Operand 11621 states and 34761 transitions. [2019-12-07 13:48:18,596 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 13:48:18,596 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:48:18,596 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:48:18,596 INFO L410 AbstractCegarLoop]: === Iteration 29 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:48:18,596 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:48:18,596 INFO L82 PathProgramCache]: Analyzing trace with hash 721495091, now seen corresponding path program 3 times [2019-12-07 13:48:18,596 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:48:18,596 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [405761324] [2019-12-07 13:48:18,597 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:48:18,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:48:18,718 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:48:18,718 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [405761324] [2019-12-07 13:48:18,718 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:48:18,718 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 13:48:18,719 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2002751397] [2019-12-07 13:48:18,719 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 13:48:18,719 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:48:18,719 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 13:48:18,719 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2019-12-07 13:48:18,719 INFO L87 Difference]: Start difference. First operand 11621 states and 34761 transitions. Second operand 10 states. [2019-12-07 13:48:19,155 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:48:19,155 INFO L93 Difference]: Finished difference Result 17276 states and 51157 transitions. [2019-12-07 13:48:19,155 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-12-07 13:48:19,155 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 67 [2019-12-07 13:48:19,155 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:48:19,171 INFO L225 Difference]: With dead ends: 17276 [2019-12-07 13:48:19,171 INFO L226 Difference]: Without dead ends: 16257 [2019-12-07 13:48:19,172 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 95 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=110, Invalid=442, Unknown=0, NotChecked=0, Total=552 [2019-12-07 13:48:19,239 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16257 states. [2019-12-07 13:48:19,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16257 to 13570. [2019-12-07 13:48:19,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13570 states. [2019-12-07 13:48:19,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13570 states to 13570 states and 40412 transitions. [2019-12-07 13:48:19,393 INFO L78 Accepts]: Start accepts. Automaton has 13570 states and 40412 transitions. Word has length 67 [2019-12-07 13:48:19,393 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:48:19,393 INFO L462 AbstractCegarLoop]: Abstraction has 13570 states and 40412 transitions. [2019-12-07 13:48:19,393 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 13:48:19,393 INFO L276 IsEmpty]: Start isEmpty. Operand 13570 states and 40412 transitions. [2019-12-07 13:48:19,405 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 13:48:19,406 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:48:19,406 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:48:19,406 INFO L410 AbstractCegarLoop]: === Iteration 30 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:48:19,406 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:48:19,406 INFO L82 PathProgramCache]: Analyzing trace with hash 957967249, now seen corresponding path program 4 times [2019-12-07 13:48:19,406 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:48:19,406 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2111098145] [2019-12-07 13:48:19,406 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:48:19,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:48:19,499 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:48:19,499 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2111098145] [2019-12-07 13:48:19,500 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:48:19,500 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 13:48:19,500 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1669082399] [2019-12-07 13:48:19,500 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 13:48:19,500 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:48:19,500 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 13:48:19,500 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2019-12-07 13:48:19,500 INFO L87 Difference]: Start difference. First operand 13570 states and 40412 transitions. Second operand 10 states. [2019-12-07 13:48:19,835 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:48:19,835 INFO L93 Difference]: Finished difference Result 16814 states and 49303 transitions. [2019-12-07 13:48:19,835 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 13:48:19,836 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 67 [2019-12-07 13:48:19,836 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:48:19,850 INFO L225 Difference]: With dead ends: 16814 [2019-12-07 13:48:19,850 INFO L226 Difference]: Without dead ends: 14313 [2019-12-07 13:48:19,851 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 72 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=100, Invalid=362, Unknown=0, NotChecked=0, Total=462 [2019-12-07 13:48:19,913 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14313 states. [2019-12-07 13:48:20,020 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14313 to 11325. [2019-12-07 13:48:20,020 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11325 states. [2019-12-07 13:48:20,036 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11325 states to 11325 states and 33878 transitions. [2019-12-07 13:48:20,036 INFO L78 Accepts]: Start accepts. Automaton has 11325 states and 33878 transitions. Word has length 67 [2019-12-07 13:48:20,037 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:48:20,037 INFO L462 AbstractCegarLoop]: Abstraction has 11325 states and 33878 transitions. [2019-12-07 13:48:20,037 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 13:48:20,037 INFO L276 IsEmpty]: Start isEmpty. Operand 11325 states and 33878 transitions. [2019-12-07 13:48:20,046 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 13:48:20,046 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:48:20,046 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:48:20,046 INFO L410 AbstractCegarLoop]: === Iteration 31 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:48:20,046 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:48:20,046 INFO L82 PathProgramCache]: Analyzing trace with hash 88464887, now seen corresponding path program 5 times [2019-12-07 13:48:20,046 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:48:20,047 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1794822009] [2019-12-07 13:48:20,047 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:48:20,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:48:20,208 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:48:20,208 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1794822009] [2019-12-07 13:48:20,208 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:48:20,208 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 13:48:20,208 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1952896369] [2019-12-07 13:48:20,208 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 13:48:20,209 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:48:20,209 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 13:48:20,209 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2019-12-07 13:48:20,209 INFO L87 Difference]: Start difference. First operand 11325 states and 33878 transitions. Second operand 11 states. [2019-12-07 13:48:20,667 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:48:20,667 INFO L93 Difference]: Finished difference Result 17799 states and 53073 transitions. [2019-12-07 13:48:20,668 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2019-12-07 13:48:20,668 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 67 [2019-12-07 13:48:20,668 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:48:20,684 INFO L225 Difference]: With dead ends: 17799 [2019-12-07 13:48:20,684 INFO L226 Difference]: Without dead ends: 16780 [2019-12-07 13:48:20,685 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 140 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=139, Invalid=617, Unknown=0, NotChecked=0, Total=756 [2019-12-07 13:48:20,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16780 states. [2019-12-07 13:48:20,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16780 to 14852. [2019-12-07 13:48:20,902 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14852 states. [2019-12-07 13:48:20,925 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14852 states to 14852 states and 44588 transitions. [2019-12-07 13:48:20,925 INFO L78 Accepts]: Start accepts. Automaton has 14852 states and 44588 transitions. Word has length 67 [2019-12-07 13:48:20,926 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:48:20,926 INFO L462 AbstractCegarLoop]: Abstraction has 14852 states and 44588 transitions. [2019-12-07 13:48:20,926 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 13:48:20,926 INFO L276 IsEmpty]: Start isEmpty. Operand 14852 states and 44588 transitions. [2019-12-07 13:48:20,939 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 13:48:20,939 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:48:20,939 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:48:20,939 INFO L410 AbstractCegarLoop]: === Iteration 32 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:48:20,939 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:48:20,939 INFO L82 PathProgramCache]: Analyzing trace with hash 324937045, now seen corresponding path program 6 times [2019-12-07 13:48:20,939 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:48:20,939 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1267700523] [2019-12-07 13:48:20,940 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:48:20,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:48:21,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:48:21,053 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1267700523] [2019-12-07 13:48:21,053 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:48:21,053 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 13:48:21,053 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1740417574] [2019-12-07 13:48:21,053 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 13:48:21,053 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:48:21,053 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 13:48:21,053 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2019-12-07 13:48:21,053 INFO L87 Difference]: Start difference. First operand 14852 states and 44588 transitions. Second operand 11 states. [2019-12-07 13:48:21,540 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:48:21,540 INFO L93 Difference]: Finished difference Result 17530 states and 51633 transitions. [2019-12-07 13:48:21,541 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2019-12-07 13:48:21,541 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 67 [2019-12-07 13:48:21,541 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:48:21,555 INFO L225 Difference]: With dead ends: 17530 [2019-12-07 13:48:21,556 INFO L226 Difference]: Without dead ends: 13488 [2019-12-07 13:48:21,556 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 127 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=132, Invalid=570, Unknown=0, NotChecked=0, Total=702 [2019-12-07 13:48:21,617 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13488 states. [2019-12-07 13:48:21,716 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13488 to 11297. [2019-12-07 13:48:21,716 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11297 states. [2019-12-07 13:48:21,733 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11297 states to 11297 states and 33668 transitions. [2019-12-07 13:48:21,733 INFO L78 Accepts]: Start accepts. Automaton has 11297 states and 33668 transitions. Word has length 67 [2019-12-07 13:48:21,733 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:48:21,733 INFO L462 AbstractCegarLoop]: Abstraction has 11297 states and 33668 transitions. [2019-12-07 13:48:21,733 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 13:48:21,733 INFO L276 IsEmpty]: Start isEmpty. Operand 11297 states and 33668 transitions. [2019-12-07 13:48:21,742 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 13:48:21,742 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:48:21,742 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:48:21,742 INFO L410 AbstractCegarLoop]: === Iteration 33 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:48:21,742 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:48:21,742 INFO L82 PathProgramCache]: Analyzing trace with hash 975038819, now seen corresponding path program 7 times [2019-12-07 13:48:21,742 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:48:21,743 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [283404190] [2019-12-07 13:48:21,743 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:48:21,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:48:22,077 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:48:22,077 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [283404190] [2019-12-07 13:48:22,077 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:48:22,077 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2019-12-07 13:48:22,077 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1652516739] [2019-12-07 13:48:22,077 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 13:48:22,077 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:48:22,077 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 13:48:22,078 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2019-12-07 13:48:22,078 INFO L87 Difference]: Start difference. First operand 11297 states and 33668 transitions. Second operand 16 states. [2019-12-07 13:48:24,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:48:24,278 INFO L93 Difference]: Finished difference Result 11927 states and 34556 transitions. [2019-12-07 13:48:24,279 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-12-07 13:48:24,279 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 67 [2019-12-07 13:48:24,280 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:48:24,297 INFO L225 Difference]: With dead ends: 11927 [2019-12-07 13:48:24,297 INFO L226 Difference]: Without dead ends: 11748 [2019-12-07 13:48:24,298 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 1 SyntacticMatches, 3 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 180 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=172, Invalid=950, Unknown=0, NotChecked=0, Total=1122 [2019-12-07 13:48:24,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11748 states. [2019-12-07 13:48:24,443 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11748 to 10796. [2019-12-07 13:48:24,443 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10796 states. [2019-12-07 13:48:24,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10796 states to 10796 states and 31839 transitions. [2019-12-07 13:48:24,459 INFO L78 Accepts]: Start accepts. Automaton has 10796 states and 31839 transitions. Word has length 67 [2019-12-07 13:48:24,460 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:48:24,460 INFO L462 AbstractCegarLoop]: Abstraction has 10796 states and 31839 transitions. [2019-12-07 13:48:24,460 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 13:48:24,460 INFO L276 IsEmpty]: Start isEmpty. Operand 10796 states and 31839 transitions. [2019-12-07 13:48:24,469 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 13:48:24,469 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:48:24,469 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:48:24,469 INFO L410 AbstractCegarLoop]: === Iteration 34 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:48:24,469 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:48:24,469 INFO L82 PathProgramCache]: Analyzing trace with hash -478785703, now seen corresponding path program 8 times [2019-12-07 13:48:24,469 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:48:24,469 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2140567097] [2019-12-07 13:48:24,470 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:48:24,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:48:24,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:48:24,580 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2140567097] [2019-12-07 13:48:24,580 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:48:24,580 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 13:48:24,580 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2107613043] [2019-12-07 13:48:24,580 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 13:48:24,580 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:48:24,580 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 13:48:24,580 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2019-12-07 13:48:24,580 INFO L87 Difference]: Start difference. First operand 10796 states and 31839 transitions. Second operand 10 states. [2019-12-07 13:48:25,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:48:25,170 INFO L93 Difference]: Finished difference Result 14091 states and 40486 transitions. [2019-12-07 13:48:25,170 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2019-12-07 13:48:25,170 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 67 [2019-12-07 13:48:25,170 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:48:25,184 INFO L225 Difference]: With dead ends: 14091 [2019-12-07 13:48:25,184 INFO L226 Difference]: Without dead ends: 13074 [2019-12-07 13:48:25,184 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 64 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=81, Invalid=381, Unknown=0, NotChecked=0, Total=462 [2019-12-07 13:48:25,244 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13074 states. [2019-12-07 13:48:25,335 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13074 to 10173. [2019-12-07 13:48:25,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10173 states. [2019-12-07 13:48:25,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10173 states to 10173 states and 30181 transitions. [2019-12-07 13:48:25,349 INFO L78 Accepts]: Start accepts. Automaton has 10173 states and 30181 transitions. Word has length 67 [2019-12-07 13:48:25,350 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:48:25,350 INFO L462 AbstractCegarLoop]: Abstraction has 10173 states and 30181 transitions. [2019-12-07 13:48:25,350 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 13:48:25,350 INFO L276 IsEmpty]: Start isEmpty. Operand 10173 states and 30181 transitions. [2019-12-07 13:48:25,358 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 13:48:25,358 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:48:25,358 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:48:25,358 INFO L410 AbstractCegarLoop]: === Iteration 35 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:48:25,358 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:48:25,358 INFO L82 PathProgramCache]: Analyzing trace with hash -1516551711, now seen corresponding path program 9 times [2019-12-07 13:48:25,358 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:48:25,358 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1229970227] [2019-12-07 13:48:25,359 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:48:25,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 13:48:25,637 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 13:48:25,637 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1229970227] [2019-12-07 13:48:25,637 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 13:48:25,637 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 13:48:25,637 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1034252783] [2019-12-07 13:48:25,637 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 13:48:25,638 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 13:48:25,638 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 13:48:25,638 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=151, Unknown=0, NotChecked=0, Total=182 [2019-12-07 13:48:25,638 INFO L87 Difference]: Start difference. First operand 10173 states and 30181 transitions. Second operand 14 states. [2019-12-07 13:48:26,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 13:48:26,991 INFO L93 Difference]: Finished difference Result 14378 states and 41610 transitions. [2019-12-07 13:48:26,991 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2019-12-07 13:48:26,991 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 67 [2019-12-07 13:48:26,991 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 13:48:27,003 INFO L225 Difference]: With dead ends: 14378 [2019-12-07 13:48:27,003 INFO L226 Difference]: Without dead ends: 14135 [2019-12-07 13:48:27,003 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 0 SyntacticMatches, 4 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 280 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=230, Invalid=1102, Unknown=0, NotChecked=0, Total=1332 [2019-12-07 13:48:27,063 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14135 states. [2019-12-07 13:48:27,148 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14135 to 9997. [2019-12-07 13:48:27,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9997 states. [2019-12-07 13:48:27,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9997 states to 9997 states and 29709 transitions. [2019-12-07 13:48:27,162 INFO L78 Accepts]: Start accepts. Automaton has 9997 states and 29709 transitions. Word has length 67 [2019-12-07 13:48:27,162 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 13:48:27,162 INFO L462 AbstractCegarLoop]: Abstraction has 9997 states and 29709 transitions. [2019-12-07 13:48:27,162 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 13:48:27,162 INFO L276 IsEmpty]: Start isEmpty. Operand 9997 states and 29709 transitions. [2019-12-07 13:48:27,170 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 13:48:27,170 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 13:48:27,170 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 13:48:27,171 INFO L410 AbstractCegarLoop]: === Iteration 36 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 13:48:27,171 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 13:48:27,171 INFO L82 PathProgramCache]: Analyzing trace with hash -494782975, now seen corresponding path program 10 times [2019-12-07 13:48:27,171 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 13:48:27,171 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1364935214] [2019-12-07 13:48:27,171 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 13:48:27,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:48:27,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 13:48:27,234 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 13:48:27,234 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 13:48:27,236 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [904] [904] ULTIMATE.startENTRY-->L837: Formula: (let ((.cse0 (store |v_#valid_64| 0 0))) (and (= 0 v_~weak$$choice0~0_10) (= v_~a$r_buff1_thd0~0_132 0) (= 0 v_~a$w_buff0_used~0_689) (= 0 v_~a$w_buff1_used~0_376) (= v_~a$r_buff0_thd3~0_328 0) (= |v_ULTIMATE.start_main_~#t403~0.offset_22| 0) (= |v_#length_23| (store |v_#length_24| |v_ULTIMATE.start_main_~#t403~0.base_29| 4)) (= |v_#NULL.offset_6| 0) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t403~0.base_29|) (= v_~y~0_79 0) (= 0 v_~a$r_buff1_thd1~0_125) (= 0 v_~__unbuffered_p0_EAX~0_92) (= 0 v_~__unbuffered_p1_EAX~0_37) (= v_~x~0_69 0) (= 0 v_~a$r_buff1_thd2~0_129) (= (store |v_#memory_int_22| |v_ULTIMATE.start_main_~#t403~0.base_29| (store (select |v_#memory_int_22| |v_ULTIMATE.start_main_~#t403~0.base_29|) |v_ULTIMATE.start_main_~#t403~0.offset_22| 0)) |v_#memory_int_21|) (< 0 |v_#StackHeapBarrier_17|) (= v_~__unbuffered_p0_EBX~0_92 0) (= v_~a$flush_delayed~0_23 0) (= v_~a$r_buff1_thd3~0_224 0) (= v_~__unbuffered_p2_EBX~0_38 0) (= 0 v_~__unbuffered_cnt~0_98) (= v_~main$tmp_guard0~0_28 0) (= 0 v_~a$r_buff0_thd2~0_124) (= v_~a~0_181 0) (= 0 |v_#NULL.base_6|) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t403~0.base_29|)) (= 0 v_~__unbuffered_p2_EAX~0_33) (= 0 v_~a$r_buff0_thd1~0_195) (= v_~a$mem_tmp~0_12 0) (= v_~main$tmp_guard1~0_36 0) (= 0 v_~a$w_buff1~0_172) (= v_~a$r_buff0_thd0~0_144 0) (= v_~a$w_buff0~0_228 0) (= v_~weak$$choice2~0_107 0) (= v_~z~0_20 0) (= |v_#valid_62| (store .cse0 |v_ULTIMATE.start_main_~#t403~0.base_29| 1)) (= 0 v_~a$read_delayed~0_6) (= v_~a$read_delayed_var~0.offset_6 0) (= 0 v_~a$read_delayed_var~0.base_6))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_64|, #memory_int=|v_#memory_int_22|, #length=|v_#length_24|} OutVars{ULTIMATE.start_main_~#t405~0.offset=|v_ULTIMATE.start_main_~#t405~0.offset_15|, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_129, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_51|, #NULL.offset=|v_#NULL.offset_6|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_281|, ~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_144, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_31|, ~a~0=v_~a~0_181, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_67|, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_92, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_37, #length=|v_#length_23|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_33, ULTIMATE.start_main_~#t405~0.base=|v_ULTIMATE.start_main_~#t405~0.base_17|, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_38, ~__unbuffered_p0_EBX~0=v_~__unbuffered_p0_EBX~0_92, ULTIMATE.start_main_~#t404~0.base=|v_ULTIMATE.start_main_~#t404~0.base_29|, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_10|, ~a$r_buff1_thd3~0=v_~a$r_buff1_thd3~0_224, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_689, ~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_195, ULTIMATE.start_main_~#t403~0.base=|v_ULTIMATE.start_main_~#t403~0.base_29|, ~weak$$choice0~0=v_~weak$$choice0~0_10, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ~a$read_delayed_var~0.offset=v_~a$read_delayed_var~0.offset_6, ~a$w_buff0~0=v_~a$w_buff0~0_228, ~a$r_buff1_thd0~0=v_~a$r_buff1_thd0~0_132, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_98, ~x~0=v_~x~0_69, ~a$read_delayed~0=v_~a$read_delayed~0_6, ~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_124, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_36, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_55|, ~a$mem_tmp~0=v_~a$mem_tmp~0_12, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_45|, ~a$w_buff1~0=v_~a$w_buff1~0_172, ~y~0=v_~y~0_79, ULTIMATE.start_main_#t~nondet46=|v_ULTIMATE.start_main_#t~nondet46_27|, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_9|, ~a$r_buff1_thd1~0=v_~a$r_buff1_thd1~0_125, ~a$r_buff0_thd3~0=v_~a$r_buff0_thd3~0_328, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_28, #NULL.base=|v_#NULL.base_6|, ULTIMATE.start_main_~#t404~0.offset=|v_ULTIMATE.start_main_~#t404~0.offset_22|, ~a$flush_delayed~0=v_~a$flush_delayed~0_23, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, #valid=|v_#valid_62|, #memory_int=|v_#memory_int_21|, ULTIMATE.start_main_~#t403~0.offset=|v_ULTIMATE.start_main_~#t403~0.offset_22|, ~z~0=v_~z~0_20, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_376, ~weak$$choice2~0=v_~weak$$choice2~0_107, ~a$read_delayed_var~0.base=v_~a$read_delayed_var~0.base_6} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t405~0.offset, ~a$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite49, ~a$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite50, ~a~0, ULTIMATE.start_main_#t~ite52, ~__unbuffered_p0_EAX~0, ~__unbuffered_p1_EAX~0, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_~#t405~0.base, ~__unbuffered_p2_EBX~0, ~__unbuffered_p0_EBX~0, ULTIMATE.start_main_~#t404~0.base, ULTIMATE.start_main_#t~nondet45, ~a$r_buff1_thd3~0, ~a$w_buff0_used~0, ~a$r_buff0_thd1~0, ULTIMATE.start_main_~#t403~0.base, ~weak$$choice0~0, ~a$read_delayed_var~0.offset, ~a$w_buff0~0, ~a$r_buff1_thd0~0, ~__unbuffered_cnt~0, ~x~0, ~a$read_delayed~0, ~a$r_buff0_thd2~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite48, ~a$mem_tmp~0, ULTIMATE.start_main_#t~ite51, ~a$w_buff1~0, ~y~0, ULTIMATE.start_main_#t~nondet46, ULTIMATE.start_main_#t~nondet44, ~a$r_buff1_thd1~0, ~a$r_buff0_thd3~0, ~main$tmp_guard0~0, #NULL.base, ULTIMATE.start_main_~#t404~0.offset, ~a$flush_delayed~0, ULTIMATE.start_main_#res, #valid, #memory_int, ULTIMATE.start_main_~#t403~0.offset, ~z~0, ~a$w_buff1_used~0, ~weak$$choice2~0, ~a$read_delayed_var~0.base] because there is no mapped edge [2019-12-07 13:48:27,237 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [865] [865] L837-1-->L839: Formula: (and (= |v_#length_13| (store |v_#length_14| |v_ULTIMATE.start_main_~#t404~0.base_12| 4)) (= |v_#memory_int_11| (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t404~0.base_12| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t404~0.base_12|) |v_ULTIMATE.start_main_~#t404~0.offset_10| 1))) (not (= |v_ULTIMATE.start_main_~#t404~0.base_12| 0)) (= |v_ULTIMATE.start_main_~#t404~0.offset_10| 0) (< |v_#StackHeapBarrier_9| |v_ULTIMATE.start_main_~#t404~0.base_12|) (= (store |v_#valid_35| |v_ULTIMATE.start_main_~#t404~0.base_12| 1) |v_#valid_34|) (= 0 (select |v_#valid_35| |v_ULTIMATE.start_main_~#t404~0.base_12|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_12|, #length=|v_#length_14|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_9|, ULTIMATE.start_main_~#t404~0.offset=|v_ULTIMATE.start_main_~#t404~0.offset_10|, ULTIMATE.start_main_~#t404~0.base=|v_ULTIMATE.start_main_~#t404~0.base_12|, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_4|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_11|, #length=|v_#length_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t404~0.offset, ULTIMATE.start_main_~#t404~0.base, ULTIMATE.start_main_#t~nondet44, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 13:48:27,237 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [876] [876] L839-1-->L841: Formula: (and (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t405~0.base_13| 4)) (= |v_#valid_36| (store |v_#valid_37| |v_ULTIMATE.start_main_~#t405~0.base_13| 1)) (not (= 0 |v_ULTIMATE.start_main_~#t405~0.base_13|)) (= (select |v_#valid_37| |v_ULTIMATE.start_main_~#t405~0.base_13|) 0) (= 0 |v_ULTIMATE.start_main_~#t405~0.offset_11|) (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t405~0.base_13|) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t405~0.base_13| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t405~0.base_13|) |v_ULTIMATE.start_main_~#t405~0.offset_11| 2)) |v_#memory_int_13|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_37|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{ULTIMATE.start_main_~#t405~0.offset=|v_ULTIMATE.start_main_~#t405~0.offset_11|, #StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_36|, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_6|, #memory_int=|v_#memory_int_13|, #length=|v_#length_15|, ULTIMATE.start_main_~#t405~0.base=|v_ULTIMATE.start_main_~#t405~0.base_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t405~0.offset, #valid, ULTIMATE.start_main_#t~nondet45, #memory_int, #length, ULTIMATE.start_main_~#t405~0.base] because there is no mapped edge [2019-12-07 13:48:27,238 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [881] [881] L4-->L758: Formula: (and (= ~a$r_buff1_thd3~0_Out-909317594 ~a$r_buff0_thd3~0_In-909317594) (= ~x~0_Out-909317594 ~__unbuffered_p0_EAX~0_Out-909317594) (= 1 ~x~0_Out-909317594) (= ~y~0_In-909317594 ~__unbuffered_p0_EBX~0_Out-909317594) (not (= 0 P0Thread1of1ForFork1___VERIFIER_assert_~expression_In-909317594)) (= ~a$r_buff0_thd1~0_In-909317594 ~a$r_buff1_thd1~0_Out-909317594) (= ~a$r_buff1_thd0~0_Out-909317594 ~a$r_buff0_thd0~0_In-909317594) (= 1 ~a$r_buff0_thd1~0_Out-909317594) (= ~a$r_buff0_thd2~0_In-909317594 ~a$r_buff1_thd2~0_Out-909317594)) InVars {~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In-909317594, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-909317594, P0Thread1of1ForFork1___VERIFIER_assert_~expression=P0Thread1of1ForFork1___VERIFIER_assert_~expression_In-909317594, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In-909317594, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In-909317594, ~y~0=~y~0_In-909317594} OutVars{~__unbuffered_p0_EBX~0=~__unbuffered_p0_EBX~0_Out-909317594, ~a$r_buff1_thd1~0=~a$r_buff1_thd1~0_Out-909317594, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_Out-909317594, ~a$r_buff1_thd2~0=~a$r_buff1_thd2~0_Out-909317594, ~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In-909317594, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-909317594, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_Out-909317594, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In-909317594, ~__unbuffered_p0_EAX~0=~__unbuffered_p0_EAX~0_Out-909317594, ~a$r_buff1_thd0~0=~a$r_buff1_thd0~0_Out-909317594, P0Thread1of1ForFork1___VERIFIER_assert_~expression=P0Thread1of1ForFork1___VERIFIER_assert_~expression_In-909317594, ~y~0=~y~0_In-909317594, ~x~0=~x~0_Out-909317594} AuxVars[] AssignedVars[~__unbuffered_p0_EAX~0, ~__unbuffered_p0_EBX~0, ~a$r_buff1_thd1~0, ~a$r_buff1_thd3~0, ~a$r_buff1_thd2~0, ~a$r_buff1_thd0~0, ~a$r_buff0_thd1~0, ~x~0] because there is no mapped edge [2019-12-07 13:48:27,240 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [842] [842] L759-->L759-2: Formula: (let ((.cse0 (= (mod ~a$w_buff0_used~0_In201306404 256) 0)) (.cse1 (= 0 (mod ~a$r_buff0_thd1~0_In201306404 256)))) (or (and (not .cse0) (= 0 |P0Thread1of1ForFork1_#t~ite5_Out201306404|) (not .cse1)) (and (or .cse0 .cse1) (= ~a$w_buff0_used~0_In201306404 |P0Thread1of1ForFork1_#t~ite5_Out201306404|)))) InVars {~a$w_buff0_used~0=~a$w_buff0_used~0_In201306404, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In201306404} OutVars{P0Thread1of1ForFork1_#t~ite5=|P0Thread1of1ForFork1_#t~ite5_Out201306404|, ~a$w_buff0_used~0=~a$w_buff0_used~0_In201306404, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In201306404} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite5] because there is no mapped edge [2019-12-07 13:48:27,240 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [840] [840] L760-->L760-2: Formula: (let ((.cse1 (= (mod ~a$r_buff0_thd1~0_In-1766244926 256) 0)) (.cse0 (= 0 (mod ~a$w_buff0_used~0_In-1766244926 256))) (.cse2 (= 0 (mod ~a$w_buff1_used~0_In-1766244926 256))) (.cse3 (= (mod ~a$r_buff1_thd1~0_In-1766244926 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P0Thread1of1ForFork1_#t~ite6_Out-1766244926|)) (and (or .cse1 .cse0) (= ~a$w_buff1_used~0_In-1766244926 |P0Thread1of1ForFork1_#t~ite6_Out-1766244926|) (or .cse2 .cse3)))) InVars {~a$r_buff1_thd1~0=~a$r_buff1_thd1~0_In-1766244926, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1766244926, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In-1766244926, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1766244926} OutVars{P0Thread1of1ForFork1_#t~ite6=|P0Thread1of1ForFork1_#t~ite6_Out-1766244926|, ~a$r_buff1_thd1~0=~a$r_buff1_thd1~0_In-1766244926, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1766244926, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In-1766244926, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1766244926} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite6] because there is no mapped edge [2019-12-07 13:48:27,240 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [829] [829] L778-2-->L778-4: Formula: (let ((.cse1 (= 0 (mod ~a$r_buff1_thd2~0_In1319310668 256))) (.cse0 (= (mod ~a$w_buff1_used~0_In1319310668 256) 0))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork2_#t~ite9_Out1319310668| ~a~0_In1319310668)) (and (= |P1Thread1of1ForFork2_#t~ite9_Out1319310668| ~a$w_buff1~0_In1319310668) (not .cse1) (not .cse0)))) InVars {~a~0=~a~0_In1319310668, ~a$w_buff1~0=~a$w_buff1~0_In1319310668, ~a$r_buff1_thd2~0=~a$r_buff1_thd2~0_In1319310668, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1319310668} OutVars{~a~0=~a~0_In1319310668, P1Thread1of1ForFork2_#t~ite9=|P1Thread1of1ForFork2_#t~ite9_Out1319310668|, ~a$w_buff1~0=~a$w_buff1~0_In1319310668, ~a$r_buff1_thd2~0=~a$r_buff1_thd2~0_In1319310668, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1319310668} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite9] because there is no mapped edge [2019-12-07 13:48:27,240 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L778-4-->L779: Formula: (= |v_P1Thread1of1ForFork2_#t~ite9_10| v_~a~0_28) InVars {P1Thread1of1ForFork2_#t~ite9=|v_P1Thread1of1ForFork2_#t~ite9_10|} OutVars{~a~0=v_~a~0_28, P1Thread1of1ForFork2_#t~ite9=|v_P1Thread1of1ForFork2_#t~ite9_9|, P1Thread1of1ForFork2_#t~ite10=|v_P1Thread1of1ForFork2_#t~ite10_13|} AuxVars[] AssignedVars[~a~0, P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite10] because there is no mapped edge [2019-12-07 13:48:27,241 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [836] [836] L761-->L762: Formula: (let ((.cse1 (= (mod ~a$w_buff0_used~0_In-854895123 256) 0)) (.cse0 (= 0 (mod ~a$r_buff0_thd1~0_In-854895123 256))) (.cse2 (= ~a$r_buff0_thd1~0_Out-854895123 ~a$r_buff0_thd1~0_In-854895123))) (or (and (not .cse0) (not .cse1) (= ~a$r_buff0_thd1~0_Out-854895123 0)) (and .cse1 .cse2) (and .cse0 .cse2))) InVars {~a$w_buff0_used~0=~a$w_buff0_used~0_In-854895123, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In-854895123} OutVars{P0Thread1of1ForFork1_#t~ite7=|P0Thread1of1ForFork1_#t~ite7_Out-854895123|, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-854895123, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_Out-854895123} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite7, ~a$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 13:48:27,241 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [850] [850] L762-->L762-2: Formula: (let ((.cse1 (= (mod ~a$r_buff1_thd1~0_In1808458810 256) 0)) (.cse0 (= (mod ~a$w_buff1_used~0_In1808458810 256) 0)) (.cse3 (= (mod ~a$w_buff0_used~0_In1808458810 256) 0)) (.cse2 (= (mod ~a$r_buff0_thd1~0_In1808458810 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P0Thread1of1ForFork1_#t~ite8_Out1808458810| 0)) (and (= |P0Thread1of1ForFork1_#t~ite8_Out1808458810| ~a$r_buff1_thd1~0_In1808458810) (or .cse1 .cse0) (or .cse3 .cse2)))) InVars {~a$r_buff1_thd1~0=~a$r_buff1_thd1~0_In1808458810, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1808458810, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In1808458810, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1808458810} OutVars{P0Thread1of1ForFork1_#t~ite8=|P0Thread1of1ForFork1_#t~ite8_Out1808458810|, ~a$r_buff1_thd1~0=~a$r_buff1_thd1~0_In1808458810, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1808458810, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In1808458810, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1808458810} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite8] because there is no mapped edge [2019-12-07 13:48:27,241 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [860] [860] L762-2-->P0EXIT: Formula: (and (= 0 |v_P0Thread1of1ForFork1_#res.base_3|) (= v_~__unbuffered_cnt~0_49 (+ v_~__unbuffered_cnt~0_50 1)) (= 0 |v_P0Thread1of1ForFork1_#res.offset_3|) (= v_~a$r_buff1_thd1~0_63 |v_P0Thread1of1ForFork1_#t~ite8_34|)) InVars {P0Thread1of1ForFork1_#t~ite8=|v_P0Thread1of1ForFork1_#t~ite8_34|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_50} OutVars{P0Thread1of1ForFork1_#t~ite8=|v_P0Thread1of1ForFork1_#t~ite8_33|, P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_3|, ~a$r_buff1_thd1~0=v_~a$r_buff1_thd1~0_63, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_49} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite8, P0Thread1of1ForFork1_#res.offset, ~a$r_buff1_thd1~0, P0Thread1of1ForFork1_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 13:48:27,241 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [846] [846] L779-->L779-2: Formula: (let ((.cse0 (= 0 (mod ~a$w_buff0_used~0_In-671787214 256))) (.cse1 (= 0 (mod ~a$r_buff0_thd2~0_In-671787214 256)))) (or (and (= |P1Thread1of1ForFork2_#t~ite11_Out-671787214| ~a$w_buff0_used~0_In-671787214) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= |P1Thread1of1ForFork2_#t~ite11_Out-671787214| 0)))) InVars {~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In-671787214, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-671787214} OutVars{~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In-671787214, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-671787214, P1Thread1of1ForFork2_#t~ite11=|P1Thread1of1ForFork2_#t~ite11_Out-671787214|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite11] because there is no mapped edge [2019-12-07 13:48:27,241 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [880] [880] L803-->L803-8: Formula: (let ((.cse1 (= (mod ~weak$$choice2~0_In-1497378651 256) 0))) (or (and (= |P2Thread1of1ForFork0_#t~ite21_Out-1497378651| |P2Thread1of1ForFork0_#t~ite20_Out-1497378651|) (let ((.cse0 (= (mod ~a$r_buff0_thd3~0_In-1497378651 256) 0))) (or (and .cse0 (= (mod ~a$r_buff1_thd3~0_In-1497378651 256) 0)) (= 0 (mod ~a$w_buff0_used~0_In-1497378651 256)) (and .cse0 (= 0 (mod ~a$w_buff1_used~0_In-1497378651 256))))) .cse1 (= |P2Thread1of1ForFork0_#t~ite20_Out-1497378651| ~a$w_buff0~0_In-1497378651)) (and (= |P2Thread1of1ForFork0_#t~ite21_Out-1497378651| ~a$w_buff0~0_In-1497378651) (not .cse1) (= |P2Thread1of1ForFork0_#t~ite20_In-1497378651| |P2Thread1of1ForFork0_#t~ite20_Out-1497378651|)))) InVars {~a$w_buff0~0=~a$w_buff0~0_In-1497378651, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In-1497378651, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1497378651, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1497378651, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1497378651, P2Thread1of1ForFork0_#t~ite20=|P2Thread1of1ForFork0_#t~ite20_In-1497378651|, ~weak$$choice2~0=~weak$$choice2~0_In-1497378651} OutVars{P2Thread1of1ForFork0_#t~ite21=|P2Thread1of1ForFork0_#t~ite21_Out-1497378651|, ~a$w_buff0~0=~a$w_buff0~0_In-1497378651, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In-1497378651, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1497378651, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1497378651, P2Thread1of1ForFork0_#t~ite20=|P2Thread1of1ForFork0_#t~ite20_Out-1497378651|, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1497378651, ~weak$$choice2~0=~weak$$choice2~0_In-1497378651} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite21, P2Thread1of1ForFork0_#t~ite20] because there is no mapped edge [2019-12-07 13:48:27,242 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [884] [884] L804-->L804-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In193267429 256) 0))) (or (and .cse0 (= ~a$w_buff1~0_In193267429 |P2Thread1of1ForFork0_#t~ite23_Out193267429|) (= |P2Thread1of1ForFork0_#t~ite24_Out193267429| |P2Thread1of1ForFork0_#t~ite23_Out193267429|) (let ((.cse1 (= 0 (mod ~a$r_buff0_thd3~0_In193267429 256)))) (or (= 0 (mod ~a$w_buff0_used~0_In193267429 256)) (and (= (mod ~a$w_buff1_used~0_In193267429 256) 0) .cse1) (and (= (mod ~a$r_buff1_thd3~0_In193267429 256) 0) .cse1)))) (and (= ~a$w_buff1~0_In193267429 |P2Thread1of1ForFork0_#t~ite24_Out193267429|) (= |P2Thread1of1ForFork0_#t~ite23_In193267429| |P2Thread1of1ForFork0_#t~ite23_Out193267429|) (not .cse0)))) InVars {~a$w_buff1~0=~a$w_buff1~0_In193267429, P2Thread1of1ForFork0_#t~ite23=|P2Thread1of1ForFork0_#t~ite23_In193267429|, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In193267429, ~a$w_buff0_used~0=~a$w_buff0_used~0_In193267429, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In193267429, ~a$w_buff1_used~0=~a$w_buff1_used~0_In193267429, ~weak$$choice2~0=~weak$$choice2~0_In193267429} OutVars{~a$w_buff1~0=~a$w_buff1~0_In193267429, P2Thread1of1ForFork0_#t~ite23=|P2Thread1of1ForFork0_#t~ite23_Out193267429|, P2Thread1of1ForFork0_#t~ite24=|P2Thread1of1ForFork0_#t~ite24_Out193267429|, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In193267429, ~a$w_buff0_used~0=~a$w_buff0_used~0_In193267429, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In193267429, ~a$w_buff1_used~0=~a$w_buff1_used~0_In193267429, ~weak$$choice2~0=~weak$$choice2~0_In193267429} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite23, P2Thread1of1ForFork0_#t~ite24] because there is no mapped edge [2019-12-07 13:48:27,242 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [883] [883] L805-->L805-8: Formula: (let ((.cse1 (= 0 (mod ~weak$$choice2~0_In-1723651070 256)))) (or (and (let ((.cse0 (= (mod ~a$r_buff0_thd3~0_In-1723651070 256) 0))) (or (and .cse0 (= (mod ~a$w_buff1_used~0_In-1723651070 256) 0)) (and .cse0 (= 0 (mod ~a$r_buff1_thd3~0_In-1723651070 256))) (= 0 (mod ~a$w_buff0_used~0_In-1723651070 256)))) (= |P2Thread1of1ForFork0_#t~ite27_Out-1723651070| |P2Thread1of1ForFork0_#t~ite26_Out-1723651070|) .cse1 (= ~a$w_buff0_used~0_In-1723651070 |P2Thread1of1ForFork0_#t~ite26_Out-1723651070|)) (and (= ~a$w_buff0_used~0_In-1723651070 |P2Thread1of1ForFork0_#t~ite27_Out-1723651070|) (= |P2Thread1of1ForFork0_#t~ite26_In-1723651070| |P2Thread1of1ForFork0_#t~ite26_Out-1723651070|) (not .cse1)))) InVars {P2Thread1of1ForFork0_#t~ite26=|P2Thread1of1ForFork0_#t~ite26_In-1723651070|, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In-1723651070, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1723651070, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1723651070, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1723651070, ~weak$$choice2~0=~weak$$choice2~0_In-1723651070} OutVars{P2Thread1of1ForFork0_#t~ite26=|P2Thread1of1ForFork0_#t~ite26_Out-1723651070|, P2Thread1of1ForFork0_#t~ite27=|P2Thread1of1ForFork0_#t~ite27_Out-1723651070|, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In-1723651070, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1723651070, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1723651070, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1723651070, ~weak$$choice2~0=~weak$$choice2~0_In-1723651070} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite26, P2Thread1of1ForFork0_#t~ite27] because there is no mapped edge [2019-12-07 13:48:27,243 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [768] [768] L807-->L808: Formula: (and (= v_~a$r_buff0_thd3~0_53 v_~a$r_buff0_thd3~0_52) (not (= 0 (mod v_~weak$$choice2~0_17 256)))) InVars {~a$r_buff0_thd3~0=v_~a$r_buff0_thd3~0_53, ~weak$$choice2~0=v_~weak$$choice2~0_17} OutVars{P2Thread1of1ForFork0_#t~ite33=|v_P2Thread1of1ForFork0_#t~ite33_5|, P2Thread1of1ForFork0_#t~ite32=|v_P2Thread1of1ForFork0_#t~ite32_5|, ~a$r_buff0_thd3~0=v_~a$r_buff0_thd3~0_52, P2Thread1of1ForFork0_#t~ite31=|v_P2Thread1of1ForFork0_#t~ite31_5|, ~weak$$choice2~0=v_~weak$$choice2~0_17} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite33, P2Thread1of1ForFork0_#t~ite32, ~a$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite31] because there is no mapped edge [2019-12-07 13:48:27,244 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L810-->L814: Formula: (and (not (= (mod v_~a$flush_delayed~0_7 256) 0)) (= v_~a~0_16 v_~a$mem_tmp~0_4) (= v_~a$flush_delayed~0_6 0)) InVars {~a$mem_tmp~0=v_~a$mem_tmp~0_4, ~a$flush_delayed~0=v_~a$flush_delayed~0_7} OutVars{P2Thread1of1ForFork0_#t~ite37=|v_P2Thread1of1ForFork0_#t~ite37_5|, ~a~0=v_~a~0_16, ~a$mem_tmp~0=v_~a$mem_tmp~0_4, ~a$flush_delayed~0=v_~a$flush_delayed~0_6} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite37, ~a~0, ~a$flush_delayed~0] because there is no mapped edge [2019-12-07 13:48:27,244 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [849] [849] L814-2-->L814-4: Formula: (let ((.cse0 (= 0 (mod ~a$w_buff1_used~0_In2088449369 256))) (.cse1 (= 0 (mod ~a$r_buff1_thd3~0_In2088449369 256)))) (or (and (= ~a~0_In2088449369 |P2Thread1of1ForFork0_#t~ite38_Out2088449369|) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= ~a$w_buff1~0_In2088449369 |P2Thread1of1ForFork0_#t~ite38_Out2088449369|)))) InVars {~a~0=~a~0_In2088449369, ~a$w_buff1~0=~a$w_buff1~0_In2088449369, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In2088449369, ~a$w_buff1_used~0=~a$w_buff1_used~0_In2088449369} OutVars{~a~0=~a~0_In2088449369, P2Thread1of1ForFork0_#t~ite38=|P2Thread1of1ForFork0_#t~ite38_Out2088449369|, ~a$w_buff1~0=~a$w_buff1~0_In2088449369, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In2088449369, ~a$w_buff1_used~0=~a$w_buff1_used~0_In2088449369} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite38] because there is no mapped edge [2019-12-07 13:48:27,244 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [783] [783] L814-4-->L815: Formula: (= v_~a~0_36 |v_P2Thread1of1ForFork0_#t~ite38_8|) InVars {P2Thread1of1ForFork0_#t~ite38=|v_P2Thread1of1ForFork0_#t~ite38_8|} OutVars{~a~0=v_~a~0_36, P2Thread1of1ForFork0_#t~ite39=|v_P2Thread1of1ForFork0_#t~ite39_11|, P2Thread1of1ForFork0_#t~ite38=|v_P2Thread1of1ForFork0_#t~ite38_7|} AuxVars[] AssignedVars[~a~0, P2Thread1of1ForFork0_#t~ite39, P2Thread1of1ForFork0_#t~ite38] because there is no mapped edge [2019-12-07 13:48:27,244 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [851] [851] L815-->L815-2: Formula: (let ((.cse0 (= (mod ~a$r_buff0_thd3~0_In-1083272070 256) 0)) (.cse1 (= 0 (mod ~a$w_buff0_used~0_In-1083272070 256)))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork0_#t~ite40_Out-1083272070| ~a$w_buff0_used~0_In-1083272070)) (and (not .cse0) (not .cse1) (= |P2Thread1of1ForFork0_#t~ite40_Out-1083272070| 0)))) InVars {~a$w_buff0_used~0=~a$w_buff0_used~0_In-1083272070, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1083272070} OutVars{P2Thread1of1ForFork0_#t~ite40=|P2Thread1of1ForFork0_#t~ite40_Out-1083272070|, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1083272070, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1083272070} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite40] because there is no mapped edge [2019-12-07 13:48:27,245 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [825] [825] L816-->L816-2: Formula: (let ((.cse1 (= (mod ~a$w_buff0_used~0_In-1925847367 256) 0)) (.cse0 (= 0 (mod ~a$r_buff0_thd3~0_In-1925847367 256))) (.cse2 (= (mod ~a$r_buff1_thd3~0_In-1925847367 256) 0)) (.cse3 (= (mod ~a$w_buff1_used~0_In-1925847367 256) 0))) (or (and (= |P2Thread1of1ForFork0_#t~ite41_Out-1925847367| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (or .cse2 .cse3) (= |P2Thread1of1ForFork0_#t~ite41_Out-1925847367| ~a$w_buff1_used~0_In-1925847367)))) InVars {~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In-1925847367, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1925847367, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1925847367, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1925847367} OutVars{~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In-1925847367, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1925847367, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1925847367, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1925847367, P2Thread1of1ForFork0_#t~ite41=|P2Thread1of1ForFork0_#t~ite41_Out-1925847367|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite41] because there is no mapped edge [2019-12-07 13:48:27,245 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [844] [844] L817-->L817-2: Formula: (let ((.cse1 (= (mod ~a$w_buff0_used~0_In1445510027 256) 0)) (.cse0 (= 0 (mod ~a$r_buff0_thd3~0_In1445510027 256)))) (or (and (not .cse0) (= 0 |P2Thread1of1ForFork0_#t~ite42_Out1445510027|) (not .cse1)) (and (or .cse1 .cse0) (= |P2Thread1of1ForFork0_#t~ite42_Out1445510027| ~a$r_buff0_thd3~0_In1445510027)))) InVars {~a$w_buff0_used~0=~a$w_buff0_used~0_In1445510027, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In1445510027} OutVars{~a$w_buff0_used~0=~a$w_buff0_used~0_In1445510027, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In1445510027, P2Thread1of1ForFork0_#t~ite42=|P2Thread1of1ForFork0_#t~ite42_Out1445510027|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite42] because there is no mapped edge [2019-12-07 13:48:27,246 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [828] [828] L818-->L818-2: Formula: (let ((.cse0 (= 0 (mod ~a$r_buff0_thd3~0_In1824585213 256))) (.cse1 (= (mod ~a$w_buff0_used~0_In1824585213 256) 0)) (.cse2 (= 0 (mod ~a$w_buff1_used~0_In1824585213 256))) (.cse3 (= 0 (mod ~a$r_buff1_thd3~0_In1824585213 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~a$r_buff1_thd3~0_In1824585213 |P2Thread1of1ForFork0_#t~ite43_Out1824585213|)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork0_#t~ite43_Out1824585213| 0)))) InVars {~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In1824585213, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1824585213, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In1824585213, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1824585213} OutVars{P2Thread1of1ForFork0_#t~ite43=|P2Thread1of1ForFork0_#t~ite43_Out1824585213|, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In1824585213, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1824585213, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In1824585213, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1824585213} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite43] because there is no mapped edge [2019-12-07 13:48:27,246 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [848] [848] L780-->L780-2: Formula: (let ((.cse2 (= (mod ~a$w_buff0_used~0_In-1345775623 256) 0)) (.cse3 (= 0 (mod ~a$r_buff0_thd2~0_In-1345775623 256))) (.cse1 (= 0 (mod ~a$w_buff1_used~0_In-1345775623 256))) (.cse0 (= 0 (mod ~a$r_buff1_thd2~0_In-1345775623 256)))) (or (and (= 0 |P1Thread1of1ForFork2_#t~ite12_Out-1345775623|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse2 .cse3) (= |P1Thread1of1ForFork2_#t~ite12_Out-1345775623| ~a$w_buff1_used~0_In-1345775623) (or .cse1 .cse0)))) InVars {~a$r_buff1_thd2~0=~a$r_buff1_thd2~0_In-1345775623, ~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In-1345775623, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1345775623, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1345775623} OutVars{~a$r_buff1_thd2~0=~a$r_buff1_thd2~0_In-1345775623, ~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In-1345775623, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1345775623, P1Thread1of1ForFork2_#t~ite12=|P1Thread1of1ForFork2_#t~ite12_Out-1345775623|, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1345775623} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite12] because there is no mapped edge [2019-12-07 13:48:27,246 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [838] [838] L781-->L781-2: Formula: (let ((.cse0 (= 0 (mod ~a$w_buff0_used~0_In136767720 256))) (.cse1 (= 0 (mod ~a$r_buff0_thd2~0_In136767720 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork2_#t~ite13_Out136767720|)) (and (or .cse0 .cse1) (= ~a$r_buff0_thd2~0_In136767720 |P1Thread1of1ForFork2_#t~ite13_Out136767720|)))) InVars {~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In136767720, ~a$w_buff0_used~0=~a$w_buff0_used~0_In136767720} OutVars{~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In136767720, ~a$w_buff0_used~0=~a$w_buff0_used~0_In136767720, P1Thread1of1ForFork2_#t~ite13=|P1Thread1of1ForFork2_#t~ite13_Out136767720|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite13] because there is no mapped edge [2019-12-07 13:48:27,247 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [837] [837] L782-->L782-2: Formula: (let ((.cse1 (= 0 (mod ~a$r_buff1_thd2~0_In1887932965 256))) (.cse0 (= 0 (mod ~a$w_buff1_used~0_In1887932965 256))) (.cse3 (= 0 (mod ~a$w_buff0_used~0_In1887932965 256))) (.cse2 (= 0 (mod ~a$r_buff0_thd2~0_In1887932965 256)))) (or (and (= |P1Thread1of1ForFork2_#t~ite14_Out1887932965| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (or .cse3 .cse2) (= |P1Thread1of1ForFork2_#t~ite14_Out1887932965| ~a$r_buff1_thd2~0_In1887932965)))) InVars {~a$r_buff1_thd2~0=~a$r_buff1_thd2~0_In1887932965, ~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In1887932965, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1887932965, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1887932965} OutVars{~a$r_buff1_thd2~0=~a$r_buff1_thd2~0_In1887932965, ~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In1887932965, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1887932965, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1887932965, P1Thread1of1ForFork2_#t~ite14=|P1Thread1of1ForFork2_#t~ite14_Out1887932965|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite14] because there is no mapped edge [2019-12-07 13:48:27,247 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [863] [863] L818-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= (+ v_~__unbuffered_cnt~0_56 1) v_~__unbuffered_cnt~0_55) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0) (= v_~a$r_buff1_thd3~0_123 |v_P2Thread1of1ForFork0_#t~ite43_32|)) InVars {P2Thread1of1ForFork0_#t~ite43=|v_P2Thread1of1ForFork0_#t~ite43_32|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_56} OutVars{P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, P2Thread1of1ForFork0_#t~ite43=|v_P2Thread1of1ForFork0_#t~ite43_31|, ~a$r_buff1_thd3~0=v_~a$r_buff1_thd3~0_123, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#res.base, P2Thread1of1ForFork0_#t~ite43, ~a$r_buff1_thd3~0, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 13:48:27,247 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [879] [879] L782-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= |v_P1Thread1of1ForFork2_#t~ite14_42| v_~a$r_buff1_thd2~0_99) (= (+ v_~__unbuffered_cnt~0_83 1) v_~__unbuffered_cnt~0_82)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_83, P1Thread1of1ForFork2_#t~ite14=|v_P1Thread1of1ForFork2_#t~ite14_42|} OutVars{P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_99, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_82, P1Thread1of1ForFork2_#t~ite14=|v_P1Thread1of1ForFork2_#t~ite14_41|, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#res.offset, ~a$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#t~ite14, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-12-07 13:48:27,247 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [799] [799] L841-1-->L847: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_9 256))) (= v_~main$tmp_guard0~0_9 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_36) 1 0)) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_36} OutVars{ULTIMATE.start_main_#t~nondet46=|v_ULTIMATE.start_main_#t~nondet46_7|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_36, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_9} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet46, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 13:48:27,247 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [832] [832] L847-2-->L847-4: Formula: (let ((.cse1 (= 0 (mod ~a$r_buff1_thd0~0_In769446604 256))) (.cse0 (= 0 (mod ~a$w_buff1_used~0_In769446604 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite47_Out769446604| ~a$w_buff1~0_In769446604) (not .cse1)) (and (= |ULTIMATE.start_main_#t~ite47_Out769446604| ~a~0_In769446604) (or .cse1 .cse0)))) InVars {~a~0=~a~0_In769446604, ~a$w_buff1~0=~a$w_buff1~0_In769446604, ~a$r_buff1_thd0~0=~a$r_buff1_thd0~0_In769446604, ~a$w_buff1_used~0=~a$w_buff1_used~0_In769446604} OutVars{~a~0=~a~0_In769446604, ~a$w_buff1~0=~a$w_buff1~0_In769446604, ULTIMATE.start_main_#t~ite47=|ULTIMATE.start_main_#t~ite47_Out769446604|, ~a$r_buff1_thd0~0=~a$r_buff1_thd0~0_In769446604, ~a$w_buff1_used~0=~a$w_buff1_used~0_In769446604} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47] because there is no mapped edge [2019-12-07 13:48:27,247 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [796] [796] L847-4-->L848: Formula: (= v_~a~0_44 |v_ULTIMATE.start_main_#t~ite47_19|) InVars {ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_19|} OutVars{~a~0=v_~a~0_44, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_18|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_16|} AuxVars[] AssignedVars[~a~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 13:48:27,248 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [826] [826] L848-->L848-2: Formula: (let ((.cse1 (= 0 (mod ~a$w_buff0_used~0_In1050417585 256))) (.cse0 (= 0 (mod ~a$r_buff0_thd0~0_In1050417585 256)))) (or (and (= |ULTIMATE.start_main_#t~ite49_Out1050417585| ~a$w_buff0_used~0_In1050417585) (or .cse0 .cse1)) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite49_Out1050417585| 0) (not .cse0)))) InVars {~a$w_buff0_used~0=~a$w_buff0_used~0_In1050417585, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In1050417585} OutVars{~a$w_buff0_used~0=~a$w_buff0_used~0_In1050417585, ULTIMATE.start_main_#t~ite49=|ULTIMATE.start_main_#t~ite49_Out1050417585|, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In1050417585} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite49] because there is no mapped edge [2019-12-07 13:48:27,248 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [831] [831] L849-->L849-2: Formula: (let ((.cse0 (= (mod ~a$w_buff1_used~0_In1266141171 256) 0)) (.cse1 (= (mod ~a$r_buff1_thd0~0_In1266141171 256) 0)) (.cse3 (= 0 (mod ~a$w_buff0_used~0_In1266141171 256))) (.cse2 (= 0 (mod ~a$r_buff0_thd0~0_In1266141171 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite50_Out1266141171|)) (and (= ~a$w_buff1_used~0_In1266141171 |ULTIMATE.start_main_#t~ite50_Out1266141171|) (or .cse0 .cse1) (or .cse3 .cse2)))) InVars {~a$r_buff1_thd0~0=~a$r_buff1_thd0~0_In1266141171, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1266141171, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In1266141171, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1266141171} OutVars{ULTIMATE.start_main_#t~ite50=|ULTIMATE.start_main_#t~ite50_Out1266141171|, ~a$r_buff1_thd0~0=~a$r_buff1_thd0~0_In1266141171, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1266141171, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In1266141171, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1266141171} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite50] because there is no mapped edge [2019-12-07 13:48:27,248 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [830] [830] L850-->L850-2: Formula: (let ((.cse1 (= 0 (mod ~a$r_buff0_thd0~0_In1812785205 256))) (.cse0 (= (mod ~a$w_buff0_used~0_In1812785205 256) 0))) (or (and (= ~a$r_buff0_thd0~0_In1812785205 |ULTIMATE.start_main_#t~ite51_Out1812785205|) (or .cse0 .cse1)) (and (= 0 |ULTIMATE.start_main_#t~ite51_Out1812785205|) (not .cse1) (not .cse0)))) InVars {~a$w_buff0_used~0=~a$w_buff0_used~0_In1812785205, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In1812785205} OutVars{ULTIMATE.start_main_#t~ite51=|ULTIMATE.start_main_#t~ite51_Out1812785205|, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1812785205, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In1812785205} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite51] because there is no mapped edge [2019-12-07 13:48:27,249 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [841] [841] L851-->L851-2: Formula: (let ((.cse0 (= 0 (mod ~a$r_buff1_thd0~0_In-1421356120 256))) (.cse1 (= (mod ~a$w_buff1_used~0_In-1421356120 256) 0)) (.cse2 (= 0 (mod ~a$w_buff0_used~0_In-1421356120 256))) (.cse3 (= (mod ~a$r_buff0_thd0~0_In-1421356120 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~a$r_buff1_thd0~0_In-1421356120 |ULTIMATE.start_main_#t~ite52_Out-1421356120|)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite52_Out-1421356120|)))) InVars {~a$r_buff1_thd0~0=~a$r_buff1_thd0~0_In-1421356120, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1421356120, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In-1421356120, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1421356120} OutVars{ULTIMATE.start_main_#t~ite52=|ULTIMATE.start_main_#t~ite52_Out-1421356120|, ~a$r_buff1_thd0~0=~a$r_buff1_thd0~0_In-1421356120, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1421356120, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In-1421356120, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1421356120} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52] because there is no mapped edge [2019-12-07 13:48:27,249 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [899] [899] L851-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_~a$r_buff1_thd0~0_125 |v_ULTIMATE.start_main_#t~ite52_55|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_22 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_16|) (= (mod v_~main$tmp_guard1~0_29 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_16|) (= v_~main$tmp_guard1~0_29 (ite (= (ite (not (and (= v_~__unbuffered_p2_EBX~0_29 0) (= 0 v_~__unbuffered_p1_EAX~0_28) (= 1 v_~__unbuffered_p2_EAX~0_26) (= v_~__unbuffered_p0_EBX~0_85 0) (= 1 v_~__unbuffered_p0_EAX~0_85))) 1 0) 0) 0 1)) (= v_ULTIMATE.start___VERIFIER_assert_~expression_22 0)) InVars {~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_85, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_55|, ~__unbuffered_p0_EBX~0=v_~__unbuffered_p0_EBX~0_85, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_29, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_28, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_26} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_85, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_54|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_22, ~__unbuffered_p0_EBX~0=v_~__unbuffered_p0_EBX~0_85, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_29, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_28, ~a$r_buff1_thd0~0=v_~a$r_buff1_thd0~0_125, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_29, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_26, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_16|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start___VERIFIER_assert_~expression, ~a$r_buff1_thd0~0, ~main$tmp_guard1~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 13:48:27,296 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 01:48:27 BasicIcfg [2019-12-07 13:48:27,296 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 13:48:27,297 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 13:48:27,297 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 13:48:27,297 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 13:48:27,297 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 01:47:09" (3/4) ... [2019-12-07 13:48:27,298 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 13:48:27,299 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [904] [904] ULTIMATE.startENTRY-->L837: Formula: (let ((.cse0 (store |v_#valid_64| 0 0))) (and (= 0 v_~weak$$choice0~0_10) (= v_~a$r_buff1_thd0~0_132 0) (= 0 v_~a$w_buff0_used~0_689) (= 0 v_~a$w_buff1_used~0_376) (= v_~a$r_buff0_thd3~0_328 0) (= |v_ULTIMATE.start_main_~#t403~0.offset_22| 0) (= |v_#length_23| (store |v_#length_24| |v_ULTIMATE.start_main_~#t403~0.base_29| 4)) (= |v_#NULL.offset_6| 0) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t403~0.base_29|) (= v_~y~0_79 0) (= 0 v_~a$r_buff1_thd1~0_125) (= 0 v_~__unbuffered_p0_EAX~0_92) (= 0 v_~__unbuffered_p1_EAX~0_37) (= v_~x~0_69 0) (= 0 v_~a$r_buff1_thd2~0_129) (= (store |v_#memory_int_22| |v_ULTIMATE.start_main_~#t403~0.base_29| (store (select |v_#memory_int_22| |v_ULTIMATE.start_main_~#t403~0.base_29|) |v_ULTIMATE.start_main_~#t403~0.offset_22| 0)) |v_#memory_int_21|) (< 0 |v_#StackHeapBarrier_17|) (= v_~__unbuffered_p0_EBX~0_92 0) (= v_~a$flush_delayed~0_23 0) (= v_~a$r_buff1_thd3~0_224 0) (= v_~__unbuffered_p2_EBX~0_38 0) (= 0 v_~__unbuffered_cnt~0_98) (= v_~main$tmp_guard0~0_28 0) (= 0 v_~a$r_buff0_thd2~0_124) (= v_~a~0_181 0) (= 0 |v_#NULL.base_6|) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t403~0.base_29|)) (= 0 v_~__unbuffered_p2_EAX~0_33) (= 0 v_~a$r_buff0_thd1~0_195) (= v_~a$mem_tmp~0_12 0) (= v_~main$tmp_guard1~0_36 0) (= 0 v_~a$w_buff1~0_172) (= v_~a$r_buff0_thd0~0_144 0) (= v_~a$w_buff0~0_228 0) (= v_~weak$$choice2~0_107 0) (= v_~z~0_20 0) (= |v_#valid_62| (store .cse0 |v_ULTIMATE.start_main_~#t403~0.base_29| 1)) (= 0 v_~a$read_delayed~0_6) (= v_~a$read_delayed_var~0.offset_6 0) (= 0 v_~a$read_delayed_var~0.base_6))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_64|, #memory_int=|v_#memory_int_22|, #length=|v_#length_24|} OutVars{ULTIMATE.start_main_~#t405~0.offset=|v_ULTIMATE.start_main_~#t405~0.offset_15|, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_129, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_51|, #NULL.offset=|v_#NULL.offset_6|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_281|, ~a$r_buff0_thd0~0=v_~a$r_buff0_thd0~0_144, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_31|, ~a~0=v_~a~0_181, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_67|, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_92, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_37, #length=|v_#length_23|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_33, ULTIMATE.start_main_~#t405~0.base=|v_ULTIMATE.start_main_~#t405~0.base_17|, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_38, ~__unbuffered_p0_EBX~0=v_~__unbuffered_p0_EBX~0_92, ULTIMATE.start_main_~#t404~0.base=|v_ULTIMATE.start_main_~#t404~0.base_29|, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_10|, ~a$r_buff1_thd3~0=v_~a$r_buff1_thd3~0_224, ~a$w_buff0_used~0=v_~a$w_buff0_used~0_689, ~a$r_buff0_thd1~0=v_~a$r_buff0_thd1~0_195, ULTIMATE.start_main_~#t403~0.base=|v_ULTIMATE.start_main_~#t403~0.base_29|, ~weak$$choice0~0=v_~weak$$choice0~0_10, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ~a$read_delayed_var~0.offset=v_~a$read_delayed_var~0.offset_6, ~a$w_buff0~0=v_~a$w_buff0~0_228, ~a$r_buff1_thd0~0=v_~a$r_buff1_thd0~0_132, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_98, ~x~0=v_~x~0_69, ~a$read_delayed~0=v_~a$read_delayed~0_6, ~a$r_buff0_thd2~0=v_~a$r_buff0_thd2~0_124, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_36, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_55|, ~a$mem_tmp~0=v_~a$mem_tmp~0_12, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_45|, ~a$w_buff1~0=v_~a$w_buff1~0_172, ~y~0=v_~y~0_79, ULTIMATE.start_main_#t~nondet46=|v_ULTIMATE.start_main_#t~nondet46_27|, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_9|, ~a$r_buff1_thd1~0=v_~a$r_buff1_thd1~0_125, ~a$r_buff0_thd3~0=v_~a$r_buff0_thd3~0_328, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_28, #NULL.base=|v_#NULL.base_6|, ULTIMATE.start_main_~#t404~0.offset=|v_ULTIMATE.start_main_~#t404~0.offset_22|, ~a$flush_delayed~0=v_~a$flush_delayed~0_23, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, #valid=|v_#valid_62|, #memory_int=|v_#memory_int_21|, ULTIMATE.start_main_~#t403~0.offset=|v_ULTIMATE.start_main_~#t403~0.offset_22|, ~z~0=v_~z~0_20, ~a$w_buff1_used~0=v_~a$w_buff1_used~0_376, ~weak$$choice2~0=v_~weak$$choice2~0_107, ~a$read_delayed_var~0.base=v_~a$read_delayed_var~0.base_6} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t405~0.offset, ~a$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite49, ~a$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite50, ~a~0, ULTIMATE.start_main_#t~ite52, ~__unbuffered_p0_EAX~0, ~__unbuffered_p1_EAX~0, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_~#t405~0.base, ~__unbuffered_p2_EBX~0, ~__unbuffered_p0_EBX~0, ULTIMATE.start_main_~#t404~0.base, ULTIMATE.start_main_#t~nondet45, ~a$r_buff1_thd3~0, ~a$w_buff0_used~0, ~a$r_buff0_thd1~0, ULTIMATE.start_main_~#t403~0.base, ~weak$$choice0~0, ~a$read_delayed_var~0.offset, ~a$w_buff0~0, ~a$r_buff1_thd0~0, ~__unbuffered_cnt~0, ~x~0, ~a$read_delayed~0, ~a$r_buff0_thd2~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite48, ~a$mem_tmp~0, ULTIMATE.start_main_#t~ite51, ~a$w_buff1~0, ~y~0, ULTIMATE.start_main_#t~nondet46, ULTIMATE.start_main_#t~nondet44, ~a$r_buff1_thd1~0, ~a$r_buff0_thd3~0, ~main$tmp_guard0~0, #NULL.base, ULTIMATE.start_main_~#t404~0.offset, ~a$flush_delayed~0, ULTIMATE.start_main_#res, #valid, #memory_int, ULTIMATE.start_main_~#t403~0.offset, ~z~0, ~a$w_buff1_used~0, ~weak$$choice2~0, ~a$read_delayed_var~0.base] because there is no mapped edge [2019-12-07 13:48:27,299 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [865] [865] L837-1-->L839: Formula: (and (= |v_#length_13| (store |v_#length_14| |v_ULTIMATE.start_main_~#t404~0.base_12| 4)) (= |v_#memory_int_11| (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t404~0.base_12| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t404~0.base_12|) |v_ULTIMATE.start_main_~#t404~0.offset_10| 1))) (not (= |v_ULTIMATE.start_main_~#t404~0.base_12| 0)) (= |v_ULTIMATE.start_main_~#t404~0.offset_10| 0) (< |v_#StackHeapBarrier_9| |v_ULTIMATE.start_main_~#t404~0.base_12|) (= (store |v_#valid_35| |v_ULTIMATE.start_main_~#t404~0.base_12| 1) |v_#valid_34|) (= 0 (select |v_#valid_35| |v_ULTIMATE.start_main_~#t404~0.base_12|))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_12|, #length=|v_#length_14|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_9|, ULTIMATE.start_main_~#t404~0.offset=|v_ULTIMATE.start_main_~#t404~0.offset_10|, ULTIMATE.start_main_~#t404~0.base=|v_ULTIMATE.start_main_~#t404~0.base_12|, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_4|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_11|, #length=|v_#length_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t404~0.offset, ULTIMATE.start_main_~#t404~0.base, ULTIMATE.start_main_#t~nondet44, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 13:48:27,299 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [876] [876] L839-1-->L841: Formula: (and (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t405~0.base_13| 4)) (= |v_#valid_36| (store |v_#valid_37| |v_ULTIMATE.start_main_~#t405~0.base_13| 1)) (not (= 0 |v_ULTIMATE.start_main_~#t405~0.base_13|)) (= (select |v_#valid_37| |v_ULTIMATE.start_main_~#t405~0.base_13|) 0) (= 0 |v_ULTIMATE.start_main_~#t405~0.offset_11|) (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t405~0.base_13|) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t405~0.base_13| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t405~0.base_13|) |v_ULTIMATE.start_main_~#t405~0.offset_11| 2)) |v_#memory_int_13|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_37|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{ULTIMATE.start_main_~#t405~0.offset=|v_ULTIMATE.start_main_~#t405~0.offset_11|, #StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_36|, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_6|, #memory_int=|v_#memory_int_13|, #length=|v_#length_15|, ULTIMATE.start_main_~#t405~0.base=|v_ULTIMATE.start_main_~#t405~0.base_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t405~0.offset, #valid, ULTIMATE.start_main_#t~nondet45, #memory_int, #length, ULTIMATE.start_main_~#t405~0.base] because there is no mapped edge [2019-12-07 13:48:27,300 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [881] [881] L4-->L758: Formula: (and (= ~a$r_buff1_thd3~0_Out-909317594 ~a$r_buff0_thd3~0_In-909317594) (= ~x~0_Out-909317594 ~__unbuffered_p0_EAX~0_Out-909317594) (= 1 ~x~0_Out-909317594) (= ~y~0_In-909317594 ~__unbuffered_p0_EBX~0_Out-909317594) (not (= 0 P0Thread1of1ForFork1___VERIFIER_assert_~expression_In-909317594)) (= ~a$r_buff0_thd1~0_In-909317594 ~a$r_buff1_thd1~0_Out-909317594) (= ~a$r_buff1_thd0~0_Out-909317594 ~a$r_buff0_thd0~0_In-909317594) (= 1 ~a$r_buff0_thd1~0_Out-909317594) (= ~a$r_buff0_thd2~0_In-909317594 ~a$r_buff1_thd2~0_Out-909317594)) InVars {~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In-909317594, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-909317594, P0Thread1of1ForFork1___VERIFIER_assert_~expression=P0Thread1of1ForFork1___VERIFIER_assert_~expression_In-909317594, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In-909317594, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In-909317594, ~y~0=~y~0_In-909317594} OutVars{~__unbuffered_p0_EBX~0=~__unbuffered_p0_EBX~0_Out-909317594, ~a$r_buff1_thd1~0=~a$r_buff1_thd1~0_Out-909317594, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_Out-909317594, ~a$r_buff1_thd2~0=~a$r_buff1_thd2~0_Out-909317594, ~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In-909317594, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-909317594, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_Out-909317594, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In-909317594, ~__unbuffered_p0_EAX~0=~__unbuffered_p0_EAX~0_Out-909317594, ~a$r_buff1_thd0~0=~a$r_buff1_thd0~0_Out-909317594, P0Thread1of1ForFork1___VERIFIER_assert_~expression=P0Thread1of1ForFork1___VERIFIER_assert_~expression_In-909317594, ~y~0=~y~0_In-909317594, ~x~0=~x~0_Out-909317594} AuxVars[] AssignedVars[~__unbuffered_p0_EAX~0, ~__unbuffered_p0_EBX~0, ~a$r_buff1_thd1~0, ~a$r_buff1_thd3~0, ~a$r_buff1_thd2~0, ~a$r_buff1_thd0~0, ~a$r_buff0_thd1~0, ~x~0] because there is no mapped edge [2019-12-07 13:48:27,302 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [842] [842] L759-->L759-2: Formula: (let ((.cse0 (= (mod ~a$w_buff0_used~0_In201306404 256) 0)) (.cse1 (= 0 (mod ~a$r_buff0_thd1~0_In201306404 256)))) (or (and (not .cse0) (= 0 |P0Thread1of1ForFork1_#t~ite5_Out201306404|) (not .cse1)) (and (or .cse0 .cse1) (= ~a$w_buff0_used~0_In201306404 |P0Thread1of1ForFork1_#t~ite5_Out201306404|)))) InVars {~a$w_buff0_used~0=~a$w_buff0_used~0_In201306404, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In201306404} OutVars{P0Thread1of1ForFork1_#t~ite5=|P0Thread1of1ForFork1_#t~ite5_Out201306404|, ~a$w_buff0_used~0=~a$w_buff0_used~0_In201306404, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In201306404} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite5] because there is no mapped edge [2019-12-07 13:48:27,302 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [840] [840] L760-->L760-2: Formula: (let ((.cse1 (= (mod ~a$r_buff0_thd1~0_In-1766244926 256) 0)) (.cse0 (= 0 (mod ~a$w_buff0_used~0_In-1766244926 256))) (.cse2 (= 0 (mod ~a$w_buff1_used~0_In-1766244926 256))) (.cse3 (= (mod ~a$r_buff1_thd1~0_In-1766244926 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P0Thread1of1ForFork1_#t~ite6_Out-1766244926|)) (and (or .cse1 .cse0) (= ~a$w_buff1_used~0_In-1766244926 |P0Thread1of1ForFork1_#t~ite6_Out-1766244926|) (or .cse2 .cse3)))) InVars {~a$r_buff1_thd1~0=~a$r_buff1_thd1~0_In-1766244926, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1766244926, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In-1766244926, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1766244926} OutVars{P0Thread1of1ForFork1_#t~ite6=|P0Thread1of1ForFork1_#t~ite6_Out-1766244926|, ~a$r_buff1_thd1~0=~a$r_buff1_thd1~0_In-1766244926, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1766244926, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In-1766244926, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1766244926} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite6] because there is no mapped edge [2019-12-07 13:48:27,302 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [829] [829] L778-2-->L778-4: Formula: (let ((.cse1 (= 0 (mod ~a$r_buff1_thd2~0_In1319310668 256))) (.cse0 (= (mod ~a$w_buff1_used~0_In1319310668 256) 0))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork2_#t~ite9_Out1319310668| ~a~0_In1319310668)) (and (= |P1Thread1of1ForFork2_#t~ite9_Out1319310668| ~a$w_buff1~0_In1319310668) (not .cse1) (not .cse0)))) InVars {~a~0=~a~0_In1319310668, ~a$w_buff1~0=~a$w_buff1~0_In1319310668, ~a$r_buff1_thd2~0=~a$r_buff1_thd2~0_In1319310668, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1319310668} OutVars{~a~0=~a~0_In1319310668, P1Thread1of1ForFork2_#t~ite9=|P1Thread1of1ForFork2_#t~ite9_Out1319310668|, ~a$w_buff1~0=~a$w_buff1~0_In1319310668, ~a$r_buff1_thd2~0=~a$r_buff1_thd2~0_In1319310668, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1319310668} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite9] because there is no mapped edge [2019-12-07 13:48:27,302 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L778-4-->L779: Formula: (= |v_P1Thread1of1ForFork2_#t~ite9_10| v_~a~0_28) InVars {P1Thread1of1ForFork2_#t~ite9=|v_P1Thread1of1ForFork2_#t~ite9_10|} OutVars{~a~0=v_~a~0_28, P1Thread1of1ForFork2_#t~ite9=|v_P1Thread1of1ForFork2_#t~ite9_9|, P1Thread1of1ForFork2_#t~ite10=|v_P1Thread1of1ForFork2_#t~ite10_13|} AuxVars[] AssignedVars[~a~0, P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite10] because there is no mapped edge [2019-12-07 13:48:27,303 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [836] [836] L761-->L762: Formula: (let ((.cse1 (= (mod ~a$w_buff0_used~0_In-854895123 256) 0)) (.cse0 (= 0 (mod ~a$r_buff0_thd1~0_In-854895123 256))) (.cse2 (= ~a$r_buff0_thd1~0_Out-854895123 ~a$r_buff0_thd1~0_In-854895123))) (or (and (not .cse0) (not .cse1) (= ~a$r_buff0_thd1~0_Out-854895123 0)) (and .cse1 .cse2) (and .cse0 .cse2))) InVars {~a$w_buff0_used~0=~a$w_buff0_used~0_In-854895123, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In-854895123} OutVars{P0Thread1of1ForFork1_#t~ite7=|P0Thread1of1ForFork1_#t~ite7_Out-854895123|, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-854895123, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_Out-854895123} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite7, ~a$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 13:48:27,303 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [850] [850] L762-->L762-2: Formula: (let ((.cse1 (= (mod ~a$r_buff1_thd1~0_In1808458810 256) 0)) (.cse0 (= (mod ~a$w_buff1_used~0_In1808458810 256) 0)) (.cse3 (= (mod ~a$w_buff0_used~0_In1808458810 256) 0)) (.cse2 (= (mod ~a$r_buff0_thd1~0_In1808458810 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P0Thread1of1ForFork1_#t~ite8_Out1808458810| 0)) (and (= |P0Thread1of1ForFork1_#t~ite8_Out1808458810| ~a$r_buff1_thd1~0_In1808458810) (or .cse1 .cse0) (or .cse3 .cse2)))) InVars {~a$r_buff1_thd1~0=~a$r_buff1_thd1~0_In1808458810, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1808458810, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In1808458810, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1808458810} OutVars{P0Thread1of1ForFork1_#t~ite8=|P0Thread1of1ForFork1_#t~ite8_Out1808458810|, ~a$r_buff1_thd1~0=~a$r_buff1_thd1~0_In1808458810, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1808458810, ~a$r_buff0_thd1~0=~a$r_buff0_thd1~0_In1808458810, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1808458810} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite8] because there is no mapped edge [2019-12-07 13:48:27,303 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [860] [860] L762-2-->P0EXIT: Formula: (and (= 0 |v_P0Thread1of1ForFork1_#res.base_3|) (= v_~__unbuffered_cnt~0_49 (+ v_~__unbuffered_cnt~0_50 1)) (= 0 |v_P0Thread1of1ForFork1_#res.offset_3|) (= v_~a$r_buff1_thd1~0_63 |v_P0Thread1of1ForFork1_#t~ite8_34|)) InVars {P0Thread1of1ForFork1_#t~ite8=|v_P0Thread1of1ForFork1_#t~ite8_34|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_50} OutVars{P0Thread1of1ForFork1_#t~ite8=|v_P0Thread1of1ForFork1_#t~ite8_33|, P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_3|, ~a$r_buff1_thd1~0=v_~a$r_buff1_thd1~0_63, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_49} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite8, P0Thread1of1ForFork1_#res.offset, ~a$r_buff1_thd1~0, P0Thread1of1ForFork1_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 13:48:27,303 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [846] [846] L779-->L779-2: Formula: (let ((.cse0 (= 0 (mod ~a$w_buff0_used~0_In-671787214 256))) (.cse1 (= 0 (mod ~a$r_buff0_thd2~0_In-671787214 256)))) (or (and (= |P1Thread1of1ForFork2_#t~ite11_Out-671787214| ~a$w_buff0_used~0_In-671787214) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= |P1Thread1of1ForFork2_#t~ite11_Out-671787214| 0)))) InVars {~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In-671787214, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-671787214} OutVars{~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In-671787214, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-671787214, P1Thread1of1ForFork2_#t~ite11=|P1Thread1of1ForFork2_#t~ite11_Out-671787214|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite11] because there is no mapped edge [2019-12-07 13:48:27,303 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [880] [880] L803-->L803-8: Formula: (let ((.cse1 (= (mod ~weak$$choice2~0_In-1497378651 256) 0))) (or (and (= |P2Thread1of1ForFork0_#t~ite21_Out-1497378651| |P2Thread1of1ForFork0_#t~ite20_Out-1497378651|) (let ((.cse0 (= (mod ~a$r_buff0_thd3~0_In-1497378651 256) 0))) (or (and .cse0 (= (mod ~a$r_buff1_thd3~0_In-1497378651 256) 0)) (= 0 (mod ~a$w_buff0_used~0_In-1497378651 256)) (and .cse0 (= 0 (mod ~a$w_buff1_used~0_In-1497378651 256))))) .cse1 (= |P2Thread1of1ForFork0_#t~ite20_Out-1497378651| ~a$w_buff0~0_In-1497378651)) (and (= |P2Thread1of1ForFork0_#t~ite21_Out-1497378651| ~a$w_buff0~0_In-1497378651) (not .cse1) (= |P2Thread1of1ForFork0_#t~ite20_In-1497378651| |P2Thread1of1ForFork0_#t~ite20_Out-1497378651|)))) InVars {~a$w_buff0~0=~a$w_buff0~0_In-1497378651, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In-1497378651, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1497378651, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1497378651, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1497378651, P2Thread1of1ForFork0_#t~ite20=|P2Thread1of1ForFork0_#t~ite20_In-1497378651|, ~weak$$choice2~0=~weak$$choice2~0_In-1497378651} OutVars{P2Thread1of1ForFork0_#t~ite21=|P2Thread1of1ForFork0_#t~ite21_Out-1497378651|, ~a$w_buff0~0=~a$w_buff0~0_In-1497378651, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In-1497378651, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1497378651, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1497378651, P2Thread1of1ForFork0_#t~ite20=|P2Thread1of1ForFork0_#t~ite20_Out-1497378651|, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1497378651, ~weak$$choice2~0=~weak$$choice2~0_In-1497378651} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite21, P2Thread1of1ForFork0_#t~ite20] because there is no mapped edge [2019-12-07 13:48:27,304 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [884] [884] L804-->L804-8: Formula: (let ((.cse0 (= (mod ~weak$$choice2~0_In193267429 256) 0))) (or (and .cse0 (= ~a$w_buff1~0_In193267429 |P2Thread1of1ForFork0_#t~ite23_Out193267429|) (= |P2Thread1of1ForFork0_#t~ite24_Out193267429| |P2Thread1of1ForFork0_#t~ite23_Out193267429|) (let ((.cse1 (= 0 (mod ~a$r_buff0_thd3~0_In193267429 256)))) (or (= 0 (mod ~a$w_buff0_used~0_In193267429 256)) (and (= (mod ~a$w_buff1_used~0_In193267429 256) 0) .cse1) (and (= (mod ~a$r_buff1_thd3~0_In193267429 256) 0) .cse1)))) (and (= ~a$w_buff1~0_In193267429 |P2Thread1of1ForFork0_#t~ite24_Out193267429|) (= |P2Thread1of1ForFork0_#t~ite23_In193267429| |P2Thread1of1ForFork0_#t~ite23_Out193267429|) (not .cse0)))) InVars {~a$w_buff1~0=~a$w_buff1~0_In193267429, P2Thread1of1ForFork0_#t~ite23=|P2Thread1of1ForFork0_#t~ite23_In193267429|, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In193267429, ~a$w_buff0_used~0=~a$w_buff0_used~0_In193267429, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In193267429, ~a$w_buff1_used~0=~a$w_buff1_used~0_In193267429, ~weak$$choice2~0=~weak$$choice2~0_In193267429} OutVars{~a$w_buff1~0=~a$w_buff1~0_In193267429, P2Thread1of1ForFork0_#t~ite23=|P2Thread1of1ForFork0_#t~ite23_Out193267429|, P2Thread1of1ForFork0_#t~ite24=|P2Thread1of1ForFork0_#t~ite24_Out193267429|, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In193267429, ~a$w_buff0_used~0=~a$w_buff0_used~0_In193267429, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In193267429, ~a$w_buff1_used~0=~a$w_buff1_used~0_In193267429, ~weak$$choice2~0=~weak$$choice2~0_In193267429} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite23, P2Thread1of1ForFork0_#t~ite24] because there is no mapped edge [2019-12-07 13:48:27,304 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [883] [883] L805-->L805-8: Formula: (let ((.cse1 (= 0 (mod ~weak$$choice2~0_In-1723651070 256)))) (or (and (let ((.cse0 (= (mod ~a$r_buff0_thd3~0_In-1723651070 256) 0))) (or (and .cse0 (= (mod ~a$w_buff1_used~0_In-1723651070 256) 0)) (and .cse0 (= 0 (mod ~a$r_buff1_thd3~0_In-1723651070 256))) (= 0 (mod ~a$w_buff0_used~0_In-1723651070 256)))) (= |P2Thread1of1ForFork0_#t~ite27_Out-1723651070| |P2Thread1of1ForFork0_#t~ite26_Out-1723651070|) .cse1 (= ~a$w_buff0_used~0_In-1723651070 |P2Thread1of1ForFork0_#t~ite26_Out-1723651070|)) (and (= ~a$w_buff0_used~0_In-1723651070 |P2Thread1of1ForFork0_#t~ite27_Out-1723651070|) (= |P2Thread1of1ForFork0_#t~ite26_In-1723651070| |P2Thread1of1ForFork0_#t~ite26_Out-1723651070|) (not .cse1)))) InVars {P2Thread1of1ForFork0_#t~ite26=|P2Thread1of1ForFork0_#t~ite26_In-1723651070|, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In-1723651070, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1723651070, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1723651070, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1723651070, ~weak$$choice2~0=~weak$$choice2~0_In-1723651070} OutVars{P2Thread1of1ForFork0_#t~ite26=|P2Thread1of1ForFork0_#t~ite26_Out-1723651070|, P2Thread1of1ForFork0_#t~ite27=|P2Thread1of1ForFork0_#t~ite27_Out-1723651070|, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In-1723651070, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1723651070, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1723651070, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1723651070, ~weak$$choice2~0=~weak$$choice2~0_In-1723651070} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite26, P2Thread1of1ForFork0_#t~ite27] because there is no mapped edge [2019-12-07 13:48:27,305 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [768] [768] L807-->L808: Formula: (and (= v_~a$r_buff0_thd3~0_53 v_~a$r_buff0_thd3~0_52) (not (= 0 (mod v_~weak$$choice2~0_17 256)))) InVars {~a$r_buff0_thd3~0=v_~a$r_buff0_thd3~0_53, ~weak$$choice2~0=v_~weak$$choice2~0_17} OutVars{P2Thread1of1ForFork0_#t~ite33=|v_P2Thread1of1ForFork0_#t~ite33_5|, P2Thread1of1ForFork0_#t~ite32=|v_P2Thread1of1ForFork0_#t~ite32_5|, ~a$r_buff0_thd3~0=v_~a$r_buff0_thd3~0_52, P2Thread1of1ForFork0_#t~ite31=|v_P2Thread1of1ForFork0_#t~ite31_5|, ~weak$$choice2~0=v_~weak$$choice2~0_17} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite33, P2Thread1of1ForFork0_#t~ite32, ~a$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite31] because there is no mapped edge [2019-12-07 13:48:27,306 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L810-->L814: Formula: (and (not (= (mod v_~a$flush_delayed~0_7 256) 0)) (= v_~a~0_16 v_~a$mem_tmp~0_4) (= v_~a$flush_delayed~0_6 0)) InVars {~a$mem_tmp~0=v_~a$mem_tmp~0_4, ~a$flush_delayed~0=v_~a$flush_delayed~0_7} OutVars{P2Thread1of1ForFork0_#t~ite37=|v_P2Thread1of1ForFork0_#t~ite37_5|, ~a~0=v_~a~0_16, ~a$mem_tmp~0=v_~a$mem_tmp~0_4, ~a$flush_delayed~0=v_~a$flush_delayed~0_6} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite37, ~a~0, ~a$flush_delayed~0] because there is no mapped edge [2019-12-07 13:48:27,306 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [849] [849] L814-2-->L814-4: Formula: (let ((.cse0 (= 0 (mod ~a$w_buff1_used~0_In2088449369 256))) (.cse1 (= 0 (mod ~a$r_buff1_thd3~0_In2088449369 256)))) (or (and (= ~a~0_In2088449369 |P2Thread1of1ForFork0_#t~ite38_Out2088449369|) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= ~a$w_buff1~0_In2088449369 |P2Thread1of1ForFork0_#t~ite38_Out2088449369|)))) InVars {~a~0=~a~0_In2088449369, ~a$w_buff1~0=~a$w_buff1~0_In2088449369, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In2088449369, ~a$w_buff1_used~0=~a$w_buff1_used~0_In2088449369} OutVars{~a~0=~a~0_In2088449369, P2Thread1of1ForFork0_#t~ite38=|P2Thread1of1ForFork0_#t~ite38_Out2088449369|, ~a$w_buff1~0=~a$w_buff1~0_In2088449369, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In2088449369, ~a$w_buff1_used~0=~a$w_buff1_used~0_In2088449369} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite38] because there is no mapped edge [2019-12-07 13:48:27,306 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [783] [783] L814-4-->L815: Formula: (= v_~a~0_36 |v_P2Thread1of1ForFork0_#t~ite38_8|) InVars {P2Thread1of1ForFork0_#t~ite38=|v_P2Thread1of1ForFork0_#t~ite38_8|} OutVars{~a~0=v_~a~0_36, P2Thread1of1ForFork0_#t~ite39=|v_P2Thread1of1ForFork0_#t~ite39_11|, P2Thread1of1ForFork0_#t~ite38=|v_P2Thread1of1ForFork0_#t~ite38_7|} AuxVars[] AssignedVars[~a~0, P2Thread1of1ForFork0_#t~ite39, P2Thread1of1ForFork0_#t~ite38] because there is no mapped edge [2019-12-07 13:48:27,306 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [851] [851] L815-->L815-2: Formula: (let ((.cse0 (= (mod ~a$r_buff0_thd3~0_In-1083272070 256) 0)) (.cse1 (= 0 (mod ~a$w_buff0_used~0_In-1083272070 256)))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork0_#t~ite40_Out-1083272070| ~a$w_buff0_used~0_In-1083272070)) (and (not .cse0) (not .cse1) (= |P2Thread1of1ForFork0_#t~ite40_Out-1083272070| 0)))) InVars {~a$w_buff0_used~0=~a$w_buff0_used~0_In-1083272070, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1083272070} OutVars{P2Thread1of1ForFork0_#t~ite40=|P2Thread1of1ForFork0_#t~ite40_Out-1083272070|, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1083272070, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1083272070} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite40] because there is no mapped edge [2019-12-07 13:48:27,307 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [825] [825] L816-->L816-2: Formula: (let ((.cse1 (= (mod ~a$w_buff0_used~0_In-1925847367 256) 0)) (.cse0 (= 0 (mod ~a$r_buff0_thd3~0_In-1925847367 256))) (.cse2 (= (mod ~a$r_buff1_thd3~0_In-1925847367 256) 0)) (.cse3 (= (mod ~a$w_buff1_used~0_In-1925847367 256) 0))) (or (and (= |P2Thread1of1ForFork0_#t~ite41_Out-1925847367| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (or .cse2 .cse3) (= |P2Thread1of1ForFork0_#t~ite41_Out-1925847367| ~a$w_buff1_used~0_In-1925847367)))) InVars {~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In-1925847367, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1925847367, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1925847367, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1925847367} OutVars{~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In-1925847367, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1925847367, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In-1925847367, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1925847367, P2Thread1of1ForFork0_#t~ite41=|P2Thread1of1ForFork0_#t~ite41_Out-1925847367|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite41] because there is no mapped edge [2019-12-07 13:48:27,307 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [844] [844] L817-->L817-2: Formula: (let ((.cse1 (= (mod ~a$w_buff0_used~0_In1445510027 256) 0)) (.cse0 (= 0 (mod ~a$r_buff0_thd3~0_In1445510027 256)))) (or (and (not .cse0) (= 0 |P2Thread1of1ForFork0_#t~ite42_Out1445510027|) (not .cse1)) (and (or .cse1 .cse0) (= |P2Thread1of1ForFork0_#t~ite42_Out1445510027| ~a$r_buff0_thd3~0_In1445510027)))) InVars {~a$w_buff0_used~0=~a$w_buff0_used~0_In1445510027, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In1445510027} OutVars{~a$w_buff0_used~0=~a$w_buff0_used~0_In1445510027, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In1445510027, P2Thread1of1ForFork0_#t~ite42=|P2Thread1of1ForFork0_#t~ite42_Out1445510027|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite42] because there is no mapped edge [2019-12-07 13:48:27,308 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [828] [828] L818-->L818-2: Formula: (let ((.cse0 (= 0 (mod ~a$r_buff0_thd3~0_In1824585213 256))) (.cse1 (= (mod ~a$w_buff0_used~0_In1824585213 256) 0)) (.cse2 (= 0 (mod ~a$w_buff1_used~0_In1824585213 256))) (.cse3 (= 0 (mod ~a$r_buff1_thd3~0_In1824585213 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~a$r_buff1_thd3~0_In1824585213 |P2Thread1of1ForFork0_#t~ite43_Out1824585213|)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork0_#t~ite43_Out1824585213| 0)))) InVars {~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In1824585213, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1824585213, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In1824585213, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1824585213} OutVars{P2Thread1of1ForFork0_#t~ite43=|P2Thread1of1ForFork0_#t~ite43_Out1824585213|, ~a$r_buff1_thd3~0=~a$r_buff1_thd3~0_In1824585213, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1824585213, ~a$r_buff0_thd3~0=~a$r_buff0_thd3~0_In1824585213, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1824585213} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite43] because there is no mapped edge [2019-12-07 13:48:27,308 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [848] [848] L780-->L780-2: Formula: (let ((.cse2 (= (mod ~a$w_buff0_used~0_In-1345775623 256) 0)) (.cse3 (= 0 (mod ~a$r_buff0_thd2~0_In-1345775623 256))) (.cse1 (= 0 (mod ~a$w_buff1_used~0_In-1345775623 256))) (.cse0 (= 0 (mod ~a$r_buff1_thd2~0_In-1345775623 256)))) (or (and (= 0 |P1Thread1of1ForFork2_#t~ite12_Out-1345775623|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse2 .cse3) (= |P1Thread1of1ForFork2_#t~ite12_Out-1345775623| ~a$w_buff1_used~0_In-1345775623) (or .cse1 .cse0)))) InVars {~a$r_buff1_thd2~0=~a$r_buff1_thd2~0_In-1345775623, ~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In-1345775623, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1345775623, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1345775623} OutVars{~a$r_buff1_thd2~0=~a$r_buff1_thd2~0_In-1345775623, ~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In-1345775623, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1345775623, P1Thread1of1ForFork2_#t~ite12=|P1Thread1of1ForFork2_#t~ite12_Out-1345775623|, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1345775623} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite12] because there is no mapped edge [2019-12-07 13:48:27,308 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [838] [838] L781-->L781-2: Formula: (let ((.cse0 (= 0 (mod ~a$w_buff0_used~0_In136767720 256))) (.cse1 (= 0 (mod ~a$r_buff0_thd2~0_In136767720 256)))) (or (and (not .cse0) (not .cse1) (= 0 |P1Thread1of1ForFork2_#t~ite13_Out136767720|)) (and (or .cse0 .cse1) (= ~a$r_buff0_thd2~0_In136767720 |P1Thread1of1ForFork2_#t~ite13_Out136767720|)))) InVars {~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In136767720, ~a$w_buff0_used~0=~a$w_buff0_used~0_In136767720} OutVars{~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In136767720, ~a$w_buff0_used~0=~a$w_buff0_used~0_In136767720, P1Thread1of1ForFork2_#t~ite13=|P1Thread1of1ForFork2_#t~ite13_Out136767720|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite13] because there is no mapped edge [2019-12-07 13:48:27,309 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [837] [837] L782-->L782-2: Formula: (let ((.cse1 (= 0 (mod ~a$r_buff1_thd2~0_In1887932965 256))) (.cse0 (= 0 (mod ~a$w_buff1_used~0_In1887932965 256))) (.cse3 (= 0 (mod ~a$w_buff0_used~0_In1887932965 256))) (.cse2 (= 0 (mod ~a$r_buff0_thd2~0_In1887932965 256)))) (or (and (= |P1Thread1of1ForFork2_#t~ite14_Out1887932965| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (or .cse3 .cse2) (= |P1Thread1of1ForFork2_#t~ite14_Out1887932965| ~a$r_buff1_thd2~0_In1887932965)))) InVars {~a$r_buff1_thd2~0=~a$r_buff1_thd2~0_In1887932965, ~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In1887932965, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1887932965, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1887932965} OutVars{~a$r_buff1_thd2~0=~a$r_buff1_thd2~0_In1887932965, ~a$r_buff0_thd2~0=~a$r_buff0_thd2~0_In1887932965, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1887932965, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1887932965, P1Thread1of1ForFork2_#t~ite14=|P1Thread1of1ForFork2_#t~ite14_Out1887932965|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite14] because there is no mapped edge [2019-12-07 13:48:27,309 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [863] [863] L818-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= (+ v_~__unbuffered_cnt~0_56 1) v_~__unbuffered_cnt~0_55) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0) (= v_~a$r_buff1_thd3~0_123 |v_P2Thread1of1ForFork0_#t~ite43_32|)) InVars {P2Thread1of1ForFork0_#t~ite43=|v_P2Thread1of1ForFork0_#t~ite43_32|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_56} OutVars{P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, P2Thread1of1ForFork0_#t~ite43=|v_P2Thread1of1ForFork0_#t~ite43_31|, ~a$r_buff1_thd3~0=v_~a$r_buff1_thd3~0_123, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#res.base, P2Thread1of1ForFork0_#t~ite43, ~a$r_buff1_thd3~0, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 13:48:27,309 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [879] [879] L782-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= |v_P1Thread1of1ForFork2_#t~ite14_42| v_~a$r_buff1_thd2~0_99) (= (+ v_~__unbuffered_cnt~0_83 1) v_~__unbuffered_cnt~0_82)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_83, P1Thread1of1ForFork2_#t~ite14=|v_P1Thread1of1ForFork2_#t~ite14_42|} OutVars{P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, ~a$r_buff1_thd2~0=v_~a$r_buff1_thd2~0_99, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_82, P1Thread1of1ForFork2_#t~ite14=|v_P1Thread1of1ForFork2_#t~ite14_41|, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#res.offset, ~a$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#t~ite14, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-12-07 13:48:27,309 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [799] [799] L841-1-->L847: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_9 256))) (= v_~main$tmp_guard0~0_9 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_36) 1 0)) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_36} OutVars{ULTIMATE.start_main_#t~nondet46=|v_ULTIMATE.start_main_#t~nondet46_7|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_36, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_9} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet46, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 13:48:27,309 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [832] [832] L847-2-->L847-4: Formula: (let ((.cse1 (= 0 (mod ~a$r_buff1_thd0~0_In769446604 256))) (.cse0 (= 0 (mod ~a$w_buff1_used~0_In769446604 256)))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite47_Out769446604| ~a$w_buff1~0_In769446604) (not .cse1)) (and (= |ULTIMATE.start_main_#t~ite47_Out769446604| ~a~0_In769446604) (or .cse1 .cse0)))) InVars {~a~0=~a~0_In769446604, ~a$w_buff1~0=~a$w_buff1~0_In769446604, ~a$r_buff1_thd0~0=~a$r_buff1_thd0~0_In769446604, ~a$w_buff1_used~0=~a$w_buff1_used~0_In769446604} OutVars{~a~0=~a~0_In769446604, ~a$w_buff1~0=~a$w_buff1~0_In769446604, ULTIMATE.start_main_#t~ite47=|ULTIMATE.start_main_#t~ite47_Out769446604|, ~a$r_buff1_thd0~0=~a$r_buff1_thd0~0_In769446604, ~a$w_buff1_used~0=~a$w_buff1_used~0_In769446604} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47] because there is no mapped edge [2019-12-07 13:48:27,309 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [796] [796] L847-4-->L848: Formula: (= v_~a~0_44 |v_ULTIMATE.start_main_#t~ite47_19|) InVars {ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_19|} OutVars{~a~0=v_~a~0_44, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_18|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_16|} AuxVars[] AssignedVars[~a~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 13:48:27,309 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [826] [826] L848-->L848-2: Formula: (let ((.cse1 (= 0 (mod ~a$w_buff0_used~0_In1050417585 256))) (.cse0 (= 0 (mod ~a$r_buff0_thd0~0_In1050417585 256)))) (or (and (= |ULTIMATE.start_main_#t~ite49_Out1050417585| ~a$w_buff0_used~0_In1050417585) (or .cse0 .cse1)) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite49_Out1050417585| 0) (not .cse0)))) InVars {~a$w_buff0_used~0=~a$w_buff0_used~0_In1050417585, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In1050417585} OutVars{~a$w_buff0_used~0=~a$w_buff0_used~0_In1050417585, ULTIMATE.start_main_#t~ite49=|ULTIMATE.start_main_#t~ite49_Out1050417585|, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In1050417585} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite49] because there is no mapped edge [2019-12-07 13:48:27,310 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [831] [831] L849-->L849-2: Formula: (let ((.cse0 (= (mod ~a$w_buff1_used~0_In1266141171 256) 0)) (.cse1 (= (mod ~a$r_buff1_thd0~0_In1266141171 256) 0)) (.cse3 (= 0 (mod ~a$w_buff0_used~0_In1266141171 256))) (.cse2 (= 0 (mod ~a$r_buff0_thd0~0_In1266141171 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite50_Out1266141171|)) (and (= ~a$w_buff1_used~0_In1266141171 |ULTIMATE.start_main_#t~ite50_Out1266141171|) (or .cse0 .cse1) (or .cse3 .cse2)))) InVars {~a$r_buff1_thd0~0=~a$r_buff1_thd0~0_In1266141171, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1266141171, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In1266141171, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1266141171} OutVars{ULTIMATE.start_main_#t~ite50=|ULTIMATE.start_main_#t~ite50_Out1266141171|, ~a$r_buff1_thd0~0=~a$r_buff1_thd0~0_In1266141171, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1266141171, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In1266141171, ~a$w_buff1_used~0=~a$w_buff1_used~0_In1266141171} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite50] because there is no mapped edge [2019-12-07 13:48:27,310 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [830] [830] L850-->L850-2: Formula: (let ((.cse1 (= 0 (mod ~a$r_buff0_thd0~0_In1812785205 256))) (.cse0 (= (mod ~a$w_buff0_used~0_In1812785205 256) 0))) (or (and (= ~a$r_buff0_thd0~0_In1812785205 |ULTIMATE.start_main_#t~ite51_Out1812785205|) (or .cse0 .cse1)) (and (= 0 |ULTIMATE.start_main_#t~ite51_Out1812785205|) (not .cse1) (not .cse0)))) InVars {~a$w_buff0_used~0=~a$w_buff0_used~0_In1812785205, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In1812785205} OutVars{ULTIMATE.start_main_#t~ite51=|ULTIMATE.start_main_#t~ite51_Out1812785205|, ~a$w_buff0_used~0=~a$w_buff0_used~0_In1812785205, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In1812785205} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite51] because there is no mapped edge [2019-12-07 13:48:27,311 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [841] [841] L851-->L851-2: Formula: (let ((.cse0 (= 0 (mod ~a$r_buff1_thd0~0_In-1421356120 256))) (.cse1 (= (mod ~a$w_buff1_used~0_In-1421356120 256) 0)) (.cse2 (= 0 (mod ~a$w_buff0_used~0_In-1421356120 256))) (.cse3 (= (mod ~a$r_buff0_thd0~0_In-1421356120 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~a$r_buff1_thd0~0_In-1421356120 |ULTIMATE.start_main_#t~ite52_Out-1421356120|)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite52_Out-1421356120|)))) InVars {~a$r_buff1_thd0~0=~a$r_buff1_thd0~0_In-1421356120, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1421356120, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In-1421356120, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1421356120} OutVars{ULTIMATE.start_main_#t~ite52=|ULTIMATE.start_main_#t~ite52_Out-1421356120|, ~a$r_buff1_thd0~0=~a$r_buff1_thd0~0_In-1421356120, ~a$w_buff0_used~0=~a$w_buff0_used~0_In-1421356120, ~a$r_buff0_thd0~0=~a$r_buff0_thd0~0_In-1421356120, ~a$w_buff1_used~0=~a$w_buff1_used~0_In-1421356120} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52] because there is no mapped edge [2019-12-07 13:48:27,311 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [899] [899] L851-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_~a$r_buff1_thd0~0_125 |v_ULTIMATE.start_main_#t~ite52_55|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_22 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_16|) (= (mod v_~main$tmp_guard1~0_29 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_16|) (= v_~main$tmp_guard1~0_29 (ite (= (ite (not (and (= v_~__unbuffered_p2_EBX~0_29 0) (= 0 v_~__unbuffered_p1_EAX~0_28) (= 1 v_~__unbuffered_p2_EAX~0_26) (= v_~__unbuffered_p0_EBX~0_85 0) (= 1 v_~__unbuffered_p0_EAX~0_85))) 1 0) 0) 0 1)) (= v_ULTIMATE.start___VERIFIER_assert_~expression_22 0)) InVars {~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_85, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_55|, ~__unbuffered_p0_EBX~0=v_~__unbuffered_p0_EBX~0_85, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_29, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_28, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_26} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_85, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_54|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_22, ~__unbuffered_p0_EBX~0=v_~__unbuffered_p0_EBX~0_85, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_29, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_28, ~a$r_buff1_thd0~0=v_~a$r_buff1_thd0~0_125, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_29, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_26, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_16|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start___VERIFIER_assert_~expression, ~a$r_buff1_thd0~0, ~main$tmp_guard1~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 13:48:27,362 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_19f73177-67ff-40c3-8153-5de86a4e2c20/bin/uautomizer/witness.graphml [2019-12-07 13:48:27,362 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 13:48:27,363 INFO L168 Benchmark]: Toolchain (without parser) took 78555.73 ms. Allocated memory was 1.0 GB in the beginning and 6.7 GB in the end (delta: 5.6 GB). Free memory was 934.0 MB in the beginning and 4.4 GB in the end (delta: -3.4 GB). Peak memory consumption was 2.2 GB. Max. memory is 11.5 GB. [2019-12-07 13:48:27,364 INFO L168 Benchmark]: CDTParser took 0.21 ms. Allocated memory is still 1.0 GB. Free memory is still 955.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 13:48:27,364 INFO L168 Benchmark]: CACSL2BoogieTranslator took 390.62 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 92.8 MB). Free memory was 934.0 MB in the beginning and 1.1 GB in the end (delta: -130.5 MB). Peak memory consumption was 23.7 MB. Max. memory is 11.5 GB. [2019-12-07 13:48:27,364 INFO L168 Benchmark]: Boogie Procedure Inliner took 36.10 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 13:48:27,364 INFO L168 Benchmark]: Boogie Preprocessor took 25.02 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 13:48:27,364 INFO L168 Benchmark]: RCFGBuilder took 415.28 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 55.4 MB). Peak memory consumption was 55.4 MB. Max. memory is 11.5 GB. [2019-12-07 13:48:27,365 INFO L168 Benchmark]: TraceAbstraction took 77619.72 ms. Allocated memory was 1.1 GB in the beginning and 6.7 GB in the end (delta: 5.5 GB). Free memory was 998.3 MB in the beginning and 4.4 GB in the end (delta: -3.4 GB). Peak memory consumption was 2.1 GB. Max. memory is 11.5 GB. [2019-12-07 13:48:27,365 INFO L168 Benchmark]: Witness Printer took 65.81 ms. Allocated memory is still 6.7 GB. Free memory was 4.4 GB in the beginning and 4.4 GB in the end (delta: 20.5 MB). Peak memory consumption was 20.5 MB. Max. memory is 11.5 GB. [2019-12-07 13:48:27,366 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.21 ms. Allocated memory is still 1.0 GB. Free memory is still 955.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 390.62 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 92.8 MB). Free memory was 934.0 MB in the beginning and 1.1 GB in the end (delta: -130.5 MB). Peak memory consumption was 23.7 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 36.10 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 25.02 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 415.28 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 55.4 MB). Peak memory consumption was 55.4 MB. Max. memory is 11.5 GB. * TraceAbstraction took 77619.72 ms. Allocated memory was 1.1 GB in the beginning and 6.7 GB in the end (delta: 5.5 GB). Free memory was 998.3 MB in the beginning and 4.4 GB in the end (delta: -3.4 GB). Peak memory consumption was 2.1 GB. Max. memory is 11.5 GB. * Witness Printer took 65.81 ms. Allocated memory is still 6.7 GB. Free memory was 4.4 GB in the beginning and 4.4 GB in the end (delta: 20.5 MB). Peak memory consumption was 20.5 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.2s, 179 ProgramPointsBefore, 94 ProgramPointsAfterwards, 216 TransitionsBefore, 102 TransitionsAfterwards, 19004 CoEnabledTransitionPairs, 7 FixpointIterations, 36 TrivialSequentialCompositions, 48 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 32 ConcurrentYvCompositions, 33 ChoiceCompositions, 7151 VarBasedMoverChecksPositive, 221 VarBasedMoverChecksNegative, 29 SemBasedMoverChecksPositive, 258 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.8s, 0 MoverChecksTotal, 80759 CheckedPairsTotal, 116 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L837] FCALL, FORK 0 pthread_create(&t403, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff0_thd3=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$r_buff1_thd3=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0] [L839] FCALL, FORK 0 pthread_create(&t404, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff0_thd3=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$r_buff1_thd3=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0] [L841] FCALL, FORK 0 pthread_create(&t405, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=0, a$r_buff0_thd2=0, a$r_buff0_thd3=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$r_buff1_thd3=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=0, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0] [L737] 1 a$w_buff1 = a$w_buff0 [L738] 1 a$w_buff0 = 1 [L739] 1 a$w_buff1_used = a$w_buff0_used [L740] 1 a$w_buff0_used = (_Bool)1 [L758] EXPR 1 a$w_buff0_used && a$r_buff0_thd1 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd1 ? a$w_buff1 : a) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff0_thd3=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$r_buff1_thd3=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0] [L772] 2 y = 1 [L775] 2 __unbuffered_p1_EAX = z VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff0_thd3=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$r_buff1_thd3=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=0] [L778] 2 a$w_buff0_used && a$r_buff0_thd2 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd2 ? a$w_buff1 : a) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff0_thd3=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$r_buff1_thd3=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=0] [L792] 3 z = 1 [L795] 3 __unbuffered_p2_EAX = z [L798] 3 weak$$choice0 = __VERIFIER_nondet_bool() [L799] 3 weak$$choice2 = __VERIFIER_nondet_bool() [L800] 3 a$flush_delayed = weak$$choice2 [L801] 3 a$mem_tmp = a VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff0_thd3=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$r_buff1_thd3=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=1] [L802] EXPR 3 !a$w_buff0_used || !a$r_buff0_thd3 && !a$w_buff1_used || !a$r_buff0_thd3 && !a$r_buff1_thd3 ? a : (a$w_buff0_used && a$r_buff0_thd3 ? a$w_buff0 : a$w_buff1) VAL [!a$w_buff0_used || !a$r_buff0_thd3 && !a$w_buff1_used || !a$r_buff0_thd3 && !a$r_buff1_thd3 ? a : (a$w_buff0_used && a$r_buff0_thd3 ? a$w_buff0 : a$w_buff1)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff0_thd3=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$r_buff1_thd3=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=1, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=1] [L758] 1 a = a$w_buff0_used && a$r_buff0_thd1 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd1 ? a$w_buff1 : a) [L759] 1 a$w_buff0_used = a$w_buff0_used && a$r_buff0_thd1 ? (_Bool)0 : a$w_buff0_used [L760] 1 a$w_buff1_used = a$w_buff0_used && a$r_buff0_thd1 || a$w_buff1_used && a$r_buff1_thd1 ? (_Bool)0 : a$w_buff1_used [L802] 3 a = !a$w_buff0_used || !a$r_buff0_thd3 && !a$w_buff1_used || !a$r_buff0_thd3 && !a$r_buff1_thd3 ? a : (a$w_buff0_used && a$r_buff0_thd3 ? a$w_buff0 : a$w_buff1) [L803] 3 a$w_buff0 = weak$$choice2 ? a$w_buff0 : (!a$w_buff0_used || !a$r_buff0_thd3 && !a$w_buff1_used || !a$r_buff0_thd3 && !a$r_buff1_thd3 ? a$w_buff0 : (a$w_buff0_used && a$r_buff0_thd3 ? a$w_buff0 : a$w_buff0)) [L804] 3 a$w_buff1 = weak$$choice2 ? a$w_buff1 : (!a$w_buff0_used || !a$r_buff0_thd3 && !a$w_buff1_used || !a$r_buff0_thd3 && !a$r_buff1_thd3 ? a$w_buff1 : (a$w_buff0_used && a$r_buff0_thd3 ? a$w_buff1 : a$w_buff1)) [L805] 3 a$w_buff0_used = weak$$choice2 ? a$w_buff0_used : (!a$w_buff0_used || !a$r_buff0_thd3 && !a$w_buff1_used || !a$r_buff0_thd3 && !a$r_buff1_thd3 ? a$w_buff0_used : (a$w_buff0_used && a$r_buff0_thd3 ? (_Bool)0 : a$w_buff0_used)) [L806] EXPR 3 weak$$choice2 ? a$w_buff1_used : (!a$w_buff0_used || !a$r_buff0_thd3 && !a$w_buff1_used || !a$r_buff0_thd3 && !a$r_buff1_thd3 ? a$w_buff1_used : (a$w_buff0_used && a$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff0_thd3=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$r_buff1_thd3=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, weak$$choice2 ? a$w_buff1_used : (!a$w_buff0_used || !a$r_buff0_thd3 && !a$w_buff1_used || !a$r_buff0_thd3 && !a$r_buff1_thd3 ? a$w_buff1_used : (a$w_buff0_used && a$r_buff0_thd3 ? (_Bool)0 : (_Bool)0))=0, x=1, y=1, z=1] [L806] 3 a$w_buff1_used = weak$$choice2 ? a$w_buff1_used : (!a$w_buff0_used || !a$r_buff0_thd3 && !a$w_buff1_used || !a$r_buff0_thd3 && !a$r_buff1_thd3 ? a$w_buff1_used : (a$w_buff0_used && a$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) [L808] EXPR 3 weak$$choice2 ? a$r_buff1_thd3 : (!a$w_buff0_used || !a$r_buff0_thd3 && !a$w_buff1_used || !a$r_buff0_thd3 && !a$r_buff1_thd3 ? a$r_buff1_thd3 : (a$w_buff0_used && a$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff0_thd3=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$r_buff1_thd3=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, weak$$choice2 ? a$r_buff1_thd3 : (!a$w_buff0_used || !a$r_buff0_thd3 && !a$w_buff1_used || !a$r_buff0_thd3 && !a$r_buff1_thd3 ? a$r_buff1_thd3 : (a$w_buff0_used && a$r_buff0_thd3 ? (_Bool)0 : (_Bool)0))=0, x=1, y=1, z=1] [L808] 3 a$r_buff1_thd3 = weak$$choice2 ? a$r_buff1_thd3 : (!a$w_buff0_used || !a$r_buff0_thd3 && !a$w_buff1_used || !a$r_buff0_thd3 && !a$r_buff1_thd3 ? a$r_buff1_thd3 : (a$w_buff0_used && a$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) [L809] 3 __unbuffered_p2_EBX = a VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=0, a$flush_delayed=1, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff0_thd3=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$r_buff1_thd3=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=1] [L814] 3 a$w_buff0_used && a$r_buff0_thd3 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd3 ? a$w_buff1 : a) VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff0_thd3=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$r_buff1_thd3=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=1] [L815] 3 a$w_buff0_used = a$w_buff0_used && a$r_buff0_thd3 ? (_Bool)0 : a$w_buff0_used [L816] 3 a$w_buff1_used = a$w_buff0_used && a$r_buff0_thd3 || a$w_buff1_used && a$r_buff1_thd3 ? (_Bool)0 : a$w_buff1_used [L817] 3 a$r_buff0_thd3 = a$w_buff0_used && a$r_buff0_thd3 ? (_Bool)0 : a$r_buff0_thd3 [L779] 2 a$w_buff0_used = a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$w_buff0_used [L780] 2 a$w_buff1_used = a$w_buff0_used && a$r_buff0_thd2 || a$w_buff1_used && a$r_buff1_thd2 ? (_Bool)0 : a$w_buff1_used [L781] 2 a$r_buff0_thd2 = a$w_buff0_used && a$r_buff0_thd2 ? (_Bool)0 : a$r_buff0_thd2 [L847] 0 a$w_buff0_used && a$r_buff0_thd0 ? a$w_buff0 : (a$w_buff1_used && a$r_buff1_thd0 ? a$w_buff1 : a) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p0_EBX=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, a=0, a$flush_delayed=0, a$mem_tmp=0, a$r_buff0_thd0=0, a$r_buff0_thd1=1, a$r_buff0_thd2=0, a$r_buff0_thd3=0, a$r_buff1_thd0=0, a$r_buff1_thd1=0, a$r_buff1_thd2=0, a$r_buff1_thd3=0, a$read_delayed=0, a$read_delayed_var={0:0}, a$w_buff0=1, a$w_buff0_used=0, a$w_buff1=0, a$w_buff1_used=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=1, y=1, z=1] [L848] 0 a$w_buff0_used = a$w_buff0_used && a$r_buff0_thd0 ? (_Bool)0 : a$w_buff0_used [L849] 0 a$w_buff1_used = a$w_buff0_used && a$r_buff0_thd0 || a$w_buff1_used && a$r_buff1_thd0 ? (_Bool)0 : a$w_buff1_used [L850] 0 a$r_buff0_thd0 = a$w_buff0_used && a$r_buff0_thd0 ? (_Bool)0 : a$r_buff0_thd0 - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 170 locations, 2 error locations. Result: UNSAFE, OverallTime: 77.4s, OverallIterations: 36, TraceHistogramMax: 1, AutomataDifference: 21.6s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 7489 SDtfs, 10391 SDslu, 24974 SDs, 0 SdLazy, 14929 SolverSat, 494 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 9.7s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 449 GetRequests, 54 SyntacticMatches, 27 SemanticMatches, 368 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1450 ImplicationChecksByTransitivity, 3.9s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=156295occurred in iteration=2, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 34.1s AutomataMinimizationTime, 35 MinimizatonAttempts, 294936 StatesRemovedByMinimization, 30 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 2.1s InterpolantComputationTime, 1598 NumberOfCodeBlocks, 1598 NumberOfCodeBlocksAsserted, 36 NumberOfCheckSat, 1496 ConstructedInterpolants, 0 QuantifiedInterpolants, 596251 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 35 InterpolantComputations, 35 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...