./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/mix019_rmo.oepc.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_62a55107-5fa3-4010-b348-791676e8ae59/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_62a55107-5fa3-4010-b348-791676e8ae59/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_62a55107-5fa3-4010-b348-791676e8ae59/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_62a55107-5fa3-4010-b348-791676e8ae59/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/mix019_rmo.oepc.i -s /tmp/vcloud-vcloud-master/worker/run_dir_62a55107-5fa3-4010-b348-791676e8ae59/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_62a55107-5fa3-4010-b348-791676e8ae59/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash cf06a9878c8fdff64dcf95151b201b0211e1b7a9 .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 18:59:22,995 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 18:59:22,996 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 18:59:23,004 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 18:59:23,004 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 18:59:23,005 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 18:59:23,006 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 18:59:23,007 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 18:59:23,008 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 18:59:23,009 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 18:59:23,009 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 18:59:23,010 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 18:59:23,010 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 18:59:23,011 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 18:59:23,012 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 18:59:23,013 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 18:59:23,013 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 18:59:23,014 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 18:59:23,015 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 18:59:23,017 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 18:59:23,018 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 18:59:23,018 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 18:59:23,019 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 18:59:23,020 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 18:59:23,021 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 18:59:23,021 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 18:59:23,022 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 18:59:23,022 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 18:59:23,022 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 18:59:23,023 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 18:59:23,023 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 18:59:23,023 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 18:59:23,024 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 18:59:23,024 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 18:59:23,025 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 18:59:23,025 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 18:59:23,025 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 18:59:23,025 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 18:59:23,026 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 18:59:23,026 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 18:59:23,026 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 18:59:23,027 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_62a55107-5fa3-4010-b348-791676e8ae59/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 18:59:23,036 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 18:59:23,036 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 18:59:23,036 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 18:59:23,037 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 18:59:23,037 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 18:59:23,037 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 18:59:23,037 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 18:59:23,037 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 18:59:23,037 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 18:59:23,037 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 18:59:23,037 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 18:59:23,038 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 18:59:23,038 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 18:59:23,038 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 18:59:23,038 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 18:59:23,038 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 18:59:23,038 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 18:59:23,038 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 18:59:23,038 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 18:59:23,038 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 18:59:23,039 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 18:59:23,039 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:59:23,039 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 18:59:23,039 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 18:59:23,039 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 18:59:23,039 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 18:59:23,039 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 18:59:23,039 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 18:59:23,040 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 18:59:23,040 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_62a55107-5fa3-4010-b348-791676e8ae59/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> cf06a9878c8fdff64dcf95151b201b0211e1b7a9 [2019-12-07 18:59:23,141 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 18:59:23,148 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 18:59:23,151 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 18:59:23,151 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 18:59:23,152 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 18:59:23,152 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_62a55107-5fa3-4010-b348-791676e8ae59/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/mix019_rmo.oepc.i [2019-12-07 18:59:23,190 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_62a55107-5fa3-4010-b348-791676e8ae59/bin/uautomizer/data/b64cf921b/e888b374d6e346358b84b178aea64bea/FLAG36307af6e [2019-12-07 18:59:23,639 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 18:59:23,640 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_62a55107-5fa3-4010-b348-791676e8ae59/sv-benchmarks/c/pthread-wmm/mix019_rmo.oepc.i [2019-12-07 18:59:23,650 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_62a55107-5fa3-4010-b348-791676e8ae59/bin/uautomizer/data/b64cf921b/e888b374d6e346358b84b178aea64bea/FLAG36307af6e [2019-12-07 18:59:23,658 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_62a55107-5fa3-4010-b348-791676e8ae59/bin/uautomizer/data/b64cf921b/e888b374d6e346358b84b178aea64bea [2019-12-07 18:59:23,660 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 18:59:23,661 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 18:59:23,662 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 18:59:23,662 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 18:59:23,664 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 18:59:23,665 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:59:23" (1/1) ... [2019-12-07 18:59:23,667 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@25138a46 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:23, skipping insertion in model container [2019-12-07 18:59:23,667 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:59:23" (1/1) ... [2019-12-07 18:59:23,671 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 18:59:23,699 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 18:59:23,966 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:59:23,974 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 18:59:24,017 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:59:24,063 INFO L208 MainTranslator]: Completed translation [2019-12-07 18:59:24,064 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:24 WrapperNode [2019-12-07 18:59:24,064 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 18:59:24,064 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 18:59:24,064 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 18:59:24,064 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 18:59:24,070 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:24" (1/1) ... [2019-12-07 18:59:24,083 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:24" (1/1) ... [2019-12-07 18:59:24,101 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 18:59:24,102 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 18:59:24,102 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 18:59:24,102 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 18:59:24,108 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:24" (1/1) ... [2019-12-07 18:59:24,108 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:24" (1/1) ... [2019-12-07 18:59:24,111 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:24" (1/1) ... [2019-12-07 18:59:24,112 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:24" (1/1) ... [2019-12-07 18:59:24,119 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:24" (1/1) ... [2019-12-07 18:59:24,121 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:24" (1/1) ... [2019-12-07 18:59:24,124 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:24" (1/1) ... [2019-12-07 18:59:24,127 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 18:59:24,127 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 18:59:24,127 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 18:59:24,128 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 18:59:24,128 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:24" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_62a55107-5fa3-4010-b348-791676e8ae59/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:59:24,168 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 18:59:24,168 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 18:59:24,168 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 18:59:24,169 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 18:59:24,169 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 18:59:24,169 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 18:59:24,169 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 18:59:24,169 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 18:59:24,169 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 18:59:24,169 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 18:59:24,169 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 18:59:24,169 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 18:59:24,169 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 18:59:24,170 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 18:59:24,539 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 18:59:24,539 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 18:59:24,540 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:59:24 BoogieIcfgContainer [2019-12-07 18:59:24,540 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 18:59:24,541 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 18:59:24,541 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 18:59:24,543 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 18:59:24,543 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 06:59:23" (1/3) ... [2019-12-07 18:59:24,543 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@43c51ec7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:59:24, skipping insertion in model container [2019-12-07 18:59:24,543 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:59:24" (2/3) ... [2019-12-07 18:59:24,544 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@43c51ec7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:59:24, skipping insertion in model container [2019-12-07 18:59:24,544 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:59:24" (3/3) ... [2019-12-07 18:59:24,545 INFO L109 eAbstractionObserver]: Analyzing ICFG mix019_rmo.oepc.i [2019-12-07 18:59:24,551 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 18:59:24,551 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 18:59:24,556 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 18:59:24,557 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 18:59:24,581 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,581 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,582 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,582 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,582 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,582 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,582 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,582 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,582 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,583 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,583 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,583 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,583 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,583 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,583 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,583 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,584 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,584 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,584 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,584 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,584 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,584 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,584 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,584 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,585 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,585 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,585 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,585 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,585 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,585 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,585 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,585 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,586 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,586 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,586 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,586 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,587 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,587 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,587 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,587 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,587 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,587 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,588 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,588 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,588 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,588 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,588 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,589 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,589 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,589 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,589 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,589 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,590 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,590 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,590 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,590 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,590 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,590 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,590 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,590 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,591 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,591 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,591 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,591 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,592 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,592 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,592 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,592 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,592 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,592 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,593 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,593 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,593 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,593 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,593 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,593 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,594 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,594 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,594 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,594 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,594 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,594 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,595 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,595 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,595 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,595 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,595 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,595 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,595 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,596 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,596 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,596 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,596 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,596 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,596 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,596 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,597 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,597 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,597 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,597 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,597 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,597 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,598 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,598 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,598 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,598 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,598 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,598 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,598 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,599 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,599 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,599 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,599 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,599 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,599 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,600 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,600 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,600 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,600 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,600 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,600 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,600 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,600 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,600 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,601 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,601 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,601 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,601 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,601 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,601 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,601 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,601 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,601 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,601 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,602 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,602 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,602 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,602 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,602 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,602 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,603 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,603 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,603 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,603 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,603 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,603 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,603 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,603 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,604 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,604 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,604 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,604 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,604 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,604 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,604 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,604 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,604 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,604 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,604 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,605 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,605 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,605 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,605 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,605 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,605 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,605 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,605 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,605 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,605 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,606 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,606 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,606 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,606 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,606 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,606 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,606 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,607 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,607 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,607 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,607 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,607 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,607 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:59:24,618 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 18:59:24,631 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 18:59:24,631 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 18:59:24,631 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 18:59:24,631 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 18:59:24,631 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 18:59:24,631 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 18:59:24,631 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 18:59:24,631 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 18:59:24,644 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 176 places, 213 transitions [2019-12-07 18:59:24,645 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 176 places, 213 transitions [2019-12-07 18:59:24,712 INFO L134 PetriNetUnfolder]: 47/210 cut-off events. [2019-12-07 18:59:24,712 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:59:24,723 INFO L76 FinitePrefix]: Finished finitePrefix Result has 220 conditions, 210 events. 47/210 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 704 event pairs. 9/170 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 18:59:24,739 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 176 places, 213 transitions [2019-12-07 18:59:24,777 INFO L134 PetriNetUnfolder]: 47/210 cut-off events. [2019-12-07 18:59:24,777 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:59:24,783 INFO L76 FinitePrefix]: Finished finitePrefix Result has 220 conditions, 210 events. 47/210 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 704 event pairs. 9/170 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 18:59:24,800 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 19004 [2019-12-07 18:59:24,800 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 18:59:27,627 WARN L192 SmtUtils]: Spent 157.00 ms on a formula simplification. DAG size of input: 91 DAG size of output: 89 [2019-12-07 18:59:27,870 INFO L206 etLargeBlockEncoding]: Checked pairs total: 130103 [2019-12-07 18:59:27,871 INFO L214 etLargeBlockEncoding]: Total number of compositions: 120 [2019-12-07 18:59:27,873 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 94 places, 105 transitions [2019-12-07 18:59:45,360 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 122102 states. [2019-12-07 18:59:45,362 INFO L276 IsEmpty]: Start isEmpty. Operand 122102 states. [2019-12-07 18:59:45,365 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-12-07 18:59:45,365 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:59:45,366 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-12-07 18:59:45,366 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:59:45,370 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:59:45,370 INFO L82 PathProgramCache]: Analyzing trace with hash 913940, now seen corresponding path program 1 times [2019-12-07 18:59:45,375 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:59:45,375 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [668380721] [2019-12-07 18:59:45,375 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:59:45,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:59:45,570 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:59:45,571 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [668380721] [2019-12-07 18:59:45,571 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:59:45,571 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 18:59:45,572 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1993457869] [2019-12-07 18:59:45,575 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:59:45,575 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:59:45,584 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:59:45,584 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:59:45,585 INFO L87 Difference]: Start difference. First operand 122102 states. Second operand 3 states. [2019-12-07 18:59:46,336 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:59:46,337 INFO L93 Difference]: Finished difference Result 121140 states and 517588 transitions. [2019-12-07 18:59:46,337 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:59:46,338 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2019-12-07 18:59:46,338 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:59:46,758 INFO L225 Difference]: With dead ends: 121140 [2019-12-07 18:59:46,758 INFO L226 Difference]: Without dead ends: 107958 [2019-12-07 18:59:46,759 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:59:50,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107958 states. [2019-12-07 18:59:52,196 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107958 to 107958. [2019-12-07 18:59:52,197 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 107958 states. [2019-12-07 18:59:54,675 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 107958 states to 107958 states and 460128 transitions. [2019-12-07 18:59:54,676 INFO L78 Accepts]: Start accepts. Automaton has 107958 states and 460128 transitions. Word has length 3 [2019-12-07 18:59:54,677 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:59:54,677 INFO L462 AbstractCegarLoop]: Abstraction has 107958 states and 460128 transitions. [2019-12-07 18:59:54,677 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:59:54,677 INFO L276 IsEmpty]: Start isEmpty. Operand 107958 states and 460128 transitions. [2019-12-07 18:59:54,680 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-12-07 18:59:54,680 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:59:54,680 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:59:54,680 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:59:54,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:59:54,680 INFO L82 PathProgramCache]: Analyzing trace with hash 2082409598, now seen corresponding path program 1 times [2019-12-07 18:59:54,681 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:59:54,681 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2037869252] [2019-12-07 18:59:54,681 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:59:54,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:59:54,741 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:59:54,741 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2037869252] [2019-12-07 18:59:54,742 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:59:54,742 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:59:54,742 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1981873586] [2019-12-07 18:59:54,743 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:59:54,743 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:59:54,743 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:59:54,743 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:59:54,743 INFO L87 Difference]: Start difference. First operand 107958 states and 460128 transitions. Second operand 4 states. [2019-12-07 18:59:55,684 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:59:55,684 INFO L93 Difference]: Finished difference Result 172022 states and 703369 transitions. [2019-12-07 18:59:55,685 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:59:55,685 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-12-07 18:59:55,685 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:59:56,123 INFO L225 Difference]: With dead ends: 172022 [2019-12-07 18:59:56,123 INFO L226 Difference]: Without dead ends: 171924 [2019-12-07 18:59:56,124 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:00:00,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171924 states. [2019-12-07 19:00:03,120 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171924 to 156115. [2019-12-07 19:00:03,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 156115 states. [2019-12-07 19:00:03,573 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156115 states to 156115 states and 647087 transitions. [2019-12-07 19:00:03,574 INFO L78 Accepts]: Start accepts. Automaton has 156115 states and 647087 transitions. Word has length 11 [2019-12-07 19:00:03,574 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:03,574 INFO L462 AbstractCegarLoop]: Abstraction has 156115 states and 647087 transitions. [2019-12-07 19:00:03,574 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 19:00:03,574 INFO L276 IsEmpty]: Start isEmpty. Operand 156115 states and 647087 transitions. [2019-12-07 19:00:03,579 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 19:00:03,579 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:03,580 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:03,580 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:03,580 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:03,580 INFO L82 PathProgramCache]: Analyzing trace with hash 594088235, now seen corresponding path program 1 times [2019-12-07 19:00:03,580 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:03,580 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [502019881] [2019-12-07 19:00:03,580 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:03,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:03,636 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:03,636 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [502019881] [2019-12-07 19:00:03,636 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:03,636 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:03,636 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [512499558] [2019-12-07 19:00:03,636 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 19:00:03,637 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:03,637 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 19:00:03,637 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 19:00:03,637 INFO L87 Difference]: Start difference. First operand 156115 states and 647087 transitions. Second operand 4 states. [2019-12-07 19:00:06,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:06,424 INFO L93 Difference]: Finished difference Result 219290 states and 888852 transitions. [2019-12-07 19:00:06,425 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 19:00:06,425 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 19:00:06,425 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:07,000 INFO L225 Difference]: With dead ends: 219290 [2019-12-07 19:00:07,000 INFO L226 Difference]: Without dead ends: 219178 [2019-12-07 19:00:07,001 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:00:12,193 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 219178 states. [2019-12-07 19:00:14,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 219178 to 184451. [2019-12-07 19:00:14,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 184451 states. [2019-12-07 19:00:15,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 184451 states to 184451 states and 760798 transitions. [2019-12-07 19:00:15,278 INFO L78 Accepts]: Start accepts. Automaton has 184451 states and 760798 transitions. Word has length 13 [2019-12-07 19:00:15,279 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:15,279 INFO L462 AbstractCegarLoop]: Abstraction has 184451 states and 760798 transitions. [2019-12-07 19:00:15,279 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 19:00:15,279 INFO L276 IsEmpty]: Start isEmpty. Operand 184451 states and 760798 transitions. [2019-12-07 19:00:15,286 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2019-12-07 19:00:15,286 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:15,286 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:15,286 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:15,287 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:15,287 INFO L82 PathProgramCache]: Analyzing trace with hash -805978823, now seen corresponding path program 1 times [2019-12-07 19:00:15,287 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:15,287 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1449763851] [2019-12-07 19:00:15,287 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:15,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:15,314 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:15,314 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1449763851] [2019-12-07 19:00:15,315 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:15,315 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 19:00:15,315 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [623829699] [2019-12-07 19:00:15,315 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:00:15,315 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:15,315 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:00:15,315 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:15,315 INFO L87 Difference]: Start difference. First operand 184451 states and 760798 transitions. Second operand 3 states. [2019-12-07 19:00:16,493 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:16,493 INFO L93 Difference]: Finished difference Result 284614 states and 1168466 transitions. [2019-12-07 19:00:16,494 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:00:16,494 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 16 [2019-12-07 19:00:16,495 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:19,912 INFO L225 Difference]: With dead ends: 284614 [2019-12-07 19:00:19,912 INFO L226 Difference]: Without dead ends: 284614 [2019-12-07 19:00:19,912 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:00:25,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284614 states. [2019-12-07 19:00:28,983 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284614 to 221232. [2019-12-07 19:00:28,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 221232 states. [2019-12-07 19:00:29,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 221232 states to 221232 states and 911865 transitions. [2019-12-07 19:00:29,654 INFO L78 Accepts]: Start accepts. Automaton has 221232 states and 911865 transitions. Word has length 16 [2019-12-07 19:00:29,654 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:29,654 INFO L462 AbstractCegarLoop]: Abstraction has 221232 states and 911865 transitions. [2019-12-07 19:00:29,654 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:00:29,655 INFO L276 IsEmpty]: Start isEmpty. Operand 221232 states and 911865 transitions. [2019-12-07 19:00:29,661 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2019-12-07 19:00:29,661 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:29,661 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:29,661 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:29,662 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:29,662 INFO L82 PathProgramCache]: Analyzing trace with hash -805853304, now seen corresponding path program 1 times [2019-12-07 19:00:29,662 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:29,662 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [848188312] [2019-12-07 19:00:29,662 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:29,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:29,699 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:29,699 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [848188312] [2019-12-07 19:00:29,699 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:29,699 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:29,699 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [487097846] [2019-12-07 19:00:29,700 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 19:00:29,700 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:29,700 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 19:00:29,700 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 19:00:29,700 INFO L87 Difference]: Start difference. First operand 221232 states and 911865 transitions. Second operand 4 states. [2019-12-07 19:00:30,978 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:30,979 INFO L93 Difference]: Finished difference Result 262568 states and 1070974 transitions. [2019-12-07 19:00:30,979 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 19:00:30,979 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2019-12-07 19:00:30,979 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:32,279 INFO L225 Difference]: With dead ends: 262568 [2019-12-07 19:00:32,279 INFO L226 Difference]: Without dead ends: 262568 [2019-12-07 19:00:32,280 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:00:38,197 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 262568 states. [2019-12-07 19:00:44,525 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 262568 to 233184. [2019-12-07 19:00:44,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 233184 states. [2019-12-07 19:00:45,209 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 233184 states to 233184 states and 959818 transitions. [2019-12-07 19:00:45,210 INFO L78 Accepts]: Start accepts. Automaton has 233184 states and 959818 transitions. Word has length 16 [2019-12-07 19:00:45,210 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:00:45,210 INFO L462 AbstractCegarLoop]: Abstraction has 233184 states and 959818 transitions. [2019-12-07 19:00:45,210 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 19:00:45,210 INFO L276 IsEmpty]: Start isEmpty. Operand 233184 states and 959818 transitions. [2019-12-07 19:00:45,218 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2019-12-07 19:00:45,218 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:00:45,218 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:00:45,218 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:00:45,219 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:00:45,219 INFO L82 PathProgramCache]: Analyzing trace with hash -1222928522, now seen corresponding path program 1 times [2019-12-07 19:00:45,219 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:00:45,219 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [831569716] [2019-12-07 19:00:45,219 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:00:45,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:00:45,256 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:00:45,257 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [831569716] [2019-12-07 19:00:45,257 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:00:45,257 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:00:45,257 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [940667818] [2019-12-07 19:00:45,257 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 19:00:45,257 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:00:45,258 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 19:00:45,258 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 19:00:45,258 INFO L87 Difference]: Start difference. First operand 233184 states and 959818 transitions. Second operand 4 states. [2019-12-07 19:00:46,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:00:46,984 INFO L93 Difference]: Finished difference Result 277148 states and 1134062 transitions. [2019-12-07 19:00:46,984 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 19:00:46,985 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2019-12-07 19:00:46,985 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:00:47,687 INFO L225 Difference]: With dead ends: 277148 [2019-12-07 19:00:47,687 INFO L226 Difference]: Without dead ends: 277148 [2019-12-07 19:00:47,687 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:00:53,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 277148 states. [2019-12-07 19:00:59,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 277148 to 236057. [2019-12-07 19:00:59,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 236057 states. [2019-12-07 19:01:00,224 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 236057 states to 236057 states and 972653 transitions. [2019-12-07 19:01:00,224 INFO L78 Accepts]: Start accepts. Automaton has 236057 states and 972653 transitions. Word has length 16 [2019-12-07 19:01:00,225 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:01:00,225 INFO L462 AbstractCegarLoop]: Abstraction has 236057 states and 972653 transitions. [2019-12-07 19:01:00,225 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 19:01:00,225 INFO L276 IsEmpty]: Start isEmpty. Operand 236057 states and 972653 transitions. [2019-12-07 19:01:00,236 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2019-12-07 19:01:00,236 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:01:00,236 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:01:00,236 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:01:00,237 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:01:00,237 INFO L82 PathProgramCache]: Analyzing trace with hash -2141168645, now seen corresponding path program 1 times [2019-12-07 19:01:00,237 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:01:00,237 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [594840446] [2019-12-07 19:01:00,237 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:01:00,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:01:00,282 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:01:00,282 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [594840446] [2019-12-07 19:01:00,282 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:01:00,282 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 19:01:00,282 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [474679207] [2019-12-07 19:01:00,282 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:01:00,283 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:01:00,283 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:01:00,283 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:01:00,283 INFO L87 Difference]: Start difference. First operand 236057 states and 972653 transitions. Second operand 3 states. [2019-12-07 19:01:02,531 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:01:02,532 INFO L93 Difference]: Finished difference Result 426567 states and 1746949 transitions. [2019-12-07 19:01:02,532 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:01:02,532 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 18 [2019-12-07 19:01:02,532 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:01:04,102 INFO L225 Difference]: With dead ends: 426567 [2019-12-07 19:01:04,102 INFO L226 Difference]: Without dead ends: 388856 [2019-12-07 19:01:04,102 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:01:14,207 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 388856 states. [2019-12-07 19:01:19,520 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 388856 to 372573. [2019-12-07 19:01:19,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 372573 states. [2019-12-07 19:01:21,037 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 372573 states to 372573 states and 1538118 transitions. [2019-12-07 19:01:21,037 INFO L78 Accepts]: Start accepts. Automaton has 372573 states and 1538118 transitions. Word has length 18 [2019-12-07 19:01:21,037 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:01:21,037 INFO L462 AbstractCegarLoop]: Abstraction has 372573 states and 1538118 transitions. [2019-12-07 19:01:21,037 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:01:21,037 INFO L276 IsEmpty]: Start isEmpty. Operand 372573 states and 1538118 transitions. [2019-12-07 19:01:21,065 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 19:01:21,065 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:01:21,065 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:01:21,065 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:01:21,066 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:01:21,066 INFO L82 PathProgramCache]: Analyzing trace with hash -1595183089, now seen corresponding path program 1 times [2019-12-07 19:01:21,066 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:01:21,066 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1722362032] [2019-12-07 19:01:21,066 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:01:21,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:01:21,104 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:01:21,105 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1722362032] [2019-12-07 19:01:21,105 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:01:21,105 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 19:01:21,105 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [173398204] [2019-12-07 19:01:21,105 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:01:21,105 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:01:21,106 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:01:21,106 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:01:21,106 INFO L87 Difference]: Start difference. First operand 372573 states and 1538118 transitions. Second operand 3 states. [2019-12-07 19:01:23,333 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:01:23,333 INFO L93 Difference]: Finished difference Result 372215 states and 1536731 transitions. [2019-12-07 19:01:23,334 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:01:23,334 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 19 [2019-12-07 19:01:23,334 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:01:24,330 INFO L225 Difference]: With dead ends: 372215 [2019-12-07 19:01:24,331 INFO L226 Difference]: Without dead ends: 372215 [2019-12-07 19:01:24,331 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:01:35,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 372215 states. [2019-12-07 19:01:40,387 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 372215 to 369047. [2019-12-07 19:01:40,387 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 369047 states. [2019-12-07 19:01:41,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 369047 states to 369047 states and 1524635 transitions. [2019-12-07 19:01:41,869 INFO L78 Accepts]: Start accepts. Automaton has 369047 states and 1524635 transitions. Word has length 19 [2019-12-07 19:01:41,869 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:01:41,869 INFO L462 AbstractCegarLoop]: Abstraction has 369047 states and 1524635 transitions. [2019-12-07 19:01:41,869 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:01:41,869 INFO L276 IsEmpty]: Start isEmpty. Operand 369047 states and 1524635 transitions. [2019-12-07 19:01:41,896 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 19:01:41,896 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:01:41,896 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:01:41,896 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:01:41,897 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:01:41,897 INFO L82 PathProgramCache]: Analyzing trace with hash 700766782, now seen corresponding path program 1 times [2019-12-07 19:01:41,897 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:01:41,897 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [112083689] [2019-12-07 19:01:41,897 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:01:41,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:01:41,928 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:01:41,928 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [112083689] [2019-12-07 19:01:41,929 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:01:41,929 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:01:41,929 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [906778014] [2019-12-07 19:01:41,929 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:01:41,929 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:01:41,929 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:01:41,929 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:01:41,929 INFO L87 Difference]: Start difference. First operand 369047 states and 1524635 transitions. Second operand 3 states. [2019-12-07 19:01:43,926 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:01:43,926 INFO L93 Difference]: Finished difference Result 346890 states and 1416741 transitions. [2019-12-07 19:01:43,927 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:01:43,927 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 19 [2019-12-07 19:01:43,927 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:01:44,813 INFO L225 Difference]: With dead ends: 346890 [2019-12-07 19:01:44,813 INFO L226 Difference]: Without dead ends: 346890 [2019-12-07 19:01:44,814 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:01:51,378 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 346890 states. [2019-12-07 19:01:55,807 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 346890 to 342976. [2019-12-07 19:01:55,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 342976 states. [2019-12-07 19:02:02,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 342976 states to 342976 states and 1402379 transitions. [2019-12-07 19:02:02,662 INFO L78 Accepts]: Start accepts. Automaton has 342976 states and 1402379 transitions. Word has length 19 [2019-12-07 19:02:02,662 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:02:02,663 INFO L462 AbstractCegarLoop]: Abstraction has 342976 states and 1402379 transitions. [2019-12-07 19:02:02,663 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:02:02,663 INFO L276 IsEmpty]: Start isEmpty. Operand 342976 states and 1402379 transitions. [2019-12-07 19:02:02,686 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 19:02:02,686 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:02:02,686 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:02:02,686 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:02:02,686 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:02:02,686 INFO L82 PathProgramCache]: Analyzing trace with hash -116744345, now seen corresponding path program 1 times [2019-12-07 19:02:02,686 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:02:02,687 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1209939534] [2019-12-07 19:02:02,687 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:02:02,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:02:02,729 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:02:02,729 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1209939534] [2019-12-07 19:02:02,729 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:02:02,729 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 19:02:02,729 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1481410880] [2019-12-07 19:02:02,729 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 19:02:02,729 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:02:02,730 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 19:02:02,730 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:02:02,730 INFO L87 Difference]: Start difference. First operand 342976 states and 1402379 transitions. Second operand 5 states. [2019-12-07 19:02:05,489 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:02:05,489 INFO L93 Difference]: Finished difference Result 486564 states and 1950082 transitions. [2019-12-07 19:02:05,490 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 19:02:05,490 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 19:02:05,490 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:02:06,744 INFO L225 Difference]: With dead ends: 486564 [2019-12-07 19:02:06,744 INFO L226 Difference]: Without dead ends: 486382 [2019-12-07 19:02:06,744 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 19:02:14,662 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 486382 states. [2019-12-07 19:02:20,454 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 486382 to 366451. [2019-12-07 19:02:20,454 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 366451 states. [2019-12-07 19:02:22,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 366451 states to 366451 states and 1493995 transitions. [2019-12-07 19:02:22,072 INFO L78 Accepts]: Start accepts. Automaton has 366451 states and 1493995 transitions. Word has length 19 [2019-12-07 19:02:22,072 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:02:22,072 INFO L462 AbstractCegarLoop]: Abstraction has 366451 states and 1493995 transitions. [2019-12-07 19:02:22,072 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 19:02:22,072 INFO L276 IsEmpty]: Start isEmpty. Operand 366451 states and 1493995 transitions. [2019-12-07 19:02:22,095 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 19:02:22,095 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:02:22,095 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:02:22,095 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:02:22,095 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:02:22,095 INFO L82 PathProgramCache]: Analyzing trace with hash 1088543872, now seen corresponding path program 1 times [2019-12-07 19:02:22,095 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:02:22,095 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [981959322] [2019-12-07 19:02:22,096 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:02:22,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:02:22,134 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:02:22,135 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [981959322] [2019-12-07 19:02:22,135 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:02:22,135 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:02:22,135 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [715476240] [2019-12-07 19:02:22,135 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 19:02:22,135 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:02:22,135 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 19:02:22,136 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 19:02:22,136 INFO L87 Difference]: Start difference. First operand 366451 states and 1493995 transitions. Second operand 4 states. [2019-12-07 19:02:23,763 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:02:23,763 INFO L93 Difference]: Finished difference Result 383518 states and 1549336 transitions. [2019-12-07 19:02:23,764 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 19:02:23,764 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 19 [2019-12-07 19:02:23,764 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:02:25,487 INFO L225 Difference]: With dead ends: 383518 [2019-12-07 19:02:25,487 INFO L226 Difference]: Without dead ends: 383518 [2019-12-07 19:02:25,487 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 19:02:35,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 383518 states. [2019-12-07 19:02:41,097 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 383518 to 366071. [2019-12-07 19:02:41,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 366071 states. [2019-12-07 19:02:42,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 366071 states to 366071 states and 1492583 transitions. [2019-12-07 19:02:42,641 INFO L78 Accepts]: Start accepts. Automaton has 366071 states and 1492583 transitions. Word has length 19 [2019-12-07 19:02:42,641 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:02:42,642 INFO L462 AbstractCegarLoop]: Abstraction has 366071 states and 1492583 transitions. [2019-12-07 19:02:42,642 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 19:02:42,642 INFO L276 IsEmpty]: Start isEmpty. Operand 366071 states and 1492583 transitions. [2019-12-07 19:02:42,666 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2019-12-07 19:02:42,666 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:02:42,667 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:02:42,667 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:02:42,667 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:02:42,667 INFO L82 PathProgramCache]: Analyzing trace with hash -2047376576, now seen corresponding path program 1 times [2019-12-07 19:02:42,667 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:02:42,667 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1152962271] [2019-12-07 19:02:42,667 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:02:42,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:02:42,694 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:02:42,695 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1152962271] [2019-12-07 19:02:42,695 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:02:42,695 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:02:42,695 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [215044309] [2019-12-07 19:02:42,695 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:02:42,695 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:02:42,696 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:02:42,696 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:02:42,696 INFO L87 Difference]: Start difference. First operand 366071 states and 1492583 transitions. Second operand 3 states. [2019-12-07 19:02:42,929 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:02:42,929 INFO L93 Difference]: Finished difference Result 73045 states and 234851 transitions. [2019-12-07 19:02:42,930 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:02:42,930 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 20 [2019-12-07 19:02:42,930 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:02:43,041 INFO L225 Difference]: With dead ends: 73045 [2019-12-07 19:02:43,041 INFO L226 Difference]: Without dead ends: 73045 [2019-12-07 19:02:43,041 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:02:43,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73045 states. [2019-12-07 19:02:43,969 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73045 to 73045. [2019-12-07 19:02:43,969 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73045 states. [2019-12-07 19:02:44,108 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73045 states to 73045 states and 234851 transitions. [2019-12-07 19:02:44,108 INFO L78 Accepts]: Start accepts. Automaton has 73045 states and 234851 transitions. Word has length 20 [2019-12-07 19:02:44,108 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:02:44,108 INFO L462 AbstractCegarLoop]: Abstraction has 73045 states and 234851 transitions. [2019-12-07 19:02:44,108 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:02:44,108 INFO L276 IsEmpty]: Start isEmpty. Operand 73045 states and 234851 transitions. [2019-12-07 19:02:44,115 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2019-12-07 19:02:44,115 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:02:44,115 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:02:44,115 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:02:44,116 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:02:44,116 INFO L82 PathProgramCache]: Analyzing trace with hash -655013944, now seen corresponding path program 1 times [2019-12-07 19:02:44,116 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:02:44,116 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2007808263] [2019-12-07 19:02:44,116 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:02:44,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:02:44,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:02:44,150 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2007808263] [2019-12-07 19:02:44,151 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:02:44,151 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 19:02:44,151 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [839586246] [2019-12-07 19:02:44,151 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 19:02:44,151 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:02:44,151 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 19:02:44,151 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:02:44,151 INFO L87 Difference]: Start difference. First operand 73045 states and 234851 transitions. Second operand 5 states. [2019-12-07 19:02:45,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:02:45,083 INFO L93 Difference]: Finished difference Result 95045 states and 298925 transitions. [2019-12-07 19:02:45,083 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 19:02:45,083 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 22 [2019-12-07 19:02:45,083 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:02:45,214 INFO L225 Difference]: With dead ends: 95045 [2019-12-07 19:02:45,214 INFO L226 Difference]: Without dead ends: 95031 [2019-12-07 19:02:45,214 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 19:02:45,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95031 states. [2019-12-07 19:02:46,397 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95031 to 77503. [2019-12-07 19:02:46,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77503 states. [2019-12-07 19:02:46,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77503 states to 77503 states and 248087 transitions. [2019-12-07 19:02:46,545 INFO L78 Accepts]: Start accepts. Automaton has 77503 states and 248087 transitions. Word has length 22 [2019-12-07 19:02:46,545 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:02:46,545 INFO L462 AbstractCegarLoop]: Abstraction has 77503 states and 248087 transitions. [2019-12-07 19:02:46,546 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 19:02:46,546 INFO L276 IsEmpty]: Start isEmpty. Operand 77503 states and 248087 transitions. [2019-12-07 19:02:46,552 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2019-12-07 19:02:46,553 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:02:46,553 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:02:46,553 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:02:46,553 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:02:46,553 INFO L82 PathProgramCache]: Analyzing trace with hash -2032339914, now seen corresponding path program 1 times [2019-12-07 19:02:46,553 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:02:46,553 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [31749165] [2019-12-07 19:02:46,553 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:02:46,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:02:46,580 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:02:46,581 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [31749165] [2019-12-07 19:02:46,581 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:02:46,581 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 19:02:46,581 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [864641223] [2019-12-07 19:02:46,581 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 19:02:46,582 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:02:46,582 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 19:02:46,582 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:02:46,582 INFO L87 Difference]: Start difference. First operand 77503 states and 248087 transitions. Second operand 5 states. [2019-12-07 19:02:47,335 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:02:47,336 INFO L93 Difference]: Finished difference Result 98221 states and 310051 transitions. [2019-12-07 19:02:47,336 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 19:02:47,336 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 22 [2019-12-07 19:02:47,336 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:02:47,470 INFO L225 Difference]: With dead ends: 98221 [2019-12-07 19:02:47,470 INFO L226 Difference]: Without dead ends: 98207 [2019-12-07 19:02:47,471 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 19:02:47,770 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98207 states. [2019-12-07 19:02:48,623 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98207 to 76018. [2019-12-07 19:02:48,623 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 76018 states. [2019-12-07 19:02:48,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76018 states to 76018 states and 243643 transitions. [2019-12-07 19:02:48,769 INFO L78 Accepts]: Start accepts. Automaton has 76018 states and 243643 transitions. Word has length 22 [2019-12-07 19:02:48,769 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:02:48,769 INFO L462 AbstractCegarLoop]: Abstraction has 76018 states and 243643 transitions. [2019-12-07 19:02:48,769 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 19:02:48,769 INFO L276 IsEmpty]: Start isEmpty. Operand 76018 states and 243643 transitions. [2019-12-07 19:02:48,785 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2019-12-07 19:02:48,785 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:02:48,785 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:02:48,786 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:02:48,786 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:02:48,786 INFO L82 PathProgramCache]: Analyzing trace with hash -1083173402, now seen corresponding path program 1 times [2019-12-07 19:02:48,786 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:02:48,786 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1175489606] [2019-12-07 19:02:48,786 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:02:48,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:02:48,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:02:48,815 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1175489606] [2019-12-07 19:02:48,815 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:02:48,815 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 19:02:48,815 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [771774511] [2019-12-07 19:02:48,815 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 19:02:48,815 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:02:48,816 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 19:02:48,816 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:02:48,816 INFO L87 Difference]: Start difference. First operand 76018 states and 243643 transitions. Second operand 5 states. [2019-12-07 19:02:49,256 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:02:49,256 INFO L93 Difference]: Finished difference Result 92182 states and 291859 transitions. [2019-12-07 19:02:49,256 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 19:02:49,256 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 26 [2019-12-07 19:02:49,256 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:02:49,392 INFO L225 Difference]: With dead ends: 92182 [2019-12-07 19:02:49,392 INFO L226 Difference]: Without dead ends: 92134 [2019-12-07 19:02:49,393 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 19:02:49,798 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92134 states. [2019-12-07 19:02:50,607 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92134 to 79055. [2019-12-07 19:02:50,607 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 79055 states. [2019-12-07 19:02:50,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79055 states to 79055 states and 252753 transitions. [2019-12-07 19:02:50,758 INFO L78 Accepts]: Start accepts. Automaton has 79055 states and 252753 transitions. Word has length 26 [2019-12-07 19:02:50,758 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:02:50,758 INFO L462 AbstractCegarLoop]: Abstraction has 79055 states and 252753 transitions. [2019-12-07 19:02:50,758 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 19:02:50,758 INFO L276 IsEmpty]: Start isEmpty. Operand 79055 states and 252753 transitions. [2019-12-07 19:02:50,780 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-12-07 19:02:50,780 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:02:50,780 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:02:50,780 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:02:50,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:02:50,780 INFO L82 PathProgramCache]: Analyzing trace with hash -799804073, now seen corresponding path program 1 times [2019-12-07 19:02:50,781 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:02:50,781 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1767923835] [2019-12-07 19:02:50,781 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:02:50,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:02:50,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:02:50,815 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1767923835] [2019-12-07 19:02:50,815 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:02:50,815 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 19:02:50,815 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1201898596] [2019-12-07 19:02:50,816 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 19:02:50,816 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:02:50,816 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 19:02:50,816 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:02:50,816 INFO L87 Difference]: Start difference. First operand 79055 states and 252753 transitions. Second operand 5 states. [2019-12-07 19:02:51,235 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:02:51,235 INFO L93 Difference]: Finished difference Result 92878 states and 292736 transitions. [2019-12-07 19:02:51,236 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 19:02:51,236 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 28 [2019-12-07 19:02:51,236 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:02:51,370 INFO L225 Difference]: With dead ends: 92878 [2019-12-07 19:02:51,370 INFO L226 Difference]: Without dead ends: 92834 [2019-12-07 19:02:51,370 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 19:02:51,663 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92834 states. [2019-12-07 19:02:52,599 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92834 to 78251. [2019-12-07 19:02:52,599 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78251 states. [2019-12-07 19:02:52,747 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78251 states to 78251 states and 250288 transitions. [2019-12-07 19:02:52,748 INFO L78 Accepts]: Start accepts. Automaton has 78251 states and 250288 transitions. Word has length 28 [2019-12-07 19:02:52,748 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:02:52,748 INFO L462 AbstractCegarLoop]: Abstraction has 78251 states and 250288 transitions. [2019-12-07 19:02:52,748 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 19:02:52,748 INFO L276 IsEmpty]: Start isEmpty. Operand 78251 states and 250288 transitions. [2019-12-07 19:02:52,774 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2019-12-07 19:02:52,774 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:02:52,774 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:02:52,775 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:02:52,775 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:02:52,775 INFO L82 PathProgramCache]: Analyzing trace with hash -1469523336, now seen corresponding path program 1 times [2019-12-07 19:02:52,775 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:02:52,775 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1589690985] [2019-12-07 19:02:52,775 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:02:52,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:02:52,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:02:52,822 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1589690985] [2019-12-07 19:02:52,822 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:02:52,822 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 19:02:52,822 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2000959341] [2019-12-07 19:02:52,823 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 19:02:52,823 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:02:52,823 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 19:02:52,823 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 19:02:52,823 INFO L87 Difference]: Start difference. First operand 78251 states and 250288 transitions. Second operand 4 states. [2019-12-07 19:02:53,127 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:02:53,127 INFO L93 Difference]: Finished difference Result 104200 states and 333998 transitions. [2019-12-07 19:02:53,128 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 19:02:53,128 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 30 [2019-12-07 19:02:53,128 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:02:53,186 INFO L225 Difference]: With dead ends: 104200 [2019-12-07 19:02:53,186 INFO L226 Difference]: Without dead ends: 39781 [2019-12-07 19:02:53,186 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 19:02:53,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39781 states. [2019-12-07 19:02:53,713 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39781 to 37292. [2019-12-07 19:02:53,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37292 states. [2019-12-07 19:02:53,775 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37292 states to 37292 states and 117321 transitions. [2019-12-07 19:02:53,775 INFO L78 Accepts]: Start accepts. Automaton has 37292 states and 117321 transitions. Word has length 30 [2019-12-07 19:02:53,775 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:02:53,775 INFO L462 AbstractCegarLoop]: Abstraction has 37292 states and 117321 transitions. [2019-12-07 19:02:53,775 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 19:02:53,775 INFO L276 IsEmpty]: Start isEmpty. Operand 37292 states and 117321 transitions. [2019-12-07 19:02:53,787 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2019-12-07 19:02:53,787 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:02:53,787 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:02:53,787 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:02:53,787 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:02:53,787 INFO L82 PathProgramCache]: Analyzing trace with hash 256918600, now seen corresponding path program 1 times [2019-12-07 19:02:53,787 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:02:53,787 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1056351379] [2019-12-07 19:02:53,787 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:02:53,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:02:53,827 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:02:53,827 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1056351379] [2019-12-07 19:02:53,828 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:02:53,828 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 19:02:53,828 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1340674856] [2019-12-07 19:02:53,828 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 19:02:53,828 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:02:53,828 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 19:02:53,829 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 19:02:53,829 INFO L87 Difference]: Start difference. First operand 37292 states and 117321 transitions. Second operand 4 states. [2019-12-07 19:02:53,928 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:02:53,929 INFO L93 Difference]: Finished difference Result 14286 states and 43011 transitions. [2019-12-07 19:02:53,929 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 19:02:53,929 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 31 [2019-12-07 19:02:53,929 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:02:53,944 INFO L225 Difference]: With dead ends: 14286 [2019-12-07 19:02:53,944 INFO L226 Difference]: Without dead ends: 14286 [2019-12-07 19:02:53,945 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 19:02:53,996 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14286 states. [2019-12-07 19:02:54,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14286 to 13807. [2019-12-07 19:02:54,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13807 states. [2019-12-07 19:02:54,131 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13807 states to 13807 states and 41928 transitions. [2019-12-07 19:02:54,131 INFO L78 Accepts]: Start accepts. Automaton has 13807 states and 41928 transitions. Word has length 31 [2019-12-07 19:02:54,131 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:02:54,131 INFO L462 AbstractCegarLoop]: Abstraction has 13807 states and 41928 transitions. [2019-12-07 19:02:54,131 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 19:02:54,132 INFO L276 IsEmpty]: Start isEmpty. Operand 13807 states and 41928 transitions. [2019-12-07 19:02:54,140 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-12-07 19:02:54,140 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:02:54,140 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:02:54,140 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:02:54,140 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:02:54,140 INFO L82 PathProgramCache]: Analyzing trace with hash -145847770, now seen corresponding path program 1 times [2019-12-07 19:02:54,140 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:02:54,140 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1766712122] [2019-12-07 19:02:54,140 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:02:54,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:02:54,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:02:54,186 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1766712122] [2019-12-07 19:02:54,186 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:02:54,186 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 19:02:54,186 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [45098541] [2019-12-07 19:02:54,186 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 19:02:54,186 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:02:54,187 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 19:02:54,187 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 19:02:54,187 INFO L87 Difference]: Start difference. First operand 13807 states and 41928 transitions. Second operand 6 states. [2019-12-07 19:02:54,544 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:02:54,544 INFO L93 Difference]: Finished difference Result 18584 states and 54898 transitions. [2019-12-07 19:02:54,544 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 19:02:54,545 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 32 [2019-12-07 19:02:54,545 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:02:54,564 INFO L225 Difference]: With dead ends: 18584 [2019-12-07 19:02:54,564 INFO L226 Difference]: Without dead ends: 18584 [2019-12-07 19:02:54,564 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=111, Unknown=0, NotChecked=0, Total=156 [2019-12-07 19:02:54,623 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18584 states. [2019-12-07 19:02:54,758 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18584 to 13968. [2019-12-07 19:02:54,758 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13968 states. [2019-12-07 19:02:54,779 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13968 states to 13968 states and 42400 transitions. [2019-12-07 19:02:54,780 INFO L78 Accepts]: Start accepts. Automaton has 13968 states and 42400 transitions. Word has length 32 [2019-12-07 19:02:54,780 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:02:54,780 INFO L462 AbstractCegarLoop]: Abstraction has 13968 states and 42400 transitions. [2019-12-07 19:02:54,780 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 19:02:54,780 INFO L276 IsEmpty]: Start isEmpty. Operand 13968 states and 42400 transitions. [2019-12-07 19:02:54,789 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 19:02:54,789 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:02:54,789 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:02:54,789 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:02:54,789 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:02:54,789 INFO L82 PathProgramCache]: Analyzing trace with hash -1380765993, now seen corresponding path program 1 times [2019-12-07 19:02:54,790 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:02:54,790 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [91090189] [2019-12-07 19:02:54,790 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:02:54,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:02:54,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:02:54,836 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [91090189] [2019-12-07 19:02:54,836 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:02:54,836 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 19:02:54,836 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [834160062] [2019-12-07 19:02:54,837 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 19:02:54,837 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:02:54,837 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 19:02:54,837 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 19:02:54,837 INFO L87 Difference]: Start difference. First operand 13968 states and 42400 transitions. Second operand 6 states. [2019-12-07 19:02:55,217 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:02:55,217 INFO L93 Difference]: Finished difference Result 18280 states and 54022 transitions. [2019-12-07 19:02:55,217 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 19:02:55,217 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 34 [2019-12-07 19:02:55,217 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:02:55,236 INFO L225 Difference]: With dead ends: 18280 [2019-12-07 19:02:55,237 INFO L226 Difference]: Without dead ends: 18280 [2019-12-07 19:02:55,237 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=111, Unknown=0, NotChecked=0, Total=156 [2019-12-07 19:02:55,296 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18280 states. [2019-12-07 19:02:55,429 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18280 to 13440. [2019-12-07 19:02:55,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13440 states. [2019-12-07 19:02:55,451 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13440 states to 13440 states and 40858 transitions. [2019-12-07 19:02:55,451 INFO L78 Accepts]: Start accepts. Automaton has 13440 states and 40858 transitions. Word has length 34 [2019-12-07 19:02:55,451 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:02:55,451 INFO L462 AbstractCegarLoop]: Abstraction has 13440 states and 40858 transitions. [2019-12-07 19:02:55,451 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 19:02:55,451 INFO L276 IsEmpty]: Start isEmpty. Operand 13440 states and 40858 transitions. [2019-12-07 19:02:55,461 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2019-12-07 19:02:55,461 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:02:55,461 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:02:55,461 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:02:55,462 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:02:55,462 INFO L82 PathProgramCache]: Analyzing trace with hash 1174419869, now seen corresponding path program 1 times [2019-12-07 19:02:55,462 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:02:55,462 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [793170501] [2019-12-07 19:02:55,462 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:02:55,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:02:55,513 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:02:55,513 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [793170501] [2019-12-07 19:02:55,513 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:02:55,513 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 19:02:55,513 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1579034081] [2019-12-07 19:02:55,513 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 19:02:55,513 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:02:55,514 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 19:02:55,514 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:02:55,514 INFO L87 Difference]: Start difference. First operand 13440 states and 40858 transitions. Second operand 5 states. [2019-12-07 19:02:55,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:02:55,992 INFO L93 Difference]: Finished difference Result 20381 states and 61298 transitions. [2019-12-07 19:02:55,992 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 19:02:55,992 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 41 [2019-12-07 19:02:55,992 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:02:56,023 INFO L225 Difference]: With dead ends: 20381 [2019-12-07 19:02:56,023 INFO L226 Difference]: Without dead ends: 20381 [2019-12-07 19:02:56,024 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 19:02:56,086 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20381 states. [2019-12-07 19:02:56,251 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20381 to 17244. [2019-12-07 19:02:56,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17244 states. [2019-12-07 19:02:56,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17244 states to 17244 states and 52553 transitions. [2019-12-07 19:02:56,278 INFO L78 Accepts]: Start accepts. Automaton has 17244 states and 52553 transitions. Word has length 41 [2019-12-07 19:02:56,278 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:02:56,278 INFO L462 AbstractCegarLoop]: Abstraction has 17244 states and 52553 transitions. [2019-12-07 19:02:56,278 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 19:02:56,278 INFO L276 IsEmpty]: Start isEmpty. Operand 17244 states and 52553 transitions. [2019-12-07 19:02:56,292 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2019-12-07 19:02:56,292 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:02:56,293 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:02:56,293 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:02:56,293 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:02:56,293 INFO L82 PathProgramCache]: Analyzing trace with hash 1274395705, now seen corresponding path program 2 times [2019-12-07 19:02:56,293 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:02:56,293 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1961241606] [2019-12-07 19:02:56,293 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:02:56,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:02:56,325 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:02:56,325 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1961241606] [2019-12-07 19:02:56,325 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:02:56,325 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:02:56,326 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [525832499] [2019-12-07 19:02:56,326 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:02:56,326 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:02:56,326 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:02:56,326 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:02:56,326 INFO L87 Difference]: Start difference. First operand 17244 states and 52553 transitions. Second operand 3 states. [2019-12-07 19:02:56,385 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:02:56,385 INFO L93 Difference]: Finished difference Result 17244 states and 51750 transitions. [2019-12-07 19:02:56,385 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:02:56,385 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 41 [2019-12-07 19:02:56,385 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:02:56,412 INFO L225 Difference]: With dead ends: 17244 [2019-12-07 19:02:56,412 INFO L226 Difference]: Without dead ends: 17244 [2019-12-07 19:02:56,412 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:02:56,470 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17244 states. [2019-12-07 19:02:56,607 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17244 to 16758. [2019-12-07 19:02:56,607 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16758 states. [2019-12-07 19:02:56,631 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16758 states to 16758 states and 50385 transitions. [2019-12-07 19:02:56,631 INFO L78 Accepts]: Start accepts. Automaton has 16758 states and 50385 transitions. Word has length 41 [2019-12-07 19:02:56,631 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:02:56,632 INFO L462 AbstractCegarLoop]: Abstraction has 16758 states and 50385 transitions. [2019-12-07 19:02:56,632 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:02:56,632 INFO L276 IsEmpty]: Start isEmpty. Operand 16758 states and 50385 transitions. [2019-12-07 19:02:56,645 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-12-07 19:02:56,645 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:02:56,645 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:02:56,645 INFO L410 AbstractCegarLoop]: === Iteration 23 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:02:56,645 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:02:56,645 INFO L82 PathProgramCache]: Analyzing trace with hash 1961497157, now seen corresponding path program 1 times [2019-12-07 19:02:56,645 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:02:56,645 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [351967253] [2019-12-07 19:02:56,646 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:02:56,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:02:56,679 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:02:56,680 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [351967253] [2019-12-07 19:02:56,680 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:02:56,680 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 19:02:56,680 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [38252262] [2019-12-07 19:02:56,680 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 19:02:56,680 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:02:56,680 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 19:02:56,680 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:02:56,681 INFO L87 Difference]: Start difference. First operand 16758 states and 50385 transitions. Second operand 5 states. [2019-12-07 19:02:56,764 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:02:56,764 INFO L93 Difference]: Finished difference Result 15604 states and 47845 transitions. [2019-12-07 19:02:56,764 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 19:02:56,764 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 42 [2019-12-07 19:02:56,764 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:02:56,780 INFO L225 Difference]: With dead ends: 15604 [2019-12-07 19:02:56,780 INFO L226 Difference]: Without dead ends: 14001 [2019-12-07 19:02:56,781 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 19:02:56,832 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14001 states. [2019-12-07 19:02:56,952 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14001 to 14001. [2019-12-07 19:02:56,952 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14001 states. [2019-12-07 19:02:56,974 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14001 states to 14001 states and 43829 transitions. [2019-12-07 19:02:56,974 INFO L78 Accepts]: Start accepts. Automaton has 14001 states and 43829 transitions. Word has length 42 [2019-12-07 19:02:56,974 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:02:56,974 INFO L462 AbstractCegarLoop]: Abstraction has 14001 states and 43829 transitions. [2019-12-07 19:02:56,974 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 19:02:56,974 INFO L276 IsEmpty]: Start isEmpty. Operand 14001 states and 43829 transitions. [2019-12-07 19:02:56,986 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 19:02:56,986 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:02:56,986 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:02:56,986 INFO L410 AbstractCegarLoop]: === Iteration 24 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:02:56,986 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:02:56,987 INFO L82 PathProgramCache]: Analyzing trace with hash -668679299, now seen corresponding path program 1 times [2019-12-07 19:02:56,987 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:02:56,987 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1054123368] [2019-12-07 19:02:56,987 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:02:56,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:02:57,042 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:02:57,042 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1054123368] [2019-12-07 19:02:57,043 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:02:57,043 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 19:02:57,043 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [963689995] [2019-12-07 19:02:57,043 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 19:02:57,043 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:02:57,043 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 19:02:57,044 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 19:02:57,044 INFO L87 Difference]: Start difference. First operand 14001 states and 43829 transitions. Second operand 6 states. [2019-12-07 19:02:57,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:02:57,502 INFO L93 Difference]: Finished difference Result 19859 states and 61066 transitions. [2019-12-07 19:02:57,502 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 19:02:57,502 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 65 [2019-12-07 19:02:57,502 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:02:57,524 INFO L225 Difference]: With dead ends: 19859 [2019-12-07 19:02:57,524 INFO L226 Difference]: Without dead ends: 19859 [2019-12-07 19:02:57,525 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2019-12-07 19:02:57,585 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19859 states. [2019-12-07 19:02:57,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19859 to 14668. [2019-12-07 19:02:57,739 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14668 states. [2019-12-07 19:02:57,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14668 states to 14668 states and 45904 transitions. [2019-12-07 19:02:57,762 INFO L78 Accepts]: Start accepts. Automaton has 14668 states and 45904 transitions. Word has length 65 [2019-12-07 19:02:57,763 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:02:57,763 INFO L462 AbstractCegarLoop]: Abstraction has 14668 states and 45904 transitions. [2019-12-07 19:02:57,763 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 19:02:57,763 INFO L276 IsEmpty]: Start isEmpty. Operand 14668 states and 45904 transitions. [2019-12-07 19:02:57,775 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 19:02:57,775 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:02:57,776 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:02:57,776 INFO L410 AbstractCegarLoop]: === Iteration 25 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:02:57,776 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:02:57,776 INFO L82 PathProgramCache]: Analyzing trace with hash 339295601, now seen corresponding path program 2 times [2019-12-07 19:02:57,776 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:02:57,776 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1801352866] [2019-12-07 19:02:57,776 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:02:57,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:02:57,806 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:02:57,806 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1801352866] [2019-12-07 19:02:57,806 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:02:57,806 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 19:02:57,806 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1138067987] [2019-12-07 19:02:57,807 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 19:02:57,807 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:02:57,807 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 19:02:57,807 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:02:57,807 INFO L87 Difference]: Start difference. First operand 14668 states and 45904 transitions. Second operand 3 states. [2019-12-07 19:02:57,877 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:02:57,877 INFO L93 Difference]: Finished difference Result 18150 states and 56424 transitions. [2019-12-07 19:02:57,878 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 19:02:57,878 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 65 [2019-12-07 19:02:57,878 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:02:57,897 INFO L225 Difference]: With dead ends: 18150 [2019-12-07 19:02:57,897 INFO L226 Difference]: Without dead ends: 18150 [2019-12-07 19:02:57,897 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 19:02:57,955 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18150 states. [2019-12-07 19:02:58,101 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18150 to 14713. [2019-12-07 19:02:58,102 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14713 states. [2019-12-07 19:02:58,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14713 states to 14713 states and 46167 transitions. [2019-12-07 19:02:58,125 INFO L78 Accepts]: Start accepts. Automaton has 14713 states and 46167 transitions. Word has length 65 [2019-12-07 19:02:58,126 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:02:58,126 INFO L462 AbstractCegarLoop]: Abstraction has 14713 states and 46167 transitions. [2019-12-07 19:02:58,126 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 19:02:58,126 INFO L276 IsEmpty]: Start isEmpty. Operand 14713 states and 46167 transitions. [2019-12-07 19:02:58,139 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 19:02:58,139 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:02:58,139 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:02:58,139 INFO L410 AbstractCegarLoop]: === Iteration 26 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:02:58,140 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:02:58,140 INFO L82 PathProgramCache]: Analyzing trace with hash -1524862519, now seen corresponding path program 1 times [2019-12-07 19:02:58,140 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:02:58,140 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1195157974] [2019-12-07 19:02:58,140 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:02:58,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:02:58,433 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:02:58,433 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1195157974] [2019-12-07 19:02:58,434 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:02:58,434 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 19:02:58,434 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [14302523] [2019-12-07 19:02:58,434 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 19:02:58,434 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:02:58,434 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 19:02:58,434 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=176, Unknown=0, NotChecked=0, Total=210 [2019-12-07 19:02:58,434 INFO L87 Difference]: Start difference. First operand 14713 states and 46167 transitions. Second operand 15 states. [2019-12-07 19:03:05,010 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:03:05,010 INFO L93 Difference]: Finished difference Result 50512 states and 156804 transitions. [2019-12-07 19:03:05,011 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 77 states. [2019-12-07 19:03:05,011 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 66 [2019-12-07 19:03:05,011 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:03:05,061 INFO L225 Difference]: With dead ends: 50512 [2019-12-07 19:03:05,061 INFO L226 Difference]: Without dead ends: 43050 [2019-12-07 19:03:05,063 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 82 GetRequests, 0 SyntacticMatches, 5 SemanticMatches, 77 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2031 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=887, Invalid=5275, Unknown=0, NotChecked=0, Total=6162 [2019-12-07 19:03:05,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43050 states. [2019-12-07 19:03:05,465 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43050 to 21415. [2019-12-07 19:03:05,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21415 states. [2019-12-07 19:03:05,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21415 states to 21415 states and 66949 transitions. [2019-12-07 19:03:05,502 INFO L78 Accepts]: Start accepts. Automaton has 21415 states and 66949 transitions. Word has length 66 [2019-12-07 19:03:05,503 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:03:05,503 INFO L462 AbstractCegarLoop]: Abstraction has 21415 states and 66949 transitions. [2019-12-07 19:03:05,503 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 19:03:05,503 INFO L276 IsEmpty]: Start isEmpty. Operand 21415 states and 66949 transitions. [2019-12-07 19:03:05,522 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 19:03:05,522 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:03:05,522 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:03:05,522 INFO L410 AbstractCegarLoop]: === Iteration 27 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:03:05,522 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:03:05,523 INFO L82 PathProgramCache]: Analyzing trace with hash -1239159877, now seen corresponding path program 2 times [2019-12-07 19:03:05,523 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:03:05,523 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [437189627] [2019-12-07 19:03:05,523 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:03:05,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:03:05,891 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:03:05,891 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [437189627] [2019-12-07 19:03:05,891 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:03:05,891 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [16] imperfect sequences [] total 16 [2019-12-07 19:03:05,891 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1502490215] [2019-12-07 19:03:05,891 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-12-07 19:03:05,891 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:03:05,892 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-12-07 19:03:05,892 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=264, Unknown=0, NotChecked=0, Total=306 [2019-12-07 19:03:05,892 INFO L87 Difference]: Start difference. First operand 21415 states and 66949 transitions. Second operand 18 states. [2019-12-07 19:03:11,781 WARN L192 SmtUtils]: Spent 100.00 ms on a formula simplification. DAG size of input: 24 DAG size of output: 21 [2019-12-07 19:03:13,834 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:03:13,834 INFO L93 Difference]: Finished difference Result 37185 states and 113569 transitions. [2019-12-07 19:03:13,834 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2019-12-07 19:03:13,834 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 66 [2019-12-07 19:03:13,834 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:03:13,869 INFO L225 Difference]: With dead ends: 37185 [2019-12-07 19:03:13,869 INFO L226 Difference]: Without dead ends: 31279 [2019-12-07 19:03:13,870 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 445 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=314, Invalid=1942, Unknown=0, NotChecked=0, Total=2256 [2019-12-07 19:03:13,993 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31279 states. [2019-12-07 19:03:14,213 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31279 to 23929. [2019-12-07 19:03:14,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23929 states. [2019-12-07 19:03:14,252 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23929 states to 23929 states and 73946 transitions. [2019-12-07 19:03:14,253 INFO L78 Accepts]: Start accepts. Automaton has 23929 states and 73946 transitions. Word has length 66 [2019-12-07 19:03:14,253 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:03:14,253 INFO L462 AbstractCegarLoop]: Abstraction has 23929 states and 73946 transitions. [2019-12-07 19:03:14,253 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-12-07 19:03:14,253 INFO L276 IsEmpty]: Start isEmpty. Operand 23929 states and 73946 transitions. [2019-12-07 19:03:14,275 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 19:03:14,275 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:03:14,275 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:03:14,275 INFO L410 AbstractCegarLoop]: === Iteration 28 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:03:14,275 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:03:14,276 INFO L82 PathProgramCache]: Analyzing trace with hash 1626008201, now seen corresponding path program 3 times [2019-12-07 19:03:14,276 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:03:14,276 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1008913213] [2019-12-07 19:03:14,276 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:03:14,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:03:14,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:03:14,400 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1008913213] [2019-12-07 19:03:14,400 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:03:14,400 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 19:03:14,400 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [760841972] [2019-12-07 19:03:14,400 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 19:03:14,400 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:03:14,401 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 19:03:14,401 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2019-12-07 19:03:14,401 INFO L87 Difference]: Start difference. First operand 23929 states and 73946 transitions. Second operand 11 states. [2019-12-07 19:03:15,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:03:15,324 INFO L93 Difference]: Finished difference Result 57778 states and 177837 transitions. [2019-12-07 19:03:15,324 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2019-12-07 19:03:15,324 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 66 [2019-12-07 19:03:15,324 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:03:15,361 INFO L225 Difference]: With dead ends: 57778 [2019-12-07 19:03:15,361 INFO L226 Difference]: Without dead ends: 30920 [2019-12-07 19:03:15,362 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 381 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=284, Invalid=1198, Unknown=0, NotChecked=0, Total=1482 [2019-12-07 19:03:15,443 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30920 states. [2019-12-07 19:03:15,654 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30920 to 16874. [2019-12-07 19:03:15,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16874 states. [2019-12-07 19:03:15,681 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16874 states to 16874 states and 51757 transitions. [2019-12-07 19:03:15,681 INFO L78 Accepts]: Start accepts. Automaton has 16874 states and 51757 transitions. Word has length 66 [2019-12-07 19:03:15,681 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:03:15,681 INFO L462 AbstractCegarLoop]: Abstraction has 16874 states and 51757 transitions. [2019-12-07 19:03:15,681 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 19:03:15,681 INFO L276 IsEmpty]: Start isEmpty. Operand 16874 states and 51757 transitions. [2019-12-07 19:03:15,696 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 19:03:15,696 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:03:15,696 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:03:15,696 INFO L410 AbstractCegarLoop]: === Iteration 29 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:03:15,696 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:03:15,696 INFO L82 PathProgramCache]: Analyzing trace with hash -71749557, now seen corresponding path program 4 times [2019-12-07 19:03:15,696 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:03:15,697 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1784088398] [2019-12-07 19:03:15,697 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:03:15,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:03:15,898 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:03:15,898 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1784088398] [2019-12-07 19:03:15,898 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:03:15,898 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 19:03:15,898 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1891110394] [2019-12-07 19:03:15,898 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 19:03:15,898 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:03:15,899 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 19:03:15,899 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=153, Unknown=0, NotChecked=0, Total=182 [2019-12-07 19:03:15,899 INFO L87 Difference]: Start difference. First operand 16874 states and 51757 transitions. Second operand 14 states. [2019-12-07 19:03:17,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:03:17,659 INFO L93 Difference]: Finished difference Result 20834 states and 62192 transitions. [2019-12-07 19:03:17,659 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-12-07 19:03:17,659 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 66 [2019-12-07 19:03:17,660 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:03:17,680 INFO L225 Difference]: With dead ends: 20834 [2019-12-07 19:03:17,680 INFO L226 Difference]: Without dead ends: 19315 [2019-12-07 19:03:17,680 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 153 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=150, Invalid=780, Unknown=0, NotChecked=0, Total=930 [2019-12-07 19:03:17,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19315 states. [2019-12-07 19:03:17,891 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19315 to 16884. [2019-12-07 19:03:17,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16884 states. [2019-12-07 19:03:17,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16884 states to 16884 states and 51588 transitions. [2019-12-07 19:03:17,919 INFO L78 Accepts]: Start accepts. Automaton has 16884 states and 51588 transitions. Word has length 66 [2019-12-07 19:03:17,919 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:03:17,919 INFO L462 AbstractCegarLoop]: Abstraction has 16884 states and 51588 transitions. [2019-12-07 19:03:17,919 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 19:03:17,919 INFO L276 IsEmpty]: Start isEmpty. Operand 16884 states and 51588 transitions. [2019-12-07 19:03:17,933 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 19:03:17,933 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:03:17,934 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:03:17,934 INFO L410 AbstractCegarLoop]: === Iteration 30 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:03:17,934 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:03:17,934 INFO L82 PathProgramCache]: Analyzing trace with hash -952881413, now seen corresponding path program 5 times [2019-12-07 19:03:17,934 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:03:17,934 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [635037637] [2019-12-07 19:03:17,934 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:03:17,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:03:18,298 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:03:18,298 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [635037637] [2019-12-07 19:03:18,298 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:03:18,298 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2019-12-07 19:03:18,298 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [877563890] [2019-12-07 19:03:18,299 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 19:03:18,299 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:03:18,299 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 19:03:18,299 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=236, Unknown=0, NotChecked=0, Total=272 [2019-12-07 19:03:18,299 INFO L87 Difference]: Start difference. First operand 16884 states and 51588 transitions. Second operand 17 states. [2019-12-07 19:03:21,265 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:03:21,266 INFO L93 Difference]: Finished difference Result 20048 states and 60242 transitions. [2019-12-07 19:03:21,266 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-12-07 19:03:21,266 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 66 [2019-12-07 19:03:21,266 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:03:21,286 INFO L225 Difference]: With dead ends: 20048 [2019-12-07 19:03:21,286 INFO L226 Difference]: Without dead ends: 19061 [2019-12-07 19:03:21,287 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 1 SyntacticMatches, 3 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 395 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=246, Invalid=1646, Unknown=0, NotChecked=0, Total=1892 [2019-12-07 19:03:21,344 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19061 states. [2019-12-07 19:03:21,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19061 to 16860. [2019-12-07 19:03:21,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16860 states. [2019-12-07 19:03:21,525 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16860 states to 16860 states and 51519 transitions. [2019-12-07 19:03:21,525 INFO L78 Accepts]: Start accepts. Automaton has 16860 states and 51519 transitions. Word has length 66 [2019-12-07 19:03:21,525 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:03:21,525 INFO L462 AbstractCegarLoop]: Abstraction has 16860 states and 51519 transitions. [2019-12-07 19:03:21,526 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 19:03:21,526 INFO L276 IsEmpty]: Start isEmpty. Operand 16860 states and 51519 transitions. [2019-12-07 19:03:21,540 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 19:03:21,540 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:03:21,540 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:03:21,540 INFO L410 AbstractCegarLoop]: === Iteration 31 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:03:21,540 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:03:21,541 INFO L82 PathProgramCache]: Analyzing trace with hash 1173514763, now seen corresponding path program 6 times [2019-12-07 19:03:21,541 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:03:21,541 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1255793062] [2019-12-07 19:03:21,541 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:03:21,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:03:21,883 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:03:21,883 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1255793062] [2019-12-07 19:03:21,883 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:03:21,883 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2019-12-07 19:03:21,883 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1994819426] [2019-12-07 19:03:21,883 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 19:03:21,883 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:03:21,883 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 19:03:21,884 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=226, Unknown=0, NotChecked=0, Total=272 [2019-12-07 19:03:21,884 INFO L87 Difference]: Start difference. First operand 16860 states and 51519 transitions. Second operand 17 states. [2019-12-07 19:03:23,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:03:23,823 INFO L93 Difference]: Finished difference Result 23472 states and 69990 transitions. [2019-12-07 19:03:23,823 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2019-12-07 19:03:23,823 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 66 [2019-12-07 19:03:23,824 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:03:23,846 INFO L225 Difference]: With dead ends: 23472 [2019-12-07 19:03:23,846 INFO L226 Difference]: Without dead ends: 21866 [2019-12-07 19:03:23,847 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 0 SyntacticMatches, 3 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 762 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=492, Invalid=2160, Unknown=0, NotChecked=0, Total=2652 [2019-12-07 19:03:23,911 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21866 states. [2019-12-07 19:03:24,077 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21866 to 16732. [2019-12-07 19:03:24,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16732 states. [2019-12-07 19:03:24,104 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16732 states to 16732 states and 51186 transitions. [2019-12-07 19:03:24,105 INFO L78 Accepts]: Start accepts. Automaton has 16732 states and 51186 transitions. Word has length 66 [2019-12-07 19:03:24,105 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:03:24,105 INFO L462 AbstractCegarLoop]: Abstraction has 16732 states and 51186 transitions. [2019-12-07 19:03:24,105 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 19:03:24,105 INFO L276 IsEmpty]: Start isEmpty. Operand 16732 states and 51186 transitions. [2019-12-07 19:03:24,119 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 19:03:24,119 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:03:24,119 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:03:24,119 INFO L410 AbstractCegarLoop]: === Iteration 32 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:03:24,120 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:03:24,120 INFO L82 PathProgramCache]: Analyzing trace with hash -457383415, now seen corresponding path program 7 times [2019-12-07 19:03:24,120 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:03:24,120 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1016376871] [2019-12-07 19:03:24,120 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:03:24,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:03:24,247 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:03:24,247 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1016376871] [2019-12-07 19:03:24,247 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:03:24,247 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 19:03:24,247 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [414754920] [2019-12-07 19:03:24,247 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 19:03:24,247 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:03:24,248 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 19:03:24,248 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2019-12-07 19:03:24,248 INFO L87 Difference]: Start difference. First operand 16732 states and 51186 transitions. Second operand 11 states. [2019-12-07 19:03:25,199 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:03:25,199 INFO L93 Difference]: Finished difference Result 20120 states and 61075 transitions. [2019-12-07 19:03:25,200 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 19:03:25,200 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 66 [2019-12-07 19:03:25,200 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:03:25,222 INFO L225 Difference]: With dead ends: 20120 [2019-12-07 19:03:25,223 INFO L226 Difference]: Without dead ends: 19005 [2019-12-07 19:03:25,223 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 65 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=88, Invalid=418, Unknown=0, NotChecked=0, Total=506 [2019-12-07 19:03:25,281 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19005 states. [2019-12-07 19:03:25,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19005 to 16450. [2019-12-07 19:03:25,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16450 states. [2019-12-07 19:03:25,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16450 states to 16450 states and 50374 transitions. [2019-12-07 19:03:25,460 INFO L78 Accepts]: Start accepts. Automaton has 16450 states and 50374 transitions. Word has length 66 [2019-12-07 19:03:25,460 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:03:25,460 INFO L462 AbstractCegarLoop]: Abstraction has 16450 states and 50374 transitions. [2019-12-07 19:03:25,460 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 19:03:25,460 INFO L276 IsEmpty]: Start isEmpty. Operand 16450 states and 50374 transitions. [2019-12-07 19:03:25,474 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 19:03:25,474 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:03:25,474 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:03:25,474 INFO L410 AbstractCegarLoop]: === Iteration 33 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:03:25,474 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:03:25,474 INFO L82 PathProgramCache]: Analyzing trace with hash 579487659, now seen corresponding path program 8 times [2019-12-07 19:03:25,475 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:03:25,475 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [369505597] [2019-12-07 19:03:25,475 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:03:25,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 19:03:25,597 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 19:03:25,597 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [369505597] [2019-12-07 19:03:25,597 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 19:03:25,597 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 19:03:25,597 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1450598637] [2019-12-07 19:03:25,597 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 19:03:25,597 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 19:03:25,597 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 19:03:25,598 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2019-12-07 19:03:25,598 INFO L87 Difference]: Start difference. First operand 16450 states and 50374 transitions. Second operand 11 states. [2019-12-07 19:03:26,393 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 19:03:26,393 INFO L93 Difference]: Finished difference Result 20815 states and 63364 transitions. [2019-12-07 19:03:26,393 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-12-07 19:03:26,393 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 66 [2019-12-07 19:03:26,393 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 19:03:26,415 INFO L225 Difference]: With dead ends: 20815 [2019-12-07 19:03:26,415 INFO L226 Difference]: Without dead ends: 20386 [2019-12-07 19:03:26,415 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 79 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=94, Invalid=458, Unknown=0, NotChecked=0, Total=552 [2019-12-07 19:03:26,476 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20386 states. [2019-12-07 19:03:26,640 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20386 to 16262. [2019-12-07 19:03:26,640 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16262 states. [2019-12-07 19:03:26,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16262 states to 16262 states and 49902 transitions. [2019-12-07 19:03:26,666 INFO L78 Accepts]: Start accepts. Automaton has 16262 states and 49902 transitions. Word has length 66 [2019-12-07 19:03:26,666 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 19:03:26,666 INFO L462 AbstractCegarLoop]: Abstraction has 16262 states and 49902 transitions. [2019-12-07 19:03:26,666 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 19:03:26,666 INFO L276 IsEmpty]: Start isEmpty. Operand 16262 states and 49902 transitions. [2019-12-07 19:03:26,680 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 19:03:26,680 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 19:03:26,680 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 19:03:26,680 INFO L410 AbstractCegarLoop]: === Iteration 34 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 19:03:26,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 19:03:26,680 INFO L82 PathProgramCache]: Analyzing trace with hash 620198601, now seen corresponding path program 9 times [2019-12-07 19:03:26,680 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 19:03:26,681 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1096787349] [2019-12-07 19:03:26,681 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 19:03:26,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 19:03:26,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 19:03:26,757 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 19:03:26,757 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 19:03:26,760 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [895] [895] ULTIMATE.startENTRY-->L825: Formula: (let ((.cse0 (store |v_#valid_71| 0 0))) (and (= (select .cse0 |v_ULTIMATE.start_main_~#t509~0.base_22|) 0) (= v_~z$w_buff0_used~0_749 0) (= v_~weak$$choice2~0_132 0) (= 0 v_~weak$$choice0~0_14) (= v_~z$read_delayed_var~0.offset_6 0) (= |v_ULTIMATE.start_main_~#t509~0.offset_16| 0) (= |v_#NULL.offset_6| 0) (= (store .cse0 |v_ULTIMATE.start_main_~#t509~0.base_22| 1) |v_#valid_69|) (= 0 v_~z$r_buff0_thd3~0_377) (= v_~__unbuffered_cnt~0_128 0) (= v_~z$r_buff0_thd1~0_378 0) (= v_~z$mem_tmp~0_24 0) (< 0 |v_#StackHeapBarrier_15|) (= v_~z$read_delayed_var~0.base_6 0) (= v_~z$r_buff0_thd0~0_195 0) (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t509~0.base_22| 4)) (= v_~y~0_28 0) (= v_~z$w_buff1_used~0_500 0) (= 0 |v_#NULL.base_6|) (= v_~main$tmp_guard1~0_38 0) (= 0 v_~z$flush_delayed~0_43) (= v_~z$read_delayed~0_7 0) (< |v_#StackHeapBarrier_15| |v_ULTIMATE.start_main_~#t509~0.base_22|) (= v_~z$r_buff0_thd2~0_182 0) (= 0 v_~z$r_buff1_thd3~0_396) (= 0 v_~x~0_245) (= v_~z$r_buff1_thd1~0_267 0) (= 0 v_~__unbuffered_p2_EAX~0_35) (= v_~z$r_buff1_thd0~0_294 0) (= v_~z$w_buff0~0_256 0) (= v_~main$tmp_guard0~0_22 0) (= v_~__unbuffered_p2_EBX~0_48 0) (= 0 v_~__unbuffered_p1_EAX~0_41) (= v_~z$r_buff1_thd2~0_280 0) (= v_~z$w_buff1~0_199 0) (= (store |v_#memory_int_20| |v_ULTIMATE.start_main_~#t509~0.base_22| (store (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#t509~0.base_22|) |v_ULTIMATE.start_main_~#t509~0.offset_16| 0)) |v_#memory_int_19|) (= v_~z~0_182 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_15|, #valid=|v_#valid_71|, #memory_int=|v_#memory_int_20|, #length=|v_#length_22|} OutVars{~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_280, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_63|, #NULL.offset=|v_#NULL.offset_6|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_113|, ULTIMATE.start_main_~#t509~0.base=|v_ULTIMATE.start_main_~#t509~0.base_22|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_223|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_72|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_195, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_41, ULTIMATE.start_main_~#t511~0.offset=|v_ULTIMATE.start_main_~#t511~0.offset_14|, ULTIMATE.start_main_~#t509~0.offset=|v_ULTIMATE.start_main_~#t509~0.offset_16|, #length=|v_#length_21|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_35, ~z$mem_tmp~0=v_~z$mem_tmp~0_24, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_48, ULTIMATE.start_main_~#t510~0.offset=|v_ULTIMATE.start_main_~#t510~0.offset_14|, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_8|, ULTIMATE.start_main_~#t510~0.base=|v_ULTIMATE.start_main_~#t510~0.base_19|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_500, ~z$flush_delayed~0=v_~z$flush_delayed~0_43, ~weak$$choice0~0=v_~weak$$choice0~0_14, #StackHeapBarrier=|v_#StackHeapBarrier_15|, ULTIMATE.start_main_~#t511~0.base=|v_ULTIMATE.start_main_~#t511~0.base_17|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_267, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_6, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_377, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_128, ~x~0=v_~x~0_245, ~z$read_delayed~0=v_~z$read_delayed~0_7, ~z$w_buff1~0=v_~z$w_buff1~0_199, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_38, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_45|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_6, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_33|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_294, ~y~0=v_~y~0_28, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_182, ULTIMATE.start_main_#t~nondet46=|v_ULTIMATE.start_main_#t~nondet46_19|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_749, ~z$w_buff0~0=v_~z$w_buff0~0_256, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_7|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_396, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_22, #NULL.base=|v_#NULL.base_6|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_31|, #valid=|v_#valid_69|, #memory_int=|v_#memory_int_19|, ~z~0=v_~z~0_182, ~weak$$choice2~0=v_~weak$$choice2~0_132, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_378} AuxVars[] AssignedVars[~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_~#t509~0.base, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ~z$r_buff0_thd0~0, ~__unbuffered_p1_EAX~0, ULTIMATE.start_main_~#t511~0.offset, ULTIMATE.start_main_~#t509~0.offset, #length, ~__unbuffered_p2_EAX~0, ~z$mem_tmp~0, ~__unbuffered_p2_EBX~0, ULTIMATE.start_main_~#t510~0.offset, ULTIMATE.start_main_#t~nondet45, ULTIMATE.start_main_~#t510~0.base, ~z$w_buff1_used~0, ~z$flush_delayed~0, ~weak$$choice0~0, ULTIMATE.start_main_~#t511~0.base, ~z$r_buff1_thd1~0, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ~__unbuffered_cnt~0, ~x~0, ~z$read_delayed~0, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite48, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite51, ~z$r_buff1_thd0~0, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet46, ~z$w_buff0_used~0, ~z$w_buff0~0, ULTIMATE.start_main_#t~nondet44, ~z$r_buff1_thd3~0, ~main$tmp_guard0~0, #NULL.base, ULTIMATE.start_main_#res, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 19:03:26,761 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [772] [772] L4-->L746: Formula: (and (= v_~z$r_buff0_thd1~0_29 v_~z$r_buff1_thd1~0_17) (= v_~z$r_buff0_thd2~0_25 v_~z$r_buff1_thd2~0_17) (= v_~x~0_11 1) (= v_~z$r_buff0_thd3~0_70 v_~z$r_buff1_thd3~0_54) (= v_~z$r_buff0_thd1~0_28 1) (not (= 0 v_P0Thread1of1ForFork1___VERIFIER_assert_~expression_8)) (= v_~z$r_buff0_thd0~0_26 v_~z$r_buff1_thd0~0_23)) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_26, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_70, P0Thread1of1ForFork1___VERIFIER_assert_~expression=v_P0Thread1of1ForFork1___VERIFIER_assert_~expression_8, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_29, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_25} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_26, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_54, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_23, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_17, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_17, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_70, P0Thread1of1ForFork1___VERIFIER_assert_~expression=v_P0Thread1of1ForFork1___VERIFIER_assert_~expression_8, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_28, ~x~0=v_~x~0_11, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_25} AuxVars[] AssignedVars[~z$r_buff1_thd3~0, ~z$r_buff1_thd0~0, ~z$r_buff1_thd2~0, ~z$r_buff1_thd1~0, ~z$r_buff0_thd1~0, ~x~0] because there is no mapped edge [2019-12-07 19:03:26,761 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [860] [860] L825-1-->L827: Formula: (and (< |v_#StackHeapBarrier_9| |v_ULTIMATE.start_main_~#t510~0.base_11|) (not (= 0 |v_ULTIMATE.start_main_~#t510~0.base_11|)) (= (store |v_#valid_32| |v_ULTIMATE.start_main_~#t510~0.base_11| 1) |v_#valid_31|) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t510~0.base_11| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t510~0.base_11|) |v_ULTIMATE.start_main_~#t510~0.offset_10| 1)) |v_#memory_int_13|) (= (select |v_#valid_32| |v_ULTIMATE.start_main_~#t510~0.base_11|) 0) (= 0 |v_ULTIMATE.start_main_~#t510~0.offset_10|) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t510~0.base_11| 4))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_9|, ULTIMATE.start_main_~#t510~0.offset=|v_ULTIMATE.start_main_~#t510~0.offset_10|, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_4|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_~#t510~0.base=|v_ULTIMATE.start_main_~#t510~0.base_11|, #length=|v_#length_15|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t510~0.offset, ULTIMATE.start_main_#t~nondet44, #valid, #memory_int, ULTIMATE.start_main_~#t510~0.base, #length] because there is no mapped edge [2019-12-07 19:03:26,762 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [856] [856] L827-1-->L829: Formula: (and (= |v_#valid_29| (store |v_#valid_30| |v_ULTIMATE.start_main_~#t511~0.base_12| 1)) (= |v_#length_13| (store |v_#length_14| |v_ULTIMATE.start_main_~#t511~0.base_12| 4)) (= 0 (select |v_#valid_30| |v_ULTIMATE.start_main_~#t511~0.base_12|)) (not (= 0 |v_ULTIMATE.start_main_~#t511~0.base_12|)) (= (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t511~0.base_12| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t511~0.base_12|) |v_ULTIMATE.start_main_~#t511~0.offset_10| 2)) |v_#memory_int_11|) (= |v_ULTIMATE.start_main_~#t511~0.offset_10| 0) (< |v_#StackHeapBarrier_8| |v_ULTIMATE.start_main_~#t511~0.base_12|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_8|, #valid=|v_#valid_30|, #memory_int=|v_#memory_int_12|, #length=|v_#length_14|} OutVars{ULTIMATE.start_main_~#t511~0.base=|v_ULTIMATE.start_main_~#t511~0.base_12|, #StackHeapBarrier=|v_#StackHeapBarrier_8|, ULTIMATE.start_main_~#t511~0.offset=|v_ULTIMATE.start_main_~#t511~0.offset_10|, #valid=|v_#valid_29|, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_5|, #memory_int=|v_#memory_int_11|, #length=|v_#length_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t511~0.base, ULTIMATE.start_main_~#t511~0.offset, #valid, ULTIMATE.start_main_#t~nondet45, #memory_int, #length] because there is no mapped edge [2019-12-07 19:03:26,763 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [843] [843] L766-2-->L766-5: Formula: (let ((.cse1 (= |P1Thread1of1ForFork2_#t~ite10_Out-1833699432| |P1Thread1of1ForFork2_#t~ite9_Out-1833699432|)) (.cse0 (= (mod ~z$w_buff1_used~0_In-1833699432 256) 0)) (.cse2 (= 0 (mod ~z$r_buff1_thd2~0_In-1833699432 256)))) (or (and (not .cse0) .cse1 (not .cse2) (= |P1Thread1of1ForFork2_#t~ite9_Out-1833699432| ~z$w_buff1~0_In-1833699432)) (and .cse1 (or .cse0 .cse2) (= |P1Thread1of1ForFork2_#t~ite9_Out-1833699432| ~z~0_In-1833699432)))) InVars {~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1833699432, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1833699432, ~z$w_buff1~0=~z$w_buff1~0_In-1833699432, ~z~0=~z~0_In-1833699432} OutVars{P1Thread1of1ForFork2_#t~ite9=|P1Thread1of1ForFork2_#t~ite9_Out-1833699432|, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1833699432, P1Thread1of1ForFork2_#t~ite10=|P1Thread1of1ForFork2_#t~ite10_Out-1833699432|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1833699432, ~z$w_buff1~0=~z$w_buff1~0_In-1833699432, ~z~0=~z~0_In-1833699432} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite10] because there is no mapped edge [2019-12-07 19:03:26,764 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [871] [871] L792-->L792-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In729399008 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite24_Out729399008| ~z$w_buff1~0_In729399008) (= |P2Thread1of1ForFork0_#t~ite23_In729399008| |P2Thread1of1ForFork0_#t~ite23_Out729399008|) (not .cse0)) (and .cse0 (let ((.cse1 (= (mod ~z$r_buff0_thd3~0_In729399008 256) 0))) (or (and (= 0 (mod ~z$r_buff1_thd3~0_In729399008 256)) .cse1) (= (mod ~z$w_buff0_used~0_In729399008 256) 0) (and .cse1 (= 0 (mod ~z$w_buff1_used~0_In729399008 256))))) (= |P2Thread1of1ForFork0_#t~ite23_Out729399008| ~z$w_buff1~0_In729399008) (= |P2Thread1of1ForFork0_#t~ite24_Out729399008| |P2Thread1of1ForFork0_#t~ite23_Out729399008|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In729399008, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In729399008, P2Thread1of1ForFork0_#t~ite23=|P2Thread1of1ForFork0_#t~ite23_In729399008|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In729399008, ~z$w_buff1~0=~z$w_buff1~0_In729399008, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In729399008, ~weak$$choice2~0=~weak$$choice2~0_In729399008} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In729399008, P2Thread1of1ForFork0_#t~ite23=|P2Thread1of1ForFork0_#t~ite23_Out729399008|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In729399008, P2Thread1of1ForFork0_#t~ite24=|P2Thread1of1ForFork0_#t~ite24_Out729399008|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In729399008, ~z$w_buff1~0=~z$w_buff1~0_In729399008, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In729399008, ~weak$$choice2~0=~weak$$choice2~0_In729399008} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite23, P2Thread1of1ForFork0_#t~ite24] because there is no mapped edge [2019-12-07 19:03:26,765 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [884] [884] L794-->L794-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In761870436 256))) (.cse5 (= (mod ~z$r_buff1_thd3~0_In761870436 256) 0)) (.cse1 (= |P2Thread1of1ForFork0_#t~ite29_Out761870436| |P2Thread1of1ForFork0_#t~ite30_Out761870436|)) (.cse2 (= (mod ~z$w_buff0_used~0_In761870436 256) 0)) (.cse3 (= (mod ~z$w_buff1_used~0_In761870436 256) 0)) (.cse4 (= 0 (mod ~z$r_buff0_thd3~0_In761870436 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite28_In761870436| |P2Thread1of1ForFork0_#t~ite28_Out761870436|) (or (and (= |P2Thread1of1ForFork0_#t~ite29_Out761870436| |P2Thread1of1ForFork0_#t~ite29_In761870436|) (= |P2Thread1of1ForFork0_#t~ite30_Out761870436| ~z$w_buff1_used~0_In761870436) (not .cse0)) (and .cse0 .cse1 (or .cse2 (and .cse3 .cse4) (and .cse5 .cse4)) (= |P2Thread1of1ForFork0_#t~ite29_Out761870436| ~z$w_buff1_used~0_In761870436)))) (let ((.cse6 (not .cse4))) (and .cse0 (or (not .cse5) .cse6) (= |P2Thread1of1ForFork0_#t~ite28_Out761870436| 0) (= |P2Thread1of1ForFork0_#t~ite29_Out761870436| |P2Thread1of1ForFork0_#t~ite28_Out761870436|) .cse1 (not .cse2) (or (not .cse3) .cse6))))) InVars {P2Thread1of1ForFork0_#t~ite28=|P2Thread1of1ForFork0_#t~ite28_In761870436|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In761870436, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In761870436, ~z$w_buff1_used~0=~z$w_buff1_used~0_In761870436, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In761870436, ~weak$$choice2~0=~weak$$choice2~0_In761870436, P2Thread1of1ForFork0_#t~ite29=|P2Thread1of1ForFork0_#t~ite29_In761870436|} OutVars{P2Thread1of1ForFork0_#t~ite28=|P2Thread1of1ForFork0_#t~ite28_Out761870436|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In761870436, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In761870436, ~z$w_buff1_used~0=~z$w_buff1_used~0_In761870436, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In761870436, P2Thread1of1ForFork0_#t~ite30=|P2Thread1of1ForFork0_#t~ite30_Out761870436|, P2Thread1of1ForFork0_#t~ite29=|P2Thread1of1ForFork0_#t~ite29_Out761870436|, ~weak$$choice2~0=~weak$$choice2~0_In761870436} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite28, P2Thread1of1ForFork0_#t~ite30, P2Thread1of1ForFork0_#t~ite29] because there is no mapped edge [2019-12-07 19:03:26,766 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [890] [890] L794-8-->L796: Formula: (and (= v_~z$w_buff1_used~0_493 |v_P2Thread1of1ForFork0_#t~ite30_36|) (= v_~z$r_buff0_thd3~0_371 v_~z$r_buff0_thd3~0_370) (not (= (mod v_~weak$$choice2~0_130 256) 0))) InVars {~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_371, P2Thread1of1ForFork0_#t~ite30=|v_P2Thread1of1ForFork0_#t~ite30_36|, ~weak$$choice2~0=v_~weak$$choice2~0_130} OutVars{P2Thread1of1ForFork0_#t~ite28=|v_P2Thread1of1ForFork0_#t~ite28_37|, P2Thread1of1ForFork0_#t~ite33=|v_P2Thread1of1ForFork0_#t~ite33_13|, P2Thread1of1ForFork0_#t~ite32=|v_P2Thread1of1ForFork0_#t~ite32_29|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_493, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_370, P2Thread1of1ForFork0_#t~ite31=|v_P2Thread1of1ForFork0_#t~ite31_21|, P2Thread1of1ForFork0_#t~ite30=|v_P2Thread1of1ForFork0_#t~ite30_35|, ~weak$$choice2~0=v_~weak$$choice2~0_130, P2Thread1of1ForFork0_#t~ite29=|v_P2Thread1of1ForFork0_#t~ite29_47|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite28, P2Thread1of1ForFork0_#t~ite33, P2Thread1of1ForFork0_#t~ite32, ~z$w_buff1_used~0, ~z$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite31, P2Thread1of1ForFork0_#t~ite30, P2Thread1of1ForFork0_#t~ite29] because there is no mapped edge [2019-12-07 19:03:26,766 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [795] [795] L798-->L802: Formula: (and (not (= 0 (mod v_~z$flush_delayed~0_10 256))) (= 0 v_~z$flush_delayed~0_9) (= v_~z~0_46 v_~z$mem_tmp~0_7)) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_7, ~z$flush_delayed~0=v_~z$flush_delayed~0_10} OutVars{P2Thread1of1ForFork0_#t~ite37=|v_P2Thread1of1ForFork0_#t~ite37_5|, ~z$mem_tmp~0=v_~z$mem_tmp~0_7, ~z$flush_delayed~0=v_~z$flush_delayed~0_9, ~z~0=v_~z~0_46} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite37, ~z$flush_delayed~0, ~z~0] because there is no mapped edge [2019-12-07 19:03:26,767 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [819] [819] L802-2-->L802-5: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff1_thd3~0_In-1396203001 256))) (.cse1 (= (mod ~z$w_buff1_used~0_In-1396203001 256) 0)) (.cse2 (= |P2Thread1of1ForFork0_#t~ite39_Out-1396203001| |P2Thread1of1ForFork0_#t~ite38_Out-1396203001|))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork0_#t~ite38_Out-1396203001| ~z~0_In-1396203001) .cse2) (and (not .cse0) (not .cse1) (= |P2Thread1of1ForFork0_#t~ite38_Out-1396203001| ~z$w_buff1~0_In-1396203001) .cse2))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1396203001, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1396203001, ~z$w_buff1~0=~z$w_buff1~0_In-1396203001, ~z~0=~z~0_In-1396203001} OutVars{P2Thread1of1ForFork0_#t~ite39=|P2Thread1of1ForFork0_#t~ite39_Out-1396203001|, P2Thread1of1ForFork0_#t~ite38=|P2Thread1of1ForFork0_#t~ite38_Out-1396203001|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1396203001, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1396203001, ~z$w_buff1~0=~z$w_buff1~0_In-1396203001, ~z~0=~z~0_In-1396203001} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite39, P2Thread1of1ForFork0_#t~ite38] because there is no mapped edge [2019-12-07 19:03:26,767 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [823] [823] L803-->L803-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd3~0_In1285957628 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In1285957628 256) 0))) (or (and (or .cse0 .cse1) (= ~z$w_buff0_used~0_In1285957628 |P2Thread1of1ForFork0_#t~ite40_Out1285957628|)) (and (not .cse0) (= |P2Thread1of1ForFork0_#t~ite40_Out1285957628| 0) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1285957628, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1285957628} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1285957628, P2Thread1of1ForFork0_#t~ite40=|P2Thread1of1ForFork0_#t~ite40_Out1285957628|, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1285957628} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite40] because there is no mapped edge [2019-12-07 19:03:26,767 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [818] [818] L804-->L804-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff1_used~0_In-598548221 256))) (.cse1 (= 0 (mod ~z$r_buff1_thd3~0_In-598548221 256))) (.cse2 (= 0 (mod ~z$r_buff0_thd3~0_In-598548221 256))) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In-598548221 256)))) (or (and (= 0 |P2Thread1of1ForFork0_#t~ite41_Out-598548221|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~z$w_buff1_used~0_In-598548221 |P2Thread1of1ForFork0_#t~ite41_Out-598548221|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-598548221, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-598548221, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-598548221, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-598548221} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-598548221, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-598548221, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-598548221, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-598548221, P2Thread1of1ForFork0_#t~ite41=|P2Thread1of1ForFork0_#t~ite41_Out-598548221|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite41] because there is no mapped edge [2019-12-07 19:03:26,768 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [841] [841] L805-->L805-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In1803995242 256))) (.cse0 (= (mod ~z$r_buff0_thd3~0_In1803995242 256) 0))) (or (and (= 0 |P2Thread1of1ForFork0_#t~ite42_Out1803995242|) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= ~z$r_buff0_thd3~0_In1803995242 |P2Thread1of1ForFork0_#t~ite42_Out1803995242|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1803995242, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1803995242} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1803995242, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1803995242, P2Thread1of1ForFork0_#t~ite42=|P2Thread1of1ForFork0_#t~ite42_Out1803995242|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite42] because there is no mapped edge [2019-12-07 19:03:26,768 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [835] [835] L806-->L806-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff1_used~0_In153953061 256))) (.cse1 (= 0 (mod ~z$r_buff1_thd3~0_In153953061 256))) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In153953061 256))) (.cse2 (= 0 (mod ~z$r_buff0_thd3~0_In153953061 256)))) (or (and (= 0 |P2Thread1of1ForFork0_#t~ite43_Out153953061|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (or .cse3 .cse2) (= ~z$r_buff1_thd3~0_In153953061 |P2Thread1of1ForFork0_#t~ite43_Out153953061|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In153953061, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In153953061, ~z$w_buff1_used~0=~z$w_buff1_used~0_In153953061, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In153953061} OutVars{P2Thread1of1ForFork0_#t~ite43=|P2Thread1of1ForFork0_#t~ite43_Out153953061|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In153953061, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In153953061, ~z$w_buff1_used~0=~z$w_buff1_used~0_In153953061, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In153953061} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite43] because there is no mapped edge [2019-12-07 19:03:26,768 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [870] [870] L806-2-->P2EXIT: Formula: (and (= v_~z$r_buff1_thd3~0_308 |v_P2Thread1of1ForFork0_#t~ite43_54|) (= (+ v_~__unbuffered_cnt~0_100 1) v_~__unbuffered_cnt~0_99) (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite43=|v_P2Thread1of1ForFork0_#t~ite43_54|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_100} OutVars{P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, P2Thread1of1ForFork0_#t~ite43=|v_P2Thread1of1ForFork0_#t~ite43_53|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_308, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_99, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#res.base, P2Thread1of1ForFork0_#t~ite43, ~z$r_buff1_thd3~0, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 19:03:26,769 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [838] [838] L747-->L747-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In170321841 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd1~0_In170321841 256)))) (or (and (not .cse0) (= 0 |P0Thread1of1ForFork1_#t~ite5_Out170321841|) (not .cse1)) (and (or .cse0 .cse1) (= ~z$w_buff0_used~0_In170321841 |P0Thread1of1ForFork1_#t~ite5_Out170321841|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In170321841, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In170321841} OutVars{P0Thread1of1ForFork1_#t~ite5=|P0Thread1of1ForFork1_#t~ite5_Out170321841|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In170321841, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In170321841} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite5] because there is no mapped edge [2019-12-07 19:03:26,769 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [842] [842] L748-->L748-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1586403353 256))) (.cse1 (= (mod ~z$r_buff0_thd1~0_In-1586403353 256) 0)) (.cse3 (= 0 (mod ~z$r_buff1_thd1~0_In-1586403353 256))) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In-1586403353 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P0Thread1of1ForFork1_#t~ite6_Out-1586403353|)) (and (or .cse0 .cse1) (= |P0Thread1of1ForFork1_#t~ite6_Out-1586403353| ~z$w_buff1_used~0_In-1586403353) (or .cse3 .cse2)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1586403353, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-1586403353, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1586403353, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1586403353} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1586403353, P0Thread1of1ForFork1_#t~ite6=|P0Thread1of1ForFork1_#t~ite6_Out-1586403353|, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-1586403353, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1586403353, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1586403353} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite6] because there is no mapped edge [2019-12-07 19:03:26,769 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [824] [824] L749-->L750: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In-1327305483 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd1~0_In-1327305483 256))) (.cse2 (= ~z$r_buff0_thd1~0_In-1327305483 ~z$r_buff0_thd1~0_Out-1327305483))) (or (and (= 0 ~z$r_buff0_thd1~0_Out-1327305483) (not .cse0) (not .cse1)) (and .cse1 .cse2) (and .cse0 .cse2))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1327305483, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1327305483} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1327305483, P0Thread1of1ForFork1_#t~ite7=|P0Thread1of1ForFork1_#t~ite7_Out-1327305483|, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_Out-1327305483} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite7, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 19:03:26,769 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [826] [826] L750-->L750-2: Formula: (let ((.cse3 (= 0 (mod ~z$r_buff0_thd1~0_In460971007 256))) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In460971007 256))) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In460971007 256))) (.cse1 (= (mod ~z$r_buff1_thd1~0_In460971007 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P0Thread1of1ForFork1_#t~ite8_Out460971007|)) (and (= |P0Thread1of1ForFork1_#t~ite8_Out460971007| ~z$r_buff1_thd1~0_In460971007) (or .cse3 .cse2) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In460971007, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In460971007, ~z$w_buff1_used~0=~z$w_buff1_used~0_In460971007, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In460971007} OutVars{P0Thread1of1ForFork1_#t~ite8=|P0Thread1of1ForFork1_#t~ite8_Out460971007|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In460971007, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In460971007, ~z$w_buff1_used~0=~z$w_buff1_used~0_In460971007, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In460971007} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite8] because there is no mapped edge [2019-12-07 19:03:26,770 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [853] [853] L750-2-->P0EXIT: Formula: (and (= 0 |v_P0Thread1of1ForFork1_#res.base_3|) (= v_~__unbuffered_cnt~0_71 (+ v_~__unbuffered_cnt~0_72 1)) (= v_~z$r_buff1_thd1~0_83 |v_P0Thread1of1ForFork1_#t~ite8_38|) (= 0 |v_P0Thread1of1ForFork1_#res.offset_3|)) InVars {P0Thread1of1ForFork1_#t~ite8=|v_P0Thread1of1ForFork1_#t~ite8_38|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_72} OutVars{P0Thread1of1ForFork1_#t~ite8=|v_P0Thread1of1ForFork1_#t~ite8_37|, P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_3|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_83, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_71} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite8, P0Thread1of1ForFork1_#res.offset, ~z$r_buff1_thd1~0, P0Thread1of1ForFork1_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 19:03:26,770 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [831] [831] L767-->L767-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In-771211460 256) 0)) (.cse1 (= (mod ~z$r_buff0_thd2~0_In-771211460 256) 0))) (or (and (or .cse0 .cse1) (= ~z$w_buff0_used~0_In-771211460 |P1Thread1of1ForFork2_#t~ite11_Out-771211460|)) (and (= 0 |P1Thread1of1ForFork2_#t~ite11_Out-771211460|) (not .cse0) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-771211460, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-771211460} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-771211460, P1Thread1of1ForFork2_#t~ite11=|P1Thread1of1ForFork2_#t~ite11_Out-771211460|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-771211460} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite11] because there is no mapped edge [2019-12-07 19:03:26,770 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [836] [836] L768-->L768-2: Formula: (let ((.cse2 (= (mod ~z$r_buff1_thd2~0_In766977074 256) 0)) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In766977074 256))) (.cse0 (= (mod ~z$r_buff0_thd2~0_In766977074 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In766977074 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork2_#t~ite12_Out766977074|)) (and (or .cse2 .cse3) (or .cse0 .cse1) (= |P1Thread1of1ForFork2_#t~ite12_Out766977074| ~z$w_buff1_used~0_In766977074)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In766977074, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In766977074, ~z$w_buff1_used~0=~z$w_buff1_used~0_In766977074, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In766977074} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In766977074, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In766977074, ~z$w_buff1_used~0=~z$w_buff1_used~0_In766977074, P1Thread1of1ForFork2_#t~ite12=|P1Thread1of1ForFork2_#t~ite12_Out766977074|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In766977074} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite12] because there is no mapped edge [2019-12-07 19:03:26,770 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [825] [825] L769-->L769-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In524736670 256))) (.cse1 (= (mod ~z$w_buff0_used~0_In524736670 256) 0))) (or (and (or .cse0 .cse1) (= ~z$r_buff0_thd2~0_In524736670 |P1Thread1of1ForFork2_#t~ite13_Out524736670|)) (and (= |P1Thread1of1ForFork2_#t~ite13_Out524736670| 0) (not .cse0) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In524736670, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In524736670} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In524736670, P1Thread1of1ForFork2_#t~ite13=|P1Thread1of1ForFork2_#t~ite13_Out524736670|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In524736670} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite13] because there is no mapped edge [2019-12-07 19:03:26,771 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [821] [821] L770-->L770-2: Formula: (let ((.cse2 (= (mod ~z$w_buff1_used~0_In1080248869 256) 0)) (.cse3 (= (mod ~z$r_buff1_thd2~0_In1080248869 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In1080248869 256))) (.cse0 (= (mod ~z$r_buff0_thd2~0_In1080248869 256) 0))) (or (and (or .cse0 .cse1) (= ~z$r_buff1_thd2~0_In1080248869 |P1Thread1of1ForFork2_#t~ite14_Out1080248869|) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= 0 |P1Thread1of1ForFork2_#t~ite14_Out1080248869|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1080248869, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1080248869, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1080248869, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1080248869} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1080248869, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1080248869, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1080248869, P1Thread1of1ForFork2_#t~ite14=|P1Thread1of1ForFork2_#t~ite14_Out1080248869|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1080248869} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite14] because there is no mapped edge [2019-12-07 19:03:26,771 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [868] [868] L770-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_94 1) v_~__unbuffered_cnt~0_93) (= v_~z$r_buff1_thd2~0_188 |v_P1Thread1of1ForFork2_#t~ite14_48|)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_94, P1Thread1of1ForFork2_#t~ite14=|v_P1Thread1of1ForFork2_#t~ite14_48|} OutVars{P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_188, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_93, P1Thread1of1ForFork2_#t~ite14=|v_P1Thread1of1ForFork2_#t~ite14_47|, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#res.offset, ~z$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#t~ite14, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-12-07 19:03:26,771 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L829-1-->L835: Formula: (and (= v_~main$tmp_guard0~0_6 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_14) 1 0) 0) 0 1)) (not (= 0 (mod v_~main$tmp_guard0~0_6 256)))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14} OutVars{ULTIMATE.start_main_#t~nondet46=|v_ULTIMATE.start_main_#t~nondet46_5|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet46, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 19:03:26,771 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [832] [832] L835-2-->L835-4: Formula: (let ((.cse1 (= (mod ~z$w_buff1_used~0_In138805361 256) 0)) (.cse0 (= (mod ~z$r_buff1_thd0~0_In138805361 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite47_Out138805361| ~z~0_In138805361)) (and (not .cse1) (not .cse0) (= |ULTIMATE.start_main_#t~ite47_Out138805361| ~z$w_buff1~0_In138805361)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In138805361, ~z$w_buff1_used~0=~z$w_buff1_used~0_In138805361, ~z$w_buff1~0=~z$w_buff1~0_In138805361, ~z~0=~z~0_In138805361} OutVars{~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In138805361, ULTIMATE.start_main_#t~ite47=|ULTIMATE.start_main_#t~ite47_Out138805361|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In138805361, ~z$w_buff1~0=~z$w_buff1~0_In138805361, ~z~0=~z~0_In138805361} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47] because there is no mapped edge [2019-12-07 19:03:26,772 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L835-4-->L836: Formula: (= v_~z~0_40 |v_ULTIMATE.start_main_#t~ite47_9|) InVars {ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_9|} OutVars{ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_8|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_12|, ~z~0=v_~z~0_40} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite48, ~z~0] because there is no mapped edge [2019-12-07 19:03:26,772 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [830] [830] L836-->L836-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd0~0_In210317701 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In210317701 256)))) (or (and (= |ULTIMATE.start_main_#t~ite49_Out210317701| ~z$w_buff0_used~0_In210317701) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite49_Out210317701| 0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In210317701, ~z$w_buff0_used~0=~z$w_buff0_used~0_In210317701} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In210317701, ~z$w_buff0_used~0=~z$w_buff0_used~0_In210317701, ULTIMATE.start_main_#t~ite49=|ULTIMATE.start_main_#t~ite49_Out210317701|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite49] because there is no mapped edge [2019-12-07 19:03:26,772 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [817] [817] L837-->L837-2: Formula: (let ((.cse3 (= 0 (mod ~z$r_buff0_thd0~0_In-540213841 256))) (.cse2 (= (mod ~z$w_buff0_used~0_In-540213841 256) 0)) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In-540213841 256))) (.cse1 (= (mod ~z$r_buff1_thd0~0_In-540213841 256) 0))) (or (and (or .cse0 .cse1) (= ~z$w_buff1_used~0_In-540213841 |ULTIMATE.start_main_#t~ite50_Out-540213841|) (or .cse2 .cse3)) (and (= 0 |ULTIMATE.start_main_#t~ite50_Out-540213841|) (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1)))))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-540213841, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-540213841, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-540213841, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-540213841} OutVars{ULTIMATE.start_main_#t~ite50=|ULTIMATE.start_main_#t~ite50_Out-540213841|, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-540213841, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-540213841, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-540213841, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-540213841} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite50] because there is no mapped edge [2019-12-07 19:03:26,772 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [833] [833] L838-->L838-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd0~0_In2124289530 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In2124289530 256)))) (or (and (= 0 |ULTIMATE.start_main_#t~ite51_Out2124289530|) (not .cse0) (not .cse1)) (and (= ~z$r_buff0_thd0~0_In2124289530 |ULTIMATE.start_main_#t~ite51_Out2124289530|) (or .cse1 .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In2124289530, ~z$w_buff0_used~0=~z$w_buff0_used~0_In2124289530} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In2124289530, ULTIMATE.start_main_#t~ite51=|ULTIMATE.start_main_#t~ite51_Out2124289530|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In2124289530} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite51] because there is no mapped edge [2019-12-07 19:03:26,773 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [834] [834] L839-->L839-2: Formula: (let ((.cse2 (= (mod ~z$r_buff0_thd0~0_In-1958677726 256) 0)) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In-1958677726 256))) (.cse1 (= 0 (mod ~z$r_buff1_thd0~0_In-1958677726 256))) (.cse0 (= (mod ~z$w_buff1_used~0_In-1958677726 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite52_Out-1958677726| ~z$r_buff1_thd0~0_In-1958677726) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= |ULTIMATE.start_main_#t~ite52_Out-1958677726| 0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1958677726, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1958677726, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1958677726, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1958677726} OutVars{ULTIMATE.start_main_#t~ite52=|ULTIMATE.start_main_#t~ite52_Out-1958677726|, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1958677726, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1958677726, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1958677726, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1958677726} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52] because there is no mapped edge [2019-12-07 19:03:26,773 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [877] [877] L839-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_~z$r_buff1_thd0~0_221 |v_ULTIMATE.start_main_#t~ite52_38|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_12 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_12 0) (= (ite (= (ite (not (and (= 0 v_~__unbuffered_p1_EAX~0_22) (= 1 v_~__unbuffered_p2_EAX~0_21) (= v_~__unbuffered_p2_EBX~0_34 0) (= 2 v_~x~0_186))) 1 0) 0) 0 1) v_~main$tmp_guard1~0_16) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8| (mod v_~main$tmp_guard1~0_16 256))) InVars {ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_38|, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_34, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_22, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_21, ~x~0=v_~x~0_186} OutVars{ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_37|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_12, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_34, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_22, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_221, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_16, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_21, ~x~0=v_~x~0_186, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start___VERIFIER_assert_~expression, ~z$r_buff1_thd0~0, ~main$tmp_guard1~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 19:03:26,822 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 07:03:26 BasicIcfg [2019-12-07 19:03:26,822 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 19:03:26,822 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 19:03:26,822 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 19:03:26,822 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 19:03:26,823 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:59:24" (3/4) ... [2019-12-07 19:03:26,824 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 19:03:26,824 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [895] [895] ULTIMATE.startENTRY-->L825: Formula: (let ((.cse0 (store |v_#valid_71| 0 0))) (and (= (select .cse0 |v_ULTIMATE.start_main_~#t509~0.base_22|) 0) (= v_~z$w_buff0_used~0_749 0) (= v_~weak$$choice2~0_132 0) (= 0 v_~weak$$choice0~0_14) (= v_~z$read_delayed_var~0.offset_6 0) (= |v_ULTIMATE.start_main_~#t509~0.offset_16| 0) (= |v_#NULL.offset_6| 0) (= (store .cse0 |v_ULTIMATE.start_main_~#t509~0.base_22| 1) |v_#valid_69|) (= 0 v_~z$r_buff0_thd3~0_377) (= v_~__unbuffered_cnt~0_128 0) (= v_~z$r_buff0_thd1~0_378 0) (= v_~z$mem_tmp~0_24 0) (< 0 |v_#StackHeapBarrier_15|) (= v_~z$read_delayed_var~0.base_6 0) (= v_~z$r_buff0_thd0~0_195 0) (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t509~0.base_22| 4)) (= v_~y~0_28 0) (= v_~z$w_buff1_used~0_500 0) (= 0 |v_#NULL.base_6|) (= v_~main$tmp_guard1~0_38 0) (= 0 v_~z$flush_delayed~0_43) (= v_~z$read_delayed~0_7 0) (< |v_#StackHeapBarrier_15| |v_ULTIMATE.start_main_~#t509~0.base_22|) (= v_~z$r_buff0_thd2~0_182 0) (= 0 v_~z$r_buff1_thd3~0_396) (= 0 v_~x~0_245) (= v_~z$r_buff1_thd1~0_267 0) (= 0 v_~__unbuffered_p2_EAX~0_35) (= v_~z$r_buff1_thd0~0_294 0) (= v_~z$w_buff0~0_256 0) (= v_~main$tmp_guard0~0_22 0) (= v_~__unbuffered_p2_EBX~0_48 0) (= 0 v_~__unbuffered_p1_EAX~0_41) (= v_~z$r_buff1_thd2~0_280 0) (= v_~z$w_buff1~0_199 0) (= (store |v_#memory_int_20| |v_ULTIMATE.start_main_~#t509~0.base_22| (store (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#t509~0.base_22|) |v_ULTIMATE.start_main_~#t509~0.offset_16| 0)) |v_#memory_int_19|) (= v_~z~0_182 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_15|, #valid=|v_#valid_71|, #memory_int=|v_#memory_int_20|, #length=|v_#length_22|} OutVars{~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_280, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_63|, #NULL.offset=|v_#NULL.offset_6|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_113|, ULTIMATE.start_main_~#t509~0.base=|v_ULTIMATE.start_main_~#t509~0.base_22|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_223|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_72|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_195, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_41, ULTIMATE.start_main_~#t511~0.offset=|v_ULTIMATE.start_main_~#t511~0.offset_14|, ULTIMATE.start_main_~#t509~0.offset=|v_ULTIMATE.start_main_~#t509~0.offset_16|, #length=|v_#length_21|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_35, ~z$mem_tmp~0=v_~z$mem_tmp~0_24, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_48, ULTIMATE.start_main_~#t510~0.offset=|v_ULTIMATE.start_main_~#t510~0.offset_14|, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_8|, ULTIMATE.start_main_~#t510~0.base=|v_ULTIMATE.start_main_~#t510~0.base_19|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_500, ~z$flush_delayed~0=v_~z$flush_delayed~0_43, ~weak$$choice0~0=v_~weak$$choice0~0_14, #StackHeapBarrier=|v_#StackHeapBarrier_15|, ULTIMATE.start_main_~#t511~0.base=|v_ULTIMATE.start_main_~#t511~0.base_17|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_267, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_6, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_377, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_128, ~x~0=v_~x~0_245, ~z$read_delayed~0=v_~z$read_delayed~0_7, ~z$w_buff1~0=v_~z$w_buff1~0_199, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_38, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_45|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_6, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_33|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_294, ~y~0=v_~y~0_28, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_182, ULTIMATE.start_main_#t~nondet46=|v_ULTIMATE.start_main_#t~nondet46_19|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_749, ~z$w_buff0~0=v_~z$w_buff0~0_256, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_7|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_396, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_22, #NULL.base=|v_#NULL.base_6|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_31|, #valid=|v_#valid_69|, #memory_int=|v_#memory_int_19|, ~z~0=v_~z~0_182, ~weak$$choice2~0=v_~weak$$choice2~0_132, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_378} AuxVars[] AssignedVars[~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_~#t509~0.base, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ~z$r_buff0_thd0~0, ~__unbuffered_p1_EAX~0, ULTIMATE.start_main_~#t511~0.offset, ULTIMATE.start_main_~#t509~0.offset, #length, ~__unbuffered_p2_EAX~0, ~z$mem_tmp~0, ~__unbuffered_p2_EBX~0, ULTIMATE.start_main_~#t510~0.offset, ULTIMATE.start_main_#t~nondet45, ULTIMATE.start_main_~#t510~0.base, ~z$w_buff1_used~0, ~z$flush_delayed~0, ~weak$$choice0~0, ULTIMATE.start_main_~#t511~0.base, ~z$r_buff1_thd1~0, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ~__unbuffered_cnt~0, ~x~0, ~z$read_delayed~0, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite48, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_#t~ite51, ~z$r_buff1_thd0~0, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet46, ~z$w_buff0_used~0, ~z$w_buff0~0, ULTIMATE.start_main_#t~nondet44, ~z$r_buff1_thd3~0, ~main$tmp_guard0~0, #NULL.base, ULTIMATE.start_main_#res, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 19:03:26,825 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [772] [772] L4-->L746: Formula: (and (= v_~z$r_buff0_thd1~0_29 v_~z$r_buff1_thd1~0_17) (= v_~z$r_buff0_thd2~0_25 v_~z$r_buff1_thd2~0_17) (= v_~x~0_11 1) (= v_~z$r_buff0_thd3~0_70 v_~z$r_buff1_thd3~0_54) (= v_~z$r_buff0_thd1~0_28 1) (not (= 0 v_P0Thread1of1ForFork1___VERIFIER_assert_~expression_8)) (= v_~z$r_buff0_thd0~0_26 v_~z$r_buff1_thd0~0_23)) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_26, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_70, P0Thread1of1ForFork1___VERIFIER_assert_~expression=v_P0Thread1of1ForFork1___VERIFIER_assert_~expression_8, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_29, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_25} OutVars{~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_26, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_54, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_23, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_17, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_17, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_70, P0Thread1of1ForFork1___VERIFIER_assert_~expression=v_P0Thread1of1ForFork1___VERIFIER_assert_~expression_8, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_28, ~x~0=v_~x~0_11, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_25} AuxVars[] AssignedVars[~z$r_buff1_thd3~0, ~z$r_buff1_thd0~0, ~z$r_buff1_thd2~0, ~z$r_buff1_thd1~0, ~z$r_buff0_thd1~0, ~x~0] because there is no mapped edge [2019-12-07 19:03:26,825 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [860] [860] L825-1-->L827: Formula: (and (< |v_#StackHeapBarrier_9| |v_ULTIMATE.start_main_~#t510~0.base_11|) (not (= 0 |v_ULTIMATE.start_main_~#t510~0.base_11|)) (= (store |v_#valid_32| |v_ULTIMATE.start_main_~#t510~0.base_11| 1) |v_#valid_31|) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t510~0.base_11| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t510~0.base_11|) |v_ULTIMATE.start_main_~#t510~0.offset_10| 1)) |v_#memory_int_13|) (= (select |v_#valid_32| |v_ULTIMATE.start_main_~#t510~0.base_11|) 0) (= 0 |v_ULTIMATE.start_main_~#t510~0.offset_10|) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t510~0.base_11| 4))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_9|, ULTIMATE.start_main_~#t510~0.offset=|v_ULTIMATE.start_main_~#t510~0.offset_10|, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_4|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_~#t510~0.base=|v_ULTIMATE.start_main_~#t510~0.base_11|, #length=|v_#length_15|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t510~0.offset, ULTIMATE.start_main_#t~nondet44, #valid, #memory_int, ULTIMATE.start_main_~#t510~0.base, #length] because there is no mapped edge [2019-12-07 19:03:26,826 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [856] [856] L827-1-->L829: Formula: (and (= |v_#valid_29| (store |v_#valid_30| |v_ULTIMATE.start_main_~#t511~0.base_12| 1)) (= |v_#length_13| (store |v_#length_14| |v_ULTIMATE.start_main_~#t511~0.base_12| 4)) (= 0 (select |v_#valid_30| |v_ULTIMATE.start_main_~#t511~0.base_12|)) (not (= 0 |v_ULTIMATE.start_main_~#t511~0.base_12|)) (= (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t511~0.base_12| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t511~0.base_12|) |v_ULTIMATE.start_main_~#t511~0.offset_10| 2)) |v_#memory_int_11|) (= |v_ULTIMATE.start_main_~#t511~0.offset_10| 0) (< |v_#StackHeapBarrier_8| |v_ULTIMATE.start_main_~#t511~0.base_12|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_8|, #valid=|v_#valid_30|, #memory_int=|v_#memory_int_12|, #length=|v_#length_14|} OutVars{ULTIMATE.start_main_~#t511~0.base=|v_ULTIMATE.start_main_~#t511~0.base_12|, #StackHeapBarrier=|v_#StackHeapBarrier_8|, ULTIMATE.start_main_~#t511~0.offset=|v_ULTIMATE.start_main_~#t511~0.offset_10|, #valid=|v_#valid_29|, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_5|, #memory_int=|v_#memory_int_11|, #length=|v_#length_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t511~0.base, ULTIMATE.start_main_~#t511~0.offset, #valid, ULTIMATE.start_main_#t~nondet45, #memory_int, #length] because there is no mapped edge [2019-12-07 19:03:26,827 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [843] [843] L766-2-->L766-5: Formula: (let ((.cse1 (= |P1Thread1of1ForFork2_#t~ite10_Out-1833699432| |P1Thread1of1ForFork2_#t~ite9_Out-1833699432|)) (.cse0 (= (mod ~z$w_buff1_used~0_In-1833699432 256) 0)) (.cse2 (= 0 (mod ~z$r_buff1_thd2~0_In-1833699432 256)))) (or (and (not .cse0) .cse1 (not .cse2) (= |P1Thread1of1ForFork2_#t~ite9_Out-1833699432| ~z$w_buff1~0_In-1833699432)) (and .cse1 (or .cse0 .cse2) (= |P1Thread1of1ForFork2_#t~ite9_Out-1833699432| ~z~0_In-1833699432)))) InVars {~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1833699432, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1833699432, ~z$w_buff1~0=~z$w_buff1~0_In-1833699432, ~z~0=~z~0_In-1833699432} OutVars{P1Thread1of1ForFork2_#t~ite9=|P1Thread1of1ForFork2_#t~ite9_Out-1833699432|, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1833699432, P1Thread1of1ForFork2_#t~ite10=|P1Thread1of1ForFork2_#t~ite10_Out-1833699432|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1833699432, ~z$w_buff1~0=~z$w_buff1~0_In-1833699432, ~z~0=~z~0_In-1833699432} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite10] because there is no mapped edge [2019-12-07 19:03:26,828 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [871] [871] L792-->L792-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In729399008 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite24_Out729399008| ~z$w_buff1~0_In729399008) (= |P2Thread1of1ForFork0_#t~ite23_In729399008| |P2Thread1of1ForFork0_#t~ite23_Out729399008|) (not .cse0)) (and .cse0 (let ((.cse1 (= (mod ~z$r_buff0_thd3~0_In729399008 256) 0))) (or (and (= 0 (mod ~z$r_buff1_thd3~0_In729399008 256)) .cse1) (= (mod ~z$w_buff0_used~0_In729399008 256) 0) (and .cse1 (= 0 (mod ~z$w_buff1_used~0_In729399008 256))))) (= |P2Thread1of1ForFork0_#t~ite23_Out729399008| ~z$w_buff1~0_In729399008) (= |P2Thread1of1ForFork0_#t~ite24_Out729399008| |P2Thread1of1ForFork0_#t~ite23_Out729399008|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In729399008, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In729399008, P2Thread1of1ForFork0_#t~ite23=|P2Thread1of1ForFork0_#t~ite23_In729399008|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In729399008, ~z$w_buff1~0=~z$w_buff1~0_In729399008, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In729399008, ~weak$$choice2~0=~weak$$choice2~0_In729399008} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In729399008, P2Thread1of1ForFork0_#t~ite23=|P2Thread1of1ForFork0_#t~ite23_Out729399008|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In729399008, P2Thread1of1ForFork0_#t~ite24=|P2Thread1of1ForFork0_#t~ite24_Out729399008|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In729399008, ~z$w_buff1~0=~z$w_buff1~0_In729399008, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In729399008, ~weak$$choice2~0=~weak$$choice2~0_In729399008} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite23, P2Thread1of1ForFork0_#t~ite24] because there is no mapped edge [2019-12-07 19:03:26,829 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [884] [884] L794-->L794-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In761870436 256))) (.cse5 (= (mod ~z$r_buff1_thd3~0_In761870436 256) 0)) (.cse1 (= |P2Thread1of1ForFork0_#t~ite29_Out761870436| |P2Thread1of1ForFork0_#t~ite30_Out761870436|)) (.cse2 (= (mod ~z$w_buff0_used~0_In761870436 256) 0)) (.cse3 (= (mod ~z$w_buff1_used~0_In761870436 256) 0)) (.cse4 (= 0 (mod ~z$r_buff0_thd3~0_In761870436 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite28_In761870436| |P2Thread1of1ForFork0_#t~ite28_Out761870436|) (or (and (= |P2Thread1of1ForFork0_#t~ite29_Out761870436| |P2Thread1of1ForFork0_#t~ite29_In761870436|) (= |P2Thread1of1ForFork0_#t~ite30_Out761870436| ~z$w_buff1_used~0_In761870436) (not .cse0)) (and .cse0 .cse1 (or .cse2 (and .cse3 .cse4) (and .cse5 .cse4)) (= |P2Thread1of1ForFork0_#t~ite29_Out761870436| ~z$w_buff1_used~0_In761870436)))) (let ((.cse6 (not .cse4))) (and .cse0 (or (not .cse5) .cse6) (= |P2Thread1of1ForFork0_#t~ite28_Out761870436| 0) (= |P2Thread1of1ForFork0_#t~ite29_Out761870436| |P2Thread1of1ForFork0_#t~ite28_Out761870436|) .cse1 (not .cse2) (or (not .cse3) .cse6))))) InVars {P2Thread1of1ForFork0_#t~ite28=|P2Thread1of1ForFork0_#t~ite28_In761870436|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In761870436, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In761870436, ~z$w_buff1_used~0=~z$w_buff1_used~0_In761870436, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In761870436, ~weak$$choice2~0=~weak$$choice2~0_In761870436, P2Thread1of1ForFork0_#t~ite29=|P2Thread1of1ForFork0_#t~ite29_In761870436|} OutVars{P2Thread1of1ForFork0_#t~ite28=|P2Thread1of1ForFork0_#t~ite28_Out761870436|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In761870436, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In761870436, ~z$w_buff1_used~0=~z$w_buff1_used~0_In761870436, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In761870436, P2Thread1of1ForFork0_#t~ite30=|P2Thread1of1ForFork0_#t~ite30_Out761870436|, P2Thread1of1ForFork0_#t~ite29=|P2Thread1of1ForFork0_#t~ite29_Out761870436|, ~weak$$choice2~0=~weak$$choice2~0_In761870436} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite28, P2Thread1of1ForFork0_#t~ite30, P2Thread1of1ForFork0_#t~ite29] because there is no mapped edge [2019-12-07 19:03:26,830 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [890] [890] L794-8-->L796: Formula: (and (= v_~z$w_buff1_used~0_493 |v_P2Thread1of1ForFork0_#t~ite30_36|) (= v_~z$r_buff0_thd3~0_371 v_~z$r_buff0_thd3~0_370) (not (= (mod v_~weak$$choice2~0_130 256) 0))) InVars {~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_371, P2Thread1of1ForFork0_#t~ite30=|v_P2Thread1of1ForFork0_#t~ite30_36|, ~weak$$choice2~0=v_~weak$$choice2~0_130} OutVars{P2Thread1of1ForFork0_#t~ite28=|v_P2Thread1of1ForFork0_#t~ite28_37|, P2Thread1of1ForFork0_#t~ite33=|v_P2Thread1of1ForFork0_#t~ite33_13|, P2Thread1of1ForFork0_#t~ite32=|v_P2Thread1of1ForFork0_#t~ite32_29|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_493, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_370, P2Thread1of1ForFork0_#t~ite31=|v_P2Thread1of1ForFork0_#t~ite31_21|, P2Thread1of1ForFork0_#t~ite30=|v_P2Thread1of1ForFork0_#t~ite30_35|, ~weak$$choice2~0=v_~weak$$choice2~0_130, P2Thread1of1ForFork0_#t~ite29=|v_P2Thread1of1ForFork0_#t~ite29_47|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite28, P2Thread1of1ForFork0_#t~ite33, P2Thread1of1ForFork0_#t~ite32, ~z$w_buff1_used~0, ~z$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite31, P2Thread1of1ForFork0_#t~ite30, P2Thread1of1ForFork0_#t~ite29] because there is no mapped edge [2019-12-07 19:03:26,830 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [795] [795] L798-->L802: Formula: (and (not (= 0 (mod v_~z$flush_delayed~0_10 256))) (= 0 v_~z$flush_delayed~0_9) (= v_~z~0_46 v_~z$mem_tmp~0_7)) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_7, ~z$flush_delayed~0=v_~z$flush_delayed~0_10} OutVars{P2Thread1of1ForFork0_#t~ite37=|v_P2Thread1of1ForFork0_#t~ite37_5|, ~z$mem_tmp~0=v_~z$mem_tmp~0_7, ~z$flush_delayed~0=v_~z$flush_delayed~0_9, ~z~0=v_~z~0_46} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite37, ~z$flush_delayed~0, ~z~0] because there is no mapped edge [2019-12-07 19:03:26,831 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [819] [819] L802-2-->L802-5: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff1_thd3~0_In-1396203001 256))) (.cse1 (= (mod ~z$w_buff1_used~0_In-1396203001 256) 0)) (.cse2 (= |P2Thread1of1ForFork0_#t~ite39_Out-1396203001| |P2Thread1of1ForFork0_#t~ite38_Out-1396203001|))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork0_#t~ite38_Out-1396203001| ~z~0_In-1396203001) .cse2) (and (not .cse0) (not .cse1) (= |P2Thread1of1ForFork0_#t~ite38_Out-1396203001| ~z$w_buff1~0_In-1396203001) .cse2))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1396203001, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1396203001, ~z$w_buff1~0=~z$w_buff1~0_In-1396203001, ~z~0=~z~0_In-1396203001} OutVars{P2Thread1of1ForFork0_#t~ite39=|P2Thread1of1ForFork0_#t~ite39_Out-1396203001|, P2Thread1of1ForFork0_#t~ite38=|P2Thread1of1ForFork0_#t~ite38_Out-1396203001|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1396203001, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1396203001, ~z$w_buff1~0=~z$w_buff1~0_In-1396203001, ~z~0=~z~0_In-1396203001} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite39, P2Thread1of1ForFork0_#t~ite38] because there is no mapped edge [2019-12-07 19:03:26,831 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [823] [823] L803-->L803-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd3~0_In1285957628 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In1285957628 256) 0))) (or (and (or .cse0 .cse1) (= ~z$w_buff0_used~0_In1285957628 |P2Thread1of1ForFork0_#t~ite40_Out1285957628|)) (and (not .cse0) (= |P2Thread1of1ForFork0_#t~ite40_Out1285957628| 0) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1285957628, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1285957628} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1285957628, P2Thread1of1ForFork0_#t~ite40=|P2Thread1of1ForFork0_#t~ite40_Out1285957628|, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1285957628} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite40] because there is no mapped edge [2019-12-07 19:03:26,831 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [818] [818] L804-->L804-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff1_used~0_In-598548221 256))) (.cse1 (= 0 (mod ~z$r_buff1_thd3~0_In-598548221 256))) (.cse2 (= 0 (mod ~z$r_buff0_thd3~0_In-598548221 256))) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In-598548221 256)))) (or (and (= 0 |P2Thread1of1ForFork0_#t~ite41_Out-598548221|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~z$w_buff1_used~0_In-598548221 |P2Thread1of1ForFork0_#t~ite41_Out-598548221|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-598548221, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-598548221, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-598548221, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-598548221} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-598548221, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-598548221, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-598548221, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-598548221, P2Thread1of1ForFork0_#t~ite41=|P2Thread1of1ForFork0_#t~ite41_Out-598548221|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite41] because there is no mapped edge [2019-12-07 19:03:26,832 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [841] [841] L805-->L805-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In1803995242 256))) (.cse0 (= (mod ~z$r_buff0_thd3~0_In1803995242 256) 0))) (or (and (= 0 |P2Thread1of1ForFork0_#t~ite42_Out1803995242|) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= ~z$r_buff0_thd3~0_In1803995242 |P2Thread1of1ForFork0_#t~ite42_Out1803995242|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1803995242, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1803995242} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1803995242, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1803995242, P2Thread1of1ForFork0_#t~ite42=|P2Thread1of1ForFork0_#t~ite42_Out1803995242|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite42] because there is no mapped edge [2019-12-07 19:03:26,832 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [835] [835] L806-->L806-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff1_used~0_In153953061 256))) (.cse1 (= 0 (mod ~z$r_buff1_thd3~0_In153953061 256))) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In153953061 256))) (.cse2 (= 0 (mod ~z$r_buff0_thd3~0_In153953061 256)))) (or (and (= 0 |P2Thread1of1ForFork0_#t~ite43_Out153953061|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (or .cse3 .cse2) (= ~z$r_buff1_thd3~0_In153953061 |P2Thread1of1ForFork0_#t~ite43_Out153953061|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In153953061, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In153953061, ~z$w_buff1_used~0=~z$w_buff1_used~0_In153953061, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In153953061} OutVars{P2Thread1of1ForFork0_#t~ite43=|P2Thread1of1ForFork0_#t~ite43_Out153953061|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In153953061, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In153953061, ~z$w_buff1_used~0=~z$w_buff1_used~0_In153953061, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In153953061} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite43] because there is no mapped edge [2019-12-07 19:03:26,832 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [870] [870] L806-2-->P2EXIT: Formula: (and (= v_~z$r_buff1_thd3~0_308 |v_P2Thread1of1ForFork0_#t~ite43_54|) (= (+ v_~__unbuffered_cnt~0_100 1) v_~__unbuffered_cnt~0_99) (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite43=|v_P2Thread1of1ForFork0_#t~ite43_54|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_100} OutVars{P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, P2Thread1of1ForFork0_#t~ite43=|v_P2Thread1of1ForFork0_#t~ite43_53|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_308, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_99, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#res.base, P2Thread1of1ForFork0_#t~ite43, ~z$r_buff1_thd3~0, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 19:03:26,833 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [838] [838] L747-->L747-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In170321841 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd1~0_In170321841 256)))) (or (and (not .cse0) (= 0 |P0Thread1of1ForFork1_#t~ite5_Out170321841|) (not .cse1)) (and (or .cse0 .cse1) (= ~z$w_buff0_used~0_In170321841 |P0Thread1of1ForFork1_#t~ite5_Out170321841|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In170321841, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In170321841} OutVars{P0Thread1of1ForFork1_#t~ite5=|P0Thread1of1ForFork1_#t~ite5_Out170321841|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In170321841, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In170321841} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite5] because there is no mapped edge [2019-12-07 19:03:26,833 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [842] [842] L748-->L748-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1586403353 256))) (.cse1 (= (mod ~z$r_buff0_thd1~0_In-1586403353 256) 0)) (.cse3 (= 0 (mod ~z$r_buff1_thd1~0_In-1586403353 256))) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In-1586403353 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P0Thread1of1ForFork1_#t~ite6_Out-1586403353|)) (and (or .cse0 .cse1) (= |P0Thread1of1ForFork1_#t~ite6_Out-1586403353| ~z$w_buff1_used~0_In-1586403353) (or .cse3 .cse2)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1586403353, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-1586403353, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1586403353, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1586403353} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1586403353, P0Thread1of1ForFork1_#t~ite6=|P0Thread1of1ForFork1_#t~ite6_Out-1586403353|, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-1586403353, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1586403353, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1586403353} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite6] because there is no mapped edge [2019-12-07 19:03:26,834 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [824] [824] L749-->L750: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In-1327305483 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd1~0_In-1327305483 256))) (.cse2 (= ~z$r_buff0_thd1~0_In-1327305483 ~z$r_buff0_thd1~0_Out-1327305483))) (or (and (= 0 ~z$r_buff0_thd1~0_Out-1327305483) (not .cse0) (not .cse1)) (and .cse1 .cse2) (and .cse0 .cse2))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1327305483, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1327305483} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1327305483, P0Thread1of1ForFork1_#t~ite7=|P0Thread1of1ForFork1_#t~ite7_Out-1327305483|, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_Out-1327305483} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite7, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 19:03:26,834 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [826] [826] L750-->L750-2: Formula: (let ((.cse3 (= 0 (mod ~z$r_buff0_thd1~0_In460971007 256))) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In460971007 256))) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In460971007 256))) (.cse1 (= (mod ~z$r_buff1_thd1~0_In460971007 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P0Thread1of1ForFork1_#t~ite8_Out460971007|)) (and (= |P0Thread1of1ForFork1_#t~ite8_Out460971007| ~z$r_buff1_thd1~0_In460971007) (or .cse3 .cse2) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In460971007, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In460971007, ~z$w_buff1_used~0=~z$w_buff1_used~0_In460971007, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In460971007} OutVars{P0Thread1of1ForFork1_#t~ite8=|P0Thread1of1ForFork1_#t~ite8_Out460971007|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In460971007, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In460971007, ~z$w_buff1_used~0=~z$w_buff1_used~0_In460971007, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In460971007} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite8] because there is no mapped edge [2019-12-07 19:03:26,834 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [853] [853] L750-2-->P0EXIT: Formula: (and (= 0 |v_P0Thread1of1ForFork1_#res.base_3|) (= v_~__unbuffered_cnt~0_71 (+ v_~__unbuffered_cnt~0_72 1)) (= v_~z$r_buff1_thd1~0_83 |v_P0Thread1of1ForFork1_#t~ite8_38|) (= 0 |v_P0Thread1of1ForFork1_#res.offset_3|)) InVars {P0Thread1of1ForFork1_#t~ite8=|v_P0Thread1of1ForFork1_#t~ite8_38|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_72} OutVars{P0Thread1of1ForFork1_#t~ite8=|v_P0Thread1of1ForFork1_#t~ite8_37|, P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_3|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_83, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_71} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite8, P0Thread1of1ForFork1_#res.offset, ~z$r_buff1_thd1~0, P0Thread1of1ForFork1_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 19:03:26,834 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [831] [831] L767-->L767-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In-771211460 256) 0)) (.cse1 (= (mod ~z$r_buff0_thd2~0_In-771211460 256) 0))) (or (and (or .cse0 .cse1) (= ~z$w_buff0_used~0_In-771211460 |P1Thread1of1ForFork2_#t~ite11_Out-771211460|)) (and (= 0 |P1Thread1of1ForFork2_#t~ite11_Out-771211460|) (not .cse0) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-771211460, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-771211460} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-771211460, P1Thread1of1ForFork2_#t~ite11=|P1Thread1of1ForFork2_#t~ite11_Out-771211460|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-771211460} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite11] because there is no mapped edge [2019-12-07 19:03:26,834 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [836] [836] L768-->L768-2: Formula: (let ((.cse2 (= (mod ~z$r_buff1_thd2~0_In766977074 256) 0)) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In766977074 256))) (.cse0 (= (mod ~z$r_buff0_thd2~0_In766977074 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In766977074 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork2_#t~ite12_Out766977074|)) (and (or .cse2 .cse3) (or .cse0 .cse1) (= |P1Thread1of1ForFork2_#t~ite12_Out766977074| ~z$w_buff1_used~0_In766977074)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In766977074, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In766977074, ~z$w_buff1_used~0=~z$w_buff1_used~0_In766977074, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In766977074} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In766977074, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In766977074, ~z$w_buff1_used~0=~z$w_buff1_used~0_In766977074, P1Thread1of1ForFork2_#t~ite12=|P1Thread1of1ForFork2_#t~ite12_Out766977074|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In766977074} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite12] because there is no mapped edge [2019-12-07 19:03:26,835 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [825] [825] L769-->L769-2: Formula: (let ((.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In524736670 256))) (.cse1 (= (mod ~z$w_buff0_used~0_In524736670 256) 0))) (or (and (or .cse0 .cse1) (= ~z$r_buff0_thd2~0_In524736670 |P1Thread1of1ForFork2_#t~ite13_Out524736670|)) (and (= |P1Thread1of1ForFork2_#t~ite13_Out524736670| 0) (not .cse0) (not .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In524736670, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In524736670} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In524736670, P1Thread1of1ForFork2_#t~ite13=|P1Thread1of1ForFork2_#t~ite13_Out524736670|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In524736670} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite13] because there is no mapped edge [2019-12-07 19:03:26,835 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [821] [821] L770-->L770-2: Formula: (let ((.cse2 (= (mod ~z$w_buff1_used~0_In1080248869 256) 0)) (.cse3 (= (mod ~z$r_buff1_thd2~0_In1080248869 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In1080248869 256))) (.cse0 (= (mod ~z$r_buff0_thd2~0_In1080248869 256) 0))) (or (and (or .cse0 .cse1) (= ~z$r_buff1_thd2~0_In1080248869 |P1Thread1of1ForFork2_#t~ite14_Out1080248869|) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= 0 |P1Thread1of1ForFork2_#t~ite14_Out1080248869|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1080248869, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1080248869, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1080248869, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1080248869} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1080248869, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1080248869, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1080248869, P1Thread1of1ForFork2_#t~ite14=|P1Thread1of1ForFork2_#t~ite14_Out1080248869|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1080248869} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite14] because there is no mapped edge [2019-12-07 19:03:26,835 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [868] [868] L770-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_94 1) v_~__unbuffered_cnt~0_93) (= v_~z$r_buff1_thd2~0_188 |v_P1Thread1of1ForFork2_#t~ite14_48|)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_94, P1Thread1of1ForFork2_#t~ite14=|v_P1Thread1of1ForFork2_#t~ite14_48|} OutVars{P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_188, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_93, P1Thread1of1ForFork2_#t~ite14=|v_P1Thread1of1ForFork2_#t~ite14_47|, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#res.offset, ~z$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#t~ite14, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-12-07 19:03:26,835 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L829-1-->L835: Formula: (and (= v_~main$tmp_guard0~0_6 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_14) 1 0) 0) 0 1)) (not (= 0 (mod v_~main$tmp_guard0~0_6 256)))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14} OutVars{ULTIMATE.start_main_#t~nondet46=|v_ULTIMATE.start_main_#t~nondet46_5|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet46, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 19:03:26,836 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [832] [832] L835-2-->L835-4: Formula: (let ((.cse1 (= (mod ~z$w_buff1_used~0_In138805361 256) 0)) (.cse0 (= (mod ~z$r_buff1_thd0~0_In138805361 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite47_Out138805361| ~z~0_In138805361)) (and (not .cse1) (not .cse0) (= |ULTIMATE.start_main_#t~ite47_Out138805361| ~z$w_buff1~0_In138805361)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In138805361, ~z$w_buff1_used~0=~z$w_buff1_used~0_In138805361, ~z$w_buff1~0=~z$w_buff1~0_In138805361, ~z~0=~z~0_In138805361} OutVars{~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In138805361, ULTIMATE.start_main_#t~ite47=|ULTIMATE.start_main_#t~ite47_Out138805361|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In138805361, ~z$w_buff1~0=~z$w_buff1~0_In138805361, ~z~0=~z~0_In138805361} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47] because there is no mapped edge [2019-12-07 19:03:26,836 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L835-4-->L836: Formula: (= v_~z~0_40 |v_ULTIMATE.start_main_#t~ite47_9|) InVars {ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_9|} OutVars{ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_8|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_12|, ~z~0=v_~z~0_40} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite48, ~z~0] because there is no mapped edge [2019-12-07 19:03:26,836 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [830] [830] L836-->L836-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd0~0_In210317701 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In210317701 256)))) (or (and (= |ULTIMATE.start_main_#t~ite49_Out210317701| ~z$w_buff0_used~0_In210317701) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite49_Out210317701| 0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In210317701, ~z$w_buff0_used~0=~z$w_buff0_used~0_In210317701} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In210317701, ~z$w_buff0_used~0=~z$w_buff0_used~0_In210317701, ULTIMATE.start_main_#t~ite49=|ULTIMATE.start_main_#t~ite49_Out210317701|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite49] because there is no mapped edge [2019-12-07 19:03:26,836 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [817] [817] L837-->L837-2: Formula: (let ((.cse3 (= 0 (mod ~z$r_buff0_thd0~0_In-540213841 256))) (.cse2 (= (mod ~z$w_buff0_used~0_In-540213841 256) 0)) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In-540213841 256))) (.cse1 (= (mod ~z$r_buff1_thd0~0_In-540213841 256) 0))) (or (and (or .cse0 .cse1) (= ~z$w_buff1_used~0_In-540213841 |ULTIMATE.start_main_#t~ite50_Out-540213841|) (or .cse2 .cse3)) (and (= 0 |ULTIMATE.start_main_#t~ite50_Out-540213841|) (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1)))))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-540213841, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-540213841, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-540213841, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-540213841} OutVars{ULTIMATE.start_main_#t~ite50=|ULTIMATE.start_main_#t~ite50_Out-540213841|, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-540213841, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-540213841, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-540213841, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-540213841} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite50] because there is no mapped edge [2019-12-07 19:03:26,837 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [833] [833] L838-->L838-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd0~0_In2124289530 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In2124289530 256)))) (or (and (= 0 |ULTIMATE.start_main_#t~ite51_Out2124289530|) (not .cse0) (not .cse1)) (and (= ~z$r_buff0_thd0~0_In2124289530 |ULTIMATE.start_main_#t~ite51_Out2124289530|) (or .cse1 .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In2124289530, ~z$w_buff0_used~0=~z$w_buff0_used~0_In2124289530} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In2124289530, ULTIMATE.start_main_#t~ite51=|ULTIMATE.start_main_#t~ite51_Out2124289530|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In2124289530} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite51] because there is no mapped edge [2019-12-07 19:03:26,837 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [834] [834] L839-->L839-2: Formula: (let ((.cse2 (= (mod ~z$r_buff0_thd0~0_In-1958677726 256) 0)) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In-1958677726 256))) (.cse1 (= 0 (mod ~z$r_buff1_thd0~0_In-1958677726 256))) (.cse0 (= (mod ~z$w_buff1_used~0_In-1958677726 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite52_Out-1958677726| ~z$r_buff1_thd0~0_In-1958677726) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= |ULTIMATE.start_main_#t~ite52_Out-1958677726| 0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1958677726, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1958677726, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1958677726, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1958677726} OutVars{ULTIMATE.start_main_#t~ite52=|ULTIMATE.start_main_#t~ite52_Out-1958677726|, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1958677726, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1958677726, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In-1958677726, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1958677726} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52] because there is no mapped edge [2019-12-07 19:03:26,837 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [877] [877] L839-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_~z$r_buff1_thd0~0_221 |v_ULTIMATE.start_main_#t~ite52_38|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_12 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_12 0) (= (ite (= (ite (not (and (= 0 v_~__unbuffered_p1_EAX~0_22) (= 1 v_~__unbuffered_p2_EAX~0_21) (= v_~__unbuffered_p2_EBX~0_34 0) (= 2 v_~x~0_186))) 1 0) 0) 0 1) v_~main$tmp_guard1~0_16) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8| (mod v_~main$tmp_guard1~0_16 256))) InVars {ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_38|, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_34, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_22, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_21, ~x~0=v_~x~0_186} OutVars{ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_37|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_12, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_34, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_22, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_221, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_16, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_21, ~x~0=v_~x~0_186, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start___VERIFIER_assert_~expression, ~z$r_buff1_thd0~0, ~main$tmp_guard1~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 19:03:26,886 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_62a55107-5fa3-4010-b348-791676e8ae59/bin/uautomizer/witness.graphml [2019-12-07 19:03:26,887 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 19:03:26,888 INFO L168 Benchmark]: Toolchain (without parser) took 243226.56 ms. Allocated memory was 1.0 GB in the beginning and 9.1 GB in the end (delta: 8.0 GB). Free memory was 939.3 MB in the beginning and 3.7 GB in the end (delta: -2.7 GB). Peak memory consumption was 5.3 GB. Max. memory is 11.5 GB. [2019-12-07 19:03:26,888 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 960.8 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 19:03:26,888 INFO L168 Benchmark]: CACSL2BoogieTranslator took 401.79 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 102.2 MB). Free memory was 939.3 MB in the beginning and 1.1 GB in the end (delta: -125.3 MB). Peak memory consumption was 18.2 MB. Max. memory is 11.5 GB. [2019-12-07 19:03:26,888 INFO L168 Benchmark]: Boogie Procedure Inliner took 37.51 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 19:03:26,889 INFO L168 Benchmark]: Boogie Preprocessor took 25.30 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 19:03:26,889 INFO L168 Benchmark]: RCFGBuilder took 412.78 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 57.3 MB). Peak memory consumption was 57.3 MB. Max. memory is 11.5 GB. [2019-12-07 19:03:26,889 INFO L168 Benchmark]: TraceAbstraction took 242281.25 ms. Allocated memory was 1.1 GB in the beginning and 9.1 GB in the end (delta: 7.9 GB). Free memory was 1.0 GB in the beginning and 3.7 GB in the end (delta: -2.7 GB). Peak memory consumption was 5.2 GB. Max. memory is 11.5 GB. [2019-12-07 19:03:26,889 INFO L168 Benchmark]: Witness Printer took 64.62 ms. Allocated memory is still 9.1 GB. Free memory was 3.7 GB in the beginning and 3.7 GB in the end (delta: 38.9 MB). Peak memory consumption was 38.9 MB. Max. memory is 11.5 GB. [2019-12-07 19:03:26,891 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 960.8 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 401.79 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 102.2 MB). Free memory was 939.3 MB in the beginning and 1.1 GB in the end (delta: -125.3 MB). Peak memory consumption was 18.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 37.51 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 25.30 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 412.78 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 57.3 MB). Peak memory consumption was 57.3 MB. Max. memory is 11.5 GB. * TraceAbstraction took 242281.25 ms. Allocated memory was 1.1 GB in the beginning and 9.1 GB in the end (delta: 7.9 GB). Free memory was 1.0 GB in the beginning and 3.7 GB in the end (delta: -2.7 GB). Peak memory consumption was 5.2 GB. Max. memory is 11.5 GB. * Witness Printer took 64.62 ms. Allocated memory is still 9.1 GB. Free memory was 3.7 GB in the beginning and 3.7 GB in the end (delta: 38.9 MB). Peak memory consumption was 38.9 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.2s, 176 ProgramPointsBefore, 94 ProgramPointsAfterwards, 213 TransitionsBefore, 105 TransitionsAfterwards, 19004 CoEnabledTransitionPairs, 12 FixpointIterations, 33 TrivialSequentialCompositions, 53 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 34 ConcurrentYvCompositions, 30 ChoiceCompositions, 7044 VarBasedMoverChecksPositive, 336 VarBasedMoverChecksNegative, 168 SemBasedMoverChecksPositive, 252 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.9s, 0 MoverChecksTotal, 130103 CheckedPairsTotal, 120 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L825] FCALL, FORK 0 pthread_create(&t509, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L731] 1 z$w_buff1 = z$w_buff0 [L732] 1 z$w_buff0 = 1 [L733] 1 z$w_buff1_used = z$w_buff0_used [L734] 1 z$w_buff0_used = (_Bool)1 [L746] EXPR 1 z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L827] FCALL, FORK 0 pthread_create(&t510, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L760] 2 x = 2 [L763] 2 __unbuffered_p1_EAX = y VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L766] EXPR 2 z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L829] FCALL, FORK 0 pthread_create(&t511, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L780] 3 y = 1 [L783] 3 __unbuffered_p2_EAX = y [L786] 3 weak$$choice0 = __VERIFIER_nondet_bool() [L787] 3 weak$$choice2 = __VERIFIER_nondet_bool() [L788] 3 z$flush_delayed = weak$$choice2 [L789] 3 z$mem_tmp = z VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L790] EXPR 3 !z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff1) VAL [!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L790] 3 z = !z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff1) [L766] 2 z = z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z) [L791] EXPR 3 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff0))=1, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L791] 3 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff0)) [L792] 3 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff1 : z$w_buff1)) [L793] EXPR 3 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used))=1, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L793] 3 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used)) [L796] EXPR 3 weak$$choice2 ? z$r_buff1_thd3 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$r_buff1_thd3 : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, weak$$choice2 ? z$r_buff1_thd3 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$r_buff1_thd3 : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0))=0, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L796] 3 z$r_buff1_thd3 = weak$$choice2 ? z$r_buff1_thd3 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$r_buff1_thd3 : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) [L797] 3 __unbuffered_p2_EBX = z VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L802] EXPR 3 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L802] 3 z = z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) [L803] 3 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used [L804] 3 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used [L805] 3 z$r_buff0_thd3 = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 [L746] 1 z = z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) [L747] 1 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$w_buff0_used [L748] 1 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd1 || z$w_buff1_used && z$r_buff1_thd1 ? (_Bool)0 : z$w_buff1_used [L767] 2 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used [L768] 2 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$w_buff1_used [L769] 2 z$r_buff0_thd2 = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2 [L835] 0 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, x=2, y=1, z=1, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L836] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L837] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L838] 0 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 167 locations, 2 error locations. Result: UNSAFE, OverallTime: 242.1s, OverallIterations: 34, TraceHistogramMax: 1, AutomataDifference: 62.8s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 7228 SDtfs, 9391 SDslu, 27107 SDs, 0 SdLazy, 22512 SolverSat, 486 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 17.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 486 GetRequests, 39 SyntacticMatches, 27 SemanticMatches, 420 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4372 ImplicationChecksByTransitivity, 7.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=372573occurred in iteration=7, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 154.7s AutomataMinimizationTime, 33 MinimizatonAttempts, 496666 StatesRemovedByMinimization, 30 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 2.5s InterpolantComputationTime, 1262 NumberOfCodeBlocks, 1262 NumberOfCodeBlocksAsserted, 34 NumberOfCheckSat, 1163 ConstructedInterpolants, 0 QuantifiedInterpolants, 416048 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 33 InterpolantComputations, 33 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...