./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/mix019_tso.oepc.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_67fafc63-f118-40bf-8219-8f2ad0b7af69/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_67fafc63-f118-40bf-8219-8f2ad0b7af69/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_67fafc63-f118-40bf-8219-8f2ad0b7af69/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_67fafc63-f118-40bf-8219-8f2ad0b7af69/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/mix019_tso.oepc.i -s /tmp/vcloud-vcloud-master/worker/run_dir_67fafc63-f118-40bf-8219-8f2ad0b7af69/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_67fafc63-f118-40bf-8219-8f2ad0b7af69/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash de66e8bc7694077cbe406f19dae0a2831174e80d ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 14:25:18,900 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 14:25:18,902 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 14:25:18,909 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 14:25:18,909 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 14:25:18,910 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 14:25:18,911 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 14:25:18,912 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 14:25:18,913 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 14:25:18,914 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 14:25:18,914 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 14:25:18,915 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 14:25:18,915 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 14:25:18,916 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 14:25:18,917 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 14:25:18,917 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 14:25:18,918 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 14:25:18,919 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 14:25:18,920 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 14:25:18,921 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 14:25:18,922 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 14:25:18,923 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 14:25:18,924 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 14:25:18,924 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 14:25:18,926 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 14:25:18,926 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 14:25:18,926 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 14:25:18,926 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 14:25:18,927 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 14:25:18,927 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 14:25:18,927 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 14:25:18,928 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 14:25:18,928 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 14:25:18,929 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 14:25:18,929 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 14:25:18,929 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 14:25:18,930 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 14:25:18,930 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 14:25:18,930 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 14:25:18,930 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 14:25:18,931 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 14:25:18,931 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_67fafc63-f118-40bf-8219-8f2ad0b7af69/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 14:25:18,940 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 14:25:18,940 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 14:25:18,941 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 14:25:18,941 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 14:25:18,941 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 14:25:18,942 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 14:25:18,942 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 14:25:18,942 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 14:25:18,942 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 14:25:18,942 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 14:25:18,942 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 14:25:18,942 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 14:25:18,942 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 14:25:18,942 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 14:25:18,942 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 14:25:18,943 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 14:25:18,943 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 14:25:18,943 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 14:25:18,943 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 14:25:18,943 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 14:25:18,943 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 14:25:18,943 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 14:25:18,943 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 14:25:18,943 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 14:25:18,944 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 14:25:18,944 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 14:25:18,944 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 14:25:18,944 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 14:25:18,944 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 14:25:18,944 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_67fafc63-f118-40bf-8219-8f2ad0b7af69/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> de66e8bc7694077cbe406f19dae0a2831174e80d [2019-12-07 14:25:19,043 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 14:25:19,052 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 14:25:19,054 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 14:25:19,055 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 14:25:19,056 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 14:25:19,056 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_67fafc63-f118-40bf-8219-8f2ad0b7af69/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/mix019_tso.oepc.i [2019-12-07 14:25:19,096 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_67fafc63-f118-40bf-8219-8f2ad0b7af69/bin/uautomizer/data/6b3a66a6e/c6a2282738454a4a9771561c181c77c1/FLAGda6e21a80 [2019-12-07 14:25:19,551 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 14:25:19,551 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_67fafc63-f118-40bf-8219-8f2ad0b7af69/sv-benchmarks/c/pthread-wmm/mix019_tso.oepc.i [2019-12-07 14:25:19,561 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_67fafc63-f118-40bf-8219-8f2ad0b7af69/bin/uautomizer/data/6b3a66a6e/c6a2282738454a4a9771561c181c77c1/FLAGda6e21a80 [2019-12-07 14:25:19,573 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_67fafc63-f118-40bf-8219-8f2ad0b7af69/bin/uautomizer/data/6b3a66a6e/c6a2282738454a4a9771561c181c77c1 [2019-12-07 14:25:19,576 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 14:25:19,577 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 14:25:19,578 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 14:25:19,578 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 14:25:19,581 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 14:25:19,582 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 02:25:19" (1/1) ... [2019-12-07 14:25:19,584 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6a1693e9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:25:19, skipping insertion in model container [2019-12-07 14:25:19,584 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 02:25:19" (1/1) ... [2019-12-07 14:25:19,591 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 14:25:19,620 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 14:25:19,874 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 14:25:19,882 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 14:25:19,925 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 14:25:19,971 INFO L208 MainTranslator]: Completed translation [2019-12-07 14:25:19,971 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:25:19 WrapperNode [2019-12-07 14:25:19,971 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 14:25:19,972 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 14:25:19,972 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 14:25:19,972 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 14:25:19,977 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:25:19" (1/1) ... [2019-12-07 14:25:19,991 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:25:19" (1/1) ... [2019-12-07 14:25:20,013 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 14:25:20,013 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 14:25:20,013 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 14:25:20,013 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 14:25:20,020 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:25:19" (1/1) ... [2019-12-07 14:25:20,020 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:25:19" (1/1) ... [2019-12-07 14:25:20,023 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:25:19" (1/1) ... [2019-12-07 14:25:20,023 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:25:19" (1/1) ... [2019-12-07 14:25:20,030 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:25:19" (1/1) ... [2019-12-07 14:25:20,033 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:25:19" (1/1) ... [2019-12-07 14:25:20,035 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:25:19" (1/1) ... [2019-12-07 14:25:20,039 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 14:25:20,039 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 14:25:20,039 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 14:25:20,039 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 14:25:20,040 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:25:19" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_67fafc63-f118-40bf-8219-8f2ad0b7af69/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 14:25:20,081 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 14:25:20,081 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 14:25:20,081 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 14:25:20,081 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 14:25:20,081 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 14:25:20,082 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 14:25:20,082 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 14:25:20,082 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 14:25:20,082 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 14:25:20,082 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 14:25:20,082 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 14:25:20,082 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 14:25:20,082 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 14:25:20,083 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 14:25:20,450 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 14:25:20,450 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 14:25:20,451 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 02:25:20 BoogieIcfgContainer [2019-12-07 14:25:20,451 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 14:25:20,452 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 14:25:20,453 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 14:25:20,455 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 14:25:20,455 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 02:25:19" (1/3) ... [2019-12-07 14:25:20,456 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@69ed326a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 02:25:20, skipping insertion in model container [2019-12-07 14:25:20,456 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 02:25:19" (2/3) ... [2019-12-07 14:25:20,456 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@69ed326a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 02:25:20, skipping insertion in model container [2019-12-07 14:25:20,456 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 02:25:20" (3/3) ... [2019-12-07 14:25:20,458 INFO L109 eAbstractionObserver]: Analyzing ICFG mix019_tso.oepc.i [2019-12-07 14:25:20,466 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 14:25:20,467 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 14:25:20,473 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 14:25:20,474 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 14:25:20,497 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,497 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,497 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,497 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,497 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,497 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,497 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,498 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,498 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,498 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,498 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,498 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,498 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,498 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,498 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,499 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,499 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,499 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,499 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,499 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,499 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,499 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,499 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,499 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,500 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,500 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,500 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,500 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,500 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,500 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,501 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,501 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,501 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,501 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,501 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,501 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,501 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,501 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,502 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,502 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,502 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,502 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,502 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,502 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,502 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,503 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,503 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,503 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,503 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,503 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,503 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,503 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,503 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,503 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,504 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,504 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,504 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,504 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,504 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,504 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,504 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,504 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,504 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,505 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,505 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,505 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,505 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,505 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,505 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,505 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,505 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,506 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,506 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,506 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,506 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,506 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,506 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,506 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,506 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,506 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,507 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,507 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,507 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,507 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,507 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,507 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,507 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,507 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,507 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,508 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,508 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,508 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,508 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,508 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 14:25:20,519 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 14:25:20,532 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 14:25:20,532 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 14:25:20,532 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 14:25:20,532 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 14:25:20,532 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 14:25:20,532 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 14:25:20,532 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 14:25:20,533 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 14:25:20,543 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 176 places, 213 transitions [2019-12-07 14:25:20,544 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 176 places, 213 transitions [2019-12-07 14:25:20,599 INFO L134 PetriNetUnfolder]: 47/210 cut-off events. [2019-12-07 14:25:20,599 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 14:25:20,609 INFO L76 FinitePrefix]: Finished finitePrefix Result has 220 conditions, 210 events. 47/210 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 581 event pairs. 9/170 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 14:25:20,625 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 176 places, 213 transitions [2019-12-07 14:25:20,655 INFO L134 PetriNetUnfolder]: 47/210 cut-off events. [2019-12-07 14:25:20,655 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 14:25:20,661 INFO L76 FinitePrefix]: Finished finitePrefix Result has 220 conditions, 210 events. 47/210 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 581 event pairs. 9/170 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 14:25:20,675 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 17074 [2019-12-07 14:25:20,676 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 14:25:23,509 WARN L192 SmtUtils]: Spent 122.00 ms on a formula simplification. DAG size of input: 84 DAG size of output: 82 [2019-12-07 14:25:23,753 INFO L206 etLargeBlockEncoding]: Checked pairs total: 88380 [2019-12-07 14:25:23,753 INFO L214 etLargeBlockEncoding]: Total number of compositions: 115 [2019-12-07 14:25:23,755 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 94 places, 103 transitions [2019-12-07 14:25:39,931 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 118050 states. [2019-12-07 14:25:39,933 INFO L276 IsEmpty]: Start isEmpty. Operand 118050 states. [2019-12-07 14:25:39,937 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-12-07 14:25:39,937 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:39,937 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-12-07 14:25:39,937 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:39,941 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:39,941 INFO L82 PathProgramCache]: Analyzing trace with hash 819981841, now seen corresponding path program 1 times [2019-12-07 14:25:39,947 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:25:39,947 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1395199570] [2019-12-07 14:25:39,947 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:40,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:40,082 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:40,083 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1395199570] [2019-12-07 14:25:40,083 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:40,084 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 14:25:40,084 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1669741263] [2019-12-07 14:25:40,087 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:25:40,087 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:25:40,096 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:25:40,096 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:25:40,097 INFO L87 Difference]: Start difference. First operand 118050 states. Second operand 3 states. [2019-12-07 14:25:40,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:40,871 INFO L93 Difference]: Finished difference Result 117660 states and 499306 transitions. [2019-12-07 14:25:40,871 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:25:40,872 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 5 [2019-12-07 14:25:40,873 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:41,746 INFO L225 Difference]: With dead ends: 117660 [2019-12-07 14:25:41,746 INFO L226 Difference]: Without dead ends: 115112 [2019-12-07 14:25:41,747 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:25:45,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115112 states. [2019-12-07 14:25:48,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115112 to 115112. [2019-12-07 14:25:48,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115112 states. [2019-12-07 14:25:48,628 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115112 states to 115112 states and 488918 transitions. [2019-12-07 14:25:48,629 INFO L78 Accepts]: Start accepts. Automaton has 115112 states and 488918 transitions. Word has length 5 [2019-12-07 14:25:48,629 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:48,629 INFO L462 AbstractCegarLoop]: Abstraction has 115112 states and 488918 transitions. [2019-12-07 14:25:48,629 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:25:48,629 INFO L276 IsEmpty]: Start isEmpty. Operand 115112 states and 488918 transitions. [2019-12-07 14:25:48,632 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-12-07 14:25:48,632 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:48,632 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:48,633 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:48,633 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:48,633 INFO L82 PathProgramCache]: Analyzing trace with hash 690822117, now seen corresponding path program 1 times [2019-12-07 14:25:48,633 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:25:48,633 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1678243418] [2019-12-07 14:25:48,634 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:48,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:48,706 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:48,707 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1678243418] [2019-12-07 14:25:48,707 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:48,707 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 14:25:48,707 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1047906550] [2019-12-07 14:25:48,709 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 14:25:48,709 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:25:48,709 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 14:25:48,709 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 14:25:48,709 INFO L87 Difference]: Start difference. First operand 115112 states and 488918 transitions. Second operand 4 states. [2019-12-07 14:25:49,920 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:25:49,920 INFO L93 Difference]: Finished difference Result 180042 states and 736423 transitions. [2019-12-07 14:25:49,921 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 14:25:49,921 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-12-07 14:25:49,921 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:25:50,448 INFO L225 Difference]: With dead ends: 180042 [2019-12-07 14:25:50,448 INFO L226 Difference]: Without dead ends: 179993 [2019-12-07 14:25:50,449 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:25:54,933 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179993 states. [2019-12-07 14:25:59,006 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179993 to 163765. [2019-12-07 14:25:59,007 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 163765 states. [2019-12-07 14:25:59,768 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 163765 states to 163765 states and 677555 transitions. [2019-12-07 14:25:59,768 INFO L78 Accepts]: Start accepts. Automaton has 163765 states and 677555 transitions. Word has length 11 [2019-12-07 14:25:59,769 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:25:59,769 INFO L462 AbstractCegarLoop]: Abstraction has 163765 states and 677555 transitions. [2019-12-07 14:25:59,769 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 14:25:59,769 INFO L276 IsEmpty]: Start isEmpty. Operand 163765 states and 677555 transitions. [2019-12-07 14:25:59,775 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 14:25:59,775 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:25:59,775 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:25:59,776 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:25:59,776 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:25:59,776 INFO L82 PathProgramCache]: Analyzing trace with hash -2114852839, now seen corresponding path program 1 times [2019-12-07 14:25:59,776 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:25:59,776 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2044703493] [2019-12-07 14:25:59,776 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:25:59,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:25:59,824 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:25:59,824 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2044703493] [2019-12-07 14:25:59,824 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:25:59,824 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 14:25:59,825 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1638798602] [2019-12-07 14:25:59,825 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 14:25:59,825 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:25:59,825 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 14:25:59,825 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 14:25:59,825 INFO L87 Difference]: Start difference. First operand 163765 states and 677555 transitions. Second operand 4 states. [2019-12-07 14:26:01,000 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:26:01,001 INFO L93 Difference]: Finished difference Result 234635 states and 948933 transitions. [2019-12-07 14:26:01,001 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 14:26:01,001 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 14:26:01,002 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:26:01,641 INFO L225 Difference]: With dead ends: 234635 [2019-12-07 14:26:01,641 INFO L226 Difference]: Without dead ends: 234572 [2019-12-07 14:26:01,642 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:26:06,961 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 234572 states. [2019-12-07 14:26:12,097 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 234572 to 198233. [2019-12-07 14:26:12,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 198233 states. [2019-12-07 14:26:12,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 198233 states to 198233 states and 814440 transitions. [2019-12-07 14:26:12,700 INFO L78 Accepts]: Start accepts. Automaton has 198233 states and 814440 transitions. Word has length 13 [2019-12-07 14:26:12,700 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:26:12,700 INFO L462 AbstractCegarLoop]: Abstraction has 198233 states and 814440 transitions. [2019-12-07 14:26:12,701 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 14:26:12,701 INFO L276 IsEmpty]: Start isEmpty. Operand 198233 states and 814440 transitions. [2019-12-07 14:26:12,703 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 14:26:12,703 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:26:12,704 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:26:12,704 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:26:12,704 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:26:12,704 INFO L82 PathProgramCache]: Analyzing trace with hash -389644701, now seen corresponding path program 1 times [2019-12-07 14:26:12,704 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:26:12,704 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [96634674] [2019-12-07 14:26:12,704 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:26:12,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:26:12,757 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:26:12,757 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [96634674] [2019-12-07 14:26:12,757 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:26:12,757 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 14:26:12,757 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [535016951] [2019-12-07 14:26:12,757 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 14:26:12,758 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:26:12,758 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 14:26:12,758 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 14:26:12,758 INFO L87 Difference]: Start difference. First operand 198233 states and 814440 transitions. Second operand 4 states. [2019-12-07 14:26:14,340 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:26:14,341 INFO L93 Difference]: Finished difference Result 247181 states and 1005908 transitions. [2019-12-07 14:26:14,341 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 14:26:14,342 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 14:26:14,342 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:26:14,977 INFO L225 Difference]: With dead ends: 247181 [2019-12-07 14:26:14,977 INFO L226 Difference]: Without dead ends: 247181 [2019-12-07 14:26:14,977 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:26:20,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 247181 states. [2019-12-07 14:26:23,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 247181 to 209765. [2019-12-07 14:26:23,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 209765 states. [2019-12-07 14:26:24,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 209765 states to 209765 states and 862010 transitions. [2019-12-07 14:26:24,414 INFO L78 Accepts]: Start accepts. Automaton has 209765 states and 862010 transitions. Word has length 13 [2019-12-07 14:26:24,415 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:26:24,415 INFO L462 AbstractCegarLoop]: Abstraction has 209765 states and 862010 transitions. [2019-12-07 14:26:24,415 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 14:26:24,415 INFO L276 IsEmpty]: Start isEmpty. Operand 209765 states and 862010 transitions. [2019-12-07 14:26:24,437 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 14:26:24,438 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:26:24,438 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:26:24,438 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:26:24,438 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:26:24,438 INFO L82 PathProgramCache]: Analyzing trace with hash -1204820739, now seen corresponding path program 1 times [2019-12-07 14:26:24,438 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:26:24,439 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1448270876] [2019-12-07 14:26:24,439 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:26:24,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:26:24,483 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:26:24,483 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1448270876] [2019-12-07 14:26:24,484 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:26:24,484 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 14:26:24,484 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1116560411] [2019-12-07 14:26:24,484 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 14:26:24,484 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:26:24,484 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 14:26:24,484 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:26:24,484 INFO L87 Difference]: Start difference. First operand 209765 states and 862010 transitions. Second operand 5 states. [2019-12-07 14:26:26,229 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:26:26,229 INFO L93 Difference]: Finished difference Result 305325 states and 1226868 transitions. [2019-12-07 14:26:26,230 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 14:26:26,230 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 14:26:26,230 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:26:27,019 INFO L225 Difference]: With dead ends: 305325 [2019-12-07 14:26:27,019 INFO L226 Difference]: Without dead ends: 305178 [2019-12-07 14:26:27,020 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 14:26:36,015 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 305178 states. [2019-12-07 14:26:39,718 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 305178 to 231185. [2019-12-07 14:26:39,719 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 231185 states. [2019-12-07 14:26:40,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 231185 states to 231185 states and 945346 transitions. [2019-12-07 14:26:40,379 INFO L78 Accepts]: Start accepts. Automaton has 231185 states and 945346 transitions. Word has length 19 [2019-12-07 14:26:40,379 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:26:40,379 INFO L462 AbstractCegarLoop]: Abstraction has 231185 states and 945346 transitions. [2019-12-07 14:26:40,379 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 14:26:40,379 INFO L276 IsEmpty]: Start isEmpty. Operand 231185 states and 945346 transitions. [2019-12-07 14:26:40,391 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 14:26:40,391 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:26:40,391 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:26:40,391 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:26:40,392 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:26:40,392 INFO L82 PathProgramCache]: Analyzing trace with hash 737886097, now seen corresponding path program 1 times [2019-12-07 14:26:40,392 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:26:40,392 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1236997335] [2019-12-07 14:26:40,392 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:26:40,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:26:40,432 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:26:40,433 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1236997335] [2019-12-07 14:26:40,433 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:26:40,433 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 14:26:40,433 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1245663539] [2019-12-07 14:26:40,433 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 14:26:40,434 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:26:40,434 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 14:26:40,434 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:26:40,434 INFO L87 Difference]: Start difference. First operand 231185 states and 945346 transitions. Second operand 5 states. [2019-12-07 14:26:42,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:26:42,574 INFO L93 Difference]: Finished difference Result 329703 states and 1323212 transitions. [2019-12-07 14:26:42,575 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 14:26:42,575 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 14:26:42,576 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:26:43,412 INFO L225 Difference]: With dead ends: 329703 [2019-12-07 14:26:43,412 INFO L226 Difference]: Without dead ends: 329640 [2019-12-07 14:26:43,413 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 14:26:52,751 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 329640 states. [2019-12-07 14:26:56,323 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 329640 to 234401. [2019-12-07 14:26:56,324 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 234401 states. [2019-12-07 14:26:57,337 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 234401 states to 234401 states and 957976 transitions. [2019-12-07 14:26:57,337 INFO L78 Accepts]: Start accepts. Automaton has 234401 states and 957976 transitions. Word has length 19 [2019-12-07 14:26:57,337 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:26:57,337 INFO L462 AbstractCegarLoop]: Abstraction has 234401 states and 957976 transitions. [2019-12-07 14:26:57,337 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 14:26:57,337 INFO L276 IsEmpty]: Start isEmpty. Operand 234401 states and 957976 transitions. [2019-12-07 14:26:57,352 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 14:26:57,352 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:26:57,352 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:26:57,352 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:26:57,352 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:26:57,353 INFO L82 PathProgramCache]: Analyzing trace with hash 346547774, now seen corresponding path program 1 times [2019-12-07 14:26:57,353 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:26:57,353 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1844878654] [2019-12-07 14:26:57,353 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:26:57,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:26:57,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:26:57,410 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1844878654] [2019-12-07 14:26:57,410 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:26:57,410 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 14:26:57,411 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1289797822] [2019-12-07 14:26:57,411 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 14:26:57,411 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:26:57,411 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 14:26:57,411 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:26:57,411 INFO L87 Difference]: Start difference. First operand 234401 states and 957976 transitions. Second operand 5 states. [2019-12-07 14:26:59,755 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:26:59,755 INFO L93 Difference]: Finished difference Result 340487 states and 1368160 transitions. [2019-12-07 14:26:59,756 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 14:26:59,756 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 14:26:59,756 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:27:00,607 INFO L225 Difference]: With dead ends: 340487 [2019-12-07 14:27:00,608 INFO L226 Difference]: Without dead ends: 340424 [2019-12-07 14:27:00,608 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 14:27:06,971 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 340424 states. [2019-12-07 14:27:10,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 340424 to 253200. [2019-12-07 14:27:10,903 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 253200 states. [2019-12-07 14:27:12,027 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 253200 states to 253200 states and 1033563 transitions. [2019-12-07 14:27:12,027 INFO L78 Accepts]: Start accepts. Automaton has 253200 states and 1033563 transitions. Word has length 19 [2019-12-07 14:27:12,028 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:27:12,028 INFO L462 AbstractCegarLoop]: Abstraction has 253200 states and 1033563 transitions. [2019-12-07 14:27:12,028 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 14:27:12,028 INFO L276 IsEmpty]: Start isEmpty. Operand 253200 states and 1033563 transitions. [2019-12-07 14:27:12,093 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 14:27:12,093 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:27:12,093 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:27:12,093 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:27:12,093 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:27:12,093 INFO L82 PathProgramCache]: Analyzing trace with hash 224247286, now seen corresponding path program 1 times [2019-12-07 14:27:12,094 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:27:12,094 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [711182236] [2019-12-07 14:27:12,094 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:27:12,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:27:12,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:27:12,148 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [711182236] [2019-12-07 14:27:12,148 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:27:12,148 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 14:27:12,148 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1885160621] [2019-12-07 14:27:12,148 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 14:27:12,149 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:27:12,149 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 14:27:12,149 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 14:27:12,149 INFO L87 Difference]: Start difference. First operand 253200 states and 1033563 transitions. Second operand 6 states. [2019-12-07 14:27:14,155 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:27:14,155 INFO L93 Difference]: Finished difference Result 302263 states and 1219199 transitions. [2019-12-07 14:27:14,156 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 14:27:14,156 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 25 [2019-12-07 14:27:14,156 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:27:15,535 INFO L225 Difference]: With dead ends: 302263 [2019-12-07 14:27:15,535 INFO L226 Difference]: Without dead ends: 302116 [2019-12-07 14:27:15,536 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 40 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=81, Invalid=191, Unknown=0, NotChecked=0, Total=272 [2019-12-07 14:27:24,518 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 302116 states. [2019-12-07 14:27:27,963 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 302116 to 208616. [2019-12-07 14:27:27,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 208616 states. [2019-12-07 14:27:28,581 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 208616 states to 208616 states and 855419 transitions. [2019-12-07 14:27:28,581 INFO L78 Accepts]: Start accepts. Automaton has 208616 states and 855419 transitions. Word has length 25 [2019-12-07 14:27:28,582 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:27:28,582 INFO L462 AbstractCegarLoop]: Abstraction has 208616 states and 855419 transitions. [2019-12-07 14:27:28,582 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 14:27:28,582 INFO L276 IsEmpty]: Start isEmpty. Operand 208616 states and 855419 transitions. [2019-12-07 14:27:28,665 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 14:27:28,665 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:27:28,665 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:27:28,665 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:27:28,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:27:28,666 INFO L82 PathProgramCache]: Analyzing trace with hash 289171568, now seen corresponding path program 1 times [2019-12-07 14:27:28,666 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:27:28,666 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1533142816] [2019-12-07 14:27:28,666 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:27:28,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:27:28,694 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:27:28,695 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1533142816] [2019-12-07 14:27:28,695 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:27:28,695 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 14:27:28,695 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1591883836] [2019-12-07 14:27:28,696 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:27:28,696 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:27:28,696 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:27:28,696 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:27:28,696 INFO L87 Difference]: Start difference. First operand 208616 states and 855419 transitions. Second operand 3 states. [2019-12-07 14:27:30,304 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:27:30,304 INFO L93 Difference]: Finished difference Result 258190 states and 1058599 transitions. [2019-12-07 14:27:30,305 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:27:30,305 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-12-07 14:27:30,306 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:27:30,974 INFO L225 Difference]: With dead ends: 258190 [2019-12-07 14:27:30,974 INFO L226 Difference]: Without dead ends: 258190 [2019-12-07 14:27:30,974 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:27:36,304 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 258190 states. [2019-12-07 14:27:39,875 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 258190 to 238253. [2019-12-07 14:27:39,876 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 238253 states. [2019-12-07 14:27:40,584 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 238253 states to 238253 states and 979725 transitions. [2019-12-07 14:27:40,584 INFO L78 Accepts]: Start accepts. Automaton has 238253 states and 979725 transitions. Word has length 27 [2019-12-07 14:27:40,584 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:27:40,584 INFO L462 AbstractCegarLoop]: Abstraction has 238253 states and 979725 transitions. [2019-12-07 14:27:40,584 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:27:40,584 INFO L276 IsEmpty]: Start isEmpty. Operand 238253 states and 979725 transitions. [2019-12-07 14:27:40,661 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 14:27:40,661 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:27:40,661 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:27:40,662 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:27:40,662 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:27:40,662 INFO L82 PathProgramCache]: Analyzing trace with hash 289290298, now seen corresponding path program 1 times [2019-12-07 14:27:40,662 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:27:40,662 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1016842322] [2019-12-07 14:27:40,662 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:27:40,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:27:40,701 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:27:40,701 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1016842322] [2019-12-07 14:27:40,702 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:27:40,702 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 14:27:40,702 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [256281678] [2019-12-07 14:27:40,702 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 14:27:40,702 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:27:40,702 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 14:27:40,702 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 14:27:40,702 INFO L87 Difference]: Start difference. First operand 238253 states and 979725 transitions. Second operand 4 states. [2019-12-07 14:27:40,876 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:27:40,877 INFO L93 Difference]: Finished difference Result 52725 states and 171836 transitions. [2019-12-07 14:27:40,877 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 14:27:40,877 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 27 [2019-12-07 14:27:40,877 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:27:40,947 INFO L225 Difference]: With dead ends: 52725 [2019-12-07 14:27:40,947 INFO L226 Difference]: Without dead ends: 47538 [2019-12-07 14:27:40,948 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:27:41,553 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47538 states. [2019-12-07 14:27:41,996 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47538 to 47538. [2019-12-07 14:27:41,997 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47538 states. [2019-12-07 14:27:42,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47538 states to 47538 states and 152772 transitions. [2019-12-07 14:27:42,079 INFO L78 Accepts]: Start accepts. Automaton has 47538 states and 152772 transitions. Word has length 27 [2019-12-07 14:27:42,079 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:27:42,079 INFO L462 AbstractCegarLoop]: Abstraction has 47538 states and 152772 transitions. [2019-12-07 14:27:42,079 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 14:27:42,079 INFO L276 IsEmpty]: Start isEmpty. Operand 47538 states and 152772 transitions. [2019-12-07 14:27:42,098 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2019-12-07 14:27:42,098 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:27:42,099 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:27:42,099 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:27:42,099 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:27:42,099 INFO L82 PathProgramCache]: Analyzing trace with hash 1974769462, now seen corresponding path program 1 times [2019-12-07 14:27:42,099 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:27:42,099 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [300967954] [2019-12-07 14:27:42,099 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:27:42,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:27:42,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:27:42,150 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [300967954] [2019-12-07 14:27:42,150 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:27:42,151 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 14:27:42,151 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1251273012] [2019-12-07 14:27:42,151 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 14:27:42,151 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:27:42,151 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 14:27:42,151 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:27:42,151 INFO L87 Difference]: Start difference. First operand 47538 states and 152772 transitions. Second operand 5 states. [2019-12-07 14:27:42,208 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:27:42,208 INFO L93 Difference]: Finished difference Result 9783 states and 26538 transitions. [2019-12-07 14:27:42,208 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 14:27:42,208 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 39 [2019-12-07 14:27:42,208 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:27:42,215 INFO L225 Difference]: With dead ends: 9783 [2019-12-07 14:27:42,216 INFO L226 Difference]: Without dead ends: 8676 [2019-12-07 14:27:42,216 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-12-07 14:27:42,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8676 states. [2019-12-07 14:27:42,302 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8676 to 8536. [2019-12-07 14:27:42,302 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8536 states. [2019-12-07 14:27:42,312 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8536 states to 8536 states and 22902 transitions. [2019-12-07 14:27:42,312 INFO L78 Accepts]: Start accepts. Automaton has 8536 states and 22902 transitions. Word has length 39 [2019-12-07 14:27:42,312 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:27:42,312 INFO L462 AbstractCegarLoop]: Abstraction has 8536 states and 22902 transitions. [2019-12-07 14:27:42,313 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 14:27:42,313 INFO L276 IsEmpty]: Start isEmpty. Operand 8536 states and 22902 transitions. [2019-12-07 14:27:42,318 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-12-07 14:27:42,318 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:27:42,318 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:27:42,318 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:27:42,319 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:27:42,319 INFO L82 PathProgramCache]: Analyzing trace with hash -1447839164, now seen corresponding path program 1 times [2019-12-07 14:27:42,319 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:27:42,319 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [455128378] [2019-12-07 14:27:42,319 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:27:42,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:27:42,382 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:27:42,383 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [455128378] [2019-12-07 14:27:42,383 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:27:42,383 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 14:27:42,383 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [563834851] [2019-12-07 14:27:42,383 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 14:27:42,383 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:27:42,383 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 14:27:42,384 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2019-12-07 14:27:42,384 INFO L87 Difference]: Start difference. First operand 8536 states and 22902 transitions. Second operand 6 states. [2019-12-07 14:27:42,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:27:42,441 INFO L93 Difference]: Finished difference Result 5821 states and 16635 transitions. [2019-12-07 14:27:42,441 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 14:27:42,441 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 51 [2019-12-07 14:27:42,442 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:27:42,448 INFO L225 Difference]: With dead ends: 5821 [2019-12-07 14:27:42,448 INFO L226 Difference]: Without dead ends: 5738 [2019-12-07 14:27:42,449 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2019-12-07 14:27:42,478 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5738 states. [2019-12-07 14:27:42,518 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5738 to 5325. [2019-12-07 14:27:42,518 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5325 states. [2019-12-07 14:27:42,525 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5325 states to 5325 states and 15353 transitions. [2019-12-07 14:27:42,525 INFO L78 Accepts]: Start accepts. Automaton has 5325 states and 15353 transitions. Word has length 51 [2019-12-07 14:27:42,525 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:27:42,525 INFO L462 AbstractCegarLoop]: Abstraction has 5325 states and 15353 transitions. [2019-12-07 14:27:42,525 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 14:27:42,525 INFO L276 IsEmpty]: Start isEmpty. Operand 5325 states and 15353 transitions. [2019-12-07 14:27:42,529 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2019-12-07 14:27:42,529 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:27:42,529 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:27:42,529 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:27:42,529 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:27:42,529 INFO L82 PathProgramCache]: Analyzing trace with hash -1613083422, now seen corresponding path program 1 times [2019-12-07 14:27:42,530 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:27:42,530 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1832746077] [2019-12-07 14:27:42,530 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:27:42,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:27:42,591 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:27:42,591 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1832746077] [2019-12-07 14:27:42,591 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:27:42,591 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 14:27:42,592 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [49756384] [2019-12-07 14:27:42,592 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 14:27:42,592 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:27:42,592 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 14:27:42,592 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 14:27:42,592 INFO L87 Difference]: Start difference. First operand 5325 states and 15353 transitions. Second operand 5 states. [2019-12-07 14:27:42,776 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:27:42,777 INFO L93 Difference]: Finished difference Result 7818 states and 22326 transitions. [2019-12-07 14:27:42,777 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 14:27:42,777 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 64 [2019-12-07 14:27:42,777 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:27:42,784 INFO L225 Difference]: With dead ends: 7818 [2019-12-07 14:27:42,784 INFO L226 Difference]: Without dead ends: 7818 [2019-12-07 14:27:42,784 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 14:27:42,810 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7818 states. [2019-12-07 14:27:42,869 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7818 to 6919. [2019-12-07 14:27:42,869 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6919 states. [2019-12-07 14:27:42,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6919 states to 6919 states and 19847 transitions. [2019-12-07 14:27:42,879 INFO L78 Accepts]: Start accepts. Automaton has 6919 states and 19847 transitions. Word has length 64 [2019-12-07 14:27:42,879 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:27:42,879 INFO L462 AbstractCegarLoop]: Abstraction has 6919 states and 19847 transitions. [2019-12-07 14:27:42,879 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 14:27:42,879 INFO L276 IsEmpty]: Start isEmpty. Operand 6919 states and 19847 transitions. [2019-12-07 14:27:42,885 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2019-12-07 14:27:42,885 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:27:42,885 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:27:42,885 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:27:42,885 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:27:42,886 INFO L82 PathProgramCache]: Analyzing trace with hash -516051436, now seen corresponding path program 2 times [2019-12-07 14:27:42,886 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:27:42,886 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [737889136] [2019-12-07 14:27:42,886 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:27:42,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:27:42,945 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:27:42,945 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [737889136] [2019-12-07 14:27:42,945 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:27:42,945 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 14:27:42,946 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1107872920] [2019-12-07 14:27:42,946 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 14:27:42,946 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:27:42,946 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 14:27:42,946 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 14:27:42,947 INFO L87 Difference]: Start difference. First operand 6919 states and 19847 transitions. Second operand 6 states. [2019-12-07 14:27:43,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:27:43,227 INFO L93 Difference]: Finished difference Result 11631 states and 33222 transitions. [2019-12-07 14:27:43,227 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 14:27:43,228 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 64 [2019-12-07 14:27:43,228 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:27:43,237 INFO L225 Difference]: With dead ends: 11631 [2019-12-07 14:27:43,237 INFO L226 Difference]: Without dead ends: 11631 [2019-12-07 14:27:43,238 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2019-12-07 14:27:43,268 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11631 states. [2019-12-07 14:27:43,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11631 to 7933. [2019-12-07 14:27:43,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7933 states. [2019-12-07 14:27:43,356 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7933 states to 7933 states and 22821 transitions. [2019-12-07 14:27:43,357 INFO L78 Accepts]: Start accepts. Automaton has 7933 states and 22821 transitions. Word has length 64 [2019-12-07 14:27:43,357 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:27:43,357 INFO L462 AbstractCegarLoop]: Abstraction has 7933 states and 22821 transitions. [2019-12-07 14:27:43,357 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 14:27:43,357 INFO L276 IsEmpty]: Start isEmpty. Operand 7933 states and 22821 transitions. [2019-12-07 14:27:43,363 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2019-12-07 14:27:43,363 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:27:43,364 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:27:43,364 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:27:43,364 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:27:43,364 INFO L82 PathProgramCache]: Analyzing trace with hash 1224218282, now seen corresponding path program 3 times [2019-12-07 14:27:43,364 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:27:43,364 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [914086636] [2019-12-07 14:27:43,364 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:27:43,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:27:43,430 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:27:43,430 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [914086636] [2019-12-07 14:27:43,430 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:27:43,430 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 14:27:43,430 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1712358970] [2019-12-07 14:27:43,431 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:27:43,431 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:27:43,431 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:27:43,431 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:27:43,431 INFO L87 Difference]: Start difference. First operand 7933 states and 22821 transitions. Second operand 3 states. [2019-12-07 14:27:43,470 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:27:43,470 INFO L93 Difference]: Finished difference Result 7933 states and 22820 transitions. [2019-12-07 14:27:43,471 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:27:43,471 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 64 [2019-12-07 14:27:43,471 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:27:43,477 INFO L225 Difference]: With dead ends: 7933 [2019-12-07 14:27:43,478 INFO L226 Difference]: Without dead ends: 7933 [2019-12-07 14:27:43,478 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:27:43,501 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7933 states. [2019-12-07 14:27:43,557 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7933 to 6625. [2019-12-07 14:27:43,557 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6625 states. [2019-12-07 14:27:43,566 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6625 states to 6625 states and 19197 transitions. [2019-12-07 14:27:43,566 INFO L78 Accepts]: Start accepts. Automaton has 6625 states and 19197 transitions. Word has length 64 [2019-12-07 14:27:43,566 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:27:43,566 INFO L462 AbstractCegarLoop]: Abstraction has 6625 states and 19197 transitions. [2019-12-07 14:27:43,566 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:27:43,566 INFO L276 IsEmpty]: Start isEmpty. Operand 6625 states and 19197 transitions. [2019-12-07 14:27:43,571 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 14:27:43,571 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:27:43,571 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:27:43,571 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:27:43,571 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:27:43,572 INFO L82 PathProgramCache]: Analyzing trace with hash -927307397, now seen corresponding path program 1 times [2019-12-07 14:27:43,572 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:27:43,572 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [114584000] [2019-12-07 14:27:43,572 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:27:43,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:27:43,660 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:27:43,660 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [114584000] [2019-12-07 14:27:43,660 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:27:43,661 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 14:27:43,661 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1426108733] [2019-12-07 14:27:43,661 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 14:27:43,661 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:27:43,661 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 14:27:43,662 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 14:27:43,662 INFO L87 Difference]: Start difference. First operand 6625 states and 19197 transitions. Second operand 7 states. [2019-12-07 14:27:43,769 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:27:43,769 INFO L93 Difference]: Finished difference Result 12748 states and 37271 transitions. [2019-12-07 14:27:43,769 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 14:27:43,769 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 65 [2019-12-07 14:27:43,769 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:27:43,775 INFO L225 Difference]: With dead ends: 12748 [2019-12-07 14:27:43,775 INFO L226 Difference]: Without dead ends: 6347 [2019-12-07 14:27:43,776 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=40, Invalid=70, Unknown=0, NotChecked=0, Total=110 [2019-12-07 14:27:43,796 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6347 states. [2019-12-07 14:27:43,835 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6347 to 5074. [2019-12-07 14:27:43,835 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5074 states. [2019-12-07 14:27:43,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5074 states to 5074 states and 14661 transitions. [2019-12-07 14:27:43,841 INFO L78 Accepts]: Start accepts. Automaton has 5074 states and 14661 transitions. Word has length 65 [2019-12-07 14:27:43,841 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:27:43,841 INFO L462 AbstractCegarLoop]: Abstraction has 5074 states and 14661 transitions. [2019-12-07 14:27:43,841 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 14:27:43,842 INFO L276 IsEmpty]: Start isEmpty. Operand 5074 states and 14661 transitions. [2019-12-07 14:27:43,845 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 14:27:43,845 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:27:43,845 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:27:43,845 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:27:43,845 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:27:43,845 INFO L82 PathProgramCache]: Analyzing trace with hash 1252575037, now seen corresponding path program 2 times [2019-12-07 14:27:43,845 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:27:43,846 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1022519357] [2019-12-07 14:27:43,846 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:27:43,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:27:43,876 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:27:43,876 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1022519357] [2019-12-07 14:27:43,876 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:27:43,876 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 14:27:43,876 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2046796371] [2019-12-07 14:27:43,877 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:27:43,877 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:27:43,877 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:27:43,877 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:27:43,877 INFO L87 Difference]: Start difference. First operand 5074 states and 14661 transitions. Second operand 3 states. [2019-12-07 14:27:43,894 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:27:43,894 INFO L93 Difference]: Finished difference Result 4754 states and 13453 transitions. [2019-12-07 14:27:43,894 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:27:43,894 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 65 [2019-12-07 14:27:43,894 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:27:43,898 INFO L225 Difference]: With dead ends: 4754 [2019-12-07 14:27:43,899 INFO L226 Difference]: Without dead ends: 4754 [2019-12-07 14:27:43,899 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:27:43,916 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4754 states. [2019-12-07 14:27:43,951 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4754 to 4556. [2019-12-07 14:27:43,951 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4556 states. [2019-12-07 14:27:43,956 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4556 states to 4556 states and 12892 transitions. [2019-12-07 14:27:43,956 INFO L78 Accepts]: Start accepts. Automaton has 4556 states and 12892 transitions. Word has length 65 [2019-12-07 14:27:43,956 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:27:43,957 INFO L462 AbstractCegarLoop]: Abstraction has 4556 states and 12892 transitions. [2019-12-07 14:27:43,957 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:27:43,957 INFO L276 IsEmpty]: Start isEmpty. Operand 4556 states and 12892 transitions. [2019-12-07 14:27:43,960 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 14:27:43,960 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:27:43,960 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:27:43,960 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:27:43,960 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:27:43,960 INFO L82 PathProgramCache]: Analyzing trace with hash -1713906727, now seen corresponding path program 1 times [2019-12-07 14:27:43,960 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:27:43,961 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1301533443] [2019-12-07 14:27:43,961 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:27:43,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:27:44,611 WARN L192 SmtUtils]: Spent 621.00 ms on a formula simplification that was a NOOP. DAG size: 12 [2019-12-07 14:27:44,633 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:27:44,634 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1301533443] [2019-12-07 14:27:44,634 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:27:44,634 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 14:27:44,635 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1814527885] [2019-12-07 14:27:44,635 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 14:27:44,635 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:27:44,635 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 14:27:44,635 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 14:27:44,635 INFO L87 Difference]: Start difference. First operand 4556 states and 12892 transitions. Second operand 6 states. [2019-12-07 14:27:44,937 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:27:44,937 INFO L93 Difference]: Finished difference Result 7485 states and 20863 transitions. [2019-12-07 14:27:44,938 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 14:27:44,938 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 66 [2019-12-07 14:27:44,938 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:27:44,944 INFO L225 Difference]: With dead ends: 7485 [2019-12-07 14:27:44,944 INFO L226 Difference]: Without dead ends: 7485 [2019-12-07 14:27:44,944 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2019-12-07 14:27:44,967 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7485 states. [2019-12-07 14:27:45,011 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7485 to 4568. [2019-12-07 14:27:45,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4568 states. [2019-12-07 14:27:45,016 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4568 states to 4568 states and 12926 transitions. [2019-12-07 14:27:45,016 INFO L78 Accepts]: Start accepts. Automaton has 4568 states and 12926 transitions. Word has length 66 [2019-12-07 14:27:45,017 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:27:45,017 INFO L462 AbstractCegarLoop]: Abstraction has 4568 states and 12926 transitions. [2019-12-07 14:27:45,017 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 14:27:45,017 INFO L276 IsEmpty]: Start isEmpty. Operand 4568 states and 12926 transitions. [2019-12-07 14:27:45,019 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 14:27:45,020 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:27:45,020 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:27:45,020 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:27:45,020 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:27:45,020 INFO L82 PathProgramCache]: Analyzing trace with hash -1842201451, now seen corresponding path program 2 times [2019-12-07 14:27:45,020 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:27:45,020 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1152994890] [2019-12-07 14:27:45,020 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:27:45,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:27:45,194 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:27:45,195 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1152994890] [2019-12-07 14:27:45,195 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:27:45,195 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 14:27:45,195 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1027086789] [2019-12-07 14:27:45,195 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 14:27:45,195 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:27:45,195 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 14:27:45,195 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=148, Unknown=0, NotChecked=0, Total=182 [2019-12-07 14:27:45,196 INFO L87 Difference]: Start difference. First operand 4568 states and 12926 transitions. Second operand 14 states. [2019-12-07 14:27:46,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:27:46,483 INFO L93 Difference]: Finished difference Result 9793 states and 28012 transitions. [2019-12-07 14:27:46,483 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2019-12-07 14:27:46,483 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 66 [2019-12-07 14:27:46,484 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:27:46,493 INFO L225 Difference]: With dead ends: 9793 [2019-12-07 14:27:46,493 INFO L226 Difference]: Without dead ends: 9280 [2019-12-07 14:27:46,493 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 103 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=124, Invalid=526, Unknown=0, NotChecked=0, Total=650 [2019-12-07 14:27:46,518 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9280 states. [2019-12-07 14:27:46,570 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9280 to 5588. [2019-12-07 14:27:46,570 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5588 states. [2019-12-07 14:27:46,577 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5588 states to 5588 states and 15704 transitions. [2019-12-07 14:27:46,577 INFO L78 Accepts]: Start accepts. Automaton has 5588 states and 15704 transitions. Word has length 66 [2019-12-07 14:27:46,578 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:27:46,578 INFO L462 AbstractCegarLoop]: Abstraction has 5588 states and 15704 transitions. [2019-12-07 14:27:46,578 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 14:27:46,578 INFO L276 IsEmpty]: Start isEmpty. Operand 5588 states and 15704 transitions. [2019-12-07 14:27:46,582 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 14:27:46,582 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:27:46,582 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:27:46,582 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:27:46,582 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:27:46,582 INFO L82 PathProgramCache]: Analyzing trace with hash -1034304369, now seen corresponding path program 3 times [2019-12-07 14:27:46,582 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:27:46,582 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [966684177] [2019-12-07 14:27:46,583 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:27:46,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:27:46,631 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:27:46,631 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [966684177] [2019-12-07 14:27:46,631 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:27:46,631 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 14:27:46,631 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1113608450] [2019-12-07 14:27:46,631 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 14:27:46,632 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:27:46,632 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 14:27:46,632 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:27:46,632 INFO L87 Difference]: Start difference. First operand 5588 states and 15704 transitions. Second operand 3 states. [2019-12-07 14:27:46,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:27:46,649 INFO L93 Difference]: Finished difference Result 5153 states and 14186 transitions. [2019-12-07 14:27:46,649 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 14:27:46,650 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 66 [2019-12-07 14:27:46,650 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:27:46,653 INFO L225 Difference]: With dead ends: 5153 [2019-12-07 14:27:46,654 INFO L226 Difference]: Without dead ends: 5153 [2019-12-07 14:27:46,654 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 14:27:46,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5153 states. [2019-12-07 14:27:46,707 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5153 to 4865. [2019-12-07 14:27:46,707 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4865 states. [2019-12-07 14:27:46,712 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4865 states to 4865 states and 13398 transitions. [2019-12-07 14:27:46,713 INFO L78 Accepts]: Start accepts. Automaton has 4865 states and 13398 transitions. Word has length 66 [2019-12-07 14:27:46,713 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:27:46,713 INFO L462 AbstractCegarLoop]: Abstraction has 4865 states and 13398 transitions. [2019-12-07 14:27:46,713 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 14:27:46,713 INFO L276 IsEmpty]: Start isEmpty. Operand 4865 states and 13398 transitions. [2019-12-07 14:27:46,716 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 14:27:46,716 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:27:46,716 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:27:46,716 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:27:46,716 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:27:46,716 INFO L82 PathProgramCache]: Analyzing trace with hash -732996136, now seen corresponding path program 1 times [2019-12-07 14:27:46,716 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:27:46,717 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1074982509] [2019-12-07 14:27:46,717 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:27:46,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:27:46,840 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:27:46,840 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1074982509] [2019-12-07 14:27:46,840 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:27:46,841 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-07 14:27:46,841 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [160344225] [2019-12-07 14:27:46,841 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2019-12-07 14:27:46,841 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:27:46,841 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2019-12-07 14:27:46,841 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=105, Unknown=0, NotChecked=0, Total=132 [2019-12-07 14:27:46,841 INFO L87 Difference]: Start difference. First operand 4865 states and 13398 transitions. Second operand 12 states. [2019-12-07 14:27:47,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:27:47,106 INFO L93 Difference]: Finished difference Result 8197 states and 22588 transitions. [2019-12-07 14:27:47,106 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 14:27:47,106 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 67 [2019-12-07 14:27:47,106 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:27:47,112 INFO L225 Difference]: With dead ends: 8197 [2019-12-07 14:27:47,112 INFO L226 Difference]: Without dead ends: 7684 [2019-12-07 14:27:47,113 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 91 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=113, Invalid=439, Unknown=0, NotChecked=0, Total=552 [2019-12-07 14:27:47,133 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7684 states. [2019-12-07 14:27:47,174 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7684 to 4886. [2019-12-07 14:27:47,174 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4886 states. [2019-12-07 14:27:47,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4886 states to 4886 states and 13450 transitions. [2019-12-07 14:27:47,179 INFO L78 Accepts]: Start accepts. Automaton has 4886 states and 13450 transitions. Word has length 67 [2019-12-07 14:27:47,180 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:27:47,180 INFO L462 AbstractCegarLoop]: Abstraction has 4886 states and 13450 transitions. [2019-12-07 14:27:47,180 INFO L463 AbstractCegarLoop]: Interpolant automaton has 12 states. [2019-12-07 14:27:47,180 INFO L276 IsEmpty]: Start isEmpty. Operand 4886 states and 13450 transitions. [2019-12-07 14:27:47,182 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 14:27:47,182 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:27:47,183 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:27:47,183 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:27:47,183 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:27:47,183 INFO L82 PathProgramCache]: Analyzing trace with hash 894946434, now seen corresponding path program 2 times [2019-12-07 14:27:47,183 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:27:47,183 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2104660845] [2019-12-07 14:27:47,183 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:27:47,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:27:47,362 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:27:47,363 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2104660845] [2019-12-07 14:27:47,363 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:27:47,363 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 14:27:47,363 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [827857217] [2019-12-07 14:27:47,363 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 14:27:47,363 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:27:47,363 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 14:27:47,363 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=128, Unknown=0, NotChecked=0, Total=156 [2019-12-07 14:27:47,364 INFO L87 Difference]: Start difference. First operand 4886 states and 13450 transitions. Second operand 13 states. [2019-12-07 14:27:47,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:27:47,734 INFO L93 Difference]: Finished difference Result 9200 states and 25450 transitions. [2019-12-07 14:27:47,734 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2019-12-07 14:27:47,734 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 67 [2019-12-07 14:27:47,734 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:27:47,741 INFO L225 Difference]: With dead ends: 9200 [2019-12-07 14:27:47,741 INFO L226 Difference]: Without dead ends: 8519 [2019-12-07 14:27:47,742 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 111 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=137, Invalid=565, Unknown=0, NotChecked=0, Total=702 [2019-12-07 14:27:47,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8519 states. [2019-12-07 14:27:47,814 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8519 to 5502. [2019-12-07 14:27:47,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5502 states. [2019-12-07 14:27:47,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5502 states to 5502 states and 15200 transitions. [2019-12-07 14:27:47,821 INFO L78 Accepts]: Start accepts. Automaton has 5502 states and 15200 transitions. Word has length 67 [2019-12-07 14:27:47,821 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:27:47,821 INFO L462 AbstractCegarLoop]: Abstraction has 5502 states and 15200 transitions. [2019-12-07 14:27:47,821 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 14:27:47,821 INFO L276 IsEmpty]: Start isEmpty. Operand 5502 states and 15200 transitions. [2019-12-07 14:27:47,825 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 14:27:47,825 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:27:47,825 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:27:47,825 INFO L410 AbstractCegarLoop]: === Iteration 23 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:27:47,825 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:27:47,825 INFO L82 PathProgramCache]: Analyzing trace with hash 1053599810, now seen corresponding path program 3 times [2019-12-07 14:27:47,825 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:27:47,826 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [977546182] [2019-12-07 14:27:47,826 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:27:47,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:27:48,049 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:27:48,050 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [977546182] [2019-12-07 14:27:48,050 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:27:48,050 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 14:27:48,050 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1087660866] [2019-12-07 14:27:48,050 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 14:27:48,051 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:27:48,051 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 14:27:48,051 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=174, Unknown=0, NotChecked=0, Total=210 [2019-12-07 14:27:48,051 INFO L87 Difference]: Start difference. First operand 5502 states and 15200 transitions. Second operand 15 states. [2019-12-07 14:27:48,772 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:27:48,772 INFO L93 Difference]: Finished difference Result 12051 states and 33512 transitions. [2019-12-07 14:27:48,772 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2019-12-07 14:27:48,772 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 67 [2019-12-07 14:27:48,772 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:27:48,781 INFO L225 Difference]: With dead ends: 12051 [2019-12-07 14:27:48,781 INFO L226 Difference]: Without dead ends: 11538 [2019-12-07 14:27:48,782 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 262 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=263, Invalid=1069, Unknown=0, NotChecked=0, Total=1332 [2019-12-07 14:27:48,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11538 states. [2019-12-07 14:27:48,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11538 to 6315. [2019-12-07 14:27:48,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6315 states. [2019-12-07 14:27:48,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6315 states to 6315 states and 17536 transitions. [2019-12-07 14:27:48,881 INFO L78 Accepts]: Start accepts. Automaton has 6315 states and 17536 transitions. Word has length 67 [2019-12-07 14:27:48,881 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:27:48,881 INFO L462 AbstractCegarLoop]: Abstraction has 6315 states and 17536 transitions. [2019-12-07 14:27:48,881 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 14:27:48,881 INFO L276 IsEmpty]: Start isEmpty. Operand 6315 states and 17536 transitions. [2019-12-07 14:27:48,886 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 14:27:48,886 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:27:48,886 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:27:48,886 INFO L410 AbstractCegarLoop]: === Iteration 24 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:27:48,886 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:27:48,886 INFO L82 PathProgramCache]: Analyzing trace with hash -691900798, now seen corresponding path program 4 times [2019-12-07 14:27:48,887 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:27:48,887 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1342221736] [2019-12-07 14:27:48,887 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:27:48,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:27:49,103 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:27:49,103 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1342221736] [2019-12-07 14:27:49,103 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:27:49,103 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2019-12-07 14:27:49,103 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1036977941] [2019-12-07 14:27:49,104 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 14:27:49,104 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:27:49,104 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 14:27:49,104 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=201, Unknown=0, NotChecked=0, Total=240 [2019-12-07 14:27:49,104 INFO L87 Difference]: Start difference. First operand 6315 states and 17536 transitions. Second operand 16 states. [2019-12-07 14:27:49,897 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:27:49,897 INFO L93 Difference]: Finished difference Result 11025 states and 30577 transitions. [2019-12-07 14:27:49,897 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2019-12-07 14:27:49,897 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 67 [2019-12-07 14:27:49,898 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:27:49,908 INFO L225 Difference]: With dead ends: 11025 [2019-12-07 14:27:49,908 INFO L226 Difference]: Without dead ends: 10878 [2019-12-07 14:27:49,909 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 299 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=285, Invalid=1197, Unknown=0, NotChecked=0, Total=1482 [2019-12-07 14:27:49,936 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10878 states. [2019-12-07 14:27:49,995 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10878 to 5887. [2019-12-07 14:27:49,995 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5887 states. [2019-12-07 14:27:50,002 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5887 states to 5887 states and 16292 transitions. [2019-12-07 14:27:50,002 INFO L78 Accepts]: Start accepts. Automaton has 5887 states and 16292 transitions. Word has length 67 [2019-12-07 14:27:50,002 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:27:50,003 INFO L462 AbstractCegarLoop]: Abstraction has 5887 states and 16292 transitions. [2019-12-07 14:27:50,003 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 14:27:50,003 INFO L276 IsEmpty]: Start isEmpty. Operand 5887 states and 16292 transitions. [2019-12-07 14:27:50,006 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 14:27:50,006 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:27:50,006 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:27:50,007 INFO L410 AbstractCegarLoop]: === Iteration 25 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:27:50,007 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:27:50,007 INFO L82 PathProgramCache]: Analyzing trace with hash -1375362528, now seen corresponding path program 5 times [2019-12-07 14:27:50,007 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:27:50,007 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [904475146] [2019-12-07 14:27:50,007 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:27:50,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 14:27:50,213 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 14:27:50,213 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [904475146] [2019-12-07 14:27:50,214 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 14:27:50,214 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2019-12-07 14:27:50,214 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1467587237] [2019-12-07 14:27:50,214 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2019-12-07 14:27:50,214 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 14:27:50,214 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2019-12-07 14:27:50,214 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=201, Unknown=0, NotChecked=0, Total=240 [2019-12-07 14:27:50,214 INFO L87 Difference]: Start difference. First operand 5887 states and 16292 transitions. Second operand 16 states. [2019-12-07 14:27:50,924 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 14:27:50,924 INFO L93 Difference]: Finished difference Result 10511 states and 29104 transitions. [2019-12-07 14:27:50,924 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2019-12-07 14:27:50,924 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 67 [2019-12-07 14:27:50,924 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 14:27:50,932 INFO L225 Difference]: With dead ends: 10511 [2019-12-07 14:27:50,932 INFO L226 Difference]: Without dead ends: 10364 [2019-12-07 14:27:50,933 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 299 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=284, Invalid=1198, Unknown=0, NotChecked=0, Total=1482 [2019-12-07 14:27:50,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10364 states. [2019-12-07 14:27:51,014 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10364 to 5736. [2019-12-07 14:27:51,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5736 states. [2019-12-07 14:27:51,021 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5736 states to 5736 states and 15852 transitions. [2019-12-07 14:27:51,021 INFO L78 Accepts]: Start accepts. Automaton has 5736 states and 15852 transitions. Word has length 67 [2019-12-07 14:27:51,021 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 14:27:51,021 INFO L462 AbstractCegarLoop]: Abstraction has 5736 states and 15852 transitions. [2019-12-07 14:27:51,021 INFO L463 AbstractCegarLoop]: Interpolant automaton has 16 states. [2019-12-07 14:27:51,021 INFO L276 IsEmpty]: Start isEmpty. Operand 5736 states and 15852 transitions. [2019-12-07 14:27:51,025 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 14:27:51,025 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 14:27:51,025 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 14:27:51,025 INFO L410 AbstractCegarLoop]: === Iteration 26 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 14:27:51,025 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 14:27:51,025 INFO L82 PathProgramCache]: Analyzing trace with hash -1680235652, now seen corresponding path program 6 times [2019-12-07 14:27:51,026 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 14:27:51,026 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [759566430] [2019-12-07 14:27:51,026 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 14:27:51,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 14:27:51,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 14:27:51,108 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 14:27:51,108 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 14:27:51,110 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [834] [834] ULTIMATE.startENTRY-->L812: Formula: (let ((.cse0 (store |v_#valid_55| 0 0))) (and (= v_~main$tmp_guard0~0_30 0) (= 0 v_~x$w_buff0_used~0_718) (= 0 v_~x$w_buff1_used~0_397) (= |v_#NULL.offset_3| 0) (= v_~z~0_14 0) (= v_~x$r_buff1_thd0~0_314 0) (= 0 v_~x$r_buff0_thd3~0_141) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t515~0.base_20|) (= 0 v_~weak$$choice0~0_17) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t515~0.base_20|)) (= |v_ULTIMATE.start_main_~#t515~0.offset_15| 0) (= v_~main$tmp_guard1~0_56 0) (= 0 v_~x$read_delayed_var~0.base_8) (= 0 v_~__unbuffered_p2_EAX~0_39) (= v_~x$r_buff1_thd1~0_232 0) (= 0 v_~x$r_buff1_thd2~0_210) (< 0 |v_#StackHeapBarrier_18|) (= v_~weak$$choice2~0_122 0) (= 0 v_~x$read_delayed~0_8) (= 0 v_~x$read_delayed_var~0.offset_8) (= v_~x$mem_tmp~0_24 0) (= 0 v_~x$r_buff1_thd3~0_224) (= v_~y~0_88 0) (= 0 v_~x~0_198) (= 0 v_~x$w_buff0~0_179) (= v_~__unbuffered_p1_EAX~0_173 0) (= 0 |v_#NULL.base_3|) (= v_~__unbuffered_cnt~0_153 0) (= |v_#valid_53| (store .cse0 |v_ULTIMATE.start_main_~#t515~0.base_20| 1)) (= v_~x$r_buff0_thd1~0_158 0) (= 0 v_~x$w_buff1~0_170) (= v_~x$flush_delayed~0_54 0) (= (store |v_#memory_int_20| |v_ULTIMATE.start_main_~#t515~0.base_20| (store (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#t515~0.base_20|) |v_ULTIMATE.start_main_~#t515~0.offset_15| 0)) |v_#memory_int_19|) (= 0 v_~x$r_buff0_thd2~0_286) (= (store |v_#length_24| |v_ULTIMATE.start_main_~#t515~0.base_20| 4) |v_#length_23|) (= v_~x$r_buff0_thd0~0_390 0) (= v_~__unbuffered_p2_EBX~0_39 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_55|, #memory_int=|v_#memory_int_20|, #length=|v_#length_24|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_24|, ~x$w_buff0~0=v_~x$w_buff0~0_179, ULTIMATE.start_main_~#t515~0.base=|v_ULTIMATE.start_main_~#t515~0.base_20|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_30|, ~x$flush_delayed~0=v_~x$flush_delayed~0_54, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_24|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_38|, #NULL.offset=|v_#NULL.offset_3|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_232|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_70|, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_232, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_141, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_48|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_32|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_76|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_59|, ULTIMATE.start_main_~#t516~0.offset=|v_ULTIMATE.start_main_~#t516~0.offset_15|, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_173, #length=|v_#length_23|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_39, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_390, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_39, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_9|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_32|, ~x$w_buff1~0=v_~x$w_buff1~0_170, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_49|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_397, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_210, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_37|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_64|, ~x$read_delayed_var~0.base=v_~x$read_delayed_var~0.base_8, ~weak$$choice0~0=v_~weak$$choice0~0_17, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_25|, ULTIMATE.start_main_~#t516~0.base=|v_ULTIMATE.start_main_~#t516~0.base_19|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_153, ULTIMATE.start_main_~#t517~0.offset=|v_ULTIMATE.start_main_~#t517~0.offset_15|, ~x~0=v_~x~0_198, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_158, ULTIMATE.start_main_~#t515~0.offset=|v_ULTIMATE.start_main_~#t515~0.offset_15|, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_24|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_36|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_27|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_38|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_224, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_56, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_32|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_39|, ~x$mem_tmp~0=v_~x$mem_tmp~0_24, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_20|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_40|, ULTIMATE.start_main_~#t517~0.base=|v_ULTIMATE.start_main_~#t517~0.base_18|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_87|, ~y~0=v_~y~0_88, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_8|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_17|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_40|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_48|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_30, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_314, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_286, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_40|, #NULL.base=|v_#NULL.base_3|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_49|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_718, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_29|, ~x$read_delayed_var~0.offset=v_~x$read_delayed_var~0.offset_8, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_16|, #valid=|v_#valid_53|, #memory_int=|v_#memory_int_19|, ~z~0=v_~z~0_14, ~weak$$choice2~0=v_~weak$$choice2~0_122, ~x$read_delayed~0=v_~x$read_delayed~0_8} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ~x$w_buff0~0, ULTIMATE.start_main_~#t515~0.base, ULTIMATE.start_main_#t~ite28, ~x$flush_delayed~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ~x$r_buff1_thd1~0, ~x$r_buff0_thd3~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ULTIMATE.start_main_~#t516~0.offset, ~__unbuffered_p1_EAX~0, #length, ~__unbuffered_p2_EAX~0, ~x$r_buff0_thd0~0, ~__unbuffered_p2_EBX~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ~x$w_buff1~0, ULTIMATE.start_main_#t~ite35, ~x$w_buff1_used~0, ~x$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite33, ~x$read_delayed_var~0.base, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_~#t516~0.base, ~__unbuffered_cnt~0, ULTIMATE.start_main_~#t517~0.offset, ~x~0, ~x$r_buff0_thd1~0, ULTIMATE.start_main_~#t515~0.offset, ULTIMATE.start_main_#t~nondet31, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~x$r_buff1_thd3~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ~x$mem_tmp~0, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_~#t517~0.base, ULTIMATE.start_main_#t~ite51, ~y~0, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ~x$r_buff1_thd0~0, ~x$r_buff0_thd2~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~x$w_buff0_used~0, ULTIMATE.start_main_#t~ite41, ~x$read_delayed_var~0.offset, ULTIMATE.start_main_#res, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~x$read_delayed~0] because there is no mapped edge [2019-12-07 14:27:51,111 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L812-1-->L814: Formula: (and (not (= |v_ULTIMATE.start_main_~#t516~0.base_9| 0)) (= (select |v_#valid_30| |v_ULTIMATE.start_main_~#t516~0.base_9|) 0) (< |v_#StackHeapBarrier_9| |v_ULTIMATE.start_main_~#t516~0.base_9|) (= |v_#memory_int_9| (store |v_#memory_int_10| |v_ULTIMATE.start_main_~#t516~0.base_9| (store (select |v_#memory_int_10| |v_ULTIMATE.start_main_~#t516~0.base_9|) |v_ULTIMATE.start_main_~#t516~0.offset_8| 1))) (= |v_#length_13| (store |v_#length_14| |v_ULTIMATE.start_main_~#t516~0.base_9| 4)) (= |v_ULTIMATE.start_main_~#t516~0.offset_8| 0) (= |v_#valid_29| (store |v_#valid_30| |v_ULTIMATE.start_main_~#t516~0.base_9| 1))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_30|, #memory_int=|v_#memory_int_10|, #length=|v_#length_14|} OutVars{ULTIMATE.start_main_~#t516~0.offset=|v_ULTIMATE.start_main_~#t516~0.offset_8|, #StackHeapBarrier=|v_#StackHeapBarrier_9|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_4|, #valid=|v_#valid_29|, #memory_int=|v_#memory_int_9|, ULTIMATE.start_main_~#t516~0.base=|v_ULTIMATE.start_main_~#t516~0.base_9|, #length=|v_#length_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t516~0.offset, ULTIMATE.start_main_#t~nondet21, #valid, #memory_int, ULTIMATE.start_main_~#t516~0.base, #length] because there is no mapped edge [2019-12-07 14:27:51,111 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [800] [800] L814-1-->L816: Formula: (and (= |v_#memory_int_11| (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t517~0.base_12| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t517~0.base_12|) |v_ULTIMATE.start_main_~#t517~0.offset_10| 2))) (= (store |v_#valid_32| |v_ULTIMATE.start_main_~#t517~0.base_12| 1) |v_#valid_31|) (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t517~0.base_12|) (not (= |v_ULTIMATE.start_main_~#t517~0.base_12| 0)) (= |v_ULTIMATE.start_main_~#t517~0.offset_10| 0) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t517~0.base_12| 4)) (= (select |v_#valid_32| |v_ULTIMATE.start_main_~#t517~0.base_12|) 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_12|, #length=|v_#length_16|} OutVars{ULTIMATE.start_main_~#t517~0.base=|v_ULTIMATE.start_main_~#t517~0.base_12|, #StackHeapBarrier=|v_#StackHeapBarrier_10|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_11|, #length=|v_#length_15|, ULTIMATE.start_main_~#t517~0.offset=|v_ULTIMATE.start_main_~#t517~0.offset_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t517~0.base, ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, #length, ULTIMATE.start_main_~#t517~0.offset] because there is no mapped edge [2019-12-07 14:27:51,111 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [738] [738] L4-->L766: Formula: (and (= v_~x$r_buff1_thd0~0_91 v_~x$r_buff0_thd0~0_128) (not (= v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_8 0)) (= v_~y~0_37 v_~__unbuffered_p1_EAX~0_43) (= v_~x$r_buff1_thd1~0_47 v_~x$r_buff0_thd1~0_56) (= v_~x$r_buff1_thd3~0_52 v_~x$r_buff0_thd3~0_68) (= 1 v_~x$r_buff0_thd2~0_98) (= v_~x$r_buff1_thd2~0_53 v_~x$r_buff0_thd2~0_99)) InVars {P1Thread1of1ForFork1___VERIFIER_assert_~expression=v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_8, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_128, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_56, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_68, ~y~0=v_~y~0_37, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_99} OutVars{P1Thread1of1ForFork1___VERIFIER_assert_~expression=v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_8, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_128, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_56, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_43, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_52, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_53, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_47, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_68, ~y~0=v_~y~0_37, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_98, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_91} AuxVars[] AssignedVars[~__unbuffered_p1_EAX~0, ~x$r_buff1_thd3~0, ~x$r_buff1_thd2~0, ~x$r_buff1_thd1~0, ~x$r_buff0_thd2~0, ~x$r_buff1_thd0~0] because there is no mapped edge [2019-12-07 14:27:51,112 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [765] [765] L767-->L767-2: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff0_used~0_In2122932390 256))) (.cse1 (= 0 (mod ~x$r_buff0_thd2~0_In2122932390 256)))) (or (and (not .cse0) (not .cse1) (= |P1Thread1of1ForFork1_#t~ite11_Out2122932390| 0)) (and (= ~x$w_buff0_used~0_In2122932390 |P1Thread1of1ForFork1_#t~ite11_Out2122932390|) (or .cse0 .cse1)))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In2122932390, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2122932390} OutVars{P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out2122932390|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In2122932390, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2122932390} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 14:27:51,112 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [757] [757] L768-->L768-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff0_used~0_In-953194932 256))) (.cse0 (= 0 (mod ~x$r_buff0_thd2~0_In-953194932 256))) (.cse3 (= 0 (mod ~x$r_buff1_thd2~0_In-953194932 256))) (.cse2 (= 0 (mod ~x$w_buff1_used~0_In-953194932 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P1Thread1of1ForFork1_#t~ite12_Out-953194932| ~x$w_buff1_used~0_In-953194932)) (and (= |P1Thread1of1ForFork1_#t~ite12_Out-953194932| 0) (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2)))))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-953194932, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-953194932, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-953194932, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-953194932} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-953194932, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-953194932, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out-953194932|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-953194932, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-953194932} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 14:27:51,112 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [778] [778] L769-->L770: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff0_used~0_In-782240392 256))) (.cse2 (= 0 (mod ~x$r_buff0_thd2~0_In-782240392 256))) (.cse1 (= ~x$r_buff0_thd2~0_In-782240392 ~x$r_buff0_thd2~0_Out-782240392))) (or (and .cse0 .cse1) (and (not .cse0) (= 0 ~x$r_buff0_thd2~0_Out-782240392) (not .cse2)) (and .cse2 .cse1))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-782240392, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-782240392} OutVars{P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out-782240392|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_Out-782240392, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-782240392} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13, ~x$r_buff0_thd2~0] because there is no mapped edge [2019-12-07 14:27:51,112 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L770-->L770-2: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff0_thd2~0_In-1115654997 256))) (.cse0 (= (mod ~x$w_buff0_used~0_In-1115654997 256) 0)) (.cse2 (= (mod ~x$r_buff1_thd2~0_In-1115654997 256) 0)) (.cse3 (= (mod ~x$w_buff1_used~0_In-1115654997 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork1_#t~ite14_Out-1115654997|)) (and (or .cse1 .cse0) (or .cse2 .cse3) (= ~x$r_buff1_thd2~0_In-1115654997 |P1Thread1of1ForFork1_#t~ite14_Out-1115654997|)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-1115654997, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-1115654997, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1115654997, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1115654997} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-1115654997, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-1115654997, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1115654997, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out-1115654997|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1115654997} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 14:27:51,113 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [804] [804] L770-2-->P1EXIT: Formula: (and (= v_~x$r_buff1_thd2~0_105 |v_P1Thread1of1ForFork1_#t~ite14_38|) (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= v_~__unbuffered_cnt~0_76 (+ v_~__unbuffered_cnt~0_77 1)) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_77, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_38|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_105, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_76, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_37|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~x$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 14:27:51,113 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L789-2-->L789-4: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff1_used~0_In881150166 256))) (.cse0 (= 0 (mod ~x$r_buff1_thd3~0_In881150166 256)))) (or (and (not .cse0) (not .cse1) (= |P2Thread1of1ForFork2_#t~ite15_Out881150166| ~x$w_buff1~0_In881150166)) (and (= |P2Thread1of1ForFork2_#t~ite15_Out881150166| ~x~0_In881150166) (or .cse1 .cse0)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In881150166, ~x$w_buff1_used~0=~x$w_buff1_used~0_In881150166, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In881150166, ~x~0=~x~0_In881150166} OutVars{P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out881150166|, ~x$w_buff1~0=~x$w_buff1~0_In881150166, ~x$w_buff1_used~0=~x$w_buff1_used~0_In881150166, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In881150166, ~x~0=~x~0_In881150166} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 14:27:51,114 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L737-2-->L737-4: Formula: (let ((.cse0 (= (mod ~x$w_buff1_used~0_In-135909387 256) 0)) (.cse1 (= 0 (mod ~x$r_buff1_thd1~0_In-135909387 256)))) (or (and (= ~x~0_In-135909387 |P0Thread1of1ForFork0_#t~ite3_Out-135909387|) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= ~x$w_buff1~0_In-135909387 |P0Thread1of1ForFork0_#t~ite3_Out-135909387|)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In-135909387, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-135909387, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-135909387, ~x~0=~x~0_In-135909387} OutVars{P0Thread1of1ForFork0_#t~ite3=|P0Thread1of1ForFork0_#t~ite3_Out-135909387|, ~x$w_buff1~0=~x$w_buff1~0_In-135909387, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-135909387, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-135909387, ~x~0=~x~0_In-135909387} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite3] because there is no mapped edge [2019-12-07 14:27:51,114 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [705] [705] L737-4-->L738: Formula: (= v_~x~0_33 |v_P0Thread1of1ForFork0_#t~ite3_8|) InVars {P0Thread1of1ForFork0_#t~ite3=|v_P0Thread1of1ForFork0_#t~ite3_8|} OutVars{P0Thread1of1ForFork0_#t~ite3=|v_P0Thread1of1ForFork0_#t~ite3_7|, P0Thread1of1ForFork0_#t~ite4=|v_P0Thread1of1ForFork0_#t~ite4_11|, ~x~0=v_~x~0_33} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite3, P0Thread1of1ForFork0_#t~ite4, ~x~0] because there is no mapped edge [2019-12-07 14:27:51,114 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [732] [732] L789-4-->L790: Formula: (= |v_P2Thread1of1ForFork2_#t~ite15_8| v_~x~0_58) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_8|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_7|, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_13|, ~x~0=v_~x~0_58} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, P2Thread1of1ForFork2_#t~ite16, ~x~0] because there is no mapped edge [2019-12-07 14:27:51,114 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [780] [780] L738-->L738-2: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff0_used~0_In-1104433153 256))) (.cse1 (= (mod ~x$r_buff0_thd1~0_In-1104433153 256) 0))) (or (and (not .cse0) (= 0 |P0Thread1of1ForFork0_#t~ite5_Out-1104433153|) (not .cse1)) (and (= ~x$w_buff0_used~0_In-1104433153 |P0Thread1of1ForFork0_#t~ite5_Out-1104433153|) (or .cse0 .cse1)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-1104433153, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1104433153} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out-1104433153|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-1104433153, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1104433153} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 14:27:51,114 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [782] [782] L790-->L790-2: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff0_thd3~0_In1225542173 256))) (.cse0 (= (mod ~x$w_buff0_used~0_In1225542173 256) 0))) (or (and (= ~x$w_buff0_used~0_In1225542173 |P2Thread1of1ForFork2_#t~ite17_Out1225542173|) (or .cse0 .cse1)) (and (not .cse1) (= 0 |P2Thread1of1ForFork2_#t~ite17_Out1225542173|) (not .cse0)))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1225542173, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1225542173} OutVars{~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1225542173, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out1225542173|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1225542173} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 14:27:51,114 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [759] [759] L791-->L791-2: Formula: (let ((.cse0 (= 0 (mod ~x$r_buff0_thd3~0_In-263723772 256))) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In-263723772 256))) (.cse3 (= 0 (mod ~x$w_buff1_used~0_In-263723772 256))) (.cse2 (= (mod ~x$r_buff1_thd3~0_In-263723772 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork2_#t~ite18_Out-263723772|)) (and (= |P2Thread1of1ForFork2_#t~ite18_Out-263723772| ~x$w_buff1_used~0_In-263723772) (or .cse0 .cse1) (or .cse3 .cse2)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-263723772, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-263723772, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-263723772, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-263723772} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-263723772, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-263723772, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-263723772, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out-263723772|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-263723772} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 14:27:51,115 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L792-->L792-2: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff0_used~0_In-1560041082 256))) (.cse1 (= (mod ~x$r_buff0_thd3~0_In-1560041082 256) 0))) (or (and (not .cse0) (= 0 |P2Thread1of1ForFork2_#t~ite19_Out-1560041082|) (not .cse1)) (and (or .cse0 .cse1) (= ~x$r_buff0_thd3~0_In-1560041082 |P2Thread1of1ForFork2_#t~ite19_Out-1560041082|)))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1560041082, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1560041082} OutVars{~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1560041082, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out-1560041082|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1560041082} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 14:27:51,115 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [763] [763] L793-->L793-2: Formula: (let ((.cse0 (= (mod ~x$w_buff0_used~0_In-1345021663 256) 0)) (.cse1 (= 0 (mod ~x$r_buff0_thd3~0_In-1345021663 256))) (.cse3 (= 0 (mod ~x$w_buff1_used~0_In-1345021663 256))) (.cse2 (= (mod ~x$r_buff1_thd3~0_In-1345021663 256) 0))) (or (and (= |P2Thread1of1ForFork2_#t~ite20_Out-1345021663| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (or .cse3 .cse2) (= |P2Thread1of1ForFork2_#t~ite20_Out-1345021663| ~x$r_buff1_thd3~0_In-1345021663)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-1345021663, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1345021663, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1345021663, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1345021663} OutVars{P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out-1345021663|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1345021663, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1345021663, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1345021663, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1345021663} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 14:27:51,115 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [794] [794] L793-2-->P2EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_71 1) v_~__unbuffered_cnt~0_70) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= v_~x$r_buff1_thd3~0_93 |v_P2Thread1of1ForFork2_#t~ite20_40|)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_40|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_71} OutVars{P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_39|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_93, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_70, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, ~x$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 14:27:51,115 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [762] [762] L739-->L739-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff1_used~0_In-1503264082 256))) (.cse0 (= (mod ~x$r_buff1_thd1~0_In-1503264082 256) 0)) (.cse3 (= 0 (mod ~x$r_buff0_thd1~0_In-1503264082 256))) (.cse2 (= 0 (mod ~x$w_buff0_used~0_In-1503264082 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P0Thread1of1ForFork0_#t~ite6_Out-1503264082|)) (and (= |P0Thread1of1ForFork0_#t~ite6_Out-1503264082| ~x$w_buff1_used~0_In-1503264082) (or .cse1 .cse0) (or .cse3 .cse2)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-1503264082, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1503264082, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-1503264082, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1503264082} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out-1503264082|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-1503264082, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1503264082, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-1503264082, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1503264082} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 14:27:51,116 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L740-->L740-2: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff0_used~0_In1589800303 256))) (.cse1 (= (mod ~x$r_buff0_thd1~0_In1589800303 256) 0))) (or (and (not .cse0) (not .cse1) (= |P0Thread1of1ForFork0_#t~ite7_Out1589800303| 0)) (and (= |P0Thread1of1ForFork0_#t~ite7_Out1589800303| ~x$r_buff0_thd1~0_In1589800303) (or .cse0 .cse1)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In1589800303, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1589800303} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In1589800303, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out1589800303|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1589800303} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7] because there is no mapped edge [2019-12-07 14:27:51,116 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [769] [769] L741-->L741-2: Formula: (let ((.cse3 (= (mod ~x$r_buff1_thd1~0_In-691863423 256) 0)) (.cse2 (= 0 (mod ~x$w_buff1_used~0_In-691863423 256))) (.cse1 (= (mod ~x$r_buff0_thd1~0_In-691863423 256) 0)) (.cse0 (= 0 (mod ~x$w_buff0_used~0_In-691863423 256)))) (or (and (= |P0Thread1of1ForFork0_#t~ite8_Out-691863423| ~x$r_buff1_thd1~0_In-691863423) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |P0Thread1of1ForFork0_#t~ite8_Out-691863423| 0) (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0)))))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-691863423, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-691863423, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-691863423, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-691863423} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-691863423, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out-691863423|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-691863423, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-691863423, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-691863423} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 14:27:51,116 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [809] [809] L741-2-->P0EXIT: Formula: (and (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~x$r_buff1_thd1~0_125 |v_P0Thread1of1ForFork0_#t~ite8_56|) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_84 1) v_~__unbuffered_cnt~0_83)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_56|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_84} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_55|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_83, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_125} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, ~x$r_buff1_thd1~0] because there is no mapped edge [2019-12-07 14:27:51,116 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L820-->L822-2: Formula: (and (or (= 0 (mod v_~x$w_buff0_used~0_136 256)) (= (mod v_~x$r_buff0_thd0~0_90 256) 0)) (not (= 0 (mod v_~main$tmp_guard0~0_6 256)))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_90, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_136} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_90, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_136} AuxVars[] AssignedVars[] because there is no mapped edge [2019-12-07 14:27:51,116 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L822-2-->L822-5: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff1_thd0~0_In221889007 256))) (.cse0 (= (mod ~x$w_buff1_used~0_In221889007 256) 0)) (.cse2 (= |ULTIMATE.start_main_#t~ite25_Out221889007| |ULTIMATE.start_main_#t~ite24_Out221889007|))) (or (and (or .cse0 .cse1) (= ~x~0_In221889007 |ULTIMATE.start_main_#t~ite24_Out221889007|) .cse2) (and (not .cse1) (not .cse0) .cse2 (= |ULTIMATE.start_main_#t~ite24_Out221889007| ~x$w_buff1~0_In221889007)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In221889007, ~x$w_buff1_used~0=~x$w_buff1_used~0_In221889007, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In221889007, ~x~0=~x~0_In221889007} OutVars{~x$w_buff1~0=~x$w_buff1~0_In221889007, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out221889007|, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out221889007|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In221889007, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In221889007, ~x~0=~x~0_In221889007} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25] because there is no mapped edge [2019-12-07 14:27:51,117 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [756] [756] L823-->L823-2: Formula: (let ((.cse0 (= 0 (mod ~x$r_buff0_thd0~0_In2125112783 256))) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In2125112783 256)))) (or (and (or .cse0 .cse1) (= ~x$w_buff0_used~0_In2125112783 |ULTIMATE.start_main_#t~ite26_Out2125112783|)) (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite26_Out2125112783|) (not .cse1)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In2125112783, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2125112783} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In2125112783, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out2125112783|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2125112783} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 14:27:51,117 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L824-->L824-2: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff0_used~0_In-1036793946 256))) (.cse1 (= (mod ~x$r_buff0_thd0~0_In-1036793946 256) 0)) (.cse3 (= (mod ~x$r_buff1_thd0~0_In-1036793946 256) 0)) (.cse2 (= (mod ~x$w_buff1_used~0_In-1036793946 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |ULTIMATE.start_main_#t~ite27_Out-1036793946| ~x$w_buff1_used~0_In-1036793946)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2))) (= |ULTIMATE.start_main_#t~ite27_Out-1036793946| 0)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1036793946, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1036793946, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-1036793946, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1036793946} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1036793946, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1036793946, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out-1036793946|, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-1036793946, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1036793946} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 14:27:51,117 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [772] [772] L825-->L825-2: Formula: (let ((.cse1 (= (mod ~x$r_buff0_thd0~0_In369584709 256) 0)) (.cse0 (= 0 (mod ~x$w_buff0_used~0_In369584709 256)))) (or (and (= |ULTIMATE.start_main_#t~ite28_Out369584709| ~x$r_buff0_thd0~0_In369584709) (or .cse0 .cse1)) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite28_Out369584709| 0) (not .cse0)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In369584709, ~x$w_buff0_used~0=~x$w_buff0_used~0_In369584709} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In369584709, ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out369584709|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In369584709} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 14:27:51,118 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L826-->L826-2: Formula: (let ((.cse3 (= 0 (mod ~x$r_buff1_thd0~0_In-1027296374 256))) (.cse2 (= 0 (mod ~x$w_buff1_used~0_In-1027296374 256))) (.cse1 (= 0 (mod ~x$r_buff0_thd0~0_In-1027296374 256))) (.cse0 (= 0 (mod ~x$w_buff0_used~0_In-1027296374 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~x$r_buff1_thd0~0_In-1027296374 |ULTIMATE.start_main_#t~ite29_Out-1027296374|)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0))) (= 0 |ULTIMATE.start_main_#t~ite29_Out-1027296374|)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1027296374, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1027296374, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-1027296374, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1027296374} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1027296374, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-1027296374|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1027296374, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-1027296374, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1027296374} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 14:27:51,119 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [816] [816] L835-->L835-8: Formula: (let ((.cse1 (= 0 (mod ~weak$$choice2~0_In-2117757750 256)))) (or (and (= |ULTIMATE.start_main_#t~ite38_Out-2117757750| ~x$w_buff1~0_In-2117757750) (let ((.cse0 (= 0 (mod ~x$r_buff0_thd0~0_In-2117757750 256)))) (or (and (= (mod ~x$r_buff1_thd0~0_In-2117757750 256) 0) .cse0) (= (mod ~x$w_buff0_used~0_In-2117757750 256) 0) (and .cse0 (= (mod ~x$w_buff1_used~0_In-2117757750 256) 0)))) (= |ULTIMATE.start_main_#t~ite39_Out-2117757750| |ULTIMATE.start_main_#t~ite38_Out-2117757750|) .cse1) (and (= |ULTIMATE.start_main_#t~ite39_Out-2117757750| ~x$w_buff1~0_In-2117757750) (= |ULTIMATE.start_main_#t~ite38_In-2117757750| |ULTIMATE.start_main_#t~ite38_Out-2117757750|) (not .cse1)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-2117757750, ~x$w_buff1~0=~x$w_buff1~0_In-2117757750, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-2117757750, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_In-2117757750|, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-2117757750, ~weak$$choice2~0=~weak$$choice2~0_In-2117757750, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-2117757750} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-2117757750, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out-2117757750|, ~x$w_buff1~0=~x$w_buff1~0_In-2117757750, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-2117757750, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_Out-2117757750|, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-2117757750, ~weak$$choice2~0=~weak$$choice2~0_In-2117757750, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-2117757750} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite38] because there is no mapped edge [2019-12-07 14:27:51,120 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [829] [829] L838-->L839-8: Formula: (and (= v_~x$r_buff1_thd0~0_306 |v_ULTIMATE.start_main_#t~ite51_81|) (= v_~x$r_buff0_thd0~0_381 v_~x$r_buff0_thd0~0_380) (= |v_ULTIMATE.start_main_#t~ite49_59| |v_ULTIMATE.start_main_#t~ite49_60|) (not (= (mod v_~weak$$choice2~0_116 256) 0)) (= |v_ULTIMATE.start_main_#t~ite50_66| |v_ULTIMATE.start_main_#t~ite50_65|)) InVars {ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_66|, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_381, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_60|, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_306, ~weak$$choice2~0=v_~weak$$choice2~0_116} OutVars{ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_65|, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_380, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_81|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_34|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_34|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_59|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_35|, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_306, ~weak$$choice2~0=v_~weak$$choice2~0_116} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite50, ~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite51, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 14:27:51,120 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [796] [796] L841-->L844-1: Formula: (and (= (mod v_~main$tmp_guard1~0_23 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|) (not (= (mod v_~x$flush_delayed~0_26 256) 0)) (= v_~x$flush_delayed~0_25 0) (= v_~x$mem_tmp~0_14 v_~x~0_102)) InVars {~x$flush_delayed~0=v_~x$flush_delayed~0_26, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_23, ~x$mem_tmp~0=v_~x$mem_tmp~0_14} OutVars{ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_23|, ~x$flush_delayed~0=v_~x$flush_delayed~0_25, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_23, ~x$mem_tmp~0=v_~x$mem_tmp~0_14, ~x~0=v_~x~0_102, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ~x$flush_delayed~0, ~x~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 14:27:51,121 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [783] [783] L844-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 14:27:51,169 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 02:27:51 BasicIcfg [2019-12-07 14:27:51,169 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 14:27:51,169 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 14:27:51,169 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 14:27:51,170 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 14:27:51,170 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 02:25:20" (3/4) ... [2019-12-07 14:27:51,172 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 14:27:51,172 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [834] [834] ULTIMATE.startENTRY-->L812: Formula: (let ((.cse0 (store |v_#valid_55| 0 0))) (and (= v_~main$tmp_guard0~0_30 0) (= 0 v_~x$w_buff0_used~0_718) (= 0 v_~x$w_buff1_used~0_397) (= |v_#NULL.offset_3| 0) (= v_~z~0_14 0) (= v_~x$r_buff1_thd0~0_314 0) (= 0 v_~x$r_buff0_thd3~0_141) (< |v_#StackHeapBarrier_18| |v_ULTIMATE.start_main_~#t515~0.base_20|) (= 0 v_~weak$$choice0~0_17) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t515~0.base_20|)) (= |v_ULTIMATE.start_main_~#t515~0.offset_15| 0) (= v_~main$tmp_guard1~0_56 0) (= 0 v_~x$read_delayed_var~0.base_8) (= 0 v_~__unbuffered_p2_EAX~0_39) (= v_~x$r_buff1_thd1~0_232 0) (= 0 v_~x$r_buff1_thd2~0_210) (< 0 |v_#StackHeapBarrier_18|) (= v_~weak$$choice2~0_122 0) (= 0 v_~x$read_delayed~0_8) (= 0 v_~x$read_delayed_var~0.offset_8) (= v_~x$mem_tmp~0_24 0) (= 0 v_~x$r_buff1_thd3~0_224) (= v_~y~0_88 0) (= 0 v_~x~0_198) (= 0 v_~x$w_buff0~0_179) (= v_~__unbuffered_p1_EAX~0_173 0) (= 0 |v_#NULL.base_3|) (= v_~__unbuffered_cnt~0_153 0) (= |v_#valid_53| (store .cse0 |v_ULTIMATE.start_main_~#t515~0.base_20| 1)) (= v_~x$r_buff0_thd1~0_158 0) (= 0 v_~x$w_buff1~0_170) (= v_~x$flush_delayed~0_54 0) (= (store |v_#memory_int_20| |v_ULTIMATE.start_main_~#t515~0.base_20| (store (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#t515~0.base_20|) |v_ULTIMATE.start_main_~#t515~0.offset_15| 0)) |v_#memory_int_19|) (= 0 v_~x$r_buff0_thd2~0_286) (= (store |v_#length_24| |v_ULTIMATE.start_main_~#t515~0.base_20| 4) |v_#length_23|) (= v_~x$r_buff0_thd0~0_390 0) (= v_~__unbuffered_p2_EBX~0_39 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_18|, #valid=|v_#valid_55|, #memory_int=|v_#memory_int_20|, #length=|v_#length_24|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_24|, ~x$w_buff0~0=v_~x$w_buff0~0_179, ULTIMATE.start_main_~#t515~0.base=|v_ULTIMATE.start_main_~#t515~0.base_20|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_30|, ~x$flush_delayed~0=v_~x$flush_delayed~0_54, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_24|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_38|, #NULL.offset=|v_#NULL.offset_3|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_232|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_70|, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_232, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_141, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_48|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_32|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_76|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_59|, ULTIMATE.start_main_~#t516~0.offset=|v_ULTIMATE.start_main_~#t516~0.offset_15|, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_173, #length=|v_#length_23|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_39, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_390, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_39, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_9|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_32|, ~x$w_buff1~0=v_~x$w_buff1~0_170, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_49|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_397, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_210, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_37|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_64|, ~x$read_delayed_var~0.base=v_~x$read_delayed_var~0.base_8, ~weak$$choice0~0=v_~weak$$choice0~0_17, #StackHeapBarrier=|v_#StackHeapBarrier_18|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_25|, ULTIMATE.start_main_~#t516~0.base=|v_ULTIMATE.start_main_~#t516~0.base_19|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_153, ULTIMATE.start_main_~#t517~0.offset=|v_ULTIMATE.start_main_~#t517~0.offset_15|, ~x~0=v_~x~0_198, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_158, ULTIMATE.start_main_~#t515~0.offset=|v_ULTIMATE.start_main_~#t515~0.offset_15|, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_24|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_36|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_27|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_38|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_224, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_56, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_32|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_39|, ~x$mem_tmp~0=v_~x$mem_tmp~0_24, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_20|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_40|, ULTIMATE.start_main_~#t517~0.base=|v_ULTIMATE.start_main_~#t517~0.base_18|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_87|, ~y~0=v_~y~0_88, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_8|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_17|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_40|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_48|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_30, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_314, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_286, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_40|, #NULL.base=|v_#NULL.base_3|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_49|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_718, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_29|, ~x$read_delayed_var~0.offset=v_~x$read_delayed_var~0.offset_8, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_16|, #valid=|v_#valid_53|, #memory_int=|v_#memory_int_19|, ~z~0=v_~z~0_14, ~weak$$choice2~0=v_~weak$$choice2~0_122, ~x$read_delayed~0=v_~x$read_delayed~0_8} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ~x$w_buff0~0, ULTIMATE.start_main_~#t515~0.base, ULTIMATE.start_main_#t~ite28, ~x$flush_delayed~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ~x$r_buff1_thd1~0, ~x$r_buff0_thd3~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ULTIMATE.start_main_~#t516~0.offset, ~__unbuffered_p1_EAX~0, #length, ~__unbuffered_p2_EAX~0, ~x$r_buff0_thd0~0, ~__unbuffered_p2_EBX~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ~x$w_buff1~0, ULTIMATE.start_main_#t~ite35, ~x$w_buff1_used~0, ~x$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite33, ~x$read_delayed_var~0.base, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_~#t516~0.base, ~__unbuffered_cnt~0, ULTIMATE.start_main_~#t517~0.offset, ~x~0, ~x$r_buff0_thd1~0, ULTIMATE.start_main_~#t515~0.offset, ULTIMATE.start_main_#t~nondet31, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~x$r_buff1_thd3~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ~x$mem_tmp~0, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_~#t517~0.base, ULTIMATE.start_main_#t~ite51, ~y~0, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ~x$r_buff1_thd0~0, ~x$r_buff0_thd2~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~x$w_buff0_used~0, ULTIMATE.start_main_#t~ite41, ~x$read_delayed_var~0.offset, ULTIMATE.start_main_#res, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~x$read_delayed~0] because there is no mapped edge [2019-12-07 14:27:51,172 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L812-1-->L814: Formula: (and (not (= |v_ULTIMATE.start_main_~#t516~0.base_9| 0)) (= (select |v_#valid_30| |v_ULTIMATE.start_main_~#t516~0.base_9|) 0) (< |v_#StackHeapBarrier_9| |v_ULTIMATE.start_main_~#t516~0.base_9|) (= |v_#memory_int_9| (store |v_#memory_int_10| |v_ULTIMATE.start_main_~#t516~0.base_9| (store (select |v_#memory_int_10| |v_ULTIMATE.start_main_~#t516~0.base_9|) |v_ULTIMATE.start_main_~#t516~0.offset_8| 1))) (= |v_#length_13| (store |v_#length_14| |v_ULTIMATE.start_main_~#t516~0.base_9| 4)) (= |v_ULTIMATE.start_main_~#t516~0.offset_8| 0) (= |v_#valid_29| (store |v_#valid_30| |v_ULTIMATE.start_main_~#t516~0.base_9| 1))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_30|, #memory_int=|v_#memory_int_10|, #length=|v_#length_14|} OutVars{ULTIMATE.start_main_~#t516~0.offset=|v_ULTIMATE.start_main_~#t516~0.offset_8|, #StackHeapBarrier=|v_#StackHeapBarrier_9|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_4|, #valid=|v_#valid_29|, #memory_int=|v_#memory_int_9|, ULTIMATE.start_main_~#t516~0.base=|v_ULTIMATE.start_main_~#t516~0.base_9|, #length=|v_#length_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t516~0.offset, ULTIMATE.start_main_#t~nondet21, #valid, #memory_int, ULTIMATE.start_main_~#t516~0.base, #length] because there is no mapped edge [2019-12-07 14:27:51,172 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [800] [800] L814-1-->L816: Formula: (and (= |v_#memory_int_11| (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t517~0.base_12| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t517~0.base_12|) |v_ULTIMATE.start_main_~#t517~0.offset_10| 2))) (= (store |v_#valid_32| |v_ULTIMATE.start_main_~#t517~0.base_12| 1) |v_#valid_31|) (< |v_#StackHeapBarrier_10| |v_ULTIMATE.start_main_~#t517~0.base_12|) (not (= |v_ULTIMATE.start_main_~#t517~0.base_12| 0)) (= |v_ULTIMATE.start_main_~#t517~0.offset_10| 0) (= |v_#length_15| (store |v_#length_16| |v_ULTIMATE.start_main_~#t517~0.base_12| 4)) (= (select |v_#valid_32| |v_ULTIMATE.start_main_~#t517~0.base_12|) 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_10|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_12|, #length=|v_#length_16|} OutVars{ULTIMATE.start_main_~#t517~0.base=|v_ULTIMATE.start_main_~#t517~0.base_12|, #StackHeapBarrier=|v_#StackHeapBarrier_10|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_11|, #length=|v_#length_15|, ULTIMATE.start_main_~#t517~0.offset=|v_ULTIMATE.start_main_~#t517~0.offset_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t517~0.base, ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, #length, ULTIMATE.start_main_~#t517~0.offset] because there is no mapped edge [2019-12-07 14:27:51,173 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [738] [738] L4-->L766: Formula: (and (= v_~x$r_buff1_thd0~0_91 v_~x$r_buff0_thd0~0_128) (not (= v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_8 0)) (= v_~y~0_37 v_~__unbuffered_p1_EAX~0_43) (= v_~x$r_buff1_thd1~0_47 v_~x$r_buff0_thd1~0_56) (= v_~x$r_buff1_thd3~0_52 v_~x$r_buff0_thd3~0_68) (= 1 v_~x$r_buff0_thd2~0_98) (= v_~x$r_buff1_thd2~0_53 v_~x$r_buff0_thd2~0_99)) InVars {P1Thread1of1ForFork1___VERIFIER_assert_~expression=v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_8, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_128, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_56, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_68, ~y~0=v_~y~0_37, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_99} OutVars{P1Thread1of1ForFork1___VERIFIER_assert_~expression=v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_8, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_128, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_56, ~__unbuffered_p1_EAX~0=v_~__unbuffered_p1_EAX~0_43, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_52, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_53, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_47, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_68, ~y~0=v_~y~0_37, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_98, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_91} AuxVars[] AssignedVars[~__unbuffered_p1_EAX~0, ~x$r_buff1_thd3~0, ~x$r_buff1_thd2~0, ~x$r_buff1_thd1~0, ~x$r_buff0_thd2~0, ~x$r_buff1_thd0~0] because there is no mapped edge [2019-12-07 14:27:51,173 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [765] [765] L767-->L767-2: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff0_used~0_In2122932390 256))) (.cse1 (= 0 (mod ~x$r_buff0_thd2~0_In2122932390 256)))) (or (and (not .cse0) (not .cse1) (= |P1Thread1of1ForFork1_#t~ite11_Out2122932390| 0)) (and (= ~x$w_buff0_used~0_In2122932390 |P1Thread1of1ForFork1_#t~ite11_Out2122932390|) (or .cse0 .cse1)))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In2122932390, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2122932390} OutVars{P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out2122932390|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In2122932390, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2122932390} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 14:27:51,173 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [757] [757] L768-->L768-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff0_used~0_In-953194932 256))) (.cse0 (= 0 (mod ~x$r_buff0_thd2~0_In-953194932 256))) (.cse3 (= 0 (mod ~x$r_buff1_thd2~0_In-953194932 256))) (.cse2 (= 0 (mod ~x$w_buff1_used~0_In-953194932 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P1Thread1of1ForFork1_#t~ite12_Out-953194932| ~x$w_buff1_used~0_In-953194932)) (and (= |P1Thread1of1ForFork1_#t~ite12_Out-953194932| 0) (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2)))))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-953194932, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-953194932, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-953194932, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-953194932} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-953194932, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-953194932, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out-953194932|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-953194932, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-953194932} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 14:27:51,174 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [778] [778] L769-->L770: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff0_used~0_In-782240392 256))) (.cse2 (= 0 (mod ~x$r_buff0_thd2~0_In-782240392 256))) (.cse1 (= ~x$r_buff0_thd2~0_In-782240392 ~x$r_buff0_thd2~0_Out-782240392))) (or (and .cse0 .cse1) (and (not .cse0) (= 0 ~x$r_buff0_thd2~0_Out-782240392) (not .cse2)) (and .cse2 .cse1))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-782240392, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-782240392} OutVars{P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out-782240392|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_Out-782240392, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-782240392} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13, ~x$r_buff0_thd2~0] because there is no mapped edge [2019-12-07 14:27:51,174 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L770-->L770-2: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff0_thd2~0_In-1115654997 256))) (.cse0 (= (mod ~x$w_buff0_used~0_In-1115654997 256) 0)) (.cse2 (= (mod ~x$r_buff1_thd2~0_In-1115654997 256) 0)) (.cse3 (= (mod ~x$w_buff1_used~0_In-1115654997 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork1_#t~ite14_Out-1115654997|)) (and (or .cse1 .cse0) (or .cse2 .cse3) (= ~x$r_buff1_thd2~0_In-1115654997 |P1Thread1of1ForFork1_#t~ite14_Out-1115654997|)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-1115654997, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-1115654997, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1115654997, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1115654997} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-1115654997, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In-1115654997, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1115654997, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out-1115654997|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1115654997} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 14:27:51,174 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [804] [804] L770-2-->P1EXIT: Formula: (and (= v_~x$r_buff1_thd2~0_105 |v_P1Thread1of1ForFork1_#t~ite14_38|) (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= v_~__unbuffered_cnt~0_76 (+ v_~__unbuffered_cnt~0_77 1)) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_77, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_38|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_105, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_76, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_37|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~x$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 14:27:51,175 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L789-2-->L789-4: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff1_used~0_In881150166 256))) (.cse0 (= 0 (mod ~x$r_buff1_thd3~0_In881150166 256)))) (or (and (not .cse0) (not .cse1) (= |P2Thread1of1ForFork2_#t~ite15_Out881150166| ~x$w_buff1~0_In881150166)) (and (= |P2Thread1of1ForFork2_#t~ite15_Out881150166| ~x~0_In881150166) (or .cse1 .cse0)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In881150166, ~x$w_buff1_used~0=~x$w_buff1_used~0_In881150166, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In881150166, ~x~0=~x~0_In881150166} OutVars{P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out881150166|, ~x$w_buff1~0=~x$w_buff1~0_In881150166, ~x$w_buff1_used~0=~x$w_buff1_used~0_In881150166, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In881150166, ~x~0=~x~0_In881150166} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 14:27:51,175 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L737-2-->L737-4: Formula: (let ((.cse0 (= (mod ~x$w_buff1_used~0_In-135909387 256) 0)) (.cse1 (= 0 (mod ~x$r_buff1_thd1~0_In-135909387 256)))) (or (and (= ~x~0_In-135909387 |P0Thread1of1ForFork0_#t~ite3_Out-135909387|) (or .cse0 .cse1)) (and (not .cse0) (not .cse1) (= ~x$w_buff1~0_In-135909387 |P0Thread1of1ForFork0_#t~ite3_Out-135909387|)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In-135909387, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-135909387, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-135909387, ~x~0=~x~0_In-135909387} OutVars{P0Thread1of1ForFork0_#t~ite3=|P0Thread1of1ForFork0_#t~ite3_Out-135909387|, ~x$w_buff1~0=~x$w_buff1~0_In-135909387, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-135909387, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-135909387, ~x~0=~x~0_In-135909387} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite3] because there is no mapped edge [2019-12-07 14:27:51,175 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [705] [705] L737-4-->L738: Formula: (= v_~x~0_33 |v_P0Thread1of1ForFork0_#t~ite3_8|) InVars {P0Thread1of1ForFork0_#t~ite3=|v_P0Thread1of1ForFork0_#t~ite3_8|} OutVars{P0Thread1of1ForFork0_#t~ite3=|v_P0Thread1of1ForFork0_#t~ite3_7|, P0Thread1of1ForFork0_#t~ite4=|v_P0Thread1of1ForFork0_#t~ite4_11|, ~x~0=v_~x~0_33} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite3, P0Thread1of1ForFork0_#t~ite4, ~x~0] because there is no mapped edge [2019-12-07 14:27:51,175 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [732] [732] L789-4-->L790: Formula: (= |v_P2Thread1of1ForFork2_#t~ite15_8| v_~x~0_58) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_8|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_7|, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_13|, ~x~0=v_~x~0_58} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, P2Thread1of1ForFork2_#t~ite16, ~x~0] because there is no mapped edge [2019-12-07 14:27:51,175 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [780] [780] L738-->L738-2: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff0_used~0_In-1104433153 256))) (.cse1 (= (mod ~x$r_buff0_thd1~0_In-1104433153 256) 0))) (or (and (not .cse0) (= 0 |P0Thread1of1ForFork0_#t~ite5_Out-1104433153|) (not .cse1)) (and (= ~x$w_buff0_used~0_In-1104433153 |P0Thread1of1ForFork0_#t~ite5_Out-1104433153|) (or .cse0 .cse1)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-1104433153, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1104433153} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out-1104433153|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-1104433153, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1104433153} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 14:27:51,175 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [782] [782] L790-->L790-2: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff0_thd3~0_In1225542173 256))) (.cse0 (= (mod ~x$w_buff0_used~0_In1225542173 256) 0))) (or (and (= ~x$w_buff0_used~0_In1225542173 |P2Thread1of1ForFork2_#t~ite17_Out1225542173|) (or .cse0 .cse1)) (and (not .cse1) (= 0 |P2Thread1of1ForFork2_#t~ite17_Out1225542173|) (not .cse0)))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1225542173, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1225542173} OutVars{~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1225542173, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out1225542173|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1225542173} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 14:27:51,176 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [759] [759] L791-->L791-2: Formula: (let ((.cse0 (= 0 (mod ~x$r_buff0_thd3~0_In-263723772 256))) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In-263723772 256))) (.cse3 (= 0 (mod ~x$w_buff1_used~0_In-263723772 256))) (.cse2 (= (mod ~x$r_buff1_thd3~0_In-263723772 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork2_#t~ite18_Out-263723772|)) (and (= |P2Thread1of1ForFork2_#t~ite18_Out-263723772| ~x$w_buff1_used~0_In-263723772) (or .cse0 .cse1) (or .cse3 .cse2)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-263723772, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-263723772, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-263723772, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-263723772} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-263723772, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-263723772, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-263723772, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out-263723772|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-263723772} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 14:27:51,176 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L792-->L792-2: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff0_used~0_In-1560041082 256))) (.cse1 (= (mod ~x$r_buff0_thd3~0_In-1560041082 256) 0))) (or (and (not .cse0) (= 0 |P2Thread1of1ForFork2_#t~ite19_Out-1560041082|) (not .cse1)) (and (or .cse0 .cse1) (= ~x$r_buff0_thd3~0_In-1560041082 |P2Thread1of1ForFork2_#t~ite19_Out-1560041082|)))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1560041082, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1560041082} OutVars{~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1560041082, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out-1560041082|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1560041082} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 14:27:51,176 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [763] [763] L793-->L793-2: Formula: (let ((.cse0 (= (mod ~x$w_buff0_used~0_In-1345021663 256) 0)) (.cse1 (= 0 (mod ~x$r_buff0_thd3~0_In-1345021663 256))) (.cse3 (= 0 (mod ~x$w_buff1_used~0_In-1345021663 256))) (.cse2 (= (mod ~x$r_buff1_thd3~0_In-1345021663 256) 0))) (or (and (= |P2Thread1of1ForFork2_#t~ite20_Out-1345021663| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (or .cse3 .cse2) (= |P2Thread1of1ForFork2_#t~ite20_Out-1345021663| ~x$r_buff1_thd3~0_In-1345021663)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-1345021663, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1345021663, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1345021663, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1345021663} OutVars{P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out-1345021663|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1345021663, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-1345021663, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-1345021663, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1345021663} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 14:27:51,176 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [794] [794] L793-2-->P2EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_71 1) v_~__unbuffered_cnt~0_70) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= v_~x$r_buff1_thd3~0_93 |v_P2Thread1of1ForFork2_#t~ite20_40|)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_40|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_71} OutVars{P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_39|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_93, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_70, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, ~x$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 14:27:51,177 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [762] [762] L739-->L739-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff1_used~0_In-1503264082 256))) (.cse0 (= (mod ~x$r_buff1_thd1~0_In-1503264082 256) 0)) (.cse3 (= 0 (mod ~x$r_buff0_thd1~0_In-1503264082 256))) (.cse2 (= 0 (mod ~x$w_buff0_used~0_In-1503264082 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P0Thread1of1ForFork0_#t~ite6_Out-1503264082|)) (and (= |P0Thread1of1ForFork0_#t~ite6_Out-1503264082| ~x$w_buff1_used~0_In-1503264082) (or .cse1 .cse0) (or .cse3 .cse2)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-1503264082, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1503264082, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-1503264082, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1503264082} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out-1503264082|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-1503264082, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1503264082, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-1503264082, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1503264082} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 14:27:51,177 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L740-->L740-2: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff0_used~0_In1589800303 256))) (.cse1 (= (mod ~x$r_buff0_thd1~0_In1589800303 256) 0))) (or (and (not .cse0) (not .cse1) (= |P0Thread1of1ForFork0_#t~ite7_Out1589800303| 0)) (and (= |P0Thread1of1ForFork0_#t~ite7_Out1589800303| ~x$r_buff0_thd1~0_In1589800303) (or .cse0 .cse1)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In1589800303, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1589800303} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In1589800303, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out1589800303|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1589800303} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7] because there is no mapped edge [2019-12-07 14:27:51,177 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [769] [769] L741-->L741-2: Formula: (let ((.cse3 (= (mod ~x$r_buff1_thd1~0_In-691863423 256) 0)) (.cse2 (= 0 (mod ~x$w_buff1_used~0_In-691863423 256))) (.cse1 (= (mod ~x$r_buff0_thd1~0_In-691863423 256) 0)) (.cse0 (= 0 (mod ~x$w_buff0_used~0_In-691863423 256)))) (or (and (= |P0Thread1of1ForFork0_#t~ite8_Out-691863423| ~x$r_buff1_thd1~0_In-691863423) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= |P0Thread1of1ForFork0_#t~ite8_Out-691863423| 0) (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0)))))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-691863423, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-691863423, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-691863423, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-691863423} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-691863423, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out-691863423|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-691863423, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-691863423, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-691863423} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 14:27:51,177 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [809] [809] L741-2-->P0EXIT: Formula: (and (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~x$r_buff1_thd1~0_125 |v_P0Thread1of1ForFork0_#t~ite8_56|) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_84 1) v_~__unbuffered_cnt~0_83)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_56|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_84} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_55|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_83, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_125} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, ~x$r_buff1_thd1~0] because there is no mapped edge [2019-12-07 14:27:51,177 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [716] [716] L820-->L822-2: Formula: (and (or (= 0 (mod v_~x$w_buff0_used~0_136 256)) (= (mod v_~x$r_buff0_thd0~0_90 256) 0)) (not (= 0 (mod v_~main$tmp_guard0~0_6 256)))) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_90, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_136} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_90, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_136} AuxVars[] AssignedVars[] because there is no mapped edge [2019-12-07 14:27:51,178 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] L822-2-->L822-5: Formula: (let ((.cse1 (= 0 (mod ~x$r_buff1_thd0~0_In221889007 256))) (.cse0 (= (mod ~x$w_buff1_used~0_In221889007 256) 0)) (.cse2 (= |ULTIMATE.start_main_#t~ite25_Out221889007| |ULTIMATE.start_main_#t~ite24_Out221889007|))) (or (and (or .cse0 .cse1) (= ~x~0_In221889007 |ULTIMATE.start_main_#t~ite24_Out221889007|) .cse2) (and (not .cse1) (not .cse0) .cse2 (= |ULTIMATE.start_main_#t~ite24_Out221889007| ~x$w_buff1~0_In221889007)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In221889007, ~x$w_buff1_used~0=~x$w_buff1_used~0_In221889007, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In221889007, ~x~0=~x~0_In221889007} OutVars{~x$w_buff1~0=~x$w_buff1~0_In221889007, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out221889007|, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out221889007|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In221889007, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In221889007, ~x~0=~x~0_In221889007} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25] because there is no mapped edge [2019-12-07 14:27:51,178 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [756] [756] L823-->L823-2: Formula: (let ((.cse0 (= 0 (mod ~x$r_buff0_thd0~0_In2125112783 256))) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In2125112783 256)))) (or (and (or .cse0 .cse1) (= ~x$w_buff0_used~0_In2125112783 |ULTIMATE.start_main_#t~ite26_Out2125112783|)) (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite26_Out2125112783|) (not .cse1)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In2125112783, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2125112783} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In2125112783, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out2125112783|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2125112783} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 14:27:51,178 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L824-->L824-2: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff0_used~0_In-1036793946 256))) (.cse1 (= (mod ~x$r_buff0_thd0~0_In-1036793946 256) 0)) (.cse3 (= (mod ~x$r_buff1_thd0~0_In-1036793946 256) 0)) (.cse2 (= (mod ~x$w_buff1_used~0_In-1036793946 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |ULTIMATE.start_main_#t~ite27_Out-1036793946| ~x$w_buff1_used~0_In-1036793946)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse3) (not .cse2))) (= |ULTIMATE.start_main_#t~ite27_Out-1036793946| 0)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1036793946, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1036793946, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-1036793946, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1036793946} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1036793946, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1036793946, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out-1036793946|, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-1036793946, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1036793946} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 14:27:51,178 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [772] [772] L825-->L825-2: Formula: (let ((.cse1 (= (mod ~x$r_buff0_thd0~0_In369584709 256) 0)) (.cse0 (= 0 (mod ~x$w_buff0_used~0_In369584709 256)))) (or (and (= |ULTIMATE.start_main_#t~ite28_Out369584709| ~x$r_buff0_thd0~0_In369584709) (or .cse0 .cse1)) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite28_Out369584709| 0) (not .cse0)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In369584709, ~x$w_buff0_used~0=~x$w_buff0_used~0_In369584709} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In369584709, ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out369584709|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In369584709} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 14:27:51,179 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L826-->L826-2: Formula: (let ((.cse3 (= 0 (mod ~x$r_buff1_thd0~0_In-1027296374 256))) (.cse2 (= 0 (mod ~x$w_buff1_used~0_In-1027296374 256))) (.cse1 (= 0 (mod ~x$r_buff0_thd0~0_In-1027296374 256))) (.cse0 (= 0 (mod ~x$w_buff0_used~0_In-1027296374 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~x$r_buff1_thd0~0_In-1027296374 |ULTIMATE.start_main_#t~ite29_Out-1027296374|)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse1) (not .cse0))) (= 0 |ULTIMATE.start_main_#t~ite29_Out-1027296374|)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1027296374, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1027296374, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-1027296374, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1027296374} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-1027296374, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-1027296374|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1027296374, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-1027296374, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1027296374} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 14:27:51,180 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [816] [816] L835-->L835-8: Formula: (let ((.cse1 (= 0 (mod ~weak$$choice2~0_In-2117757750 256)))) (or (and (= |ULTIMATE.start_main_#t~ite38_Out-2117757750| ~x$w_buff1~0_In-2117757750) (let ((.cse0 (= 0 (mod ~x$r_buff0_thd0~0_In-2117757750 256)))) (or (and (= (mod ~x$r_buff1_thd0~0_In-2117757750 256) 0) .cse0) (= (mod ~x$w_buff0_used~0_In-2117757750 256) 0) (and .cse0 (= (mod ~x$w_buff1_used~0_In-2117757750 256) 0)))) (= |ULTIMATE.start_main_#t~ite39_Out-2117757750| |ULTIMATE.start_main_#t~ite38_Out-2117757750|) .cse1) (and (= |ULTIMATE.start_main_#t~ite39_Out-2117757750| ~x$w_buff1~0_In-2117757750) (= |ULTIMATE.start_main_#t~ite38_In-2117757750| |ULTIMATE.start_main_#t~ite38_Out-2117757750|) (not .cse1)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-2117757750, ~x$w_buff1~0=~x$w_buff1~0_In-2117757750, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-2117757750, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_In-2117757750|, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-2117757750, ~weak$$choice2~0=~weak$$choice2~0_In-2117757750, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-2117757750} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-2117757750, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out-2117757750|, ~x$w_buff1~0=~x$w_buff1~0_In-2117757750, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-2117757750, ULTIMATE.start_main_#t~ite38=|ULTIMATE.start_main_#t~ite38_Out-2117757750|, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-2117757750, ~weak$$choice2~0=~weak$$choice2~0_In-2117757750, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-2117757750} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~ite38] because there is no mapped edge [2019-12-07 14:27:51,181 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [829] [829] L838-->L839-8: Formula: (and (= v_~x$r_buff1_thd0~0_306 |v_ULTIMATE.start_main_#t~ite51_81|) (= v_~x$r_buff0_thd0~0_381 v_~x$r_buff0_thd0~0_380) (= |v_ULTIMATE.start_main_#t~ite49_59| |v_ULTIMATE.start_main_#t~ite49_60|) (not (= (mod v_~weak$$choice2~0_116 256) 0)) (= |v_ULTIMATE.start_main_#t~ite50_66| |v_ULTIMATE.start_main_#t~ite50_65|)) InVars {ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_66|, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_381, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_60|, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_306, ~weak$$choice2~0=v_~weak$$choice2~0_116} OutVars{ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_65|, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_380, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_81|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_34|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_34|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_59|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_35|, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_306, ~weak$$choice2~0=v_~weak$$choice2~0_116} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite50, ~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite51, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 14:27:51,181 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [796] [796] L841-->L844-1: Formula: (and (= (mod v_~main$tmp_guard1~0_23 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|) (not (= (mod v_~x$flush_delayed~0_26 256) 0)) (= v_~x$flush_delayed~0_25 0) (= v_~x$mem_tmp~0_14 v_~x~0_102)) InVars {~x$flush_delayed~0=v_~x$flush_delayed~0_26, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_23, ~x$mem_tmp~0=v_~x$mem_tmp~0_14} OutVars{ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_23|, ~x$flush_delayed~0=v_~x$flush_delayed~0_25, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_23, ~x$mem_tmp~0=v_~x$mem_tmp~0_14, ~x~0=v_~x~0_102, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ~x$flush_delayed~0, ~x~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 14:27:51,181 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [783] [783] L844-1-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_10 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 14:27:51,233 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_67fafc63-f118-40bf-8219-8f2ad0b7af69/bin/uautomizer/witness.graphml [2019-12-07 14:27:51,234 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 14:27:51,235 INFO L168 Benchmark]: Toolchain (without parser) took 151658.04 ms. Allocated memory was 1.0 GB in the beginning and 7.2 GB in the end (delta: 6.2 GB). Free memory was 937.1 MB in the beginning and 6.2 GB in the end (delta: -5.3 GB). Peak memory consumption was 882.3 MB. Max. memory is 11.5 GB. [2019-12-07 14:27:51,235 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 958.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 14:27:51,235 INFO L168 Benchmark]: CACSL2BoogieTranslator took 393.49 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 102.8 MB). Free memory was 937.1 MB in the beginning and 1.1 GB in the end (delta: -128.1 MB). Peak memory consumption was 18.1 MB. Max. memory is 11.5 GB. [2019-12-07 14:27:51,235 INFO L168 Benchmark]: Boogie Procedure Inliner took 41.36 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 14:27:51,235 INFO L168 Benchmark]: Boogie Preprocessor took 25.62 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 14:27:51,236 INFO L168 Benchmark]: RCFGBuilder took 412.59 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 56.3 MB). Peak memory consumption was 56.3 MB. Max. memory is 11.5 GB. [2019-12-07 14:27:51,236 INFO L168 Benchmark]: TraceAbstraction took 150716.84 ms. Allocated memory was 1.1 GB in the beginning and 7.2 GB in the end (delta: 6.1 GB). Free memory was 1.0 GB in the beginning and 6.2 GB in the end (delta: -5.2 GB). Peak memory consumption was 808.3 MB. Max. memory is 11.5 GB. [2019-12-07 14:27:51,236 INFO L168 Benchmark]: Witness Printer took 64.17 ms. Allocated memory is still 7.2 GB. Free memory was 6.2 GB in the beginning and 6.2 GB in the end (delta: 37.7 MB). Peak memory consumption was 37.7 MB. Max. memory is 11.5 GB. [2019-12-07 14:27:51,238 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 958.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 393.49 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 102.8 MB). Free memory was 937.1 MB in the beginning and 1.1 GB in the end (delta: -128.1 MB). Peak memory consumption was 18.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 41.36 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 25.62 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 412.59 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 56.3 MB). Peak memory consumption was 56.3 MB. Max. memory is 11.5 GB. * TraceAbstraction took 150716.84 ms. Allocated memory was 1.1 GB in the beginning and 7.2 GB in the end (delta: 6.1 GB). Free memory was 1.0 GB in the beginning and 6.2 GB in the end (delta: -5.2 GB). Peak memory consumption was 808.3 MB. Max. memory is 11.5 GB. * Witness Printer took 64.17 ms. Allocated memory is still 7.2 GB. Free memory was 6.2 GB in the beginning and 6.2 GB in the end (delta: 37.7 MB). Peak memory consumption was 37.7 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.2s, 176 ProgramPointsBefore, 94 ProgramPointsAfterwards, 213 TransitionsBefore, 103 TransitionsAfterwards, 17074 CoEnabledTransitionPairs, 8 FixpointIterations, 33 TrivialSequentialCompositions, 46 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 36 ConcurrentYvCompositions, 32 ChoiceCompositions, 6126 VarBasedMoverChecksPositive, 240 VarBasedMoverChecksNegative, 65 SemBasedMoverChecksPositive, 246 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.8s, 0 MoverChecksTotal, 88380 CheckedPairsTotal, 115 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L812] FCALL, FORK 0 pthread_create(&t515, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0, z=0] [L814] FCALL, FORK 0 pthread_create(&t516, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0, z=0] [L751] 2 x$w_buff1 = x$w_buff0 [L752] 2 x$w_buff0 = 2 [L753] 2 x$w_buff1_used = x$w_buff0_used [L754] 2 x$w_buff0_used = (_Bool)1 [L766] EXPR 2 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=0, z=0] [L766] 2 x = x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) [L767] 2 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used [L768] 2 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used [L816] FCALL, FORK 0 pthread_create(&t517, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0, z=0] [L780] 3 y = 1 [L783] 3 __unbuffered_p2_EAX = y [L786] 3 __unbuffered_p2_EBX = z VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1, z=0] [L789] 3 x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd3 ? x$w_buff1 : x) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1, z=0] [L731] 1 z = 1 [L734] 1 x = 1 VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd3 ? x$w_buff1 : x=2, y=1, z=1] [L737] 1 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [__unbuffered_cnt=1, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, x$w_buff1_used && x$r_buff1_thd3 ? x$w_buff1 : x=2, y=1, z=1] [L790] 3 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : x$w_buff0_used [L791] 3 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd3 || x$w_buff1_used && x$r_buff1_thd3 ? (_Bool)0 : x$w_buff1_used [L792] 3 x$r_buff0_thd3 = x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : x$r_buff0_thd3 [L738] 1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used [L739] 1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used [L740] 1 x$r_buff0_thd1 = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 [L818] 0 main$tmp_guard0 = __unbuffered_cnt == 3 VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1, z=1] [L822] 0 x = x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) [L823] 0 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used [L824] 0 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used [L825] 0 x$r_buff0_thd0 = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 [L826] 0 x$r_buff1_thd0 = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 [L829] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L830] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L831] 0 x$flush_delayed = weak$$choice2 [L832] 0 x$mem_tmp = x VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1, z=1] [L833] EXPR 0 !x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1, z=1] [L833] 0 x = !x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff1) [L834] EXPR 0 weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1, z=1] [L834] 0 x$w_buff0 = weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff0)) [L835] 0 x$w_buff1 = weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff1 : x$w_buff1)) [L836] EXPR 0 weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1, z=1] [L836] 0 x$w_buff0_used = weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used)) [L837] EXPR 0 weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1, z=1] [L837] 0 x$w_buff1_used = weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L839] 0 x$r_buff1_thd0 = weak$$choice2 ? x$r_buff1_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff1_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L840] 0 main$tmp_guard1 = !(x == 2 && __unbuffered_p1_EAX == 0 && __unbuffered_p2_EAX == 1 && __unbuffered_p2_EBX == 0) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=1, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=1, z=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 167 locations, 2 error locations. Result: UNSAFE, OverallTime: 150.5s, OverallIterations: 26, TraceHistogramMax: 1, AutomataDifference: 27.3s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 4226 SDtfs, 6022 SDslu, 12986 SDs, 0 SdLazy, 6973 SolverSat, 468 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 4.8s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 328 GetRequests, 37 SyntacticMatches, 16 SemanticMatches, 275 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1245 ImplicationChecksByTransitivity, 3.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=253200occurred in iteration=7, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 100.4s AutomataMinimizationTime, 25 MinimizatonAttempts, 495359 StatesRemovedByMinimization, 23 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 2.3s InterpolantComputationTime, 1190 NumberOfCodeBlocks, 1190 NumberOfCodeBlocksAsserted, 26 NumberOfCheckSat, 1098 ConstructedInterpolants, 0 QuantifiedInterpolants, 342026 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 25 InterpolantComputations, 25 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...