./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/mix021_tso.oepc.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_8704b9a5-7749-4ccc-bd15-0b6492d0cc81/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_8704b9a5-7749-4ccc-bd15-0b6492d0cc81/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_8704b9a5-7749-4ccc-bd15-0b6492d0cc81/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_8704b9a5-7749-4ccc-bd15-0b6492d0cc81/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/mix021_tso.oepc.i -s /tmp/vcloud-vcloud-master/worker/run_dir_8704b9a5-7749-4ccc-bd15-0b6492d0cc81/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_8704b9a5-7749-4ccc-bd15-0b6492d0cc81/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e289faef583685090072dd44c55300091500c2c1 .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 17:34:25,290 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 17:34:25,291 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 17:34:25,298 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 17:34:25,299 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 17:34:25,299 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 17:34:25,300 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 17:34:25,302 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 17:34:25,303 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 17:34:25,303 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 17:34:25,304 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 17:34:25,305 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 17:34:25,305 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 17:34:25,306 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 17:34:25,306 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 17:34:25,307 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 17:34:25,308 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 17:34:25,308 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 17:34:25,310 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 17:34:25,311 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 17:34:25,312 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 17:34:25,313 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 17:34:25,314 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 17:34:25,314 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 17:34:25,316 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 17:34:25,316 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 17:34:25,316 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 17:34:25,316 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 17:34:25,317 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 17:34:25,317 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 17:34:25,317 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 17:34:25,318 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 17:34:25,318 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 17:34:25,319 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 17:34:25,319 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 17:34:25,319 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 17:34:25,320 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 17:34:25,320 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 17:34:25,320 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 17:34:25,320 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 17:34:25,321 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 17:34:25,321 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_8704b9a5-7749-4ccc-bd15-0b6492d0cc81/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 17:34:25,331 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 17:34:25,331 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 17:34:25,332 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 17:34:25,332 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 17:34:25,332 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 17:34:25,332 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 17:34:25,332 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 17:34:25,332 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 17:34:25,332 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 17:34:25,333 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 17:34:25,333 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 17:34:25,333 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 17:34:25,333 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 17:34:25,333 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 17:34:25,333 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 17:34:25,333 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 17:34:25,333 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 17:34:25,334 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 17:34:25,334 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 17:34:25,334 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 17:34:25,334 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 17:34:25,334 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 17:34:25,334 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 17:34:25,334 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 17:34:25,335 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 17:34:25,335 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 17:34:25,335 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 17:34:25,335 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 17:34:25,335 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 17:34:25,335 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_8704b9a5-7749-4ccc-bd15-0b6492d0cc81/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e289faef583685090072dd44c55300091500c2c1 [2019-12-07 17:34:25,434 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 17:34:25,442 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 17:34:25,444 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 17:34:25,445 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 17:34:25,445 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 17:34:25,445 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_8704b9a5-7749-4ccc-bd15-0b6492d0cc81/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/mix021_tso.oepc.i [2019-12-07 17:34:25,482 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_8704b9a5-7749-4ccc-bd15-0b6492d0cc81/bin/uautomizer/data/9ea29e6c7/5f824ddcca3e4a5f94020a18018f19aa/FLAG1e5f885b7 [2019-12-07 17:34:25,908 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 17:34:25,908 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_8704b9a5-7749-4ccc-bd15-0b6492d0cc81/sv-benchmarks/c/pthread-wmm/mix021_tso.oepc.i [2019-12-07 17:34:25,920 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_8704b9a5-7749-4ccc-bd15-0b6492d0cc81/bin/uautomizer/data/9ea29e6c7/5f824ddcca3e4a5f94020a18018f19aa/FLAG1e5f885b7 [2019-12-07 17:34:26,268 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_8704b9a5-7749-4ccc-bd15-0b6492d0cc81/bin/uautomizer/data/9ea29e6c7/5f824ddcca3e4a5f94020a18018f19aa [2019-12-07 17:34:26,271 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 17:34:26,273 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 17:34:26,274 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 17:34:26,274 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 17:34:26,277 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 17:34:26,278 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 05:34:26" (1/1) ... [2019-12-07 17:34:26,280 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7c19867b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:34:26, skipping insertion in model container [2019-12-07 17:34:26,280 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 05:34:26" (1/1) ... [2019-12-07 17:34:26,286 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 17:34:26,318 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 17:34:26,566 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 17:34:26,574 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 17:34:26,616 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 17:34:26,662 INFO L208 MainTranslator]: Completed translation [2019-12-07 17:34:26,663 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:34:26 WrapperNode [2019-12-07 17:34:26,663 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 17:34:26,663 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 17:34:26,663 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 17:34:26,663 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 17:34:26,669 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:34:26" (1/1) ... [2019-12-07 17:34:26,681 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:34:26" (1/1) ... [2019-12-07 17:34:26,702 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 17:34:26,702 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 17:34:26,702 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 17:34:26,702 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 17:34:26,708 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:34:26" (1/1) ... [2019-12-07 17:34:26,708 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:34:26" (1/1) ... [2019-12-07 17:34:26,712 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:34:26" (1/1) ... [2019-12-07 17:34:26,712 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:34:26" (1/1) ... [2019-12-07 17:34:26,719 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:34:26" (1/1) ... [2019-12-07 17:34:26,722 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:34:26" (1/1) ... [2019-12-07 17:34:26,725 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:34:26" (1/1) ... [2019-12-07 17:34:26,728 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 17:34:26,728 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 17:34:26,728 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 17:34:26,728 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 17:34:26,729 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:34:26" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_8704b9a5-7749-4ccc-bd15-0b6492d0cc81/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 17:34:26,770 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 17:34:26,770 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 17:34:26,770 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 17:34:26,770 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 17:34:26,770 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 17:34:26,770 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 17:34:26,770 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 17:34:26,770 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 17:34:26,771 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 17:34:26,771 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 17:34:26,771 INFO L130 BoogieDeclarations]: Found specification of procedure P3 [2019-12-07 17:34:26,771 INFO L138 BoogieDeclarations]: Found implementation of procedure P3 [2019-12-07 17:34:26,771 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 17:34:26,771 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 17:34:26,771 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 17:34:26,772 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 17:34:27,139 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 17:34:27,140 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 17:34:27,141 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:34:27 BoogieIcfgContainer [2019-12-07 17:34:27,141 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 17:34:27,141 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 17:34:27,141 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 17:34:27,143 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 17:34:27,143 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 05:34:26" (1/3) ... [2019-12-07 17:34:27,144 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@770934ae and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 05:34:27, skipping insertion in model container [2019-12-07 17:34:27,144 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:34:26" (2/3) ... [2019-12-07 17:34:27,144 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@770934ae and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 05:34:27, skipping insertion in model container [2019-12-07 17:34:27,144 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:34:27" (3/3) ... [2019-12-07 17:34:27,145 INFO L109 eAbstractionObserver]: Analyzing ICFG mix021_tso.oepc.i [2019-12-07 17:34:27,152 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 17:34:27,152 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 17:34:27,157 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 17:34:27,157 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 17:34:27,181 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,181 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,181 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,181 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,182 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,182 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,182 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,182 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,182 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork3_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,182 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork3_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,182 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,183 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,183 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,183 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,183 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,183 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,183 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,183 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,183 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,184 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,184 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,184 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,184 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,184 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,184 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,184 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,184 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,184 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,185 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,185 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,185 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,185 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,185 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,185 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,185 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,185 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork3_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,186 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,186 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,186 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,186 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,186 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,186 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,186 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,187 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,187 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,187 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,187 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,187 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,187 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,187 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,187 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,188 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,188 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,188 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,188 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,188 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,188 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,188 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,188 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,188 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,189 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,189 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,189 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,189 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,189 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,189 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,189 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,189 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,189 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,190 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,190 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,190 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,190 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,190 WARN L315 ript$VariableManager]: TermVariabe P3Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,190 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,190 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,190 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,191 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,191 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,191 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,191 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,191 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,191 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,191 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,191 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,191 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,191 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,192 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,192 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,192 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,192 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,192 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,192 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,192 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,192 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,192 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,193 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,193 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,193 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,193 WARN L315 ript$VariableManager]: TermVariabe |P3Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:34:27,205 INFO L249 AbstractCegarLoop]: Starting to check reachability of 7 error locations. [2019-12-07 17:34:27,217 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 17:34:27,217 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 17:34:27,218 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 17:34:27,218 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 17:34:27,218 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 17:34:27,218 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 17:34:27,218 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 17:34:27,218 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 17:34:27,228 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 192 places, 226 transitions [2019-12-07 17:34:27,230 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 192 places, 226 transitions [2019-12-07 17:34:27,287 INFO L134 PetriNetUnfolder]: 47/222 cut-off events. [2019-12-07 17:34:27,287 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 17:34:27,298 INFO L76 FinitePrefix]: Finished finitePrefix Result has 235 conditions, 222 events. 47/222 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 586 event pairs. 12/185 useless extension candidates. Maximal degree in co-relation 190. Up to 2 conditions per place. [2019-12-07 17:34:27,314 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 192 places, 226 transitions [2019-12-07 17:34:27,346 INFO L134 PetriNetUnfolder]: 47/222 cut-off events. [2019-12-07 17:34:27,346 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 17:34:27,351 INFO L76 FinitePrefix]: Finished finitePrefix Result has 235 conditions, 222 events. 47/222 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 9. Compared 586 event pairs. 12/185 useless extension candidates. Maximal degree in co-relation 190. Up to 2 conditions per place. [2019-12-07 17:34:27,367 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 18432 [2019-12-07 17:34:27,367 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 17:34:30,464 WARN L192 SmtUtils]: Spent 177.00 ms on a formula simplification. DAG size of input: 97 DAG size of output: 95 [2019-12-07 17:34:30,562 INFO L206 etLargeBlockEncoding]: Checked pairs total: 86545 [2019-12-07 17:34:30,562 INFO L214 etLargeBlockEncoding]: Total number of compositions: 127 [2019-12-07 17:34:30,565 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 97 places, 103 transitions [2019-12-07 17:35:11,888 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 199530 states. [2019-12-07 17:35:11,889 INFO L276 IsEmpty]: Start isEmpty. Operand 199530 states. [2019-12-07 17:35:11,893 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2019-12-07 17:35:11,894 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:35:11,894 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:35:11,894 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:35:11,898 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:35:11,898 INFO L82 PathProgramCache]: Analyzing trace with hash 1574015469, now seen corresponding path program 1 times [2019-12-07 17:35:11,904 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:35:11,904 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [249505395] [2019-12-07 17:35:11,904 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:35:11,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:35:12,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:35:12,058 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [249505395] [2019-12-07 17:35:12,058 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:35:12,059 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 17:35:12,059 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1455089921] [2019-12-07 17:35:12,062 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:35:12,062 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:35:12,071 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:35:12,072 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:35:12,073 INFO L87 Difference]: Start difference. First operand 199530 states. Second operand 3 states. [2019-12-07 17:35:13,336 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:35:13,336 INFO L93 Difference]: Finished difference Result 198930 states and 939730 transitions. [2019-12-07 17:35:13,337 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:35:13,338 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2019-12-07 17:35:13,339 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:35:14,227 INFO L225 Difference]: With dead ends: 198930 [2019-12-07 17:35:14,227 INFO L226 Difference]: Without dead ends: 194562 [2019-12-07 17:35:14,228 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:35:22,820 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 194562 states. [2019-12-07 17:35:25,471 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 194562 to 194562. [2019-12-07 17:35:25,473 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 194562 states. [2019-12-07 17:35:26,192 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 194562 states to 194562 states and 919710 transitions. [2019-12-07 17:35:26,193 INFO L78 Accepts]: Start accepts. Automaton has 194562 states and 919710 transitions. Word has length 7 [2019-12-07 17:35:26,193 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:35:26,194 INFO L462 AbstractCegarLoop]: Abstraction has 194562 states and 919710 transitions. [2019-12-07 17:35:26,194 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:35:26,194 INFO L276 IsEmpty]: Start isEmpty. Operand 194562 states and 919710 transitions. [2019-12-07 17:35:26,197 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 17:35:26,197 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:35:26,198 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:35:26,198 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:35:26,198 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:35:26,198 INFO L82 PathProgramCache]: Analyzing trace with hash 1968556431, now seen corresponding path program 1 times [2019-12-07 17:35:26,198 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:35:26,198 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1518999158] [2019-12-07 17:35:26,199 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:35:26,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:35:26,282 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:35:26,282 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1518999158] [2019-12-07 17:35:26,282 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:35:26,282 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:35:26,283 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2101943137] [2019-12-07 17:35:26,284 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:35:26,284 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:35:26,284 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:35:26,284 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:35:26,284 INFO L87 Difference]: Start difference. First operand 194562 states and 919710 transitions. Second operand 4 states. [2019-12-07 17:35:30,873 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:35:30,873 INFO L93 Difference]: Finished difference Result 312518 states and 1424536 transitions. [2019-12-07 17:35:30,874 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:35:30,874 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 17:35:30,874 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:35:31,871 INFO L225 Difference]: With dead ends: 312518 [2019-12-07 17:35:31,872 INFO L226 Difference]: Without dead ends: 312420 [2019-12-07 17:35:31,872 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:35:39,105 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 312420 states. [2019-12-07 17:35:43,616 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 312420 to 280564. [2019-12-07 17:35:43,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 280564 states. [2019-12-07 17:35:44,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280564 states to 280564 states and 1291349 transitions. [2019-12-07 17:35:44,644 INFO L78 Accepts]: Start accepts. Automaton has 280564 states and 1291349 transitions. Word has length 13 [2019-12-07 17:35:44,644 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:35:44,644 INFO L462 AbstractCegarLoop]: Abstraction has 280564 states and 1291349 transitions. [2019-12-07 17:35:44,644 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:35:44,644 INFO L276 IsEmpty]: Start isEmpty. Operand 280564 states and 1291349 transitions. [2019-12-07 17:35:44,651 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 17:35:44,651 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:35:44,651 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:35:44,652 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:35:44,652 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:35:44,652 INFO L82 PathProgramCache]: Analyzing trace with hash 381664219, now seen corresponding path program 1 times [2019-12-07 17:35:44,652 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:35:44,652 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [807338050] [2019-12-07 17:35:44,653 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:35:44,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:35:44,725 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:35:44,725 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [807338050] [2019-12-07 17:35:44,725 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:35:44,725 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:35:44,725 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1615926284] [2019-12-07 17:35:44,726 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:35:44,726 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:35:44,726 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:35:44,726 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:35:44,726 INFO L87 Difference]: Start difference. First operand 280564 states and 1291349 transitions. Second operand 4 states. [2019-12-07 17:35:50,236 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:35:50,236 INFO L93 Difference]: Finished difference Result 400666 states and 1806688 transitions. [2019-12-07 17:35:50,237 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:35:50,237 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-12-07 17:35:50,237 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:35:51,515 INFO L225 Difference]: With dead ends: 400666 [2019-12-07 17:35:51,515 INFO L226 Difference]: Without dead ends: 400540 [2019-12-07 17:35:51,516 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:36:00,078 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 400540 states. [2019-12-07 17:36:05,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 400540 to 335984. [2019-12-07 17:36:05,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 335984 states. [2019-12-07 17:36:07,422 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 335984 states to 335984 states and 1536425 transitions. [2019-12-07 17:36:07,423 INFO L78 Accepts]: Start accepts. Automaton has 335984 states and 1536425 transitions. Word has length 15 [2019-12-07 17:36:07,423 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:36:07,423 INFO L462 AbstractCegarLoop]: Abstraction has 335984 states and 1536425 transitions. [2019-12-07 17:36:07,423 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:36:07,423 INFO L276 IsEmpty]: Start isEmpty. Operand 335984 states and 1536425 transitions. [2019-12-07 17:36:07,427 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2019-12-07 17:36:07,427 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:36:07,427 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:36:07,427 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:36:07,427 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:36:07,427 INFO L82 PathProgramCache]: Analyzing trace with hash 1895054000, now seen corresponding path program 1 times [2019-12-07 17:36:07,427 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:36:07,428 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [901164342] [2019-12-07 17:36:07,428 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:36:07,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:36:07,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:36:07,475 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [901164342] [2019-12-07 17:36:07,475 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:36:07,475 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:36:07,476 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1190964727] [2019-12-07 17:36:07,476 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:36:07,476 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:36:07,476 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:36:07,476 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:36:07,476 INFO L87 Difference]: Start difference. First operand 335984 states and 1536425 transitions. Second operand 4 states. [2019-12-07 17:36:08,514 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:36:08,514 INFO L93 Difference]: Finished difference Result 211585 states and 862899 transitions. [2019-12-07 17:36:08,515 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 17:36:08,515 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2019-12-07 17:36:08,515 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:36:09,055 INFO L225 Difference]: With dead ends: 211585 [2019-12-07 17:36:09,055 INFO L226 Difference]: Without dead ends: 202721 [2019-12-07 17:36:09,055 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:36:16,416 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 202721 states. [2019-12-07 17:36:19,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 202721 to 202721. [2019-12-07 17:36:19,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 202721 states. [2019-12-07 17:36:19,970 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 202721 states to 202721 states and 829134 transitions. [2019-12-07 17:36:19,970 INFO L78 Accepts]: Start accepts. Automaton has 202721 states and 829134 transitions. Word has length 15 [2019-12-07 17:36:19,970 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:36:19,970 INFO L462 AbstractCegarLoop]: Abstraction has 202721 states and 829134 transitions. [2019-12-07 17:36:19,970 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:36:19,970 INFO L276 IsEmpty]: Start isEmpty. Operand 202721 states and 829134 transitions. [2019-12-07 17:36:19,974 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2019-12-07 17:36:19,974 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:36:19,974 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:36:19,974 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:36:19,974 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:36:19,974 INFO L82 PathProgramCache]: Analyzing trace with hash 1237573064, now seen corresponding path program 1 times [2019-12-07 17:36:19,975 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:36:19,975 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1192228419] [2019-12-07 17:36:19,975 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:36:19,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:36:20,026 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:36:20,026 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1192228419] [2019-12-07 17:36:20,027 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:36:20,027 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 17:36:20,027 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [848221569] [2019-12-07 17:36:20,027 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:36:20,027 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:36:20,028 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:36:20,028 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:36:20,028 INFO L87 Difference]: Start difference. First operand 202721 states and 829134 transitions. Second operand 5 states. [2019-12-07 17:36:20,216 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:36:20,216 INFO L93 Difference]: Finished difference Result 47448 states and 157887 transitions. [2019-12-07 17:36:20,217 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:36:20,217 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 16 [2019-12-07 17:36:20,217 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:36:20,282 INFO L225 Difference]: With dead ends: 47448 [2019-12-07 17:36:20,282 INFO L226 Difference]: Without dead ends: 42021 [2019-12-07 17:36:20,283 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:36:20,462 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42021 states. [2019-12-07 17:36:20,882 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42021 to 41766. [2019-12-07 17:36:20,882 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41766 states. [2019-12-07 17:36:20,959 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41766 states to 41766 states and 137050 transitions. [2019-12-07 17:36:20,959 INFO L78 Accepts]: Start accepts. Automaton has 41766 states and 137050 transitions. Word has length 16 [2019-12-07 17:36:20,959 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:36:20,960 INFO L462 AbstractCegarLoop]: Abstraction has 41766 states and 137050 transitions. [2019-12-07 17:36:20,960 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:36:20,960 INFO L276 IsEmpty]: Start isEmpty. Operand 41766 states and 137050 transitions. [2019-12-07 17:36:20,966 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2019-12-07 17:36:20,966 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:36:20,966 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:36:20,966 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:36:20,967 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:36:20,967 INFO L82 PathProgramCache]: Analyzing trace with hash -244633219, now seen corresponding path program 1 times [2019-12-07 17:36:20,967 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:36:20,967 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1001481646] [2019-12-07 17:36:20,967 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:36:20,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:36:21,021 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:36:21,022 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1001481646] [2019-12-07 17:36:21,022 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:36:21,022 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:36:21,022 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [375181980] [2019-12-07 17:36:21,023 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:36:21,023 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:36:21,023 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:36:21,023 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:36:21,023 INFO L87 Difference]: Start difference. First operand 41766 states and 137050 transitions. Second operand 5 states. [2019-12-07 17:36:21,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:36:21,526 INFO L93 Difference]: Finished difference Result 55658 states and 178699 transitions. [2019-12-07 17:36:21,527 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 17:36:21,527 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 21 [2019-12-07 17:36:21,527 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:36:21,611 INFO L225 Difference]: With dead ends: 55658 [2019-12-07 17:36:21,611 INFO L226 Difference]: Without dead ends: 55309 [2019-12-07 17:36:21,611 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 17:36:21,820 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55309 states. [2019-12-07 17:36:22,602 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55309 to 41581. [2019-12-07 17:36:22,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41581 states. [2019-12-07 17:36:22,677 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41581 states to 41581 states and 136155 transitions. [2019-12-07 17:36:22,678 INFO L78 Accepts]: Start accepts. Automaton has 41581 states and 136155 transitions. Word has length 21 [2019-12-07 17:36:22,678 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:36:22,678 INFO L462 AbstractCegarLoop]: Abstraction has 41581 states and 136155 transitions. [2019-12-07 17:36:22,678 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:36:22,678 INFO L276 IsEmpty]: Start isEmpty. Operand 41581 states and 136155 transitions. [2019-12-07 17:36:22,690 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-12-07 17:36:22,690 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:36:22,690 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:36:22,691 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:36:22,691 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:36:22,691 INFO L82 PathProgramCache]: Analyzing trace with hash 680964803, now seen corresponding path program 1 times [2019-12-07 17:36:22,691 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:36:22,691 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [151363264] [2019-12-07 17:36:22,691 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:36:22,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:36:22,749 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:36:22,749 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [151363264] [2019-12-07 17:36:22,750 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:36:22,750 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:36:22,750 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1377100324] [2019-12-07 17:36:22,750 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:36:22,750 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:36:22,750 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:36:22,751 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:36:22,751 INFO L87 Difference]: Start difference. First operand 41581 states and 136155 transitions. Second operand 6 states. [2019-12-07 17:36:22,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:36:22,832 INFO L93 Difference]: Finished difference Result 13161 states and 41940 transitions. [2019-12-07 17:36:22,832 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 17:36:22,832 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 28 [2019-12-07 17:36:22,832 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:36:22,847 INFO L225 Difference]: With dead ends: 13161 [2019-12-07 17:36:22,847 INFO L226 Difference]: Without dead ends: 12077 [2019-12-07 17:36:22,848 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2019-12-07 17:36:22,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12077 states. [2019-12-07 17:36:22,997 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12077 to 11853. [2019-12-07 17:36:22,997 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11853 states. [2019-12-07 17:36:23,019 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11853 states to 11853 states and 38018 transitions. [2019-12-07 17:36:23,019 INFO L78 Accepts]: Start accepts. Automaton has 11853 states and 38018 transitions. Word has length 28 [2019-12-07 17:36:23,019 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:36:23,019 INFO L462 AbstractCegarLoop]: Abstraction has 11853 states and 38018 transitions. [2019-12-07 17:36:23,020 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:36:23,020 INFO L276 IsEmpty]: Start isEmpty. Operand 11853 states and 38018 transitions. [2019-12-07 17:36:23,036 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2019-12-07 17:36:23,036 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:36:23,036 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:36:23,036 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:36:23,036 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:36:23,036 INFO L82 PathProgramCache]: Analyzing trace with hash -1672770928, now seen corresponding path program 1 times [2019-12-07 17:36:23,036 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:36:23,037 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1304470354] [2019-12-07 17:36:23,037 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:36:23,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:36:23,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:36:23,113 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1304470354] [2019-12-07 17:36:23,114 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:36:23,114 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 17:36:23,114 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1853410828] [2019-12-07 17:36:23,114 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 17:36:23,114 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:36:23,114 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 17:36:23,114 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:36:23,114 INFO L87 Difference]: Start difference. First operand 11853 states and 38018 transitions. Second operand 7 states. [2019-12-07 17:36:23,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:36:23,207 INFO L93 Difference]: Finished difference Result 10087 states and 33925 transitions. [2019-12-07 17:36:23,208 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 17:36:23,208 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 40 [2019-12-07 17:36:23,208 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:36:23,220 INFO L225 Difference]: With dead ends: 10087 [2019-12-07 17:36:23,220 INFO L226 Difference]: Without dead ends: 10006 [2019-12-07 17:36:23,221 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=65, Unknown=0, NotChecked=0, Total=110 [2019-12-07 17:36:23,258 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10006 states. [2019-12-07 17:36:23,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10006 to 9278. [2019-12-07 17:36:23,345 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9278 states. [2019-12-07 17:36:23,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9278 states to 9278 states and 31432 transitions. [2019-12-07 17:36:23,362 INFO L78 Accepts]: Start accepts. Automaton has 9278 states and 31432 transitions. Word has length 40 [2019-12-07 17:36:23,363 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:36:23,363 INFO L462 AbstractCegarLoop]: Abstraction has 9278 states and 31432 transitions. [2019-12-07 17:36:23,363 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 17:36:23,363 INFO L276 IsEmpty]: Start isEmpty. Operand 9278 states and 31432 transitions. [2019-12-07 17:36:23,377 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:36:23,377 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:36:23,377 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:36:23,377 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:36:23,378 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:36:23,378 INFO L82 PathProgramCache]: Analyzing trace with hash 1196827384, now seen corresponding path program 1 times [2019-12-07 17:36:23,378 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:36:23,378 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [110746948] [2019-12-07 17:36:23,378 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:36:23,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:36:23,421 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:36:23,421 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [110746948] [2019-12-07 17:36:23,421 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:36:23,421 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:36:23,422 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1501422520] [2019-12-07 17:36:23,422 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:36:23,422 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:36:23,422 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:36:23,422 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:36:23,422 INFO L87 Difference]: Start difference. First operand 9278 states and 31432 transitions. Second operand 3 states. [2019-12-07 17:36:23,469 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:36:23,469 INFO L93 Difference]: Finished difference Result 9290 states and 31447 transitions. [2019-12-07 17:36:23,469 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:36:23,469 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 67 [2019-12-07 17:36:23,470 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:36:23,481 INFO L225 Difference]: With dead ends: 9290 [2019-12-07 17:36:23,481 INFO L226 Difference]: Without dead ends: 9290 [2019-12-07 17:36:23,481 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:36:23,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9290 states. [2019-12-07 17:36:23,596 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9290 to 9285. [2019-12-07 17:36:23,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9285 states. [2019-12-07 17:36:23,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9285 states to 9285 states and 31441 transitions. [2019-12-07 17:36:23,613 INFO L78 Accepts]: Start accepts. Automaton has 9285 states and 31441 transitions. Word has length 67 [2019-12-07 17:36:23,613 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:36:23,614 INFO L462 AbstractCegarLoop]: Abstraction has 9285 states and 31441 transitions. [2019-12-07 17:36:23,614 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:36:23,614 INFO L276 IsEmpty]: Start isEmpty. Operand 9285 states and 31441 transitions. [2019-12-07 17:36:23,627 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:36:23,627 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:36:23,627 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:36:23,627 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:36:23,627 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:36:23,627 INFO L82 PathProgramCache]: Analyzing trace with hash 1012782721, now seen corresponding path program 1 times [2019-12-07 17:36:23,627 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:36:23,628 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1715406299] [2019-12-07 17:36:23,628 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:36:23,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:36:23,686 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:36:23,686 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1715406299] [2019-12-07 17:36:23,687 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:36:23,687 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:36:23,687 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [556154382] [2019-12-07 17:36:23,687 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:36:23,687 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:36:23,688 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:36:23,688 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:36:23,688 INFO L87 Difference]: Start difference. First operand 9285 states and 31441 transitions. Second operand 5 states. [2019-12-07 17:36:23,918 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:36:23,918 INFO L93 Difference]: Finished difference Result 14779 states and 49427 transitions. [2019-12-07 17:36:23,918 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 17:36:23,918 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 67 [2019-12-07 17:36:23,918 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:36:23,937 INFO L225 Difference]: With dead ends: 14779 [2019-12-07 17:36:23,938 INFO L226 Difference]: Without dead ends: 14779 [2019-12-07 17:36:23,938 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:36:23,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14779 states. [2019-12-07 17:36:24,097 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14779 to 10797. [2019-12-07 17:36:24,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10797 states. [2019-12-07 17:36:24,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10797 states to 10797 states and 36657 transitions. [2019-12-07 17:36:24,115 INFO L78 Accepts]: Start accepts. Automaton has 10797 states and 36657 transitions. Word has length 67 [2019-12-07 17:36:24,116 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:36:24,116 INFO L462 AbstractCegarLoop]: Abstraction has 10797 states and 36657 transitions. [2019-12-07 17:36:24,116 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:36:24,116 INFO L276 IsEmpty]: Start isEmpty. Operand 10797 states and 36657 transitions. [2019-12-07 17:36:24,130 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:36:24,130 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:36:24,130 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:36:24,130 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:36:24,131 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:36:24,131 INFO L82 PathProgramCache]: Analyzing trace with hash 1925623137, now seen corresponding path program 2 times [2019-12-07 17:36:24,131 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:36:24,131 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1450712818] [2019-12-07 17:36:24,131 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:36:24,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:36:24,200 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:36:24,201 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1450712818] [2019-12-07 17:36:24,201 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:36:24,201 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 17:36:24,201 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [932484737] [2019-12-07 17:36:24,201 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:36:24,201 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:36:24,201 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:36:24,202 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:36:24,202 INFO L87 Difference]: Start difference. First operand 10797 states and 36657 transitions. Second operand 6 states. [2019-12-07 17:36:24,500 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:36:24,500 INFO L93 Difference]: Finished difference Result 18221 states and 61439 transitions. [2019-12-07 17:36:24,501 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 17:36:24,501 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 67 [2019-12-07 17:36:24,501 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:36:24,524 INFO L225 Difference]: With dead ends: 18221 [2019-12-07 17:36:24,524 INFO L226 Difference]: Without dead ends: 18221 [2019-12-07 17:36:24,525 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2019-12-07 17:36:24,579 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18221 states. [2019-12-07 17:36:24,723 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18221 to 11801. [2019-12-07 17:36:24,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11801 states. [2019-12-07 17:36:24,747 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11801 states to 11801 states and 40143 transitions. [2019-12-07 17:36:24,747 INFO L78 Accepts]: Start accepts. Automaton has 11801 states and 40143 transitions. Word has length 67 [2019-12-07 17:36:24,747 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:36:24,748 INFO L462 AbstractCegarLoop]: Abstraction has 11801 states and 40143 transitions. [2019-12-07 17:36:24,748 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:36:24,748 INFO L276 IsEmpty]: Start isEmpty. Operand 11801 states and 40143 transitions. [2019-12-07 17:36:24,764 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:36:24,764 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:36:24,764 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:36:24,764 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:36:24,764 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:36:24,764 INFO L82 PathProgramCache]: Analyzing trace with hash 1157078727, now seen corresponding path program 3 times [2019-12-07 17:36:24,764 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:36:24,764 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [180878533] [2019-12-07 17:36:24,764 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:36:24,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:36:24,935 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:36:24,936 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [180878533] [2019-12-07 17:36:24,936 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:36:24,936 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 17:36:24,936 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1334596852] [2019-12-07 17:36:24,936 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:36:24,936 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:36:24,936 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:36:24,936 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:36:24,937 INFO L87 Difference]: Start difference. First operand 11801 states and 40143 transitions. Second operand 6 states. [2019-12-07 17:36:25,230 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:36:25,230 INFO L93 Difference]: Finished difference Result 16399 states and 54897 transitions. [2019-12-07 17:36:25,231 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 17:36:25,231 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 67 [2019-12-07 17:36:25,231 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:36:25,252 INFO L225 Difference]: With dead ends: 16399 [2019-12-07 17:36:25,252 INFO L226 Difference]: Without dead ends: 16399 [2019-12-07 17:36:25,252 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 6 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2019-12-07 17:36:25,302 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16399 states. [2019-12-07 17:36:25,444 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16399 to 13173. [2019-12-07 17:36:25,445 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13173 states. [2019-12-07 17:36:25,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13173 states to 13173 states and 44679 transitions. [2019-12-07 17:36:25,471 INFO L78 Accepts]: Start accepts. Automaton has 13173 states and 44679 transitions. Word has length 67 [2019-12-07 17:36:25,472 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:36:25,472 INFO L462 AbstractCegarLoop]: Abstraction has 13173 states and 44679 transitions. [2019-12-07 17:36:25,472 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:36:25,472 INFO L276 IsEmpty]: Start isEmpty. Operand 13173 states and 44679 transitions. [2019-12-07 17:36:25,486 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:36:25,487 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:36:25,487 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:36:25,487 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:36:25,487 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:36:25,487 INFO L82 PathProgramCache]: Analyzing trace with hash -153275837, now seen corresponding path program 4 times [2019-12-07 17:36:25,487 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:36:25,487 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1991162091] [2019-12-07 17:36:25,487 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:36:25,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:36:25,592 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:36:25,592 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1991162091] [2019-12-07 17:36:25,593 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:36:25,593 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 17:36:25,593 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1657917549] [2019-12-07 17:36:25,593 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 17:36:25,593 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:36:25,593 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 17:36:25,593 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:36:25,593 INFO L87 Difference]: Start difference. First operand 13173 states and 44679 transitions. Second operand 7 states. [2019-12-07 17:36:25,739 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:36:25,739 INFO L93 Difference]: Finished difference Result 26328 states and 84330 transitions. [2019-12-07 17:36:25,740 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 17:36:25,740 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 67 [2019-12-07 17:36:25,740 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:36:25,763 INFO L225 Difference]: With dead ends: 26328 [2019-12-07 17:36:25,763 INFO L226 Difference]: Without dead ends: 18533 [2019-12-07 17:36:25,763 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=40, Invalid=70, Unknown=0, NotChecked=0, Total=110 [2019-12-07 17:36:25,819 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18533 states. [2019-12-07 17:36:25,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18533 to 11948. [2019-12-07 17:36:25,960 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11948 states. [2019-12-07 17:36:25,981 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11948 states to 11948 states and 39934 transitions. [2019-12-07 17:36:25,982 INFO L78 Accepts]: Start accepts. Automaton has 11948 states and 39934 transitions. Word has length 67 [2019-12-07 17:36:25,982 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:36:25,982 INFO L462 AbstractCegarLoop]: Abstraction has 11948 states and 39934 transitions. [2019-12-07 17:36:25,982 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 17:36:25,982 INFO L276 IsEmpty]: Start isEmpty. Operand 11948 states and 39934 transitions. [2019-12-07 17:36:25,994 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:36:25,994 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:36:25,994 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:36:25,994 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:36:25,994 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:36:25,994 INFO L82 PathProgramCache]: Analyzing trace with hash 1227929671, now seen corresponding path program 5 times [2019-12-07 17:36:25,995 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:36:25,995 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [795364600] [2019-12-07 17:36:25,995 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:36:26,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:36:26,036 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:36:26,037 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [795364600] [2019-12-07 17:36:26,037 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:36:26,037 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:36:26,037 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1364738852] [2019-12-07 17:36:26,037 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:36:26,037 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:36:26,038 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:36:26,038 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:36:26,038 INFO L87 Difference]: Start difference. First operand 11948 states and 39934 transitions. Second operand 3 states. [2019-12-07 17:36:26,077 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:36:26,077 INFO L93 Difference]: Finished difference Result 10507 states and 34595 transitions. [2019-12-07 17:36:26,077 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:36:26,077 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 67 [2019-12-07 17:36:26,077 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:36:26,096 INFO L225 Difference]: With dead ends: 10507 [2019-12-07 17:36:26,096 INFO L226 Difference]: Without dead ends: 10507 [2019-12-07 17:36:26,096 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:36:26,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10507 states. [2019-12-07 17:36:26,248 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10507 to 10227. [2019-12-07 17:36:26,248 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10227 states. [2019-12-07 17:36:26,265 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10227 states to 10227 states and 33683 transitions. [2019-12-07 17:36:26,265 INFO L78 Accepts]: Start accepts. Automaton has 10227 states and 33683 transitions. Word has length 67 [2019-12-07 17:36:26,265 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:36:26,265 INFO L462 AbstractCegarLoop]: Abstraction has 10227 states and 33683 transitions. [2019-12-07 17:36:26,265 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:36:26,265 INFO L276 IsEmpty]: Start isEmpty. Operand 10227 states and 33683 transitions. [2019-12-07 17:36:26,275 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 17:36:26,275 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:36:26,276 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:36:26,276 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:36:26,276 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:36:26,276 INFO L82 PathProgramCache]: Analyzing trace with hash 1416707750, now seen corresponding path program 1 times [2019-12-07 17:36:26,276 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:36:26,276 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [280988633] [2019-12-07 17:36:26,276 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:36:26,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:36:26,344 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:36:26,344 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [280988633] [2019-12-07 17:36:26,344 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:36:26,344 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 17:36:26,344 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1683746821] [2019-12-07 17:36:26,345 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 17:36:26,345 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:36:26,345 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 17:36:26,345 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:36:26,345 INFO L87 Difference]: Start difference. First operand 10227 states and 33683 transitions. Second operand 7 states. [2019-12-07 17:36:26,632 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:36:26,632 INFO L93 Difference]: Finished difference Result 14317 states and 46777 transitions. [2019-12-07 17:36:26,632 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 17:36:26,632 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 68 [2019-12-07 17:36:26,633 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:36:26,650 INFO L225 Difference]: With dead ends: 14317 [2019-12-07 17:36:26,650 INFO L226 Difference]: Without dead ends: 14317 [2019-12-07 17:36:26,651 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 6 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=26, Invalid=64, Unknown=0, NotChecked=0, Total=90 [2019-12-07 17:36:26,699 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14317 states. [2019-12-07 17:36:26,809 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14317 to 10885. [2019-12-07 17:36:26,809 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10885 states. [2019-12-07 17:36:26,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10885 states to 10885 states and 35906 transitions. [2019-12-07 17:36:26,829 INFO L78 Accepts]: Start accepts. Automaton has 10885 states and 35906 transitions. Word has length 68 [2019-12-07 17:36:26,829 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:36:26,829 INFO L462 AbstractCegarLoop]: Abstraction has 10885 states and 35906 transitions. [2019-12-07 17:36:26,830 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 17:36:26,830 INFO L276 IsEmpty]: Start isEmpty. Operand 10885 states and 35906 transitions. [2019-12-07 17:36:26,841 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 17:36:26,841 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:36:26,841 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:36:26,841 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:36:26,841 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:36:26,841 INFO L82 PathProgramCache]: Analyzing trace with hash 1132876198, now seen corresponding path program 2 times [2019-12-07 17:36:26,842 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:36:26,842 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [469727322] [2019-12-07 17:36:26,842 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:36:26,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:36:26,901 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:36:26,901 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [469727322] [2019-12-07 17:36:26,901 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:36:26,901 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 17:36:26,902 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2047870100] [2019-12-07 17:36:26,902 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:36:26,902 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:36:26,902 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:36:26,902 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:36:26,902 INFO L87 Difference]: Start difference. First operand 10885 states and 35906 transitions. Second operand 6 states. [2019-12-07 17:36:27,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:36:27,190 INFO L93 Difference]: Finished difference Result 14829 states and 48262 transitions. [2019-12-07 17:36:27,190 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 17:36:27,190 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 68 [2019-12-07 17:36:27,190 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:36:27,208 INFO L225 Difference]: With dead ends: 14829 [2019-12-07 17:36:27,208 INFO L226 Difference]: Without dead ends: 14829 [2019-12-07 17:36:27,209 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2019-12-07 17:36:27,256 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14829 states. [2019-12-07 17:36:27,398 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14829 to 11316. [2019-12-07 17:36:27,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11316 states. [2019-12-07 17:36:27,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11316 states to 11316 states and 37078 transitions. [2019-12-07 17:36:27,419 INFO L78 Accepts]: Start accepts. Automaton has 11316 states and 37078 transitions. Word has length 68 [2019-12-07 17:36:27,419 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:36:27,420 INFO L462 AbstractCegarLoop]: Abstraction has 11316 states and 37078 transitions. [2019-12-07 17:36:27,420 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:36:27,420 INFO L276 IsEmpty]: Start isEmpty. Operand 11316 states and 37078 transitions. [2019-12-07 17:36:27,434 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 17:36:27,434 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:36:27,435 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:36:27,435 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:36:27,435 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:36:27,435 INFO L82 PathProgramCache]: Analyzing trace with hash 469346632, now seen corresponding path program 3 times [2019-12-07 17:36:27,435 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:36:27,435 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1115618278] [2019-12-07 17:36:27,435 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:36:27,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:36:27,549 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:36:27,550 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1115618278] [2019-12-07 17:36:27,550 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:36:27,550 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 17:36:27,550 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [315919571] [2019-12-07 17:36:27,550 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 17:36:27,550 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:36:27,551 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 17:36:27,551 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:36:27,551 INFO L87 Difference]: Start difference. First operand 11316 states and 37078 transitions. Second operand 7 states. [2019-12-07 17:36:27,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:36:27,900 INFO L93 Difference]: Finished difference Result 16427 states and 53320 transitions. [2019-12-07 17:36:27,900 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 17:36:27,900 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 68 [2019-12-07 17:36:27,901 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:36:27,920 INFO L225 Difference]: With dead ends: 16427 [2019-12-07 17:36:27,921 INFO L226 Difference]: Without dead ends: 16427 [2019-12-07 17:36:27,921 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 1 SyntacticMatches, 5 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=47, Invalid=109, Unknown=0, NotChecked=0, Total=156 [2019-12-07 17:36:27,972 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16427 states. [2019-12-07 17:36:28,104 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16427 to 11057. [2019-12-07 17:36:28,104 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11057 states. [2019-12-07 17:36:28,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11057 states to 11057 states and 36226 transitions. [2019-12-07 17:36:28,123 INFO L78 Accepts]: Start accepts. Automaton has 11057 states and 36226 transitions. Word has length 68 [2019-12-07 17:36:28,123 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:36:28,123 INFO L462 AbstractCegarLoop]: Abstraction has 11057 states and 36226 transitions. [2019-12-07 17:36:28,124 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 17:36:28,124 INFO L276 IsEmpty]: Start isEmpty. Operand 11057 states and 36226 transitions. [2019-12-07 17:36:28,134 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 17:36:28,134 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:36:28,134 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:36:28,134 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:36:28,135 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:36:28,135 INFO L82 PathProgramCache]: Analyzing trace with hash 597575012, now seen corresponding path program 4 times [2019-12-07 17:36:28,135 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:36:28,135 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [377816332] [2019-12-07 17:36:28,135 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:36:28,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:36:28,196 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:36:28,197 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [377816332] [2019-12-07 17:36:28,197 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:36:28,197 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 17:36:28,197 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1730960594] [2019-12-07 17:36:28,197 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 17:36:28,198 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:36:28,198 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 17:36:28,198 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:36:28,198 INFO L87 Difference]: Start difference. First operand 11057 states and 36226 transitions. Second operand 7 states. [2019-12-07 17:36:28,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:36:28,628 INFO L93 Difference]: Finished difference Result 16512 states and 53687 transitions. [2019-12-07 17:36:28,628 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2019-12-07 17:36:28,628 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 68 [2019-12-07 17:36:28,628 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:36:28,648 INFO L225 Difference]: With dead ends: 16512 [2019-12-07 17:36:28,648 INFO L226 Difference]: Without dead ends: 16512 [2019-12-07 17:36:28,648 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 9 SyntacticMatches, 2 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=55, Invalid=155, Unknown=0, NotChecked=0, Total=210 [2019-12-07 17:36:28,700 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16512 states. [2019-12-07 17:36:28,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16512 to 10700. [2019-12-07 17:36:28,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10700 states. [2019-12-07 17:36:28,853 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10700 states to 10700 states and 35136 transitions. [2019-12-07 17:36:28,853 INFO L78 Accepts]: Start accepts. Automaton has 10700 states and 35136 transitions. Word has length 68 [2019-12-07 17:36:28,853 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:36:28,853 INFO L462 AbstractCegarLoop]: Abstraction has 10700 states and 35136 transitions. [2019-12-07 17:36:28,853 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 17:36:28,853 INFO L276 IsEmpty]: Start isEmpty. Operand 10700 states and 35136 transitions. [2019-12-07 17:36:28,862 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 17:36:28,863 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:36:28,863 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:36:28,863 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:36:28,863 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:36:28,863 INFO L82 PathProgramCache]: Analyzing trace with hash -2095319094, now seen corresponding path program 5 times [2019-12-07 17:36:28,863 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:36:28,863 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [723100794] [2019-12-07 17:36:28,863 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:36:28,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:36:28,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:36:28,893 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [723100794] [2019-12-07 17:36:28,893 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:36:28,893 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:36:28,893 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [960336560] [2019-12-07 17:36:28,893 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:36:28,894 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:36:28,894 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:36:28,894 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:36:28,894 INFO L87 Difference]: Start difference. First operand 10700 states and 35136 transitions. Second operand 3 states. [2019-12-07 17:36:28,926 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:36:28,926 INFO L93 Difference]: Finished difference Result 9642 states and 31237 transitions. [2019-12-07 17:36:28,926 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:36:28,926 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 68 [2019-12-07 17:36:28,926 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:36:28,938 INFO L225 Difference]: With dead ends: 9642 [2019-12-07 17:36:28,938 INFO L226 Difference]: Without dead ends: 9642 [2019-12-07 17:36:28,939 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:36:28,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9642 states. [2019-12-07 17:36:29,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9642 to 9642. [2019-12-07 17:36:29,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9642 states. [2019-12-07 17:36:29,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9642 states to 9642 states and 31237 transitions. [2019-12-07 17:36:29,077 INFO L78 Accepts]: Start accepts. Automaton has 9642 states and 31237 transitions. Word has length 68 [2019-12-07 17:36:29,077 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:36:29,077 INFO L462 AbstractCegarLoop]: Abstraction has 9642 states and 31237 transitions. [2019-12-07 17:36:29,077 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:36:29,077 INFO L276 IsEmpty]: Start isEmpty. Operand 9642 states and 31237 transitions. [2019-12-07 17:36:29,086 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2019-12-07 17:36:29,086 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:36:29,086 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:36:29,086 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:36:29,086 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:36:29,086 INFO L82 PathProgramCache]: Analyzing trace with hash 1254968342, now seen corresponding path program 1 times [2019-12-07 17:36:29,086 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:36:29,086 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1317085976] [2019-12-07 17:36:29,086 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:36:29,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:36:29,119 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:36:29,119 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1317085976] [2019-12-07 17:36:29,119 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:36:29,119 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:36:29,119 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2097708173] [2019-12-07 17:36:29,119 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:36:29,120 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:36:29,120 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:36:29,120 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:36:29,120 INFO L87 Difference]: Start difference. First operand 9642 states and 31237 transitions. Second operand 3 states. [2019-12-07 17:36:29,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:36:29,167 INFO L93 Difference]: Finished difference Result 9642 states and 31236 transitions. [2019-12-07 17:36:29,167 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:36:29,167 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 69 [2019-12-07 17:36:29,167 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:36:29,178 INFO L225 Difference]: With dead ends: 9642 [2019-12-07 17:36:29,178 INFO L226 Difference]: Without dead ends: 9642 [2019-12-07 17:36:29,179 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:36:29,215 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9642 states. [2019-12-07 17:36:29,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9642 to 5873. [2019-12-07 17:36:29,284 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5873 states. [2019-12-07 17:36:29,295 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5873 states to 5873 states and 19141 transitions. [2019-12-07 17:36:29,295 INFO L78 Accepts]: Start accepts. Automaton has 5873 states and 19141 transitions. Word has length 69 [2019-12-07 17:36:29,295 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:36:29,295 INFO L462 AbstractCegarLoop]: Abstraction has 5873 states and 19141 transitions. [2019-12-07 17:36:29,295 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:36:29,295 INFO L276 IsEmpty]: Start isEmpty. Operand 5873 states and 19141 transitions. [2019-12-07 17:36:29,301 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-12-07 17:36:29,301 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:36:29,301 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:36:29,301 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:36:29,301 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:36:29,302 INFO L82 PathProgramCache]: Analyzing trace with hash -1196877625, now seen corresponding path program 1 times [2019-12-07 17:36:29,302 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:36:29,302 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [11861262] [2019-12-07 17:36:29,302 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:36:29,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:36:29,386 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:36:29,386 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [11861262] [2019-12-07 17:36:29,386 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:36:29,386 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:36:29,386 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1514439915] [2019-12-07 17:36:29,386 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:36:29,387 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:36:29,387 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:36:29,387 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:36:29,387 INFO L87 Difference]: Start difference. First operand 5873 states and 19141 transitions. Second operand 6 states. [2019-12-07 17:36:29,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:36:29,463 INFO L93 Difference]: Finished difference Result 9503 states and 29927 transitions. [2019-12-07 17:36:29,463 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 17:36:29,463 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 70 [2019-12-07 17:36:29,463 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:36:29,467 INFO L225 Difference]: With dead ends: 9503 [2019-12-07 17:36:29,467 INFO L226 Difference]: Without dead ends: 3402 [2019-12-07 17:36:29,468 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2019-12-07 17:36:29,485 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3402 states. [2019-12-07 17:36:29,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3402 to 2877. [2019-12-07 17:36:29,507 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2877 states. [2019-12-07 17:36:29,511 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2877 states to 2877 states and 8028 transitions. [2019-12-07 17:36:29,511 INFO L78 Accepts]: Start accepts. Automaton has 2877 states and 8028 transitions. Word has length 70 [2019-12-07 17:36:29,511 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:36:29,511 INFO L462 AbstractCegarLoop]: Abstraction has 2877 states and 8028 transitions. [2019-12-07 17:36:29,511 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:36:29,511 INFO L276 IsEmpty]: Start isEmpty. Operand 2877 states and 8028 transitions. [2019-12-07 17:36:29,513 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2019-12-07 17:36:29,513 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:36:29,513 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:36:29,513 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P2Err0ASSERT_VIOLATIONERROR_FUNCTION, P2Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr3INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:36:29,513 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:36:29,514 INFO L82 PathProgramCache]: Analyzing trace with hash -1078025367, now seen corresponding path program 2 times [2019-12-07 17:36:29,514 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:36:29,514 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1783627779] [2019-12-07 17:36:29,514 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:36:29,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:36:29,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 17:36:29,602 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 17:36:29,603 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 17:36:29,605 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [876] [876] ULTIMATE.startENTRY-->L833: Formula: (let ((.cse0 (store |v_#valid_73| 0 0))) (and (= 0 v_~y$r_buff1_thd2~0_156) (= 0 v_~__unbuffered_p3_EBX~0_23) (= v_~y$r_buff1_thd0~0_271 0) (= 0 v_~y$read_delayed_var~0.offset_7) (= v_~y$r_buff0_thd1~0_30 0) (= v_~y$r_buff0_thd4~0_83 0) (= v_~z~0_33 0) (= v_~main$tmp_guard0~0_39 0) (= (store |v_#memory_int_28| |v_ULTIMATE.start_main_~#t577~0.base_24| (store (select |v_#memory_int_28| |v_ULTIMATE.start_main_~#t577~0.base_24|) |v_ULTIMATE.start_main_~#t577~0.offset_18| 0)) |v_#memory_int_27|) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t577~0.base_24|)) (= v_~y~0_170 0) (= 0 v_~__unbuffered_p3_EAX~0_19) (= v_~x~0_63 0) (= v_~y$read_delayed~0_6 0) (= v_~y$r_buff0_thd0~0_357 0) (= v_~y$mem_tmp~0_18 0) (= 0 v_~y$flush_delayed~0_35) (= v_~__unbuffered_cnt~0_136 0) (= v_~y$w_buff1_used~0_387 0) (= 0 v_~y$r_buff1_thd3~0_144) (= 0 |v_#NULL.base_4|) (= |v_ULTIMATE.start_main_~#t577~0.offset_18| 0) (= v_~y$w_buff1~0_158 0) (< |v_#StackHeapBarrier_20| |v_ULTIMATE.start_main_~#t577~0.base_24|) (= v_~a~0_24 0) (= 0 v_~y$read_delayed_var~0.base_7) (= 0 v_~y$r_buff1_thd1~0_92) (< 0 |v_#StackHeapBarrier_20|) (= v_~y$r_buff0_thd2~0_97 0) (= 0 v_~y$w_buff0~0_171) (= |v_#NULL.offset_4| 0) (= (store |v_#length_32| |v_ULTIMATE.start_main_~#t577~0.base_24| 4) |v_#length_31|) (= v_~main$tmp_guard1~0_24 0) (= (store .cse0 |v_ULTIMATE.start_main_~#t577~0.base_24| 1) |v_#valid_71|) (= 0 v_~weak$$choice0~0_13) (= 0 v_~y$r_buff0_thd3~0_168) (= v_~weak$$choice2~0_110 0) (= 0 v_~__unbuffered_p2_EAX~0_98) (= 0 v_~y$r_buff1_thd4~0_147) (= v_~y$w_buff0_used~0_739 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_20|, #valid=|v_#valid_73|, #memory_int=|v_#memory_int_28|, #length=|v_#length_32|} OutVars{ULTIMATE.start_main_#t~nondet32=|v_ULTIMATE.start_main_#t~nondet32_21|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_33|, ULTIMATE.start_main_~#t579~0.base=|v_ULTIMATE.start_main_~#t579~0.base_20|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_30|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_28|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_33|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_284|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_37|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_41|, ~y$read_delayed~0=v_~y$read_delayed~0_6, ULTIMATE.start_main_~#t577~0.offset=|v_ULTIMATE.start_main_~#t577~0.offset_18|, ~a~0=v_~a~0_24, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_29|, ~y$mem_tmp~0=v_~y$mem_tmp~0_18, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_144, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_30, ~y$flush_delayed~0=v_~y$flush_delayed~0_35, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_19, #length=|v_#length_31|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_98, ULTIMATE.start_main_~#t580~0.base=|v_ULTIMATE.start_main_~#t580~0.base_20|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_10|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_54|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_28|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_42|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_25|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_55|, ~weak$$choice0~0=v_~weak$$choice0~0_13, #StackHeapBarrier=|v_#StackHeapBarrier_20|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_46|, ~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_147, ~y$w_buff1~0=v_~y$w_buff1~0_158, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_7, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_97, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_136, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_271, ~x~0=v_~x~0_63, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_21|, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_7, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_739, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_27|, ULTIMATE.start_main_~#t578~0.offset=|v_ULTIMATE.start_main_~#t578~0.offset_18|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_29|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_40|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_24, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_25|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_36|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_158|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_39|, ULTIMATE.start_main_~#t580~0.offset=|v_ULTIMATE.start_main_~#t580~0.offset_16|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_92, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_33|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_51|, ~y$w_buff0~0=v_~y$w_buff0~0_171, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_168, ~y~0=v_~y~0_170, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_9|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_9|, ULTIMATE.start_main_~#t577~0.base=|v_ULTIMATE.start_main_~#t577~0.base_24|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_46|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_52|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_39, ~__unbuffered_p3_EBX~0=v_~__unbuffered_p3_EBX~0_23, ULTIMATE.start_main_#t~ite53=|v_ULTIMATE.start_main_#t~ite53_32|, ULTIMATE.start_main_~#t578~0.base=|v_ULTIMATE.start_main_~#t578~0.base_23|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_103|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_156, ~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_83, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_154|, ULTIMATE.start_main_~#t579~0.offset=|v_ULTIMATE.start_main_~#t579~0.offset_17|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_357, #valid=|v_#valid_71|, #memory_int=|v_#memory_int_27|, ~z~0=v_~z~0_33, ~weak$$choice2~0=v_~weak$$choice2~0_110, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_387} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet32, ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_~#t579~0.base, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ~y$read_delayed~0, ULTIMATE.start_main_~#t577~0.offset, ~a~0, ULTIMATE.start_main_#t~ite52, ~y$mem_tmp~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, ~__unbuffered_p3_EAX~0, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_~#t580~0.base, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$r_buff1_thd4~0, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ULTIMATE.start_main_#t~nondet31, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_~#t578~0.offset, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_~#t580~0.offset, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite51, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_~#t577~0.base, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ~__unbuffered_p3_EBX~0, ULTIMATE.start_main_#t~ite53, ULTIMATE.start_main_~#t578~0.base, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ~y$r_buff0_thd4~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_~#t579~0.offset, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 17:36:29,606 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [843] [843] L833-1-->L835: Formula: (and (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t578~0.base_10| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t578~0.base_10|) |v_ULTIMATE.start_main_~#t578~0.offset_9| 1)) |v_#memory_int_15|) (= |v_#length_19| (store |v_#length_20| |v_ULTIMATE.start_main_~#t578~0.base_10| 4)) (= |v_#valid_42| (store |v_#valid_43| |v_ULTIMATE.start_main_~#t578~0.base_10| 1)) (< |v_#StackHeapBarrier_13| |v_ULTIMATE.start_main_~#t578~0.base_10|) (not (= 0 |v_ULTIMATE.start_main_~#t578~0.base_10|)) (= 0 (select |v_#valid_43| |v_ULTIMATE.start_main_~#t578~0.base_10|)) (= 0 |v_ULTIMATE.start_main_~#t578~0.offset_9|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_43|, #memory_int=|v_#memory_int_16|, #length=|v_#length_20|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_13|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_4|, ULTIMATE.start_main_~#t578~0.offset=|v_ULTIMATE.start_main_~#t578~0.offset_9|, #valid=|v_#valid_42|, #memory_int=|v_#memory_int_15|, #length=|v_#length_19|, ULTIMATE.start_main_~#t578~0.base=|v_ULTIMATE.start_main_~#t578~0.base_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t578~0.offset, #valid, #memory_int, #length, ULTIMATE.start_main_~#t578~0.base] because there is no mapped edge [2019-12-07 17:36:29,606 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [835] [835] L835-1-->L837: Formula: (and (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t579~0.base_11| 4)) (= |v_ULTIMATE.start_main_~#t579~0.offset_10| 0) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t579~0.base_11|) (= (select |v_#valid_39| |v_ULTIMATE.start_main_~#t579~0.base_11|) 0) (not (= |v_ULTIMATE.start_main_~#t579~0.base_11| 0)) (= |v_#memory_int_13| (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t579~0.base_11| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t579~0.base_11|) |v_ULTIMATE.start_main_~#t579~0.offset_10| 2))) (= (store |v_#valid_39| |v_ULTIMATE.start_main_~#t579~0.base_11| 1) |v_#valid_38|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_39|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_~#t579~0.base=|v_ULTIMATE.start_main_~#t579~0.base_11|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, ULTIMATE.start_main_~#t579~0.offset=|v_ULTIMATE.start_main_~#t579~0.offset_10|, #valid=|v_#valid_38|, #memory_int=|v_#memory_int_13|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t579~0.base, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_~#t579~0.offset, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 17:36:29,606 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] P2ENTRY-->L4-3: Formula: (and (= (ite (not (and (not (= 0 (mod v_~y$w_buff1_used~0_105 256))) (not (= 0 (mod v_~y$w_buff0_used~0_178 256))))) 1 0) |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|) (= v_~y$w_buff0~0_34 v_~y$w_buff1~0_39) (= |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6| v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_8) (not (= 0 v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_8)) (= 2 v_~y$w_buff0~0_33) (= v_P2Thread1of1ForFork0_~arg.base_6 |v_P2Thread1of1ForFork0_#in~arg.base_8|) (= v_~y$w_buff0_used~0_179 v_~y$w_buff1_used~0_105) (= v_~y$w_buff0_used~0_178 1) (= v_P2Thread1of1ForFork0_~arg.offset_6 |v_P2Thread1of1ForFork0_#in~arg.offset_8|)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_8|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_179, ~y$w_buff0~0=v_~y$w_buff0~0_34, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_8|} OutVars{P2Thread1of1ForFork0_~arg.base=v_P2Thread1of1ForFork0_~arg.base_6, P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_8|, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_178, ~y$w_buff1~0=v_~y$w_buff1~0_39, ~y$w_buff0~0=v_~y$w_buff0~0_33, P2Thread1of1ForFork0_~arg.offset=v_P2Thread1of1ForFork0_~arg.offset_6, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_8|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_8, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_105} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 17:36:29,607 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [844] [844] L837-1-->L839: Formula: (and (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t580~0.base_11| 4)) (= 0 (select |v_#valid_45| |v_ULTIMATE.start_main_~#t580~0.base_11|)) (< |v_#StackHeapBarrier_14| |v_ULTIMATE.start_main_~#t580~0.base_11|) (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t580~0.base_11| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t580~0.base_11|) |v_ULTIMATE.start_main_~#t580~0.offset_9| 3)) |v_#memory_int_17|) (not (= |v_ULTIMATE.start_main_~#t580~0.base_11| 0)) (= |v_#valid_44| (store |v_#valid_45| |v_ULTIMATE.start_main_~#t580~0.base_11| 1)) (= |v_ULTIMATE.start_main_~#t580~0.offset_9| 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_45|, #memory_int=|v_#memory_int_18|, #length=|v_#length_22|} OutVars{ULTIMATE.start_main_~#t580~0.offset=|v_ULTIMATE.start_main_~#t580~0.offset_9|, ULTIMATE.start_main_~#t580~0.base=|v_ULTIMATE.start_main_~#t580~0.base_11|, #StackHeapBarrier=|v_#StackHeapBarrier_14|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_4|, #valid=|v_#valid_44|, #memory_int=|v_#memory_int_17|, #length=|v_#length_21|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t580~0.offset, ULTIMATE.start_main_~#t580~0.base, ULTIMATE.start_main_#t~nondet23, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 17:36:29,608 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [838] [838] P0ENTRY-->P0EXIT: Formula: (and (= v_P0Thread1of1ForFork2_~arg.base_6 |v_P0Thread1of1ForFork2_#in~arg.base_8|) (= v_~a~0_10 1) (= (+ v_~__unbuffered_cnt~0_48 1) v_~__unbuffered_cnt~0_47) (= |v_P0Thread1of1ForFork2_#res.offset_3| 0) (= v_P0Thread1of1ForFork2_~arg.offset_6 |v_P0Thread1of1ForFork2_#in~arg.offset_8|) (= v_~x~0_43 1) (= 0 |v_P0Thread1of1ForFork2_#res.base_3|)) InVars {P0Thread1of1ForFork2_#in~arg.offset=|v_P0Thread1of1ForFork2_#in~arg.offset_8|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_48, P0Thread1of1ForFork2_#in~arg.base=|v_P0Thread1of1ForFork2_#in~arg.base_8|} OutVars{~a~0=v_~a~0_10, P0Thread1of1ForFork2_#in~arg.offset=|v_P0Thread1of1ForFork2_#in~arg.offset_8|, P0Thread1of1ForFork2_~arg.offset=v_P0Thread1of1ForFork2_~arg.offset_6, P0Thread1of1ForFork2_#res.offset=|v_P0Thread1of1ForFork2_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_47, P0Thread1of1ForFork2_#in~arg.base=|v_P0Thread1of1ForFork2_#in~arg.base_8|, P0Thread1of1ForFork2_#res.base=|v_P0Thread1of1ForFork2_#res.base_3|, ~x~0=v_~x~0_43, P0Thread1of1ForFork2_~arg.base=v_P0Thread1of1ForFork2_~arg.base_6} AuxVars[] AssignedVars[~a~0, P0Thread1of1ForFork2_~arg.offset, P0Thread1of1ForFork2_#res.offset, ~__unbuffered_cnt~0, P0Thread1of1ForFork2_#res.base, ~x~0, P0Thread1of1ForFork2_~arg.base] because there is no mapped edge [2019-12-07 17:36:29,608 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [800] [800] L757-2-->L757-5: Formula: (let ((.cse1 (= |P1Thread1of1ForFork3_#t~ite4_Out-1912422771| |P1Thread1of1ForFork3_#t~ite3_Out-1912422771|)) (.cse2 (= 0 (mod ~y$r_buff1_thd2~0_In-1912422771 256))) (.cse0 (= (mod ~y$w_buff1_used~0_In-1912422771 256) 0))) (or (and (not .cse0) (= |P1Thread1of1ForFork3_#t~ite3_Out-1912422771| ~y$w_buff1~0_In-1912422771) .cse1 (not .cse2)) (and (= |P1Thread1of1ForFork3_#t~ite3_Out-1912422771| ~y~0_In-1912422771) .cse1 (or .cse2 .cse0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1912422771, ~y$w_buff1~0=~y$w_buff1~0_In-1912422771, ~y~0=~y~0_In-1912422771, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1912422771} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1912422771, ~y$w_buff1~0=~y$w_buff1~0_In-1912422771, P1Thread1of1ForFork3_#t~ite4=|P1Thread1of1ForFork3_#t~ite4_Out-1912422771|, P1Thread1of1ForFork3_#t~ite3=|P1Thread1of1ForFork3_#t~ite3_Out-1912422771|, ~y~0=~y~0_In-1912422771, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1912422771} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite4, P1Thread1of1ForFork3_#t~ite3] because there is no mapped edge [2019-12-07 17:36:29,609 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [802] [802] L758-->L758-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd2~0_In787808769 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In787808769 256)))) (or (and (= 0 |P1Thread1of1ForFork3_#t~ite5_Out787808769|) (not .cse0) (not .cse1)) (and (or .cse0 .cse1) (= ~y$w_buff0_used~0_In787808769 |P1Thread1of1ForFork3_#t~ite5_Out787808769|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In787808769, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In787808769} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In787808769, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In787808769, P1Thread1of1ForFork3_#t~ite5=|P1Thread1of1ForFork3_#t~ite5_Out787808769|} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite5] because there is no mapped edge [2019-12-07 17:36:29,609 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [807] [807] L810-2-->L810-4: Formula: (let ((.cse0 (= (mod ~y$w_buff1_used~0_In-1991310628 256) 0)) (.cse1 (= (mod ~y$r_buff1_thd4~0_In-1991310628 256) 0))) (or (and (or .cse0 .cse1) (= |P3Thread1of1ForFork1_#t~ite15_Out-1991310628| ~y~0_In-1991310628)) (and (not .cse0) (= |P3Thread1of1ForFork1_#t~ite15_Out-1991310628| ~y$w_buff1~0_In-1991310628) (not .cse1)))) InVars {~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-1991310628, ~y$w_buff1~0=~y$w_buff1~0_In-1991310628, ~y~0=~y~0_In-1991310628, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1991310628} OutVars{~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-1991310628, ~y$w_buff1~0=~y$w_buff1~0_In-1991310628, P3Thread1of1ForFork1_#t~ite15=|P3Thread1of1ForFork1_#t~ite15_Out-1991310628|, ~y~0=~y~0_In-1991310628, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1991310628} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite15] because there is no mapped edge [2019-12-07 17:36:29,609 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [794] [794] L759-->L759-2: Formula: (let ((.cse0 (= (mod ~y$w_buff1_used~0_In1409964647 256) 0)) (.cse1 (= 0 (mod ~y$r_buff1_thd2~0_In1409964647 256))) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In1409964647 256))) (.cse3 (= 0 (mod ~y$r_buff0_thd2~0_In1409964647 256)))) (or (and (= |P1Thread1of1ForFork3_#t~ite6_Out1409964647| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (= |P1Thread1of1ForFork3_#t~ite6_Out1409964647| ~y$w_buff1_used~0_In1409964647) (or .cse2 .cse3)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1409964647, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1409964647, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1409964647, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1409964647} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1409964647, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1409964647, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1409964647, P1Thread1of1ForFork3_#t~ite6=|P1Thread1of1ForFork3_#t~ite6_Out1409964647|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1409964647} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite6] because there is no mapped edge [2019-12-07 17:36:29,609 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [731] [731] L810-4-->L811: Formula: (= v_~y~0_28 |v_P3Thread1of1ForFork1_#t~ite15_8|) InVars {P3Thread1of1ForFork1_#t~ite15=|v_P3Thread1of1ForFork1_#t~ite15_8|} OutVars{P3Thread1of1ForFork1_#t~ite16=|v_P3Thread1of1ForFork1_#t~ite16_13|, P3Thread1of1ForFork1_#t~ite15=|v_P3Thread1of1ForFork1_#t~ite15_7|, ~y~0=v_~y~0_28} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite16, P3Thread1of1ForFork1_#t~ite15, ~y~0] because there is no mapped edge [2019-12-07 17:36:29,609 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [793] [793] L811-->L811-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1097394295 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd4~0_In-1097394295 256)))) (or (and (or .cse0 .cse1) (= ~y$w_buff0_used~0_In-1097394295 |P3Thread1of1ForFork1_#t~ite17_Out-1097394295|)) (and (not .cse1) (= |P3Thread1of1ForFork1_#t~ite17_Out-1097394295| 0) (not .cse0)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-1097394295, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1097394295} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-1097394295, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1097394295, P3Thread1of1ForFork1_#t~ite17=|P3Thread1of1ForFork1_#t~ite17_Out-1097394295|} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite17] because there is no mapped edge [2019-12-07 17:36:29,610 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [806] [806] L812-->L812-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In-2109563336 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd4~0_In-2109563336 256))) (.cse3 (= 0 (mod ~y$w_buff1_used~0_In-2109563336 256))) (.cse2 (= 0 (mod ~y$r_buff1_thd4~0_In-2109563336 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P3Thread1of1ForFork1_#t~ite18_Out-2109563336| 0)) (and (or .cse0 .cse1) (= |P3Thread1of1ForFork1_#t~ite18_Out-2109563336| ~y$w_buff1_used~0_In-2109563336) (or .cse3 .cse2)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-2109563336, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-2109563336, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2109563336, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2109563336} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-2109563336, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-2109563336, P3Thread1of1ForFork1_#t~ite18=|P3Thread1of1ForFork1_#t~ite18_Out-2109563336|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2109563336, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2109563336} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite18] because there is no mapped edge [2019-12-07 17:36:29,611 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [796] [796] L813-->L813-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd4~0_In-610255116 256) 0)) (.cse1 (= (mod ~y$w_buff0_used~0_In-610255116 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 |P3Thread1of1ForFork1_#t~ite19_Out-610255116|)) (and (or .cse0 .cse1) (= |P3Thread1of1ForFork1_#t~ite19_Out-610255116| ~y$r_buff0_thd4~0_In-610255116)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-610255116, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-610255116} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-610255116, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-610255116, P3Thread1of1ForFork1_#t~ite19=|P3Thread1of1ForFork1_#t~ite19_Out-610255116|} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite19] because there is no mapped edge [2019-12-07 17:36:29,611 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L760-->L760-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd2~0_In-2042454840 256) 0)) (.cse1 (= (mod ~y$w_buff0_used~0_In-2042454840 256) 0))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork3_#t~ite7_Out-2042454840| ~y$r_buff0_thd2~0_In-2042454840)) (and (not .cse0) (= |P1Thread1of1ForFork3_#t~ite7_Out-2042454840| 0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-2042454840, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-2042454840} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-2042454840, P1Thread1of1ForFork3_#t~ite7=|P1Thread1of1ForFork3_#t~ite7_Out-2042454840|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-2042454840} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite7] because there is no mapped edge [2019-12-07 17:36:29,611 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [810] [810] L761-->L761-2: Formula: (let ((.cse2 (= 0 (mod ~y$r_buff1_thd2~0_In-2042684100 256))) (.cse3 (= 0 (mod ~y$w_buff1_used~0_In-2042684100 256))) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-2042684100 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In-2042684100 256)))) (or (and (or .cse0 .cse1) (= ~y$r_buff1_thd2~0_In-2042684100 |P1Thread1of1ForFork3_#t~ite8_Out-2042684100|) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= 0 |P1Thread1of1ForFork3_#t~ite8_Out-2042684100|)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-2042684100, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2042684100, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-2042684100, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2042684100} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-2042684100, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2042684100, P1Thread1of1ForFork3_#t~ite8=|P1Thread1of1ForFork3_#t~ite8_Out-2042684100|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-2042684100, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2042684100} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite8] because there is no mapped edge [2019-12-07 17:36:29,611 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [826] [826] L761-2-->P1EXIT: Formula: (and (= |v_P1Thread1of1ForFork3_#t~ite8_24| v_~y$r_buff1_thd2~0_109) (= (+ v_~__unbuffered_cnt~0_41 1) v_~__unbuffered_cnt~0_40) (= 0 |v_P1Thread1of1ForFork3_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork3_#res.base_3|)) InVars {P1Thread1of1ForFork3_#t~ite8=|v_P1Thread1of1ForFork3_#t~ite8_24|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_41} OutVars{P1Thread1of1ForFork3_#res.base=|v_P1Thread1of1ForFork3_#res.base_3|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_109, P1Thread1of1ForFork3_#t~ite8=|v_P1Thread1of1ForFork3_#t~ite8_23|, P1Thread1of1ForFork3_#res.offset=|v_P1Thread1of1ForFork3_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_40} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#res.base, ~y$r_buff1_thd2~0, P1Thread1of1ForFork3_#t~ite8, P1Thread1of1ForFork3_#res.offset, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 17:36:29,612 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [795] [795] L788-->L788-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In808346148 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In808346148 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite11_Out808346148| ~y$w_buff0_used~0_In808346148) (or .cse0 .cse1)) (and (not .cse0) (= |P2Thread1of1ForFork0_#t~ite11_Out808346148| 0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In808346148, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In808346148} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In808346148, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out808346148|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In808346148} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-12-07 17:36:29,612 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [813] [813] L789-->L789-2: Formula: (let ((.cse2 (= (mod ~y$w_buff1_used~0_In1769944165 256) 0)) (.cse3 (= 0 (mod ~y$r_buff1_thd3~0_In1769944165 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In1769944165 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In1769944165 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~y$w_buff1_used~0_In1769944165 |P2Thread1of1ForFork0_#t~ite12_Out1769944165|)) (and (= |P2Thread1of1ForFork0_#t~ite12_Out1769944165| 0) (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1769944165, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1769944165, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1769944165, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1769944165} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1769944165, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1769944165, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out1769944165|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1769944165, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1769944165} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-12-07 17:36:29,613 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [799] [799] L790-->L791: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In-1791116007 256))) (.cse2 (= ~y$r_buff0_thd3~0_In-1791116007 ~y$r_buff0_thd3~0_Out-1791116007)) (.cse1 (= (mod ~y$r_buff0_thd3~0_In-1791116007 256) 0))) (or (and (not .cse0) (not .cse1) (= ~y$r_buff0_thd3~0_Out-1791116007 0)) (and .cse0 .cse2) (and .cse2 .cse1))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1791116007, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1791116007} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1791116007, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out-1791116007, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out-1791116007|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-12-07 17:36:29,613 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [804] [804] L791-->L791-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff1_thd3~0_In1071999575 256))) (.cse0 (= 0 (mod ~y$w_buff1_used~0_In1071999575 256))) (.cse3 (= (mod ~y$r_buff0_thd3~0_In1071999575 256) 0)) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In1071999575 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork0_#t~ite14_Out1071999575|)) (and (or .cse1 .cse0) (= |P2Thread1of1ForFork0_#t~ite14_Out1071999575| ~y$r_buff1_thd3~0_In1071999575) (or .cse3 .cse2)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1071999575, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1071999575, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1071999575, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1071999575} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out1071999575|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1071999575, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1071999575, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1071999575, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1071999575} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-12-07 17:36:29,613 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [847] [847] L791-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= v_~__unbuffered_cnt~0_59 (+ v_~__unbuffered_cnt~0_60 1)) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0) (= v_~y$r_buff1_thd3~0_112 |v_P2Thread1of1ForFork0_#t~ite14_20|)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_20|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_60} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_19|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_112, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_59, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 17:36:29,613 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [792] [792] L814-->L814-2: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd4~0_In1184031156 256) 0)) (.cse0 (= (mod ~y$w_buff0_used~0_In1184031156 256) 0)) (.cse3 (= 0 (mod ~y$w_buff1_used~0_In1184031156 256))) (.cse2 (= (mod ~y$r_buff1_thd4~0_In1184031156 256) 0))) (or (and (= 0 |P3Thread1of1ForFork1_#t~ite20_Out1184031156|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~y$r_buff1_thd4~0_In1184031156 |P3Thread1of1ForFork1_#t~ite20_Out1184031156|) (or .cse1 .cse0) (or .cse3 .cse2)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1184031156, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In1184031156, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1184031156, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1184031156} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1184031156, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In1184031156, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1184031156, P3Thread1of1ForFork1_#t~ite20=|P3Thread1of1ForFork1_#t~ite20_Out1184031156|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1184031156} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite20] because there is no mapped edge [2019-12-07 17:36:29,613 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [846] [846] L814-2-->P3EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_54 1) v_~__unbuffered_cnt~0_53) (= |v_P3Thread1of1ForFork1_#res.offset_3| 0) (= |v_P3Thread1of1ForFork1_#t~ite20_28| v_~y$r_buff1_thd4~0_109) (= |v_P3Thread1of1ForFork1_#res.base_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_54, P3Thread1of1ForFork1_#t~ite20=|v_P3Thread1of1ForFork1_#t~ite20_28|} OutVars{~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_109, P3Thread1of1ForFork1_#res.base=|v_P3Thread1of1ForFork1_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_53, P3Thread1of1ForFork1_#res.offset=|v_P3Thread1of1ForFork1_#res.offset_3|, P3Thread1of1ForFork1_#t~ite20=|v_P3Thread1of1ForFork1_#t~ite20_27|} AuxVars[] AssignedVars[~y$r_buff1_thd4~0, P3Thread1of1ForFork1_#res.base, ~__unbuffered_cnt~0, P3Thread1of1ForFork1_#res.offset, P3Thread1of1ForFork1_#t~ite20] because there is no mapped edge [2019-12-07 17:36:29,614 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L843-->L845-2: Formula: (and (not (= (mod v_~main$tmp_guard0~0_8 256) 0)) (or (= (mod v_~y$w_buff0_used~0_216 256) 0) (= 0 (mod v_~y$r_buff0_thd0~0_104 256)))) InVars {~y$w_buff0_used~0=v_~y$w_buff0_used~0_216, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_104, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8} OutVars{~y$w_buff0_used~0=v_~y$w_buff0_used~0_216, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_104, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8} AuxVars[] AssignedVars[] because there is no mapped edge [2019-12-07 17:36:29,614 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L845-2-->L845-5: Formula: (let ((.cse1 (= (mod ~y$r_buff1_thd0~0_In-1663472441 256) 0)) (.cse0 (= |ULTIMATE.start_main_#t~ite26_Out-1663472441| |ULTIMATE.start_main_#t~ite25_Out-1663472441|)) (.cse2 (= (mod ~y$w_buff1_used~0_In-1663472441 256) 0))) (or (and (= ~y~0_In-1663472441 |ULTIMATE.start_main_#t~ite25_Out-1663472441|) .cse0 (or .cse1 .cse2)) (and (not .cse1) .cse0 (= ~y$w_buff1~0_In-1663472441 |ULTIMATE.start_main_#t~ite25_Out-1663472441|) (not .cse2)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-1663472441, ~y~0=~y~0_In-1663472441, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1663472441, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1663472441} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-1663472441, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out-1663472441|, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out-1663472441|, ~y~0=~y~0_In-1663472441, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1663472441, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1663472441} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 17:36:29,614 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [797] [797] L846-->L846-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In645563400 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In645563400 256)))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite27_Out645563400| ~y$w_buff0_used~0_In645563400)) (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite27_Out645563400| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In645563400, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In645563400} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In645563400, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In645563400, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out645563400|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 17:36:29,615 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [801] [801] L847-->L847-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff1_used~0_In-379748146 256))) (.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In-379748146 256))) (.cse2 (= (mod ~y$w_buff0_used~0_In-379748146 256) 0)) (.cse3 (= 0 (mod ~y$r_buff0_thd0~0_In-379748146 256)))) (or (and (= 0 |ULTIMATE.start_main_#t~ite28_Out-379748146|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (or .cse2 .cse3) (= ~y$w_buff1_used~0_In-379748146 |ULTIMATE.start_main_#t~ite28_Out-379748146|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-379748146, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-379748146, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-379748146, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-379748146} OutVars{ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out-379748146|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-379748146, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-379748146, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-379748146, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-379748146} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 17:36:29,615 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [812] [812] L848-->L848-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd0~0_In-1543914493 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1543914493 256)))) (or (and (= ~y$r_buff0_thd0~0_In-1543914493 |ULTIMATE.start_main_#t~ite29_Out-1543914493|) (or .cse0 .cse1)) (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite29_Out-1543914493|) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1543914493, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1543914493} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1543914493, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-1543914493|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1543914493} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 17:36:29,615 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [790] [790] L849-->L849-2: Formula: (let ((.cse2 (= 0 (mod ~y$w_buff0_used~0_In-1157193354 256))) (.cse3 (= (mod ~y$r_buff0_thd0~0_In-1157193354 256) 0)) (.cse1 (= (mod ~y$w_buff1_used~0_In-1157193354 256) 0)) (.cse0 (= (mod ~y$r_buff1_thd0~0_In-1157193354 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite30_Out-1157193354| ~y$r_buff1_thd0~0_In-1157193354) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= |ULTIMATE.start_main_#t~ite30_Out-1157193354| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1157193354, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1157193354, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1157193354, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1157193354} OutVars{ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out-1157193354|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1157193354, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1157193354, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1157193354, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1157193354} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30] because there is no mapped edge [2019-12-07 17:36:29,617 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [852] [852] L858-->L858-8: Formula: (let ((.cse1 (= 0 (mod ~weak$$choice2~0_In512810520 256)))) (or (and (let ((.cse0 (= (mod ~y$r_buff0_thd0~0_In512810520 256) 0))) (or (and (= (mod ~y$r_buff1_thd0~0_In512810520 256) 0) .cse0) (= 0 (mod ~y$w_buff0_used~0_In512810520 256)) (and (= (mod ~y$w_buff1_used~0_In512810520 256) 0) .cse0))) .cse1 (= |ULTIMATE.start_main_#t~ite40_Out512810520| |ULTIMATE.start_main_#t~ite39_Out512810520|) (= ~y$w_buff1~0_In512810520 |ULTIMATE.start_main_#t~ite39_Out512810520|)) (and (= |ULTIMATE.start_main_#t~ite40_Out512810520| ~y$w_buff1~0_In512810520) (not .cse1) (= |ULTIMATE.start_main_#t~ite39_In512810520| |ULTIMATE.start_main_#t~ite39_Out512810520|)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In512810520, ~y$w_buff0_used~0=~y$w_buff0_used~0_In512810520, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_In512810520|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In512810520, ~weak$$choice2~0=~weak$$choice2~0_In512810520, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In512810520, ~y$w_buff1_used~0=~y$w_buff1_used~0_In512810520} OutVars{ULTIMATE.start_main_#t~ite40=|ULTIMATE.start_main_#t~ite40_Out512810520|, ~y$w_buff1~0=~y$w_buff1~0_In512810520, ~y$w_buff0_used~0=~y$w_buff0_used~0_In512810520, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out512810520|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In512810520, ~weak$$choice2~0=~weak$$choice2~0_In512810520, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In512810520, ~y$w_buff1_used~0=~y$w_buff1_used~0_In512810520} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~ite39] because there is no mapped edge [2019-12-07 17:36:29,617 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [853] [853] L859-->L859-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In1183191206 256)))) (or (and (= |ULTIMATE.start_main_#t~ite42_In1183191206| |ULTIMATE.start_main_#t~ite42_Out1183191206|) (not .cse0) (= ~y$w_buff0_used~0_In1183191206 |ULTIMATE.start_main_#t~ite43_Out1183191206|)) (and .cse0 (= ~y$w_buff0_used~0_In1183191206 |ULTIMATE.start_main_#t~ite42_Out1183191206|) (= |ULTIMATE.start_main_#t~ite42_Out1183191206| |ULTIMATE.start_main_#t~ite43_Out1183191206|) (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In1183191206 256) 0))) (or (and (= 0 (mod ~y$w_buff1_used~0_In1183191206 256)) .cse1) (and (= 0 (mod ~y$r_buff1_thd0~0_In1183191206 256)) .cse1) (= 0 (mod ~y$w_buff0_used~0_In1183191206 256))))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1183191206, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1183191206, ~weak$$choice2~0=~weak$$choice2~0_In1183191206, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1183191206, ULTIMATE.start_main_#t~ite42=|ULTIMATE.start_main_#t~ite42_In1183191206|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1183191206} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1183191206, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1183191206, ULTIMATE.start_main_#t~ite43=|ULTIMATE.start_main_#t~ite43_Out1183191206|, ~weak$$choice2~0=~weak$$choice2~0_In1183191206, ULTIMATE.start_main_#t~ite42=|ULTIMATE.start_main_#t~ite42_Out1183191206|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1183191206, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1183191206} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 17:36:29,618 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [865] [865] L860-->L860-8: Formula: (let ((.cse5 (= (mod ~y$r_buff1_thd0~0_In-1567301564 256) 0)) (.cse0 (= 0 (mod ~weak$$choice2~0_In-1567301564 256))) (.cse1 (= |ULTIMATE.start_main_#t~ite46_Out-1567301564| |ULTIMATE.start_main_#t~ite45_Out-1567301564|)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In-1567301564 256))) (.cse4 (= (mod ~y$w_buff0_used~0_In-1567301564 256) 0)) (.cse3 (= (mod ~y$r_buff0_thd0~0_In-1567301564 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite44_In-1567301564| |ULTIMATE.start_main_#t~ite44_Out-1567301564|) (or (and (= ~y$w_buff1_used~0_In-1567301564 |ULTIMATE.start_main_#t~ite45_Out-1567301564|) .cse0 .cse1 (or (and .cse2 .cse3) .cse4 (and .cse3 .cse5))) (and (= |ULTIMATE.start_main_#t~ite45_Out-1567301564| |ULTIMATE.start_main_#t~ite45_In-1567301564|) (not .cse0) (= ~y$w_buff1_used~0_In-1567301564 |ULTIMATE.start_main_#t~ite46_Out-1567301564|)))) (let ((.cse6 (not .cse3))) (and (or (not .cse5) .cse6) .cse0 .cse1 (or (not .cse2) .cse6) (not .cse4) (= 0 |ULTIMATE.start_main_#t~ite44_Out-1567301564|) (= |ULTIMATE.start_main_#t~ite45_Out-1567301564| |ULTIMATE.start_main_#t~ite44_Out-1567301564|))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1567301564, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1567301564, ~weak$$choice2~0=~weak$$choice2~0_In-1567301564, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1567301564, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_In-1567301564|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1567301564, ULTIMATE.start_main_#t~ite44=|ULTIMATE.start_main_#t~ite44_In-1567301564|} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1567301564, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1567301564, ULTIMATE.start_main_#t~ite46=|ULTIMATE.start_main_#t~ite46_Out-1567301564|, ~weak$$choice2~0=~weak$$choice2~0_In-1567301564, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1567301564, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_Out-1567301564|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1567301564, ULTIMATE.start_main_#t~ite44=|ULTIMATE.start_main_#t~ite44_Out-1567301564|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44] because there is no mapped edge [2019-12-07 17:36:29,618 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [868] [868] L860-8-->L862: Formula: (and (not (= (mod v_~weak$$choice2~0_106 256) 0)) (= v_~y$w_buff1_used~0_383 |v_ULTIMATE.start_main_#t~ite46_36|) (= v_~y$r_buff0_thd0~0_352 v_~y$r_buff0_thd0~0_351)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_352, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_36|, ~weak$$choice2~0=v_~weak$$choice2~0_106} OutVars{~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_351, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_28|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_35|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_31|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_34|, ~weak$$choice2~0=v_~weak$$choice2~0_106, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_31|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_33|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_383} AuxVars[] AssignedVars[~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite48, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 17:36:29,618 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [832] [832] L864-->L4: Formula: (and (= 0 v_~y$flush_delayed~0_25) (= v_~y~0_116 v_~y$mem_tmp~0_11) (not (= (mod v_~y$flush_delayed~0_26 256) 0)) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5| (mod v_~main$tmp_guard1~0_15 256))) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_11, ~y$flush_delayed~0=v_~y$flush_delayed~0_26, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_15} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_11, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ~y$flush_delayed~0=v_~y$flush_delayed~0_25, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_15, ~y~0=v_~y~0_116, ULTIMATE.start_main_#t~ite53=|v_ULTIMATE.start_main_#t~ite53_23|, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ~y$flush_delayed~0, ~y~0, ULTIMATE.start_main_#t~ite53, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 17:36:29,619 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [841] [841] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 17:36:29,679 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 05:36:29 BasicIcfg [2019-12-07 17:36:29,679 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 17:36:29,679 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 17:36:29,679 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 17:36:29,679 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 17:36:29,680 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:34:27" (3/4) ... [2019-12-07 17:36:29,681 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 17:36:29,681 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [876] [876] ULTIMATE.startENTRY-->L833: Formula: (let ((.cse0 (store |v_#valid_73| 0 0))) (and (= 0 v_~y$r_buff1_thd2~0_156) (= 0 v_~__unbuffered_p3_EBX~0_23) (= v_~y$r_buff1_thd0~0_271 0) (= 0 v_~y$read_delayed_var~0.offset_7) (= v_~y$r_buff0_thd1~0_30 0) (= v_~y$r_buff0_thd4~0_83 0) (= v_~z~0_33 0) (= v_~main$tmp_guard0~0_39 0) (= (store |v_#memory_int_28| |v_ULTIMATE.start_main_~#t577~0.base_24| (store (select |v_#memory_int_28| |v_ULTIMATE.start_main_~#t577~0.base_24|) |v_ULTIMATE.start_main_~#t577~0.offset_18| 0)) |v_#memory_int_27|) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t577~0.base_24|)) (= v_~y~0_170 0) (= 0 v_~__unbuffered_p3_EAX~0_19) (= v_~x~0_63 0) (= v_~y$read_delayed~0_6 0) (= v_~y$r_buff0_thd0~0_357 0) (= v_~y$mem_tmp~0_18 0) (= 0 v_~y$flush_delayed~0_35) (= v_~__unbuffered_cnt~0_136 0) (= v_~y$w_buff1_used~0_387 0) (= 0 v_~y$r_buff1_thd3~0_144) (= 0 |v_#NULL.base_4|) (= |v_ULTIMATE.start_main_~#t577~0.offset_18| 0) (= v_~y$w_buff1~0_158 0) (< |v_#StackHeapBarrier_20| |v_ULTIMATE.start_main_~#t577~0.base_24|) (= v_~a~0_24 0) (= 0 v_~y$read_delayed_var~0.base_7) (= 0 v_~y$r_buff1_thd1~0_92) (< 0 |v_#StackHeapBarrier_20|) (= v_~y$r_buff0_thd2~0_97 0) (= 0 v_~y$w_buff0~0_171) (= |v_#NULL.offset_4| 0) (= (store |v_#length_32| |v_ULTIMATE.start_main_~#t577~0.base_24| 4) |v_#length_31|) (= v_~main$tmp_guard1~0_24 0) (= (store .cse0 |v_ULTIMATE.start_main_~#t577~0.base_24| 1) |v_#valid_71|) (= 0 v_~weak$$choice0~0_13) (= 0 v_~y$r_buff0_thd3~0_168) (= v_~weak$$choice2~0_110 0) (= 0 v_~__unbuffered_p2_EAX~0_98) (= 0 v_~y$r_buff1_thd4~0_147) (= v_~y$w_buff0_used~0_739 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_20|, #valid=|v_#valid_73|, #memory_int=|v_#memory_int_28|, #length=|v_#length_32|} OutVars{ULTIMATE.start_main_#t~nondet32=|v_ULTIMATE.start_main_#t~nondet32_21|, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_33|, ULTIMATE.start_main_~#t579~0.base=|v_ULTIMATE.start_main_~#t579~0.base_20|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_30|, #NULL.offset=|v_#NULL.offset_4|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_28|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_33|, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_284|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_37|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_41|, ~y$read_delayed~0=v_~y$read_delayed~0_6, ULTIMATE.start_main_~#t577~0.offset=|v_ULTIMATE.start_main_~#t577~0.offset_18|, ~a~0=v_~a~0_24, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_29|, ~y$mem_tmp~0=v_~y$mem_tmp~0_18, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_144, ~y$r_buff0_thd1~0=v_~y$r_buff0_thd1~0_30, ~y$flush_delayed~0=v_~y$flush_delayed~0_35, ~__unbuffered_p3_EAX~0=v_~__unbuffered_p3_EAX~0_19, #length=|v_#length_31|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_98, ULTIMATE.start_main_~#t580~0.base=|v_ULTIMATE.start_main_~#t580~0.base_20|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_10|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_54|, ULTIMATE.start_main_#t~nondet24=|v_ULTIMATE.start_main_#t~nondet24_28|, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_42|, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_25|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_55|, ~weak$$choice0~0=v_~weak$$choice0~0_13, #StackHeapBarrier=|v_#StackHeapBarrier_20|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_46|, ~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_147, ~y$w_buff1~0=v_~y$w_buff1~0_158, ~y$read_delayed_var~0.base=v_~y$read_delayed_var~0.base_7, ~y$r_buff0_thd2~0=v_~y$r_buff0_thd2~0_97, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_136, ~y$r_buff1_thd0~0=v_~y$r_buff1_thd0~0_271, ~x~0=v_~x~0_63, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_21|, ~y$read_delayed_var~0.offset=v_~y$read_delayed_var~0.offset_7, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_739, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_27|, ULTIMATE.start_main_~#t578~0.offset=|v_ULTIMATE.start_main_~#t578~0.offset_18|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_29|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_40|, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_24, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_25|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_36|, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_158|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_39|, ULTIMATE.start_main_~#t580~0.offset=|v_ULTIMATE.start_main_~#t580~0.offset_16|, ~y$r_buff1_thd1~0=v_~y$r_buff1_thd1~0_92, ULTIMATE.start_main_#t~ite30=|v_ULTIMATE.start_main_#t~ite30_33|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_51|, ~y$w_buff0~0=v_~y$w_buff0~0_171, ~y$r_buff0_thd3~0=v_~y$r_buff0_thd3~0_168, ~y~0=v_~y~0_170, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_9|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_9|, ULTIMATE.start_main_~#t577~0.base=|v_ULTIMATE.start_main_~#t577~0.base_24|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_46|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_52|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_39, ~__unbuffered_p3_EBX~0=v_~__unbuffered_p3_EBX~0_23, ULTIMATE.start_main_#t~ite53=|v_ULTIMATE.start_main_#t~ite53_32|, ULTIMATE.start_main_~#t578~0.base=|v_ULTIMATE.start_main_~#t578~0.base_23|, #NULL.base=|v_#NULL.base_4|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_103|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_156, ~y$r_buff0_thd4~0=v_~y$r_buff0_thd4~0_83, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_154|, ULTIMATE.start_main_~#t579~0.offset=|v_ULTIMATE.start_main_~#t579~0.offset_17|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_357, #valid=|v_#valid_71|, #memory_int=|v_#memory_int_27|, ~z~0=v_~z~0_33, ~weak$$choice2~0=v_~weak$$choice2~0_110, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_387} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet32, ULTIMATE.start_main_#t~ite28, ULTIMATE.start_main_~#t579~0.base, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ~y$read_delayed~0, ULTIMATE.start_main_~#t577~0.offset, ~a~0, ULTIMATE.start_main_#t~ite52, ~y$mem_tmp~0, ~y$r_buff1_thd3~0, ~y$r_buff0_thd1~0, ~y$flush_delayed~0, ~__unbuffered_p3_EAX~0, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_~#t580~0.base, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ULTIMATE.start_main_#t~nondet24, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite33, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~y$r_buff1_thd4~0, ~y$w_buff1~0, ~y$read_delayed_var~0.base, ~y$r_buff0_thd2~0, ~__unbuffered_cnt~0, ~y$r_buff1_thd0~0, ~x~0, ULTIMATE.start_main_#t~nondet31, ~y$read_delayed_var~0.offset, ~y$w_buff0_used~0, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_~#t578~0.offset, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_~#t580~0.offset, ~y$r_buff1_thd1~0, ULTIMATE.start_main_#t~ite30, ULTIMATE.start_main_#t~ite51, ~y$w_buff0~0, ~y$r_buff0_thd3~0, ~y~0, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_~#t577~0.base, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ~__unbuffered_p3_EBX~0, ULTIMATE.start_main_#t~ite53, ULTIMATE.start_main_~#t578~0.base, #NULL.base, ULTIMATE.start_main_#t~ite34, ~y$r_buff1_thd2~0, ~y$r_buff0_thd4~0, ULTIMATE.start_main_#t~ite41, ULTIMATE.start_main_~#t579~0.offset, ULTIMATE.start_main_#res, ~y$r_buff0_thd0~0, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 17:36:29,682 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [843] [843] L833-1-->L835: Formula: (and (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t578~0.base_10| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t578~0.base_10|) |v_ULTIMATE.start_main_~#t578~0.offset_9| 1)) |v_#memory_int_15|) (= |v_#length_19| (store |v_#length_20| |v_ULTIMATE.start_main_~#t578~0.base_10| 4)) (= |v_#valid_42| (store |v_#valid_43| |v_ULTIMATE.start_main_~#t578~0.base_10| 1)) (< |v_#StackHeapBarrier_13| |v_ULTIMATE.start_main_~#t578~0.base_10|) (not (= 0 |v_ULTIMATE.start_main_~#t578~0.base_10|)) (= 0 (select |v_#valid_43| |v_ULTIMATE.start_main_~#t578~0.base_10|)) (= 0 |v_ULTIMATE.start_main_~#t578~0.offset_9|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_13|, #valid=|v_#valid_43|, #memory_int=|v_#memory_int_16|, #length=|v_#length_20|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_13|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_4|, ULTIMATE.start_main_~#t578~0.offset=|v_ULTIMATE.start_main_~#t578~0.offset_9|, #valid=|v_#valid_42|, #memory_int=|v_#memory_int_15|, #length=|v_#length_19|, ULTIMATE.start_main_~#t578~0.base=|v_ULTIMATE.start_main_~#t578~0.base_10|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t578~0.offset, #valid, #memory_int, #length, ULTIMATE.start_main_~#t578~0.base] because there is no mapped edge [2019-12-07 17:36:29,682 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [835] [835] L835-1-->L837: Formula: (and (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t579~0.base_11| 4)) (= |v_ULTIMATE.start_main_~#t579~0.offset_10| 0) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t579~0.base_11|) (= (select |v_#valid_39| |v_ULTIMATE.start_main_~#t579~0.base_11|) 0) (not (= |v_ULTIMATE.start_main_~#t579~0.base_11| 0)) (= |v_#memory_int_13| (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t579~0.base_11| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t579~0.base_11|) |v_ULTIMATE.start_main_~#t579~0.offset_10| 2))) (= (store |v_#valid_39| |v_ULTIMATE.start_main_~#t579~0.base_11| 1) |v_#valid_38|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_39|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_~#t579~0.base=|v_ULTIMATE.start_main_~#t579~0.base_11|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, ULTIMATE.start_main_~#t579~0.offset=|v_ULTIMATE.start_main_~#t579~0.offset_10|, #valid=|v_#valid_38|, #memory_int=|v_#memory_int_13|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t579~0.base, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_~#t579~0.offset, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 17:36:29,682 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [758] [758] P2ENTRY-->L4-3: Formula: (and (= (ite (not (and (not (= 0 (mod v_~y$w_buff1_used~0_105 256))) (not (= 0 (mod v_~y$w_buff0_used~0_178 256))))) 1 0) |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|) (= v_~y$w_buff0~0_34 v_~y$w_buff1~0_39) (= |v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6| v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_8) (not (= 0 v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_8)) (= 2 v_~y$w_buff0~0_33) (= v_P2Thread1of1ForFork0_~arg.base_6 |v_P2Thread1of1ForFork0_#in~arg.base_8|) (= v_~y$w_buff0_used~0_179 v_~y$w_buff1_used~0_105) (= v_~y$w_buff0_used~0_178 1) (= v_P2Thread1of1ForFork0_~arg.offset_6 |v_P2Thread1of1ForFork0_#in~arg.offset_8|)) InVars {P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_8|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_179, ~y$w_buff0~0=v_~y$w_buff0~0_34, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_8|} OutVars{P2Thread1of1ForFork0_~arg.base=v_P2Thread1of1ForFork0_~arg.base_6, P2Thread1of1ForFork0_#in~arg.offset=|v_P2Thread1of1ForFork0_#in~arg.offset_8|, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P2Thread1of1ForFork0___VERIFIER_assert_#in~expression_6|, ~y$w_buff0_used~0=v_~y$w_buff0_used~0_178, ~y$w_buff1~0=v_~y$w_buff1~0_39, ~y$w_buff0~0=v_~y$w_buff0~0_33, P2Thread1of1ForFork0_~arg.offset=v_P2Thread1of1ForFork0_~arg.offset_6, P2Thread1of1ForFork0_#in~arg.base=|v_P2Thread1of1ForFork0_#in~arg.base_8|, P2Thread1of1ForFork0___VERIFIER_assert_~expression=v_P2Thread1of1ForFork0___VERIFIER_assert_~expression_8, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_105} AuxVars[] AssignedVars[P2Thread1of1ForFork0_~arg.base, P2Thread1of1ForFork0___VERIFIER_assert_#in~expression, ~y$w_buff0_used~0, ~y$w_buff1~0, ~y$w_buff0~0, P2Thread1of1ForFork0_~arg.offset, P2Thread1of1ForFork0___VERIFIER_assert_~expression, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 17:36:29,683 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [844] [844] L837-1-->L839: Formula: (and (= |v_#length_21| (store |v_#length_22| |v_ULTIMATE.start_main_~#t580~0.base_11| 4)) (= 0 (select |v_#valid_45| |v_ULTIMATE.start_main_~#t580~0.base_11|)) (< |v_#StackHeapBarrier_14| |v_ULTIMATE.start_main_~#t580~0.base_11|) (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t580~0.base_11| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t580~0.base_11|) |v_ULTIMATE.start_main_~#t580~0.offset_9| 3)) |v_#memory_int_17|) (not (= |v_ULTIMATE.start_main_~#t580~0.base_11| 0)) (= |v_#valid_44| (store |v_#valid_45| |v_ULTIMATE.start_main_~#t580~0.base_11| 1)) (= |v_ULTIMATE.start_main_~#t580~0.offset_9| 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_14|, #valid=|v_#valid_45|, #memory_int=|v_#memory_int_18|, #length=|v_#length_22|} OutVars{ULTIMATE.start_main_~#t580~0.offset=|v_ULTIMATE.start_main_~#t580~0.offset_9|, ULTIMATE.start_main_~#t580~0.base=|v_ULTIMATE.start_main_~#t580~0.base_11|, #StackHeapBarrier=|v_#StackHeapBarrier_14|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_4|, #valid=|v_#valid_44|, #memory_int=|v_#memory_int_17|, #length=|v_#length_21|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t580~0.offset, ULTIMATE.start_main_~#t580~0.base, ULTIMATE.start_main_#t~nondet23, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 17:36:29,684 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [838] [838] P0ENTRY-->P0EXIT: Formula: (and (= v_P0Thread1of1ForFork2_~arg.base_6 |v_P0Thread1of1ForFork2_#in~arg.base_8|) (= v_~a~0_10 1) (= (+ v_~__unbuffered_cnt~0_48 1) v_~__unbuffered_cnt~0_47) (= |v_P0Thread1of1ForFork2_#res.offset_3| 0) (= v_P0Thread1of1ForFork2_~arg.offset_6 |v_P0Thread1of1ForFork2_#in~arg.offset_8|) (= v_~x~0_43 1) (= 0 |v_P0Thread1of1ForFork2_#res.base_3|)) InVars {P0Thread1of1ForFork2_#in~arg.offset=|v_P0Thread1of1ForFork2_#in~arg.offset_8|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_48, P0Thread1of1ForFork2_#in~arg.base=|v_P0Thread1of1ForFork2_#in~arg.base_8|} OutVars{~a~0=v_~a~0_10, P0Thread1of1ForFork2_#in~arg.offset=|v_P0Thread1of1ForFork2_#in~arg.offset_8|, P0Thread1of1ForFork2_~arg.offset=v_P0Thread1of1ForFork2_~arg.offset_6, P0Thread1of1ForFork2_#res.offset=|v_P0Thread1of1ForFork2_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_47, P0Thread1of1ForFork2_#in~arg.base=|v_P0Thread1of1ForFork2_#in~arg.base_8|, P0Thread1of1ForFork2_#res.base=|v_P0Thread1of1ForFork2_#res.base_3|, ~x~0=v_~x~0_43, P0Thread1of1ForFork2_~arg.base=v_P0Thread1of1ForFork2_~arg.base_6} AuxVars[] AssignedVars[~a~0, P0Thread1of1ForFork2_~arg.offset, P0Thread1of1ForFork2_#res.offset, ~__unbuffered_cnt~0, P0Thread1of1ForFork2_#res.base, ~x~0, P0Thread1of1ForFork2_~arg.base] because there is no mapped edge [2019-12-07 17:36:29,684 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [800] [800] L757-2-->L757-5: Formula: (let ((.cse1 (= |P1Thread1of1ForFork3_#t~ite4_Out-1912422771| |P1Thread1of1ForFork3_#t~ite3_Out-1912422771|)) (.cse2 (= 0 (mod ~y$r_buff1_thd2~0_In-1912422771 256))) (.cse0 (= (mod ~y$w_buff1_used~0_In-1912422771 256) 0))) (or (and (not .cse0) (= |P1Thread1of1ForFork3_#t~ite3_Out-1912422771| ~y$w_buff1~0_In-1912422771) .cse1 (not .cse2)) (and (= |P1Thread1of1ForFork3_#t~ite3_Out-1912422771| ~y~0_In-1912422771) .cse1 (or .cse2 .cse0)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1912422771, ~y$w_buff1~0=~y$w_buff1~0_In-1912422771, ~y~0=~y~0_In-1912422771, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1912422771} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-1912422771, ~y$w_buff1~0=~y$w_buff1~0_In-1912422771, P1Thread1of1ForFork3_#t~ite4=|P1Thread1of1ForFork3_#t~ite4_Out-1912422771|, P1Thread1of1ForFork3_#t~ite3=|P1Thread1of1ForFork3_#t~ite3_Out-1912422771|, ~y~0=~y~0_In-1912422771, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1912422771} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite4, P1Thread1of1ForFork3_#t~ite3] because there is no mapped edge [2019-12-07 17:36:29,684 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [802] [802] L758-->L758-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd2~0_In787808769 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In787808769 256)))) (or (and (= 0 |P1Thread1of1ForFork3_#t~ite5_Out787808769|) (not .cse0) (not .cse1)) (and (or .cse0 .cse1) (= ~y$w_buff0_used~0_In787808769 |P1Thread1of1ForFork3_#t~ite5_Out787808769|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In787808769, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In787808769} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In787808769, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In787808769, P1Thread1of1ForFork3_#t~ite5=|P1Thread1of1ForFork3_#t~ite5_Out787808769|} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite5] because there is no mapped edge [2019-12-07 17:36:29,685 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [807] [807] L810-2-->L810-4: Formula: (let ((.cse0 (= (mod ~y$w_buff1_used~0_In-1991310628 256) 0)) (.cse1 (= (mod ~y$r_buff1_thd4~0_In-1991310628 256) 0))) (or (and (or .cse0 .cse1) (= |P3Thread1of1ForFork1_#t~ite15_Out-1991310628| ~y~0_In-1991310628)) (and (not .cse0) (= |P3Thread1of1ForFork1_#t~ite15_Out-1991310628| ~y$w_buff1~0_In-1991310628) (not .cse1)))) InVars {~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-1991310628, ~y$w_buff1~0=~y$w_buff1~0_In-1991310628, ~y~0=~y~0_In-1991310628, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1991310628} OutVars{~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-1991310628, ~y$w_buff1~0=~y$w_buff1~0_In-1991310628, P3Thread1of1ForFork1_#t~ite15=|P3Thread1of1ForFork1_#t~ite15_Out-1991310628|, ~y~0=~y~0_In-1991310628, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1991310628} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite15] because there is no mapped edge [2019-12-07 17:36:29,685 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [794] [794] L759-->L759-2: Formula: (let ((.cse0 (= (mod ~y$w_buff1_used~0_In1409964647 256) 0)) (.cse1 (= 0 (mod ~y$r_buff1_thd2~0_In1409964647 256))) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In1409964647 256))) (.cse3 (= 0 (mod ~y$r_buff0_thd2~0_In1409964647 256)))) (or (and (= |P1Thread1of1ForFork3_#t~ite6_Out1409964647| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (= |P1Thread1of1ForFork3_#t~ite6_Out1409964647| ~y$w_buff1_used~0_In1409964647) (or .cse2 .cse3)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1409964647, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1409964647, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1409964647, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1409964647} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In1409964647, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1409964647, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In1409964647, P1Thread1of1ForFork3_#t~ite6=|P1Thread1of1ForFork3_#t~ite6_Out1409964647|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1409964647} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite6] because there is no mapped edge [2019-12-07 17:36:29,685 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [731] [731] L810-4-->L811: Formula: (= v_~y~0_28 |v_P3Thread1of1ForFork1_#t~ite15_8|) InVars {P3Thread1of1ForFork1_#t~ite15=|v_P3Thread1of1ForFork1_#t~ite15_8|} OutVars{P3Thread1of1ForFork1_#t~ite16=|v_P3Thread1of1ForFork1_#t~ite16_13|, P3Thread1of1ForFork1_#t~ite15=|v_P3Thread1of1ForFork1_#t~ite15_7|, ~y~0=v_~y~0_28} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite16, P3Thread1of1ForFork1_#t~ite15, ~y~0] because there is no mapped edge [2019-12-07 17:36:29,685 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [793] [793] L811-->L811-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1097394295 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd4~0_In-1097394295 256)))) (or (and (or .cse0 .cse1) (= ~y$w_buff0_used~0_In-1097394295 |P3Thread1of1ForFork1_#t~ite17_Out-1097394295|)) (and (not .cse1) (= |P3Thread1of1ForFork1_#t~ite17_Out-1097394295| 0) (not .cse0)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-1097394295, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1097394295} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-1097394295, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1097394295, P3Thread1of1ForFork1_#t~ite17=|P3Thread1of1ForFork1_#t~ite17_Out-1097394295|} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite17] because there is no mapped edge [2019-12-07 17:36:29,686 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [806] [806] L812-->L812-2: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In-2109563336 256))) (.cse1 (= 0 (mod ~y$r_buff0_thd4~0_In-2109563336 256))) (.cse3 (= 0 (mod ~y$w_buff1_used~0_In-2109563336 256))) (.cse2 (= 0 (mod ~y$r_buff1_thd4~0_In-2109563336 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P3Thread1of1ForFork1_#t~ite18_Out-2109563336| 0)) (and (or .cse0 .cse1) (= |P3Thread1of1ForFork1_#t~ite18_Out-2109563336| ~y$w_buff1_used~0_In-2109563336) (or .cse3 .cse2)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-2109563336, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-2109563336, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2109563336, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2109563336} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-2109563336, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In-2109563336, P3Thread1of1ForFork1_#t~ite18=|P3Thread1of1ForFork1_#t~ite18_Out-2109563336|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2109563336, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2109563336} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite18] because there is no mapped edge [2019-12-07 17:36:29,686 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [796] [796] L813-->L813-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd4~0_In-610255116 256) 0)) (.cse1 (= (mod ~y$w_buff0_used~0_In-610255116 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 |P3Thread1of1ForFork1_#t~ite19_Out-610255116|)) (and (or .cse0 .cse1) (= |P3Thread1of1ForFork1_#t~ite19_Out-610255116| ~y$r_buff0_thd4~0_In-610255116)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-610255116, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-610255116} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In-610255116, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-610255116, P3Thread1of1ForFork1_#t~ite19=|P3Thread1of1ForFork1_#t~ite19_Out-610255116|} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite19] because there is no mapped edge [2019-12-07 17:36:29,686 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L760-->L760-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd2~0_In-2042454840 256) 0)) (.cse1 (= (mod ~y$w_buff0_used~0_In-2042454840 256) 0))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork3_#t~ite7_Out-2042454840| ~y$r_buff0_thd2~0_In-2042454840)) (and (not .cse0) (= |P1Thread1of1ForFork3_#t~ite7_Out-2042454840| 0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-2042454840, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-2042454840} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-2042454840, P1Thread1of1ForFork3_#t~ite7=|P1Thread1of1ForFork3_#t~ite7_Out-2042454840|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-2042454840} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite7] because there is no mapped edge [2019-12-07 17:36:29,687 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [810] [810] L761-->L761-2: Formula: (let ((.cse2 (= 0 (mod ~y$r_buff1_thd2~0_In-2042684100 256))) (.cse3 (= 0 (mod ~y$w_buff1_used~0_In-2042684100 256))) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-2042684100 256))) (.cse0 (= 0 (mod ~y$r_buff0_thd2~0_In-2042684100 256)))) (or (and (or .cse0 .cse1) (= ~y$r_buff1_thd2~0_In-2042684100 |P1Thread1of1ForFork3_#t~ite8_Out-2042684100|) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= 0 |P1Thread1of1ForFork3_#t~ite8_Out-2042684100|)))) InVars {~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-2042684100, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2042684100, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-2042684100, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2042684100} OutVars{~y$r_buff1_thd2~0=~y$r_buff1_thd2~0_In-2042684100, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-2042684100, P1Thread1of1ForFork3_#t~ite8=|P1Thread1of1ForFork3_#t~ite8_Out-2042684100|, ~y$r_buff0_thd2~0=~y$r_buff0_thd2~0_In-2042684100, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-2042684100} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#t~ite8] because there is no mapped edge [2019-12-07 17:36:29,687 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [826] [826] L761-2-->P1EXIT: Formula: (and (= |v_P1Thread1of1ForFork3_#t~ite8_24| v_~y$r_buff1_thd2~0_109) (= (+ v_~__unbuffered_cnt~0_41 1) v_~__unbuffered_cnt~0_40) (= 0 |v_P1Thread1of1ForFork3_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork3_#res.base_3|)) InVars {P1Thread1of1ForFork3_#t~ite8=|v_P1Thread1of1ForFork3_#t~ite8_24|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_41} OutVars{P1Thread1of1ForFork3_#res.base=|v_P1Thread1of1ForFork3_#res.base_3|, ~y$r_buff1_thd2~0=v_~y$r_buff1_thd2~0_109, P1Thread1of1ForFork3_#t~ite8=|v_P1Thread1of1ForFork3_#t~ite8_23|, P1Thread1of1ForFork3_#res.offset=|v_P1Thread1of1ForFork3_#res.offset_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_40} AuxVars[] AssignedVars[P1Thread1of1ForFork3_#res.base, ~y$r_buff1_thd2~0, P1Thread1of1ForFork3_#t~ite8, P1Thread1of1ForFork3_#res.offset, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 17:36:29,687 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [795] [795] L788-->L788-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In808346148 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd3~0_In808346148 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite11_Out808346148| ~y$w_buff0_used~0_In808346148) (or .cse0 .cse1)) (and (not .cse0) (= |P2Thread1of1ForFork0_#t~ite11_Out808346148| 0) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In808346148, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In808346148} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In808346148, P2Thread1of1ForFork0_#t~ite11=|P2Thread1of1ForFork0_#t~ite11_Out808346148|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In808346148} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite11] because there is no mapped edge [2019-12-07 17:36:29,688 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [813] [813] L789-->L789-2: Formula: (let ((.cse2 (= (mod ~y$w_buff1_used~0_In1769944165 256) 0)) (.cse3 (= 0 (mod ~y$r_buff1_thd3~0_In1769944165 256))) (.cse1 (= (mod ~y$w_buff0_used~0_In1769944165 256) 0)) (.cse0 (= 0 (mod ~y$r_buff0_thd3~0_In1769944165 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~y$w_buff1_used~0_In1769944165 |P2Thread1of1ForFork0_#t~ite12_Out1769944165|)) (and (= |P2Thread1of1ForFork0_#t~ite12_Out1769944165| 0) (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0)))))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1769944165, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1769944165, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1769944165, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1769944165} OutVars{~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1769944165, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1769944165, P2Thread1of1ForFork0_#t~ite12=|P2Thread1of1ForFork0_#t~ite12_Out1769944165|, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1769944165, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1769944165} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite12] because there is no mapped edge [2019-12-07 17:36:29,688 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [799] [799] L790-->L791: Formula: (let ((.cse0 (= 0 (mod ~y$w_buff0_used~0_In-1791116007 256))) (.cse2 (= ~y$r_buff0_thd3~0_In-1791116007 ~y$r_buff0_thd3~0_Out-1791116007)) (.cse1 (= (mod ~y$r_buff0_thd3~0_In-1791116007 256) 0))) (or (and (not .cse0) (not .cse1) (= ~y$r_buff0_thd3~0_Out-1791116007 0)) (and .cse0 .cse2) (and .cse2 .cse1))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1791116007, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In-1791116007} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1791116007, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_Out-1791116007, P2Thread1of1ForFork0_#t~ite13=|P2Thread1of1ForFork0_#t~ite13_Out-1791116007|} AuxVars[] AssignedVars[~y$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite13] because there is no mapped edge [2019-12-07 17:36:29,688 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [804] [804] L791-->L791-2: Formula: (let ((.cse1 (= 0 (mod ~y$r_buff1_thd3~0_In1071999575 256))) (.cse0 (= 0 (mod ~y$w_buff1_used~0_In1071999575 256))) (.cse3 (= (mod ~y$r_buff0_thd3~0_In1071999575 256) 0)) (.cse2 (= 0 (mod ~y$w_buff0_used~0_In1071999575 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork0_#t~ite14_Out1071999575|)) (and (or .cse1 .cse0) (= |P2Thread1of1ForFork0_#t~ite14_Out1071999575| ~y$r_buff1_thd3~0_In1071999575) (or .cse3 .cse2)))) InVars {~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1071999575, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1071999575, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1071999575, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1071999575} OutVars{P2Thread1of1ForFork0_#t~ite14=|P2Thread1of1ForFork0_#t~ite14_Out1071999575|, ~y$r_buff1_thd3~0=~y$r_buff1_thd3~0_In1071999575, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1071999575, ~y$r_buff0_thd3~0=~y$r_buff0_thd3~0_In1071999575, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1071999575} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14] because there is no mapped edge [2019-12-07 17:36:29,688 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [847] [847] L791-2-->P2EXIT: Formula: (and (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= v_~__unbuffered_cnt~0_59 (+ v_~__unbuffered_cnt~0_60 1)) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0) (= v_~y$r_buff1_thd3~0_112 |v_P2Thread1of1ForFork0_#t~ite14_20|)) InVars {P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_20|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_60} OutVars{P2Thread1of1ForFork0_#t~ite14=|v_P2Thread1of1ForFork0_#t~ite14_19|, ~y$r_buff1_thd3~0=v_~y$r_buff1_thd3~0_112, P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_59, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite14, ~y$r_buff1_thd3~0, P2Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 17:36:29,689 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [792] [792] L814-->L814-2: Formula: (let ((.cse1 (= (mod ~y$r_buff0_thd4~0_In1184031156 256) 0)) (.cse0 (= (mod ~y$w_buff0_used~0_In1184031156 256) 0)) (.cse3 (= 0 (mod ~y$w_buff1_used~0_In1184031156 256))) (.cse2 (= (mod ~y$r_buff1_thd4~0_In1184031156 256) 0))) (or (and (= 0 |P3Thread1of1ForFork1_#t~ite20_Out1184031156|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~y$r_buff1_thd4~0_In1184031156 |P3Thread1of1ForFork1_#t~ite20_Out1184031156|) (or .cse1 .cse0) (or .cse3 .cse2)))) InVars {~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1184031156, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In1184031156, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1184031156, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1184031156} OutVars{~y$r_buff0_thd4~0=~y$r_buff0_thd4~0_In1184031156, ~y$r_buff1_thd4~0=~y$r_buff1_thd4~0_In1184031156, ~y$w_buff0_used~0=~y$w_buff0_used~0_In1184031156, P3Thread1of1ForFork1_#t~ite20=|P3Thread1of1ForFork1_#t~ite20_Out1184031156|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1184031156} AuxVars[] AssignedVars[P3Thread1of1ForFork1_#t~ite20] because there is no mapped edge [2019-12-07 17:36:29,689 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [846] [846] L814-2-->P3EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_54 1) v_~__unbuffered_cnt~0_53) (= |v_P3Thread1of1ForFork1_#res.offset_3| 0) (= |v_P3Thread1of1ForFork1_#t~ite20_28| v_~y$r_buff1_thd4~0_109) (= |v_P3Thread1of1ForFork1_#res.base_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_54, P3Thread1of1ForFork1_#t~ite20=|v_P3Thread1of1ForFork1_#t~ite20_28|} OutVars{~y$r_buff1_thd4~0=v_~y$r_buff1_thd4~0_109, P3Thread1of1ForFork1_#res.base=|v_P3Thread1of1ForFork1_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_53, P3Thread1of1ForFork1_#res.offset=|v_P3Thread1of1ForFork1_#res.offset_3|, P3Thread1of1ForFork1_#t~ite20=|v_P3Thread1of1ForFork1_#t~ite20_27|} AuxVars[] AssignedVars[~y$r_buff1_thd4~0, P3Thread1of1ForFork1_#res.base, ~__unbuffered_cnt~0, P3Thread1of1ForFork1_#res.offset, P3Thread1of1ForFork1_#t~ite20] because there is no mapped edge [2019-12-07 17:36:29,689 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L843-->L845-2: Formula: (and (not (= (mod v_~main$tmp_guard0~0_8 256) 0)) (or (= (mod v_~y$w_buff0_used~0_216 256) 0) (= 0 (mod v_~y$r_buff0_thd0~0_104 256)))) InVars {~y$w_buff0_used~0=v_~y$w_buff0_used~0_216, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_104, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8} OutVars{~y$w_buff0_used~0=v_~y$w_buff0_used~0_216, ~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_104, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_8} AuxVars[] AssignedVars[] because there is no mapped edge [2019-12-07 17:36:29,689 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [798] [798] L845-2-->L845-5: Formula: (let ((.cse1 (= (mod ~y$r_buff1_thd0~0_In-1663472441 256) 0)) (.cse0 (= |ULTIMATE.start_main_#t~ite26_Out-1663472441| |ULTIMATE.start_main_#t~ite25_Out-1663472441|)) (.cse2 (= (mod ~y$w_buff1_used~0_In-1663472441 256) 0))) (or (and (= ~y~0_In-1663472441 |ULTIMATE.start_main_#t~ite25_Out-1663472441|) .cse0 (or .cse1 .cse2)) (and (not .cse1) .cse0 (= ~y$w_buff1~0_In-1663472441 |ULTIMATE.start_main_#t~ite25_Out-1663472441|) (not .cse2)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In-1663472441, ~y~0=~y~0_In-1663472441, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1663472441, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1663472441} OutVars{~y$w_buff1~0=~y$w_buff1~0_In-1663472441, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out-1663472441|, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out-1663472441|, ~y~0=~y~0_In-1663472441, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1663472441, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1663472441} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 17:36:29,690 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [797] [797] L846-->L846-2: Formula: (let ((.cse0 (= (mod ~y$w_buff0_used~0_In645563400 256) 0)) (.cse1 (= 0 (mod ~y$r_buff0_thd0~0_In645563400 256)))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite27_Out645563400| ~y$w_buff0_used~0_In645563400)) (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite27_Out645563400| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In645563400, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In645563400} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In645563400, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In645563400, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out645563400|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 17:36:29,690 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [801] [801] L847-->L847-2: Formula: (let ((.cse1 (= 0 (mod ~y$w_buff1_used~0_In-379748146 256))) (.cse0 (= 0 (mod ~y$r_buff1_thd0~0_In-379748146 256))) (.cse2 (= (mod ~y$w_buff0_used~0_In-379748146 256) 0)) (.cse3 (= 0 (mod ~y$r_buff0_thd0~0_In-379748146 256)))) (or (and (= 0 |ULTIMATE.start_main_#t~ite28_Out-379748146|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse1 .cse0) (or .cse2 .cse3) (= ~y$w_buff1_used~0_In-379748146 |ULTIMATE.start_main_#t~ite28_Out-379748146|)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-379748146, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-379748146, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-379748146, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-379748146} OutVars{ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out-379748146|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-379748146, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-379748146, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-379748146, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-379748146} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 17:36:29,690 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [812] [812] L848-->L848-2: Formula: (let ((.cse0 (= (mod ~y$r_buff0_thd0~0_In-1543914493 256) 0)) (.cse1 (= 0 (mod ~y$w_buff0_used~0_In-1543914493 256)))) (or (and (= ~y$r_buff0_thd0~0_In-1543914493 |ULTIMATE.start_main_#t~ite29_Out-1543914493|) (or .cse0 .cse1)) (and (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite29_Out-1543914493|) (not .cse1)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1543914493, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1543914493} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1543914493, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-1543914493|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1543914493} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 17:36:29,691 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [790] [790] L849-->L849-2: Formula: (let ((.cse2 (= 0 (mod ~y$w_buff0_used~0_In-1157193354 256))) (.cse3 (= (mod ~y$r_buff0_thd0~0_In-1157193354 256) 0)) (.cse1 (= (mod ~y$w_buff1_used~0_In-1157193354 256) 0)) (.cse0 (= (mod ~y$r_buff1_thd0~0_In-1157193354 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite30_Out-1157193354| ~y$r_buff1_thd0~0_In-1157193354) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= |ULTIMATE.start_main_#t~ite30_Out-1157193354| 0)))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1157193354, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1157193354, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1157193354, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1157193354} OutVars{ULTIMATE.start_main_#t~ite30=|ULTIMATE.start_main_#t~ite30_Out-1157193354|, ~y$w_buff0_used~0=~y$w_buff0_used~0_In-1157193354, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1157193354, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1157193354, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1157193354} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite30] because there is no mapped edge [2019-12-07 17:36:29,692 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [852] [852] L858-->L858-8: Formula: (let ((.cse1 (= 0 (mod ~weak$$choice2~0_In512810520 256)))) (or (and (let ((.cse0 (= (mod ~y$r_buff0_thd0~0_In512810520 256) 0))) (or (and (= (mod ~y$r_buff1_thd0~0_In512810520 256) 0) .cse0) (= 0 (mod ~y$w_buff0_used~0_In512810520 256)) (and (= (mod ~y$w_buff1_used~0_In512810520 256) 0) .cse0))) .cse1 (= |ULTIMATE.start_main_#t~ite40_Out512810520| |ULTIMATE.start_main_#t~ite39_Out512810520|) (= ~y$w_buff1~0_In512810520 |ULTIMATE.start_main_#t~ite39_Out512810520|)) (and (= |ULTIMATE.start_main_#t~ite40_Out512810520| ~y$w_buff1~0_In512810520) (not .cse1) (= |ULTIMATE.start_main_#t~ite39_In512810520| |ULTIMATE.start_main_#t~ite39_Out512810520|)))) InVars {~y$w_buff1~0=~y$w_buff1~0_In512810520, ~y$w_buff0_used~0=~y$w_buff0_used~0_In512810520, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_In512810520|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In512810520, ~weak$$choice2~0=~weak$$choice2~0_In512810520, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In512810520, ~y$w_buff1_used~0=~y$w_buff1_used~0_In512810520} OutVars{ULTIMATE.start_main_#t~ite40=|ULTIMATE.start_main_#t~ite40_Out512810520|, ~y$w_buff1~0=~y$w_buff1~0_In512810520, ~y$w_buff0_used~0=~y$w_buff0_used~0_In512810520, ULTIMATE.start_main_#t~ite39=|ULTIMATE.start_main_#t~ite39_Out512810520|, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In512810520, ~weak$$choice2~0=~weak$$choice2~0_In512810520, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In512810520, ~y$w_buff1_used~0=~y$w_buff1_used~0_In512810520} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite40, ULTIMATE.start_main_#t~ite39] because there is no mapped edge [2019-12-07 17:36:29,693 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [853] [853] L859-->L859-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In1183191206 256)))) (or (and (= |ULTIMATE.start_main_#t~ite42_In1183191206| |ULTIMATE.start_main_#t~ite42_Out1183191206|) (not .cse0) (= ~y$w_buff0_used~0_In1183191206 |ULTIMATE.start_main_#t~ite43_Out1183191206|)) (and .cse0 (= ~y$w_buff0_used~0_In1183191206 |ULTIMATE.start_main_#t~ite42_Out1183191206|) (= |ULTIMATE.start_main_#t~ite42_Out1183191206| |ULTIMATE.start_main_#t~ite43_Out1183191206|) (let ((.cse1 (= (mod ~y$r_buff0_thd0~0_In1183191206 256) 0))) (or (and (= 0 (mod ~y$w_buff1_used~0_In1183191206 256)) .cse1) (and (= 0 (mod ~y$r_buff1_thd0~0_In1183191206 256)) .cse1) (= 0 (mod ~y$w_buff0_used~0_In1183191206 256))))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In1183191206, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1183191206, ~weak$$choice2~0=~weak$$choice2~0_In1183191206, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1183191206, ULTIMATE.start_main_#t~ite42=|ULTIMATE.start_main_#t~ite42_In1183191206|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1183191206} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In1183191206, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In1183191206, ULTIMATE.start_main_#t~ite43=|ULTIMATE.start_main_#t~ite43_Out1183191206|, ~weak$$choice2~0=~weak$$choice2~0_In1183191206, ULTIMATE.start_main_#t~ite42=|ULTIMATE.start_main_#t~ite42_Out1183191206|, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In1183191206, ~y$w_buff1_used~0=~y$w_buff1_used~0_In1183191206} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite42] because there is no mapped edge [2019-12-07 17:36:29,693 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [865] [865] L860-->L860-8: Formula: (let ((.cse5 (= (mod ~y$r_buff1_thd0~0_In-1567301564 256) 0)) (.cse0 (= 0 (mod ~weak$$choice2~0_In-1567301564 256))) (.cse1 (= |ULTIMATE.start_main_#t~ite46_Out-1567301564| |ULTIMATE.start_main_#t~ite45_Out-1567301564|)) (.cse2 (= 0 (mod ~y$w_buff1_used~0_In-1567301564 256))) (.cse4 (= (mod ~y$w_buff0_used~0_In-1567301564 256) 0)) (.cse3 (= (mod ~y$r_buff0_thd0~0_In-1567301564 256) 0))) (or (and (= |ULTIMATE.start_main_#t~ite44_In-1567301564| |ULTIMATE.start_main_#t~ite44_Out-1567301564|) (or (and (= ~y$w_buff1_used~0_In-1567301564 |ULTIMATE.start_main_#t~ite45_Out-1567301564|) .cse0 .cse1 (or (and .cse2 .cse3) .cse4 (and .cse3 .cse5))) (and (= |ULTIMATE.start_main_#t~ite45_Out-1567301564| |ULTIMATE.start_main_#t~ite45_In-1567301564|) (not .cse0) (= ~y$w_buff1_used~0_In-1567301564 |ULTIMATE.start_main_#t~ite46_Out-1567301564|)))) (let ((.cse6 (not .cse3))) (and (or (not .cse5) .cse6) .cse0 .cse1 (or (not .cse2) .cse6) (not .cse4) (= 0 |ULTIMATE.start_main_#t~ite44_Out-1567301564|) (= |ULTIMATE.start_main_#t~ite45_Out-1567301564| |ULTIMATE.start_main_#t~ite44_Out-1567301564|))))) InVars {~y$w_buff0_used~0=~y$w_buff0_used~0_In-1567301564, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1567301564, ~weak$$choice2~0=~weak$$choice2~0_In-1567301564, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1567301564, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_In-1567301564|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1567301564, ULTIMATE.start_main_#t~ite44=|ULTIMATE.start_main_#t~ite44_In-1567301564|} OutVars{~y$w_buff0_used~0=~y$w_buff0_used~0_In-1567301564, ~y$r_buff0_thd0~0=~y$r_buff0_thd0~0_In-1567301564, ULTIMATE.start_main_#t~ite46=|ULTIMATE.start_main_#t~ite46_Out-1567301564|, ~weak$$choice2~0=~weak$$choice2~0_In-1567301564, ~y$r_buff1_thd0~0=~y$r_buff1_thd0~0_In-1567301564, ULTIMATE.start_main_#t~ite45=|ULTIMATE.start_main_#t~ite45_Out-1567301564|, ~y$w_buff1_used~0=~y$w_buff1_used~0_In-1567301564, ULTIMATE.start_main_#t~ite44=|ULTIMATE.start_main_#t~ite44_Out-1567301564|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44] because there is no mapped edge [2019-12-07 17:36:29,693 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [868] [868] L860-8-->L862: Formula: (and (not (= (mod v_~weak$$choice2~0_106 256) 0)) (= v_~y$w_buff1_used~0_383 |v_ULTIMATE.start_main_#t~ite46_36|) (= v_~y$r_buff0_thd0~0_352 v_~y$r_buff0_thd0~0_351)) InVars {~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_352, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_36|, ~weak$$choice2~0=v_~weak$$choice2~0_106} OutVars{~y$r_buff0_thd0~0=v_~y$r_buff0_thd0~0_351, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_28|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_35|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_31|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_34|, ~weak$$choice2~0=v_~weak$$choice2~0_106, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_31|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_33|, ~y$w_buff1_used~0=v_~y$w_buff1_used~0_383} AuxVars[] AssignedVars[~y$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_#t~ite48, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite44, ~y$w_buff1_used~0] because there is no mapped edge [2019-12-07 17:36:29,694 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [832] [832] L864-->L4: Formula: (and (= 0 v_~y$flush_delayed~0_25) (= v_~y~0_116 v_~y$mem_tmp~0_11) (not (= (mod v_~y$flush_delayed~0_26 256) 0)) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_5| (mod v_~main$tmp_guard1~0_15 256))) InVars {~y$mem_tmp~0=v_~y$mem_tmp~0_11, ~y$flush_delayed~0=v_~y$flush_delayed~0_26, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_15} OutVars{~y$mem_tmp~0=v_~y$mem_tmp~0_11, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_10, ~y$flush_delayed~0=v_~y$flush_delayed~0_25, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_15, ~y~0=v_~y~0_116, ULTIMATE.start_main_#t~ite53=|v_ULTIMATE.start_main_#t~ite53_23|, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_5|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression, ~y$flush_delayed~0, ~y~0, ULTIMATE.start_main_#t~ite53, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 17:36:29,694 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [841] [841] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_11 0)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 17:36:29,750 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_8704b9a5-7749-4ccc-bd15-0b6492d0cc81/bin/uautomizer/witness.graphml [2019-12-07 17:36:29,750 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 17:36:29,751 INFO L168 Benchmark]: Toolchain (without parser) took 123479.09 ms. Allocated memory was 1.0 GB in the beginning and 8.2 GB in the end (delta: 7.2 GB). Free memory was 937.2 MB in the beginning and 3.5 GB in the end (delta: -2.6 GB). Peak memory consumption was 4.6 GB. Max. memory is 11.5 GB. [2019-12-07 17:36:29,752 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 958.7 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 17:36:29,752 INFO L168 Benchmark]: CACSL2BoogieTranslator took 389.08 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 108.0 MB). Free memory was 937.2 MB in the beginning and 1.1 GB in the end (delta: -137.4 MB). Peak memory consumption was 24.0 MB. Max. memory is 11.5 GB. [2019-12-07 17:36:29,752 INFO L168 Benchmark]: Boogie Procedure Inliner took 38.77 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 17:36:29,753 INFO L168 Benchmark]: Boogie Preprocessor took 25.97 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 17:36:29,753 INFO L168 Benchmark]: RCFGBuilder took 412.54 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 55.2 MB). Peak memory consumption was 55.2 MB. Max. memory is 11.5 GB. [2019-12-07 17:36:29,753 INFO L168 Benchmark]: TraceAbstraction took 122537.76 ms. Allocated memory was 1.1 GB in the beginning and 8.2 GB in the end (delta: 7.1 GB). Free memory was 1.0 GB in the beginning and 3.5 GB in the end (delta: -2.5 GB). Peak memory consumption was 4.5 GB. Max. memory is 11.5 GB. [2019-12-07 17:36:29,753 INFO L168 Benchmark]: Witness Printer took 71.24 ms. Allocated memory is still 8.2 GB. Free memory was 3.5 GB in the beginning and 3.5 GB in the end (delta: 37.8 MB). Peak memory consumption was 37.8 MB. Max. memory is 11.5 GB. [2019-12-07 17:36:29,755 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17 ms. Allocated memory is still 1.0 GB. Free memory is still 958.7 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 389.08 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 108.0 MB). Free memory was 937.2 MB in the beginning and 1.1 GB in the end (delta: -137.4 MB). Peak memory consumption was 24.0 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 38.77 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 25.97 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 412.54 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 55.2 MB). Peak memory consumption was 55.2 MB. Max. memory is 11.5 GB. * TraceAbstraction took 122537.76 ms. Allocated memory was 1.1 GB in the beginning and 8.2 GB in the end (delta: 7.1 GB). Free memory was 1.0 GB in the beginning and 3.5 GB in the end (delta: -2.5 GB). Peak memory consumption was 4.5 GB. Max. memory is 11.5 GB. * Witness Printer took 71.24 ms. Allocated memory is still 8.2 GB. Free memory was 3.5 GB in the beginning and 3.5 GB in the end (delta: 37.8 MB). Peak memory consumption was 37.8 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.3s, 192 ProgramPointsBefore, 97 ProgramPointsAfterwards, 226 TransitionsBefore, 103 TransitionsAfterwards, 18432 CoEnabledTransitionPairs, 8 FixpointIterations, 36 TrivialSequentialCompositions, 54 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 37 ConcurrentYvCompositions, 33 ChoiceCompositions, 6019 VarBasedMoverChecksPositive, 222 VarBasedMoverChecksNegative, 63 SemBasedMoverChecksPositive, 227 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.7s, 0 MoverChecksTotal, 86545 CheckedPairsTotal, 127 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L833] FCALL, FORK 0 pthread_create(&t577, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L835] FCALL, FORK 0 pthread_create(&t578, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L837] FCALL, FORK 0 pthread_create(&t579, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=0, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=0, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=0] [L776] 3 y$r_buff1_thd0 = y$r_buff0_thd0 [L777] 3 y$r_buff1_thd1 = y$r_buff0_thd1 [L778] 3 y$r_buff1_thd2 = y$r_buff0_thd2 [L779] 3 y$r_buff1_thd3 = y$r_buff0_thd3 [L780] 3 y$r_buff1_thd4 = y$r_buff0_thd4 [L781] 3 y$r_buff0_thd3 = (_Bool)1 [L784] 3 __unbuffered_p2_EAX = z VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=0] [L839] FCALL, FORK 0 pthread_create(&t580, ((void *)0), P3, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=0, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=0] [L801] 4 z = 1 [L804] 4 __unbuffered_p3_EAX = z [L807] 4 __unbuffered_p3_EBX = a VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L810] 4 y$w_buff0_used && y$r_buff0_thd4 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd4 ? y$w_buff1 : y) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L751] 2 x = 2 [L754] 2 y = 1 VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L757] EXPR 2 y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff1=0, y$w_buff1_used=0, z=1] [L757] 2 y = y$w_buff0_used && y$r_buff0_thd2 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd2 ? y$w_buff1 : y) [L758] 2 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$w_buff0_used [L811] 4 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd4 ? (_Bool)0 : y$w_buff0_used [L812] 4 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd4 || y$w_buff1_used && y$r_buff1_thd4 ? (_Bool)0 : y$w_buff1_used [L787] EXPR 3 y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=1, y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L759] 2 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd2 || y$w_buff1_used && y$r_buff1_thd2 ? (_Bool)0 : y$w_buff1_used [L760] 2 y$r_buff0_thd2 = y$w_buff0_used && y$r_buff0_thd2 ? (_Bool)0 : y$r_buff0_thd2 [L787] 3 y = y$w_buff0_used && y$r_buff0_thd3 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd3 ? y$w_buff1 : y) [L788] 3 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd3 ? (_Bool)0 : y$w_buff0_used [L789] 3 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd3 || y$w_buff1_used && y$r_buff1_thd3 ? (_Bool)0 : y$w_buff1_used [L813] 4 y$r_buff0_thd4 = y$w_buff0_used && y$r_buff0_thd4 ? (_Bool)0 : y$r_buff0_thd4 [L841] 0 main$tmp_guard0 = __unbuffered_cnt == 4 VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=2, y$flush_delayed=0, y$mem_tmp=0, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L845] 0 y = y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : (y$w_buff1_used && y$r_buff1_thd0 ? y$w_buff1 : y) [L846] 0 y$w_buff0_used = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used [L847] 0 y$w_buff1_used = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$w_buff1_used [L848] 0 y$r_buff0_thd0 = y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$r_buff0_thd0 [L849] 0 y$r_buff1_thd0 = y$w_buff0_used && y$r_buff0_thd0 || y$w_buff1_used && y$r_buff1_thd0 ? (_Bool)0 : y$r_buff1_thd0 [L852] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L853] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L854] 0 y$flush_delayed = weak$$choice2 [L855] 0 y$mem_tmp = y VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L856] EXPR 0 !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L856] 0 y = !y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff1) [L857] EXPR 0 weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L857] 0 y$w_buff0 = weak$$choice2 ? y$w_buff0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff0 : y$w_buff0)) [L858] 0 y$w_buff1 = weak$$choice2 ? y$w_buff1 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff1 : (y$w_buff0_used && y$r_buff0_thd0 ? y$w_buff1 : y$w_buff1)) [L859] 0 y$w_buff0_used = weak$$choice2 ? y$w_buff0_used : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$w_buff0_used : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : y$w_buff0_used)) [L862] EXPR 0 weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] [L862] 0 y$r_buff1_thd0 = weak$$choice2 ? y$r_buff1_thd0 : (!y$w_buff0_used || !y$r_buff0_thd0 && !y$w_buff1_used || !y$r_buff0_thd0 && !y$r_buff1_thd0 ? y$r_buff1_thd0 : (y$w_buff0_used && y$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L863] 0 main$tmp_guard1 = !(x == 2 && y == 2 && __unbuffered_p2_EAX == 0 && __unbuffered_p3_EAX == 1 && __unbuffered_p3_EBX == 0) VAL [\result={0:0}, \result={0:0}, \result={0:0}, __unbuffered_cnt=4, __unbuffered_p2_EAX=0, __unbuffered_p3_EAX=1, __unbuffered_p3_EBX=0, a=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=1, x=2, y=2, y$flush_delayed=1, y$mem_tmp=2, y$r_buff0_thd0=0, y$r_buff0_thd1=0, y$r_buff0_thd2=0, y$r_buff0_thd3=1, y$r_buff0_thd4=0, y$r_buff1_thd0=0, y$r_buff1_thd1=0, y$r_buff1_thd2=0, y$r_buff1_thd3=0, y$r_buff1_thd4=0, y$read_delayed=0, y$read_delayed_var={0:0}, y$w_buff0=2, y$w_buff0_used=0, y$w_buff1=0, y$w_buff1_used=0, z=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 5 procedures, 180 locations, 2 error locations. Result: UNSAFE, OverallTime: 122.3s, OverallIterations: 22, TraceHistogramMax: 1, AutomataDifference: 19.9s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 3186 SDtfs, 3388 SDslu, 6271 SDs, 0 SdLazy, 3615 SolverSat, 211 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 2.2s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 182 GetRequests, 48 SyntacticMatches, 20 SemanticMatches, 114 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 95 ImplicationChecksByTransitivity, 0.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=335984occurred in iteration=3, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 55.8s AutomataMinimizationTime, 21 MinimizatonAttempts, 154266 StatesRemovedByMinimization, 18 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 1.0s InterpolantComputationTime, 1106 NumberOfCodeBlocks, 1106 NumberOfCodeBlocksAsserted, 22 NumberOfCheckSat, 1015 ConstructedInterpolants, 0 QuantifiedInterpolants, 180185 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 21 InterpolantComputations, 21 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...