./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/mix025_tso.oepc.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_4b6765ec-d8fe-4308-afe8-c4ab758a5330/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_4b6765ec-d8fe-4308-afe8-c4ab758a5330/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_4b6765ec-d8fe-4308-afe8-c4ab758a5330/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_4b6765ec-d8fe-4308-afe8-c4ab758a5330/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/mix025_tso.oepc.i -s /tmp/vcloud-vcloud-master/worker/run_dir_4b6765ec-d8fe-4308-afe8-c4ab758a5330/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_4b6765ec-d8fe-4308-afe8-c4ab758a5330/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 8faf293eb6719c0e3a6773f45fc684958f3a3f1b ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 18:28:09,658 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 18:28:09,659 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 18:28:09,667 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 18:28:09,667 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 18:28:09,668 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 18:28:09,669 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 18:28:09,670 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 18:28:09,671 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 18:28:09,672 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 18:28:09,672 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 18:28:09,673 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 18:28:09,673 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 18:28:09,674 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 18:28:09,675 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 18:28:09,675 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 18:28:09,676 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 18:28:09,676 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 18:28:09,678 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 18:28:09,679 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 18:28:09,680 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 18:28:09,681 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 18:28:09,682 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 18:28:09,682 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 18:28:09,684 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 18:28:09,684 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 18:28:09,684 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 18:28:09,684 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 18:28:09,685 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 18:28:09,685 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 18:28:09,685 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 18:28:09,686 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 18:28:09,686 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 18:28:09,687 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 18:28:09,687 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 18:28:09,687 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 18:28:09,688 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 18:28:09,688 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 18:28:09,688 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 18:28:09,688 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 18:28:09,689 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 18:28:09,689 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_4b6765ec-d8fe-4308-afe8-c4ab758a5330/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 18:28:09,699 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 18:28:09,699 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 18:28:09,700 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 18:28:09,700 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 18:28:09,700 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 18:28:09,700 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 18:28:09,700 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 18:28:09,700 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 18:28:09,700 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 18:28:09,701 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 18:28:09,701 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 18:28:09,701 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 18:28:09,701 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 18:28:09,701 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 18:28:09,701 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 18:28:09,701 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 18:28:09,701 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 18:28:09,702 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 18:28:09,702 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 18:28:09,702 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 18:28:09,702 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 18:28:09,702 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:28:09,702 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 18:28:09,702 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 18:28:09,702 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 18:28:09,703 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 18:28:09,703 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 18:28:09,703 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 18:28:09,703 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 18:28:09,703 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_4b6765ec-d8fe-4308-afe8-c4ab758a5330/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 8faf293eb6719c0e3a6773f45fc684958f3a3f1b [2019-12-07 18:28:09,802 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 18:28:09,811 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 18:28:09,814 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 18:28:09,815 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 18:28:09,816 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 18:28:09,816 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_4b6765ec-d8fe-4308-afe8-c4ab758a5330/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/mix025_tso.oepc.i [2019-12-07 18:28:09,858 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_4b6765ec-d8fe-4308-afe8-c4ab758a5330/bin/uautomizer/data/210fbd2bf/2e23baee958345f29c76439242a28921/FLAGbc214a44b [2019-12-07 18:28:10,314 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 18:28:10,315 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_4b6765ec-d8fe-4308-afe8-c4ab758a5330/sv-benchmarks/c/pthread-wmm/mix025_tso.oepc.i [2019-12-07 18:28:10,325 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_4b6765ec-d8fe-4308-afe8-c4ab758a5330/bin/uautomizer/data/210fbd2bf/2e23baee958345f29c76439242a28921/FLAGbc214a44b [2019-12-07 18:28:10,647 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_4b6765ec-d8fe-4308-afe8-c4ab758a5330/bin/uautomizer/data/210fbd2bf/2e23baee958345f29c76439242a28921 [2019-12-07 18:28:10,653 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 18:28:10,656 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 18:28:10,657 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 18:28:10,657 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 18:28:10,662 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 18:28:10,662 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:28:10" (1/1) ... [2019-12-07 18:28:10,664 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@ac4b79f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:28:10, skipping insertion in model container [2019-12-07 18:28:10,664 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:28:10" (1/1) ... [2019-12-07 18:28:10,669 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 18:28:10,698 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 18:28:10,933 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:28:10,941 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 18:28:10,982 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:28:11,026 INFO L208 MainTranslator]: Completed translation [2019-12-07 18:28:11,026 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:28:11 WrapperNode [2019-12-07 18:28:11,026 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 18:28:11,027 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 18:28:11,027 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 18:28:11,027 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 18:28:11,032 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:28:11" (1/1) ... [2019-12-07 18:28:11,045 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:28:11" (1/1) ... [2019-12-07 18:28:11,063 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 18:28:11,063 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 18:28:11,063 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 18:28:11,063 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 18:28:11,070 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:28:11" (1/1) ... [2019-12-07 18:28:11,070 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:28:11" (1/1) ... [2019-12-07 18:28:11,073 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:28:11" (1/1) ... [2019-12-07 18:28:11,073 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:28:11" (1/1) ... [2019-12-07 18:28:11,080 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:28:11" (1/1) ... [2019-12-07 18:28:11,083 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:28:11" (1/1) ... [2019-12-07 18:28:11,086 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:28:11" (1/1) ... [2019-12-07 18:28:11,089 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 18:28:11,089 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 18:28:11,090 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 18:28:11,090 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 18:28:11,090 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:28:11" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_4b6765ec-d8fe-4308-afe8-c4ab758a5330/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:28:11,129 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 18:28:11,129 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 18:28:11,129 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 18:28:11,129 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 18:28:11,130 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 18:28:11,130 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 18:28:11,130 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 18:28:11,130 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 18:28:11,130 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 18:28:11,130 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 18:28:11,130 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 18:28:11,130 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 18:28:11,130 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 18:28:11,131 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 18:28:11,485 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 18:28:11,485 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 18:28:11,487 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:28:11 BoogieIcfgContainer [2019-12-07 18:28:11,487 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 18:28:11,488 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 18:28:11,488 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 18:28:11,490 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 18:28:11,490 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 06:28:10" (1/3) ... [2019-12-07 18:28:11,491 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@53b7aba and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:28:11, skipping insertion in model container [2019-12-07 18:28:11,491 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:28:11" (2/3) ... [2019-12-07 18:28:11,491 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@53b7aba and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:28:11, skipping insertion in model container [2019-12-07 18:28:11,492 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:28:11" (3/3) ... [2019-12-07 18:28:11,493 INFO L109 eAbstractionObserver]: Analyzing ICFG mix025_tso.oepc.i [2019-12-07 18:28:11,501 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 18:28:11,502 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 18:28:11,508 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 18:28:11,509 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 18:28:11,533 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,534 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,534 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,534 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,534 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,534 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,534 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,534 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,535 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,535 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,535 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,535 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,535 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,536 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,536 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,536 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,536 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,536 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,536 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,536 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,536 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,537 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,537 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,537 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,537 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,537 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,537 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,537 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,537 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,538 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,538 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,538 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,538 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,538 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,539 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,539 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,539 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,539 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,539 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,540 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,540 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,540 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,540 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,540 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,541 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,541 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,541 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,541 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,541 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,541 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,542 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,542 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,542 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,542 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,542 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,543 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,543 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,543 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,543 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,543 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,543 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,543 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,544 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,544 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,545 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,545 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,545 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,545 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,545 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,545 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,546 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,546 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~nondet16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,546 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,546 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,546 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,546 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,547 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,547 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,547 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,547 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,547 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,548 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,548 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,548 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,548 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,548 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,548 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,549 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,549 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,549 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,549 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,549 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,549 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,549 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,550 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,550 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,550 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,550 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,550 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,551 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,551 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,551 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,551 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,551 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,551 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,552 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,552 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,552 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,552 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,552 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,552 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,553 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,553 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,553 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,553 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,553 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,553 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,553 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,554 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,554 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,554 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,554 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,554 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,554 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,555 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,555 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,555 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,555 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,555 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,555 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,555 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,556 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,556 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,556 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,556 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,556 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,556 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,557 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,557 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,557 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,557 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,557 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,557 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,558 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,558 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,558 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,558 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,558 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,558 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,559 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,559 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,559 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,559 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,559 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,559 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,559 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,560 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,560 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,560 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,560 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,560 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,560 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,561 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,561 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,561 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,561 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,561 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,561 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,562 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,562 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,562 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,562 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,562 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,562 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,563 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,563 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,563 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,563 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,563 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,563 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,564 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,564 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:28:11,575 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 18:28:11,587 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 18:28:11,587 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 18:28:11,587 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 18:28:11,587 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 18:28:11,588 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 18:28:11,588 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 18:28:11,588 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 18:28:11,588 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 18:28:11,598 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 176 places, 213 transitions [2019-12-07 18:28:11,599 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 176 places, 213 transitions [2019-12-07 18:28:11,654 INFO L134 PetriNetUnfolder]: 47/210 cut-off events. [2019-12-07 18:28:11,654 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:28:11,664 INFO L76 FinitePrefix]: Finished finitePrefix Result has 220 conditions, 210 events. 47/210 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 704 event pairs. 9/170 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 18:28:11,679 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 176 places, 213 transitions [2019-12-07 18:28:11,709 INFO L134 PetriNetUnfolder]: 47/210 cut-off events. [2019-12-07 18:28:11,709 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:28:11,716 INFO L76 FinitePrefix]: Finished finitePrefix Result has 220 conditions, 210 events. 47/210 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 704 event pairs. 9/170 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 18:28:11,731 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 19004 [2019-12-07 18:28:11,732 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 18:28:14,578 WARN L192 SmtUtils]: Spent 141.00 ms on a formula simplification. DAG size of input: 91 DAG size of output: 89 [2019-12-07 18:28:14,827 INFO L206 etLargeBlockEncoding]: Checked pairs total: 130103 [2019-12-07 18:28:14,827 INFO L214 etLargeBlockEncoding]: Total number of compositions: 120 [2019-12-07 18:28:14,829 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 94 places, 105 transitions [2019-12-07 18:28:32,628 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 122102 states. [2019-12-07 18:28:32,629 INFO L276 IsEmpty]: Start isEmpty. Operand 122102 states. [2019-12-07 18:28:32,634 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-12-07 18:28:32,634 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:28:32,634 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-12-07 18:28:32,634 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:28:32,638 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:28:32,638 INFO L82 PathProgramCache]: Analyzing trace with hash 913940, now seen corresponding path program 1 times [2019-12-07 18:28:32,644 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:28:32,644 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [690437026] [2019-12-07 18:28:32,644 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:28:32,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:28:32,778 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:28:32,778 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [690437026] [2019-12-07 18:28:32,779 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:28:32,779 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 18:28:32,780 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1265234545] [2019-12-07 18:28:32,784 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:28:32,784 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:28:32,795 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:28:32,796 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:28:32,798 INFO L87 Difference]: Start difference. First operand 122102 states. Second operand 3 states. [2019-12-07 18:28:33,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:28:33,604 INFO L93 Difference]: Finished difference Result 121140 states and 517588 transitions. [2019-12-07 18:28:33,605 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:28:33,606 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2019-12-07 18:28:33,606 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:28:34,249 INFO L225 Difference]: With dead ends: 121140 [2019-12-07 18:28:34,249 INFO L226 Difference]: Without dead ends: 107958 [2019-12-07 18:28:34,250 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:28:39,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107958 states. [2019-12-07 18:28:40,952 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107958 to 107958. [2019-12-07 18:28:40,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 107958 states. [2019-12-07 18:28:41,312 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 107958 states to 107958 states and 460128 transitions. [2019-12-07 18:28:41,313 INFO L78 Accepts]: Start accepts. Automaton has 107958 states and 460128 transitions. Word has length 3 [2019-12-07 18:28:41,314 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:28:41,314 INFO L462 AbstractCegarLoop]: Abstraction has 107958 states and 460128 transitions. [2019-12-07 18:28:41,314 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:28:41,314 INFO L276 IsEmpty]: Start isEmpty. Operand 107958 states and 460128 transitions. [2019-12-07 18:28:41,317 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-12-07 18:28:41,318 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:28:41,318 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:28:41,318 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:28:41,318 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:28:41,318 INFO L82 PathProgramCache]: Analyzing trace with hash 2082409598, now seen corresponding path program 1 times [2019-12-07 18:28:41,318 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:28:41,318 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [492307172] [2019-12-07 18:28:41,319 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:28:41,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:28:41,375 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:28:41,376 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [492307172] [2019-12-07 18:28:41,376 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:28:41,376 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:28:41,376 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1306377307] [2019-12-07 18:28:41,377 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:28:41,377 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:28:41,377 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:28:41,378 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:28:41,378 INFO L87 Difference]: Start difference. First operand 107958 states and 460128 transitions. Second operand 4 states. [2019-12-07 18:28:42,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:28:42,349 INFO L93 Difference]: Finished difference Result 172022 states and 703369 transitions. [2019-12-07 18:28:42,350 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:28:42,350 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-12-07 18:28:42,350 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:28:43,249 INFO L225 Difference]: With dead ends: 172022 [2019-12-07 18:28:43,249 INFO L226 Difference]: Without dead ends: 171924 [2019-12-07 18:28:43,250 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:28:50,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171924 states. [2019-12-07 18:28:52,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171924 to 156115. [2019-12-07 18:28:52,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 156115 states. [2019-12-07 18:28:53,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156115 states to 156115 states and 647087 transitions. [2019-12-07 18:28:53,237 INFO L78 Accepts]: Start accepts. Automaton has 156115 states and 647087 transitions. Word has length 11 [2019-12-07 18:28:53,238 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:28:53,238 INFO L462 AbstractCegarLoop]: Abstraction has 156115 states and 647087 transitions. [2019-12-07 18:28:53,238 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:28:53,238 INFO L276 IsEmpty]: Start isEmpty. Operand 156115 states and 647087 transitions. [2019-12-07 18:28:53,244 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 18:28:53,244 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:28:53,245 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:28:53,245 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:28:53,245 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:28:53,245 INFO L82 PathProgramCache]: Analyzing trace with hash 594088235, now seen corresponding path program 1 times [2019-12-07 18:28:53,245 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:28:53,245 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2069438649] [2019-12-07 18:28:53,246 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:28:53,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:28:53,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:28:53,301 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2069438649] [2019-12-07 18:28:53,301 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:28:53,302 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:28:53,302 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1826115122] [2019-12-07 18:28:53,302 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:28:53,302 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:28:53,302 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:28:53,303 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:28:53,303 INFO L87 Difference]: Start difference. First operand 156115 states and 647087 transitions. Second operand 4 states. [2019-12-07 18:28:54,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:28:54,508 INFO L93 Difference]: Finished difference Result 219290 states and 888852 transitions. [2019-12-07 18:28:54,509 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:28:54,509 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 18:28:54,509 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:28:55,086 INFO L225 Difference]: With dead ends: 219290 [2019-12-07 18:28:55,086 INFO L226 Difference]: Without dead ends: 219178 [2019-12-07 18:28:55,086 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:29:01,328 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 219178 states. [2019-12-07 18:29:06,300 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 219178 to 184451. [2019-12-07 18:29:06,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 184451 states. [2019-12-07 18:29:06,949 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 184451 states to 184451 states and 760798 transitions. [2019-12-07 18:29:06,950 INFO L78 Accepts]: Start accepts. Automaton has 184451 states and 760798 transitions. Word has length 13 [2019-12-07 18:29:06,950 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:29:06,950 INFO L462 AbstractCegarLoop]: Abstraction has 184451 states and 760798 transitions. [2019-12-07 18:29:06,951 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:29:06,951 INFO L276 IsEmpty]: Start isEmpty. Operand 184451 states and 760798 transitions. [2019-12-07 18:29:06,959 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2019-12-07 18:29:06,959 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:29:06,959 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:29:06,960 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:29:06,960 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:29:06,960 INFO L82 PathProgramCache]: Analyzing trace with hash -805978823, now seen corresponding path program 1 times [2019-12-07 18:29:06,960 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:29:06,960 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1660489908] [2019-12-07 18:29:06,960 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:29:06,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:29:06,997 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:29:06,997 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1660489908] [2019-12-07 18:29:06,998 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:29:06,998 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:29:06,998 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1822867473] [2019-12-07 18:29:06,998 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:29:06,998 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:29:06,998 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:29:06,998 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:29:06,998 INFO L87 Difference]: Start difference. First operand 184451 states and 760798 transitions. Second operand 3 states. [2019-12-07 18:29:08,563 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:29:08,563 INFO L93 Difference]: Finished difference Result 284614 states and 1168466 transitions. [2019-12-07 18:29:08,564 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:29:08,564 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 16 [2019-12-07 18:29:08,564 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:29:09,326 INFO L225 Difference]: With dead ends: 284614 [2019-12-07 18:29:09,326 INFO L226 Difference]: Without dead ends: 284614 [2019-12-07 18:29:09,327 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:29:16,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284614 states. [2019-12-07 18:29:22,258 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284614 to 221232. [2019-12-07 18:29:22,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 221232 states. [2019-12-07 18:29:23,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 221232 states to 221232 states and 911865 transitions. [2019-12-07 18:29:23,248 INFO L78 Accepts]: Start accepts. Automaton has 221232 states and 911865 transitions. Word has length 16 [2019-12-07 18:29:23,248 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:29:23,248 INFO L462 AbstractCegarLoop]: Abstraction has 221232 states and 911865 transitions. [2019-12-07 18:29:23,248 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:29:23,248 INFO L276 IsEmpty]: Start isEmpty. Operand 221232 states and 911865 transitions. [2019-12-07 18:29:23,255 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2019-12-07 18:29:23,256 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:29:23,256 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:29:23,256 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:29:23,256 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:29:23,256 INFO L82 PathProgramCache]: Analyzing trace with hash -805853304, now seen corresponding path program 1 times [2019-12-07 18:29:23,256 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:29:23,257 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1005202162] [2019-12-07 18:29:23,257 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:29:23,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:29:23,298 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:29:23,298 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1005202162] [2019-12-07 18:29:23,298 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:29:23,299 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:29:23,299 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1467920495] [2019-12-07 18:29:23,299 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:29:23,299 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:29:23,299 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:29:23,299 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:29:23,299 INFO L87 Difference]: Start difference. First operand 221232 states and 911865 transitions. Second operand 4 states. [2019-12-07 18:29:24,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:29:24,669 INFO L93 Difference]: Finished difference Result 262568 states and 1070974 transitions. [2019-12-07 18:29:24,670 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:29:24,670 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2019-12-07 18:29:24,670 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:29:25,886 INFO L225 Difference]: With dead ends: 262568 [2019-12-07 18:29:25,886 INFO L226 Difference]: Without dead ends: 262568 [2019-12-07 18:29:25,886 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:29:32,701 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 262568 states. [2019-12-07 18:29:36,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 262568 to 233184. [2019-12-07 18:29:36,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 233184 states. [2019-12-07 18:29:37,064 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 233184 states to 233184 states and 959818 transitions. [2019-12-07 18:29:37,065 INFO L78 Accepts]: Start accepts. Automaton has 233184 states and 959818 transitions. Word has length 16 [2019-12-07 18:29:37,065 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:29:37,065 INFO L462 AbstractCegarLoop]: Abstraction has 233184 states and 959818 transitions. [2019-12-07 18:29:37,065 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:29:37,065 INFO L276 IsEmpty]: Start isEmpty. Operand 233184 states and 959818 transitions. [2019-12-07 18:29:37,071 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2019-12-07 18:29:37,071 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:29:37,071 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:29:37,071 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:29:37,071 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:29:37,071 INFO L82 PathProgramCache]: Analyzing trace with hash -1222928522, now seen corresponding path program 1 times [2019-12-07 18:29:37,071 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:29:37,072 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1387165720] [2019-12-07 18:29:37,072 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:29:37,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:29:37,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:29:37,110 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1387165720] [2019-12-07 18:29:37,110 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:29:37,110 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:29:37,110 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1069720601] [2019-12-07 18:29:37,111 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:29:37,111 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:29:37,111 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:29:37,111 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:29:37,111 INFO L87 Difference]: Start difference. First operand 233184 states and 959818 transitions. Second operand 4 states. [2019-12-07 18:29:41,162 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:29:41,162 INFO L93 Difference]: Finished difference Result 277148 states and 1134062 transitions. [2019-12-07 18:29:41,163 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:29:41,163 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2019-12-07 18:29:41,163 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:29:41,883 INFO L225 Difference]: With dead ends: 277148 [2019-12-07 18:29:41,883 INFO L226 Difference]: Without dead ends: 277148 [2019-12-07 18:29:41,884 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:29:48,399 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 277148 states. [2019-12-07 18:29:52,268 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 277148 to 236057. [2019-12-07 18:29:52,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 236057 states. [2019-12-07 18:29:53,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 236057 states to 236057 states and 972653 transitions. [2019-12-07 18:29:53,061 INFO L78 Accepts]: Start accepts. Automaton has 236057 states and 972653 transitions. Word has length 16 [2019-12-07 18:29:53,061 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:29:53,061 INFO L462 AbstractCegarLoop]: Abstraction has 236057 states and 972653 transitions. [2019-12-07 18:29:53,061 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:29:53,061 INFO L276 IsEmpty]: Start isEmpty. Operand 236057 states and 972653 transitions. [2019-12-07 18:29:53,073 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2019-12-07 18:29:53,073 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:29:53,073 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:29:53,073 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:29:53,074 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:29:53,074 INFO L82 PathProgramCache]: Analyzing trace with hash -2141168645, now seen corresponding path program 1 times [2019-12-07 18:29:53,074 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:29:53,074 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1312409747] [2019-12-07 18:29:53,074 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:29:53,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:29:53,520 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:29:53,520 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1312409747] [2019-12-07 18:29:53,521 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:29:53,521 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 18:29:53,521 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [849160145] [2019-12-07 18:29:53,521 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:29:53,521 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:29:53,522 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:29:53,522 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:29:53,522 INFO L87 Difference]: Start difference. First operand 236057 states and 972653 transitions. Second operand 3 states. [2019-12-07 18:29:56,031 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:29:56,031 INFO L93 Difference]: Finished difference Result 419928 states and 1722928 transitions. [2019-12-07 18:29:56,032 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:29:56,032 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 18 [2019-12-07 18:29:56,032 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:29:56,994 INFO L225 Difference]: With dead ends: 419928 [2019-12-07 18:29:56,994 INFO L226 Difference]: Without dead ends: 386621 [2019-12-07 18:29:56,995 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:30:04,584 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 386621 states. [2019-12-07 18:30:10,479 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 386621 to 371396. [2019-12-07 18:30:10,479 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 371396 states. [2019-12-07 18:30:12,098 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 371396 states to 371396 states and 1535333 transitions. [2019-12-07 18:30:12,098 INFO L78 Accepts]: Start accepts. Automaton has 371396 states and 1535333 transitions. Word has length 18 [2019-12-07 18:30:12,098 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:30:12,098 INFO L462 AbstractCegarLoop]: Abstraction has 371396 states and 1535333 transitions. [2019-12-07 18:30:12,099 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:30:12,099 INFO L276 IsEmpty]: Start isEmpty. Operand 371396 states and 1535333 transitions. [2019-12-07 18:30:12,129 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 18:30:12,129 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:30:12,129 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:30:12,129 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:30:12,129 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:30:12,129 INFO L82 PathProgramCache]: Analyzing trace with hash -1067747929, now seen corresponding path program 1 times [2019-12-07 18:30:12,129 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:30:12,129 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1228753240] [2019-12-07 18:30:12,130 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:30:12,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:30:12,184 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:30:12,185 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1228753240] [2019-12-07 18:30:12,185 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:30:12,185 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:30:12,185 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1090537743] [2019-12-07 18:30:12,185 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:30:12,185 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:30:12,186 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:30:12,186 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:30:12,186 INFO L87 Difference]: Start difference. First operand 371396 states and 1535333 transitions. Second operand 4 states. [2019-12-07 18:30:17,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:30:17,405 INFO L93 Difference]: Finished difference Result 385817 states and 1580823 transitions. [2019-12-07 18:30:17,406 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 18:30:17,406 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 19 [2019-12-07 18:30:17,406 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:30:18,407 INFO L225 Difference]: With dead ends: 385817 [2019-12-07 18:30:18,407 INFO L226 Difference]: Without dead ends: 385817 [2019-12-07 18:30:18,408 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:30:26,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 385817 states. [2019-12-07 18:30:32,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 385817 to 367892. [2019-12-07 18:30:32,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 367892 states. [2019-12-07 18:30:33,955 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 367892 states to 367892 states and 1521919 transitions. [2019-12-07 18:30:33,956 INFO L78 Accepts]: Start accepts. Automaton has 367892 states and 1521919 transitions. Word has length 19 [2019-12-07 18:30:33,956 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:30:33,956 INFO L462 AbstractCegarLoop]: Abstraction has 367892 states and 1521919 transitions. [2019-12-07 18:30:33,956 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:30:33,956 INFO L276 IsEmpty]: Start isEmpty. Operand 367892 states and 1521919 transitions. [2019-12-07 18:30:33,986 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 18:30:33,986 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:30:33,986 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:30:33,986 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:30:33,986 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:30:33,986 INFO L82 PathProgramCache]: Analyzing trace with hash 700766782, now seen corresponding path program 1 times [2019-12-07 18:30:33,986 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:30:33,986 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [536318892] [2019-12-07 18:30:33,987 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:30:33,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:30:34,020 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:30:34,021 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [536318892] [2019-12-07 18:30:34,021 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:30:34,021 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:30:34,021 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [568839713] [2019-12-07 18:30:34,021 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:30:34,022 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:30:34,022 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:30:34,022 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:30:34,022 INFO L87 Difference]: Start difference. First operand 367892 states and 1521919 transitions. Second operand 3 states. [2019-12-07 18:30:35,696 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:30:35,696 INFO L93 Difference]: Finished difference Result 346805 states and 1418106 transitions. [2019-12-07 18:30:35,697 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:30:35,697 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 19 [2019-12-07 18:30:35,698 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:30:37,343 INFO L225 Difference]: With dead ends: 346805 [2019-12-07 18:30:37,343 INFO L226 Difference]: Without dead ends: 346805 [2019-12-07 18:30:37,343 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:30:44,267 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 346805 states. [2019-12-07 18:30:52,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 346805 to 343459. [2019-12-07 18:30:52,712 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 343459 states. [2019-12-07 18:30:54,197 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 343459 states to 343459 states and 1405774 transitions. [2019-12-07 18:30:54,197 INFO L78 Accepts]: Start accepts. Automaton has 343459 states and 1405774 transitions. Word has length 19 [2019-12-07 18:30:54,198 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:30:54,198 INFO L462 AbstractCegarLoop]: Abstraction has 343459 states and 1405774 transitions. [2019-12-07 18:30:54,198 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:30:54,198 INFO L276 IsEmpty]: Start isEmpty. Operand 343459 states and 1405774 transitions. [2019-12-07 18:30:54,222 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 18:30:54,222 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:30:54,222 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:30:54,222 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:30:54,222 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:30:54,222 INFO L82 PathProgramCache]: Analyzing trace with hash -116744345, now seen corresponding path program 1 times [2019-12-07 18:30:54,222 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:30:54,223 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [561572948] [2019-12-07 18:30:54,223 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:30:54,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:30:54,253 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:30:54,253 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [561572948] [2019-12-07 18:30:54,254 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:30:54,254 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:30:54,254 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [484159525] [2019-12-07 18:30:54,254 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:30:54,254 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:30:54,254 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:30:54,255 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:30:54,255 INFO L87 Difference]: Start difference. First operand 343459 states and 1405774 transitions. Second operand 5 states. [2019-12-07 18:30:57,393 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:30:57,393 INFO L93 Difference]: Finished difference Result 481018 states and 1929261 transitions. [2019-12-07 18:30:57,394 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:30:57,394 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 18:30:57,394 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:30:59,192 INFO L225 Difference]: With dead ends: 481018 [2019-12-07 18:30:59,193 INFO L226 Difference]: Without dead ends: 480836 [2019-12-07 18:30:59,193 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:31:07,610 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 480836 states. [2019-12-07 18:31:13,763 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 480836 to 364743. [2019-12-07 18:31:13,763 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 364743 states. [2019-12-07 18:31:15,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 364743 states to 364743 states and 1489285 transitions. [2019-12-07 18:31:15,374 INFO L78 Accepts]: Start accepts. Automaton has 364743 states and 1489285 transitions. Word has length 19 [2019-12-07 18:31:15,374 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:31:15,374 INFO L462 AbstractCegarLoop]: Abstraction has 364743 states and 1489285 transitions. [2019-12-07 18:31:15,374 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:31:15,374 INFO L276 IsEmpty]: Start isEmpty. Operand 364743 states and 1489285 transitions. [2019-12-07 18:31:15,399 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 18:31:15,399 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:31:15,399 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:31:15,399 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:31:15,399 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:31:15,399 INFO L82 PathProgramCache]: Analyzing trace with hash 1088543872, now seen corresponding path program 1 times [2019-12-07 18:31:15,400 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:31:15,400 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [239044183] [2019-12-07 18:31:15,400 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:31:15,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:31:15,432 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:31:15,432 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [239044183] [2019-12-07 18:31:15,432 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:31:15,432 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:31:15,432 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2046614085] [2019-12-07 18:31:15,433 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:31:15,433 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:31:15,433 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:31:15,433 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:31:15,433 INFO L87 Difference]: Start difference. First operand 364743 states and 1489285 transitions. Second operand 3 states. [2019-12-07 18:31:15,676 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:31:15,676 INFO L93 Difference]: Finished difference Result 67472 states and 218112 transitions. [2019-12-07 18:31:15,677 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:31:15,677 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 19 [2019-12-07 18:31:15,677 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:31:15,788 INFO L225 Difference]: With dead ends: 67472 [2019-12-07 18:31:15,789 INFO L226 Difference]: Without dead ends: 67472 [2019-12-07 18:31:15,789 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:31:16,054 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67472 states. [2019-12-07 18:31:19,738 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67472 to 67472. [2019-12-07 18:31:19,738 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 67472 states. [2019-12-07 18:31:19,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67472 states to 67472 states and 218112 transitions. [2019-12-07 18:31:19,872 INFO L78 Accepts]: Start accepts. Automaton has 67472 states and 218112 transitions. Word has length 19 [2019-12-07 18:31:19,872 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:31:19,872 INFO L462 AbstractCegarLoop]: Abstraction has 67472 states and 218112 transitions. [2019-12-07 18:31:19,872 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:31:19,872 INFO L276 IsEmpty]: Start isEmpty. Operand 67472 states and 218112 transitions. [2019-12-07 18:31:19,879 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2019-12-07 18:31:19,879 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:31:19,879 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:31:19,879 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:31:19,879 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:31:19,879 INFO L82 PathProgramCache]: Analyzing trace with hash -655013944, now seen corresponding path program 1 times [2019-12-07 18:31:19,880 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:31:19,880 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [526134435] [2019-12-07 18:31:19,880 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:31:19,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:31:19,910 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:31:19,910 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [526134435] [2019-12-07 18:31:19,910 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:31:19,910 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:31:19,910 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [603012930] [2019-12-07 18:31:19,910 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:31:19,911 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:31:19,911 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:31:19,911 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:31:19,911 INFO L87 Difference]: Start difference. First operand 67472 states and 218112 transitions. Second operand 5 states. [2019-12-07 18:31:20,402 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:31:20,402 INFO L93 Difference]: Finished difference Result 88451 states and 279620 transitions. [2019-12-07 18:31:20,402 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:31:20,402 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 22 [2019-12-07 18:31:20,403 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:31:20,531 INFO L225 Difference]: With dead ends: 88451 [2019-12-07 18:31:20,532 INFO L226 Difference]: Without dead ends: 88437 [2019-12-07 18:31:20,532 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:31:20,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88437 states. [2019-12-07 18:31:21,714 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88437 to 71798. [2019-12-07 18:31:21,714 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 71798 states. [2019-12-07 18:31:21,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71798 states to 71798 states and 231108 transitions. [2019-12-07 18:31:21,864 INFO L78 Accepts]: Start accepts. Automaton has 71798 states and 231108 transitions. Word has length 22 [2019-12-07 18:31:21,864 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:31:21,865 INFO L462 AbstractCegarLoop]: Abstraction has 71798 states and 231108 transitions. [2019-12-07 18:31:21,865 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:31:21,865 INFO L276 IsEmpty]: Start isEmpty. Operand 71798 states and 231108 transitions. [2019-12-07 18:31:21,872 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2019-12-07 18:31:21,872 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:31:21,872 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:31:21,872 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:31:21,872 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:31:21,872 INFO L82 PathProgramCache]: Analyzing trace with hash -2032339914, now seen corresponding path program 1 times [2019-12-07 18:31:21,872 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:31:21,873 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [28460081] [2019-12-07 18:31:21,873 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:31:21,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:31:22,022 WARN L192 SmtUtils]: Spent 125.00 ms on a formula simplification that was a NOOP. DAG size: 3 [2019-12-07 18:31:22,029 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:31:22,030 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [28460081] [2019-12-07 18:31:22,030 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:31:22,030 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:31:22,030 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1484048801] [2019-12-07 18:31:22,030 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:31:22,030 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:31:22,030 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:31:22,031 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:31:22,031 INFO L87 Difference]: Start difference. First operand 71798 states and 231108 transitions. Second operand 5 states. [2019-12-07 18:31:22,534 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:31:22,534 INFO L93 Difference]: Finished difference Result 91330 states and 289623 transitions. [2019-12-07 18:31:22,534 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:31:22,534 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 22 [2019-12-07 18:31:22,534 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:31:22,670 INFO L225 Difference]: With dead ends: 91330 [2019-12-07 18:31:22,670 INFO L226 Difference]: Without dead ends: 91316 [2019-12-07 18:31:22,670 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:31:22,992 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91316 states. [2019-12-07 18:31:23,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91316 to 69605. [2019-12-07 18:31:23,852 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69605 states. [2019-12-07 18:31:23,996 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69605 states to 69605 states and 224450 transitions. [2019-12-07 18:31:23,996 INFO L78 Accepts]: Start accepts. Automaton has 69605 states and 224450 transitions. Word has length 22 [2019-12-07 18:31:23,997 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:31:23,997 INFO L462 AbstractCegarLoop]: Abstraction has 69605 states and 224450 transitions. [2019-12-07 18:31:23,997 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:31:23,997 INFO L276 IsEmpty]: Start isEmpty. Operand 69605 states and 224450 transitions. [2019-12-07 18:31:24,012 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2019-12-07 18:31:24,012 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:31:24,012 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:31:24,013 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:31:24,013 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:31:24,013 INFO L82 PathProgramCache]: Analyzing trace with hash -1083173402, now seen corresponding path program 1 times [2019-12-07 18:31:24,013 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:31:24,013 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2106638835] [2019-12-07 18:31:24,013 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:31:24,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:31:24,046 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:31:24,047 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2106638835] [2019-12-07 18:31:24,047 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:31:24,047 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:31:24,047 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [957291276] [2019-12-07 18:31:24,047 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:31:24,048 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:31:24,048 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:31:24,048 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:31:24,048 INFO L87 Difference]: Start difference. First operand 69605 states and 224450 transitions. Second operand 5 states. [2019-12-07 18:31:24,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:31:24,478 INFO L93 Difference]: Finished difference Result 86092 states and 273664 transitions. [2019-12-07 18:31:24,479 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 18:31:24,479 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 26 [2019-12-07 18:31:24,479 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:31:24,765 INFO L225 Difference]: With dead ends: 86092 [2019-12-07 18:31:24,765 INFO L226 Difference]: Without dead ends: 86044 [2019-12-07 18:31:24,766 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:31:25,063 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86044 states. [2019-12-07 18:31:25,865 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86044 to 73017. [2019-12-07 18:31:25,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73017 states. [2019-12-07 18:31:26,019 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73017 states to 73017 states and 234757 transitions. [2019-12-07 18:31:26,019 INFO L78 Accepts]: Start accepts. Automaton has 73017 states and 234757 transitions. Word has length 26 [2019-12-07 18:31:26,019 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:31:26,019 INFO L462 AbstractCegarLoop]: Abstraction has 73017 states and 234757 transitions. [2019-12-07 18:31:26,019 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:31:26,019 INFO L276 IsEmpty]: Start isEmpty. Operand 73017 states and 234757 transitions. [2019-12-07 18:31:26,041 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-12-07 18:31:26,041 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:31:26,041 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:31:26,041 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:31:26,041 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:31:26,041 INFO L82 PathProgramCache]: Analyzing trace with hash -799804073, now seen corresponding path program 1 times [2019-12-07 18:31:26,042 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:31:26,042 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1614980890] [2019-12-07 18:31:26,042 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:31:26,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:31:26,085 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:31:26,085 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1614980890] [2019-12-07 18:31:26,085 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:31:26,085 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:31:26,085 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [89250084] [2019-12-07 18:31:26,086 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:31:26,086 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:31:26,086 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:31:26,086 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:31:26,086 INFO L87 Difference]: Start difference. First operand 73017 states and 234757 transitions. Second operand 5 states. [2019-12-07 18:31:26,522 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:31:26,522 INFO L93 Difference]: Finished difference Result 87024 states and 275380 transitions. [2019-12-07 18:31:26,522 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 18:31:26,522 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 28 [2019-12-07 18:31:26,522 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:31:26,645 INFO L225 Difference]: With dead ends: 87024 [2019-12-07 18:31:26,645 INFO L226 Difference]: Without dead ends: 86980 [2019-12-07 18:31:26,645 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:31:26,964 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86980 states. [2019-12-07 18:31:27,898 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86980 to 72137. [2019-12-07 18:31:27,898 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72137 states. [2019-12-07 18:31:28,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72137 states to 72137 states and 232084 transitions. [2019-12-07 18:31:28,049 INFO L78 Accepts]: Start accepts. Automaton has 72137 states and 232084 transitions. Word has length 28 [2019-12-07 18:31:28,049 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:31:28,049 INFO L462 AbstractCegarLoop]: Abstraction has 72137 states and 232084 transitions. [2019-12-07 18:31:28,049 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:31:28,050 INFO L276 IsEmpty]: Start isEmpty. Operand 72137 states and 232084 transitions. [2019-12-07 18:31:28,074 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2019-12-07 18:31:28,074 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:31:28,074 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:31:28,074 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:31:28,074 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:31:28,074 INFO L82 PathProgramCache]: Analyzing trace with hash -1469523336, now seen corresponding path program 1 times [2019-12-07 18:31:28,074 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:31:28,075 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [785643453] [2019-12-07 18:31:28,075 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:31:28,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:31:28,104 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:31:28,104 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [785643453] [2019-12-07 18:31:28,105 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:31:28,105 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:31:28,105 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1149250809] [2019-12-07 18:31:28,105 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:31:28,105 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:31:28,105 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:31:28,106 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:31:28,106 INFO L87 Difference]: Start difference. First operand 72137 states and 232084 transitions. Second operand 4 states. [2019-12-07 18:31:28,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:31:28,196 INFO L93 Difference]: Finished difference Result 27979 states and 86655 transitions. [2019-12-07 18:31:28,196 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 18:31:28,196 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 30 [2019-12-07 18:31:28,196 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:31:28,233 INFO L225 Difference]: With dead ends: 27979 [2019-12-07 18:31:28,234 INFO L226 Difference]: Without dead ends: 27979 [2019-12-07 18:31:28,234 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:31:28,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27979 states. [2019-12-07 18:31:28,598 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27979 to 25500. [2019-12-07 18:31:28,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25500 states. [2019-12-07 18:31:28,647 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25500 states to 25500 states and 79033 transitions. [2019-12-07 18:31:28,647 INFO L78 Accepts]: Start accepts. Automaton has 25500 states and 79033 transitions. Word has length 30 [2019-12-07 18:31:28,648 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:31:28,648 INFO L462 AbstractCegarLoop]: Abstraction has 25500 states and 79033 transitions. [2019-12-07 18:31:28,648 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:31:28,648 INFO L276 IsEmpty]: Start isEmpty. Operand 25500 states and 79033 transitions. [2019-12-07 18:31:28,666 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2019-12-07 18:31:28,666 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:31:28,667 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:31:28,667 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:31:28,667 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:31:28,667 INFO L82 PathProgramCache]: Analyzing trace with hash -145847770, now seen corresponding path program 1 times [2019-12-07 18:31:28,667 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:31:28,667 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [476191659] [2019-12-07 18:31:28,667 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:31:28,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:31:28,712 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:31:28,712 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [476191659] [2019-12-07 18:31:28,713 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:31:28,713 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:31:28,713 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1775194815] [2019-12-07 18:31:28,713 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:31:28,713 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:31:28,713 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:31:28,714 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:31:28,714 INFO L87 Difference]: Start difference. First operand 25500 states and 79033 transitions. Second operand 6 states. [2019-12-07 18:31:29,149 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:31:29,149 INFO L93 Difference]: Finished difference Result 32400 states and 98245 transitions. [2019-12-07 18:31:29,150 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 18:31:29,150 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 32 [2019-12-07 18:31:29,150 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:31:29,190 INFO L225 Difference]: With dead ends: 32400 [2019-12-07 18:31:29,190 INFO L226 Difference]: Without dead ends: 32400 [2019-12-07 18:31:29,190 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=111, Unknown=0, NotChecked=0, Total=156 [2019-12-07 18:31:29,293 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32400 states. [2019-12-07 18:31:29,618 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32400 to 25938. [2019-12-07 18:31:29,618 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25938 states. [2019-12-07 18:31:29,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25938 states to 25938 states and 80337 transitions. [2019-12-07 18:31:29,671 INFO L78 Accepts]: Start accepts. Automaton has 25938 states and 80337 transitions. Word has length 32 [2019-12-07 18:31:29,671 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:31:29,671 INFO L462 AbstractCegarLoop]: Abstraction has 25938 states and 80337 transitions. [2019-12-07 18:31:29,671 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:31:29,671 INFO L276 IsEmpty]: Start isEmpty. Operand 25938 states and 80337 transitions. [2019-12-07 18:31:29,694 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 18:31:29,694 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:31:29,694 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:31:29,694 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:31:29,694 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:31:29,694 INFO L82 PathProgramCache]: Analyzing trace with hash -1380765993, now seen corresponding path program 1 times [2019-12-07 18:31:29,694 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:31:29,695 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [774108225] [2019-12-07 18:31:29,695 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:31:29,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:31:29,759 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:31:29,760 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [774108225] [2019-12-07 18:31:29,760 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:31:29,760 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:31:29,760 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [555401426] [2019-12-07 18:31:29,761 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:31:29,761 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:31:29,761 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:31:29,761 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:31:29,761 INFO L87 Difference]: Start difference. First operand 25938 states and 80337 transitions. Second operand 6 states. [2019-12-07 18:31:30,237 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:31:30,237 INFO L93 Difference]: Finished difference Result 31899 states and 96883 transitions. [2019-12-07 18:31:30,237 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 18:31:30,238 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 34 [2019-12-07 18:31:30,238 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:31:30,282 INFO L225 Difference]: With dead ends: 31899 [2019-12-07 18:31:30,283 INFO L226 Difference]: Without dead ends: 31899 [2019-12-07 18:31:30,283 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=111, Unknown=0, NotChecked=0, Total=156 [2019-12-07 18:31:30,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31899 states. [2019-12-07 18:31:30,697 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31899 to 24780. [2019-12-07 18:31:30,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24780 states. [2019-12-07 18:31:30,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24780 states to 24780 states and 76926 transitions. [2019-12-07 18:31:30,749 INFO L78 Accepts]: Start accepts. Automaton has 24780 states and 76926 transitions. Word has length 34 [2019-12-07 18:31:30,749 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:31:30,750 INFO L462 AbstractCegarLoop]: Abstraction has 24780 states and 76926 transitions. [2019-12-07 18:31:30,750 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:31:30,750 INFO L276 IsEmpty]: Start isEmpty. Operand 24780 states and 76926 transitions. [2019-12-07 18:31:30,773 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2019-12-07 18:31:30,773 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:31:30,773 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:31:30,774 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:31:30,774 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:31:30,774 INFO L82 PathProgramCache]: Analyzing trace with hash 1174419869, now seen corresponding path program 1 times [2019-12-07 18:31:30,774 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:31:30,774 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [903560700] [2019-12-07 18:31:30,774 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:31:30,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:31:30,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:31:30,822 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [903560700] [2019-12-07 18:31:30,822 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:31:30,823 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:31:30,823 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [464159504] [2019-12-07 18:31:30,823 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:31:30,823 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:31:30,823 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:31:30,823 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:31:30,823 INFO L87 Difference]: Start difference. First operand 24780 states and 76926 transitions. Second operand 5 states. [2019-12-07 18:31:31,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:31:31,268 INFO L93 Difference]: Finished difference Result 36358 states and 111275 transitions. [2019-12-07 18:31:31,269 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 18:31:31,269 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 41 [2019-12-07 18:31:31,269 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:31:31,314 INFO L225 Difference]: With dead ends: 36358 [2019-12-07 18:31:31,314 INFO L226 Difference]: Without dead ends: 36358 [2019-12-07 18:31:31,314 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:31:31,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36358 states. [2019-12-07 18:31:31,797 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36358 to 31699. [2019-12-07 18:31:31,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31699 states. [2019-12-07 18:31:31,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31699 states to 31699 states and 98212 transitions. [2019-12-07 18:31:31,858 INFO L78 Accepts]: Start accepts. Automaton has 31699 states and 98212 transitions. Word has length 41 [2019-12-07 18:31:31,858 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:31:31,858 INFO L462 AbstractCegarLoop]: Abstraction has 31699 states and 98212 transitions. [2019-12-07 18:31:31,858 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:31:31,858 INFO L276 IsEmpty]: Start isEmpty. Operand 31699 states and 98212 transitions. [2019-12-07 18:31:31,889 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2019-12-07 18:31:31,889 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:31:31,889 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:31:31,890 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:31:31,890 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:31:31,890 INFO L82 PathProgramCache]: Analyzing trace with hash 1274395705, now seen corresponding path program 2 times [2019-12-07 18:31:31,890 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:31:31,890 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [592619583] [2019-12-07 18:31:31,890 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:31:31,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:31:31,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:31:31,928 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [592619583] [2019-12-07 18:31:31,928 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:31:31,928 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:31:31,928 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1439681645] [2019-12-07 18:31:31,928 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:31:31,928 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:31:31,928 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:31:31,928 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:31:31,928 INFO L87 Difference]: Start difference. First operand 31699 states and 98212 transitions. Second operand 5 states. [2019-12-07 18:31:32,021 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:31:32,022 INFO L93 Difference]: Finished difference Result 29593 states and 93482 transitions. [2019-12-07 18:31:32,022 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:31:32,022 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 41 [2019-12-07 18:31:32,022 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:31:32,064 INFO L225 Difference]: With dead ends: 29593 [2019-12-07 18:31:32,065 INFO L226 Difference]: Without dead ends: 29365 [2019-12-07 18:31:32,065 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:31:32,164 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29365 states. [2019-12-07 18:31:32,419 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29365 to 18223. [2019-12-07 18:31:32,419 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18223 states. [2019-12-07 18:31:32,450 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18223 states to 18223 states and 57294 transitions. [2019-12-07 18:31:32,450 INFO L78 Accepts]: Start accepts. Automaton has 18223 states and 57294 transitions. Word has length 41 [2019-12-07 18:31:32,450 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:31:32,450 INFO L462 AbstractCegarLoop]: Abstraction has 18223 states and 57294 transitions. [2019-12-07 18:31:32,450 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:31:32,450 INFO L276 IsEmpty]: Start isEmpty. Operand 18223 states and 57294 transitions. [2019-12-07 18:31:32,466 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2019-12-07 18:31:32,466 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:31:32,466 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:31:32,466 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:31:32,466 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:31:32,467 INFO L82 PathProgramCache]: Analyzing trace with hash 1306345889, now seen corresponding path program 1 times [2019-12-07 18:31:32,467 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:31:32,467 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1928435251] [2019-12-07 18:31:32,467 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:31:32,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:31:32,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:31:32,518 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1928435251] [2019-12-07 18:31:32,518 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:31:32,518 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:31:32,519 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1574885256] [2019-12-07 18:31:32,519 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:31:32,519 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:31:32,519 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:31:32,519 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:31:32,519 INFO L87 Difference]: Start difference. First operand 18223 states and 57294 transitions. Second operand 6 states. [2019-12-07 18:31:33,006 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:31:33,006 INFO L93 Difference]: Finished difference Result 24434 states and 75591 transitions. [2019-12-07 18:31:33,007 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 18:31:33,007 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 64 [2019-12-07 18:31:33,007 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:31:33,035 INFO L225 Difference]: With dead ends: 24434 [2019-12-07 18:31:33,035 INFO L226 Difference]: Without dead ends: 24434 [2019-12-07 18:31:33,035 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2019-12-07 18:31:33,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24434 states. [2019-12-07 18:31:33,331 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24434 to 19099. [2019-12-07 18:31:33,331 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19099 states. [2019-12-07 18:31:33,368 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19099 states to 19099 states and 59998 transitions. [2019-12-07 18:31:33,368 INFO L78 Accepts]: Start accepts. Automaton has 19099 states and 59998 transitions. Word has length 64 [2019-12-07 18:31:33,368 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:31:33,368 INFO L462 AbstractCegarLoop]: Abstraction has 19099 states and 59998 transitions. [2019-12-07 18:31:33,368 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:31:33,368 INFO L276 IsEmpty]: Start isEmpty. Operand 19099 states and 59998 transitions. [2019-12-07 18:31:33,386 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2019-12-07 18:31:33,386 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:31:33,387 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:31:33,387 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:31:33,387 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:31:33,387 INFO L82 PathProgramCache]: Analyzing trace with hash -1813344643, now seen corresponding path program 2 times [2019-12-07 18:31:33,387 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:31:33,387 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1732310617] [2019-12-07 18:31:33,387 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:31:33,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:31:33,453 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:31:33,453 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1732310617] [2019-12-07 18:31:33,453 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:31:33,453 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 18:31:33,454 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [38698202] [2019-12-07 18:31:33,454 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 18:31:33,454 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:31:33,454 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:31:33,454 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:31:33,454 INFO L87 Difference]: Start difference. First operand 19099 states and 59998 transitions. Second operand 7 states. [2019-12-07 18:31:34,886 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:31:34,886 INFO L93 Difference]: Finished difference Result 26732 states and 82068 transitions. [2019-12-07 18:31:34,886 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2019-12-07 18:31:34,886 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 64 [2019-12-07 18:31:34,887 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:31:34,918 INFO L225 Difference]: With dead ends: 26732 [2019-12-07 18:31:34,918 INFO L226 Difference]: Without dead ends: 26732 [2019-12-07 18:31:34,919 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 7 SyntacticMatches, 2 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 101 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=110, Invalid=396, Unknown=0, NotChecked=0, Total=506 [2019-12-07 18:31:35,010 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26732 states. [2019-12-07 18:31:35,219 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26732 to 19211. [2019-12-07 18:31:35,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19211 states. [2019-12-07 18:31:35,251 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19211 states to 19211 states and 60262 transitions. [2019-12-07 18:31:35,251 INFO L78 Accepts]: Start accepts. Automaton has 19211 states and 60262 transitions. Word has length 64 [2019-12-07 18:31:35,251 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:31:35,251 INFO L462 AbstractCegarLoop]: Abstraction has 19211 states and 60262 transitions. [2019-12-07 18:31:35,252 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 18:31:35,252 INFO L276 IsEmpty]: Start isEmpty. Operand 19211 states and 60262 transitions. [2019-12-07 18:31:35,268 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2019-12-07 18:31:35,268 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:31:35,268 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:31:35,268 INFO L410 AbstractCegarLoop]: === Iteration 23 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:31:35,268 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:31:35,268 INFO L82 PathProgramCache]: Analyzing trace with hash 1013389541, now seen corresponding path program 3 times [2019-12-07 18:31:35,269 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:31:35,269 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [547499890] [2019-12-07 18:31:35,269 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:31:35,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:31:35,323 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:31:35,324 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [547499890] [2019-12-07 18:31:35,324 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:31:35,324 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:31:35,324 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1053307415] [2019-12-07 18:31:35,324 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 18:31:35,325 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:31:35,325 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:31:35,325 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:31:35,325 INFO L87 Difference]: Start difference. First operand 19211 states and 60262 transitions. Second operand 7 states. [2019-12-07 18:31:35,698 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:31:35,698 INFO L93 Difference]: Finished difference Result 55054 states and 172444 transitions. [2019-12-07 18:31:35,698 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 18:31:35,698 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 64 [2019-12-07 18:31:35,699 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:31:35,755 INFO L225 Difference]: With dead ends: 55054 [2019-12-07 18:31:35,755 INFO L226 Difference]: Without dead ends: 41813 [2019-12-07 18:31:35,755 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=46, Invalid=136, Unknown=0, NotChecked=0, Total=182 [2019-12-07 18:31:35,880 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41813 states. [2019-12-07 18:31:36,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41813 to 23705. [2019-12-07 18:31:36,246 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23705 states. [2019-12-07 18:31:36,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23705 states to 23705 states and 74427 transitions. [2019-12-07 18:31:36,292 INFO L78 Accepts]: Start accepts. Automaton has 23705 states and 74427 transitions. Word has length 64 [2019-12-07 18:31:36,292 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:31:36,292 INFO L462 AbstractCegarLoop]: Abstraction has 23705 states and 74427 transitions. [2019-12-07 18:31:36,292 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 18:31:36,293 INFO L276 IsEmpty]: Start isEmpty. Operand 23705 states and 74427 transitions. [2019-12-07 18:31:36,316 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2019-12-07 18:31:36,316 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:31:36,316 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:31:36,316 INFO L410 AbstractCegarLoop]: === Iteration 24 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:31:36,316 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:31:36,317 INFO L82 PathProgramCache]: Analyzing trace with hash -1737700513, now seen corresponding path program 4 times [2019-12-07 18:31:36,317 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:31:36,317 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [861594354] [2019-12-07 18:31:36,317 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:31:36,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:31:36,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:31:36,378 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [861594354] [2019-12-07 18:31:36,379 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:31:36,379 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:31:36,379 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1061731234] [2019-12-07 18:31:36,379 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 18:31:36,379 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:31:36,379 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:31:36,380 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:31:36,380 INFO L87 Difference]: Start difference. First operand 23705 states and 74427 transitions. Second operand 7 states. [2019-12-07 18:31:36,730 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:31:36,730 INFO L93 Difference]: Finished difference Result 58571 states and 181283 transitions. [2019-12-07 18:31:36,730 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2019-12-07 18:31:36,730 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 64 [2019-12-07 18:31:36,730 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:31:36,785 INFO L225 Difference]: With dead ends: 58571 [2019-12-07 18:31:36,785 INFO L226 Difference]: Without dead ends: 42536 [2019-12-07 18:31:36,786 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=46, Invalid=136, Unknown=0, NotChecked=0, Total=182 [2019-12-07 18:31:36,913 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42536 states. [2019-12-07 18:31:37,281 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42536 to 26572. [2019-12-07 18:31:37,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26572 states. [2019-12-07 18:31:37,334 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26572 states to 26572 states and 82964 transitions. [2019-12-07 18:31:37,334 INFO L78 Accepts]: Start accepts. Automaton has 26572 states and 82964 transitions. Word has length 64 [2019-12-07 18:31:37,334 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:31:37,334 INFO L462 AbstractCegarLoop]: Abstraction has 26572 states and 82964 transitions. [2019-12-07 18:31:37,334 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 18:31:37,334 INFO L276 IsEmpty]: Start isEmpty. Operand 26572 states and 82964 transitions. [2019-12-07 18:31:37,363 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2019-12-07 18:31:37,363 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:31:37,363 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:31:37,363 INFO L410 AbstractCegarLoop]: === Iteration 25 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:31:37,363 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:31:37,364 INFO L82 PathProgramCache]: Analyzing trace with hash -1780388127, now seen corresponding path program 5 times [2019-12-07 18:31:37,364 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:31:37,364 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [592077741] [2019-12-07 18:31:37,364 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:31:37,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:31:37,414 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:31:37,414 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [592077741] [2019-12-07 18:31:37,414 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:31:37,414 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:31:37,415 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [58661016] [2019-12-07 18:31:37,415 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 18:31:37,415 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:31:37,415 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:31:37,415 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:31:37,415 INFO L87 Difference]: Start difference. First operand 26572 states and 82964 transitions. Second operand 7 states. [2019-12-07 18:31:37,747 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:31:37,747 INFO L93 Difference]: Finished difference Result 57324 states and 178777 transitions. [2019-12-07 18:31:37,747 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-07 18:31:37,748 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 64 [2019-12-07 18:31:37,748 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:31:37,822 INFO L225 Difference]: With dead ends: 57324 [2019-12-07 18:31:37,822 INFO L226 Difference]: Without dead ends: 51512 [2019-12-07 18:31:37,822 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=48, Invalid=134, Unknown=0, NotChecked=0, Total=182 [2019-12-07 18:31:37,970 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51512 states. [2019-12-07 18:31:38,381 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51512 to 26978. [2019-12-07 18:31:38,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26978 states. [2019-12-07 18:31:38,434 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26978 states to 26978 states and 84446 transitions. [2019-12-07 18:31:38,434 INFO L78 Accepts]: Start accepts. Automaton has 26978 states and 84446 transitions. Word has length 64 [2019-12-07 18:31:38,434 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:31:38,434 INFO L462 AbstractCegarLoop]: Abstraction has 26978 states and 84446 transitions. [2019-12-07 18:31:38,434 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 18:31:38,434 INFO L276 IsEmpty]: Start isEmpty. Operand 26978 states and 84446 transitions. [2019-12-07 18:31:38,463 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2019-12-07 18:31:38,463 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:31:38,463 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:31:38,463 INFO L410 AbstractCegarLoop]: === Iteration 26 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:31:38,463 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:31:38,463 INFO L82 PathProgramCache]: Analyzing trace with hash 2010713375, now seen corresponding path program 6 times [2019-12-07 18:31:38,464 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:31:38,464 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1667075767] [2019-12-07 18:31:38,464 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:31:38,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:31:38,522 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:31:38,522 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1667075767] [2019-12-07 18:31:38,522 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:31:38,522 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:31:38,522 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [626826901] [2019-12-07 18:31:38,523 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:31:38,523 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:31:38,523 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:31:38,523 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:31:38,523 INFO L87 Difference]: Start difference. First operand 26978 states and 84446 transitions. Second operand 3 states. [2019-12-07 18:31:38,589 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:31:38,590 INFO L93 Difference]: Finished difference Result 23404 states and 72171 transitions. [2019-12-07 18:31:38,590 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:31:38,590 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 64 [2019-12-07 18:31:38,590 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:31:38,616 INFO L225 Difference]: With dead ends: 23404 [2019-12-07 18:31:38,617 INFO L226 Difference]: Without dead ends: 23404 [2019-12-07 18:31:38,617 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:31:38,748 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23404 states. [2019-12-07 18:31:38,943 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23404 to 21770. [2019-12-07 18:31:38,943 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21770 states. [2019-12-07 18:31:38,981 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21770 states to 21770 states and 67013 transitions. [2019-12-07 18:31:38,981 INFO L78 Accepts]: Start accepts. Automaton has 21770 states and 67013 transitions. Word has length 64 [2019-12-07 18:31:38,981 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:31:38,981 INFO L462 AbstractCegarLoop]: Abstraction has 21770 states and 67013 transitions. [2019-12-07 18:31:38,982 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:31:38,982 INFO L276 IsEmpty]: Start isEmpty. Operand 21770 states and 67013 transitions. [2019-12-07 18:31:39,002 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:31:39,002 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:31:39,003 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:31:39,003 INFO L410 AbstractCegarLoop]: === Iteration 27 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:31:39,003 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:31:39,003 INFO L82 PathProgramCache]: Analyzing trace with hash 903189921, now seen corresponding path program 1 times [2019-12-07 18:31:39,003 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:31:39,003 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [577878037] [2019-12-07 18:31:39,003 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:31:39,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:31:39,142 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:31:39,142 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [577878037] [2019-12-07 18:31:39,142 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:31:39,142 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 18:31:39,142 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1431697264] [2019-12-07 18:31:39,143 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 18:31:39,143 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:31:39,143 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 18:31:39,143 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2019-12-07 18:31:39,143 INFO L87 Difference]: Start difference. First operand 21770 states and 67013 transitions. Second operand 10 states. [2019-12-07 18:31:39,968 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:31:39,968 INFO L93 Difference]: Finished difference Result 32307 states and 99165 transitions. [2019-12-07 18:31:39,968 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 18:31:39,969 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 65 [2019-12-07 18:31:39,969 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:31:40,003 INFO L225 Difference]: With dead ends: 32307 [2019-12-07 18:31:40,003 INFO L226 Difference]: Without dead ends: 26506 [2019-12-07 18:31:40,003 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=68, Invalid=238, Unknown=0, NotChecked=0, Total=306 [2019-12-07 18:31:40,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26506 states. [2019-12-07 18:31:40,317 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26506 to 22206. [2019-12-07 18:31:40,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22206 states. [2019-12-07 18:31:40,357 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22206 states to 22206 states and 68195 transitions. [2019-12-07 18:31:40,357 INFO L78 Accepts]: Start accepts. Automaton has 22206 states and 68195 transitions. Word has length 65 [2019-12-07 18:31:40,358 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:31:40,358 INFO L462 AbstractCegarLoop]: Abstraction has 22206 states and 68195 transitions. [2019-12-07 18:31:40,358 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 18:31:40,358 INFO L276 IsEmpty]: Start isEmpty. Operand 22206 states and 68195 transitions. [2019-12-07 18:31:40,378 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:31:40,378 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:31:40,378 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:31:40,378 INFO L410 AbstractCegarLoop]: === Iteration 28 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:31:40,378 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:31:40,378 INFO L82 PathProgramCache]: Analyzing trace with hash 416369971, now seen corresponding path program 2 times [2019-12-07 18:31:40,378 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:31:40,378 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1051733417] [2019-12-07 18:31:40,379 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:31:40,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:31:40,501 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:31:40,502 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1051733417] [2019-12-07 18:31:40,502 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:31:40,502 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 18:31:40,502 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [840558367] [2019-12-07 18:31:40,502 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 18:31:40,502 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:31:40,503 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 18:31:40,503 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:31:40,503 INFO L87 Difference]: Start difference. First operand 22206 states and 68195 transitions. Second operand 11 states. [2019-12-07 18:31:41,930 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:31:41,930 INFO L93 Difference]: Finished difference Result 32103 states and 97628 transitions. [2019-12-07 18:31:41,931 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 18:31:41,931 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 65 [2019-12-07 18:31:41,931 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:31:41,965 INFO L225 Difference]: With dead ends: 32103 [2019-12-07 18:31:41,965 INFO L226 Difference]: Without dead ends: 27917 [2019-12-07 18:31:41,966 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 35 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=82, Invalid=298, Unknown=0, NotChecked=0, Total=380 [2019-12-07 18:31:42,057 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27917 states. [2019-12-07 18:31:42,300 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27917 to 22336. [2019-12-07 18:31:42,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22336 states. [2019-12-07 18:31:42,342 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22336 states to 22336 states and 68344 transitions. [2019-12-07 18:31:42,342 INFO L78 Accepts]: Start accepts. Automaton has 22336 states and 68344 transitions. Word has length 65 [2019-12-07 18:31:42,343 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:31:42,343 INFO L462 AbstractCegarLoop]: Abstraction has 22336 states and 68344 transitions. [2019-12-07 18:31:42,343 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 18:31:42,343 INFO L276 IsEmpty]: Start isEmpty. Operand 22336 states and 68344 transitions. [2019-12-07 18:31:42,364 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:31:42,364 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:31:42,364 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:31:42,364 INFO L410 AbstractCegarLoop]: === Iteration 29 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:31:42,364 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:31:42,365 INFO L82 PathProgramCache]: Analyzing trace with hash -1050757295, now seen corresponding path program 3 times [2019-12-07 18:31:42,365 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:31:42,365 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2038953686] [2019-12-07 18:31:42,365 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:31:42,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:31:42,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:31:42,628 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2038953686] [2019-12-07 18:31:42,628 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:31:42,628 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 18:31:42,629 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [319417337] [2019-12-07 18:31:42,629 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 18:31:42,629 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:31:42,629 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 18:31:42,629 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=176, Unknown=0, NotChecked=0, Total=210 [2019-12-07 18:31:42,629 INFO L87 Difference]: Start difference. First operand 22336 states and 68344 transitions. Second operand 15 states. [2019-12-07 18:31:51,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:31:51,446 INFO L93 Difference]: Finished difference Result 90980 states and 277238 transitions. [2019-12-07 18:31:51,446 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 88 states. [2019-12-07 18:31:51,446 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 65 [2019-12-07 18:31:51,446 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:31:51,566 INFO L225 Difference]: With dead ends: 90980 [2019-12-07 18:31:51,566 INFO L226 Difference]: Without dead ends: 88165 [2019-12-07 18:31:51,569 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 95 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 92 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3095 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=1326, Invalid=7416, Unknown=0, NotChecked=0, Total=8742 [2019-12-07 18:31:51,793 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88165 states. [2019-12-07 18:31:52,351 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88165 to 25979. [2019-12-07 18:31:52,352 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25979 states. [2019-12-07 18:31:52,402 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25979 states to 25979 states and 78934 transitions. [2019-12-07 18:31:52,403 INFO L78 Accepts]: Start accepts. Automaton has 25979 states and 78934 transitions. Word has length 65 [2019-12-07 18:31:52,403 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:31:52,403 INFO L462 AbstractCegarLoop]: Abstraction has 25979 states and 78934 transitions. [2019-12-07 18:31:52,403 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 18:31:52,403 INFO L276 IsEmpty]: Start isEmpty. Operand 25979 states and 78934 transitions. [2019-12-07 18:31:52,430 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:31:52,430 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:31:52,430 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:31:52,431 INFO L410 AbstractCegarLoop]: === Iteration 30 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:31:52,431 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:31:52,431 INFO L82 PathProgramCache]: Analyzing trace with hash -330874671, now seen corresponding path program 4 times [2019-12-07 18:31:52,431 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:31:52,431 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1797679032] [2019-12-07 18:31:52,431 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:31:52,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:31:52,706 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:31:52,707 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1797679032] [2019-12-07 18:31:52,707 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:31:52,707 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2019-12-07 18:31:52,707 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [842943063] [2019-12-07 18:31:52,707 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-07 18:31:52,707 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:31:52,707 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-07 18:31:52,707 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=172, Unknown=0, NotChecked=0, Total=210 [2019-12-07 18:31:52,707 INFO L87 Difference]: Start difference. First operand 25979 states and 78934 transitions. Second operand 15 states. [2019-12-07 18:32:05,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:32:05,254 INFO L93 Difference]: Finished difference Result 81390 states and 244254 transitions. [2019-12-07 18:32:05,255 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 87 states. [2019-12-07 18:32:05,255 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 65 [2019-12-07 18:32:05,256 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:32:05,361 INFO L225 Difference]: With dead ends: 81390 [2019-12-07 18:32:05,361 INFO L226 Difference]: Without dead ends: 65167 [2019-12-07 18:32:05,365 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 94 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 91 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3017 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=1321, Invalid=7235, Unknown=0, NotChecked=0, Total=8556 [2019-12-07 18:32:05,540 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65167 states. [2019-12-07 18:32:06,029 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65167 to 22183. [2019-12-07 18:32:06,029 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22183 states. [2019-12-07 18:32:06,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22183 states to 22183 states and 67766 transitions. [2019-12-07 18:32:06,067 INFO L78 Accepts]: Start accepts. Automaton has 22183 states and 67766 transitions. Word has length 65 [2019-12-07 18:32:06,067 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:32:06,067 INFO L462 AbstractCegarLoop]: Abstraction has 22183 states and 67766 transitions. [2019-12-07 18:32:06,067 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-07 18:32:06,067 INFO L276 IsEmpty]: Start isEmpty. Operand 22183 states and 67766 transitions. [2019-12-07 18:32:06,086 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:32:06,086 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:32:06,086 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:32:06,087 INFO L410 AbstractCegarLoop]: === Iteration 31 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:32:06,087 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:32:06,087 INFO L82 PathProgramCache]: Analyzing trace with hash -131369463, now seen corresponding path program 5 times [2019-12-07 18:32:06,087 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:32:06,087 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [44832228] [2019-12-07 18:32:06,087 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:32:06,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:32:06,202 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:32:06,203 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [44832228] [2019-12-07 18:32:06,203 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:32:06,203 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 18:32:06,203 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [542222524] [2019-12-07 18:32:06,203 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 18:32:06,203 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:32:06,203 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 18:32:06,203 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:32:06,204 INFO L87 Difference]: Start difference. First operand 22183 states and 67766 transitions. Second operand 11 states. [2019-12-07 18:32:06,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:32:06,816 INFO L93 Difference]: Finished difference Result 29715 states and 90283 transitions. [2019-12-07 18:32:06,816 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2019-12-07 18:32:06,816 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 65 [2019-12-07 18:32:06,816 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:32:06,848 INFO L225 Difference]: With dead ends: 29715 [2019-12-07 18:32:06,848 INFO L226 Difference]: Without dead ends: 25719 [2019-12-07 18:32:06,849 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=59, Invalid=247, Unknown=0, NotChecked=0, Total=306 [2019-12-07 18:32:06,936 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25719 states. [2019-12-07 18:32:07,150 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25719 to 22063. [2019-12-07 18:32:07,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22063 states. [2019-12-07 18:32:07,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22063 states to 22063 states and 67408 transitions. [2019-12-07 18:32:07,191 INFO L78 Accepts]: Start accepts. Automaton has 22063 states and 67408 transitions. Word has length 65 [2019-12-07 18:32:07,191 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:32:07,191 INFO L462 AbstractCegarLoop]: Abstraction has 22063 states and 67408 transitions. [2019-12-07 18:32:07,191 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 18:32:07,191 INFO L276 IsEmpty]: Start isEmpty. Operand 22063 states and 67408 transitions. [2019-12-07 18:32:07,212 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:32:07,212 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:32:07,212 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:32:07,212 INFO L410 AbstractCegarLoop]: === Iteration 32 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:32:07,212 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:32:07,212 INFO L82 PathProgramCache]: Analyzing trace with hash 979273527, now seen corresponding path program 6 times [2019-12-07 18:32:07,212 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:32:07,212 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [250783808] [2019-12-07 18:32:07,212 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:32:07,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:32:07,317 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:32:07,317 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [250783808] [2019-12-07 18:32:07,317 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:32:07,317 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 18:32:07,317 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [263707113] [2019-12-07 18:32:07,317 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 18:32:07,317 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:32:07,318 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 18:32:07,318 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:32:07,318 INFO L87 Difference]: Start difference. First operand 22063 states and 67408 transitions. Second operand 11 states. [2019-12-07 18:32:08,118 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:32:08,118 INFO L93 Difference]: Finished difference Result 42922 states and 131430 transitions. [2019-12-07 18:32:08,118 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2019-12-07 18:32:08,119 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 65 [2019-12-07 18:32:08,119 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:32:08,168 INFO L225 Difference]: With dead ends: 42922 [2019-12-07 18:32:08,168 INFO L226 Difference]: Without dead ends: 40518 [2019-12-07 18:32:08,168 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 192 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=172, Invalid=758, Unknown=0, NotChecked=0, Total=930 [2019-12-07 18:32:08,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40518 states. [2019-12-07 18:32:08,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40518 to 24421. [2019-12-07 18:32:08,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24421 states. [2019-12-07 18:32:08,640 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24421 states to 24421 states and 74179 transitions. [2019-12-07 18:32:08,640 INFO L78 Accepts]: Start accepts. Automaton has 24421 states and 74179 transitions. Word has length 65 [2019-12-07 18:32:08,640 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:32:08,640 INFO L462 AbstractCegarLoop]: Abstraction has 24421 states and 74179 transitions. [2019-12-07 18:32:08,640 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 18:32:08,640 INFO L276 IsEmpty]: Start isEmpty. Operand 24421 states and 74179 transitions. [2019-12-07 18:32:08,661 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:32:08,661 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:32:08,661 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:32:08,661 INFO L410 AbstractCegarLoop]: === Iteration 33 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:32:08,661 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:32:08,661 INFO L82 PathProgramCache]: Analyzing trace with hash 1699156151, now seen corresponding path program 7 times [2019-12-07 18:32:08,661 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:32:08,662 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [641621576] [2019-12-07 18:32:08,662 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:32:08,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:32:08,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:32:08,769 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [641621576] [2019-12-07 18:32:08,769 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:32:08,769 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 18:32:08,769 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1867634014] [2019-12-07 18:32:08,770 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 18:32:08,770 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:32:08,770 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 18:32:08,770 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:32:08,770 INFO L87 Difference]: Start difference. First operand 24421 states and 74179 transitions. Second operand 11 states. [2019-12-07 18:32:10,155 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:32:10,155 INFO L93 Difference]: Finished difference Result 64899 states and 197362 transitions. [2019-12-07 18:32:10,155 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2019-12-07 18:32:10,156 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 65 [2019-12-07 18:32:10,156 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:32:10,231 INFO L225 Difference]: With dead ends: 64899 [2019-12-07 18:32:10,231 INFO L226 Difference]: Without dead ends: 55020 [2019-12-07 18:32:10,232 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 484 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=334, Invalid=1472, Unknown=0, NotChecked=0, Total=1806 [2019-12-07 18:32:10,436 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55020 states. [2019-12-07 18:32:10,741 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55020 to 21194. [2019-12-07 18:32:10,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21194 states. [2019-12-07 18:32:10,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21194 states to 21194 states and 64752 transitions. [2019-12-07 18:32:10,780 INFO L78 Accepts]: Start accepts. Automaton has 21194 states and 64752 transitions. Word has length 65 [2019-12-07 18:32:10,780 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:32:10,780 INFO L462 AbstractCegarLoop]: Abstraction has 21194 states and 64752 transitions. [2019-12-07 18:32:10,781 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 18:32:10,781 INFO L276 IsEmpty]: Start isEmpty. Operand 21194 states and 64752 transitions. [2019-12-07 18:32:10,801 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:32:10,801 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:32:10,801 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:32:10,801 INFO L410 AbstractCegarLoop]: === Iteration 34 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:32:10,801 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:32:10,801 INFO L82 PathProgramCache]: Analyzing trace with hash -1019867375, now seen corresponding path program 8 times [2019-12-07 18:32:10,801 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:32:10,802 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1985417532] [2019-12-07 18:32:10,802 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:32:10,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:32:10,854 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:32:10,854 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1985417532] [2019-12-07 18:32:10,854 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:32:10,854 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:32:10,854 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [962699516] [2019-12-07 18:32:10,854 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:32:10,854 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:32:10,854 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:32:10,855 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:32:10,855 INFO L87 Difference]: Start difference. First operand 21194 states and 64752 transitions. Second operand 4 states. [2019-12-07 18:32:10,951 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:32:10,951 INFO L93 Difference]: Finished difference Result 25029 states and 76126 transitions. [2019-12-07 18:32:10,952 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:32:10,952 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 65 [2019-12-07 18:32:10,952 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:32:10,983 INFO L225 Difference]: With dead ends: 25029 [2019-12-07 18:32:10,983 INFO L226 Difference]: Without dead ends: 25029 [2019-12-07 18:32:10,983 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:32:11,070 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25029 states. [2019-12-07 18:32:11,290 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25029 to 21225. [2019-12-07 18:32:11,290 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21225 states. [2019-12-07 18:32:11,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21225 states to 21225 states and 65024 transitions. [2019-12-07 18:32:11,328 INFO L78 Accepts]: Start accepts. Automaton has 21225 states and 65024 transitions. Word has length 65 [2019-12-07 18:32:11,328 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:32:11,328 INFO L462 AbstractCegarLoop]: Abstraction has 21225 states and 65024 transitions. [2019-12-07 18:32:11,328 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:32:11,328 INFO L276 IsEmpty]: Start isEmpty. Operand 21225 states and 65024 transitions. [2019-12-07 18:32:11,347 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 18:32:11,347 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:32:11,347 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:32:11,347 INFO L410 AbstractCegarLoop]: === Iteration 35 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:32:11,347 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:32:11,348 INFO L82 PathProgramCache]: Analyzing trace with hash -952881413, now seen corresponding path program 1 times [2019-12-07 18:32:11,348 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:32:11,348 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1361693801] [2019-12-07 18:32:11,348 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:32:11,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:32:11,716 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:32:11,716 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1361693801] [2019-12-07 18:32:11,716 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:32:11,716 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2019-12-07 18:32:11,716 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [501568714] [2019-12-07 18:32:11,716 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 18:32:11,716 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:32:11,716 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 18:32:11,717 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=226, Unknown=0, NotChecked=0, Total=272 [2019-12-07 18:32:11,717 INFO L87 Difference]: Start difference. First operand 21225 states and 65024 transitions. Second operand 17 states. [2019-12-07 18:32:16,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:32:16,312 INFO L93 Difference]: Finished difference Result 28297 states and 85644 transitions. [2019-12-07 18:32:16,313 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-12-07 18:32:16,313 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 66 [2019-12-07 18:32:16,314 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:32:16,365 INFO L225 Difference]: With dead ends: 28297 [2019-12-07 18:32:16,365 INFO L226 Difference]: Without dead ends: 27792 [2019-12-07 18:32:16,366 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 0 SyntacticMatches, 3 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 430 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=321, Invalid=1401, Unknown=0, NotChecked=0, Total=1722 [2019-12-07 18:32:16,461 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27792 states. [2019-12-07 18:32:16,687 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27792 to 21141. [2019-12-07 18:32:16,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21141 states. [2019-12-07 18:32:16,726 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21141 states to 21141 states and 64802 transitions. [2019-12-07 18:32:16,726 INFO L78 Accepts]: Start accepts. Automaton has 21141 states and 64802 transitions. Word has length 66 [2019-12-07 18:32:16,726 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:32:16,726 INFO L462 AbstractCegarLoop]: Abstraction has 21141 states and 64802 transitions. [2019-12-07 18:32:16,726 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 18:32:16,726 INFO L276 IsEmpty]: Start isEmpty. Operand 21141 states and 64802 transitions. [2019-12-07 18:32:16,745 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 18:32:16,745 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:32:16,746 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:32:16,746 INFO L410 AbstractCegarLoop]: === Iteration 36 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:32:16,746 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:32:16,746 INFO L82 PathProgramCache]: Analyzing trace with hash -2033523235, now seen corresponding path program 2 times [2019-12-07 18:32:16,746 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:32:16,746 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2143507558] [2019-12-07 18:32:16,746 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:32:16,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:32:16,860 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:32:16,860 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2143507558] [2019-12-07 18:32:16,860 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:32:16,860 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 18:32:16,861 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2100701620] [2019-12-07 18:32:16,861 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-12-07 18:32:16,861 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:32:16,861 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-12-07 18:32:16,861 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2019-12-07 18:32:16,861 INFO L87 Difference]: Start difference. First operand 21141 states and 64802 transitions. Second operand 11 states. [2019-12-07 18:32:19,084 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:32:19,084 INFO L93 Difference]: Finished difference Result 41934 states and 128153 transitions. [2019-12-07 18:32:19,085 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2019-12-07 18:32:19,085 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 66 [2019-12-07 18:32:19,086 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:32:19,157 INFO L225 Difference]: With dead ends: 41934 [2019-12-07 18:32:19,157 INFO L226 Difference]: Without dead ends: 41231 [2019-12-07 18:32:19,158 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 201 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=171, Invalid=821, Unknown=0, NotChecked=0, Total=992 [2019-12-07 18:32:19,280 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41231 states. [2019-12-07 18:32:19,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41231 to 20957. [2019-12-07 18:32:19,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20957 states. [2019-12-07 18:32:19,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20957 states to 20957 states and 64336 transitions. [2019-12-07 18:32:19,605 INFO L78 Accepts]: Start accepts. Automaton has 20957 states and 64336 transitions. Word has length 66 [2019-12-07 18:32:19,606 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:32:19,606 INFO L462 AbstractCegarLoop]: Abstraction has 20957 states and 64336 transitions. [2019-12-07 18:32:19,606 INFO L463 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-12-07 18:32:19,606 INFO L276 IsEmpty]: Start isEmpty. Operand 20957 states and 64336 transitions. [2019-12-07 18:32:19,624 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 18:32:19,624 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:32:19,625 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:32:19,625 INFO L410 AbstractCegarLoop]: === Iteration 37 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:32:19,625 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:32:19,625 INFO L82 PathProgramCache]: Analyzing trace with hash 620198601, now seen corresponding path program 3 times [2019-12-07 18:32:19,625 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:32:19,625 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [434854442] [2019-12-07 18:32:19,625 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:32:19,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:32:19,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:32:19,701 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:32:19,701 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 18:32:19,704 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [895] [895] ULTIMATE.startENTRY-->L825: Formula: (let ((.cse0 (store |v_#valid_71| 0 0))) (and (= v_~z$w_buff0_used~0_749 0) (= v_~weak$$choice2~0_132 0) (= 0 v_~weak$$choice0~0_14) (= (store |v_#memory_int_20| |v_ULTIMATE.start_main_~#t675~0.base_22| (store (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#t675~0.base_22|) |v_ULTIMATE.start_main_~#t675~0.offset_16| 0)) |v_#memory_int_19|) (= v_~z$read_delayed_var~0.offset_6 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t675~0.base_22|)) (= |v_#NULL.offset_6| 0) (= v_~z$r_buff0_thd1~0_380 0) (= v_~z$r_buff0_thd2~0_184 0) (= v_~__unbuffered_cnt~0_128 0) (= v_~y~0_48 0) (= v_~z$mem_tmp~0_24 0) (< 0 |v_#StackHeapBarrier_15|) (= v_~z$r_buff1_thd0~0_296 0) (= v_~z$read_delayed_var~0.base_6 0) (= v_~__unbuffered_p2_EBX~0_50 0) (= v_~z$w_buff1_used~0_500 0) (= v_~z$r_buff0_thd0~0_197 0) (= 0 |v_#NULL.base_6|) (= 0 v_~z$flush_delayed~0_43) (= 0 v_~__unbuffered_p0_EAX~0_233) (= v_~z$read_delayed~0_7 0) (= |v_#valid_69| (store .cse0 |v_ULTIMATE.start_main_~#t675~0.base_22| 1)) (< |v_#StackHeapBarrier_15| |v_ULTIMATE.start_main_~#t675~0.base_22|) (= 0 v_~z$r_buff1_thd3~0_396) (= v_~z$r_buff1_thd1~0_267 0) (= 0 v_~__unbuffered_p2_EAX~0_37) (= v_~z$w_buff0~0_256 0) (= v_~main$tmp_guard0~0_22 0) (= (store |v_#length_22| |v_ULTIMATE.start_main_~#t675~0.base_22| 4) |v_#length_21|) (= 0 v_~z$r_buff0_thd3~0_379) (= v_~z$r_buff1_thd2~0_280 0) (= 0 |v_ULTIMATE.start_main_~#t675~0.offset_16|) (= v_~z$w_buff1~0_199 0) (= 0 v_~x~0_133) (= v_~z~0_182 0) (= v_~main$tmp_guard1~0_40 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_15|, #valid=|v_#valid_71|, #memory_int=|v_#memory_int_20|, #length=|v_#length_22|} OutVars{ULTIMATE.start_main_~#t677~0.base=|v_ULTIMATE.start_main_~#t677~0.base_17|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_280, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_63|, #NULL.offset=|v_#NULL.offset_6|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_113|, ULTIMATE.start_main_~#t675~0.offset=|v_ULTIMATE.start_main_~#t675~0.offset_16|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_223|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_76|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_197, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_233, #length=|v_#length_21|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_37, ~z$mem_tmp~0=v_~z$mem_tmp~0_24, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_50, ULTIMATE.start_main_~#t675~0.base=|v_ULTIMATE.start_main_~#t675~0.base_22|, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_8|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_500, ~z$flush_delayed~0=v_~z$flush_delayed~0_43, ~weak$$choice0~0=v_~weak$$choice0~0_14, #StackHeapBarrier=|v_#StackHeapBarrier_15|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_267, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_6, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_379, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_128, ULTIMATE.start_main_~#t676~0.offset=|v_ULTIMATE.start_main_~#t676~0.offset_14|, ~x~0=v_~x~0_133, ~z$read_delayed~0=v_~z$read_delayed~0_7, ~z$w_buff1~0=v_~z$w_buff1~0_199, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_40, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_45|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_6, ULTIMATE.start_main_~#t676~0.base=|v_ULTIMATE.start_main_~#t676~0.base_19|, ULTIMATE.start_main_~#t677~0.offset=|v_ULTIMATE.start_main_~#t677~0.offset_14|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_33|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_296, ~y~0=v_~y~0_48, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_184, ULTIMATE.start_main_#t~nondet46=|v_ULTIMATE.start_main_#t~nondet46_19|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_749, ~z$w_buff0~0=v_~z$w_buff0~0_256, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_7|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_396, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_22, #NULL.base=|v_#NULL.base_6|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_31|, #valid=|v_#valid_69|, #memory_int=|v_#memory_int_19|, ~z~0=v_~z~0_182, ~weak$$choice2~0=v_~weak$$choice2~0_132, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_380} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t677~0.base, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_~#t675~0.offset, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ~z$r_buff0_thd0~0, ~__unbuffered_p0_EAX~0, #length, ~__unbuffered_p2_EAX~0, ~z$mem_tmp~0, ~__unbuffered_p2_EBX~0, ULTIMATE.start_main_~#t675~0.base, ULTIMATE.start_main_#t~nondet45, ~z$w_buff1_used~0, ~z$flush_delayed~0, ~weak$$choice0~0, ~z$r_buff1_thd1~0, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ~__unbuffered_cnt~0, ULTIMATE.start_main_~#t676~0.offset, ~x~0, ~z$read_delayed~0, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite48, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_~#t676~0.base, ULTIMATE.start_main_~#t677~0.offset, ULTIMATE.start_main_#t~ite51, ~z$r_buff1_thd0~0, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet46, ~z$w_buff0_used~0, ~z$w_buff0~0, ULTIMATE.start_main_#t~nondet44, ~z$r_buff1_thd3~0, ~main$tmp_guard0~0, #NULL.base, ULTIMATE.start_main_#res, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 18:32:19,705 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [772] [772] L4-->L746: Formula: (and (= v_~z$r_buff0_thd1~0_29 v_~z$r_buff1_thd1~0_17) (= v_~z$r_buff0_thd2~0_25 v_~z$r_buff1_thd2~0_17) (= v_~z$r_buff0_thd3~0_70 v_~z$r_buff1_thd3~0_54) (= v_~z$r_buff0_thd1~0_28 1) (not (= 0 v_P0Thread1of1ForFork1___VERIFIER_assert_~expression_8)) (= v_~z$r_buff0_thd0~0_26 v_~z$r_buff1_thd0~0_23) (= v_~x~0_9 v_~__unbuffered_p0_EAX~0_11)) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_26, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_70, P0Thread1of1ForFork1___VERIFIER_assert_~expression=v_P0Thread1of1ForFork1___VERIFIER_assert_~expression_8, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_29, ~x~0=v_~x~0_9, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_25} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_11, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_26, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_54, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_23, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_17, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_17, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_70, P0Thread1of1ForFork1___VERIFIER_assert_~expression=v_P0Thread1of1ForFork1___VERIFIER_assert_~expression_8, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_28, ~x~0=v_~x~0_9, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_25} AuxVars[] AssignedVars[~__unbuffered_p0_EAX~0, ~z$r_buff1_thd3~0, ~z$r_buff1_thd0~0, ~z$r_buff1_thd2~0, ~z$r_buff1_thd1~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 18:32:19,705 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [860] [860] L825-1-->L827: Formula: (and (= (store |v_#length_16| |v_ULTIMATE.start_main_~#t676~0.base_11| 4) |v_#length_15|) (= 0 (select |v_#valid_32| |v_ULTIMATE.start_main_~#t676~0.base_11|)) (not (= 0 |v_ULTIMATE.start_main_~#t676~0.base_11|)) (= 0 |v_ULTIMATE.start_main_~#t676~0.offset_10|) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t676~0.base_11| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t676~0.base_11|) |v_ULTIMATE.start_main_~#t676~0.offset_10| 1)) |v_#memory_int_13|) (= |v_#valid_31| (store |v_#valid_32| |v_ULTIMATE.start_main_~#t676~0.base_11| 1)) (< |v_#StackHeapBarrier_9| |v_ULTIMATE.start_main_~#t676~0.base_11|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_9|, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_4|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_13|, #length=|v_#length_15|, ULTIMATE.start_main_~#t676~0.offset=|v_ULTIMATE.start_main_~#t676~0.offset_10|, ULTIMATE.start_main_~#t676~0.base=|v_ULTIMATE.start_main_~#t676~0.base_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet44, #valid, #memory_int, #length, ULTIMATE.start_main_~#t676~0.offset, ULTIMATE.start_main_~#t676~0.base] because there is no mapped edge [2019-12-07 18:32:19,706 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [856] [856] L827-1-->L829: Formula: (and (not (= |v_ULTIMATE.start_main_~#t677~0.base_12| 0)) (< |v_#StackHeapBarrier_8| |v_ULTIMATE.start_main_~#t677~0.base_12|) (= (select |v_#valid_30| |v_ULTIMATE.start_main_~#t677~0.base_12|) 0) (= 0 |v_ULTIMATE.start_main_~#t677~0.offset_10|) (= (store |v_#valid_30| |v_ULTIMATE.start_main_~#t677~0.base_12| 1) |v_#valid_29|) (= (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t677~0.base_12| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t677~0.base_12|) |v_ULTIMATE.start_main_~#t677~0.offset_10| 2)) |v_#memory_int_11|) (= (store |v_#length_14| |v_ULTIMATE.start_main_~#t677~0.base_12| 4) |v_#length_13|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_8|, #valid=|v_#valid_30|, #memory_int=|v_#memory_int_12|, #length=|v_#length_14|} OutVars{ULTIMATE.start_main_~#t677~0.offset=|v_ULTIMATE.start_main_~#t677~0.offset_10|, #StackHeapBarrier=|v_#StackHeapBarrier_8|, ULTIMATE.start_main_~#t677~0.base=|v_ULTIMATE.start_main_~#t677~0.base_12|, #valid=|v_#valid_29|, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_5|, #memory_int=|v_#memory_int_11|, #length=|v_#length_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t677~0.offset, ULTIMATE.start_main_~#t677~0.base, #valid, ULTIMATE.start_main_#t~nondet45, #memory_int, #length] because there is no mapped edge [2019-12-07 18:32:19,708 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [843] [843] L766-2-->L766-5: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff1_used~0_In-841087192 256))) (.cse0 (= 0 (mod ~z$r_buff1_thd2~0_In-841087192 256))) (.cse2 (= |P1Thread1of1ForFork2_#t~ite9_Out-841087192| |P1Thread1of1ForFork2_#t~ite10_Out-841087192|))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork2_#t~ite9_Out-841087192| ~z~0_In-841087192) .cse2) (and (= |P1Thread1of1ForFork2_#t~ite9_Out-841087192| ~z$w_buff1~0_In-841087192) (not .cse1) (not .cse0) .cse2))) InVars {~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-841087192, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-841087192, ~z$w_buff1~0=~z$w_buff1~0_In-841087192, ~z~0=~z~0_In-841087192} OutVars{P1Thread1of1ForFork2_#t~ite9=|P1Thread1of1ForFork2_#t~ite9_Out-841087192|, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-841087192, P1Thread1of1ForFork2_#t~ite10=|P1Thread1of1ForFork2_#t~ite10_Out-841087192|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-841087192, ~z$w_buff1~0=~z$w_buff1~0_In-841087192, ~z~0=~z~0_In-841087192} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite10] because there is no mapped edge [2019-12-07 18:32:19,709 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [871] [871] L792-->L792-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In1617421882 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite23_In1617421882| |P2Thread1of1ForFork0_#t~ite23_Out1617421882|) (= ~z$w_buff1~0_In1617421882 |P2Thread1of1ForFork0_#t~ite24_Out1617421882|) (not .cse0)) (and (= |P2Thread1of1ForFork0_#t~ite23_Out1617421882| |P2Thread1of1ForFork0_#t~ite24_Out1617421882|) (let ((.cse1 (= (mod ~z$r_buff0_thd3~0_In1617421882 256) 0))) (or (and (= (mod ~z$w_buff1_used~0_In1617421882 256) 0) .cse1) (and (= (mod ~z$r_buff1_thd3~0_In1617421882 256) 0) .cse1) (= 0 (mod ~z$w_buff0_used~0_In1617421882 256)))) .cse0 (= ~z$w_buff1~0_In1617421882 |P2Thread1of1ForFork0_#t~ite23_Out1617421882|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1617421882, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1617421882, P2Thread1of1ForFork0_#t~ite23=|P2Thread1of1ForFork0_#t~ite23_In1617421882|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1617421882, ~z$w_buff1~0=~z$w_buff1~0_In1617421882, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1617421882, ~weak$$choice2~0=~weak$$choice2~0_In1617421882} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1617421882, P2Thread1of1ForFork0_#t~ite23=|P2Thread1of1ForFork0_#t~ite23_Out1617421882|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1617421882, P2Thread1of1ForFork0_#t~ite24=|P2Thread1of1ForFork0_#t~ite24_Out1617421882|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1617421882, ~z$w_buff1~0=~z$w_buff1~0_In1617421882, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1617421882, ~weak$$choice2~0=~weak$$choice2~0_In1617421882} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite23, P2Thread1of1ForFork0_#t~ite24] because there is no mapped edge [2019-12-07 18:32:19,710 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [884] [884] L794-->L794-8: Formula: (let ((.cse1 (= |P2Thread1of1ForFork0_#t~ite29_Out25440161| |P2Thread1of1ForFork0_#t~ite30_Out25440161|)) (.cse4 (= 0 (mod ~z$w_buff0_used~0_In25440161 256))) (.cse0 (= 0 (mod ~weak$$choice2~0_In25440161 256))) (.cse5 (= 0 (mod ~z$r_buff1_thd3~0_In25440161 256))) (.cse2 (= (mod ~z$w_buff1_used~0_In25440161 256) 0)) (.cse3 (= 0 (mod ~z$r_buff0_thd3~0_In25440161 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite28_In25440161| |P2Thread1of1ForFork0_#t~ite28_Out25440161|) (or (and (= |P2Thread1of1ForFork0_#t~ite29_Out25440161| |P2Thread1of1ForFork0_#t~ite29_In25440161|) (not .cse0) (= ~z$w_buff1_used~0_In25440161 |P2Thread1of1ForFork0_#t~ite30_Out25440161|)) (and (= ~z$w_buff1_used~0_In25440161 |P2Thread1of1ForFork0_#t~ite29_Out25440161|) .cse1 .cse0 (or (and .cse2 .cse3) .cse4 (and .cse5 .cse3))))) (let ((.cse6 (not .cse3))) (and (= |P2Thread1of1ForFork0_#t~ite29_Out25440161| |P2Thread1of1ForFork0_#t~ite28_Out25440161|) (= |P2Thread1of1ForFork0_#t~ite28_Out25440161| 0) .cse1 (not .cse4) .cse0 (or .cse6 (not .cse5)) (or (not .cse2) .cse6))))) InVars {P2Thread1of1ForFork0_#t~ite28=|P2Thread1of1ForFork0_#t~ite28_In25440161|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In25440161, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In25440161, ~z$w_buff1_used~0=~z$w_buff1_used~0_In25440161, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In25440161, ~weak$$choice2~0=~weak$$choice2~0_In25440161, P2Thread1of1ForFork0_#t~ite29=|P2Thread1of1ForFork0_#t~ite29_In25440161|} OutVars{P2Thread1of1ForFork0_#t~ite28=|P2Thread1of1ForFork0_#t~ite28_Out25440161|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In25440161, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In25440161, ~z$w_buff1_used~0=~z$w_buff1_used~0_In25440161, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In25440161, P2Thread1of1ForFork0_#t~ite30=|P2Thread1of1ForFork0_#t~ite30_Out25440161|, P2Thread1of1ForFork0_#t~ite29=|P2Thread1of1ForFork0_#t~ite29_Out25440161|, ~weak$$choice2~0=~weak$$choice2~0_In25440161} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite28, P2Thread1of1ForFork0_#t~ite30, P2Thread1of1ForFork0_#t~ite29] because there is no mapped edge [2019-12-07 18:32:19,710 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [890] [890] L794-8-->L796: Formula: (and (= v_~z$w_buff1_used~0_493 |v_P2Thread1of1ForFork0_#t~ite30_36|) (not (= (mod v_~weak$$choice2~0_130 256) 0)) (= v_~z$r_buff0_thd3~0_373 v_~z$r_buff0_thd3~0_372)) InVars {~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_373, P2Thread1of1ForFork0_#t~ite30=|v_P2Thread1of1ForFork0_#t~ite30_36|, ~weak$$choice2~0=v_~weak$$choice2~0_130} OutVars{P2Thread1of1ForFork0_#t~ite28=|v_P2Thread1of1ForFork0_#t~ite28_37|, P2Thread1of1ForFork0_#t~ite33=|v_P2Thread1of1ForFork0_#t~ite33_13|, P2Thread1of1ForFork0_#t~ite32=|v_P2Thread1of1ForFork0_#t~ite32_29|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_493, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_372, P2Thread1of1ForFork0_#t~ite31=|v_P2Thread1of1ForFork0_#t~ite31_21|, P2Thread1of1ForFork0_#t~ite30=|v_P2Thread1of1ForFork0_#t~ite30_35|, ~weak$$choice2~0=v_~weak$$choice2~0_130, P2Thread1of1ForFork0_#t~ite29=|v_P2Thread1of1ForFork0_#t~ite29_47|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite28, P2Thread1of1ForFork0_#t~ite33, P2Thread1of1ForFork0_#t~ite32, ~z$w_buff1_used~0, ~z$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite31, P2Thread1of1ForFork0_#t~ite30, P2Thread1of1ForFork0_#t~ite29] because there is no mapped edge [2019-12-07 18:32:19,711 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [795] [795] L798-->L802: Formula: (and (not (= 0 (mod v_~z$flush_delayed~0_10 256))) (= 0 v_~z$flush_delayed~0_9) (= v_~z~0_46 v_~z$mem_tmp~0_7)) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_7, ~z$flush_delayed~0=v_~z$flush_delayed~0_10} OutVars{P2Thread1of1ForFork0_#t~ite37=|v_P2Thread1of1ForFork0_#t~ite37_5|, ~z$mem_tmp~0=v_~z$mem_tmp~0_7, ~z$flush_delayed~0=v_~z$flush_delayed~0_9, ~z~0=v_~z~0_46} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite37, ~z$flush_delayed~0, ~z~0] because there is no mapped edge [2019-12-07 18:32:19,711 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [819] [819] L802-2-->L802-5: Formula: (let ((.cse2 (= 0 (mod ~z$r_buff1_thd3~0_In21236130 256))) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In21236130 256))) (.cse1 (= |P2Thread1of1ForFork0_#t~ite39_Out21236130| |P2Thread1of1ForFork0_#t~ite38_Out21236130|))) (or (and (= |P2Thread1of1ForFork0_#t~ite38_Out21236130| ~z$w_buff1~0_In21236130) (not .cse0) .cse1 (not .cse2)) (and (= |P2Thread1of1ForFork0_#t~ite38_Out21236130| ~z~0_In21236130) (or .cse2 .cse0) .cse1))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In21236130, ~z$w_buff1_used~0=~z$w_buff1_used~0_In21236130, ~z$w_buff1~0=~z$w_buff1~0_In21236130, ~z~0=~z~0_In21236130} OutVars{P2Thread1of1ForFork0_#t~ite39=|P2Thread1of1ForFork0_#t~ite39_Out21236130|, P2Thread1of1ForFork0_#t~ite38=|P2Thread1of1ForFork0_#t~ite38_Out21236130|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In21236130, ~z$w_buff1_used~0=~z$w_buff1_used~0_In21236130, ~z$w_buff1~0=~z$w_buff1~0_In21236130, ~z~0=~z~0_In21236130} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite39, P2Thread1of1ForFork0_#t~ite38] because there is no mapped edge [2019-12-07 18:32:19,711 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [823] [823] L803-->L803-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In-1865552284 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd3~0_In-1865552284 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite40_Out-1865552284| 0) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= ~z$w_buff0_used~0_In-1865552284 |P2Thread1of1ForFork0_#t~ite40_Out-1865552284|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1865552284, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1865552284} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1865552284, P2Thread1of1ForFork0_#t~ite40=|P2Thread1of1ForFork0_#t~ite40_Out-1865552284|, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1865552284} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite40] because there is no mapped edge [2019-12-07 18:32:19,712 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [818] [818] L804-->L804-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd3~0_In-647140950 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In-647140950 256) 0)) (.cse2 (= (mod ~z$r_buff1_thd3~0_In-647140950 256) 0)) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In-647140950 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P2Thread1of1ForFork0_#t~ite41_Out-647140950| ~z$w_buff1_used~0_In-647140950)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork0_#t~ite41_Out-647140950| 0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-647140950, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-647140950, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-647140950, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-647140950} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-647140950, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-647140950, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-647140950, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-647140950, P2Thread1of1ForFork0_#t~ite41=|P2Thread1of1ForFork0_#t~ite41_Out-647140950|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite41] because there is no mapped edge [2019-12-07 18:32:19,712 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [841] [841] L805-->L805-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In1007074940 256) 0)) (.cse0 (= (mod ~z$r_buff0_thd3~0_In1007074940 256) 0))) (or (and (= |P2Thread1of1ForFork0_#t~ite42_Out1007074940| ~z$r_buff0_thd3~0_In1007074940) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= |P2Thread1of1ForFork0_#t~ite42_Out1007074940| 0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1007074940, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1007074940} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1007074940, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1007074940, P2Thread1of1ForFork0_#t~ite42=|P2Thread1of1ForFork0_#t~ite42_Out1007074940|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite42] because there is no mapped edge [2019-12-07 18:32:19,713 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [835] [835] L806-->L806-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In-292692101 256))) (.cse0 (= (mod ~z$w_buff0_used~0_In-292692101 256) 0)) (.cse3 (= 0 (mod ~z$r_buff1_thd3~0_In-292692101 256))) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In-292692101 256)))) (or (and (or .cse0 .cse1) (= ~z$r_buff1_thd3~0_In-292692101 |P2Thread1of1ForFork0_#t~ite43_Out-292692101|) (or .cse2 .cse3)) (and (= |P2Thread1of1ForFork0_#t~ite43_Out-292692101| 0) (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-292692101, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-292692101, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-292692101, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-292692101} OutVars{P2Thread1of1ForFork0_#t~ite43=|P2Thread1of1ForFork0_#t~ite43_Out-292692101|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-292692101, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-292692101, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-292692101, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-292692101} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite43] because there is no mapped edge [2019-12-07 18:32:19,713 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [870] [870] L806-2-->P2EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_100 1) v_~__unbuffered_cnt~0_99) (= v_~z$r_buff1_thd3~0_306 |v_P2Thread1of1ForFork0_#t~ite43_54|) (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite43=|v_P2Thread1of1ForFork0_#t~ite43_54|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_100} OutVars{P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, P2Thread1of1ForFork0_#t~ite43=|v_P2Thread1of1ForFork0_#t~ite43_53|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_306, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_99, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#res.base, P2Thread1of1ForFork0_#t~ite43, ~z$r_buff1_thd3~0, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 18:32:19,713 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [838] [838] L747-->L747-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In1091333495 256))) (.cse1 (= (mod ~z$r_buff0_thd1~0_In1091333495 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 |P0Thread1of1ForFork1_#t~ite5_Out1091333495|)) (and (= ~z$w_buff0_used~0_In1091333495 |P0Thread1of1ForFork1_#t~ite5_Out1091333495|) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1091333495, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1091333495} OutVars{P0Thread1of1ForFork1_#t~ite5=|P0Thread1of1ForFork1_#t~ite5_Out1091333495|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1091333495, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1091333495} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite5] because there is no mapped edge [2019-12-07 18:32:19,714 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [842] [842] L748-->L748-2: Formula: (let ((.cse1 (= (mod ~z$r_buff1_thd1~0_In281471796 256) 0)) (.cse0 (= (mod ~z$w_buff1_used~0_In281471796 256) 0)) (.cse3 (= 0 (mod ~z$r_buff0_thd1~0_In281471796 256))) (.cse2 (= (mod ~z$w_buff0_used~0_In281471796 256) 0))) (or (and (= ~z$w_buff1_used~0_In281471796 |P0Thread1of1ForFork1_#t~ite6_Out281471796|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P0Thread1of1ForFork1_#t~ite6_Out281471796|) (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In281471796, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In281471796, ~z$w_buff1_used~0=~z$w_buff1_used~0_In281471796, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In281471796} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In281471796, P0Thread1of1ForFork1_#t~ite6=|P0Thread1of1ForFork1_#t~ite6_Out281471796|, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In281471796, ~z$w_buff1_used~0=~z$w_buff1_used~0_In281471796, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In281471796} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite6] because there is no mapped edge [2019-12-07 18:32:19,714 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [824] [824] L749-->L750: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In1515198035 256))) (.cse2 (= 0 (mod ~z$r_buff0_thd1~0_In1515198035 256))) (.cse1 (= ~z$r_buff0_thd1~0_Out1515198035 ~z$r_buff0_thd1~0_In1515198035))) (or (and .cse0 .cse1) (and (not .cse0) (not .cse2) (= ~z$r_buff0_thd1~0_Out1515198035 0)) (and .cse2 .cse1))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1515198035, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1515198035} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1515198035, P0Thread1of1ForFork1_#t~ite7=|P0Thread1of1ForFork1_#t~ite7_Out1515198035|, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_Out1515198035} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite7, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 18:32:19,714 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [826] [826] L750-->L750-2: Formula: (let ((.cse2 (= 0 (mod ~z$r_buff0_thd1~0_In1102816513 256))) (.cse3 (= (mod ~z$w_buff0_used~0_In1102816513 256) 0)) (.cse0 (= (mod ~z$r_buff1_thd1~0_In1102816513 256) 0)) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In1102816513 256)))) (or (and (= 0 |P0Thread1of1ForFork1_#t~ite8_Out1102816513|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse2 .cse3) (= ~z$r_buff1_thd1~0_In1102816513 |P0Thread1of1ForFork1_#t~ite8_Out1102816513|) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1102816513, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In1102816513, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1102816513, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1102816513} OutVars{P0Thread1of1ForFork1_#t~ite8=|P0Thread1of1ForFork1_#t~ite8_Out1102816513|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1102816513, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In1102816513, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1102816513, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1102816513} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite8] because there is no mapped edge [2019-12-07 18:32:19,714 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [853] [853] L750-2-->P0EXIT: Formula: (and (= 0 |v_P0Thread1of1ForFork1_#res.base_3|) (= v_~__unbuffered_cnt~0_71 (+ v_~__unbuffered_cnt~0_72 1)) (= v_~z$r_buff1_thd1~0_83 |v_P0Thread1of1ForFork1_#t~ite8_38|) (= 0 |v_P0Thread1of1ForFork1_#res.offset_3|)) InVars {P0Thread1of1ForFork1_#t~ite8=|v_P0Thread1of1ForFork1_#t~ite8_38|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_72} OutVars{P0Thread1of1ForFork1_#t~ite8=|v_P0Thread1of1ForFork1_#t~ite8_37|, P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_3|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_83, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_71} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite8, P0Thread1of1ForFork1_#res.offset, ~z$r_buff1_thd1~0, P0Thread1of1ForFork1_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 18:32:19,714 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [831] [831] L767-->L767-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd2~0_In-913321069 256))) (.cse0 (= (mod ~z$w_buff0_used~0_In-913321069 256) 0))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork2_#t~ite11_Out-913321069| ~z$w_buff0_used~0_In-913321069)) (and (= |P1Thread1of1ForFork2_#t~ite11_Out-913321069| 0) (not .cse1) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-913321069, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-913321069} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-913321069, P1Thread1of1ForFork2_#t~ite11=|P1Thread1of1ForFork2_#t~ite11_Out-913321069|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-913321069} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite11] because there is no mapped edge [2019-12-07 18:32:19,715 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [836] [836] L768-->L768-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In1540550293 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd2~0_In1540550293 256))) (.cse2 (= 0 (mod ~z$r_buff1_thd2~0_In1540550293 256))) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In1540550293 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork2_#t~ite12_Out1540550293|)) (and (= ~z$w_buff1_used~0_In1540550293 |P1Thread1of1ForFork2_#t~ite12_Out1540550293|) (or .cse0 .cse1) (or .cse2 .cse3)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1540550293, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1540550293, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1540550293, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1540550293} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1540550293, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1540550293, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1540550293, P1Thread1of1ForFork2_#t~ite12=|P1Thread1of1ForFork2_#t~ite12_Out1540550293|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1540550293} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite12] because there is no mapped edge [2019-12-07 18:32:19,715 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [825] [825] L769-->L769-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In945169287 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In945169287 256)))) (or (and (= ~z$r_buff0_thd2~0_In945169287 |P1Thread1of1ForFork2_#t~ite13_Out945169287|) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= 0 |P1Thread1of1ForFork2_#t~ite13_Out945169287|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In945169287, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In945169287} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In945169287, P1Thread1of1ForFork2_#t~ite13=|P1Thread1of1ForFork2_#t~ite13_Out945169287|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In945169287} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite13] because there is no mapped edge [2019-12-07 18:32:19,715 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [821] [821] L770-->L770-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In-1320061449 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In-1320061449 256))) (.cse2 (= (mod ~z$r_buff1_thd2~0_In-1320061449 256) 0)) (.cse3 (= (mod ~z$w_buff1_used~0_In-1320061449 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork2_#t~ite14_Out-1320061449|)) (and (or .cse1 .cse0) (= ~z$r_buff1_thd2~0_In-1320061449 |P1Thread1of1ForFork2_#t~ite14_Out-1320061449|) (or .cse2 .cse3)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1320061449, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1320061449, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1320061449, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1320061449} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1320061449, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1320061449, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1320061449, P1Thread1of1ForFork2_#t~ite14=|P1Thread1of1ForFork2_#t~ite14_Out-1320061449|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1320061449} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite14] because there is no mapped edge [2019-12-07 18:32:19,716 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [868] [868] L770-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= v_~z$r_buff1_thd2~0_186 |v_P1Thread1of1ForFork2_#t~ite14_48|) (= (+ v_~__unbuffered_cnt~0_94 1) v_~__unbuffered_cnt~0_93)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_94, P1Thread1of1ForFork2_#t~ite14=|v_P1Thread1of1ForFork2_#t~ite14_48|} OutVars{P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_186, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_93, P1Thread1of1ForFork2_#t~ite14=|v_P1Thread1of1ForFork2_#t~ite14_47|, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#res.offset, ~z$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#t~ite14, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-12-07 18:32:19,716 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L829-1-->L835: Formula: (and (= v_~main$tmp_guard0~0_6 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_14) 1 0) 0) 0 1)) (not (= 0 (mod v_~main$tmp_guard0~0_6 256)))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14} OutVars{ULTIMATE.start_main_#t~nondet46=|v_ULTIMATE.start_main_#t~nondet46_5|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet46, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 18:32:19,716 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [832] [832] L835-2-->L835-4: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd0~0_In1651619703 256) 0)) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In1651619703 256)))) (or (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite47_Out1651619703| ~z$w_buff1~0_In1651619703)) (and (= |ULTIMATE.start_main_#t~ite47_Out1651619703| ~z~0_In1651619703) (or .cse0 .cse1)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1651619703, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1651619703, ~z$w_buff1~0=~z$w_buff1~0_In1651619703, ~z~0=~z~0_In1651619703} OutVars{~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1651619703, ULTIMATE.start_main_#t~ite47=|ULTIMATE.start_main_#t~ite47_Out1651619703|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1651619703, ~z$w_buff1~0=~z$w_buff1~0_In1651619703, ~z~0=~z~0_In1651619703} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47] because there is no mapped edge [2019-12-07 18:32:19,716 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L835-4-->L836: Formula: (= v_~z~0_40 |v_ULTIMATE.start_main_#t~ite47_9|) InVars {ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_9|} OutVars{ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_8|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_12|, ~z~0=v_~z~0_40} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite48, ~z~0] because there is no mapped edge [2019-12-07 18:32:19,716 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [830] [830] L836-->L836-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In1566783785 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd0~0_In1566783785 256)))) (or (and (= 0 |ULTIMATE.start_main_#t~ite49_Out1566783785|) (not .cse0) (not .cse1)) (and (= ~z$w_buff0_used~0_In1566783785 |ULTIMATE.start_main_#t~ite49_Out1566783785|) (or .cse0 .cse1)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1566783785, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1566783785} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1566783785, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1566783785, ULTIMATE.start_main_#t~ite49=|ULTIMATE.start_main_#t~ite49_Out1566783785|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite49] because there is no mapped edge [2019-12-07 18:32:19,717 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [817] [817] L837-->L837-2: Formula: (let ((.cse2 (= 0 (mod ~z$r_buff0_thd0~0_In1372692094 256))) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In1372692094 256))) (.cse0 (= (mod ~z$r_buff1_thd0~0_In1372692094 256) 0)) (.cse1 (= (mod ~z$w_buff1_used~0_In1372692094 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |ULTIMATE.start_main_#t~ite50_Out1372692094| 0)) (and (or .cse2 .cse3) (= |ULTIMATE.start_main_#t~ite50_Out1372692094| ~z$w_buff1_used~0_In1372692094) (or .cse0 .cse1)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1372692094, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1372692094, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1372692094, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1372692094} OutVars{ULTIMATE.start_main_#t~ite50=|ULTIMATE.start_main_#t~ite50_Out1372692094|, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1372692094, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1372692094, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1372692094, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1372692094} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite50] because there is no mapped edge [2019-12-07 18:32:19,717 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [833] [833] L838-->L838-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd0~0_In926361585 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In926361585 256) 0))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite51_Out926361585| 0) (not .cse1)) (and (or .cse0 .cse1) (= ~z$r_buff0_thd0~0_In926361585 |ULTIMATE.start_main_#t~ite51_Out926361585|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In926361585, ~z$w_buff0_used~0=~z$w_buff0_used~0_In926361585} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In926361585, ULTIMATE.start_main_#t~ite51=|ULTIMATE.start_main_#t~ite51_Out926361585|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In926361585} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite51] because there is no mapped edge [2019-12-07 18:32:19,718 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [834] [834] L839-->L839-2: Formula: (let ((.cse3 (= (mod ~z$r_buff0_thd0~0_In763159009 256) 0)) (.cse2 (= (mod ~z$w_buff0_used~0_In763159009 256) 0)) (.cse0 (= (mod ~z$r_buff1_thd0~0_In763159009 256) 0)) (.cse1 (= (mod ~z$w_buff1_used~0_In763159009 256) 0))) (or (and (= ~z$r_buff1_thd0~0_In763159009 |ULTIMATE.start_main_#t~ite52_Out763159009|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1))) (= 0 |ULTIMATE.start_main_#t~ite52_Out763159009|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In763159009, ~z$w_buff0_used~0=~z$w_buff0_used~0_In763159009, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In763159009, ~z$w_buff1_used~0=~z$w_buff1_used~0_In763159009} OutVars{ULTIMATE.start_main_#t~ite52=|ULTIMATE.start_main_#t~ite52_Out763159009|, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In763159009, ~z$w_buff0_used~0=~z$w_buff0_used~0_In763159009, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In763159009, ~z$w_buff1_used~0=~z$w_buff1_used~0_In763159009} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52] because there is no mapped edge [2019-12-07 18:32:19,718 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [877] [877] L839-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_12 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|) (= v_~main$tmp_guard1~0_16 (ite (= (ite (not (and (= v_~y~0_25 2) (= 2 v_~__unbuffered_p2_EAX~0_21) (= v_~__unbuffered_p2_EBX~0_34 0) (= 0 v_~__unbuffered_p0_EAX~0_178))) 1 0) 0) 0 1)) (= v_~z$r_buff1_thd0~0_219 |v_ULTIMATE.start_main_#t~ite52_38|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_12 0) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8| (mod v_~main$tmp_guard1~0_16 256))) InVars {~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_178, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_38|, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_34, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_21, ~y~0=v_~y~0_25} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_178, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_37|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_12, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_34, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_219, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_16, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_21, ~y~0=v_~y~0_25, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start___VERIFIER_assert_~expression, ~z$r_buff1_thd0~0, ~main$tmp_guard1~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:32:19,771 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 06:32:19 BasicIcfg [2019-12-07 18:32:19,771 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 18:32:19,771 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 18:32:19,771 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 18:32:19,771 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 18:32:19,772 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:28:11" (3/4) ... [2019-12-07 18:32:19,773 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 18:32:19,773 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [895] [895] ULTIMATE.startENTRY-->L825: Formula: (let ((.cse0 (store |v_#valid_71| 0 0))) (and (= v_~z$w_buff0_used~0_749 0) (= v_~weak$$choice2~0_132 0) (= 0 v_~weak$$choice0~0_14) (= (store |v_#memory_int_20| |v_ULTIMATE.start_main_~#t675~0.base_22| (store (select |v_#memory_int_20| |v_ULTIMATE.start_main_~#t675~0.base_22|) |v_ULTIMATE.start_main_~#t675~0.offset_16| 0)) |v_#memory_int_19|) (= v_~z$read_delayed_var~0.offset_6 0) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t675~0.base_22|)) (= |v_#NULL.offset_6| 0) (= v_~z$r_buff0_thd1~0_380 0) (= v_~z$r_buff0_thd2~0_184 0) (= v_~__unbuffered_cnt~0_128 0) (= v_~y~0_48 0) (= v_~z$mem_tmp~0_24 0) (< 0 |v_#StackHeapBarrier_15|) (= v_~z$r_buff1_thd0~0_296 0) (= v_~z$read_delayed_var~0.base_6 0) (= v_~__unbuffered_p2_EBX~0_50 0) (= v_~z$w_buff1_used~0_500 0) (= v_~z$r_buff0_thd0~0_197 0) (= 0 |v_#NULL.base_6|) (= 0 v_~z$flush_delayed~0_43) (= 0 v_~__unbuffered_p0_EAX~0_233) (= v_~z$read_delayed~0_7 0) (= |v_#valid_69| (store .cse0 |v_ULTIMATE.start_main_~#t675~0.base_22| 1)) (< |v_#StackHeapBarrier_15| |v_ULTIMATE.start_main_~#t675~0.base_22|) (= 0 v_~z$r_buff1_thd3~0_396) (= v_~z$r_buff1_thd1~0_267 0) (= 0 v_~__unbuffered_p2_EAX~0_37) (= v_~z$w_buff0~0_256 0) (= v_~main$tmp_guard0~0_22 0) (= (store |v_#length_22| |v_ULTIMATE.start_main_~#t675~0.base_22| 4) |v_#length_21|) (= 0 v_~z$r_buff0_thd3~0_379) (= v_~z$r_buff1_thd2~0_280 0) (= 0 |v_ULTIMATE.start_main_~#t675~0.offset_16|) (= v_~z$w_buff1~0_199 0) (= 0 v_~x~0_133) (= v_~z~0_182 0) (= v_~main$tmp_guard1~0_40 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_15|, #valid=|v_#valid_71|, #memory_int=|v_#memory_int_20|, #length=|v_#length_22|} OutVars{ULTIMATE.start_main_~#t677~0.base=|v_ULTIMATE.start_main_~#t677~0.base_17|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_280, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_63|, #NULL.offset=|v_#NULL.offset_6|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_113|, ULTIMATE.start_main_~#t675~0.offset=|v_ULTIMATE.start_main_~#t675~0.offset_16|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_223|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_76|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_197, ~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_233, #length=|v_#length_21|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_37, ~z$mem_tmp~0=v_~z$mem_tmp~0_24, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_50, ULTIMATE.start_main_~#t675~0.base=|v_ULTIMATE.start_main_~#t675~0.base_22|, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_8|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_500, ~z$flush_delayed~0=v_~z$flush_delayed~0_43, ~weak$$choice0~0=v_~weak$$choice0~0_14, #StackHeapBarrier=|v_#StackHeapBarrier_15|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_267, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_6, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_379, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_128, ULTIMATE.start_main_~#t676~0.offset=|v_ULTIMATE.start_main_~#t676~0.offset_14|, ~x~0=v_~x~0_133, ~z$read_delayed~0=v_~z$read_delayed~0_7, ~z$w_buff1~0=v_~z$w_buff1~0_199, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_40, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_45|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_6, ULTIMATE.start_main_~#t676~0.base=|v_ULTIMATE.start_main_~#t676~0.base_19|, ULTIMATE.start_main_~#t677~0.offset=|v_ULTIMATE.start_main_~#t677~0.offset_14|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_33|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_296, ~y~0=v_~y~0_48, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_184, ULTIMATE.start_main_#t~nondet46=|v_ULTIMATE.start_main_#t~nondet46_19|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_749, ~z$w_buff0~0=v_~z$w_buff0~0_256, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_7|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_396, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_22, #NULL.base=|v_#NULL.base_6|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_31|, #valid=|v_#valid_69|, #memory_int=|v_#memory_int_19|, ~z~0=v_~z~0_182, ~weak$$choice2~0=v_~weak$$choice2~0_132, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_380} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t677~0.base, ~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite49, ULTIMATE.start_main_~#t675~0.offset, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ~z$r_buff0_thd0~0, ~__unbuffered_p0_EAX~0, #length, ~__unbuffered_p2_EAX~0, ~z$mem_tmp~0, ~__unbuffered_p2_EBX~0, ULTIMATE.start_main_~#t675~0.base, ULTIMATE.start_main_#t~nondet45, ~z$w_buff1_used~0, ~z$flush_delayed~0, ~weak$$choice0~0, ~z$r_buff1_thd1~0, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ~__unbuffered_cnt~0, ULTIMATE.start_main_~#t676~0.offset, ~x~0, ~z$read_delayed~0, ~z$w_buff1~0, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite48, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_~#t676~0.base, ULTIMATE.start_main_~#t677~0.offset, ULTIMATE.start_main_#t~ite51, ~z$r_buff1_thd0~0, ~y~0, ~z$r_buff0_thd2~0, ULTIMATE.start_main_#t~nondet46, ~z$w_buff0_used~0, ~z$w_buff0~0, ULTIMATE.start_main_#t~nondet44, ~z$r_buff1_thd3~0, ~main$tmp_guard0~0, #NULL.base, ULTIMATE.start_main_#res, #valid, #memory_int, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 18:32:19,774 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [772] [772] L4-->L746: Formula: (and (= v_~z$r_buff0_thd1~0_29 v_~z$r_buff1_thd1~0_17) (= v_~z$r_buff0_thd2~0_25 v_~z$r_buff1_thd2~0_17) (= v_~z$r_buff0_thd3~0_70 v_~z$r_buff1_thd3~0_54) (= v_~z$r_buff0_thd1~0_28 1) (not (= 0 v_P0Thread1of1ForFork1___VERIFIER_assert_~expression_8)) (= v_~z$r_buff0_thd0~0_26 v_~z$r_buff1_thd0~0_23) (= v_~x~0_9 v_~__unbuffered_p0_EAX~0_11)) InVars {~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_26, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_70, P0Thread1of1ForFork1___VERIFIER_assert_~expression=v_P0Thread1of1ForFork1___VERIFIER_assert_~expression_8, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_29, ~x~0=v_~x~0_9, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_25} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_11, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_26, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_54, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_23, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_17, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_17, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_70, P0Thread1of1ForFork1___VERIFIER_assert_~expression=v_P0Thread1of1ForFork1___VERIFIER_assert_~expression_8, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_28, ~x~0=v_~x~0_9, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_25} AuxVars[] AssignedVars[~__unbuffered_p0_EAX~0, ~z$r_buff1_thd3~0, ~z$r_buff1_thd0~0, ~z$r_buff1_thd2~0, ~z$r_buff1_thd1~0, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 18:32:19,774 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [860] [860] L825-1-->L827: Formula: (and (= (store |v_#length_16| |v_ULTIMATE.start_main_~#t676~0.base_11| 4) |v_#length_15|) (= 0 (select |v_#valid_32| |v_ULTIMATE.start_main_~#t676~0.base_11|)) (not (= 0 |v_ULTIMATE.start_main_~#t676~0.base_11|)) (= 0 |v_ULTIMATE.start_main_~#t676~0.offset_10|) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t676~0.base_11| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t676~0.base_11|) |v_ULTIMATE.start_main_~#t676~0.offset_10| 1)) |v_#memory_int_13|) (= |v_#valid_31| (store |v_#valid_32| |v_ULTIMATE.start_main_~#t676~0.base_11| 1)) (< |v_#StackHeapBarrier_9| |v_ULTIMATE.start_main_~#t676~0.base_11|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_32|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_9|, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_4|, #valid=|v_#valid_31|, #memory_int=|v_#memory_int_13|, #length=|v_#length_15|, ULTIMATE.start_main_~#t676~0.offset=|v_ULTIMATE.start_main_~#t676~0.offset_10|, ULTIMATE.start_main_~#t676~0.base=|v_ULTIMATE.start_main_~#t676~0.base_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet44, #valid, #memory_int, #length, ULTIMATE.start_main_~#t676~0.offset, ULTIMATE.start_main_~#t676~0.base] because there is no mapped edge [2019-12-07 18:32:19,775 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [856] [856] L827-1-->L829: Formula: (and (not (= |v_ULTIMATE.start_main_~#t677~0.base_12| 0)) (< |v_#StackHeapBarrier_8| |v_ULTIMATE.start_main_~#t677~0.base_12|) (= (select |v_#valid_30| |v_ULTIMATE.start_main_~#t677~0.base_12|) 0) (= 0 |v_ULTIMATE.start_main_~#t677~0.offset_10|) (= (store |v_#valid_30| |v_ULTIMATE.start_main_~#t677~0.base_12| 1) |v_#valid_29|) (= (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t677~0.base_12| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t677~0.base_12|) |v_ULTIMATE.start_main_~#t677~0.offset_10| 2)) |v_#memory_int_11|) (= (store |v_#length_14| |v_ULTIMATE.start_main_~#t677~0.base_12| 4) |v_#length_13|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_8|, #valid=|v_#valid_30|, #memory_int=|v_#memory_int_12|, #length=|v_#length_14|} OutVars{ULTIMATE.start_main_~#t677~0.offset=|v_ULTIMATE.start_main_~#t677~0.offset_10|, #StackHeapBarrier=|v_#StackHeapBarrier_8|, ULTIMATE.start_main_~#t677~0.base=|v_ULTIMATE.start_main_~#t677~0.base_12|, #valid=|v_#valid_29|, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_5|, #memory_int=|v_#memory_int_11|, #length=|v_#length_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t677~0.offset, ULTIMATE.start_main_~#t677~0.base, #valid, ULTIMATE.start_main_#t~nondet45, #memory_int, #length] because there is no mapped edge [2019-12-07 18:32:19,776 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [843] [843] L766-2-->L766-5: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff1_used~0_In-841087192 256))) (.cse0 (= 0 (mod ~z$r_buff1_thd2~0_In-841087192 256))) (.cse2 (= |P1Thread1of1ForFork2_#t~ite9_Out-841087192| |P1Thread1of1ForFork2_#t~ite10_Out-841087192|))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork2_#t~ite9_Out-841087192| ~z~0_In-841087192) .cse2) (and (= |P1Thread1of1ForFork2_#t~ite9_Out-841087192| ~z$w_buff1~0_In-841087192) (not .cse1) (not .cse0) .cse2))) InVars {~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-841087192, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-841087192, ~z$w_buff1~0=~z$w_buff1~0_In-841087192, ~z~0=~z~0_In-841087192} OutVars{P1Thread1of1ForFork2_#t~ite9=|P1Thread1of1ForFork2_#t~ite9_Out-841087192|, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-841087192, P1Thread1of1ForFork2_#t~ite10=|P1Thread1of1ForFork2_#t~ite10_Out-841087192|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-841087192, ~z$w_buff1~0=~z$w_buff1~0_In-841087192, ~z~0=~z~0_In-841087192} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite9, P1Thread1of1ForFork2_#t~ite10] because there is no mapped edge [2019-12-07 18:32:19,777 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [871] [871] L792-->L792-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In1617421882 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite23_In1617421882| |P2Thread1of1ForFork0_#t~ite23_Out1617421882|) (= ~z$w_buff1~0_In1617421882 |P2Thread1of1ForFork0_#t~ite24_Out1617421882|) (not .cse0)) (and (= |P2Thread1of1ForFork0_#t~ite23_Out1617421882| |P2Thread1of1ForFork0_#t~ite24_Out1617421882|) (let ((.cse1 (= (mod ~z$r_buff0_thd3~0_In1617421882 256) 0))) (or (and (= (mod ~z$w_buff1_used~0_In1617421882 256) 0) .cse1) (and (= (mod ~z$r_buff1_thd3~0_In1617421882 256) 0) .cse1) (= 0 (mod ~z$w_buff0_used~0_In1617421882 256)))) .cse0 (= ~z$w_buff1~0_In1617421882 |P2Thread1of1ForFork0_#t~ite23_Out1617421882|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1617421882, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1617421882, P2Thread1of1ForFork0_#t~ite23=|P2Thread1of1ForFork0_#t~ite23_In1617421882|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1617421882, ~z$w_buff1~0=~z$w_buff1~0_In1617421882, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1617421882, ~weak$$choice2~0=~weak$$choice2~0_In1617421882} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1617421882, P2Thread1of1ForFork0_#t~ite23=|P2Thread1of1ForFork0_#t~ite23_Out1617421882|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In1617421882, P2Thread1of1ForFork0_#t~ite24=|P2Thread1of1ForFork0_#t~ite24_Out1617421882|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1617421882, ~z$w_buff1~0=~z$w_buff1~0_In1617421882, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1617421882, ~weak$$choice2~0=~weak$$choice2~0_In1617421882} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite23, P2Thread1of1ForFork0_#t~ite24] because there is no mapped edge [2019-12-07 18:32:19,778 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [884] [884] L794-->L794-8: Formula: (let ((.cse1 (= |P2Thread1of1ForFork0_#t~ite29_Out25440161| |P2Thread1of1ForFork0_#t~ite30_Out25440161|)) (.cse4 (= 0 (mod ~z$w_buff0_used~0_In25440161 256))) (.cse0 (= 0 (mod ~weak$$choice2~0_In25440161 256))) (.cse5 (= 0 (mod ~z$r_buff1_thd3~0_In25440161 256))) (.cse2 (= (mod ~z$w_buff1_used~0_In25440161 256) 0)) (.cse3 (= 0 (mod ~z$r_buff0_thd3~0_In25440161 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite28_In25440161| |P2Thread1of1ForFork0_#t~ite28_Out25440161|) (or (and (= |P2Thread1of1ForFork0_#t~ite29_Out25440161| |P2Thread1of1ForFork0_#t~ite29_In25440161|) (not .cse0) (= ~z$w_buff1_used~0_In25440161 |P2Thread1of1ForFork0_#t~ite30_Out25440161|)) (and (= ~z$w_buff1_used~0_In25440161 |P2Thread1of1ForFork0_#t~ite29_Out25440161|) .cse1 .cse0 (or (and .cse2 .cse3) .cse4 (and .cse5 .cse3))))) (let ((.cse6 (not .cse3))) (and (= |P2Thread1of1ForFork0_#t~ite29_Out25440161| |P2Thread1of1ForFork0_#t~ite28_Out25440161|) (= |P2Thread1of1ForFork0_#t~ite28_Out25440161| 0) .cse1 (not .cse4) .cse0 (or .cse6 (not .cse5)) (or (not .cse2) .cse6))))) InVars {P2Thread1of1ForFork0_#t~ite28=|P2Thread1of1ForFork0_#t~ite28_In25440161|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In25440161, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In25440161, ~z$w_buff1_used~0=~z$w_buff1_used~0_In25440161, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In25440161, ~weak$$choice2~0=~weak$$choice2~0_In25440161, P2Thread1of1ForFork0_#t~ite29=|P2Thread1of1ForFork0_#t~ite29_In25440161|} OutVars{P2Thread1of1ForFork0_#t~ite28=|P2Thread1of1ForFork0_#t~ite28_Out25440161|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In25440161, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In25440161, ~z$w_buff1_used~0=~z$w_buff1_used~0_In25440161, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In25440161, P2Thread1of1ForFork0_#t~ite30=|P2Thread1of1ForFork0_#t~ite30_Out25440161|, P2Thread1of1ForFork0_#t~ite29=|P2Thread1of1ForFork0_#t~ite29_Out25440161|, ~weak$$choice2~0=~weak$$choice2~0_In25440161} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite28, P2Thread1of1ForFork0_#t~ite30, P2Thread1of1ForFork0_#t~ite29] because there is no mapped edge [2019-12-07 18:32:19,778 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [890] [890] L794-8-->L796: Formula: (and (= v_~z$w_buff1_used~0_493 |v_P2Thread1of1ForFork0_#t~ite30_36|) (not (= (mod v_~weak$$choice2~0_130 256) 0)) (= v_~z$r_buff0_thd3~0_373 v_~z$r_buff0_thd3~0_372)) InVars {~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_373, P2Thread1of1ForFork0_#t~ite30=|v_P2Thread1of1ForFork0_#t~ite30_36|, ~weak$$choice2~0=v_~weak$$choice2~0_130} OutVars{P2Thread1of1ForFork0_#t~ite28=|v_P2Thread1of1ForFork0_#t~ite28_37|, P2Thread1of1ForFork0_#t~ite33=|v_P2Thread1of1ForFork0_#t~ite33_13|, P2Thread1of1ForFork0_#t~ite32=|v_P2Thread1of1ForFork0_#t~ite32_29|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_493, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_372, P2Thread1of1ForFork0_#t~ite31=|v_P2Thread1of1ForFork0_#t~ite31_21|, P2Thread1of1ForFork0_#t~ite30=|v_P2Thread1of1ForFork0_#t~ite30_35|, ~weak$$choice2~0=v_~weak$$choice2~0_130, P2Thread1of1ForFork0_#t~ite29=|v_P2Thread1of1ForFork0_#t~ite29_47|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite28, P2Thread1of1ForFork0_#t~ite33, P2Thread1of1ForFork0_#t~ite32, ~z$w_buff1_used~0, ~z$r_buff0_thd3~0, P2Thread1of1ForFork0_#t~ite31, P2Thread1of1ForFork0_#t~ite30, P2Thread1of1ForFork0_#t~ite29] because there is no mapped edge [2019-12-07 18:32:19,779 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [795] [795] L798-->L802: Formula: (and (not (= 0 (mod v_~z$flush_delayed~0_10 256))) (= 0 v_~z$flush_delayed~0_9) (= v_~z~0_46 v_~z$mem_tmp~0_7)) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_7, ~z$flush_delayed~0=v_~z$flush_delayed~0_10} OutVars{P2Thread1of1ForFork0_#t~ite37=|v_P2Thread1of1ForFork0_#t~ite37_5|, ~z$mem_tmp~0=v_~z$mem_tmp~0_7, ~z$flush_delayed~0=v_~z$flush_delayed~0_9, ~z~0=v_~z~0_46} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite37, ~z$flush_delayed~0, ~z~0] because there is no mapped edge [2019-12-07 18:32:19,779 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [819] [819] L802-2-->L802-5: Formula: (let ((.cse2 (= 0 (mod ~z$r_buff1_thd3~0_In21236130 256))) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In21236130 256))) (.cse1 (= |P2Thread1of1ForFork0_#t~ite39_Out21236130| |P2Thread1of1ForFork0_#t~ite38_Out21236130|))) (or (and (= |P2Thread1of1ForFork0_#t~ite38_Out21236130| ~z$w_buff1~0_In21236130) (not .cse0) .cse1 (not .cse2)) (and (= |P2Thread1of1ForFork0_#t~ite38_Out21236130| ~z~0_In21236130) (or .cse2 .cse0) .cse1))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In21236130, ~z$w_buff1_used~0=~z$w_buff1_used~0_In21236130, ~z$w_buff1~0=~z$w_buff1~0_In21236130, ~z~0=~z~0_In21236130} OutVars{P2Thread1of1ForFork0_#t~ite39=|P2Thread1of1ForFork0_#t~ite39_Out21236130|, P2Thread1of1ForFork0_#t~ite38=|P2Thread1of1ForFork0_#t~ite38_Out21236130|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In21236130, ~z$w_buff1_used~0=~z$w_buff1_used~0_In21236130, ~z$w_buff1~0=~z$w_buff1~0_In21236130, ~z~0=~z~0_In21236130} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite39, P2Thread1of1ForFork0_#t~ite38] because there is no mapped edge [2019-12-07 18:32:19,780 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [823] [823] L803-->L803-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In-1865552284 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd3~0_In-1865552284 256)))) (or (and (= |P2Thread1of1ForFork0_#t~ite40_Out-1865552284| 0) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= ~z$w_buff0_used~0_In-1865552284 |P2Thread1of1ForFork0_#t~ite40_Out-1865552284|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1865552284, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1865552284} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1865552284, P2Thread1of1ForFork0_#t~ite40=|P2Thread1of1ForFork0_#t~ite40_Out-1865552284|, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1865552284} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite40] because there is no mapped edge [2019-12-07 18:32:19,780 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [818] [818] L804-->L804-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd3~0_In-647140950 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In-647140950 256) 0)) (.cse2 (= (mod ~z$r_buff1_thd3~0_In-647140950 256) 0)) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In-647140950 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P2Thread1of1ForFork0_#t~ite41_Out-647140950| ~z$w_buff1_used~0_In-647140950)) (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P2Thread1of1ForFork0_#t~ite41_Out-647140950| 0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-647140950, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-647140950, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-647140950, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-647140950} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-647140950, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-647140950, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-647140950, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-647140950, P2Thread1of1ForFork0_#t~ite41=|P2Thread1of1ForFork0_#t~ite41_Out-647140950|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite41] because there is no mapped edge [2019-12-07 18:32:19,781 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [841] [841] L805-->L805-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In1007074940 256) 0)) (.cse0 (= (mod ~z$r_buff0_thd3~0_In1007074940 256) 0))) (or (and (= |P2Thread1of1ForFork0_#t~ite42_Out1007074940| ~z$r_buff0_thd3~0_In1007074940) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= |P2Thread1of1ForFork0_#t~ite42_Out1007074940| 0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1007074940, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1007074940} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1007074940, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In1007074940, P2Thread1of1ForFork0_#t~ite42=|P2Thread1of1ForFork0_#t~ite42_Out1007074940|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite42] because there is no mapped edge [2019-12-07 18:32:19,781 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [835] [835] L806-->L806-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In-292692101 256))) (.cse0 (= (mod ~z$w_buff0_used~0_In-292692101 256) 0)) (.cse3 (= 0 (mod ~z$r_buff1_thd3~0_In-292692101 256))) (.cse2 (= 0 (mod ~z$w_buff1_used~0_In-292692101 256)))) (or (and (or .cse0 .cse1) (= ~z$r_buff1_thd3~0_In-292692101 |P2Thread1of1ForFork0_#t~ite43_Out-292692101|) (or .cse2 .cse3)) (and (= |P2Thread1of1ForFork0_#t~ite43_Out-292692101| 0) (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-292692101, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-292692101, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-292692101, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-292692101} OutVars{P2Thread1of1ForFork0_#t~ite43=|P2Thread1of1ForFork0_#t~ite43_Out-292692101|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-292692101, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-292692101, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-292692101, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-292692101} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#t~ite43] because there is no mapped edge [2019-12-07 18:32:19,781 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [870] [870] L806-2-->P2EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_100 1) v_~__unbuffered_cnt~0_99) (= v_~z$r_buff1_thd3~0_306 |v_P2Thread1of1ForFork0_#t~ite43_54|) (= |v_P2Thread1of1ForFork0_#res.base_3| 0) (= |v_P2Thread1of1ForFork0_#res.offset_3| 0)) InVars {P2Thread1of1ForFork0_#t~ite43=|v_P2Thread1of1ForFork0_#t~ite43_54|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_100} OutVars{P2Thread1of1ForFork0_#res.base=|v_P2Thread1of1ForFork0_#res.base_3|, P2Thread1of1ForFork0_#t~ite43=|v_P2Thread1of1ForFork0_#t~ite43_53|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_306, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_99, P2Thread1of1ForFork0_#res.offset=|v_P2Thread1of1ForFork0_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork0_#res.base, P2Thread1of1ForFork0_#t~ite43, ~z$r_buff1_thd3~0, ~__unbuffered_cnt~0, P2Thread1of1ForFork0_#res.offset] because there is no mapped edge [2019-12-07 18:32:19,782 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [838] [838] L747-->L747-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In1091333495 256))) (.cse1 (= (mod ~z$r_buff0_thd1~0_In1091333495 256) 0))) (or (and (not .cse0) (not .cse1) (= 0 |P0Thread1of1ForFork1_#t~ite5_Out1091333495|)) (and (= ~z$w_buff0_used~0_In1091333495 |P0Thread1of1ForFork1_#t~ite5_Out1091333495|) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1091333495, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1091333495} OutVars{P0Thread1of1ForFork1_#t~ite5=|P0Thread1of1ForFork1_#t~ite5_Out1091333495|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1091333495, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1091333495} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite5] because there is no mapped edge [2019-12-07 18:32:19,782 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [842] [842] L748-->L748-2: Formula: (let ((.cse1 (= (mod ~z$r_buff1_thd1~0_In281471796 256) 0)) (.cse0 (= (mod ~z$w_buff1_used~0_In281471796 256) 0)) (.cse3 (= 0 (mod ~z$r_buff0_thd1~0_In281471796 256))) (.cse2 (= (mod ~z$w_buff0_used~0_In281471796 256) 0))) (or (and (= ~z$w_buff1_used~0_In281471796 |P0Thread1of1ForFork1_#t~ite6_Out281471796|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (= 0 |P0Thread1of1ForFork1_#t~ite6_Out281471796|) (or (and (not .cse1) (not .cse0)) (and (not .cse3) (not .cse2)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In281471796, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In281471796, ~z$w_buff1_used~0=~z$w_buff1_used~0_In281471796, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In281471796} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In281471796, P0Thread1of1ForFork1_#t~ite6=|P0Thread1of1ForFork1_#t~ite6_Out281471796|, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In281471796, ~z$w_buff1_used~0=~z$w_buff1_used~0_In281471796, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In281471796} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite6] because there is no mapped edge [2019-12-07 18:32:19,782 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [824] [824] L749-->L750: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In1515198035 256))) (.cse2 (= 0 (mod ~z$r_buff0_thd1~0_In1515198035 256))) (.cse1 (= ~z$r_buff0_thd1~0_Out1515198035 ~z$r_buff0_thd1~0_In1515198035))) (or (and .cse0 .cse1) (and (not .cse0) (not .cse2) (= ~z$r_buff0_thd1~0_Out1515198035 0)) (and .cse2 .cse1))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1515198035, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1515198035} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1515198035, P0Thread1of1ForFork1_#t~ite7=|P0Thread1of1ForFork1_#t~ite7_Out1515198035|, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_Out1515198035} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite7, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 18:32:19,782 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [826] [826] L750-->L750-2: Formula: (let ((.cse2 (= 0 (mod ~z$r_buff0_thd1~0_In1102816513 256))) (.cse3 (= (mod ~z$w_buff0_used~0_In1102816513 256) 0)) (.cse0 (= (mod ~z$r_buff1_thd1~0_In1102816513 256) 0)) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In1102816513 256)))) (or (and (= 0 |P0Thread1of1ForFork1_#t~ite8_Out1102816513|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse2 .cse3) (= ~z$r_buff1_thd1~0_In1102816513 |P0Thread1of1ForFork1_#t~ite8_Out1102816513|) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1102816513, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In1102816513, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1102816513, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1102816513} OutVars{P0Thread1of1ForFork1_#t~ite8=|P0Thread1of1ForFork1_#t~ite8_Out1102816513|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1102816513, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In1102816513, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1102816513, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In1102816513} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite8] because there is no mapped edge [2019-12-07 18:32:19,782 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [853] [853] L750-2-->P0EXIT: Formula: (and (= 0 |v_P0Thread1of1ForFork1_#res.base_3|) (= v_~__unbuffered_cnt~0_71 (+ v_~__unbuffered_cnt~0_72 1)) (= v_~z$r_buff1_thd1~0_83 |v_P0Thread1of1ForFork1_#t~ite8_38|) (= 0 |v_P0Thread1of1ForFork1_#res.offset_3|)) InVars {P0Thread1of1ForFork1_#t~ite8=|v_P0Thread1of1ForFork1_#t~ite8_38|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_72} OutVars{P0Thread1of1ForFork1_#t~ite8=|v_P0Thread1of1ForFork1_#t~ite8_37|, P0Thread1of1ForFork1_#res.offset=|v_P0Thread1of1ForFork1_#res.offset_3|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_83, P0Thread1of1ForFork1_#res.base=|v_P0Thread1of1ForFork1_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_71} AuxVars[] AssignedVars[P0Thread1of1ForFork1_#t~ite8, P0Thread1of1ForFork1_#res.offset, ~z$r_buff1_thd1~0, P0Thread1of1ForFork1_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 18:32:19,783 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [831] [831] L767-->L767-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd2~0_In-913321069 256))) (.cse0 (= (mod ~z$w_buff0_used~0_In-913321069 256) 0))) (or (and (or .cse0 .cse1) (= |P1Thread1of1ForFork2_#t~ite11_Out-913321069| ~z$w_buff0_used~0_In-913321069)) (and (= |P1Thread1of1ForFork2_#t~ite11_Out-913321069| 0) (not .cse1) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-913321069, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-913321069} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-913321069, P1Thread1of1ForFork2_#t~ite11=|P1Thread1of1ForFork2_#t~ite11_Out-913321069|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-913321069} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite11] because there is no mapped edge [2019-12-07 18:32:19,783 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [836] [836] L768-->L768-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In1540550293 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd2~0_In1540550293 256))) (.cse2 (= 0 (mod ~z$r_buff1_thd2~0_In1540550293 256))) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In1540550293 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork2_#t~ite12_Out1540550293|)) (and (= ~z$w_buff1_used~0_In1540550293 |P1Thread1of1ForFork2_#t~ite12_Out1540550293|) (or .cse0 .cse1) (or .cse2 .cse3)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1540550293, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1540550293, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1540550293, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1540550293} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1540550293, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1540550293, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1540550293, P1Thread1of1ForFork2_#t~ite12=|P1Thread1of1ForFork2_#t~ite12_Out1540550293|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1540550293} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite12] because there is no mapped edge [2019-12-07 18:32:19,783 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [825] [825] L769-->L769-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In945169287 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In945169287 256)))) (or (and (= ~z$r_buff0_thd2~0_In945169287 |P1Thread1of1ForFork2_#t~ite13_Out945169287|) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= 0 |P1Thread1of1ForFork2_#t~ite13_Out945169287|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In945169287, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In945169287} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In945169287, P1Thread1of1ForFork2_#t~ite13=|P1Thread1of1ForFork2_#t~ite13_Out945169287|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In945169287} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite13] because there is no mapped edge [2019-12-07 18:32:19,784 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [821] [821] L770-->L770-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In-1320061449 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In-1320061449 256))) (.cse2 (= (mod ~z$r_buff1_thd2~0_In-1320061449 256) 0)) (.cse3 (= (mod ~z$w_buff1_used~0_In-1320061449 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P1Thread1of1ForFork2_#t~ite14_Out-1320061449|)) (and (or .cse1 .cse0) (= ~z$r_buff1_thd2~0_In-1320061449 |P1Thread1of1ForFork2_#t~ite14_Out-1320061449|) (or .cse2 .cse3)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1320061449, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1320061449, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1320061449, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1320061449} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1320061449, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-1320061449, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1320061449, P1Thread1of1ForFork2_#t~ite14=|P1Thread1of1ForFork2_#t~ite14_Out-1320061449|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-1320061449} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#t~ite14] because there is no mapped edge [2019-12-07 18:32:19,784 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [868] [868] L770-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork2_#res.offset_3|) (= 0 |v_P1Thread1of1ForFork2_#res.base_3|) (= v_~z$r_buff1_thd2~0_186 |v_P1Thread1of1ForFork2_#t~ite14_48|) (= (+ v_~__unbuffered_cnt~0_94 1) v_~__unbuffered_cnt~0_93)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_94, P1Thread1of1ForFork2_#t~ite14=|v_P1Thread1of1ForFork2_#t~ite14_48|} OutVars{P1Thread1of1ForFork2_#res.offset=|v_P1Thread1of1ForFork2_#res.offset_3|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_186, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_93, P1Thread1of1ForFork2_#t~ite14=|v_P1Thread1of1ForFork2_#t~ite14_47|, P1Thread1of1ForFork2_#res.base=|v_P1Thread1of1ForFork2_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork2_#res.offset, ~z$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork2_#t~ite14, P1Thread1of1ForFork2_#res.base] because there is no mapped edge [2019-12-07 18:32:19,784 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L829-1-->L835: Formula: (and (= v_~main$tmp_guard0~0_6 (ite (= (ite (= 3 v_~__unbuffered_cnt~0_14) 1 0) 0) 0 1)) (not (= 0 (mod v_~main$tmp_guard0~0_6 256)))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14} OutVars{ULTIMATE.start_main_#t~nondet46=|v_ULTIMATE.start_main_#t~nondet46_5|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_14, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet46, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 18:32:19,784 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [832] [832] L835-2-->L835-4: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd0~0_In1651619703 256) 0)) (.cse1 (= 0 (mod ~z$w_buff1_used~0_In1651619703 256)))) (or (and (not .cse0) (not .cse1) (= |ULTIMATE.start_main_#t~ite47_Out1651619703| ~z$w_buff1~0_In1651619703)) (and (= |ULTIMATE.start_main_#t~ite47_Out1651619703| ~z~0_In1651619703) (or .cse0 .cse1)))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1651619703, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1651619703, ~z$w_buff1~0=~z$w_buff1~0_In1651619703, ~z~0=~z~0_In1651619703} OutVars{~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1651619703, ULTIMATE.start_main_#t~ite47=|ULTIMATE.start_main_#t~ite47_Out1651619703|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1651619703, ~z$w_buff1~0=~z$w_buff1~0_In1651619703, ~z~0=~z~0_In1651619703} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47] because there is no mapped edge [2019-12-07 18:32:19,784 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [789] [789] L835-4-->L836: Formula: (= v_~z~0_40 |v_ULTIMATE.start_main_#t~ite47_9|) InVars {ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_9|} OutVars{ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_8|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_12|, ~z~0=v_~z~0_40} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite48, ~z~0] because there is no mapped edge [2019-12-07 18:32:19,785 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [830] [830] L836-->L836-2: Formula: (let ((.cse0 (= (mod ~z$w_buff0_used~0_In1566783785 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd0~0_In1566783785 256)))) (or (and (= 0 |ULTIMATE.start_main_#t~ite49_Out1566783785|) (not .cse0) (not .cse1)) (and (= ~z$w_buff0_used~0_In1566783785 |ULTIMATE.start_main_#t~ite49_Out1566783785|) (or .cse0 .cse1)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1566783785, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1566783785} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1566783785, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1566783785, ULTIMATE.start_main_#t~ite49=|ULTIMATE.start_main_#t~ite49_Out1566783785|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite49] because there is no mapped edge [2019-12-07 18:32:19,785 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [817] [817] L837-->L837-2: Formula: (let ((.cse2 (= 0 (mod ~z$r_buff0_thd0~0_In1372692094 256))) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In1372692094 256))) (.cse0 (= (mod ~z$r_buff1_thd0~0_In1372692094 256) 0)) (.cse1 (= (mod ~z$w_buff1_used~0_In1372692094 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |ULTIMATE.start_main_#t~ite50_Out1372692094| 0)) (and (or .cse2 .cse3) (= |ULTIMATE.start_main_#t~ite50_Out1372692094| ~z$w_buff1_used~0_In1372692094) (or .cse0 .cse1)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1372692094, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1372692094, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1372692094, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1372692094} OutVars{ULTIMATE.start_main_#t~ite50=|ULTIMATE.start_main_#t~ite50_Out1372692094|, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In1372692094, ~z$w_buff0_used~0=~z$w_buff0_used~0_In1372692094, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In1372692094, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1372692094} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite50] because there is no mapped edge [2019-12-07 18:32:19,785 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [833] [833] L838-->L838-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd0~0_In926361585 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In926361585 256) 0))) (or (and (not .cse0) (= |ULTIMATE.start_main_#t~ite51_Out926361585| 0) (not .cse1)) (and (or .cse0 .cse1) (= ~z$r_buff0_thd0~0_In926361585 |ULTIMATE.start_main_#t~ite51_Out926361585|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In926361585, ~z$w_buff0_used~0=~z$w_buff0_used~0_In926361585} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In926361585, ULTIMATE.start_main_#t~ite51=|ULTIMATE.start_main_#t~ite51_Out926361585|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In926361585} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite51] because there is no mapped edge [2019-12-07 18:32:19,786 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [834] [834] L839-->L839-2: Formula: (let ((.cse3 (= (mod ~z$r_buff0_thd0~0_In763159009 256) 0)) (.cse2 (= (mod ~z$w_buff0_used~0_In763159009 256) 0)) (.cse0 (= (mod ~z$r_buff1_thd0~0_In763159009 256) 0)) (.cse1 (= (mod ~z$w_buff1_used~0_In763159009 256) 0))) (or (and (= ~z$r_buff1_thd0~0_In763159009 |ULTIMATE.start_main_#t~ite52_Out763159009|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1))) (= 0 |ULTIMATE.start_main_#t~ite52_Out763159009|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In763159009, ~z$w_buff0_used~0=~z$w_buff0_used~0_In763159009, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In763159009, ~z$w_buff1_used~0=~z$w_buff1_used~0_In763159009} OutVars{ULTIMATE.start_main_#t~ite52=|ULTIMATE.start_main_#t~ite52_Out763159009|, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In763159009, ~z$w_buff0_used~0=~z$w_buff0_used~0_In763159009, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In763159009, ~z$w_buff1_used~0=~z$w_buff1_used~0_In763159009} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52] because there is no mapped edge [2019-12-07 18:32:19,786 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [877] [877] L839-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_12 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|) (= v_~main$tmp_guard1~0_16 (ite (= (ite (not (and (= v_~y~0_25 2) (= 2 v_~__unbuffered_p2_EAX~0_21) (= v_~__unbuffered_p2_EBX~0_34 0) (= 0 v_~__unbuffered_p0_EAX~0_178))) 1 0) 0) 0 1)) (= v_~z$r_buff1_thd0~0_219 |v_ULTIMATE.start_main_#t~ite52_38|) (= v_ULTIMATE.start___VERIFIER_assert_~expression_12 0) (= |v_ULTIMATE.start___VERIFIER_assert_#in~expression_8| (mod v_~main$tmp_guard1~0_16 256))) InVars {~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_178, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_38|, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_34, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_21, ~y~0=v_~y~0_25} OutVars{~__unbuffered_p0_EAX~0=v_~__unbuffered_p0_EAX~0_178, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_37|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_12, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_34, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_219, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_16, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_21, ~y~0=v_~y~0_25, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_8|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start___VERIFIER_assert_~expression, ~z$r_buff1_thd0~0, ~main$tmp_guard1~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:32:19,835 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_4b6765ec-d8fe-4308-afe8-c4ab758a5330/bin/uautomizer/witness.graphml [2019-12-07 18:32:19,835 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 18:32:19,836 INFO L168 Benchmark]: Toolchain (without parser) took 249182.02 ms. Allocated memory was 1.0 GB in the beginning and 9.1 GB in the end (delta: 8.1 GB). Free memory was 939.8 MB in the beginning and 6.3 GB in the end (delta: -5.4 GB). Peak memory consumption was 2.7 GB. Max. memory is 11.5 GB. [2019-12-07 18:32:19,836 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 961.3 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:32:19,837 INFO L168 Benchmark]: CACSL2BoogieTranslator took 369.39 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 97.5 MB). Free memory was 939.8 MB in the beginning and 1.1 GB in the end (delta: -129.7 MB). Peak memory consumption was 29.1 MB. Max. memory is 11.5 GB. [2019-12-07 18:32:19,837 INFO L168 Benchmark]: Boogie Procedure Inliner took 36.18 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 18:32:19,837 INFO L168 Benchmark]: Boogie Preprocessor took 26.19 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:32:19,837 INFO L168 Benchmark]: RCFGBuilder took 397.30 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 55.2 MB). Peak memory consumption was 55.2 MB. Max. memory is 11.5 GB. [2019-12-07 18:32:19,838 INFO L168 Benchmark]: TraceAbstraction took 248283.22 ms. Allocated memory was 1.1 GB in the beginning and 9.1 GB in the end (delta: 8.0 GB). Free memory was 1.0 GB in the beginning and 6.4 GB in the end (delta: -5.3 GB). Peak memory consumption was 2.6 GB. Max. memory is 11.5 GB. [2019-12-07 18:32:19,838 INFO L168 Benchmark]: Witness Printer took 64.11 ms. Allocated memory is still 9.1 GB. Free memory was 6.4 GB in the beginning and 6.3 GB in the end (delta: 45.7 MB). Peak memory consumption was 45.7 MB. Max. memory is 11.5 GB. [2019-12-07 18:32:19,839 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19 ms. Allocated memory is still 1.0 GB. Free memory is still 961.3 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 369.39 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 97.5 MB). Free memory was 939.8 MB in the beginning and 1.1 GB in the end (delta: -129.7 MB). Peak memory consumption was 29.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 36.18 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 26.19 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 397.30 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 55.2 MB). Peak memory consumption was 55.2 MB. Max. memory is 11.5 GB. * TraceAbstraction took 248283.22 ms. Allocated memory was 1.1 GB in the beginning and 9.1 GB in the end (delta: 8.0 GB). Free memory was 1.0 GB in the beginning and 6.4 GB in the end (delta: -5.3 GB). Peak memory consumption was 2.6 GB. Max. memory is 11.5 GB. * Witness Printer took 64.11 ms. Allocated memory is still 9.1 GB. Free memory was 6.4 GB in the beginning and 6.3 GB in the end (delta: 45.7 MB). Peak memory consumption was 45.7 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.2s, 176 ProgramPointsBefore, 94 ProgramPointsAfterwards, 213 TransitionsBefore, 105 TransitionsAfterwards, 19004 CoEnabledTransitionPairs, 12 FixpointIterations, 33 TrivialSequentialCompositions, 53 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 34 ConcurrentYvCompositions, 30 ChoiceCompositions, 7047 VarBasedMoverChecksPositive, 336 VarBasedMoverChecksNegative, 168 SemBasedMoverChecksPositive, 252 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 1.0s, 0 MoverChecksTotal, 130103 CheckedPairsTotal, 120 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L825] FCALL, FORK 0 pthread_create(&t675, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L731] 1 z$w_buff1 = z$w_buff0 [L732] 1 z$w_buff0 = 1 [L733] 1 z$w_buff1_used = z$w_buff0_used [L734] 1 z$w_buff0_used = (_Bool)1 [L746] EXPR 1 z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L827] FCALL, FORK 0 pthread_create(&t676, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L760] 2 x = 1 [L763] 2 y = 1 VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L766] EXPR 2 z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L829] FCALL, FORK 0 pthread_create(&t677, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L780] 3 y = 2 [L783] 3 __unbuffered_p2_EAX = y [L786] 3 weak$$choice0 = __VERIFIER_nondet_bool() [L787] 3 weak$$choice2 = __VERIFIER_nondet_bool() [L788] 3 z$flush_delayed = weak$$choice2 [L789] 3 z$mem_tmp = z VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, x=1, y=2, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L790] EXPR 3 !z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff1) VAL [!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, x=1, y=2, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L790] 3 z = !z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff1) [L766] 2 z = z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z) [L791] EXPR 3 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff0))=1, x=1, y=2, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L791] 3 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff0)) [L792] 3 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff1 : z$w_buff1)) [L793] EXPR 3 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used))=1, x=1, y=2, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L793] 3 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used)) [L796] EXPR 3 weak$$choice2 ? z$r_buff1_thd3 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$r_buff1_thd3 : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, weak$$choice2 ? z$r_buff1_thd3 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$r_buff1_thd3 : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0))=0, x=1, y=2, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L796] 3 z$r_buff1_thd3 = weak$$choice2 ? z$r_buff1_thd3 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$r_buff1_thd3 : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) [L797] 3 __unbuffered_p2_EBX = z VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, x=1, y=2, z=0, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L802] EXPR 3 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, x=1, y=2, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L802] 3 z = z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) [L803] 3 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used [L804] 3 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used [L805] 3 z$r_buff0_thd3 = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 [L746] 1 z = z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) [L747] 1 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$w_buff0_used [L748] 1 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd1 || z$w_buff1_used && z$r_buff1_thd1 ? (_Bool)0 : z$w_buff1_used [L767] 2 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used [L768] 2 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$w_buff1_used [L769] 2 z$r_buff0_thd2 = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2 [L835] 0 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p0_EAX=0, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=8, weak$$choice2=1, x=1, y=2, z=1, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L836] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L837] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L838] 0 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 167 locations, 2 error locations. Result: UNSAFE, OverallTime: 248.1s, OverallIterations: 37, TraceHistogramMax: 1, AutomataDifference: 74.6s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 10231 SDtfs, 11868 SDslu, 39464 SDs, 0 SdLazy, 27855 SolverSat, 513 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 24.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 597 GetRequests, 52 SyntacticMatches, 21 SemanticMatches, 524 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7716 ImplicationChecksByTransitivity, 8.9s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=371396occurred in iteration=7, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 148.0s AutomataMinimizationTime, 36 MinimizatonAttempts, 707518 StatesRemovedByMinimization, 34 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 2.8s InterpolantComputationTime, 1547 NumberOfCodeBlocks, 1547 NumberOfCodeBlocksAsserted, 37 NumberOfCheckSat, 1445 ConstructedInterpolants, 0 QuantifiedInterpolants, 415623 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 36 InterpolantComputations, 36 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...