./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/mix028_power.oepc.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_98bf8e3e-5cb9-4779-8088-2a499a538fd8/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_98bf8e3e-5cb9-4779-8088-2a499a538fd8/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_98bf8e3e-5cb9-4779-8088-2a499a538fd8/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_98bf8e3e-5cb9-4779-8088-2a499a538fd8/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/mix028_power.oepc.i -s /tmp/vcloud-vcloud-master/worker/run_dir_98bf8e3e-5cb9-4779-8088-2a499a538fd8/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_98bf8e3e-5cb9-4779-8088-2a499a538fd8/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash acec2d8ff98ffb0b89db33c8f53b9578d382c52c ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 17:57:49,017 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 17:57:49,019 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 17:57:49,026 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 17:57:49,026 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 17:57:49,027 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 17:57:49,028 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 17:57:49,029 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 17:57:49,031 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 17:57:49,031 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 17:57:49,032 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 17:57:49,033 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 17:57:49,033 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 17:57:49,033 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 17:57:49,034 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 17:57:49,035 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 17:57:49,035 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 17:57:49,036 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 17:57:49,037 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 17:57:49,039 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 17:57:49,040 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 17:57:49,040 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 17:57:49,041 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 17:57:49,042 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 17:57:49,043 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 17:57:49,043 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 17:57:49,044 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 17:57:49,044 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 17:57:49,044 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 17:57:49,045 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 17:57:49,045 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 17:57:49,045 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 17:57:49,046 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 17:57:49,046 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 17:57:49,047 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 17:57:49,047 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 17:57:49,047 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 17:57:49,047 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 17:57:49,048 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 17:57:49,048 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 17:57:49,048 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 17:57:49,049 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_98bf8e3e-5cb9-4779-8088-2a499a538fd8/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 17:57:49,058 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 17:57:49,058 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 17:57:49,059 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 17:57:49,059 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 17:57:49,059 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 17:57:49,059 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 17:57:49,059 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 17:57:49,059 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 17:57:49,059 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 17:57:49,059 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 17:57:49,059 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 17:57:49,060 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 17:57:49,060 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 17:57:49,060 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 17:57:49,060 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 17:57:49,060 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 17:57:49,060 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 17:57:49,060 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 17:57:49,060 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 17:57:49,060 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 17:57:49,060 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 17:57:49,061 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 17:57:49,061 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 17:57:49,061 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 17:57:49,061 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 17:57:49,061 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 17:57:49,061 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 17:57:49,061 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 17:57:49,061 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 17:57:49,062 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_98bf8e3e-5cb9-4779-8088-2a499a538fd8/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> acec2d8ff98ffb0b89db33c8f53b9578d382c52c [2019-12-07 17:57:49,160 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 17:57:49,170 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 17:57:49,173 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 17:57:49,174 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 17:57:49,175 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 17:57:49,175 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_98bf8e3e-5cb9-4779-8088-2a499a538fd8/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/mix028_power.oepc.i [2019-12-07 17:57:49,217 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_98bf8e3e-5cb9-4779-8088-2a499a538fd8/bin/uautomizer/data/8c7de10a8/be85315e45e54b218e1fba6162273a63/FLAG7ad288b49 [2019-12-07 17:57:49,674 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 17:57:49,674 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_98bf8e3e-5cb9-4779-8088-2a499a538fd8/sv-benchmarks/c/pthread-wmm/mix028_power.oepc.i [2019-12-07 17:57:49,685 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_98bf8e3e-5cb9-4779-8088-2a499a538fd8/bin/uautomizer/data/8c7de10a8/be85315e45e54b218e1fba6162273a63/FLAG7ad288b49 [2019-12-07 17:57:50,198 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_98bf8e3e-5cb9-4779-8088-2a499a538fd8/bin/uautomizer/data/8c7de10a8/be85315e45e54b218e1fba6162273a63 [2019-12-07 17:57:50,201 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 17:57:50,202 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 17:57:50,202 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 17:57:50,203 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 17:57:50,205 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 17:57:50,206 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 05:57:50" (1/1) ... [2019-12-07 17:57:50,208 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7b6fc423 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:57:50, skipping insertion in model container [2019-12-07 17:57:50,208 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 05:57:50" (1/1) ... [2019-12-07 17:57:50,214 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 17:57:50,245 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 17:57:50,489 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 17:57:50,497 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 17:57:50,540 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 17:57:50,585 INFO L208 MainTranslator]: Completed translation [2019-12-07 17:57:50,585 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:57:50 WrapperNode [2019-12-07 17:57:50,585 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 17:57:50,586 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 17:57:50,586 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 17:57:50,586 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 17:57:50,592 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:57:50" (1/1) ... [2019-12-07 17:57:50,605 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:57:50" (1/1) ... [2019-12-07 17:57:50,624 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 17:57:50,625 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 17:57:50,625 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 17:57:50,625 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 17:57:50,631 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:57:50" (1/1) ... [2019-12-07 17:57:50,632 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:57:50" (1/1) ... [2019-12-07 17:57:50,635 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:57:50" (1/1) ... [2019-12-07 17:57:50,635 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:57:50" (1/1) ... [2019-12-07 17:57:50,642 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:57:50" (1/1) ... [2019-12-07 17:57:50,645 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:57:50" (1/1) ... [2019-12-07 17:57:50,648 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:57:50" (1/1) ... [2019-12-07 17:57:50,651 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 17:57:50,651 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 17:57:50,651 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 17:57:50,652 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 17:57:50,652 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:57:50" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_98bf8e3e-5cb9-4779-8088-2a499a538fd8/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 17:57:50,693 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 17:57:50,693 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 17:57:50,694 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 17:57:50,694 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 17:57:50,694 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 17:57:50,694 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 17:57:50,694 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 17:57:50,694 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 17:57:50,694 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 17:57:50,694 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 17:57:50,694 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 17:57:50,694 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 17:57:50,694 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 17:57:50,695 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 17:57:51,056 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 17:57:51,056 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 17:57:51,057 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:57:51 BoogieIcfgContainer [2019-12-07 17:57:51,057 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 17:57:51,058 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 17:57:51,058 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 17:57:51,060 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 17:57:51,060 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 05:57:50" (1/3) ... [2019-12-07 17:57:51,060 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2fd37dbf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 05:57:51, skipping insertion in model container [2019-12-07 17:57:51,060 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 05:57:50" (2/3) ... [2019-12-07 17:57:51,061 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2fd37dbf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 05:57:51, skipping insertion in model container [2019-12-07 17:57:51,061 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:57:51" (3/3) ... [2019-12-07 17:57:51,062 INFO L109 eAbstractionObserver]: Analyzing ICFG mix028_power.oepc.i [2019-12-07 17:57:51,068 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 17:57:51,068 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 17:57:51,073 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 17:57:51,074 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 17:57:51,099 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,099 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,099 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,099 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,099 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,099 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,100 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,100 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,100 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,100 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,100 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,100 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,100 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,101 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,101 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,101 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,101 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,101 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,101 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,101 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,101 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,101 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,102 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,102 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,102 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,102 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,102 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,102 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,102 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,102 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,102 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,103 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,103 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,103 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,103 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,103 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,103 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,103 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,104 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,104 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,104 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,104 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,104 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,104 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,104 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,104 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,105 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,105 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,105 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,105 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,105 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,105 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,105 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,105 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,105 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,106 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,106 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,106 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,106 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,106 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,106 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,106 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,106 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,107 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,107 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,107 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~nondet15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,107 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~nondet16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,108 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,108 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,108 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~nondet15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,108 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,108 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~nondet16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,108 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,108 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,108 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,108 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,109 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,109 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,109 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,109 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,109 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,109 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,109 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,109 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,109 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,109 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,110 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,110 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,110 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,110 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,110 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,110 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,110 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,110 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,110 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,111 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,111 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,111 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,111 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,111 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,111 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,111 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,111 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,112 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,112 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,112 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,112 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,112 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,112 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,112 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,112 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,112 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,112 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,113 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,113 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,113 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,113 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,113 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,113 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,113 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,113 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,113 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,113 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,114 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,114 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,114 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,114 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,114 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,114 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,114 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,114 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,114 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,114 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,115 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,115 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,115 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,115 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,115 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,115 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,115 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,115 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,115 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,116 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,116 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,116 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,116 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,116 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,116 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,116 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,116 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,116 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,116 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,117 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,117 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite37| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,117 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,117 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,117 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,117 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,117 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,117 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,117 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,117 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,117 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,118 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,118 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite38| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,118 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite39| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,118 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,118 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite40| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,118 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,118 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,118 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,118 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite41| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,118 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,119 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,119 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,119 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite42| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,119 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,119 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,119 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,119 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite43| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,119 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,119 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 17:57:51,130 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 17:57:51,142 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 17:57:51,142 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 17:57:51,142 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 17:57:51,142 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 17:57:51,142 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 17:57:51,143 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 17:57:51,143 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 17:57:51,143 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 17:57:51,154 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 175 places, 212 transitions [2019-12-07 17:57:51,155 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 175 places, 212 transitions [2019-12-07 17:57:51,211 INFO L134 PetriNetUnfolder]: 47/209 cut-off events. [2019-12-07 17:57:51,211 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 17:57:51,222 INFO L76 FinitePrefix]: Finished finitePrefix Result has 219 conditions, 209 events. 47/209 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 11. Compared 682 event pairs. 9/169 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 17:57:51,238 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 175 places, 212 transitions [2019-12-07 17:57:51,269 INFO L134 PetriNetUnfolder]: 47/209 cut-off events. [2019-12-07 17:57:51,269 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 17:57:51,275 INFO L76 FinitePrefix]: Finished finitePrefix Result has 219 conditions, 209 events. 47/209 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 11. Compared 682 event pairs. 9/169 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 17:57:51,291 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 19004 [2019-12-07 17:57:51,292 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 17:57:54,502 WARN L192 SmtUtils]: Spent 127.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 44 [2019-12-07 17:57:54,765 WARN L192 SmtUtils]: Spent 133.00 ms on a formula simplification. DAG size of input: 89 DAG size of output: 87 [2019-12-07 17:57:54,850 INFO L206 etLargeBlockEncoding]: Checked pairs total: 87070 [2019-12-07 17:57:54,850 INFO L214 etLargeBlockEncoding]: Total number of compositions: 113 [2019-12-07 17:57:54,852 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 93 places, 102 transitions [2019-12-07 17:58:10,373 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 115112 states. [2019-12-07 17:58:10,375 INFO L276 IsEmpty]: Start isEmpty. Operand 115112 states. [2019-12-07 17:58:10,379 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-12-07 17:58:10,379 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:58:10,380 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-12-07 17:58:10,380 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:58:10,384 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:58:10,384 INFO L82 PathProgramCache]: Analyzing trace with hash 911890, now seen corresponding path program 1 times [2019-12-07 17:58:10,390 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:58:10,390 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1456334606] [2019-12-07 17:58:10,390 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:58:10,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:58:10,539 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:58:10,540 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1456334606] [2019-12-07 17:58:10,540 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:58:10,540 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 17:58:10,541 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1370434135] [2019-12-07 17:58:10,544 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:58:10,544 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:58:10,553 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:58:10,553 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:58:10,554 INFO L87 Difference]: Start difference. First operand 115112 states. Second operand 3 states. [2019-12-07 17:58:11,316 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:58:11,316 INFO L93 Difference]: Finished difference Result 114158 states and 484836 transitions. [2019-12-07 17:58:11,317 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:58:11,318 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2019-12-07 17:58:11,318 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:58:11,991 INFO L225 Difference]: With dead ends: 114158 [2019-12-07 17:58:11,992 INFO L226 Difference]: Without dead ends: 107060 [2019-12-07 17:58:11,992 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:58:17,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107060 states. [2019-12-07 17:58:18,708 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107060 to 107060. [2019-12-07 17:58:18,709 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 107060 states. [2019-12-07 17:58:19,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 107060 states to 107060 states and 454078 transitions. [2019-12-07 17:58:19,073 INFO L78 Accepts]: Start accepts. Automaton has 107060 states and 454078 transitions. Word has length 3 [2019-12-07 17:58:19,073 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:58:19,073 INFO L462 AbstractCegarLoop]: Abstraction has 107060 states and 454078 transitions. [2019-12-07 17:58:19,074 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:58:19,074 INFO L276 IsEmpty]: Start isEmpty. Operand 107060 states and 454078 transitions. [2019-12-07 17:58:19,077 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-12-07 17:58:19,077 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:58:19,077 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:58:19,077 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:58:19,077 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:58:19,078 INFO L82 PathProgramCache]: Analyzing trace with hash 1487504284, now seen corresponding path program 1 times [2019-12-07 17:58:19,078 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:58:19,078 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1481285789] [2019-12-07 17:58:19,078 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:58:19,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:58:19,155 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:58:19,155 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1481285789] [2019-12-07 17:58:19,155 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:58:19,155 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:58:19,155 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1139935905] [2019-12-07 17:58:19,156 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:58:19,156 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:58:19,157 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:58:19,157 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:58:19,157 INFO L87 Difference]: Start difference. First operand 107060 states and 454078 transitions. Second operand 4 states. [2019-12-07 17:58:20,308 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:58:20,309 INFO L93 Difference]: Finished difference Result 166396 states and 678148 transitions. [2019-12-07 17:58:20,309 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:58:20,309 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-12-07 17:58:20,310 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:58:20,735 INFO L225 Difference]: With dead ends: 166396 [2019-12-07 17:58:20,735 INFO L226 Difference]: Without dead ends: 166347 [2019-12-07 17:58:20,735 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:58:25,510 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 166347 states. [2019-12-07 17:58:27,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 166347 to 151934. [2019-12-07 17:58:27,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 151934 states. [2019-12-07 17:58:30,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151934 states to 151934 states and 627001 transitions. [2019-12-07 17:58:30,767 INFO L78 Accepts]: Start accepts. Automaton has 151934 states and 627001 transitions. Word has length 11 [2019-12-07 17:58:30,768 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:58:30,768 INFO L462 AbstractCegarLoop]: Abstraction has 151934 states and 627001 transitions. [2019-12-07 17:58:30,768 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:58:30,768 INFO L276 IsEmpty]: Start isEmpty. Operand 151934 states and 627001 transitions. [2019-12-07 17:58:30,772 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 17:58:30,772 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:58:30,772 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:58:30,772 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:58:30,772 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:58:30,773 INFO L82 PathProgramCache]: Analyzing trace with hash 881606285, now seen corresponding path program 1 times [2019-12-07 17:58:30,773 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:58:30,773 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1039244246] [2019-12-07 17:58:30,773 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:58:30,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:58:30,816 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:58:30,816 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1039244246] [2019-12-07 17:58:30,816 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:58:30,816 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:58:30,816 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1627311354] [2019-12-07 17:58:30,817 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:58:30,817 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:58:30,817 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:58:30,817 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:58:30,817 INFO L87 Difference]: Start difference. First operand 151934 states and 627001 transitions. Second operand 3 states. [2019-12-07 17:58:30,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:58:30,915 INFO L93 Difference]: Finished difference Result 33114 states and 107084 transitions. [2019-12-07 17:58:30,915 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:58:30,916 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 13 [2019-12-07 17:58:30,916 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:58:31,001 INFO L225 Difference]: With dead ends: 33114 [2019-12-07 17:58:31,001 INFO L226 Difference]: Without dead ends: 33114 [2019-12-07 17:58:31,002 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:58:31,166 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33114 states. [2019-12-07 17:58:31,485 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33114 to 33114. [2019-12-07 17:58:31,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33114 states. [2019-12-07 17:58:31,542 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33114 states to 33114 states and 107084 transitions. [2019-12-07 17:58:31,542 INFO L78 Accepts]: Start accepts. Automaton has 33114 states and 107084 transitions. Word has length 13 [2019-12-07 17:58:31,542 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:58:31,543 INFO L462 AbstractCegarLoop]: Abstraction has 33114 states and 107084 transitions. [2019-12-07 17:58:31,543 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:58:31,543 INFO L276 IsEmpty]: Start isEmpty. Operand 33114 states and 107084 transitions. [2019-12-07 17:58:31,545 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2019-12-07 17:58:31,545 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:58:31,545 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:58:31,545 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:58:31,545 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:58:31,545 INFO L82 PathProgramCache]: Analyzing trace with hash 1702625862, now seen corresponding path program 1 times [2019-12-07 17:58:31,545 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:58:31,546 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [73618531] [2019-12-07 17:58:31,546 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:58:31,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:58:31,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:58:31,614 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [73618531] [2019-12-07 17:58:31,615 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:58:31,615 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:58:31,615 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1416418063] [2019-12-07 17:58:31,615 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:58:31,615 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:58:31,616 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:58:31,616 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:58:31,616 INFO L87 Difference]: Start difference. First operand 33114 states and 107084 transitions. Second operand 4 states. [2019-12-07 17:58:31,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:58:31,855 INFO L93 Difference]: Finished difference Result 41561 states and 133908 transitions. [2019-12-07 17:58:31,856 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:58:31,856 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2019-12-07 17:58:31,856 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:58:31,914 INFO L225 Difference]: With dead ends: 41561 [2019-12-07 17:58:31,914 INFO L226 Difference]: Without dead ends: 41561 [2019-12-07 17:58:31,914 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:58:32,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41561 states. [2019-12-07 17:58:32,486 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41561 to 37204. [2019-12-07 17:58:32,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37204 states. [2019-12-07 17:58:32,550 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37204 states to 37204 states and 120245 transitions. [2019-12-07 17:58:32,551 INFO L78 Accepts]: Start accepts. Automaton has 37204 states and 120245 transitions. Word has length 16 [2019-12-07 17:58:32,551 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:58:32,551 INFO L462 AbstractCegarLoop]: Abstraction has 37204 states and 120245 transitions. [2019-12-07 17:58:32,552 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:58:32,552 INFO L276 IsEmpty]: Start isEmpty. Operand 37204 states and 120245 transitions. [2019-12-07 17:58:32,558 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2019-12-07 17:58:32,558 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:58:32,559 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:58:32,559 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:58:32,559 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:58:32,559 INFO L82 PathProgramCache]: Analyzing trace with hash -989401703, now seen corresponding path program 1 times [2019-12-07 17:58:32,559 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:58:32,559 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [37628140] [2019-12-07 17:58:32,559 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:58:32,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:58:32,625 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:58:32,625 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [37628140] [2019-12-07 17:58:32,625 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:58:32,625 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:58:32,626 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1238312143] [2019-12-07 17:58:32,626 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:58:32,626 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:58:32,626 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:58:32,626 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:58:32,627 INFO L87 Difference]: Start difference. First operand 37204 states and 120245 transitions. Second operand 5 states. [2019-12-07 17:58:33,057 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:58:33,057 INFO L93 Difference]: Finished difference Result 47941 states and 152440 transitions. [2019-12-07 17:58:33,057 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 17:58:33,057 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 22 [2019-12-07 17:58:33,058 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:58:33,121 INFO L225 Difference]: With dead ends: 47941 [2019-12-07 17:58:33,122 INFO L226 Difference]: Without dead ends: 47934 [2019-12-07 17:58:33,122 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 17:58:33,319 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47934 states. [2019-12-07 17:58:33,729 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47934 to 36849. [2019-12-07 17:58:33,730 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36849 states. [2019-12-07 17:58:33,793 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36849 states to 36849 states and 118974 transitions. [2019-12-07 17:58:33,793 INFO L78 Accepts]: Start accepts. Automaton has 36849 states and 118974 transitions. Word has length 22 [2019-12-07 17:58:33,793 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:58:33,793 INFO L462 AbstractCegarLoop]: Abstraction has 36849 states and 118974 transitions. [2019-12-07 17:58:33,793 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:58:33,793 INFO L276 IsEmpty]: Start isEmpty. Operand 36849 states and 118974 transitions. [2019-12-07 17:58:33,803 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 17:58:33,804 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:58:33,804 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:58:33,804 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:58:33,804 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:58:33,804 INFO L82 PathProgramCache]: Analyzing trace with hash -2090054503, now seen corresponding path program 1 times [2019-12-07 17:58:33,804 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:58:33,804 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1347062947] [2019-12-07 17:58:33,804 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:58:33,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:58:33,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:58:33,848 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1347062947] [2019-12-07 17:58:33,848 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:58:33,848 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:58:33,848 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1885788877] [2019-12-07 17:58:33,849 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:58:33,849 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:58:33,849 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:58:33,849 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:58:33,849 INFO L87 Difference]: Start difference. First operand 36849 states and 118974 transitions. Second operand 4 states. [2019-12-07 17:58:33,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:58:33,898 INFO L93 Difference]: Finished difference Result 15264 states and 46609 transitions. [2019-12-07 17:58:33,898 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 17:58:33,898 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 25 [2019-12-07 17:58:33,898 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:58:33,915 INFO L225 Difference]: With dead ends: 15264 [2019-12-07 17:58:33,915 INFO L226 Difference]: Without dead ends: 15264 [2019-12-07 17:58:33,916 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:58:33,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15264 states. [2019-12-07 17:58:34,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15264 to 14936. [2019-12-07 17:58:34,104 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14936 states. [2019-12-07 17:58:34,128 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14936 states to 14936 states and 45673 transitions. [2019-12-07 17:58:34,128 INFO L78 Accepts]: Start accepts. Automaton has 14936 states and 45673 transitions. Word has length 25 [2019-12-07 17:58:34,128 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:58:34,128 INFO L462 AbstractCegarLoop]: Abstraction has 14936 states and 45673 transitions. [2019-12-07 17:58:34,128 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:58:34,128 INFO L276 IsEmpty]: Start isEmpty. Operand 14936 states and 45673 transitions. [2019-12-07 17:58:34,138 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 17:58:34,138 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:58:34,138 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:58:34,138 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:58:34,138 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:58:34,138 INFO L82 PathProgramCache]: Analyzing trace with hash 1906532401, now seen corresponding path program 1 times [2019-12-07 17:58:34,138 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:58:34,138 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [421681361] [2019-12-07 17:58:34,139 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:58:34,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:58:34,161 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:58:34,161 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [421681361] [2019-12-07 17:58:34,162 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:58:34,162 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:58:34,162 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1396672370] [2019-12-07 17:58:34,162 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:58:34,162 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:58:34,162 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:58:34,162 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:58:34,162 INFO L87 Difference]: Start difference. First operand 14936 states and 45673 transitions. Second operand 3 states. [2019-12-07 17:58:34,448 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:58:34,448 INFO L93 Difference]: Finished difference Result 21267 states and 63997 transitions. [2019-12-07 17:58:34,449 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:58:34,449 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-12-07 17:58:34,449 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:58:34,472 INFO L225 Difference]: With dead ends: 21267 [2019-12-07 17:58:34,473 INFO L226 Difference]: Without dead ends: 21267 [2019-12-07 17:58:34,473 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:58:34,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21267 states. [2019-12-07 17:58:34,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21267 to 15790. [2019-12-07 17:58:34,705 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15790 states. [2019-12-07 17:58:34,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15790 states to 15790 states and 48131 transitions. [2019-12-07 17:58:34,731 INFO L78 Accepts]: Start accepts. Automaton has 15790 states and 48131 transitions. Word has length 27 [2019-12-07 17:58:34,732 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:58:34,732 INFO L462 AbstractCegarLoop]: Abstraction has 15790 states and 48131 transitions. [2019-12-07 17:58:34,732 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:58:34,732 INFO L276 IsEmpty]: Start isEmpty. Operand 15790 states and 48131 transitions. [2019-12-07 17:58:34,742 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 17:58:34,742 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:58:34,742 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:58:34,742 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:58:34,742 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:58:34,742 INFO L82 PathProgramCache]: Analyzing trace with hash 1466938041, now seen corresponding path program 1 times [2019-12-07 17:58:34,743 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:58:34,743 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [683407828] [2019-12-07 17:58:34,743 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:58:34,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:58:34,806 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:58:34,806 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [683407828] [2019-12-07 17:58:34,806 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:58:34,806 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 17:58:34,807 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1274309214] [2019-12-07 17:58:34,807 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:58:34,807 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:58:34,807 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:58:34,807 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:58:34,807 INFO L87 Difference]: Start difference. First operand 15790 states and 48131 transitions. Second operand 6 states. [2019-12-07 17:58:35,303 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:58:35,303 INFO L93 Difference]: Finished difference Result 40724 states and 122204 transitions. [2019-12-07 17:58:35,303 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 17:58:35,303 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 27 [2019-12-07 17:58:35,303 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:58:35,350 INFO L225 Difference]: With dead ends: 40724 [2019-12-07 17:58:35,350 INFO L226 Difference]: Without dead ends: 40724 [2019-12-07 17:58:35,351 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=39, Invalid=71, Unknown=0, NotChecked=0, Total=110 [2019-12-07 17:58:35,457 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40724 states. [2019-12-07 17:58:35,758 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40724 to 22567. [2019-12-07 17:58:35,758 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22567 states. [2019-12-07 17:58:35,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22567 states to 22567 states and 69647 transitions. [2019-12-07 17:58:35,795 INFO L78 Accepts]: Start accepts. Automaton has 22567 states and 69647 transitions. Word has length 27 [2019-12-07 17:58:35,796 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:58:35,796 INFO L462 AbstractCegarLoop]: Abstraction has 22567 states and 69647 transitions. [2019-12-07 17:58:35,796 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:58:35,796 INFO L276 IsEmpty]: Start isEmpty. Operand 22567 states and 69647 transitions. [2019-12-07 17:58:35,811 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2019-12-07 17:58:35,811 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:58:35,811 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:58:35,811 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:58:35,811 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:58:35,811 INFO L82 PathProgramCache]: Analyzing trace with hash -1177717026, now seen corresponding path program 1 times [2019-12-07 17:58:35,811 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:58:35,812 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [222920529] [2019-12-07 17:58:35,812 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:58:35,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:58:35,889 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:58:35,889 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [222920529] [2019-12-07 17:58:35,889 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:58:35,889 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 17:58:35,890 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1465700353] [2019-12-07 17:58:35,890 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 17:58:35,890 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:58:35,890 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 17:58:35,890 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:58:35,890 INFO L87 Difference]: Start difference. First operand 22567 states and 69647 transitions. Second operand 6 states. [2019-12-07 17:58:36,393 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:58:36,393 INFO L93 Difference]: Finished difference Result 37765 states and 113362 transitions. [2019-12-07 17:58:36,393 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2019-12-07 17:58:36,393 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 28 [2019-12-07 17:58:36,393 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:58:36,435 INFO L225 Difference]: With dead ends: 37765 [2019-12-07 17:58:36,435 INFO L226 Difference]: Without dead ends: 37765 [2019-12-07 17:58:36,435 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=39, Invalid=71, Unknown=0, NotChecked=0, Total=110 [2019-12-07 17:58:36,535 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37765 states. [2019-12-07 17:58:36,825 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37765 to 22218. [2019-12-07 17:58:36,825 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22218 states. [2019-12-07 17:58:36,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22218 states to 22218 states and 68697 transitions. [2019-12-07 17:58:36,863 INFO L78 Accepts]: Start accepts. Automaton has 22218 states and 68697 transitions. Word has length 28 [2019-12-07 17:58:36,864 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:58:36,864 INFO L462 AbstractCegarLoop]: Abstraction has 22218 states and 68697 transitions. [2019-12-07 17:58:36,864 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 17:58:36,864 INFO L276 IsEmpty]: Start isEmpty. Operand 22218 states and 68697 transitions. [2019-12-07 17:58:36,887 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-12-07 17:58:36,888 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:58:36,888 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:58:36,888 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:58:36,888 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:58:36,888 INFO L82 PathProgramCache]: Analyzing trace with hash 1088633804, now seen corresponding path program 1 times [2019-12-07 17:58:36,888 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:58:36,889 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1843162220] [2019-12-07 17:58:36,889 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:58:36,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:58:36,974 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:58:36,975 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1843162220] [2019-12-07 17:58:36,975 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:58:36,975 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:58:36,975 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1790441849] [2019-12-07 17:58:36,975 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 17:58:36,975 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:58:36,975 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 17:58:36,976 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:58:36,976 INFO L87 Difference]: Start difference. First operand 22218 states and 68697 transitions. Second operand 7 states. [2019-12-07 17:58:37,873 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:58:37,873 INFO L93 Difference]: Finished difference Result 50401 states and 150592 transitions. [2019-12-07 17:58:37,873 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2019-12-07 17:58:37,873 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 33 [2019-12-07 17:58:37,874 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:58:37,937 INFO L225 Difference]: With dead ends: 50401 [2019-12-07 17:58:37,938 INFO L226 Difference]: Without dead ends: 50401 [2019-12-07 17:58:37,938 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 82 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=117, Invalid=303, Unknown=0, NotChecked=0, Total=420 [2019-12-07 17:58:38,064 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50401 states. [2019-12-07 17:58:38,405 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50401 to 23449. [2019-12-07 17:58:38,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23449 states. [2019-12-07 17:58:38,442 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23449 states to 23449 states and 72523 transitions. [2019-12-07 17:58:38,442 INFO L78 Accepts]: Start accepts. Automaton has 23449 states and 72523 transitions. Word has length 33 [2019-12-07 17:58:38,442 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:58:38,442 INFO L462 AbstractCegarLoop]: Abstraction has 23449 states and 72523 transitions. [2019-12-07 17:58:38,442 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 17:58:38,442 INFO L276 IsEmpty]: Start isEmpty. Operand 23449 states and 72523 transitions. [2019-12-07 17:58:38,463 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-12-07 17:58:38,463 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:58:38,463 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:58:38,463 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:58:38,463 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:58:38,464 INFO L82 PathProgramCache]: Analyzing trace with hash 1082826604, now seen corresponding path program 1 times [2019-12-07 17:58:38,464 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:58:38,464 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [793144121] [2019-12-07 17:58:38,464 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:58:38,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:58:38,485 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:58:38,485 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [793144121] [2019-12-07 17:58:38,485 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:58:38,485 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:58:38,485 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [872842441] [2019-12-07 17:58:38,485 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:58:38,486 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:58:38,486 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:58:38,486 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:58:38,486 INFO L87 Difference]: Start difference. First operand 23449 states and 72523 transitions. Second operand 3 states. [2019-12-07 17:58:38,573 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:58:38,573 INFO L93 Difference]: Finished difference Result 31046 states and 92713 transitions. [2019-12-07 17:58:38,574 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:58:38,574 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 33 [2019-12-07 17:58:38,574 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:58:38,610 INFO L225 Difference]: With dead ends: 31046 [2019-12-07 17:58:38,610 INFO L226 Difference]: Without dead ends: 31046 [2019-12-07 17:58:38,610 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:58:38,701 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31046 states. [2019-12-07 17:58:38,931 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31046 to 22288. [2019-12-07 17:58:38,932 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22288 states. [2019-12-07 17:58:38,965 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22288 states to 22288 states and 66690 transitions. [2019-12-07 17:58:38,965 INFO L78 Accepts]: Start accepts. Automaton has 22288 states and 66690 transitions. Word has length 33 [2019-12-07 17:58:38,965 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:58:38,965 INFO L462 AbstractCegarLoop]: Abstraction has 22288 states and 66690 transitions. [2019-12-07 17:58:38,965 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:58:38,966 INFO L276 IsEmpty]: Start isEmpty. Operand 22288 states and 66690 transitions. [2019-12-07 17:58:38,980 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2019-12-07 17:58:38,980 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:58:38,980 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:58:38,980 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:58:38,980 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:58:38,980 INFO L82 PathProgramCache]: Analyzing trace with hash 1090977820, now seen corresponding path program 2 times [2019-12-07 17:58:38,981 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:58:38,981 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1433790548] [2019-12-07 17:58:38,981 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:58:38,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:58:39,104 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:58:39,105 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1433790548] [2019-12-07 17:58:39,105 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:58:39,105 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 17:58:39,105 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1045555546] [2019-12-07 17:58:39,105 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 17:58:39,105 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:58:39,105 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 17:58:39,106 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=68, Unknown=0, NotChecked=0, Total=90 [2019-12-07 17:58:39,106 INFO L87 Difference]: Start difference. First operand 22288 states and 66690 transitions. Second operand 10 states. [2019-12-07 17:58:40,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:58:40,833 INFO L93 Difference]: Finished difference Result 51660 states and 150014 transitions. [2019-12-07 17:58:40,834 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2019-12-07 17:58:40,834 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 33 [2019-12-07 17:58:40,834 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:58:40,898 INFO L225 Difference]: With dead ends: 51660 [2019-12-07 17:58:40,899 INFO L226 Difference]: Without dead ends: 51660 [2019-12-07 17:58:40,899 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 220 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=211, Invalid=719, Unknown=0, NotChecked=0, Total=930 [2019-12-07 17:58:41,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51660 states. [2019-12-07 17:58:41,434 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51660 to 21685. [2019-12-07 17:58:41,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21685 states. [2019-12-07 17:58:41,467 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21685 states to 21685 states and 64891 transitions. [2019-12-07 17:58:41,468 INFO L78 Accepts]: Start accepts. Automaton has 21685 states and 64891 transitions. Word has length 33 [2019-12-07 17:58:41,468 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:58:41,468 INFO L462 AbstractCegarLoop]: Abstraction has 21685 states and 64891 transitions. [2019-12-07 17:58:41,468 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 17:58:41,468 INFO L276 IsEmpty]: Start isEmpty. Operand 21685 states and 64891 transitions. [2019-12-07 17:58:41,483 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 17:58:41,483 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:58:41,483 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:58:41,484 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:58:41,484 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:58:41,484 INFO L82 PathProgramCache]: Analyzing trace with hash 791261483, now seen corresponding path program 1 times [2019-12-07 17:58:41,484 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:58:41,484 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1930432025] [2019-12-07 17:58:41,484 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:58:41,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:58:41,551 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:58:41,551 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1930432025] [2019-12-07 17:58:41,551 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:58:41,551 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:58:41,551 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [391781612] [2019-12-07 17:58:41,552 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 17:58:41,552 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:58:41,552 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 17:58:41,552 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:58:41,552 INFO L87 Difference]: Start difference. First operand 21685 states and 64891 transitions. Second operand 7 states. [2019-12-07 17:58:42,370 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:58:42,370 INFO L93 Difference]: Finished difference Result 37994 states and 111619 transitions. [2019-12-07 17:58:42,371 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 17:58:42,371 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 34 [2019-12-07 17:58:42,371 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:58:42,412 INFO L225 Difference]: With dead ends: 37994 [2019-12-07 17:58:42,412 INFO L226 Difference]: Without dead ends: 37994 [2019-12-07 17:58:42,413 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 62 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=89, Invalid=253, Unknown=0, NotChecked=0, Total=342 [2019-12-07 17:58:42,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37994 states. [2019-12-07 17:58:42,782 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37994 to 20324. [2019-12-07 17:58:42,782 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20324 states. [2019-12-07 17:58:42,813 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20324 states to 20324 states and 60908 transitions. [2019-12-07 17:58:42,813 INFO L78 Accepts]: Start accepts. Automaton has 20324 states and 60908 transitions. Word has length 34 [2019-12-07 17:58:42,813 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:58:42,813 INFO L462 AbstractCegarLoop]: Abstraction has 20324 states and 60908 transitions. [2019-12-07 17:58:42,813 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 17:58:42,813 INFO L276 IsEmpty]: Start isEmpty. Operand 20324 states and 60908 transitions. [2019-12-07 17:58:42,827 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 17:58:42,827 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:58:42,828 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:58:42,828 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:58:42,828 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:58:42,828 INFO L82 PathProgramCache]: Analyzing trace with hash -1244987983, now seen corresponding path program 2 times [2019-12-07 17:58:42,828 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:58:42,828 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2038875416] [2019-12-07 17:58:42,828 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:58:42,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:58:42,945 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:58:42,945 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2038875416] [2019-12-07 17:58:42,945 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:58:42,945 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:58:42,945 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1399152329] [2019-12-07 17:58:42,946 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 17:58:42,946 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:58:42,946 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 17:58:42,946 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:58:42,946 INFO L87 Difference]: Start difference. First operand 20324 states and 60908 transitions. Second operand 7 states. [2019-12-07 17:58:43,749 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:58:43,749 INFO L93 Difference]: Finished difference Result 46732 states and 135699 transitions. [2019-12-07 17:58:43,749 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2019-12-07 17:58:43,749 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 34 [2019-12-07 17:58:43,749 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:58:43,798 INFO L225 Difference]: With dead ends: 46732 [2019-12-07 17:58:43,798 INFO L226 Difference]: Without dead ends: 46732 [2019-12-07 17:58:43,798 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 0 SyntacticMatches, 6 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 59 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=81, Invalid=225, Unknown=0, NotChecked=0, Total=306 [2019-12-07 17:58:43,916 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46732 states. [2019-12-07 17:58:44,209 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46732 to 19737. [2019-12-07 17:58:44,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19737 states. [2019-12-07 17:58:44,239 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19737 states to 19737 states and 59173 transitions. [2019-12-07 17:58:44,240 INFO L78 Accepts]: Start accepts. Automaton has 19737 states and 59173 transitions. Word has length 34 [2019-12-07 17:58:44,240 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:58:44,240 INFO L462 AbstractCegarLoop]: Abstraction has 19737 states and 59173 transitions. [2019-12-07 17:58:44,240 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 17:58:44,240 INFO L276 IsEmpty]: Start isEmpty. Operand 19737 states and 59173 transitions. [2019-12-07 17:58:44,254 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2019-12-07 17:58:44,254 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:58:44,254 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:58:44,254 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:58:44,255 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:58:44,255 INFO L82 PathProgramCache]: Analyzing trace with hash -851207469, now seen corresponding path program 3 times [2019-12-07 17:58:44,255 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:58:44,255 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1932293972] [2019-12-07 17:58:44,255 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:58:44,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:58:44,338 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:58:44,338 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1932293972] [2019-12-07 17:58:44,338 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:58:44,338 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 17:58:44,339 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [168572857] [2019-12-07 17:58:44,339 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 17:58:44,339 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:58:44,339 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 17:58:44,339 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2019-12-07 17:58:44,339 INFO L87 Difference]: Start difference. First operand 19737 states and 59173 transitions. Second operand 8 states. [2019-12-07 17:58:45,390 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:58:45,391 INFO L93 Difference]: Finished difference Result 42502 states and 123478 transitions. [2019-12-07 17:58:45,391 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2019-12-07 17:58:45,391 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 34 [2019-12-07 17:58:45,391 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:58:45,437 INFO L225 Difference]: With dead ends: 42502 [2019-12-07 17:58:45,437 INFO L226 Difference]: Without dead ends: 42502 [2019-12-07 17:58:45,437 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 148 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=161, Invalid=489, Unknown=0, NotChecked=0, Total=650 [2019-12-07 17:58:45,548 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42502 states. [2019-12-07 17:58:45,815 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42502 to 18592. [2019-12-07 17:58:45,815 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18592 states. [2019-12-07 17:58:45,844 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18592 states to 18592 states and 55745 transitions. [2019-12-07 17:58:45,844 INFO L78 Accepts]: Start accepts. Automaton has 18592 states and 55745 transitions. Word has length 34 [2019-12-07 17:58:45,844 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:58:45,844 INFO L462 AbstractCegarLoop]: Abstraction has 18592 states and 55745 transitions. [2019-12-07 17:58:45,844 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 17:58:45,845 INFO L276 IsEmpty]: Start isEmpty. Operand 18592 states and 55745 transitions. [2019-12-07 17:58:45,859 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2019-12-07 17:58:45,859 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:58:45,859 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:58:45,859 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:58:45,859 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:58:45,860 INFO L82 PathProgramCache]: Analyzing trace with hash 1420266152, now seen corresponding path program 1 times [2019-12-07 17:58:45,860 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:58:45,860 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [799146203] [2019-12-07 17:58:45,860 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:58:45,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:58:45,905 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:58:45,905 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [799146203] [2019-12-07 17:58:45,906 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:58:45,906 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 17:58:45,906 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1361824434] [2019-12-07 17:58:45,906 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:58:45,906 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:58:45,906 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:58:45,907 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:58:45,907 INFO L87 Difference]: Start difference. First operand 18592 states and 55745 transitions. Second operand 5 states. [2019-12-07 17:58:46,354 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:58:46,354 INFO L93 Difference]: Finished difference Result 26839 states and 79540 transitions. [2019-12-07 17:58:46,355 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-07 17:58:46,355 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 39 [2019-12-07 17:58:46,355 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:58:46,393 INFO L225 Difference]: With dead ends: 26839 [2019-12-07 17:58:46,394 INFO L226 Difference]: Without dead ends: 26839 [2019-12-07 17:58:46,394 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-07 17:58:46,475 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26839 states. [2019-12-07 17:58:46,716 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26839 to 24871. [2019-12-07 17:58:46,716 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24871 states. [2019-12-07 17:58:46,757 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24871 states to 24871 states and 74184 transitions. [2019-12-07 17:58:46,757 INFO L78 Accepts]: Start accepts. Automaton has 24871 states and 74184 transitions. Word has length 39 [2019-12-07 17:58:46,757 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:58:46,757 INFO L462 AbstractCegarLoop]: Abstraction has 24871 states and 74184 transitions. [2019-12-07 17:58:46,757 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:58:46,757 INFO L276 IsEmpty]: Start isEmpty. Operand 24871 states and 74184 transitions. [2019-12-07 17:58:46,777 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2019-12-07 17:58:46,777 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:58:46,778 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:58:46,778 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:58:46,778 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:58:46,778 INFO L82 PathProgramCache]: Analyzing trace with hash 1017444534, now seen corresponding path program 2 times [2019-12-07 17:58:46,778 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:58:46,778 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1821364642] [2019-12-07 17:58:46,778 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:58:46,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:58:46,818 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:58:46,818 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1821364642] [2019-12-07 17:58:46,818 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:58:46,818 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:58:46,818 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [394038575] [2019-12-07 17:58:46,819 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:58:46,819 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:58:46,819 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:58:46,819 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:58:46,819 INFO L87 Difference]: Start difference. First operand 24871 states and 74184 transitions. Second operand 3 states. [2019-12-07 17:58:46,877 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:58:46,877 INFO L93 Difference]: Finished difference Result 23483 states and 69118 transitions. [2019-12-07 17:58:46,877 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:58:46,877 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 39 [2019-12-07 17:58:46,877 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:58:46,900 INFO L225 Difference]: With dead ends: 23483 [2019-12-07 17:58:46,900 INFO L226 Difference]: Without dead ends: 23483 [2019-12-07 17:58:46,900 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:58:46,972 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23483 states. [2019-12-07 17:58:47,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23483 to 23355. [2019-12-07 17:58:47,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23355 states. [2019-12-07 17:58:47,214 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23355 states to 23355 states and 68762 transitions. [2019-12-07 17:58:47,214 INFO L78 Accepts]: Start accepts. Automaton has 23355 states and 68762 transitions. Word has length 39 [2019-12-07 17:58:47,214 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:58:47,214 INFO L462 AbstractCegarLoop]: Abstraction has 23355 states and 68762 transitions. [2019-12-07 17:58:47,214 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:58:47,214 INFO L276 IsEmpty]: Start isEmpty. Operand 23355 states and 68762 transitions. [2019-12-07 17:58:47,234 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2019-12-07 17:58:47,234 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:58:47,234 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:58:47,234 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:58:47,234 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:58:47,234 INFO L82 PathProgramCache]: Analyzing trace with hash 904736365, now seen corresponding path program 1 times [2019-12-07 17:58:47,234 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:58:47,234 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1601465086] [2019-12-07 17:58:47,235 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:58:47,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:58:47,295 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:58:47,295 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1601465086] [2019-12-07 17:58:47,296 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:58:47,296 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:58:47,296 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1345938188] [2019-12-07 17:58:47,296 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:58:47,296 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:58:47,296 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:58:47,297 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:58:47,297 INFO L87 Difference]: Start difference. First operand 23355 states and 68762 transitions. Second operand 3 states. [2019-12-07 17:58:47,360 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:58:47,360 INFO L93 Difference]: Finished difference Result 23355 states and 68684 transitions. [2019-12-07 17:58:47,360 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:58:47,360 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 40 [2019-12-07 17:58:47,360 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:58:47,383 INFO L225 Difference]: With dead ends: 23355 [2019-12-07 17:58:47,383 INFO L226 Difference]: Without dead ends: 23355 [2019-12-07 17:58:47,383 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:58:47,455 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23355 states. [2019-12-07 17:58:47,716 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23355 to 19354. [2019-12-07 17:58:47,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19354 states. [2019-12-07 17:58:47,744 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19354 states to 19354 states and 57560 transitions. [2019-12-07 17:58:47,744 INFO L78 Accepts]: Start accepts. Automaton has 19354 states and 57560 transitions. Word has length 40 [2019-12-07 17:58:47,744 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:58:47,744 INFO L462 AbstractCegarLoop]: Abstraction has 19354 states and 57560 transitions. [2019-12-07 17:58:47,744 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:58:47,744 INFO L276 IsEmpty]: Start isEmpty. Operand 19354 states and 57560 transitions. [2019-12-07 17:58:47,759 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2019-12-07 17:58:47,759 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:58:47,759 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:58:47,759 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:58:47,760 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:58:47,760 INFO L82 PathProgramCache]: Analyzing trace with hash 2120844099, now seen corresponding path program 1 times [2019-12-07 17:58:47,760 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:58:47,760 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1397138608] [2019-12-07 17:58:47,760 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:58:47,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:58:47,808 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:58:47,809 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1397138608] [2019-12-07 17:58:47,809 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:58:47,809 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 17:58:47,809 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1373437892] [2019-12-07 17:58:47,809 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:58:47,809 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:58:47,809 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:58:47,809 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:58:47,809 INFO L87 Difference]: Start difference. First operand 19354 states and 57560 transitions. Second operand 4 states. [2019-12-07 17:58:47,903 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:58:47,903 INFO L93 Difference]: Finished difference Result 36255 states and 107991 transitions. [2019-12-07 17:58:47,903 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 17:58:47,903 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 41 [2019-12-07 17:58:47,904 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:58:47,944 INFO L225 Difference]: With dead ends: 36255 [2019-12-07 17:58:47,944 INFO L226 Difference]: Without dead ends: 32274 [2019-12-07 17:58:47,945 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:58:48,036 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32274 states. [2019-12-07 17:58:48,343 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32274 to 30482. [2019-12-07 17:58:48,343 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30482 states. [2019-12-07 17:58:48,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30482 states to 30482 states and 90164 transitions. [2019-12-07 17:58:48,392 INFO L78 Accepts]: Start accepts. Automaton has 30482 states and 90164 transitions. Word has length 41 [2019-12-07 17:58:48,392 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:58:48,392 INFO L462 AbstractCegarLoop]: Abstraction has 30482 states and 90164 transitions. [2019-12-07 17:58:48,392 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:58:48,392 INFO L276 IsEmpty]: Start isEmpty. Operand 30482 states and 90164 transitions. [2019-12-07 17:58:48,421 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2019-12-07 17:58:48,421 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:58:48,421 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:58:48,421 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:58:48,421 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:58:48,422 INFO L82 PathProgramCache]: Analyzing trace with hash 884175412, now seen corresponding path program 1 times [2019-12-07 17:58:48,422 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:58:48,422 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1338447082] [2019-12-07 17:58:48,422 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:58:48,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:58:48,462 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:58:48,463 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1338447082] [2019-12-07 17:58:48,463 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:58:48,463 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 17:58:48,463 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1574769399] [2019-12-07 17:58:48,463 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 17:58:48,463 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:58:48,463 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 17:58:48,463 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:58:48,464 INFO L87 Difference]: Start difference. First operand 30482 states and 90164 transitions. Second operand 5 states. [2019-12-07 17:58:48,553 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:58:48,553 INFO L93 Difference]: Finished difference Result 28583 states and 86055 transitions. [2019-12-07 17:58:48,553 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 17:58:48,553 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 42 [2019-12-07 17:58:48,554 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:58:48,584 INFO L225 Difference]: With dead ends: 28583 [2019-12-07 17:58:48,584 INFO L226 Difference]: Without dead ends: 27796 [2019-12-07 17:58:48,584 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 17:58:48,667 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27796 states. [2019-12-07 17:58:48,857 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27796 to 17274. [2019-12-07 17:58:48,857 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17274 states. [2019-12-07 17:58:48,883 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17274 states to 17274 states and 52152 transitions. [2019-12-07 17:58:48,883 INFO L78 Accepts]: Start accepts. Automaton has 17274 states and 52152 transitions. Word has length 42 [2019-12-07 17:58:48,883 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:58:48,883 INFO L462 AbstractCegarLoop]: Abstraction has 17274 states and 52152 transitions. [2019-12-07 17:58:48,883 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 17:58:48,883 INFO L276 IsEmpty]: Start isEmpty. Operand 17274 states and 52152 transitions. [2019-12-07 17:58:48,898 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:58:48,898 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:58:48,898 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:58:48,898 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:58:48,898 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:58:48,898 INFO L82 PathProgramCache]: Analyzing trace with hash 168578630, now seen corresponding path program 1 times [2019-12-07 17:58:48,898 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:58:48,899 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [340033357] [2019-12-07 17:58:48,899 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:58:48,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:58:48,970 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:58:48,970 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [340033357] [2019-12-07 17:58:48,970 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:58:48,970 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-07 17:58:48,970 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1372435181] [2019-12-07 17:58:48,970 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 17:58:48,970 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:58:48,970 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 17:58:48,971 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:58:48,971 INFO L87 Difference]: Start difference. First operand 17274 states and 52152 transitions. Second operand 7 states. [2019-12-07 17:58:49,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:58:49,799 INFO L93 Difference]: Finished difference Result 33039 states and 98969 transitions. [2019-12-07 17:58:49,799 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2019-12-07 17:58:49,799 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 66 [2019-12-07 17:58:49,799 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:58:49,835 INFO L225 Difference]: With dead ends: 33039 [2019-12-07 17:58:49,835 INFO L226 Difference]: Without dead ends: 33039 [2019-12-07 17:58:49,835 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 7 SyntacticMatches, 2 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 46 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=81, Invalid=225, Unknown=0, NotChecked=0, Total=306 [2019-12-07 17:58:49,929 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33039 states. [2019-12-07 17:58:50,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33039 to 17924. [2019-12-07 17:58:50,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17924 states. [2019-12-07 17:58:50,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17924 states to 17924 states and 54197 transitions. [2019-12-07 17:58:50,204 INFO L78 Accepts]: Start accepts. Automaton has 17924 states and 54197 transitions. Word has length 66 [2019-12-07 17:58:50,204 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:58:50,204 INFO L462 AbstractCegarLoop]: Abstraction has 17924 states and 54197 transitions. [2019-12-07 17:58:50,204 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 17:58:50,204 INFO L276 IsEmpty]: Start isEmpty. Operand 17924 states and 54197 transitions. [2019-12-07 17:58:50,219 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:58:50,219 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:58:50,219 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:58:50,220 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:58:50,220 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:58:50,220 INFO L82 PathProgramCache]: Analyzing trace with hash 712249250, now seen corresponding path program 2 times [2019-12-07 17:58:50,220 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:58:50,220 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [925322640] [2019-12-07 17:58:50,220 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:58:50,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:58:50,290 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:58:50,290 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [925322640] [2019-12-07 17:58:50,290 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:58:50,290 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 17:58:50,291 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1380025954] [2019-12-07 17:58:50,291 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 17:58:50,291 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:58:50,291 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 17:58:50,291 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2019-12-07 17:58:50,291 INFO L87 Difference]: Start difference. First operand 17924 states and 54197 transitions. Second operand 8 states. [2019-12-07 17:58:51,899 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:58:51,900 INFO L93 Difference]: Finished difference Result 37927 states and 113305 transitions. [2019-12-07 17:58:51,900 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2019-12-07 17:58:51,900 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 66 [2019-12-07 17:58:51,900 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:58:51,941 INFO L225 Difference]: With dead ends: 37927 [2019-12-07 17:58:51,941 INFO L226 Difference]: Without dead ends: 37927 [2019-12-07 17:58:51,941 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 12 SyntacticMatches, 2 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 334 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=255, Invalid=1005, Unknown=0, NotChecked=0, Total=1260 [2019-12-07 17:58:52,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37927 states. [2019-12-07 17:58:52,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37927 to 18383. [2019-12-07 17:58:52,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18383 states. [2019-12-07 17:58:52,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18383 states to 18383 states and 55577 transitions. [2019-12-07 17:58:52,348 INFO L78 Accepts]: Start accepts. Automaton has 18383 states and 55577 transitions. Word has length 66 [2019-12-07 17:58:52,348 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:58:52,348 INFO L462 AbstractCegarLoop]: Abstraction has 18383 states and 55577 transitions. [2019-12-07 17:58:52,348 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 17:58:52,348 INFO L276 IsEmpty]: Start isEmpty. Operand 18383 states and 55577 transitions. [2019-12-07 17:58:52,364 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:58:52,364 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:58:52,364 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:58:52,364 INFO L410 AbstractCegarLoop]: === Iteration 23 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:58:52,364 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:58:52,364 INFO L82 PathProgramCache]: Analyzing trace with hash 257156348, now seen corresponding path program 3 times [2019-12-07 17:58:52,364 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:58:52,365 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [277999752] [2019-12-07 17:58:52,365 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:58:52,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:58:52,453 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:58:52,453 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [277999752] [2019-12-07 17:58:52,453 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:58:52,454 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-07 17:58:52,454 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [831771855] [2019-12-07 17:58:52,454 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-12-07 17:58:52,454 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:58:52,454 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-07 17:58:52,454 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2019-12-07 17:58:52,454 INFO L87 Difference]: Start difference. First operand 18383 states and 55577 transitions. Second operand 9 states. [2019-12-07 17:58:54,566 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:58:54,566 INFO L93 Difference]: Finished difference Result 42490 states and 126403 transitions. [2019-12-07 17:58:54,566 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2019-12-07 17:58:54,566 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 66 [2019-12-07 17:58:54,566 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:58:54,612 INFO L225 Difference]: With dead ends: 42490 [2019-12-07 17:58:54,613 INFO L226 Difference]: Without dead ends: 42490 [2019-12-07 17:58:54,614 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 67 GetRequests, 15 SyntacticMatches, 3 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 832 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=481, Invalid=2069, Unknown=0, NotChecked=0, Total=2550 [2019-12-07 17:58:54,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42490 states. [2019-12-07 17:58:55,028 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42490 to 18108. [2019-12-07 17:58:55,028 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18108 states. [2019-12-07 17:58:55,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18108 states to 18108 states and 54746 transitions. [2019-12-07 17:58:55,172 INFO L78 Accepts]: Start accepts. Automaton has 18108 states and 54746 transitions. Word has length 66 [2019-12-07 17:58:55,172 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:58:55,172 INFO L462 AbstractCegarLoop]: Abstraction has 18108 states and 54746 transitions. [2019-12-07 17:58:55,172 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-12-07 17:58:55,173 INFO L276 IsEmpty]: Start isEmpty. Operand 18108 states and 54746 transitions. [2019-12-07 17:58:55,186 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:58:55,186 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:58:55,186 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:58:55,187 INFO L410 AbstractCegarLoop]: === Iteration 24 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:58:55,187 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:58:55,187 INFO L82 PathProgramCache]: Analyzing trace with hash 1254491896, now seen corresponding path program 4 times [2019-12-07 17:58:55,187 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:58:55,187 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1810936471] [2019-12-07 17:58:55,187 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:58:55,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:58:55,278 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:58:55,278 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1810936471] [2019-12-07 17:58:55,278 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:58:55,278 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 17:58:55,278 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1507595959] [2019-12-07 17:58:55,278 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 17:58:55,278 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:58:55,279 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 17:58:55,279 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2019-12-07 17:58:55,279 INFO L87 Difference]: Start difference. First operand 18108 states and 54746 transitions. Second operand 7 states. [2019-12-07 17:58:55,715 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:58:55,715 INFO L93 Difference]: Finished difference Result 72769 states and 217726 transitions. [2019-12-07 17:58:55,716 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 17:58:55,716 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 66 [2019-12-07 17:58:55,716 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:58:55,781 INFO L225 Difference]: With dead ends: 72769 [2019-12-07 17:58:55,781 INFO L226 Difference]: Without dead ends: 52414 [2019-12-07 17:58:55,781 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 50 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=78, Invalid=228, Unknown=0, NotChecked=0, Total=306 [2019-12-07 17:58:55,913 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52414 states. [2019-12-07 17:58:56,238 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52414 to 21293. [2019-12-07 17:58:56,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21293 states. [2019-12-07 17:58:56,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21293 states to 21293 states and 63710 transitions. [2019-12-07 17:58:56,270 INFO L78 Accepts]: Start accepts. Automaton has 21293 states and 63710 transitions. Word has length 66 [2019-12-07 17:58:56,270 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:58:56,271 INFO L462 AbstractCegarLoop]: Abstraction has 21293 states and 63710 transitions. [2019-12-07 17:58:56,271 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 17:58:56,271 INFO L276 IsEmpty]: Start isEmpty. Operand 21293 states and 63710 transitions. [2019-12-07 17:58:56,289 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 17:58:56,289 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:58:56,289 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:58:56,289 INFO L410 AbstractCegarLoop]: === Iteration 25 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:58:56,289 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:58:56,289 INFO L82 PathProgramCache]: Analyzing trace with hash 508796180, now seen corresponding path program 5 times [2019-12-07 17:58:56,290 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:58:56,290 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1687824030] [2019-12-07 17:58:56,290 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:58:56,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:58:56,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:58:56,348 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1687824030] [2019-12-07 17:58:56,348 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:58:56,348 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:58:56,348 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2009401594] [2019-12-07 17:58:56,348 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:58:56,348 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:58:56,349 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:58:56,349 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:58:56,349 INFO L87 Difference]: Start difference. First operand 21293 states and 63710 transitions. Second operand 4 states. [2019-12-07 17:58:56,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:58:56,440 INFO L93 Difference]: Finished difference Result 23564 states and 70640 transitions. [2019-12-07 17:58:56,440 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:58:56,441 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 66 [2019-12-07 17:58:56,441 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:58:56,464 INFO L225 Difference]: With dead ends: 23564 [2019-12-07 17:58:56,464 INFO L226 Difference]: Without dead ends: 23564 [2019-12-07 17:58:56,464 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:58:56,536 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23564 states. [2019-12-07 17:58:56,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23564 to 19950. [2019-12-07 17:58:56,739 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19950 states. [2019-12-07 17:58:56,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19950 states to 19950 states and 59949 transitions. [2019-12-07 17:58:56,769 INFO L78 Accepts]: Start accepts. Automaton has 19950 states and 59949 transitions. Word has length 66 [2019-12-07 17:58:56,769 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:58:56,770 INFO L462 AbstractCegarLoop]: Abstraction has 19950 states and 59949 transitions. [2019-12-07 17:58:56,770 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:58:56,770 INFO L276 IsEmpty]: Start isEmpty. Operand 19950 states and 59949 transitions. [2019-12-07 17:58:56,786 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:58:56,787 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:58:56,787 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:58:56,787 INFO L410 AbstractCegarLoop]: === Iteration 26 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:58:56,787 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:58:56,787 INFO L82 PathProgramCache]: Analyzing trace with hash -2089790483, now seen corresponding path program 1 times [2019-12-07 17:58:56,787 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:58:56,787 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1726522898] [2019-12-07 17:58:56,787 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:58:56,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:58:56,839 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:58:56,839 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1726522898] [2019-12-07 17:58:56,839 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:58:56,840 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:58:56,840 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [249376606] [2019-12-07 17:58:56,840 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 17:58:56,840 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:58:56,840 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 17:58:56,840 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:58:56,840 INFO L87 Difference]: Start difference. First operand 19950 states and 59949 transitions. Second operand 4 states. [2019-12-07 17:58:56,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:58:56,956 INFO L93 Difference]: Finished difference Result 49975 states and 150293 transitions. [2019-12-07 17:58:56,956 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 17:58:56,956 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 67 [2019-12-07 17:58:56,957 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:58:56,990 INFO L225 Difference]: With dead ends: 49975 [2019-12-07 17:58:56,990 INFO L226 Difference]: Without dead ends: 30582 [2019-12-07 17:58:56,990 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 17:58:57,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30582 states. [2019-12-07 17:58:57,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30582 to 18802. [2019-12-07 17:58:57,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18802 states. [2019-12-07 17:58:57,308 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18802 states to 18802 states and 56427 transitions. [2019-12-07 17:58:57,309 INFO L78 Accepts]: Start accepts. Automaton has 18802 states and 56427 transitions. Word has length 67 [2019-12-07 17:58:57,309 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:58:57,309 INFO L462 AbstractCegarLoop]: Abstraction has 18802 states and 56427 transitions. [2019-12-07 17:58:57,309 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 17:58:57,309 INFO L276 IsEmpty]: Start isEmpty. Operand 18802 states and 56427 transitions. [2019-12-07 17:58:57,325 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:58:57,325 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:58:57,326 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:58:57,326 INFO L410 AbstractCegarLoop]: === Iteration 27 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:58:57,326 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:58:57,326 INFO L82 PathProgramCache]: Analyzing trace with hash -2050480149, now seen corresponding path program 2 times [2019-12-07 17:58:57,326 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:58:57,326 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1555274814] [2019-12-07 17:58:57,326 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:58:57,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:58:57,775 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:58:57,775 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1555274814] [2019-12-07 17:58:57,775 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:58:57,775 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [16] imperfect sequences [] total 16 [2019-12-07 17:58:57,775 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [856911011] [2019-12-07 17:58:57,776 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-12-07 17:58:57,776 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:58:57,776 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-12-07 17:58:57,776 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=249, Unknown=0, NotChecked=0, Total=306 [2019-12-07 17:58:57,776 INFO L87 Difference]: Start difference. First operand 18802 states and 56427 transitions. Second operand 18 states. [2019-12-07 17:59:00,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:59:00,207 INFO L93 Difference]: Finished difference Result 35387 states and 104911 transitions. [2019-12-07 17:59:00,207 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2019-12-07 17:59:00,208 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 67 [2019-12-07 17:59:00,208 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:59:00,238 INFO L225 Difference]: With dead ends: 35387 [2019-12-07 17:59:00,238 INFO L226 Difference]: Without dead ends: 27621 [2019-12-07 17:59:00,239 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 752 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=421, Invalid=2231, Unknown=0, NotChecked=0, Total=2652 [2019-12-07 17:59:00,319 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27621 states. [2019-12-07 17:59:00,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27621 to 19747. [2019-12-07 17:59:00,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19747 states. [2019-12-07 17:59:00,559 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19747 states to 19747 states and 58672 transitions. [2019-12-07 17:59:00,559 INFO L78 Accepts]: Start accepts. Automaton has 19747 states and 58672 transitions. Word has length 67 [2019-12-07 17:59:00,560 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:59:00,560 INFO L462 AbstractCegarLoop]: Abstraction has 19747 states and 58672 transitions. [2019-12-07 17:59:00,560 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-12-07 17:59:00,560 INFO L276 IsEmpty]: Start isEmpty. Operand 19747 states and 58672 transitions. [2019-12-07 17:59:00,577 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:59:00,577 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:59:00,577 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:59:00,578 INFO L410 AbstractCegarLoop]: === Iteration 28 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:59:00,578 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:59:00,578 INFO L82 PathProgramCache]: Analyzing trace with hash 1111193301, now seen corresponding path program 3 times [2019-12-07 17:59:00,578 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:59:00,578 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [250380334] [2019-12-07 17:59:00,578 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:59:00,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:59:01,008 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:59:01,009 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [250380334] [2019-12-07 17:59:01,009 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:59:01,009 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2019-12-07 17:59:01,009 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [758923158] [2019-12-07 17:59:01,009 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2019-12-07 17:59:01,009 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:59:01,009 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2019-12-07 17:59:01,009 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=227, Unknown=0, NotChecked=0, Total=272 [2019-12-07 17:59:01,010 INFO L87 Difference]: Start difference. First operand 19747 states and 58672 transitions. Second operand 17 states. [2019-12-07 17:59:02,634 WARN L192 SmtUtils]: Spent 130.00 ms on a formula simplification. DAG size of input: 33 DAG size of output: 32 [2019-12-07 17:59:05,888 WARN L192 SmtUtils]: Spent 120.00 ms on a formula simplification. DAG size of input: 22 DAG size of output: 21 [2019-12-07 17:59:13,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:59:13,364 INFO L93 Difference]: Finished difference Result 42823 states and 126013 transitions. [2019-12-07 17:59:13,366 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 73 states. [2019-12-07 17:59:13,366 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 67 [2019-12-07 17:59:13,367 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:59:13,429 INFO L225 Difference]: With dead ends: 42823 [2019-12-07 17:59:13,429 INFO L226 Difference]: Without dead ends: 39044 [2019-12-07 17:59:13,431 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 75 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1631 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=747, Invalid=4655, Unknown=0, NotChecked=0, Total=5402 [2019-12-07 17:59:13,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39044 states. [2019-12-07 17:59:13,797 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39044 to 19951. [2019-12-07 17:59:13,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19951 states. [2019-12-07 17:59:13,828 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19951 states to 19951 states and 59190 transitions. [2019-12-07 17:59:13,828 INFO L78 Accepts]: Start accepts. Automaton has 19951 states and 59190 transitions. Word has length 67 [2019-12-07 17:59:13,828 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:59:13,828 INFO L462 AbstractCegarLoop]: Abstraction has 19951 states and 59190 transitions. [2019-12-07 17:59:13,828 INFO L463 AbstractCegarLoop]: Interpolant automaton has 17 states. [2019-12-07 17:59:13,828 INFO L276 IsEmpty]: Start isEmpty. Operand 19951 states and 59190 transitions. [2019-12-07 17:59:13,845 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:59:13,845 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:59:13,845 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:59:13,846 INFO L410 AbstractCegarLoop]: === Iteration 29 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:59:13,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:59:13,846 INFO L82 PathProgramCache]: Analyzing trace with hash -2057057855, now seen corresponding path program 4 times [2019-12-07 17:59:13,846 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:59:13,846 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1124686721] [2019-12-07 17:59:13,846 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:59:13,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:59:14,342 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:59:14,343 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1124686721] [2019-12-07 17:59:14,343 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:59:14,343 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2019-12-07 17:59:14,343 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1821783405] [2019-12-07 17:59:14,343 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2019-12-07 17:59:14,343 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:59:14,343 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2019-12-07 17:59:14,343 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=287, Unknown=0, NotChecked=0, Total=342 [2019-12-07 17:59:14,344 INFO L87 Difference]: Start difference. First operand 19951 states and 59190 transitions. Second operand 19 states. [2019-12-07 17:59:20,352 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:59:20,352 INFO L93 Difference]: Finished difference Result 43027 states and 126468 transitions. [2019-12-07 17:59:20,353 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2019-12-07 17:59:20,353 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 67 [2019-12-07 17:59:20,353 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:59:20,398 INFO L225 Difference]: With dead ends: 43027 [2019-12-07 17:59:20,398 INFO L226 Difference]: Without dead ends: 38742 [2019-12-07 17:59:20,401 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 83 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 82 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2124 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=910, Invalid=6062, Unknown=0, NotChecked=0, Total=6972 [2019-12-07 17:59:20,506 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38742 states. [2019-12-07 17:59:20,763 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38742 to 19855. [2019-12-07 17:59:20,763 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19855 states. [2019-12-07 17:59:20,794 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19855 states to 19855 states and 58918 transitions. [2019-12-07 17:59:20,794 INFO L78 Accepts]: Start accepts. Automaton has 19855 states and 58918 transitions. Word has length 67 [2019-12-07 17:59:20,794 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:59:20,794 INFO L462 AbstractCegarLoop]: Abstraction has 19855 states and 58918 transitions. [2019-12-07 17:59:20,794 INFO L463 AbstractCegarLoop]: Interpolant automaton has 19 states. [2019-12-07 17:59:20,794 INFO L276 IsEmpty]: Start isEmpty. Operand 19855 states and 58918 transitions. [2019-12-07 17:59:20,811 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:59:20,811 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:59:20,811 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:59:20,811 INFO L410 AbstractCegarLoop]: === Iteration 30 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:59:20,811 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:59:20,812 INFO L82 PathProgramCache]: Analyzing trace with hash -697251353, now seen corresponding path program 5 times [2019-12-07 17:59:20,812 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:59:20,812 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1257153806] [2019-12-07 17:59:20,812 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:59:20,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:59:21,319 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:59:21,320 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1257153806] [2019-12-07 17:59:21,320 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:59:21,320 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2019-12-07 17:59:21,320 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1727962041] [2019-12-07 17:59:21,320 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2019-12-07 17:59:21,320 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:59:21,320 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2019-12-07 17:59:21,320 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=58, Invalid=284, Unknown=0, NotChecked=0, Total=342 [2019-12-07 17:59:21,320 INFO L87 Difference]: Start difference. First operand 19855 states and 58918 transitions. Second operand 19 states. [2019-12-07 17:59:24,710 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:59:24,710 INFO L93 Difference]: Finished difference Result 30442 states and 89320 transitions. [2019-12-07 17:59:24,710 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2019-12-07 17:59:24,711 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 67 [2019-12-07 17:59:24,711 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:59:24,826 INFO L225 Difference]: With dead ends: 30442 [2019-12-07 17:59:24,826 INFO L226 Difference]: Without dead ends: 27919 [2019-12-07 17:59:24,827 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 590 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=395, Invalid=1861, Unknown=0, NotChecked=0, Total=2256 [2019-12-07 17:59:24,902 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27919 states. [2019-12-07 17:59:25,097 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27919 to 19951. [2019-12-07 17:59:25,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19951 states. [2019-12-07 17:59:25,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19951 states to 19951 states and 59164 transitions. [2019-12-07 17:59:25,127 INFO L78 Accepts]: Start accepts. Automaton has 19951 states and 59164 transitions. Word has length 67 [2019-12-07 17:59:25,128 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:59:25,128 INFO L462 AbstractCegarLoop]: Abstraction has 19951 states and 59164 transitions. [2019-12-07 17:59:25,128 INFO L463 AbstractCegarLoop]: Interpolant automaton has 19 states. [2019-12-07 17:59:25,128 INFO L276 IsEmpty]: Start isEmpty. Operand 19951 states and 59164 transitions. [2019-12-07 17:59:25,145 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:59:25,145 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:59:25,145 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:59:25,146 INFO L410 AbstractCegarLoop]: === Iteration 31 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:59:25,146 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:59:25,146 INFO L82 PathProgramCache]: Analyzing trace with hash -1676819099, now seen corresponding path program 6 times [2019-12-07 17:59:25,146 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:59:25,146 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2112850280] [2019-12-07 17:59:25,146 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:59:25,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:59:25,602 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:59:25,603 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2112850280] [2019-12-07 17:59:25,603 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:59:25,603 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [16] imperfect sequences [] total 16 [2019-12-07 17:59:25,603 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [571674945] [2019-12-07 17:59:25,603 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-12-07 17:59:25,603 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:59:25,603 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-12-07 17:59:25,604 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=253, Unknown=0, NotChecked=0, Total=306 [2019-12-07 17:59:25,604 INFO L87 Difference]: Start difference. First operand 19951 states and 59164 transitions. Second operand 18 states. [2019-12-07 17:59:27,951 WARN L192 SmtUtils]: Spent 104.00 ms on a formula simplification. DAG size of input: 25 DAG size of output: 20 [2019-12-07 17:59:31,970 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:59:31,970 INFO L93 Difference]: Finished difference Result 28440 states and 84133 transitions. [2019-12-07 17:59:31,971 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2019-12-07 17:59:31,972 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 67 [2019-12-07 17:59:31,972 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:59:32,021 INFO L225 Difference]: With dead ends: 28440 [2019-12-07 17:59:32,021 INFO L226 Difference]: Without dead ends: 26085 [2019-12-07 17:59:32,022 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 267 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=279, Invalid=1361, Unknown=0, NotChecked=0, Total=1640 [2019-12-07 17:59:32,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26085 states. [2019-12-07 17:59:32,310 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26085 to 19771. [2019-12-07 17:59:32,310 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19771 states. [2019-12-07 17:59:32,342 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19771 states to 19771 states and 58706 transitions. [2019-12-07 17:59:32,342 INFO L78 Accepts]: Start accepts. Automaton has 19771 states and 58706 transitions. Word has length 67 [2019-12-07 17:59:32,342 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:59:32,342 INFO L462 AbstractCegarLoop]: Abstraction has 19771 states and 58706 transitions. [2019-12-07 17:59:32,342 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-12-07 17:59:32,342 INFO L276 IsEmpty]: Start isEmpty. Operand 19771 states and 58706 transitions. [2019-12-07 17:59:32,360 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:59:32,360 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:59:32,360 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:59:32,360 INFO L410 AbstractCegarLoop]: === Iteration 32 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:59:32,360 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:59:32,360 INFO L82 PathProgramCache]: Analyzing trace with hash -1347841601, now seen corresponding path program 7 times [2019-12-07 17:59:32,361 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:59:32,361 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1211070965] [2019-12-07 17:59:32,361 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:59:32,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:59:32,800 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:59:32,800 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1211070965] [2019-12-07 17:59:32,800 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:59:32,800 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [18] imperfect sequences [] total 18 [2019-12-07 17:59:32,800 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [765718960] [2019-12-07 17:59:32,800 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2019-12-07 17:59:32,800 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:59:32,800 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2019-12-07 17:59:32,801 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=312, Unknown=0, NotChecked=0, Total=380 [2019-12-07 17:59:32,801 INFO L87 Difference]: Start difference. First operand 19771 states and 58706 transitions. Second operand 20 states. [2019-12-07 17:59:34,363 WARN L192 SmtUtils]: Spent 117.00 ms on a formula simplification. DAG size of input: 26 DAG size of output: 23 [2019-12-07 17:59:35,092 WARN L192 SmtUtils]: Spent 156.00 ms on a formula simplification. DAG size of input: 28 DAG size of output: 25 [2019-12-07 17:59:35,905 WARN L192 SmtUtils]: Spent 103.00 ms on a formula simplification. DAG size of input: 23 DAG size of output: 19 [2019-12-07 17:59:40,796 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:59:40,796 INFO L93 Difference]: Finished difference Result 27157 states and 80159 transitions. [2019-12-07 17:59:40,796 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2019-12-07 17:59:40,796 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 67 [2019-12-07 17:59:40,796 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:59:40,824 INFO L225 Difference]: With dead ends: 27157 [2019-12-07 17:59:40,825 INFO L226 Difference]: Without dead ends: 25142 [2019-12-07 17:59:40,826 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 914 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=600, Invalid=3432, Unknown=0, NotChecked=0, Total=4032 [2019-12-07 17:59:40,903 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25142 states. [2019-12-07 17:59:41,100 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25142 to 19751. [2019-12-07 17:59:41,100 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19751 states. [2019-12-07 17:59:41,131 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19751 states to 19751 states and 58632 transitions. [2019-12-07 17:59:41,131 INFO L78 Accepts]: Start accepts. Automaton has 19751 states and 58632 transitions. Word has length 67 [2019-12-07 17:59:41,132 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:59:41,132 INFO L462 AbstractCegarLoop]: Abstraction has 19751 states and 58632 transitions. [2019-12-07 17:59:41,132 INFO L463 AbstractCegarLoop]: Interpolant automaton has 20 states. [2019-12-07 17:59:41,132 INFO L276 IsEmpty]: Start isEmpty. Operand 19751 states and 58632 transitions. [2019-12-07 17:59:41,149 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:59:41,149 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:59:41,150 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:59:41,150 INFO L410 AbstractCegarLoop]: === Iteration 33 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:59:41,150 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:59:41,150 INFO L82 PathProgramCache]: Analyzing trace with hash 1759012269, now seen corresponding path program 1 times [2019-12-07 17:59:41,150 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:59:41,150 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [964022545] [2019-12-07 17:59:41,150 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:59:41,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:59:41,175 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:59:41,175 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [964022545] [2019-12-07 17:59:41,175 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:59:41,175 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 17:59:41,175 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1265448432] [2019-12-07 17:59:41,175 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 17:59:41,175 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:59:41,176 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 17:59:41,176 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:59:41,176 INFO L87 Difference]: Start difference. First operand 19751 states and 58632 transitions. Second operand 3 states. [2019-12-07 17:59:41,306 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:59:41,307 INFO L93 Difference]: Finished difference Result 27261 states and 81277 transitions. [2019-12-07 17:59:41,307 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 17:59:41,307 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 67 [2019-12-07 17:59:41,307 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:59:41,339 INFO L225 Difference]: With dead ends: 27261 [2019-12-07 17:59:41,339 INFO L226 Difference]: Without dead ends: 27261 [2019-12-07 17:59:41,339 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 17:59:41,420 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27261 states. [2019-12-07 17:59:41,635 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27261 to 20092. [2019-12-07 17:59:41,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20092 states. [2019-12-07 17:59:41,668 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20092 states to 20092 states and 59712 transitions. [2019-12-07 17:59:41,668 INFO L78 Accepts]: Start accepts. Automaton has 20092 states and 59712 transitions. Word has length 67 [2019-12-07 17:59:41,668 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:59:41,668 INFO L462 AbstractCegarLoop]: Abstraction has 20092 states and 59712 transitions. [2019-12-07 17:59:41,668 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 17:59:41,668 INFO L276 IsEmpty]: Start isEmpty. Operand 20092 states and 59712 transitions. [2019-12-07 17:59:41,687 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:59:41,687 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:59:41,687 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:59:41,687 INFO L410 AbstractCegarLoop]: === Iteration 34 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:59:41,687 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:59:41,687 INFO L82 PathProgramCache]: Analyzing trace with hash -1524318628, now seen corresponding path program 1 times [2019-12-07 17:59:41,687 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:59:41,688 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1951917141] [2019-12-07 17:59:41,688 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:59:41,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:59:41,751 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:59:41,751 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1951917141] [2019-12-07 17:59:41,751 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:59:41,751 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 17:59:41,751 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [484899951] [2019-12-07 17:59:41,752 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-07 17:59:41,752 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:59:41,752 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-07 17:59:41,752 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2019-12-07 17:59:41,752 INFO L87 Difference]: Start difference. First operand 20092 states and 59712 transitions. Second operand 8 states. [2019-12-07 17:59:43,567 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:59:43,568 INFO L93 Difference]: Finished difference Result 35790 states and 104653 transitions. [2019-12-07 17:59:43,568 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2019-12-07 17:59:43,568 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 67 [2019-12-07 17:59:43,568 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:59:43,603 INFO L225 Difference]: With dead ends: 35790 [2019-12-07 17:59:43,604 INFO L226 Difference]: Without dead ends: 35790 [2019-12-07 17:59:43,604 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 11 SyntacticMatches, 2 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 286 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=244, Invalid=946, Unknown=0, NotChecked=0, Total=1190 [2019-12-07 17:59:43,698 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35790 states. [2019-12-07 17:59:43,948 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35790 to 19431. [2019-12-07 17:59:43,948 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19431 states. [2019-12-07 17:59:43,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19431 states to 19431 states and 57995 transitions. [2019-12-07 17:59:43,979 INFO L78 Accepts]: Start accepts. Automaton has 19431 states and 57995 transitions. Word has length 67 [2019-12-07 17:59:43,979 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:59:43,979 INFO L462 AbstractCegarLoop]: Abstraction has 19431 states and 57995 transitions. [2019-12-07 17:59:43,980 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-07 17:59:43,980 INFO L276 IsEmpty]: Start isEmpty. Operand 19431 states and 57995 transitions. [2019-12-07 17:59:43,997 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:59:43,997 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:59:43,997 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:59:43,997 INFO L410 AbstractCegarLoop]: === Iteration 35 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:59:43,997 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:59:43,997 INFO L82 PathProgramCache]: Analyzing trace with hash 1246799597, now seen corresponding path program 8 times [2019-12-07 17:59:43,998 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:59:43,998 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [827003304] [2019-12-07 17:59:43,998 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:59:44,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:59:44,428 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:59:44,428 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [827003304] [2019-12-07 17:59:44,428 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:59:44,429 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [16] imperfect sequences [] total 16 [2019-12-07 17:59:44,429 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [268357448] [2019-12-07 17:59:44,429 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-12-07 17:59:44,429 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:59:44,429 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-12-07 17:59:44,429 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=261, Unknown=0, NotChecked=0, Total=306 [2019-12-07 17:59:44,429 INFO L87 Difference]: Start difference. First operand 19431 states and 57995 transitions. Second operand 18 states. [2019-12-07 17:59:47,095 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:59:47,095 INFO L93 Difference]: Finished difference Result 28473 states and 84254 transitions. [2019-12-07 17:59:47,095 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2019-12-07 17:59:47,095 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 67 [2019-12-07 17:59:47,095 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:59:47,124 INFO L225 Difference]: With dead ends: 28473 [2019-12-07 17:59:47,124 INFO L226 Difference]: Without dead ends: 25789 [2019-12-07 17:59:47,124 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 225 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=222, Invalid=1260, Unknown=0, NotChecked=0, Total=1482 [2019-12-07 17:59:47,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25789 states. [2019-12-07 17:59:47,405 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25789 to 19565. [2019-12-07 17:59:47,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19565 states. [2019-12-07 17:59:47,435 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19565 states to 19565 states and 58365 transitions. [2019-12-07 17:59:47,436 INFO L78 Accepts]: Start accepts. Automaton has 19565 states and 58365 transitions. Word has length 67 [2019-12-07 17:59:47,436 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:59:47,436 INFO L462 AbstractCegarLoop]: Abstraction has 19565 states and 58365 transitions. [2019-12-07 17:59:47,436 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-12-07 17:59:47,436 INFO L276 IsEmpty]: Start isEmpty. Operand 19565 states and 58365 transitions. [2019-12-07 17:59:47,453 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:59:47,453 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:59:47,454 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:59:47,454 INFO L410 AbstractCegarLoop]: === Iteration 36 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:59:47,454 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:59:47,454 INFO L82 PathProgramCache]: Analyzing trace with hash 150175589, now seen corresponding path program 9 times [2019-12-07 17:59:47,454 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:59:47,454 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [65560815] [2019-12-07 17:59:47,454 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:59:47,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:59:47,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:59:47,628 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [65560815] [2019-12-07 17:59:47,628 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:59:47,629 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 17:59:47,629 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1309648775] [2019-12-07 17:59:47,629 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 17:59:47,629 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:59:47,629 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 17:59:47,629 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=128, Unknown=0, NotChecked=0, Total=156 [2019-12-07 17:59:47,629 INFO L87 Difference]: Start difference. First operand 19565 states and 58365 transitions. Second operand 13 states. [2019-12-07 17:59:48,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:59:48,762 INFO L93 Difference]: Finished difference Result 31880 states and 94081 transitions. [2019-12-07 17:59:48,762 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2019-12-07 17:59:48,762 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 67 [2019-12-07 17:59:48,763 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:59:48,791 INFO L225 Difference]: With dead ends: 31880 [2019-12-07 17:59:48,792 INFO L226 Difference]: Without dead ends: 26060 [2019-12-07 17:59:48,792 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 119 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=152, Invalid=660, Unknown=0, NotChecked=0, Total=812 [2019-12-07 17:59:48,867 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26060 states. [2019-12-07 17:59:49,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26060 to 19668. [2019-12-07 17:59:49,070 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19668 states. [2019-12-07 17:59:49,100 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19668 states to 19668 states and 58642 transitions. [2019-12-07 17:59:49,100 INFO L78 Accepts]: Start accepts. Automaton has 19668 states and 58642 transitions. Word has length 67 [2019-12-07 17:59:49,101 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:59:49,101 INFO L462 AbstractCegarLoop]: Abstraction has 19668 states and 58642 transitions. [2019-12-07 17:59:49,101 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 17:59:49,101 INFO L276 IsEmpty]: Start isEmpty. Operand 19668 states and 58642 transitions. [2019-12-07 17:59:49,118 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:59:49,118 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:59:49,118 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:59:49,118 INFO L410 AbstractCegarLoop]: === Iteration 37 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:59:49,119 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:59:49,119 INFO L82 PathProgramCache]: Analyzing trace with hash -1296513075, now seen corresponding path program 10 times [2019-12-07 17:59:49,119 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:59:49,119 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1211342112] [2019-12-07 17:59:49,119 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:59:49,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:59:49,597 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:59:49,597 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1211342112] [2019-12-07 17:59:49,597 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:59:49,597 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [16] imperfect sequences [] total 16 [2019-12-07 17:59:49,597 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [753977643] [2019-12-07 17:59:49,598 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2019-12-07 17:59:49,598 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:59:49,598 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2019-12-07 17:59:49,598 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=251, Unknown=0, NotChecked=0, Total=306 [2019-12-07 17:59:49,598 INFO L87 Difference]: Start difference. First operand 19668 states and 58642 transitions. Second operand 18 states. [2019-12-07 17:59:52,247 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:59:52,247 INFO L93 Difference]: Finished difference Result 27102 states and 79617 transitions. [2019-12-07 17:59:52,247 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2019-12-07 17:59:52,247 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 67 [2019-12-07 17:59:52,247 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:59:52,277 INFO L225 Difference]: With dead ends: 27102 [2019-12-07 17:59:52,277 INFO L226 Difference]: Without dead ends: 26435 [2019-12-07 17:59:52,278 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 0 SyntacticMatches, 6 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 793 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=475, Invalid=2387, Unknown=0, NotChecked=0, Total=2862 [2019-12-07 17:59:52,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26435 states. [2019-12-07 17:59:52,557 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26435 to 19608. [2019-12-07 17:59:52,557 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19608 states. [2019-12-07 17:59:52,588 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19608 states to 19608 states and 58504 transitions. [2019-12-07 17:59:52,589 INFO L78 Accepts]: Start accepts. Automaton has 19608 states and 58504 transitions. Word has length 67 [2019-12-07 17:59:52,589 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 17:59:52,589 INFO L462 AbstractCegarLoop]: Abstraction has 19608 states and 58504 transitions. [2019-12-07 17:59:52,589 INFO L463 AbstractCegarLoop]: Interpolant automaton has 18 states. [2019-12-07 17:59:52,589 INFO L276 IsEmpty]: Start isEmpty. Operand 19608 states and 58504 transitions. [2019-12-07 17:59:52,606 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 17:59:52,607 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 17:59:52,607 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 17:59:52,607 INFO L410 AbstractCegarLoop]: === Iteration 38 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 17:59:52,607 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 17:59:52,607 INFO L82 PathProgramCache]: Analyzing trace with hash 196609103, now seen corresponding path program 11 times [2019-12-07 17:59:52,607 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 17:59:52,607 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1865791396] [2019-12-07 17:59:52,607 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 17:59:52,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 17:59:52,983 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 17:59:52,983 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1865791396] [2019-12-07 17:59:52,983 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 17:59:52,984 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2019-12-07 17:59:52,984 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [121188055] [2019-12-07 17:59:52,984 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2019-12-07 17:59:52,984 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 17:59:52,984 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2019-12-07 17:59:52,984 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=56, Invalid=286, Unknown=0, NotChecked=0, Total=342 [2019-12-07 17:59:52,984 INFO L87 Difference]: Start difference. First operand 19608 states and 58504 transitions. Second operand 19 states. [2019-12-07 17:59:59,675 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 17:59:59,675 INFO L93 Difference]: Finished difference Result 42645 states and 125751 transitions. [2019-12-07 17:59:59,676 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 86 states. [2019-12-07 17:59:59,676 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 67 [2019-12-07 17:59:59,676 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 17:59:59,724 INFO L225 Difference]: With dead ends: 42645 [2019-12-07 17:59:59,724 INFO L226 Difference]: Without dead ends: 41848 [2019-12-07 17:59:59,727 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 89 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 87 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2714 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=1014, Invalid=6818, Unknown=0, NotChecked=0, Total=7832 [2019-12-07 17:59:59,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41848 states. [2019-12-07 18:00:00,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41848 to 19630. [2019-12-07 18:00:00,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19630 states. [2019-12-07 18:00:00,140 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19630 states to 19630 states and 58555 transitions. [2019-12-07 18:00:00,141 INFO L78 Accepts]: Start accepts. Automaton has 19630 states and 58555 transitions. Word has length 67 [2019-12-07 18:00:00,141 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:00:00,141 INFO L462 AbstractCegarLoop]: Abstraction has 19630 states and 58555 transitions. [2019-12-07 18:00:00,141 INFO L463 AbstractCegarLoop]: Interpolant automaton has 19 states. [2019-12-07 18:00:00,141 INFO L276 IsEmpty]: Start isEmpty. Operand 19630 states and 58555 transitions. [2019-12-07 18:00:00,158 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 18:00:00,158 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:00:00,158 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:00:00,158 INFO L410 AbstractCegarLoop]: === Iteration 39 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:00:00,158 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:00:00,158 INFO L82 PathProgramCache]: Analyzing trace with hash -825031337, now seen corresponding path program 12 times [2019-12-07 18:00:00,159 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:00:00,159 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1678296164] [2019-12-07 18:00:00,159 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:00:00,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:00:03,427 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:00:03,427 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1678296164] [2019-12-07 18:00:03,428 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:00:03,428 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [30] imperfect sequences [] total 30 [2019-12-07 18:00:03,428 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [741943081] [2019-12-07 18:00:03,428 INFO L442 AbstractCegarLoop]: Interpolant automaton has 32 states [2019-12-07 18:00:03,428 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:00:03,428 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2019-12-07 18:00:03,429 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=86, Invalid=906, Unknown=0, NotChecked=0, Total=992 [2019-12-07 18:00:03,429 INFO L87 Difference]: Start difference. First operand 19630 states and 58555 transitions. Second operand 32 states. [2019-12-07 18:00:09,045 WARN L192 SmtUtils]: Spent 152.00 ms on a formula simplification. DAG size of input: 25 DAG size of output: 23 [2019-12-07 18:00:15,993 WARN L192 SmtUtils]: Spent 118.00 ms on a formula simplification. DAG size of input: 35 DAG size of output: 28 [2019-12-07 18:00:17,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:00:17,191 INFO L93 Difference]: Finished difference Result 23834 states and 69757 transitions. [2019-12-07 18:00:17,192 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 100 states. [2019-12-07 18:00:17,192 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 67 [2019-12-07 18:00:17,193 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:00:17,233 INFO L225 Difference]: With dead ends: 23834 [2019-12-07 18:00:17,233 INFO L226 Difference]: Without dead ends: 22128 [2019-12-07 18:00:17,237 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 117 GetRequests, 1 SyntacticMatches, 5 SemanticMatches, 111 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3307 ImplicationChecksByTransitivity, 8.4s TimeCoverageRelationStatistics Valid=1111, Invalid=11545, Unknown=0, NotChecked=0, Total=12656 [2019-12-07 18:00:17,304 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22128 states. [2019-12-07 18:00:17,476 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22128 to 18967. [2019-12-07 18:00:17,476 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18967 states. [2019-12-07 18:00:17,505 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18967 states to 18967 states and 56319 transitions. [2019-12-07 18:00:17,505 INFO L78 Accepts]: Start accepts. Automaton has 18967 states and 56319 transitions. Word has length 67 [2019-12-07 18:00:17,505 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:00:17,505 INFO L462 AbstractCegarLoop]: Abstraction has 18967 states and 56319 transitions. [2019-12-07 18:00:17,505 INFO L463 AbstractCegarLoop]: Interpolant automaton has 32 states. [2019-12-07 18:00:17,505 INFO L276 IsEmpty]: Start isEmpty. Operand 18967 states and 56319 transitions. [2019-12-07 18:00:17,521 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 18:00:17,521 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:00:17,521 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:00:17,522 INFO L410 AbstractCegarLoop]: === Iteration 40 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:00:17,522 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:00:17,522 INFO L82 PathProgramCache]: Analyzing trace with hash 2106128165, now seen corresponding path program 13 times [2019-12-07 18:00:17,522 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:00:17,522 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1161390729] [2019-12-07 18:00:17,522 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:00:17,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:00:18,540 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:00:18,540 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1161390729] [2019-12-07 18:00:18,541 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:00:18,541 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [19] imperfect sequences [] total 19 [2019-12-07 18:00:18,541 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1008023236] [2019-12-07 18:00:18,541 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-12-07 18:00:18,541 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:00:18,541 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-12-07 18:00:18,541 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=354, Unknown=0, NotChecked=0, Total=420 [2019-12-07 18:00:18,542 INFO L87 Difference]: Start difference. First operand 18967 states and 56319 transitions. Second operand 21 states. [2019-12-07 18:00:21,132 WARN L192 SmtUtils]: Spent 164.00 ms on a formula simplification. DAG size of input: 38 DAG size of output: 22 [2019-12-07 18:00:22,244 WARN L192 SmtUtils]: Spent 172.00 ms on a formula simplification. DAG size of input: 36 DAG size of output: 22 [2019-12-07 18:00:23,304 WARN L192 SmtUtils]: Spent 169.00 ms on a formula simplification. DAG size of input: 32 DAG size of output: 32 [2019-12-07 18:00:23,564 WARN L192 SmtUtils]: Spent 187.00 ms on a formula simplification. DAG size of input: 38 DAG size of output: 24 [2019-12-07 18:00:24,591 WARN L192 SmtUtils]: Spent 223.00 ms on a formula simplification. DAG size of input: 34 DAG size of output: 28 [2019-12-07 18:00:26,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:00:26,967 INFO L93 Difference]: Finished difference Result 24454 states and 71467 transitions. [2019-12-07 18:00:26,967 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2019-12-07 18:00:26,967 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 67 [2019-12-07 18:00:26,967 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:00:26,991 INFO L225 Difference]: With dead ends: 24454 [2019-12-07 18:00:26,991 INFO L226 Difference]: Without dead ends: 23915 [2019-12-07 18:00:26,991 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 2 SyntacticMatches, 4 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1015 ImplicationChecksByTransitivity, 3.5s TimeCoverageRelationStatistics Valid=556, Invalid=2984, Unknown=0, NotChecked=0, Total=3540 [2019-12-07 18:00:27,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23915 states. [2019-12-07 18:00:27,250 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23915 to 18954. [2019-12-07 18:00:27,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18954 states. [2019-12-07 18:00:27,279 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18954 states to 18954 states and 56284 transitions. [2019-12-07 18:00:27,280 INFO L78 Accepts]: Start accepts. Automaton has 18954 states and 56284 transitions. Word has length 67 [2019-12-07 18:00:27,280 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:00:27,280 INFO L462 AbstractCegarLoop]: Abstraction has 18954 states and 56284 transitions. [2019-12-07 18:00:27,280 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-12-07 18:00:27,280 INFO L276 IsEmpty]: Start isEmpty. Operand 18954 states and 56284 transitions. [2019-12-07 18:00:27,296 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 18:00:27,297 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:00:27,297 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:00:27,297 INFO L410 AbstractCegarLoop]: === Iteration 41 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:00:27,297 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:00:27,297 INFO L82 PathProgramCache]: Analyzing trace with hash -231220581, now seen corresponding path program 14 times [2019-12-07 18:00:27,297 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:00:27,297 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [786694833] [2019-12-07 18:00:27,297 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:00:27,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:00:27,942 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:00:27,943 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [786694833] [2019-12-07 18:00:27,943 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:00:27,943 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [19] imperfect sequences [] total 19 [2019-12-07 18:00:27,943 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1300168715] [2019-12-07 18:00:27,943 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2019-12-07 18:00:27,943 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:00:27,943 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2019-12-07 18:00:27,943 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=65, Invalid=355, Unknown=0, NotChecked=0, Total=420 [2019-12-07 18:00:27,943 INFO L87 Difference]: Start difference. First operand 18954 states and 56284 transitions. Second operand 21 states. [2019-12-07 18:00:32,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:00:32,436 INFO L93 Difference]: Finished difference Result 28614 states and 84249 transitions. [2019-12-07 18:00:32,437 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2019-12-07 18:00:32,437 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 67 [2019-12-07 18:00:32,437 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:00:32,473 INFO L225 Difference]: With dead ends: 28614 [2019-12-07 18:00:32,474 INFO L226 Difference]: Without dead ends: 28207 [2019-12-07 18:00:32,474 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 2 SyntacticMatches, 4 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1196 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=660, Invalid=3372, Unknown=0, NotChecked=0, Total=4032 [2019-12-07 18:00:32,556 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28207 states. [2019-12-07 18:00:32,767 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28207 to 18901. [2019-12-07 18:00:32,767 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18901 states. [2019-12-07 18:00:32,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18901 states to 18901 states and 56159 transitions. [2019-12-07 18:00:32,796 INFO L78 Accepts]: Start accepts. Automaton has 18901 states and 56159 transitions. Word has length 67 [2019-12-07 18:00:32,796 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:00:32,796 INFO L462 AbstractCegarLoop]: Abstraction has 18901 states and 56159 transitions. [2019-12-07 18:00:32,796 INFO L463 AbstractCegarLoop]: Interpolant automaton has 21 states. [2019-12-07 18:00:32,797 INFO L276 IsEmpty]: Start isEmpty. Operand 18901 states and 56159 transitions. [2019-12-07 18:00:32,916 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 18:00:32,916 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:00:32,917 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:00:32,917 INFO L410 AbstractCegarLoop]: === Iteration 42 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:00:32,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:00:32,917 INFO L82 PathProgramCache]: Analyzing trace with hash -1552392047, now seen corresponding path program 15 times [2019-12-07 18:00:32,917 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:00:32,917 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1318693615] [2019-12-07 18:00:32,917 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:00:32,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:00:33,098 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:00:33,099 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1318693615] [2019-12-07 18:00:33,099 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:00:33,099 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2019-12-07 18:00:33,099 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [744826058] [2019-12-07 18:00:33,099 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 18:00:33,099 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:00:33,099 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 18:00:33,099 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=129, Unknown=0, NotChecked=0, Total=156 [2019-12-07 18:00:33,100 INFO L87 Difference]: Start difference. First operand 18901 states and 56159 transitions. Second operand 13 states. [2019-12-07 18:00:34,929 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:00:34,929 INFO L93 Difference]: Finished difference Result 44890 states and 131785 transitions. [2019-12-07 18:00:34,929 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2019-12-07 18:00:34,929 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 67 [2019-12-07 18:00:34,929 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:00:34,969 INFO L225 Difference]: With dead ends: 44890 [2019-12-07 18:00:34,970 INFO L226 Difference]: Without dead ends: 35518 [2019-12-07 18:00:34,970 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 0 SyntacticMatches, 2 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 580 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=396, Invalid=1860, Unknown=0, NotChecked=0, Total=2256 [2019-12-07 18:00:35,065 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35518 states. [2019-12-07 18:00:35,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35518 to 18585. [2019-12-07 18:00:35,294 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18585 states. [2019-12-07 18:00:35,322 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18585 states to 18585 states and 55220 transitions. [2019-12-07 18:00:35,323 INFO L78 Accepts]: Start accepts. Automaton has 18585 states and 55220 transitions. Word has length 67 [2019-12-07 18:00:35,323 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:00:35,323 INFO L462 AbstractCegarLoop]: Abstraction has 18585 states and 55220 transitions. [2019-12-07 18:00:35,323 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 18:00:35,323 INFO L276 IsEmpty]: Start isEmpty. Operand 18585 states and 55220 transitions. [2019-12-07 18:00:35,339 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 18:00:35,339 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:00:35,339 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:00:35,339 INFO L410 AbstractCegarLoop]: === Iteration 43 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:00:35,339 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:00:35,339 INFO L82 PathProgramCache]: Analyzing trace with hash 199262577, now seen corresponding path program 16 times [2019-12-07 18:00:35,340 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:00:35,340 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [850325380] [2019-12-07 18:00:35,340 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:00:35,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:00:35,510 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:00:35,511 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [850325380] [2019-12-07 18:00:35,511 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:00:35,511 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 18:00:35,511 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1943256864] [2019-12-07 18:00:35,511 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 18:00:35,511 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:00:35,511 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 18:00:35,512 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=152, Unknown=0, NotChecked=0, Total=182 [2019-12-07 18:00:35,512 INFO L87 Difference]: Start difference. First operand 18585 states and 55220 transitions. Second operand 14 states. [2019-12-07 18:00:37,661 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:00:37,661 INFO L93 Difference]: Finished difference Result 48008 states and 140546 transitions. [2019-12-07 18:00:37,661 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2019-12-07 18:00:37,661 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 67 [2019-12-07 18:00:37,662 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:00:37,699 INFO L225 Difference]: With dead ends: 48008 [2019-12-07 18:00:37,699 INFO L226 Difference]: Without dead ends: 35145 [2019-12-07 18:00:37,700 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 813 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=470, Invalid=2610, Unknown=0, NotChecked=0, Total=3080 [2019-12-07 18:00:37,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35145 states. [2019-12-07 18:00:38,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35145 to 18358. [2019-12-07 18:00:38,025 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18358 states. [2019-12-07 18:00:38,053 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18358 states to 18358 states and 54614 transitions. [2019-12-07 18:00:38,053 INFO L78 Accepts]: Start accepts. Automaton has 18358 states and 54614 transitions. Word has length 67 [2019-12-07 18:00:38,053 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:00:38,053 INFO L462 AbstractCegarLoop]: Abstraction has 18358 states and 54614 transitions. [2019-12-07 18:00:38,053 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 18:00:38,054 INFO L276 IsEmpty]: Start isEmpty. Operand 18358 states and 54614 transitions. [2019-12-07 18:00:38,069 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 18:00:38,070 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:00:38,070 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:00:38,070 INFO L410 AbstractCegarLoop]: === Iteration 44 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:00:38,070 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:00:38,070 INFO L82 PathProgramCache]: Analyzing trace with hash -1230610911, now seen corresponding path program 17 times [2019-12-07 18:00:38,070 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:00:38,070 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [706497697] [2019-12-07 18:00:38,070 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:00:38,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:00:38,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:00:38,185 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [706497697] [2019-12-07 18:00:38,185 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:00:38,185 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-07 18:00:38,185 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [96586291] [2019-12-07 18:00:38,186 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-12-07 18:00:38,186 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:00:38,186 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-12-07 18:00:38,186 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2019-12-07 18:00:38,186 INFO L87 Difference]: Start difference. First operand 18358 states and 54614 transitions. Second operand 10 states. [2019-12-07 18:00:39,153 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:00:39,153 INFO L93 Difference]: Finished difference Result 31724 states and 94511 transitions. [2019-12-07 18:00:39,153 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 18:00:39,153 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 67 [2019-12-07 18:00:39,153 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:00:39,183 INFO L225 Difference]: With dead ends: 31724 [2019-12-07 18:00:39,183 INFO L226 Difference]: Without dead ends: 26973 [2019-12-07 18:00:39,183 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 43 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=73, Invalid=307, Unknown=0, NotChecked=0, Total=380 [2019-12-07 18:00:39,262 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26973 states. [2019-12-07 18:00:39,467 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26973 to 18236. [2019-12-07 18:00:39,468 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18236 states. [2019-12-07 18:00:39,496 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18236 states to 18236 states and 54285 transitions. [2019-12-07 18:00:39,496 INFO L78 Accepts]: Start accepts. Automaton has 18236 states and 54285 transitions. Word has length 67 [2019-12-07 18:00:39,496 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:00:39,496 INFO L462 AbstractCegarLoop]: Abstraction has 18236 states and 54285 transitions. [2019-12-07 18:00:39,496 INFO L463 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-12-07 18:00:39,496 INFO L276 IsEmpty]: Start isEmpty. Operand 18236 states and 54285 transitions. [2019-12-07 18:00:39,512 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 18:00:39,512 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:00:39,512 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:00:39,512 INFO L410 AbstractCegarLoop]: === Iteration 45 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:00:39,512 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:00:39,513 INFO L82 PathProgramCache]: Analyzing trace with hash -2013885398, now seen corresponding path program 2 times [2019-12-07 18:00:39,513 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:00:39,513 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [541495472] [2019-12-07 18:00:39,513 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:00:39,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:00:39,687 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:00:39,687 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [541495472] [2019-12-07 18:00:39,687 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:00:39,687 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 18:00:39,687 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [350515704] [2019-12-07 18:00:39,687 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2019-12-07 18:00:39,687 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:00:39,687 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2019-12-07 18:00:39,688 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=149, Unknown=0, NotChecked=0, Total=182 [2019-12-07 18:00:39,688 INFO L87 Difference]: Start difference. First operand 18236 states and 54285 transitions. Second operand 14 states. [2019-12-07 18:00:41,167 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:00:41,167 INFO L93 Difference]: Finished difference Result 26033 states and 76898 transitions. [2019-12-07 18:00:41,167 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2019-12-07 18:00:41,167 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 67 [2019-12-07 18:00:41,167 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:00:41,188 INFO L225 Difference]: With dead ends: 26033 [2019-12-07 18:00:41,188 INFO L226 Difference]: Without dead ends: 21216 [2019-12-07 18:00:41,189 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 213 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=237, Invalid=1023, Unknown=0, NotChecked=0, Total=1260 [2019-12-07 18:00:41,254 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21216 states. [2019-12-07 18:00:41,420 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21216 to 17906. [2019-12-07 18:00:41,420 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17906 states. [2019-12-07 18:00:41,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17906 states to 17906 states and 53437 transitions. [2019-12-07 18:00:41,447 INFO L78 Accepts]: Start accepts. Automaton has 17906 states and 53437 transitions. Word has length 67 [2019-12-07 18:00:41,447 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:00:41,448 INFO L462 AbstractCegarLoop]: Abstraction has 17906 states and 53437 transitions. [2019-12-07 18:00:41,448 INFO L463 AbstractCegarLoop]: Interpolant automaton has 14 states. [2019-12-07 18:00:41,448 INFO L276 IsEmpty]: Start isEmpty. Operand 17906 states and 53437 transitions. [2019-12-07 18:00:41,463 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 18:00:41,463 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:00:41,463 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:00:41,463 INFO L410 AbstractCegarLoop]: === Iteration 46 === [P0Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P0Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:00:41,463 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:00:41,463 INFO L82 PathProgramCache]: Analyzing trace with hash -1127178005, now seen corresponding path program 18 times [2019-12-07 18:00:41,463 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:00:41,463 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [40992454] [2019-12-07 18:00:41,463 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:00:41,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:00:41,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:00:41,542 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:00:41,542 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 18:00:41,544 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [893] [893] ULTIMATE.startENTRY-->L823: Formula: (let ((.cse0 (store |v_#valid_82| 0 0))) (and (= 0 v_~z$r_buff1_thd3~0_333) (= 0 v_~__unbuffered_cnt~0_79) (= v_~z~0_222 0) (= 0 v_~x~0_150) (= 0 v_~z$flush_delayed~0_66) (= v_~__unbuffered_p2_EBX~0_70 0) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t745~0.base_43|) (= (store .cse0 |v_ULTIMATE.start_main_~#t745~0.base_43| 1) |v_#valid_80|) (= v_~y~0_71 0) (= v_~z$read_delayed_var~0.base_8 0) (< 0 |v_#StackHeapBarrier_17|) (= v_~z$r_buff0_thd1~0_186 0) (= v_~z$w_buff1_used~0_670 0) (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t745~0.base_43| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t745~0.base_43|) |v_ULTIMATE.start_main_~#t745~0.offset_29| 0)) |v_#memory_int_17|) (= (select .cse0 |v_ULTIMATE.start_main_~#t745~0.base_43|) 0) (= v_~z$r_buff0_thd2~0_110 0) (= 0 v_~weak$$choice0~0_29) (= v_~z$w_buff0~0_701 0) (= v_~z$r_buff1_thd0~0_201 0) (= v_~z$read_delayed~0_7 0) (= 0 v_~z$r_buff0_thd3~0_363) (= 0 v_~__unbuffered_p2_EAX~0_62) (= |v_#NULL.offset_5| 0) (= v_~z$mem_tmp~0_43 0) (= v_~z$r_buff0_thd0~0_137 0) (= v_~weak$$choice2~0_160 0) (= |v_#length_27| (store |v_#length_28| |v_ULTIMATE.start_main_~#t745~0.base_43| 4)) (= 0 |v_ULTIMATE.start_main_~#t745~0.offset_29|) (= v_~z$r_buff1_thd1~0_144 0) (= v_~z$r_buff1_thd2~0_165 0) (= v_~z$w_buff0_used~0_1072 0) (= v_~z$w_buff1~0_410 0) (= v_~main$tmp_guard0~0_24 0) (= v_~main$tmp_guard1~0_54 0) (= 0 |v_#NULL.base_5|) (= v_~z$read_delayed_var~0.offset_8 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_82|, #memory_int=|v_#memory_int_18|, #length=|v_#length_28|} OutVars{~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_165, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_46|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_202|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_46|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_120|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_137, ULTIMATE.start_main_~#t745~0.base=|v_ULTIMATE.start_main_~#t745~0.base_43|, #length=|v_#length_27|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_62, ~z$mem_tmp~0=v_~z$mem_tmp~0_43, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_70, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_10|, ULTIMATE.start_main_~#t747~0.base=|v_ULTIMATE.start_main_~#t747~0.base_29|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_670, ULTIMATE.start_main_~#t746~0.offset=|v_ULTIMATE.start_main_~#t746~0.offset_22|, ~z$flush_delayed~0=v_~z$flush_delayed~0_66, ~weak$$choice0~0=v_~weak$$choice0~0_29, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_144, ULTIMATE.start_main_~#t747~0.offset=|v_ULTIMATE.start_main_~#t747~0.offset_21|, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_8, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_363, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_79, ~x~0=v_~x~0_150, ~z$read_delayed~0=v_~z$read_delayed~0_7, ~z$w_buff1~0=v_~z$w_buff1~0_410, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_54, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_74|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_8, ULTIMATE.start_main_~#t746~0.base=|v_ULTIMATE.start_main_~#t746~0.base_37|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_34|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_201, ~y~0=v_~y~0_71, ULTIMATE.start_main_~#t745~0.offset=|v_ULTIMATE.start_main_~#t745~0.offset_29|, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_110, ULTIMATE.start_main_#t~nondet46=|v_ULTIMATE.start_main_#t~nondet46_26|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_1072, ~z$w_buff0~0=v_~z$w_buff0~0_701, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_10|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_333, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_24, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_31|, #valid=|v_#valid_80|, #memory_int=|v_#memory_int_17|, ~z~0=v_~z~0_222, ~weak$$choice2~0=v_~weak$$choice2~0_160, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_186} AuxVars[] AssignedVars[~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite47, ~z$read_delayed~0, #NULL.offset, ~z$w_buff1~0, ULTIMATE.start_main_#t~ite49, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite48, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_~#t746~0.base, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite51, ULTIMATE.start_main_~#t745~0.base, ~z$r_buff1_thd0~0, #length, ~__unbuffered_p2_EAX~0, ~y~0, ULTIMATE.start_main_~#t745~0.offset, ~z$r_buff0_thd2~0, ~z$mem_tmp~0, ~__unbuffered_p2_EBX~0, ULTIMATE.start_main_#t~nondet46, ~z$w_buff0_used~0, ~z$w_buff0~0, ULTIMATE.start_main_#t~nondet44, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~nondet45, ULTIMATE.start_main_~#t747~0.base, ~z$w_buff1_used~0, ULTIMATE.start_main_~#t746~0.offset, ~z$flush_delayed~0, ~main$tmp_guard0~0, #NULL.base, ~weak$$choice0~0, ULTIMATE.start_main_#res, ~z$r_buff1_thd1~0, #valid, ULTIMATE.start_main_~#t747~0.offset, #memory_int, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ~__unbuffered_cnt~0, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0, ~x~0] because there is no mapped edge [2019-12-07 18:00:41,545 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [865] [865] L823-1-->L825: Formula: (and (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t746~0.base_11| 4)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t746~0.base_11| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t746~0.base_11|) |v_ULTIMATE.start_main_~#t746~0.offset_10| 1)) |v_#memory_int_13|) (= |v_ULTIMATE.start_main_~#t746~0.offset_10| 0) (= 0 (select |v_#valid_34| |v_ULTIMATE.start_main_~#t746~0.base_11|)) (not (= |v_ULTIMATE.start_main_~#t746~0.base_11| 0)) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t746~0.base_11|) (= |v_#valid_33| (store |v_#valid_34| |v_ULTIMATE.start_main_~#t746~0.base_11| 1))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_5|, #valid=|v_#valid_33|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_~#t746~0.offset=|v_ULTIMATE.start_main_~#t746~0.offset_10|, #length=|v_#length_17|, ULTIMATE.start_main_~#t746~0.base=|v_ULTIMATE.start_main_~#t746~0.base_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet44, #valid, #memory_int, ULTIMATE.start_main_~#t746~0.offset, #length, ULTIMATE.start_main_~#t746~0.base] because there is no mapped edge [2019-12-07 18:00:41,545 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [772] [772] P0ENTRY-->L4-3: Formula: (and (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_21 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_19|) (= |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_19| (ite (not (and (not (= (mod v_~z$w_buff0_used~0_174 256) 0)) (not (= (mod v_~z$w_buff1_used~0_104 256) 0)))) 1 0)) (= v_~z$w_buff0_used~0_174 1) (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_21 0)) (= v_~z$w_buff0~0_53 v_~z$w_buff1~0_38) (= v_~z$w_buff0_used~0_175 v_~z$w_buff1_used~0_104) (= v_P0Thread1of1ForFork0_~arg.offset_19 |v_P0Thread1of1ForFork0_#in~arg.offset_21|) (= v_P0Thread1of1ForFork0_~arg.base_19 |v_P0Thread1of1ForFork0_#in~arg.base_21|) (= 1 v_~z$w_buff0~0_52)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_21|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_175, ~z$w_buff0~0=v_~z$w_buff0~0_53, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_21|} OutVars{P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_21|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_174, ~z$w_buff0~0=v_~z$w_buff0~0_52, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_21, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_104, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_21|, ~z$w_buff1~0=v_~z$w_buff1~0_38, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_19, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_19|, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_19} AuxVars[] AssignedVars[~z$w_buff0_used~0, ~z$w_buff0~0, P0Thread1of1ForFork0___VERIFIER_assert_~expression, ~z$w_buff1_used~0, ~z$w_buff1~0, P0Thread1of1ForFork0_~arg.base, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression, P0Thread1of1ForFork0_~arg.offset] because there is no mapped edge [2019-12-07 18:00:41,546 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [853] [853] L825-1-->L827: Formula: (and (= (store |v_#length_16| |v_ULTIMATE.start_main_~#t747~0.base_10| 4) |v_#length_15|) (= (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t747~0.base_10| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t747~0.base_10|) |v_ULTIMATE.start_main_~#t747~0.offset_9| 2)) |v_#memory_int_11|) (< |v_#StackHeapBarrier_9| |v_ULTIMATE.start_main_~#t747~0.base_10|) (= |v_#valid_29| (store |v_#valid_30| |v_ULTIMATE.start_main_~#t747~0.base_10| 1)) (not (= |v_ULTIMATE.start_main_~#t747~0.base_10| 0)) (= (select |v_#valid_30| |v_ULTIMATE.start_main_~#t747~0.base_10|) 0) (= 0 |v_ULTIMATE.start_main_~#t747~0.offset_9|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_30|, #memory_int=|v_#memory_int_12|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_9|, ULTIMATE.start_main_~#t747~0.base=|v_ULTIMATE.start_main_~#t747~0.base_10|, #valid=|v_#valid_29|, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_5|, #memory_int=|v_#memory_int_11|, ULTIMATE.start_main_~#t747~0.offset=|v_ULTIMATE.start_main_~#t747~0.offset_9|, #length=|v_#length_15|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t747~0.base, #valid, ULTIMATE.start_main_#t~nondet45, #memory_int, ULTIMATE.start_main_~#t747~0.offset, #length] because there is no mapped edge [2019-12-07 18:00:41,548 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [819] [819] L764-2-->L764-4: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff1_used~0_In141598029 256))) (.cse0 (= 0 (mod ~z$r_buff1_thd2~0_In141598029 256)))) (or (and (not .cse0) (not .cse1) (= ~z$w_buff1~0_In141598029 |P1Thread1of1ForFork1_#t~ite9_Out141598029|)) (and (= ~z~0_In141598029 |P1Thread1of1ForFork1_#t~ite9_Out141598029|) (or .cse1 .cse0)))) InVars {~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In141598029, ~z$w_buff1_used~0=~z$w_buff1_used~0_In141598029, ~z$w_buff1~0=~z$w_buff1~0_In141598029, ~z~0=~z~0_In141598029} OutVars{P1Thread1of1ForFork1_#t~ite9=|P1Thread1of1ForFork1_#t~ite9_Out141598029|, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In141598029, ~z$w_buff1_used~0=~z$w_buff1_used~0_In141598029, ~z$w_buff1~0=~z$w_buff1~0_In141598029, ~z~0=~z~0_In141598029} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9] because there is no mapped edge [2019-12-07 18:00:41,549 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [875] [875] L789-->L789-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In153953061 256)))) (or (and (= ~z$w_buff0~0_In153953061 |P2Thread1of1ForFork2_#t~ite21_Out153953061|) (= |P2Thread1of1ForFork2_#t~ite20_In153953061| |P2Thread1of1ForFork2_#t~ite20_Out153953061|) (not .cse0)) (and .cse0 (= |P2Thread1of1ForFork2_#t~ite21_Out153953061| |P2Thread1of1ForFork2_#t~ite20_Out153953061|) (let ((.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In153953061 256)))) (or (= 0 (mod ~z$w_buff0_used~0_In153953061 256)) (and (= 0 (mod ~z$w_buff1_used~0_In153953061 256)) .cse1) (and (= 0 (mod ~z$r_buff1_thd3~0_In153953061 256)) .cse1))) (= ~z$w_buff0~0_In153953061 |P2Thread1of1ForFork2_#t~ite20_Out153953061|)))) InVars {~z$w_buff0~0=~z$w_buff0~0_In153953061, ~z$w_buff0_used~0=~z$w_buff0_used~0_In153953061, P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_In153953061|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In153953061, ~z$w_buff1_used~0=~z$w_buff1_used~0_In153953061, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In153953061, ~weak$$choice2~0=~weak$$choice2~0_In153953061} OutVars{~z$w_buff0~0=~z$w_buff0~0_In153953061, P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out153953061|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In153953061, P2Thread1of1ForFork2_#t~ite21=|P2Thread1of1ForFork2_#t~ite21_Out153953061|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In153953061, ~z$w_buff1_used~0=~z$w_buff1_used~0_In153953061, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In153953061, ~weak$$choice2~0=~weak$$choice2~0_In153953061} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, P2Thread1of1ForFork2_#t~ite21] because there is no mapped edge [2019-12-07 18:00:41,550 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [839] [839] L745-->L745-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1625098975 256))) (.cse1 (= (mod ~z$r_buff0_thd1~0_In-1625098975 256) 0))) (or (and (= 0 |P0Thread1of1ForFork0_#t~ite5_Out-1625098975|) (not .cse0) (not .cse1)) (and (or .cse0 .cse1) (= ~z$w_buff0_used~0_In-1625098975 |P0Thread1of1ForFork0_#t~ite5_Out-1625098975|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1625098975, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1625098975} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out-1625098975|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1625098975, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1625098975} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 18:00:41,550 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [833] [833] L746-->L746-2: Formula: (let ((.cse3 (= (mod ~z$r_buff0_thd1~0_In332727980 256) 0)) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In332727980 256))) (.cse0 (= (mod ~z$r_buff1_thd1~0_In332727980 256) 0)) (.cse1 (= (mod ~z$w_buff1_used~0_In332727980 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P0Thread1of1ForFork0_#t~ite6_Out332727980| ~z$w_buff1_used~0_In332727980)) (and (= |P0Thread1of1ForFork0_#t~ite6_Out332727980| 0) (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In332727980, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In332727980, ~z$w_buff1_used~0=~z$w_buff1_used~0_In332727980, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In332727980} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out332727980|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In332727980, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In332727980, ~z$w_buff1_used~0=~z$w_buff1_used~0_In332727980, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In332727980} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 18:00:41,551 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [838] [838] L747-->L748: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In2146788807 256))) (.cse2 (= ~z$r_buff0_thd1~0_Out2146788807 ~z$r_buff0_thd1~0_In2146788807)) (.cse0 (= 0 (mod ~z$r_buff0_thd1~0_In2146788807 256)))) (or (and (not .cse0) (not .cse1) (= ~z$r_buff0_thd1~0_Out2146788807 0)) (and .cse2 .cse1) (and .cse2 .cse0))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In2146788807, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In2146788807} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In2146788807, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out2146788807|, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_Out2146788807} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 18:00:41,551 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [828] [828] L748-->L748-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd1~0_In-540213841 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In-540213841 256) 0)) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In-540213841 256))) (.cse2 (= 0 (mod ~z$r_buff1_thd1~0_In-540213841 256)))) (or (and (= |P0Thread1of1ForFork0_#t~ite8_Out-540213841| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (or .cse3 .cse2) (= |P0Thread1of1ForFork0_#t~ite8_Out-540213841| ~z$r_buff1_thd1~0_In-540213841)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-540213841, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-540213841, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-540213841, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-540213841} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-540213841, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out-540213841|, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-540213841, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-540213841, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-540213841} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 18:00:41,551 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [851] [851] L748-2-->P0EXIT: Formula: (and (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~z$r_buff1_thd1~0_62 |v_P0Thread1of1ForFork0_#t~ite8_22|) (= (+ v_~__unbuffered_cnt~0_56 1) v_~__unbuffered_cnt~0_55) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_22|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_56} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_21|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_62, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, ~z$r_buff1_thd1~0, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 18:00:41,552 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [874] [874] L790-->L790-8: Formula: (let ((.cse1 (= (mod ~weak$$choice2~0_In-1958677726 256) 0))) (or (and (let ((.cse0 (= (mod ~z$r_buff0_thd3~0_In-1958677726 256) 0))) (or (and (= (mod ~z$w_buff1_used~0_In-1958677726 256) 0) .cse0) (and (= (mod ~z$r_buff1_thd3~0_In-1958677726 256) 0) .cse0) (= 0 (mod ~z$w_buff0_used~0_In-1958677726 256)))) (= ~z$w_buff1~0_In-1958677726 |P2Thread1of1ForFork2_#t~ite23_Out-1958677726|) .cse1 (= |P2Thread1of1ForFork2_#t~ite24_Out-1958677726| |P2Thread1of1ForFork2_#t~ite23_Out-1958677726|)) (and (= ~z$w_buff1~0_In-1958677726 |P2Thread1of1ForFork2_#t~ite24_Out-1958677726|) (= |P2Thread1of1ForFork2_#t~ite23_In-1958677726| |P2Thread1of1ForFork2_#t~ite23_Out-1958677726|) (not .cse1)))) InVars {P2Thread1of1ForFork2_#t~ite23=|P2Thread1of1ForFork2_#t~ite23_In-1958677726|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1958677726, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1958677726, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1958677726, ~z$w_buff1~0=~z$w_buff1~0_In-1958677726, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1958677726, ~weak$$choice2~0=~weak$$choice2~0_In-1958677726} OutVars{P2Thread1of1ForFork2_#t~ite23=|P2Thread1of1ForFork2_#t~ite23_Out-1958677726|, P2Thread1of1ForFork2_#t~ite24=|P2Thread1of1ForFork2_#t~ite24_Out-1958677726|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1958677726, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1958677726, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1958677726, ~z$w_buff1~0=~z$w_buff1~0_In-1958677726, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1958677726, ~weak$$choice2~0=~weak$$choice2~0_In-1958677726} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite23, P2Thread1of1ForFork2_#t~ite24] because there is no mapped edge [2019-12-07 18:00:41,553 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [873] [873] L791-->L791-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In2124289530 256)))) (or (and (= |P2Thread1of1ForFork2_#t~ite27_Out2124289530| ~z$w_buff0_used~0_In2124289530) (not .cse0) (= |P2Thread1of1ForFork2_#t~ite26_In2124289530| |P2Thread1of1ForFork2_#t~ite26_Out2124289530|)) (and (= |P2Thread1of1ForFork2_#t~ite26_Out2124289530| |P2Thread1of1ForFork2_#t~ite27_Out2124289530|) (let ((.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In2124289530 256)))) (or (and .cse1 (= (mod ~z$r_buff1_thd3~0_In2124289530 256) 0)) (and (= 0 (mod ~z$w_buff1_used~0_In2124289530 256)) .cse1) (= 0 (mod ~z$w_buff0_used~0_In2124289530 256)))) .cse0 (= |P2Thread1of1ForFork2_#t~ite26_Out2124289530| ~z$w_buff0_used~0_In2124289530)))) InVars {P2Thread1of1ForFork2_#t~ite26=|P2Thread1of1ForFork2_#t~ite26_In2124289530|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In2124289530, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In2124289530, ~z$w_buff1_used~0=~z$w_buff1_used~0_In2124289530, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In2124289530, ~weak$$choice2~0=~weak$$choice2~0_In2124289530} OutVars{P2Thread1of1ForFork2_#t~ite26=|P2Thread1of1ForFork2_#t~ite26_Out2124289530|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In2124289530, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In2124289530, ~z$w_buff1_used~0=~z$w_buff1_used~0_In2124289530, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In2124289530, ~weak$$choice2~0=~weak$$choice2~0_In2124289530, P2Thread1of1ForFork2_#t~ite27=|P2Thread1of1ForFork2_#t~ite27_Out2124289530|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite26, P2Thread1of1ForFork2_#t~ite27] because there is no mapped edge [2019-12-07 18:00:41,554 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [812] [812] L793-->L794: Formula: (and (not (= (mod v_~weak$$choice2~0_37 256) 0)) (= v_~z$r_buff0_thd3~0_119 v_~z$r_buff0_thd3~0_118)) InVars {~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_119, ~weak$$choice2~0=v_~weak$$choice2~0_37} OutVars{P2Thread1of1ForFork2_#t~ite31=|v_P2Thread1of1ForFork2_#t~ite31_6|, P2Thread1of1ForFork2_#t~ite33=|v_P2Thread1of1ForFork2_#t~ite33_6|, P2Thread1of1ForFork2_#t~ite32=|v_P2Thread1of1ForFork2_#t~ite32_7|, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_118, ~weak$$choice2~0=v_~weak$$choice2~0_37} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite31, P2Thread1of1ForFork2_#t~ite33, P2Thread1of1ForFork2_#t~ite32, ~z$r_buff0_thd3~0] because there is no mapped edge [2019-12-07 18:00:41,555 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [750] [750] L764-4-->L765: Formula: (= |v_P1Thread1of1ForFork1_#t~ite9_6| v_~z~0_16) InVars {P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_6|} OutVars{P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_5|, P1Thread1of1ForFork1_#t~ite10=|v_P1Thread1of1ForFork1_#t~ite10_5|, ~z~0=v_~z~0_16} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9, P1Thread1of1ForFork1_#t~ite10, ~z~0] because there is no mapped edge [2019-12-07 18:00:41,555 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [823] [823] L765-->L765-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In185604816 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In185604816 256)))) (or (and (= ~z$w_buff0_used~0_In185604816 |P1Thread1of1ForFork1_#t~ite11_Out185604816|) (or .cse0 .cse1)) (and (= 0 |P1Thread1of1ForFork1_#t~ite11_Out185604816|) (not .cse1) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In185604816, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In185604816} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In185604816, P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out185604816|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In185604816} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 18:00:41,556 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [816] [816] L766-->L766-2: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd2~0_In-531084114 256) 0)) (.cse1 (= (mod ~z$w_buff1_used~0_In-531084114 256) 0)) (.cse3 (= (mod ~z$w_buff0_used~0_In-531084114 256) 0)) (.cse2 (= (mod ~z$r_buff0_thd2~0_In-531084114 256) 0))) (or (and (= |P1Thread1of1ForFork1_#t~ite12_Out-531084114| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (= ~z$w_buff1_used~0_In-531084114 |P1Thread1of1ForFork1_#t~ite12_Out-531084114|) (or .cse3 .cse2)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-531084114, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-531084114, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-531084114, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-531084114} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-531084114, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-531084114, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-531084114, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out-531084114|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-531084114} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 18:00:41,557 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [817] [817] L767-->L767-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd2~0_In-2116334430 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-2116334430 256)))) (or (and (not .cse0) (= 0 |P1Thread1of1ForFork1_#t~ite13_Out-2116334430|) (not .cse1)) (and (or .cse1 .cse0) (= ~z$r_buff0_thd2~0_In-2116334430 |P1Thread1of1ForFork1_#t~ite13_Out-2116334430|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-2116334430, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-2116334430} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-2116334430, P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out-2116334430|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-2116334430} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13] because there is no mapped edge [2019-12-07 18:00:41,557 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [811] [811] L796-->L800: Formula: (and (= v_~z~0_64 v_~z$mem_tmp~0_7) (not (= 0 (mod v_~z$flush_delayed~0_10 256))) (= 0 v_~z$flush_delayed~0_9)) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_7, ~z$flush_delayed~0=v_~z$flush_delayed~0_10} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_7, P2Thread1of1ForFork2_#t~ite37=|v_P2Thread1of1ForFork2_#t~ite37_5|, ~z$flush_delayed~0=v_~z$flush_delayed~0_9, ~z~0=v_~z~0_64} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite37, ~z$flush_delayed~0, ~z~0] because there is no mapped edge [2019-12-07 18:00:41,557 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [822] [822] L800-2-->L800-5: Formula: (let ((.cse1 (= |P2Thread1of1ForFork2_#t~ite38_Out2061772868| |P2Thread1of1ForFork2_#t~ite39_Out2061772868|)) (.cse2 (= (mod ~z$w_buff1_used~0_In2061772868 256) 0)) (.cse0 (= 0 (mod ~z$r_buff1_thd3~0_In2061772868 256)))) (or (and (not .cse0) .cse1 (not .cse2) (= |P2Thread1of1ForFork2_#t~ite38_Out2061772868| ~z$w_buff1~0_In2061772868)) (and .cse1 (= |P2Thread1of1ForFork2_#t~ite38_Out2061772868| ~z~0_In2061772868) (or .cse2 .cse0)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In2061772868, ~z$w_buff1_used~0=~z$w_buff1_used~0_In2061772868, ~z$w_buff1~0=~z$w_buff1~0_In2061772868, ~z~0=~z~0_In2061772868} OutVars{~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In2061772868, ~z$w_buff1_used~0=~z$w_buff1_used~0_In2061772868, ~z$w_buff1~0=~z$w_buff1~0_In2061772868, ~z~0=~z~0_In2061772868, P2Thread1of1ForFork2_#t~ite39=|P2Thread1of1ForFork2_#t~ite39_Out2061772868|, P2Thread1of1ForFork2_#t~ite38=|P2Thread1of1ForFork2_#t~ite38_Out2061772868|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite39, P2Thread1of1ForFork2_#t~ite38] because there is no mapped edge [2019-12-07 18:00:41,558 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [818] [818] L801-->L801-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd3~0_In-2107717262 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In-2107717262 256)))) (or (and (not .cse0) (not .cse1) (= |P2Thread1of1ForFork2_#t~ite40_Out-2107717262| 0)) (and (= |P2Thread1of1ForFork2_#t~ite40_Out-2107717262| ~z$w_buff0_used~0_In-2107717262) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-2107717262, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-2107717262} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-2107717262, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-2107717262, P2Thread1of1ForFork2_#t~ite40=|P2Thread1of1ForFork2_#t~ite40_Out-2107717262|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite40] because there is no mapped edge [2019-12-07 18:00:41,559 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [821] [821] L802-->L802-2: Formula: (let ((.cse3 (= 0 (mod ~z$w_buff1_used~0_In-1110084360 256))) (.cse2 (= 0 (mod ~z$r_buff1_thd3~0_In-1110084360 256))) (.cse0 (= (mod ~z$w_buff0_used~0_In-1110084360 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In-1110084360 256)))) (or (and (= |P2Thread1of1ForFork2_#t~ite41_Out-1110084360| ~z$w_buff1_used~0_In-1110084360) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1))) (= |P2Thread1of1ForFork2_#t~ite41_Out-1110084360| 0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1110084360, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1110084360, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1110084360, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1110084360} OutVars{P2Thread1of1ForFork2_#t~ite41=|P2Thread1of1ForFork2_#t~ite41_Out-1110084360|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1110084360, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1110084360, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1110084360, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1110084360} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite41] because there is no mapped edge [2019-12-07 18:00:41,559 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [832] [832] L768-->L768-2: Formula: (let ((.cse2 (= (mod ~z$w_buff1_used~0_In1080248869 256) 0)) (.cse3 (= (mod ~z$r_buff1_thd2~0_In1080248869 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In1080248869 256))) (.cse0 (= (mod ~z$r_buff0_thd2~0_In1080248869 256) 0))) (or (and (= ~z$r_buff1_thd2~0_In1080248869 |P1Thread1of1ForFork1_#t~ite14_Out1080248869|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= 0 |P1Thread1of1ForFork1_#t~ite14_Out1080248869|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1080248869, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1080248869, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1080248869, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1080248869} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1080248869, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1080248869, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1080248869, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out1080248869|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1080248869} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 18:00:41,559 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [849] [849] L768-2-->P1EXIT: Formula: (and (= |v_P1Thread1of1ForFork1_#t~ite14_26| v_~z$r_buff1_thd2~0_70) (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= v_~__unbuffered_cnt~0_49 (+ v_~__unbuffered_cnt~0_50 1)) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_50, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_26|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_70, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_49, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_25|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~z$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 18:00:41,560 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [840] [840] L803-->L803-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd3~0_In-1358582275 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In-1358582275 256) 0))) (or (and (not .cse0) (= 0 |P2Thread1of1ForFork2_#t~ite42_Out-1358582275|) (not .cse1)) (and (or .cse0 .cse1) (= |P2Thread1of1ForFork2_#t~ite42_Out-1358582275| ~z$r_buff0_thd3~0_In-1358582275)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1358582275, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1358582275} OutVars{P2Thread1of1ForFork2_#t~ite42=|P2Thread1of1ForFork2_#t~ite42_Out-1358582275|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1358582275, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1358582275} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite42] because there is no mapped edge [2019-12-07 18:00:41,561 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [830] [830] L804-->L804-2: Formula: (let ((.cse2 (= 0 (mod ~z$r_buff1_thd3~0_In-1396203001 256))) (.cse3 (= (mod ~z$w_buff1_used~0_In-1396203001 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In-1396203001 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd3~0_In-1396203001 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork2_#t~ite43_Out-1396203001|)) (and (or .cse2 .cse3) (or .cse1 .cse0) (= ~z$r_buff1_thd3~0_In-1396203001 |P2Thread1of1ForFork2_#t~ite43_Out-1396203001|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1396203001, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1396203001, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1396203001, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1396203001} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1396203001, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1396203001, P2Thread1of1ForFork2_#t~ite43=|P2Thread1of1ForFork2_#t~ite43_Out-1396203001|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1396203001, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1396203001} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite43] because there is no mapped edge [2019-12-07 18:00:41,561 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [843] [843] L804-2-->P2EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_44 1) v_~__unbuffered_cnt~0_43) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= v_~z$r_buff1_thd3~0_119 |v_P2Thread1of1ForFork2_#t~ite43_26|)) InVars {P2Thread1of1ForFork2_#t~ite43=|v_P2Thread1of1ForFork2_#t~ite43_26|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_44} OutVars{~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_119, P2Thread1of1ForFork2_#t~ite43=|v_P2Thread1of1ForFork2_#t~ite43_25|, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_43, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[~z$r_buff1_thd3~0, P2Thread1of1ForFork2_#t~ite43, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 18:00:41,561 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [801] [801] L827-1-->L833: Formula: (and (= v_~main$tmp_guard0~0_9 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_34) 1 0)) 0 1)) (not (= 0 (mod v_~main$tmp_guard0~0_9 256)))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_34} OutVars{ULTIMATE.start_main_#t~nondet46=|v_ULTIMATE.start_main_#t~nondet46_8|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_34, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_9} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet46, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 18:00:41,562 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [837] [837] L833-2-->L833-5: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff1_thd0~0_In460971007 256))) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In460971007 256))) (.cse2 (= |ULTIMATE.start_main_#t~ite48_Out460971007| |ULTIMATE.start_main_#t~ite47_Out460971007|))) (or (and (= |ULTIMATE.start_main_#t~ite47_Out460971007| ~z~0_In460971007) (or .cse0 .cse1) .cse2) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite47_Out460971007| ~z$w_buff1~0_In460971007) (not .cse0) .cse2))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In460971007, ~z$w_buff1_used~0=~z$w_buff1_used~0_In460971007, ~z$w_buff1~0=~z$w_buff1~0_In460971007, ~z~0=~z~0_In460971007} OutVars{~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In460971007, ULTIMATE.start_main_#t~ite47=|ULTIMATE.start_main_#t~ite47_Out460971007|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In460971007, ~z$w_buff1~0=~z$w_buff1~0_In460971007, ULTIMATE.start_main_#t~ite48=|ULTIMATE.start_main_#t~ite48_Out460971007|, ~z~0=~z~0_In460971007} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 18:00:41,562 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [820] [820] L834-->L834-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In506336193 256))) (.cse0 (= (mod ~z$r_buff0_thd0~0_In506336193 256) 0))) (or (and (= ~z$w_buff0_used~0_In506336193 |ULTIMATE.start_main_#t~ite49_Out506336193|) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite49_Out506336193|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In506336193, ~z$w_buff0_used~0=~z$w_buff0_used~0_In506336193} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In506336193, ~z$w_buff0_used~0=~z$w_buff0_used~0_In506336193, ULTIMATE.start_main_#t~ite49=|ULTIMATE.start_main_#t~ite49_Out506336193|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite49] because there is no mapped edge [2019-12-07 18:00:41,563 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [825] [825] L835-->L835-2: Formula: (let ((.cse1 (= (mod ~z$r_buff1_thd0~0_In745139152 256) 0)) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In745139152 256))) (.cse2 (= (mod ~z$r_buff0_thd0~0_In745139152 256) 0)) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In745139152 256)))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite50_Out745139152| ~z$w_buff1_used~0_In745139152) (or .cse2 .cse3)) (and (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite50_Out745139152|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In745139152, ~z$w_buff0_used~0=~z$w_buff0_used~0_In745139152, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In745139152, ~z$w_buff1_used~0=~z$w_buff1_used~0_In745139152} OutVars{ULTIMATE.start_main_#t~ite50=|ULTIMATE.start_main_#t~ite50_Out745139152|, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In745139152, ~z$w_buff0_used~0=~z$w_buff0_used~0_In745139152, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In745139152, ~z$w_buff1_used~0=~z$w_buff1_used~0_In745139152} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite50] because there is no mapped edge [2019-12-07 18:00:41,563 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [824] [824] L836-->L836-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In-1529251070 256) 0)) (.cse0 (= (mod ~z$r_buff0_thd0~0_In-1529251070 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite51_Out-1529251070| ~z$r_buff0_thd0~0_In-1529251070)) (and (= |ULTIMATE.start_main_#t~ite51_Out-1529251070| 0) (not .cse1) (not .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1529251070, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1529251070} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1529251070, ULTIMATE.start_main_#t~ite51=|ULTIMATE.start_main_#t~ite51_Out-1529251070|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1529251070} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite51] because there is no mapped edge [2019-12-07 18:00:41,564 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [814] [814] L837-->L837-2: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd0~0_In932769995 256) 0)) (.cse1 (= (mod ~z$w_buff1_used~0_In932769995 256) 0)) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In932769995 256))) (.cse2 (= (mod ~z$r_buff0_thd0~0_In932769995 256) 0))) (or (and (= 0 |ULTIMATE.start_main_#t~ite52_Out932769995|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~z$r_buff1_thd0~0_In932769995 |ULTIMATE.start_main_#t~ite52_Out932769995|) (or .cse0 .cse1) (or .cse3 .cse2)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In932769995, ~z$w_buff0_used~0=~z$w_buff0_used~0_In932769995, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In932769995, ~z$w_buff1_used~0=~z$w_buff1_used~0_In932769995} OutVars{ULTIMATE.start_main_#t~ite52=|ULTIMATE.start_main_#t~ite52_Out932769995|, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In932769995, ~z$w_buff0_used~0=~z$w_buff0_used~0_In932769995, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In932769995, ~z$w_buff1_used~0=~z$w_buff1_used~0_In932769995} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52] because there is no mapped edge [2019-12-07 18:00:41,564 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [878] [878] L837-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_~main$tmp_guard1~0_27 (ite (= 0 (ite (not (and (= v_~y~0_37 2) (= 2 v_~__unbuffered_p2_EAX~0_30) (= v_~__unbuffered_p2_EBX~0_37 0) (= 2 v_~x~0_117))) 1 0)) 0 1)) (= v_ULTIMATE.start___VERIFIER_assert_~expression_16 0) (= v_ULTIMATE.start___VERIFIER_assert_~expression_16 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_12|) (= (mod v_~main$tmp_guard1~0_27 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_12|) (= v_~z$r_buff1_thd0~0_162 |v_ULTIMATE.start_main_#t~ite52_69|)) InVars {ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_69|, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_37, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_30, ~y~0=v_~y~0_37, ~x~0=v_~x~0_117} OutVars{ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_68|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_16, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_37, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_162, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_27, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_30, ~y~0=v_~y~0_37, ~x~0=v_~x~0_117, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_12|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start___VERIFIER_assert_~expression, ~z$r_buff1_thd0~0, ~main$tmp_guard1~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:00:41,623 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 06:00:41 BasicIcfg [2019-12-07 18:00:41,623 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 18:00:41,623 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 18:00:41,623 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 18:00:41,623 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 18:00:41,624 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 05:57:51" (3/4) ... [2019-12-07 18:00:41,626 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 18:00:41,626 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [893] [893] ULTIMATE.startENTRY-->L823: Formula: (let ((.cse0 (store |v_#valid_82| 0 0))) (and (= 0 v_~z$r_buff1_thd3~0_333) (= 0 v_~__unbuffered_cnt~0_79) (= v_~z~0_222 0) (= 0 v_~x~0_150) (= 0 v_~z$flush_delayed~0_66) (= v_~__unbuffered_p2_EBX~0_70 0) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t745~0.base_43|) (= (store .cse0 |v_ULTIMATE.start_main_~#t745~0.base_43| 1) |v_#valid_80|) (= v_~y~0_71 0) (= v_~z$read_delayed_var~0.base_8 0) (< 0 |v_#StackHeapBarrier_17|) (= v_~z$r_buff0_thd1~0_186 0) (= v_~z$w_buff1_used~0_670 0) (= (store |v_#memory_int_18| |v_ULTIMATE.start_main_~#t745~0.base_43| (store (select |v_#memory_int_18| |v_ULTIMATE.start_main_~#t745~0.base_43|) |v_ULTIMATE.start_main_~#t745~0.offset_29| 0)) |v_#memory_int_17|) (= (select .cse0 |v_ULTIMATE.start_main_~#t745~0.base_43|) 0) (= v_~z$r_buff0_thd2~0_110 0) (= 0 v_~weak$$choice0~0_29) (= v_~z$w_buff0~0_701 0) (= v_~z$r_buff1_thd0~0_201 0) (= v_~z$read_delayed~0_7 0) (= 0 v_~z$r_buff0_thd3~0_363) (= 0 v_~__unbuffered_p2_EAX~0_62) (= |v_#NULL.offset_5| 0) (= v_~z$mem_tmp~0_43 0) (= v_~z$r_buff0_thd0~0_137 0) (= v_~weak$$choice2~0_160 0) (= |v_#length_27| (store |v_#length_28| |v_ULTIMATE.start_main_~#t745~0.base_43| 4)) (= 0 |v_ULTIMATE.start_main_~#t745~0.offset_29|) (= v_~z$r_buff1_thd1~0_144 0) (= v_~z$r_buff1_thd2~0_165 0) (= v_~z$w_buff0_used~0_1072 0) (= v_~z$w_buff1~0_410 0) (= v_~main$tmp_guard0~0_24 0) (= v_~main$tmp_guard1~0_54 0) (= 0 |v_#NULL.base_5|) (= v_~z$read_delayed_var~0.offset_8 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_82|, #memory_int=|v_#memory_int_18|, #length=|v_#length_28|} OutVars{~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_165, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_46|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_202|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_46|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_120|, ~z$r_buff0_thd0~0=v_~z$r_buff0_thd0~0_137, ULTIMATE.start_main_~#t745~0.base=|v_ULTIMATE.start_main_~#t745~0.base_43|, #length=|v_#length_27|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_62, ~z$mem_tmp~0=v_~z$mem_tmp~0_43, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_70, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_10|, ULTIMATE.start_main_~#t747~0.base=|v_ULTIMATE.start_main_~#t747~0.base_29|, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_670, ULTIMATE.start_main_~#t746~0.offset=|v_ULTIMATE.start_main_~#t746~0.offset_22|, ~z$flush_delayed~0=v_~z$flush_delayed~0_66, ~weak$$choice0~0=v_~weak$$choice0~0_29, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_144, ULTIMATE.start_main_~#t747~0.offset=|v_ULTIMATE.start_main_~#t747~0.offset_21|, ~z$read_delayed_var~0.base=v_~z$read_delayed_var~0.base_8, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_363, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_79, ~x~0=v_~x~0_150, ~z$read_delayed~0=v_~z$read_delayed~0_7, ~z$w_buff1~0=v_~z$w_buff1~0_410, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_54, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_74|, ~z$read_delayed_var~0.offset=v_~z$read_delayed_var~0.offset_8, ULTIMATE.start_main_~#t746~0.base=|v_ULTIMATE.start_main_~#t746~0.base_37|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_34|, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_201, ~y~0=v_~y~0_71, ULTIMATE.start_main_~#t745~0.offset=|v_ULTIMATE.start_main_~#t745~0.offset_29|, ~z$r_buff0_thd2~0=v_~z$r_buff0_thd2~0_110, ULTIMATE.start_main_#t~nondet46=|v_ULTIMATE.start_main_#t~nondet46_26|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_1072, ~z$w_buff0~0=v_~z$w_buff0~0_701, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_10|, ~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_333, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_24, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_31|, #valid=|v_#valid_80|, #memory_int=|v_#memory_int_17|, ~z~0=v_~z~0_222, ~weak$$choice2~0=v_~weak$$choice2~0_160, ~z$r_buff0_thd1~0=v_~z$r_buff0_thd1~0_186} AuxVars[] AssignedVars[~z$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite47, ~z$read_delayed~0, #NULL.offset, ~z$w_buff1~0, ULTIMATE.start_main_#t~ite49, ~main$tmp_guard1~0, ULTIMATE.start_main_#t~ite48, ~z$read_delayed_var~0.offset, ULTIMATE.start_main_~#t746~0.base, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ~z$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite51, ULTIMATE.start_main_~#t745~0.base, ~z$r_buff1_thd0~0, #length, ~__unbuffered_p2_EAX~0, ~y~0, ULTIMATE.start_main_~#t745~0.offset, ~z$r_buff0_thd2~0, ~z$mem_tmp~0, ~__unbuffered_p2_EBX~0, ULTIMATE.start_main_#t~nondet46, ~z$w_buff0_used~0, ~z$w_buff0~0, ULTIMATE.start_main_#t~nondet44, ~z$r_buff1_thd3~0, ULTIMATE.start_main_#t~nondet45, ULTIMATE.start_main_~#t747~0.base, ~z$w_buff1_used~0, ULTIMATE.start_main_~#t746~0.offset, ~z$flush_delayed~0, ~main$tmp_guard0~0, #NULL.base, ~weak$$choice0~0, ULTIMATE.start_main_#res, ~z$r_buff1_thd1~0, #valid, ULTIMATE.start_main_~#t747~0.offset, #memory_int, ~z$read_delayed_var~0.base, ~z$r_buff0_thd3~0, ~__unbuffered_cnt~0, ~z~0, ~weak$$choice2~0, ~z$r_buff0_thd1~0, ~x~0] because there is no mapped edge [2019-12-07 18:00:41,627 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [865] [865] L823-1-->L825: Formula: (and (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t746~0.base_11| 4)) (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t746~0.base_11| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t746~0.base_11|) |v_ULTIMATE.start_main_~#t746~0.offset_10| 1)) |v_#memory_int_13|) (= |v_ULTIMATE.start_main_~#t746~0.offset_10| 0) (= 0 (select |v_#valid_34| |v_ULTIMATE.start_main_~#t746~0.base_11|)) (not (= |v_ULTIMATE.start_main_~#t746~0.base_11| 0)) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t746~0.base_11|) (= |v_#valid_33| (store |v_#valid_34| |v_ULTIMATE.start_main_~#t746~0.base_11| 1))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_14|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_#t~nondet44=|v_ULTIMATE.start_main_#t~nondet44_5|, #valid=|v_#valid_33|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_~#t746~0.offset=|v_ULTIMATE.start_main_~#t746~0.offset_10|, #length=|v_#length_17|, ULTIMATE.start_main_~#t746~0.base=|v_ULTIMATE.start_main_~#t746~0.base_11|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet44, #valid, #memory_int, ULTIMATE.start_main_~#t746~0.offset, #length, ULTIMATE.start_main_~#t746~0.base] because there is no mapped edge [2019-12-07 18:00:41,627 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [772] [772] P0ENTRY-->L4-3: Formula: (and (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_21 |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_19|) (= |v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_19| (ite (not (and (not (= (mod v_~z$w_buff0_used~0_174 256) 0)) (not (= (mod v_~z$w_buff1_used~0_104 256) 0)))) 1 0)) (= v_~z$w_buff0_used~0_174 1) (not (= v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_21 0)) (= v_~z$w_buff0~0_53 v_~z$w_buff1~0_38) (= v_~z$w_buff0_used~0_175 v_~z$w_buff1_used~0_104) (= v_P0Thread1of1ForFork0_~arg.offset_19 |v_P0Thread1of1ForFork0_#in~arg.offset_21|) (= v_P0Thread1of1ForFork0_~arg.base_19 |v_P0Thread1of1ForFork0_#in~arg.base_21|) (= 1 v_~z$w_buff0~0_52)) InVars {P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_21|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_175, ~z$w_buff0~0=v_~z$w_buff0~0_53, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_21|} OutVars{P0Thread1of1ForFork0_#in~arg.offset=|v_P0Thread1of1ForFork0_#in~arg.offset_21|, ~z$w_buff0_used~0=v_~z$w_buff0_used~0_174, ~z$w_buff0~0=v_~z$w_buff0~0_52, P0Thread1of1ForFork0___VERIFIER_assert_~expression=v_P0Thread1of1ForFork0___VERIFIER_assert_~expression_21, ~z$w_buff1_used~0=v_~z$w_buff1_used~0_104, P0Thread1of1ForFork0_#in~arg.base=|v_P0Thread1of1ForFork0_#in~arg.base_21|, ~z$w_buff1~0=v_~z$w_buff1~0_38, P0Thread1of1ForFork0_~arg.base=v_P0Thread1of1ForFork0_~arg.base_19, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression=|v_P0Thread1of1ForFork0___VERIFIER_assert_#in~expression_19|, P0Thread1of1ForFork0_~arg.offset=v_P0Thread1of1ForFork0_~arg.offset_19} AuxVars[] AssignedVars[~z$w_buff0_used~0, ~z$w_buff0~0, P0Thread1of1ForFork0___VERIFIER_assert_~expression, ~z$w_buff1_used~0, ~z$w_buff1~0, P0Thread1of1ForFork0_~arg.base, P0Thread1of1ForFork0___VERIFIER_assert_#in~expression, P0Thread1of1ForFork0_~arg.offset] because there is no mapped edge [2019-12-07 18:00:41,628 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [853] [853] L825-1-->L827: Formula: (and (= (store |v_#length_16| |v_ULTIMATE.start_main_~#t747~0.base_10| 4) |v_#length_15|) (= (store |v_#memory_int_12| |v_ULTIMATE.start_main_~#t747~0.base_10| (store (select |v_#memory_int_12| |v_ULTIMATE.start_main_~#t747~0.base_10|) |v_ULTIMATE.start_main_~#t747~0.offset_9| 2)) |v_#memory_int_11|) (< |v_#StackHeapBarrier_9| |v_ULTIMATE.start_main_~#t747~0.base_10|) (= |v_#valid_29| (store |v_#valid_30| |v_ULTIMATE.start_main_~#t747~0.base_10| 1)) (not (= |v_ULTIMATE.start_main_~#t747~0.base_10| 0)) (= (select |v_#valid_30| |v_ULTIMATE.start_main_~#t747~0.base_10|) 0) (= 0 |v_ULTIMATE.start_main_~#t747~0.offset_9|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_9|, #valid=|v_#valid_30|, #memory_int=|v_#memory_int_12|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_9|, ULTIMATE.start_main_~#t747~0.base=|v_ULTIMATE.start_main_~#t747~0.base_10|, #valid=|v_#valid_29|, ULTIMATE.start_main_#t~nondet45=|v_ULTIMATE.start_main_#t~nondet45_5|, #memory_int=|v_#memory_int_11|, ULTIMATE.start_main_~#t747~0.offset=|v_ULTIMATE.start_main_~#t747~0.offset_9|, #length=|v_#length_15|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t747~0.base, #valid, ULTIMATE.start_main_#t~nondet45, #memory_int, ULTIMATE.start_main_~#t747~0.offset, #length] because there is no mapped edge [2019-12-07 18:00:41,630 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [819] [819] L764-2-->L764-4: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff1_used~0_In141598029 256))) (.cse0 (= 0 (mod ~z$r_buff1_thd2~0_In141598029 256)))) (or (and (not .cse0) (not .cse1) (= ~z$w_buff1~0_In141598029 |P1Thread1of1ForFork1_#t~ite9_Out141598029|)) (and (= ~z~0_In141598029 |P1Thread1of1ForFork1_#t~ite9_Out141598029|) (or .cse1 .cse0)))) InVars {~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In141598029, ~z$w_buff1_used~0=~z$w_buff1_used~0_In141598029, ~z$w_buff1~0=~z$w_buff1~0_In141598029, ~z~0=~z~0_In141598029} OutVars{P1Thread1of1ForFork1_#t~ite9=|P1Thread1of1ForFork1_#t~ite9_Out141598029|, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In141598029, ~z$w_buff1_used~0=~z$w_buff1_used~0_In141598029, ~z$w_buff1~0=~z$w_buff1~0_In141598029, ~z~0=~z~0_In141598029} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9] because there is no mapped edge [2019-12-07 18:00:41,631 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [875] [875] L789-->L789-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In153953061 256)))) (or (and (= ~z$w_buff0~0_In153953061 |P2Thread1of1ForFork2_#t~ite21_Out153953061|) (= |P2Thread1of1ForFork2_#t~ite20_In153953061| |P2Thread1of1ForFork2_#t~ite20_Out153953061|) (not .cse0)) (and .cse0 (= |P2Thread1of1ForFork2_#t~ite21_Out153953061| |P2Thread1of1ForFork2_#t~ite20_Out153953061|) (let ((.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In153953061 256)))) (or (= 0 (mod ~z$w_buff0_used~0_In153953061 256)) (and (= 0 (mod ~z$w_buff1_used~0_In153953061 256)) .cse1) (and (= 0 (mod ~z$r_buff1_thd3~0_In153953061 256)) .cse1))) (= ~z$w_buff0~0_In153953061 |P2Thread1of1ForFork2_#t~ite20_Out153953061|)))) InVars {~z$w_buff0~0=~z$w_buff0~0_In153953061, ~z$w_buff0_used~0=~z$w_buff0_used~0_In153953061, P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_In153953061|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In153953061, ~z$w_buff1_used~0=~z$w_buff1_used~0_In153953061, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In153953061, ~weak$$choice2~0=~weak$$choice2~0_In153953061} OutVars{~z$w_buff0~0=~z$w_buff0~0_In153953061, P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out153953061|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In153953061, P2Thread1of1ForFork2_#t~ite21=|P2Thread1of1ForFork2_#t~ite21_Out153953061|, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In153953061, ~z$w_buff1_used~0=~z$w_buff1_used~0_In153953061, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In153953061, ~weak$$choice2~0=~weak$$choice2~0_In153953061} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, P2Thread1of1ForFork2_#t~ite21] because there is no mapped edge [2019-12-07 18:00:41,632 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [839] [839] L745-->L745-2: Formula: (let ((.cse0 (= 0 (mod ~z$w_buff0_used~0_In-1625098975 256))) (.cse1 (= (mod ~z$r_buff0_thd1~0_In-1625098975 256) 0))) (or (and (= 0 |P0Thread1of1ForFork0_#t~ite5_Out-1625098975|) (not .cse0) (not .cse1)) (and (or .cse0 .cse1) (= ~z$w_buff0_used~0_In-1625098975 |P0Thread1of1ForFork0_#t~ite5_Out-1625098975|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1625098975, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1625098975} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out-1625098975|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1625098975, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-1625098975} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 18:00:41,632 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [833] [833] L746-->L746-2: Formula: (let ((.cse3 (= (mod ~z$r_buff0_thd1~0_In332727980 256) 0)) (.cse2 (= 0 (mod ~z$w_buff0_used~0_In332727980 256))) (.cse0 (= (mod ~z$r_buff1_thd1~0_In332727980 256) 0)) (.cse1 (= (mod ~z$w_buff1_used~0_In332727980 256) 0))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P0Thread1of1ForFork0_#t~ite6_Out332727980| ~z$w_buff1_used~0_In332727980)) (and (= |P0Thread1of1ForFork0_#t~ite6_Out332727980| 0) (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1)))))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In332727980, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In332727980, ~z$w_buff1_used~0=~z$w_buff1_used~0_In332727980, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In332727980} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out332727980|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In332727980, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In332727980, ~z$w_buff1_used~0=~z$w_buff1_used~0_In332727980, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In332727980} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 18:00:41,633 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [838] [838] L747-->L748: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In2146788807 256))) (.cse2 (= ~z$r_buff0_thd1~0_Out2146788807 ~z$r_buff0_thd1~0_In2146788807)) (.cse0 (= 0 (mod ~z$r_buff0_thd1~0_In2146788807 256)))) (or (and (not .cse0) (not .cse1) (= ~z$r_buff0_thd1~0_Out2146788807 0)) (and .cse2 .cse1) (and .cse2 .cse0))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In2146788807, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In2146788807} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In2146788807, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out2146788807|, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_Out2146788807} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7, ~z$r_buff0_thd1~0] because there is no mapped edge [2019-12-07 18:00:41,633 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [828] [828] L748-->L748-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd1~0_In-540213841 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In-540213841 256) 0)) (.cse3 (= 0 (mod ~z$w_buff1_used~0_In-540213841 256))) (.cse2 (= 0 (mod ~z$r_buff1_thd1~0_In-540213841 256)))) (or (and (= |P0Thread1of1ForFork0_#t~ite8_Out-540213841| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (or .cse3 .cse2) (= |P0Thread1of1ForFork0_#t~ite8_Out-540213841| ~z$r_buff1_thd1~0_In-540213841)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-540213841, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-540213841, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-540213841, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-540213841} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-540213841, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out-540213841|, ~z$r_buff1_thd1~0=~z$r_buff1_thd1~0_In-540213841, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-540213841, ~z$r_buff0_thd1~0=~z$r_buff0_thd1~0_In-540213841} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 18:00:41,633 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [851] [851] L748-2-->P0EXIT: Formula: (and (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= v_~z$r_buff1_thd1~0_62 |v_P0Thread1of1ForFork0_#t~ite8_22|) (= (+ v_~__unbuffered_cnt~0_56 1) v_~__unbuffered_cnt~0_55) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_22|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_56} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_21|, ~z$r_buff1_thd1~0=v_~z$r_buff1_thd1~0_62, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, ~z$r_buff1_thd1~0, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0] because there is no mapped edge [2019-12-07 18:00:41,633 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [874] [874] L790-->L790-8: Formula: (let ((.cse1 (= (mod ~weak$$choice2~0_In-1958677726 256) 0))) (or (and (let ((.cse0 (= (mod ~z$r_buff0_thd3~0_In-1958677726 256) 0))) (or (and (= (mod ~z$w_buff1_used~0_In-1958677726 256) 0) .cse0) (and (= (mod ~z$r_buff1_thd3~0_In-1958677726 256) 0) .cse0) (= 0 (mod ~z$w_buff0_used~0_In-1958677726 256)))) (= ~z$w_buff1~0_In-1958677726 |P2Thread1of1ForFork2_#t~ite23_Out-1958677726|) .cse1 (= |P2Thread1of1ForFork2_#t~ite24_Out-1958677726| |P2Thread1of1ForFork2_#t~ite23_Out-1958677726|)) (and (= ~z$w_buff1~0_In-1958677726 |P2Thread1of1ForFork2_#t~ite24_Out-1958677726|) (= |P2Thread1of1ForFork2_#t~ite23_In-1958677726| |P2Thread1of1ForFork2_#t~ite23_Out-1958677726|) (not .cse1)))) InVars {P2Thread1of1ForFork2_#t~ite23=|P2Thread1of1ForFork2_#t~ite23_In-1958677726|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1958677726, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1958677726, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1958677726, ~z$w_buff1~0=~z$w_buff1~0_In-1958677726, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1958677726, ~weak$$choice2~0=~weak$$choice2~0_In-1958677726} OutVars{P2Thread1of1ForFork2_#t~ite23=|P2Thread1of1ForFork2_#t~ite23_Out-1958677726|, P2Thread1of1ForFork2_#t~ite24=|P2Thread1of1ForFork2_#t~ite24_Out-1958677726|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1958677726, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1958677726, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1958677726, ~z$w_buff1~0=~z$w_buff1~0_In-1958677726, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1958677726, ~weak$$choice2~0=~weak$$choice2~0_In-1958677726} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite23, P2Thread1of1ForFork2_#t~ite24] because there is no mapped edge [2019-12-07 18:00:41,634 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [873] [873] L791-->L791-8: Formula: (let ((.cse0 (= 0 (mod ~weak$$choice2~0_In2124289530 256)))) (or (and (= |P2Thread1of1ForFork2_#t~ite27_Out2124289530| ~z$w_buff0_used~0_In2124289530) (not .cse0) (= |P2Thread1of1ForFork2_#t~ite26_In2124289530| |P2Thread1of1ForFork2_#t~ite26_Out2124289530|)) (and (= |P2Thread1of1ForFork2_#t~ite26_Out2124289530| |P2Thread1of1ForFork2_#t~ite27_Out2124289530|) (let ((.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In2124289530 256)))) (or (and .cse1 (= (mod ~z$r_buff1_thd3~0_In2124289530 256) 0)) (and (= 0 (mod ~z$w_buff1_used~0_In2124289530 256)) .cse1) (= 0 (mod ~z$w_buff0_used~0_In2124289530 256)))) .cse0 (= |P2Thread1of1ForFork2_#t~ite26_Out2124289530| ~z$w_buff0_used~0_In2124289530)))) InVars {P2Thread1of1ForFork2_#t~ite26=|P2Thread1of1ForFork2_#t~ite26_In2124289530|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In2124289530, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In2124289530, ~z$w_buff1_used~0=~z$w_buff1_used~0_In2124289530, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In2124289530, ~weak$$choice2~0=~weak$$choice2~0_In2124289530} OutVars{P2Thread1of1ForFork2_#t~ite26=|P2Thread1of1ForFork2_#t~ite26_Out2124289530|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In2124289530, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In2124289530, ~z$w_buff1_used~0=~z$w_buff1_used~0_In2124289530, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In2124289530, ~weak$$choice2~0=~weak$$choice2~0_In2124289530, P2Thread1of1ForFork2_#t~ite27=|P2Thread1of1ForFork2_#t~ite27_Out2124289530|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite26, P2Thread1of1ForFork2_#t~ite27] because there is no mapped edge [2019-12-07 18:00:41,635 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [812] [812] L793-->L794: Formula: (and (not (= (mod v_~weak$$choice2~0_37 256) 0)) (= v_~z$r_buff0_thd3~0_119 v_~z$r_buff0_thd3~0_118)) InVars {~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_119, ~weak$$choice2~0=v_~weak$$choice2~0_37} OutVars{P2Thread1of1ForFork2_#t~ite31=|v_P2Thread1of1ForFork2_#t~ite31_6|, P2Thread1of1ForFork2_#t~ite33=|v_P2Thread1of1ForFork2_#t~ite33_6|, P2Thread1of1ForFork2_#t~ite32=|v_P2Thread1of1ForFork2_#t~ite32_7|, ~z$r_buff0_thd3~0=v_~z$r_buff0_thd3~0_118, ~weak$$choice2~0=v_~weak$$choice2~0_37} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite31, P2Thread1of1ForFork2_#t~ite33, P2Thread1of1ForFork2_#t~ite32, ~z$r_buff0_thd3~0] because there is no mapped edge [2019-12-07 18:00:41,635 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [750] [750] L764-4-->L765: Formula: (= |v_P1Thread1of1ForFork1_#t~ite9_6| v_~z~0_16) InVars {P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_6|} OutVars{P1Thread1of1ForFork1_#t~ite9=|v_P1Thread1of1ForFork1_#t~ite9_5|, P1Thread1of1ForFork1_#t~ite10=|v_P1Thread1of1ForFork1_#t~ite10_5|, ~z~0=v_~z~0_16} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite9, P1Thread1of1ForFork1_#t~ite10, ~z~0] because there is no mapped edge [2019-12-07 18:00:41,635 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [823] [823] L765-->L765-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In185604816 256) 0)) (.cse0 (= 0 (mod ~z$r_buff0_thd2~0_In185604816 256)))) (or (and (= ~z$w_buff0_used~0_In185604816 |P1Thread1of1ForFork1_#t~ite11_Out185604816|) (or .cse0 .cse1)) (and (= 0 |P1Thread1of1ForFork1_#t~ite11_Out185604816|) (not .cse1) (not .cse0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In185604816, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In185604816} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In185604816, P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out185604816|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In185604816} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 18:00:41,636 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [816] [816] L766-->L766-2: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd2~0_In-531084114 256) 0)) (.cse1 (= (mod ~z$w_buff1_used~0_In-531084114 256) 0)) (.cse3 (= (mod ~z$w_buff0_used~0_In-531084114 256) 0)) (.cse2 (= (mod ~z$r_buff0_thd2~0_In-531084114 256) 0))) (or (and (= |P1Thread1of1ForFork1_#t~ite12_Out-531084114| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (or .cse0 .cse1) (= ~z$w_buff1_used~0_In-531084114 |P1Thread1of1ForFork1_#t~ite12_Out-531084114|) (or .cse3 .cse2)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-531084114, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-531084114, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-531084114, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-531084114} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-531084114, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In-531084114, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-531084114, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out-531084114|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-531084114} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 18:00:41,637 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [817] [817] L767-->L767-2: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff0_thd2~0_In-2116334430 256))) (.cse0 (= 0 (mod ~z$w_buff0_used~0_In-2116334430 256)))) (or (and (not .cse0) (= 0 |P1Thread1of1ForFork1_#t~ite13_Out-2116334430|) (not .cse1)) (and (or .cse1 .cse0) (= ~z$r_buff0_thd2~0_In-2116334430 |P1Thread1of1ForFork1_#t~ite13_Out-2116334430|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-2116334430, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-2116334430} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-2116334430, P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out-2116334430|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In-2116334430} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13] because there is no mapped edge [2019-12-07 18:00:41,637 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [811] [811] L796-->L800: Formula: (and (= v_~z~0_64 v_~z$mem_tmp~0_7) (not (= 0 (mod v_~z$flush_delayed~0_10 256))) (= 0 v_~z$flush_delayed~0_9)) InVars {~z$mem_tmp~0=v_~z$mem_tmp~0_7, ~z$flush_delayed~0=v_~z$flush_delayed~0_10} OutVars{~z$mem_tmp~0=v_~z$mem_tmp~0_7, P2Thread1of1ForFork2_#t~ite37=|v_P2Thread1of1ForFork2_#t~ite37_5|, ~z$flush_delayed~0=v_~z$flush_delayed~0_9, ~z~0=v_~z~0_64} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite37, ~z$flush_delayed~0, ~z~0] because there is no mapped edge [2019-12-07 18:00:41,637 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [822] [822] L800-2-->L800-5: Formula: (let ((.cse1 (= |P2Thread1of1ForFork2_#t~ite38_Out2061772868| |P2Thread1of1ForFork2_#t~ite39_Out2061772868|)) (.cse2 (= (mod ~z$w_buff1_used~0_In2061772868 256) 0)) (.cse0 (= 0 (mod ~z$r_buff1_thd3~0_In2061772868 256)))) (or (and (not .cse0) .cse1 (not .cse2) (= |P2Thread1of1ForFork2_#t~ite38_Out2061772868| ~z$w_buff1~0_In2061772868)) (and .cse1 (= |P2Thread1of1ForFork2_#t~ite38_Out2061772868| ~z~0_In2061772868) (or .cse2 .cse0)))) InVars {~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In2061772868, ~z$w_buff1_used~0=~z$w_buff1_used~0_In2061772868, ~z$w_buff1~0=~z$w_buff1~0_In2061772868, ~z~0=~z~0_In2061772868} OutVars{~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In2061772868, ~z$w_buff1_used~0=~z$w_buff1_used~0_In2061772868, ~z$w_buff1~0=~z$w_buff1~0_In2061772868, ~z~0=~z~0_In2061772868, P2Thread1of1ForFork2_#t~ite39=|P2Thread1of1ForFork2_#t~ite39_Out2061772868|, P2Thread1of1ForFork2_#t~ite38=|P2Thread1of1ForFork2_#t~ite38_Out2061772868|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite39, P2Thread1of1ForFork2_#t~ite38] because there is no mapped edge [2019-12-07 18:00:41,638 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [818] [818] L801-->L801-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd3~0_In-2107717262 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In-2107717262 256)))) (or (and (not .cse0) (not .cse1) (= |P2Thread1of1ForFork2_#t~ite40_Out-2107717262| 0)) (and (= |P2Thread1of1ForFork2_#t~ite40_Out-2107717262| ~z$w_buff0_used~0_In-2107717262) (or .cse0 .cse1)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-2107717262, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-2107717262} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-2107717262, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-2107717262, P2Thread1of1ForFork2_#t~ite40=|P2Thread1of1ForFork2_#t~ite40_Out-2107717262|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite40] because there is no mapped edge [2019-12-07 18:00:41,638 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [821] [821] L802-->L802-2: Formula: (let ((.cse3 (= 0 (mod ~z$w_buff1_used~0_In-1110084360 256))) (.cse2 (= 0 (mod ~z$r_buff1_thd3~0_In-1110084360 256))) (.cse0 (= (mod ~z$w_buff0_used~0_In-1110084360 256) 0)) (.cse1 (= 0 (mod ~z$r_buff0_thd3~0_In-1110084360 256)))) (or (and (= |P2Thread1of1ForFork2_#t~ite41_Out-1110084360| ~z$w_buff1_used~0_In-1110084360) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse3) (not .cse2)) (and (not .cse0) (not .cse1))) (= |P2Thread1of1ForFork2_#t~ite41_Out-1110084360| 0)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1110084360, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1110084360, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1110084360, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1110084360} OutVars{P2Thread1of1ForFork2_#t~ite41=|P2Thread1of1ForFork2_#t~ite41_Out-1110084360|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1110084360, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1110084360, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1110084360, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1110084360} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite41] because there is no mapped edge [2019-12-07 18:00:41,639 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [832] [832] L768-->L768-2: Formula: (let ((.cse2 (= (mod ~z$w_buff1_used~0_In1080248869 256) 0)) (.cse3 (= (mod ~z$r_buff1_thd2~0_In1080248869 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In1080248869 256))) (.cse0 (= (mod ~z$r_buff0_thd2~0_In1080248869 256) 0))) (or (and (= ~z$r_buff1_thd2~0_In1080248869 |P1Thread1of1ForFork1_#t~ite14_Out1080248869|) (or .cse0 .cse1) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= 0 |P1Thread1of1ForFork1_#t~ite14_Out1080248869|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In1080248869, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1080248869, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1080248869, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1080248869} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In1080248869, ~z$r_buff1_thd2~0=~z$r_buff1_thd2~0_In1080248869, ~z$w_buff1_used~0=~z$w_buff1_used~0_In1080248869, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out1080248869|, ~z$r_buff0_thd2~0=~z$r_buff0_thd2~0_In1080248869} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 18:00:41,639 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [849] [849] L768-2-->P1EXIT: Formula: (and (= |v_P1Thread1of1ForFork1_#t~ite14_26| v_~z$r_buff1_thd2~0_70) (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= v_~__unbuffered_cnt~0_49 (+ v_~__unbuffered_cnt~0_50 1)) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_50, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_26|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~z$r_buff1_thd2~0=v_~z$r_buff1_thd2~0_70, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_49, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_25|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~z$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 18:00:41,640 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [840] [840] L803-->L803-2: Formula: (let ((.cse0 (= (mod ~z$r_buff0_thd3~0_In-1358582275 256) 0)) (.cse1 (= (mod ~z$w_buff0_used~0_In-1358582275 256) 0))) (or (and (not .cse0) (= 0 |P2Thread1of1ForFork2_#t~ite42_Out-1358582275|) (not .cse1)) (and (or .cse0 .cse1) (= |P2Thread1of1ForFork2_#t~ite42_Out-1358582275| ~z$r_buff0_thd3~0_In-1358582275)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1358582275, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1358582275} OutVars{P2Thread1of1ForFork2_#t~ite42=|P2Thread1of1ForFork2_#t~ite42_Out-1358582275|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1358582275, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1358582275} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite42] because there is no mapped edge [2019-12-07 18:00:41,640 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [830] [830] L804-->L804-2: Formula: (let ((.cse2 (= 0 (mod ~z$r_buff1_thd3~0_In-1396203001 256))) (.cse3 (= (mod ~z$w_buff1_used~0_In-1396203001 256) 0)) (.cse1 (= 0 (mod ~z$w_buff0_used~0_In-1396203001 256))) (.cse0 (= 0 (mod ~z$r_buff0_thd3~0_In-1396203001 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |P2Thread1of1ForFork2_#t~ite43_Out-1396203001|)) (and (or .cse2 .cse3) (or .cse1 .cse0) (= ~z$r_buff1_thd3~0_In-1396203001 |P2Thread1of1ForFork2_#t~ite43_Out-1396203001|)))) InVars {~z$w_buff0_used~0=~z$w_buff0_used~0_In-1396203001, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1396203001, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1396203001, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1396203001} OutVars{~z$w_buff0_used~0=~z$w_buff0_used~0_In-1396203001, ~z$r_buff1_thd3~0=~z$r_buff1_thd3~0_In-1396203001, P2Thread1of1ForFork2_#t~ite43=|P2Thread1of1ForFork2_#t~ite43_Out-1396203001|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In-1396203001, ~z$r_buff0_thd3~0=~z$r_buff0_thd3~0_In-1396203001} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite43] because there is no mapped edge [2019-12-07 18:00:41,641 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [843] [843] L804-2-->P2EXIT: Formula: (and (= (+ v_~__unbuffered_cnt~0_44 1) v_~__unbuffered_cnt~0_43) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= v_~z$r_buff1_thd3~0_119 |v_P2Thread1of1ForFork2_#t~ite43_26|)) InVars {P2Thread1of1ForFork2_#t~ite43=|v_P2Thread1of1ForFork2_#t~ite43_26|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_44} OutVars{~z$r_buff1_thd3~0=v_~z$r_buff1_thd3~0_119, P2Thread1of1ForFork2_#t~ite43=|v_P2Thread1of1ForFork2_#t~ite43_25|, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_43, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[~z$r_buff1_thd3~0, P2Thread1of1ForFork2_#t~ite43, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 18:00:41,641 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [801] [801] L827-1-->L833: Formula: (and (= v_~main$tmp_guard0~0_9 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_34) 1 0)) 0 1)) (not (= 0 (mod v_~main$tmp_guard0~0_9 256)))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_34} OutVars{ULTIMATE.start_main_#t~nondet46=|v_ULTIMATE.start_main_#t~nondet46_8|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_34, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_9} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet46, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 18:00:41,641 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [837] [837] L833-2-->L833-5: Formula: (let ((.cse1 (= 0 (mod ~z$r_buff1_thd0~0_In460971007 256))) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In460971007 256))) (.cse2 (= |ULTIMATE.start_main_#t~ite48_Out460971007| |ULTIMATE.start_main_#t~ite47_Out460971007|))) (or (and (= |ULTIMATE.start_main_#t~ite47_Out460971007| ~z~0_In460971007) (or .cse0 .cse1) .cse2) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite47_Out460971007| ~z$w_buff1~0_In460971007) (not .cse0) .cse2))) InVars {~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In460971007, ~z$w_buff1_used~0=~z$w_buff1_used~0_In460971007, ~z$w_buff1~0=~z$w_buff1~0_In460971007, ~z~0=~z~0_In460971007} OutVars{~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In460971007, ULTIMATE.start_main_#t~ite47=|ULTIMATE.start_main_#t~ite47_Out460971007|, ~z$w_buff1_used~0=~z$w_buff1_used~0_In460971007, ~z$w_buff1~0=~z$w_buff1~0_In460971007, ULTIMATE.start_main_#t~ite48=|ULTIMATE.start_main_#t~ite48_Out460971007|, ~z~0=~z~0_In460971007} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 18:00:41,642 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [820] [820] L834-->L834-2: Formula: (let ((.cse1 (= 0 (mod ~z$w_buff0_used~0_In506336193 256))) (.cse0 (= (mod ~z$r_buff0_thd0~0_In506336193 256) 0))) (or (and (= ~z$w_buff0_used~0_In506336193 |ULTIMATE.start_main_#t~ite49_Out506336193|) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= 0 |ULTIMATE.start_main_#t~ite49_Out506336193|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In506336193, ~z$w_buff0_used~0=~z$w_buff0_used~0_In506336193} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In506336193, ~z$w_buff0_used~0=~z$w_buff0_used~0_In506336193, ULTIMATE.start_main_#t~ite49=|ULTIMATE.start_main_#t~ite49_Out506336193|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite49] because there is no mapped edge [2019-12-07 18:00:41,643 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [825] [825] L835-->L835-2: Formula: (let ((.cse1 (= (mod ~z$r_buff1_thd0~0_In745139152 256) 0)) (.cse0 (= 0 (mod ~z$w_buff1_used~0_In745139152 256))) (.cse2 (= (mod ~z$r_buff0_thd0~0_In745139152 256) 0)) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In745139152 256)))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite50_Out745139152| ~z$w_buff1_used~0_In745139152) (or .cse2 .cse3)) (and (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite50_Out745139152|)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In745139152, ~z$w_buff0_used~0=~z$w_buff0_used~0_In745139152, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In745139152, ~z$w_buff1_used~0=~z$w_buff1_used~0_In745139152} OutVars{ULTIMATE.start_main_#t~ite50=|ULTIMATE.start_main_#t~ite50_Out745139152|, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In745139152, ~z$w_buff0_used~0=~z$w_buff0_used~0_In745139152, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In745139152, ~z$w_buff1_used~0=~z$w_buff1_used~0_In745139152} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite50] because there is no mapped edge [2019-12-07 18:00:41,643 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [824] [824] L836-->L836-2: Formula: (let ((.cse1 (= (mod ~z$w_buff0_used~0_In-1529251070 256) 0)) (.cse0 (= (mod ~z$r_buff0_thd0~0_In-1529251070 256) 0))) (or (and (or .cse0 .cse1) (= |ULTIMATE.start_main_#t~ite51_Out-1529251070| ~z$r_buff0_thd0~0_In-1529251070)) (and (= |ULTIMATE.start_main_#t~ite51_Out-1529251070| 0) (not .cse1) (not .cse0)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1529251070, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1529251070} OutVars{~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In-1529251070, ULTIMATE.start_main_#t~ite51=|ULTIMATE.start_main_#t~ite51_Out-1529251070|, ~z$w_buff0_used~0=~z$w_buff0_used~0_In-1529251070} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite51] because there is no mapped edge [2019-12-07 18:00:41,644 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [814] [814] L837-->L837-2: Formula: (let ((.cse0 (= (mod ~z$r_buff1_thd0~0_In932769995 256) 0)) (.cse1 (= (mod ~z$w_buff1_used~0_In932769995 256) 0)) (.cse3 (= 0 (mod ~z$w_buff0_used~0_In932769995 256))) (.cse2 (= (mod ~z$r_buff0_thd0~0_In932769995 256) 0))) (or (and (= 0 |ULTIMATE.start_main_#t~ite52_Out932769995|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= ~z$r_buff1_thd0~0_In932769995 |ULTIMATE.start_main_#t~ite52_Out932769995|) (or .cse0 .cse1) (or .cse3 .cse2)))) InVars {~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In932769995, ~z$w_buff0_used~0=~z$w_buff0_used~0_In932769995, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In932769995, ~z$w_buff1_used~0=~z$w_buff1_used~0_In932769995} OutVars{ULTIMATE.start_main_#t~ite52=|ULTIMATE.start_main_#t~ite52_Out932769995|, ~z$r_buff0_thd0~0=~z$r_buff0_thd0~0_In932769995, ~z$w_buff0_used~0=~z$w_buff0_used~0_In932769995, ~z$r_buff1_thd0~0=~z$r_buff1_thd0~0_In932769995, ~z$w_buff1_used~0=~z$w_buff1_used~0_In932769995} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52] because there is no mapped edge [2019-12-07 18:00:41,644 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [878] [878] L837-2-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_~main$tmp_guard1~0_27 (ite (= 0 (ite (not (and (= v_~y~0_37 2) (= 2 v_~__unbuffered_p2_EAX~0_30) (= v_~__unbuffered_p2_EBX~0_37 0) (= 2 v_~x~0_117))) 1 0)) 0 1)) (= v_ULTIMATE.start___VERIFIER_assert_~expression_16 0) (= v_ULTIMATE.start___VERIFIER_assert_~expression_16 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_12|) (= (mod v_~main$tmp_guard1~0_27 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_12|) (= v_~z$r_buff1_thd0~0_162 |v_ULTIMATE.start_main_#t~ite52_69|)) InVars {ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_69|, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_37, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_30, ~y~0=v_~y~0_37, ~x~0=v_~x~0_117} OutVars{ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_68|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_16, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_37, ~z$r_buff1_thd0~0=v_~z$r_buff1_thd0~0_162, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_27, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_30, ~y~0=v_~y~0_37, ~x~0=v_~x~0_117, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_12|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start___VERIFIER_assert_~expression, ~z$r_buff1_thd0~0, ~main$tmp_guard1~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:00:41,714 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_98bf8e3e-5cb9-4779-8088-2a499a538fd8/bin/uautomizer/witness.graphml [2019-12-07 18:00:41,714 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 18:00:41,715 INFO L168 Benchmark]: Toolchain (without parser) took 171514.01 ms. Allocated memory was 1.0 GB in the beginning and 6.9 GB in the end (delta: 5.8 GB). Free memory was 938.2 MB in the beginning and 1.9 GB in the end (delta: -912.4 MB). Peak memory consumption was 4.9 GB. Max. memory is 11.5 GB. [2019-12-07 18:00:41,716 INFO L168 Benchmark]: CDTParser took 0.22 ms. Allocated memory is still 1.0 GB. Free memory is still 958.7 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:00:41,716 INFO L168 Benchmark]: CACSL2BoogieTranslator took 383.12 ms. Allocated memory is still 1.0 GB. Free memory was 938.2 MB in the beginning and 979.1 MB in the end (delta: -40.9 MB). Peak memory consumption was 17.9 MB. Max. memory is 11.5 GB. [2019-12-07 18:00:41,716 INFO L168 Benchmark]: Boogie Procedure Inliner took 38.69 ms. Allocated memory is still 1.0 GB. Free memory was 979.1 MB in the beginning and 973.7 MB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 18:00:41,716 INFO L168 Benchmark]: Boogie Preprocessor took 26.41 ms. Allocated memory is still 1.0 GB. Free memory is still 973.7 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:00:41,717 INFO L168 Benchmark]: RCFGBuilder took 405.75 ms. Allocated memory is still 1.0 GB. Free memory was 973.7 MB in the beginning and 919.1 MB in the end (delta: 54.6 MB). Peak memory consumption was 54.6 MB. Max. memory is 11.5 GB. [2019-12-07 18:00:41,717 INFO L168 Benchmark]: TraceAbstraction took 170565.21 ms. Allocated memory was 1.0 GB in the beginning and 6.9 GB in the end (delta: 5.8 GB). Free memory was 919.1 MB in the beginning and 1.9 GB in the end (delta: -1.0 GB). Peak memory consumption was 4.8 GB. Max. memory is 11.5 GB. [2019-12-07 18:00:41,717 INFO L168 Benchmark]: Witness Printer took 91.21 ms. Allocated memory is still 6.9 GB. Free memory was 1.9 GB in the beginning and 1.9 GB in the end (delta: 86.4 MB). Peak memory consumption was 86.4 MB. Max. memory is 11.5 GB. [2019-12-07 18:00:41,719 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.22 ms. Allocated memory is still 1.0 GB. Free memory is still 958.7 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 383.12 ms. Allocated memory is still 1.0 GB. Free memory was 938.2 MB in the beginning and 979.1 MB in the end (delta: -40.9 MB). Peak memory consumption was 17.9 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 38.69 ms. Allocated memory is still 1.0 GB. Free memory was 979.1 MB in the beginning and 973.7 MB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 26.41 ms. Allocated memory is still 1.0 GB. Free memory is still 973.7 MB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 405.75 ms. Allocated memory is still 1.0 GB. Free memory was 973.7 MB in the beginning and 919.1 MB in the end (delta: 54.6 MB). Peak memory consumption was 54.6 MB. Max. memory is 11.5 GB. * TraceAbstraction took 170565.21 ms. Allocated memory was 1.0 GB in the beginning and 6.9 GB in the end (delta: 5.8 GB). Free memory was 919.1 MB in the beginning and 1.9 GB in the end (delta: -1.0 GB). Peak memory consumption was 4.8 GB. Max. memory is 11.5 GB. * Witness Printer took 91.21 ms. Allocated memory is still 6.9 GB. Free memory was 1.9 GB in the beginning and 1.9 GB in the end (delta: 86.4 MB). Peak memory consumption was 86.4 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 3.6s, 175 ProgramPointsBefore, 93 ProgramPointsAfterwards, 212 TransitionsBefore, 102 TransitionsAfterwards, 19004 CoEnabledTransitionPairs, 8 FixpointIterations, 32 TrivialSequentialCompositions, 49 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 32 ConcurrentYvCompositions, 32 ChoiceCompositions, 6798 VarBasedMoverChecksPositive, 289 VarBasedMoverChecksNegative, 75 SemBasedMoverChecksPositive, 285 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 1.2s, 0 MoverChecksTotal, 87070 CheckedPairsTotal, 113 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L823] FCALL, FORK 0 pthread_create(&t745, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L734] 1 z$r_buff1_thd0 = z$r_buff0_thd0 [L735] 1 z$r_buff1_thd1 = z$r_buff0_thd1 [L736] 1 z$r_buff1_thd2 = z$r_buff0_thd2 [L737] 1 z$r_buff1_thd3 = z$r_buff0_thd3 [L738] 1 z$r_buff0_thd1 = (_Bool)1 [L741] 1 x = 1 VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L744] EXPR 1 z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L825] FCALL, FORK 0 pthread_create(&t746, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L827] FCALL, FORK 0 pthread_create(&t747, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, y=0, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L758] 2 x = 2 [L761] 2 y = 1 VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L764] 2 z$w_buff0_used && z$r_buff0_thd2 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, y=1, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L778] 3 y = 2 [L781] 3 __unbuffered_p2_EAX = y [L784] 3 weak$$choice0 = __VERIFIER_nondet_bool() [L785] 3 weak$$choice2 = __VERIFIER_nondet_bool() [L786] 3 z$flush_delayed = weak$$choice2 [L787] 3 z$mem_tmp = z VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=7, x=2, y=2, z=0, z$flush_delayed=7, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0] [L788] EXPR 3 !z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff1) VAL [!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff1)=0, __unbuffered_cnt=0, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=7, x=2, y=2, z=0, z$flush_delayed=7, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=1, z$w_buff1=0, z$w_buff1_used=0, z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z=0] [L788] 3 z = !z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff1) [L744] 1 z = z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd1 ? z$w_buff1 : z) [L745] 1 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$w_buff0_used [L746] 1 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd1 || z$w_buff1_used && z$r_buff1_thd1 ? (_Bool)0 : z$w_buff1_used [L789] 3 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : z$w_buff0)) [L790] 3 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff1 : z$w_buff1)) [L791] 3 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used)) [L792] EXPR 3 weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=1, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=7, weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0))=0, x=2, y=2, z=1, z$flush_delayed=7, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0, z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z=0] [L792] 3 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) [L794] EXPR 3 weak$$choice2 ? z$r_buff1_thd3 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$r_buff1_thd3 : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=1, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=7, weak$$choice2 ? z$r_buff1_thd3 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$r_buff1_thd3 : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0))=0, x=2, y=2, z=1, z$flush_delayed=7, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0, z$w_buff1_used && z$r_buff1_thd2 ? z$w_buff1 : z=0] [L765] 2 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$w_buff0_used [L794] 3 z$r_buff1_thd3 = weak$$choice2 ? z$r_buff1_thd3 : (!z$w_buff0_used || !z$r_buff0_thd3 && !z$w_buff1_used || !z$r_buff0_thd3 && !z$r_buff1_thd3 ? z$r_buff1_thd3 : (z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : (_Bool)0)) [L795] 3 __unbuffered_p2_EBX = z VAL [__unbuffered_cnt=1, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=7, x=2, y=2, z=0, z$flush_delayed=7, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$w_buff1_used=0, z$w_buff1=0, z$w_buff1_used=0] [L766] 2 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd2 || z$w_buff1_used && z$r_buff1_thd2 ? (_Bool)0 : z$w_buff1_used [L800] EXPR 3 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [__unbuffered_cnt=1, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=7, x=2, y=2, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2=0, z$w_buff1=0, z$w_buff1_used=0] [L800] 3 z = z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) [L801] 3 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used [L767] 2 z$r_buff0_thd2 = z$w_buff0_used && z$r_buff0_thd2 ? (_Bool)0 : z$r_buff0_thd2 [L802] 3 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used [L803] 3 z$r_buff0_thd3 = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 [L833] EXPR 0 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=9, weak$$choice2=7, x=2, y=2, z=0, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=1, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=1, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L833] 0 z = z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) [L834] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L835] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L836] 0 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 166 locations, 2 error locations. Result: UNSAFE, OverallTime: 170.4s, OverallIterations: 46, TraceHistogramMax: 1, AutomataDifference: 105.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 13233 SDtfs, 20139 SDslu, 59447 SDs, 0 SdLazy, 87210 SolverSat, 1678 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 60.2s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1401 GetRequests, 101 SyntacticMatches, 57 SemanticMatches, 1243 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19440 ImplicationChecksByTransitivity, 32.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=151934occurred in iteration=2, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 33.4s AutomataMinimizationTime, 45 MinimizatonAttempts, 521502 StatesRemovedByMinimization, 43 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.5s SatisfiabilityAnalysisTime, 10.7s InterpolantComputationTime, 2311 NumberOfCodeBlocks, 2311 NumberOfCodeBlocksAsserted, 46 NumberOfCheckSat, 2199 ConstructedInterpolants, 0 QuantifiedInterpolants, 1071004 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 45 InterpolantComputations, 45 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...