./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread-wmm/mix028_power.opt.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version f470102c Calling Ultimate with: /usr/lib/jvm/java-8-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/run_dir_c6caa1d2-8da2-49a6-9013-ef55de0dbf83/bin/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/run_dir_c6caa1d2-8da2-49a6-9013-ef55de0dbf83/bin/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/run_dir_c6caa1d2-8da2-49a6-9013-ef55de0dbf83/bin/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/run_dir_c6caa1d2-8da2-49a6-9013-ef55de0dbf83/bin/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread-wmm/mix028_power.opt.i -s /tmp/vcloud-vcloud-master/worker/run_dir_c6caa1d2-8da2-49a6-9013-ef55de0dbf83/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/run_dir_c6caa1d2-8da2-49a6-9013-ef55de0dbf83/bin/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bf799c5afc786bc4b4e202f948a826ac4f2d002c ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.25-f470102 [2019-12-07 18:55:03,751 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-07 18:55:03,753 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-07 18:55:03,762 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-07 18:55:03,762 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-07 18:55:03,763 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-07 18:55:03,764 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-07 18:55:03,765 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-07 18:55:03,767 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-07 18:55:03,767 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-07 18:55:03,768 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-07 18:55:03,769 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-07 18:55:03,769 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-07 18:55:03,769 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-07 18:55:03,770 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-07 18:55:03,771 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-07 18:55:03,772 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-07 18:55:03,772 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-07 18:55:03,774 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-07 18:55:03,775 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-07 18:55:03,776 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-07 18:55:03,777 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-07 18:55:03,778 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-07 18:55:03,778 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-07 18:55:03,780 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-12-07 18:55:03,780 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-12-07 18:55:03,780 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-12-07 18:55:03,781 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2019-12-07 18:55:03,781 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-12-07 18:55:03,782 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2019-12-07 18:55:03,782 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-07 18:55:03,782 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-07 18:55:03,783 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-07 18:55:03,783 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-07 18:55:03,784 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-07 18:55:03,784 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-07 18:55:03,785 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-07 18:55:03,785 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-07 18:55:03,785 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-07 18:55:03,786 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-07 18:55:03,787 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-07 18:55:03,787 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/run_dir_c6caa1d2-8da2-49a6-9013-ef55de0dbf83/bin/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2019-12-07 18:55:03,800 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-07 18:55:03,800 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-07 18:55:03,801 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-07 18:55:03,801 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-07 18:55:03,801 INFO L138 SettingsManager]: * Use SBE=true [2019-12-07 18:55:03,801 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-07 18:55:03,802 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-07 18:55:03,802 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-07 18:55:03,802 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-07 18:55:03,802 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-07 18:55:03,802 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-07 18:55:03,803 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-07 18:55:03,803 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-07 18:55:03,803 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-07 18:55:03,803 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-07 18:55:03,803 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-07 18:55:03,803 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-07 18:55:03,804 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-07 18:55:03,804 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-07 18:55:03,804 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-07 18:55:03,804 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-07 18:55:03,804 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:55:03,805 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-07 18:55:03,805 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-07 18:55:03,805 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-07 18:55:03,805 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-07 18:55:03,805 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-07 18:55:03,805 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-07 18:55:03,806 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2019-12-07 18:55:03,806 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/run_dir_c6caa1d2-8da2-49a6-9013-ef55de0dbf83/bin/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bf799c5afc786bc4b4e202f948a826ac4f2d002c [2019-12-07 18:55:03,908 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-07 18:55:03,916 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-07 18:55:03,918 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-07 18:55:03,919 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-07 18:55:03,920 INFO L275 PluginConnector]: CDTParser initialized [2019-12-07 18:55:03,920 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/run_dir_c6caa1d2-8da2-49a6-9013-ef55de0dbf83/bin/uautomizer/../../sv-benchmarks/c/pthread-wmm/mix028_power.opt.i [2019-12-07 18:55:03,957 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_c6caa1d2-8da2-49a6-9013-ef55de0dbf83/bin/uautomizer/data/d3adbe318/2db0b734bd774e9dbe739eb9c0559c3e/FLAG52e2d83ab [2019-12-07 18:55:04,483 INFO L306 CDTParser]: Found 1 translation units. [2019-12-07 18:55:04,484 INFO L160 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/run_dir_c6caa1d2-8da2-49a6-9013-ef55de0dbf83/sv-benchmarks/c/pthread-wmm/mix028_power.opt.i [2019-12-07 18:55:04,497 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/run_dir_c6caa1d2-8da2-49a6-9013-ef55de0dbf83/bin/uautomizer/data/d3adbe318/2db0b734bd774e9dbe739eb9c0559c3e/FLAG52e2d83ab [2019-12-07 18:55:04,991 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/run_dir_c6caa1d2-8da2-49a6-9013-ef55de0dbf83/bin/uautomizer/data/d3adbe318/2db0b734bd774e9dbe739eb9c0559c3e [2019-12-07 18:55:04,993 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-07 18:55:04,994 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2019-12-07 18:55:04,995 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-07 18:55:04,995 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-07 18:55:04,998 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-07 18:55:04,999 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:55:04" (1/1) ... [2019-12-07 18:55:05,001 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7b6fc423 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:55:04, skipping insertion in model container [2019-12-07 18:55:05,001 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 06:55:04" (1/1) ... [2019-12-07 18:55:05,007 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-07 18:55:05,041 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-07 18:55:05,309 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:55:05,316 INFO L203 MainTranslator]: Completed pre-run [2019-12-07 18:55:05,356 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-07 18:55:05,400 INFO L208 MainTranslator]: Completed translation [2019-12-07 18:55:05,401 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:55:05 WrapperNode [2019-12-07 18:55:05,401 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-07 18:55:05,401 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-07 18:55:05,401 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-07 18:55:05,401 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-07 18:55:05,407 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:55:05" (1/1) ... [2019-12-07 18:55:05,419 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:55:05" (1/1) ... [2019-12-07 18:55:05,440 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-07 18:55:05,440 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-07 18:55:05,441 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-07 18:55:05,441 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-07 18:55:05,447 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:55:05" (1/1) ... [2019-12-07 18:55:05,447 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:55:05" (1/1) ... [2019-12-07 18:55:05,451 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:55:05" (1/1) ... [2019-12-07 18:55:05,451 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:55:05" (1/1) ... [2019-12-07 18:55:05,458 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:55:05" (1/1) ... [2019-12-07 18:55:05,461 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:55:05" (1/1) ... [2019-12-07 18:55:05,463 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:55:05" (1/1) ... [2019-12-07 18:55:05,466 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-07 18:55:05,467 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-07 18:55:05,467 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-07 18:55:05,467 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-07 18:55:05,467 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:55:05" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/run_dir_c6caa1d2-8da2-49a6-9013-ef55de0dbf83/bin/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-07 18:55:05,507 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-07 18:55:05,507 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-07 18:55:05,507 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-07 18:55:05,507 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-07 18:55:05,507 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-07 18:55:05,507 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-07 18:55:05,507 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-07 18:55:05,507 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-07 18:55:05,507 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-07 18:55:05,508 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-07 18:55:05,508 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-07 18:55:05,508 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-07 18:55:05,508 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-07 18:55:05,509 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-07 18:55:05,874 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-07 18:55:05,874 INFO L287 CfgBuilder]: Removed 8 assume(true) statements. [2019-12-07 18:55:05,875 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:55:05 BoogieIcfgContainer [2019-12-07 18:55:05,875 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-07 18:55:05,876 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-07 18:55:05,876 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-07 18:55:05,878 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-07 18:55:05,878 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.12 06:55:04" (1/3) ... [2019-12-07 18:55:05,879 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@8251976 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:55:05, skipping insertion in model container [2019-12-07 18:55:05,879 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 06:55:05" (2/3) ... [2019-12-07 18:55:05,879 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@8251976 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.12 06:55:05, skipping insertion in model container [2019-12-07 18:55:05,880 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:55:05" (3/3) ... [2019-12-07 18:55:05,881 INFO L109 eAbstractionObserver]: Analyzing ICFG mix028_power.opt.i [2019-12-07 18:55:05,887 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-07 18:55:05,887 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-07 18:55:05,893 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2019-12-07 18:55:05,894 INFO L339 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-07 18:55:05,921 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,921 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,921 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,921 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,921 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,921 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,922 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,922 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,922 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,922 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,922 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,922 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,922 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,922 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,923 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,923 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,923 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,923 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,923 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,923 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,923 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,923 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,924 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,924 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,924 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,924 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,924 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,924 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,924 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,925 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,925 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,925 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,926 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,926 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,926 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1___VERIFIER_assert_#in~expression| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,926 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,926 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,927 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork1___VERIFIER_assert_~expression not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,927 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,927 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,927 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,927 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,928 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,928 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,928 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,928 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,928 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,928 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,928 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,929 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,929 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,929 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,929 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,929 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,929 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,929 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,929 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,929 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,930 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,930 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,930 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,930 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,930 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,930 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,931 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,931 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,931 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,931 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,931 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,931 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,931 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,932 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,932 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,932 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,932 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,932 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,932 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,933 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,933 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,933 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,933 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,933 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,933 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,933 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,934 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,934 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,934 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,934 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,934 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,934 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,934 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,935 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,935 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,935 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-07 18:55:05,946 INFO L249 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-12-07 18:55:05,958 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-07 18:55:05,958 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-07 18:55:05,958 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-07 18:55:05,959 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-12-07 18:55:05,959 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-07 18:55:05,959 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-07 18:55:05,959 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-07 18:55:05,959 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-07 18:55:05,971 INFO L152 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 175 places, 212 transitions [2019-12-07 18:55:05,973 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 175 places, 212 transitions [2019-12-07 18:55:06,033 INFO L134 PetriNetUnfolder]: 47/209 cut-off events. [2019-12-07 18:55:06,033 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:55:06,044 INFO L76 FinitePrefix]: Finished finitePrefix Result has 219 conditions, 209 events. 47/209 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 577 event pairs. 9/169 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 18:55:06,058 INFO L68 FinitePrefix]: Start finitePrefix. Operand has 175 places, 212 transitions [2019-12-07 18:55:06,086 INFO L134 PetriNetUnfolder]: 47/209 cut-off events. [2019-12-07 18:55:06,086 INFO L135 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2019-12-07 18:55:06,092 INFO L76 FinitePrefix]: Finished finitePrefix Result has 219 conditions, 209 events. 47/209 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 10. Compared 577 event pairs. 9/169 useless extension candidates. Maximal degree in co-relation 179. Up to 2 conditions per place. [2019-12-07 18:55:06,108 INFO L158 etLargeBlockEncoding]: Number of co-enabled transitions 17074 [2019-12-07 18:55:06,109 INFO L170 etLargeBlockEncoding]: Semantic Check. [2019-12-07 18:55:08,816 WARN L192 SmtUtils]: Spent 138.00 ms on a formula simplification. DAG size of input: 89 DAG size of output: 87 [2019-12-07 18:55:08,905 INFO L206 etLargeBlockEncoding]: Checked pairs total: 79058 [2019-12-07 18:55:08,905 INFO L214 etLargeBlockEncoding]: Total number of compositions: 111 [2019-12-07 18:55:08,907 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 95 places, 107 transitions [2019-12-07 18:55:23,953 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 115078 states. [2019-12-07 18:55:23,954 INFO L276 IsEmpty]: Start isEmpty. Operand 115078 states. [2019-12-07 18:55:23,959 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-12-07 18:55:23,959 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:23,960 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-12-07 18:55:23,960 INFO L410 AbstractCegarLoop]: === Iteration 1 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:23,964 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:23,964 INFO L82 PathProgramCache]: Analyzing trace with hash 811621075, now seen corresponding path program 1 times [2019-12-07 18:55:23,969 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:23,969 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1553695948] [2019-12-07 18:55:23,970 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:24,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:24,114 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:24,114 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1553695948] [2019-12-07 18:55:24,115 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:24,115 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-12-07 18:55:24,115 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [886734220] [2019-12-07 18:55:24,118 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:55:24,118 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:24,127 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:55:24,128 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:55:24,129 INFO L87 Difference]: Start difference. First operand 115078 states. Second operand 3 states. [2019-12-07 18:55:24,868 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:24,868 INFO L93 Difference]: Finished difference Result 114778 states and 493920 transitions. [2019-12-07 18:55:24,869 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:55:24,870 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 5 [2019-12-07 18:55:24,870 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:25,587 INFO L225 Difference]: With dead ends: 114778 [2019-12-07 18:55:25,587 INFO L226 Difference]: Without dead ends: 112412 [2019-12-07 18:55:25,588 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:55:30,821 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112412 states. [2019-12-07 18:55:32,396 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112412 to 112412. [2019-12-07 18:55:32,397 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112412 states. [2019-12-07 18:55:32,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112412 states to 112412 states and 484274 transitions. [2019-12-07 18:55:32,766 INFO L78 Accepts]: Start accepts. Automaton has 112412 states and 484274 transitions. Word has length 5 [2019-12-07 18:55:32,766 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:32,767 INFO L462 AbstractCegarLoop]: Abstraction has 112412 states and 484274 transitions. [2019-12-07 18:55:32,767 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:55:32,767 INFO L276 IsEmpty]: Start isEmpty. Operand 112412 states and 484274 transitions. [2019-12-07 18:55:32,769 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2019-12-07 18:55:32,769 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:32,769 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:32,769 INFO L410 AbstractCegarLoop]: === Iteration 2 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:32,769 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:32,770 INFO L82 PathProgramCache]: Analyzing trace with hash -287251583, now seen corresponding path program 1 times [2019-12-07 18:55:32,770 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:32,770 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1478885749] [2019-12-07 18:55:32,770 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:32,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:32,824 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:32,824 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1478885749] [2019-12-07 18:55:32,824 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:32,825 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:55:32,825 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [974319980] [2019-12-07 18:55:32,826 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:55:32,826 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:32,826 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:55:32,826 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:55:32,827 INFO L87 Difference]: Start difference. First operand 112412 states and 484274 transitions. Second operand 4 states. [2019-12-07 18:55:33,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:33,798 INFO L93 Difference]: Finished difference Result 180702 states and 747767 transitions. [2019-12-07 18:55:33,798 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:55:33,799 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2019-12-07 18:55:33,799 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:34,659 INFO L225 Difference]: With dead ends: 180702 [2019-12-07 18:55:34,659 INFO L226 Difference]: Without dead ends: 180653 [2019-12-07 18:55:34,660 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:55:41,309 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 180653 states. [2019-12-07 18:55:43,612 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 180653 to 165577. [2019-12-07 18:55:43,613 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165577 states. [2019-12-07 18:55:44,103 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165577 states to 165577 states and 693075 transitions. [2019-12-07 18:55:44,103 INFO L78 Accepts]: Start accepts. Automaton has 165577 states and 693075 transitions. Word has length 11 [2019-12-07 18:55:44,103 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:44,103 INFO L462 AbstractCegarLoop]: Abstraction has 165577 states and 693075 transitions. [2019-12-07 18:55:44,103 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:55:44,104 INFO L276 IsEmpty]: Start isEmpty. Operand 165577 states and 693075 transitions. [2019-12-07 18:55:44,111 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 18:55:44,112 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:44,112 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:44,112 INFO L410 AbstractCegarLoop]: === Iteration 3 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:44,112 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:44,112 INFO L82 PathProgramCache]: Analyzing trace with hash 228163746, now seen corresponding path program 1 times [2019-12-07 18:55:44,112 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:44,113 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [614944400] [2019-12-07 18:55:44,113 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:44,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:44,158 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:44,159 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [614944400] [2019-12-07 18:55:44,159 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:44,159 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:55:44,159 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1385607911] [2019-12-07 18:55:44,159 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:55:44,159 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:44,160 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:55:44,160 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:55:44,160 INFO L87 Difference]: Start difference. First operand 165577 states and 693075 transitions. Second operand 4 states. [2019-12-07 18:55:46,030 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:46,030 INFO L93 Difference]: Finished difference Result 235681 states and 964563 transitions. [2019-12-07 18:55:46,030 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:55:46,030 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 18:55:46,031 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:55:46,628 INFO L225 Difference]: With dead ends: 235681 [2019-12-07 18:55:46,628 INFO L226 Difference]: Without dead ends: 235618 [2019-12-07 18:55:46,629 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:55:54,748 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 235618 states. [2019-12-07 18:55:57,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 235618 to 199613. [2019-12-07 18:55:57,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 199613 states. [2019-12-07 18:55:58,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 199613 states to 199613 states and 830031 transitions. [2019-12-07 18:55:58,452 INFO L78 Accepts]: Start accepts. Automaton has 199613 states and 830031 transitions. Word has length 13 [2019-12-07 18:55:58,453 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:55:58,453 INFO L462 AbstractCegarLoop]: Abstraction has 199613 states and 830031 transitions. [2019-12-07 18:55:58,453 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:55:58,453 INFO L276 IsEmpty]: Start isEmpty. Operand 199613 states and 830031 transitions. [2019-12-07 18:55:58,456 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2019-12-07 18:55:58,456 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:55:58,456 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:55:58,456 INFO L410 AbstractCegarLoop]: === Iteration 4 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:55:58,456 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:55:58,456 INFO L82 PathProgramCache]: Analyzing trace with hash 986322522, now seen corresponding path program 1 times [2019-12-07 18:55:58,457 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:55:58,457 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1382038924] [2019-12-07 18:55:58,457 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:55:58,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:55:58,501 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:55:58,502 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1382038924] [2019-12-07 18:55:58,502 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:55:58,502 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:55:58,502 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1696087138] [2019-12-07 18:55:58,502 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:55:58,502 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:55:58,503 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:55:58,503 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:55:58,503 INFO L87 Difference]: Start difference. First operand 199613 states and 830031 transitions. Second operand 4 states. [2019-12-07 18:55:59,769 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:55:59,770 INFO L93 Difference]: Finished difference Result 248914 states and 1025031 transitions. [2019-12-07 18:55:59,770 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:55:59,771 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2019-12-07 18:55:59,771 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:00,451 INFO L225 Difference]: With dead ends: 248914 [2019-12-07 18:56:00,452 INFO L226 Difference]: Without dead ends: 248914 [2019-12-07 18:56:00,452 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:56:06,860 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 248914 states. [2019-12-07 18:56:12,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 248914 to 210888. [2019-12-07 18:56:12,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 210888 states. [2019-12-07 18:56:13,455 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 210888 states to 210888 states and 876967 transitions. [2019-12-07 18:56:13,455 INFO L78 Accepts]: Start accepts. Automaton has 210888 states and 876967 transitions. Word has length 13 [2019-12-07 18:56:13,456 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:13,456 INFO L462 AbstractCegarLoop]: Abstraction has 210888 states and 876967 transitions. [2019-12-07 18:56:13,456 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:56:13,456 INFO L276 IsEmpty]: Start isEmpty. Operand 210888 states and 876967 transitions. [2019-12-07 18:56:13,471 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 18:56:13,471 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:13,471 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:13,471 INFO L410 AbstractCegarLoop]: === Iteration 5 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:13,471 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:13,472 INFO L82 PathProgramCache]: Analyzing trace with hash -462367392, now seen corresponding path program 1 times [2019-12-07 18:56:13,472 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:13,472 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1770023832] [2019-12-07 18:56:13,472 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:13,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:13,529 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:13,530 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1770023832] [2019-12-07 18:56:13,530 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:13,530 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:56:13,530 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1893912479] [2019-12-07 18:56:13,530 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:56:13,530 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:13,530 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:56:13,531 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:56:13,531 INFO L87 Difference]: Start difference. First operand 210888 states and 876967 transitions. Second operand 5 states. [2019-12-07 18:56:15,305 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:15,305 INFO L93 Difference]: Finished difference Result 307547 states and 1250410 transitions. [2019-12-07 18:56:15,306 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:56:15,306 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 18:56:15,306 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:16,644 INFO L225 Difference]: With dead ends: 307547 [2019-12-07 18:56:16,644 INFO L226 Difference]: Without dead ends: 307407 [2019-12-07 18:56:16,644 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:56:23,584 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 307407 states. [2019-12-07 18:56:27,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 307407 to 231468. [2019-12-07 18:56:27,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 231468 states. [2019-12-07 18:56:28,166 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 231468 states to 231468 states and 958023 transitions. [2019-12-07 18:56:28,166 INFO L78 Accepts]: Start accepts. Automaton has 231468 states and 958023 transitions. Word has length 19 [2019-12-07 18:56:28,166 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:28,166 INFO L462 AbstractCegarLoop]: Abstraction has 231468 states and 958023 transitions. [2019-12-07 18:56:28,166 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:56:28,166 INFO L276 IsEmpty]: Start isEmpty. Operand 231468 states and 958023 transitions. [2019-12-07 18:56:28,178 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 18:56:28,178 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:28,178 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:28,178 INFO L410 AbstractCegarLoop]: === Iteration 6 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:28,178 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:28,179 INFO L82 PathProgramCache]: Analyzing trace with hash 1565841874, now seen corresponding path program 1 times [2019-12-07 18:56:28,179 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:28,179 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1550558991] [2019-12-07 18:56:28,179 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:28,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:28,217 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:28,217 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1550558991] [2019-12-07 18:56:28,218 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:28,218 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:56:28,218 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1662708359] [2019-12-07 18:56:28,218 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:56:28,218 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:28,218 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:56:28,219 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:56:28,219 INFO L87 Difference]: Start difference. First operand 231468 states and 958023 transitions. Second operand 5 states. [2019-12-07 18:56:30,409 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:30,409 INFO L93 Difference]: Finished difference Result 336881 states and 1367511 transitions. [2019-12-07 18:56:30,410 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:56:30,410 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 18:56:30,410 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:31,260 INFO L225 Difference]: With dead ends: 336881 [2019-12-07 18:56:31,261 INFO L226 Difference]: Without dead ends: 336818 [2019-12-07 18:56:31,261 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:56:41,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 336818 states. [2019-12-07 18:56:45,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 336818 to 236903. [2019-12-07 18:56:45,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 236903 states. [2019-12-07 18:56:46,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 236903 states to 236903 states and 979540 transitions. [2019-12-07 18:56:46,206 INFO L78 Accepts]: Start accepts. Automaton has 236903 states and 979540 transitions. Word has length 19 [2019-12-07 18:56:46,206 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:56:46,206 INFO L462 AbstractCegarLoop]: Abstraction has 236903 states and 979540 transitions. [2019-12-07 18:56:46,206 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:56:46,206 INFO L276 IsEmpty]: Start isEmpty. Operand 236903 states and 979540 transitions. [2019-12-07 18:56:46,219 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2019-12-07 18:56:46,219 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:56:46,219 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:56:46,219 INFO L410 AbstractCegarLoop]: === Iteration 7 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:56:46,219 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:56:46,219 INFO L82 PathProgramCache]: Analyzing trace with hash 1619434579, now seen corresponding path program 1 times [2019-12-07 18:56:46,220 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:56:46,220 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1593527836] [2019-12-07 18:56:46,220 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:56:46,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:56:46,259 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:56:46,259 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1593527836] [2019-12-07 18:56:46,259 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:56:46,259 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:56:46,260 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [621504150] [2019-12-07 18:56:46,260 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:56:46,260 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:56:46,260 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:56:46,260 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:56:46,260 INFO L87 Difference]: Start difference. First operand 236903 states and 979540 transitions. Second operand 5 states. [2019-12-07 18:56:48,591 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:56:48,591 INFO L93 Difference]: Finished difference Result 346916 states and 1409827 transitions. [2019-12-07 18:56:48,592 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:56:48,592 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 19 [2019-12-07 18:56:48,592 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:56:49,436 INFO L225 Difference]: With dead ends: 346916 [2019-12-07 18:56:49,436 INFO L226 Difference]: Without dead ends: 346853 [2019-12-07 18:56:49,436 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:56:56,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 346853 states. [2019-12-07 18:57:00,824 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 346853 to 254808. [2019-12-07 18:57:00,824 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 254808 states. [2019-12-07 18:57:01,928 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 254808 states to 254808 states and 1052340 transitions. [2019-12-07 18:57:01,929 INFO L78 Accepts]: Start accepts. Automaton has 254808 states and 1052340 transitions. Word has length 19 [2019-12-07 18:57:01,929 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:57:01,929 INFO L462 AbstractCegarLoop]: Abstraction has 254808 states and 1052340 transitions. [2019-12-07 18:57:01,929 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:57:01,929 INFO L276 IsEmpty]: Start isEmpty. Operand 254808 states and 1052340 transitions. [2019-12-07 18:57:01,988 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2019-12-07 18:57:01,989 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:57:01,989 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:57:01,989 INFO L410 AbstractCegarLoop]: === Iteration 8 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:57:01,989 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:57:01,989 INFO L82 PathProgramCache]: Analyzing trace with hash -1274808359, now seen corresponding path program 1 times [2019-12-07 18:57:01,989 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:57:01,989 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [881339604] [2019-12-07 18:57:01,989 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:57:02,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:57:02,070 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:57:02,070 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [881339604] [2019-12-07 18:57:02,070 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:57:02,070 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:57:02,070 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1677876617] [2019-12-07 18:57:02,070 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-07 18:57:02,071 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:57:02,071 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-07 18:57:02,071 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:57:02,071 INFO L87 Difference]: Start difference. First operand 254808 states and 1052340 transitions. Second operand 7 states. [2019-12-07 18:57:07,012 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:57:07,012 INFO L93 Difference]: Finished difference Result 307851 states and 1257197 transitions. [2019-12-07 18:57:07,013 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2019-12-07 18:57:07,013 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 25 [2019-12-07 18:57:07,014 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:57:07,785 INFO L225 Difference]: With dead ends: 307851 [2019-12-07 18:57:07,785 INFO L226 Difference]: Without dead ends: 307711 [2019-12-07 18:57:07,786 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 1 SyntacticMatches, 4 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 57 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=96, Invalid=246, Unknown=0, NotChecked=0, Total=342 [2019-12-07 18:57:14,333 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 307711 states. [2019-12-07 18:57:17,925 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 307711 to 209314. [2019-12-07 18:57:17,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 209314 states. [2019-12-07 18:57:18,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 209314 states to 209314 states and 868471 transitions. [2019-12-07 18:57:18,578 INFO L78 Accepts]: Start accepts. Automaton has 209314 states and 868471 transitions. Word has length 25 [2019-12-07 18:57:18,579 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:57:18,579 INFO L462 AbstractCegarLoop]: Abstraction has 209314 states and 868471 transitions. [2019-12-07 18:57:18,579 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-07 18:57:18,579 INFO L276 IsEmpty]: Start isEmpty. Operand 209314 states and 868471 transitions. [2019-12-07 18:57:18,652 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 18:57:18,652 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:57:18,652 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:57:18,652 INFO L410 AbstractCegarLoop]: === Iteration 9 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:57:18,653 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:57:18,653 INFO L82 PathProgramCache]: Analyzing trace with hash -730041914, now seen corresponding path program 1 times [2019-12-07 18:57:18,653 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:57:18,653 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1554317018] [2019-12-07 18:57:18,653 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:57:18,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:57:18,676 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:57:18,677 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1554317018] [2019-12-07 18:57:18,677 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:57:18,677 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:57:18,677 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [773535908] [2019-12-07 18:57:18,677 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:57:18,677 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:57:18,678 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:57:18,678 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:57:18,678 INFO L87 Difference]: Start difference. First operand 209314 states and 868471 transitions. Second operand 3 states. [2019-12-07 18:57:20,222 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:57:20,222 INFO L93 Difference]: Finished difference Result 252030 states and 1035145 transitions. [2019-12-07 18:57:20,222 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:57:20,223 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-12-07 18:57:20,223 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:57:20,875 INFO L225 Difference]: With dead ends: 252030 [2019-12-07 18:57:20,875 INFO L226 Difference]: Without dead ends: 252030 [2019-12-07 18:57:20,875 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:57:26,982 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 252030 states. [2019-12-07 18:57:30,613 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 252030 to 220743. [2019-12-07 18:57:30,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220743 states. [2019-12-07 18:57:31,323 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220743 states to 220743 states and 915334 transitions. [2019-12-07 18:57:31,324 INFO L78 Accepts]: Start accepts. Automaton has 220743 states and 915334 transitions. Word has length 27 [2019-12-07 18:57:31,324 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:57:31,324 INFO L462 AbstractCegarLoop]: Abstraction has 220743 states and 915334 transitions. [2019-12-07 18:57:31,324 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:57:31,324 INFO L276 IsEmpty]: Start isEmpty. Operand 220743 states and 915334 transitions. [2019-12-07 18:57:31,398 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2019-12-07 18:57:31,398 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:57:31,398 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:57:31,398 INFO L410 AbstractCegarLoop]: === Iteration 10 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:57:31,398 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:57:31,398 INFO L82 PathProgramCache]: Analyzing trace with hash -730215328, now seen corresponding path program 1 times [2019-12-07 18:57:31,398 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:57:31,399 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [228068942] [2019-12-07 18:57:31,399 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:57:31,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:57:31,427 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:57:31,427 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [228068942] [2019-12-07 18:57:31,427 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:57:31,428 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:57:31,428 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [384042369] [2019-12-07 18:57:31,428 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:57:31,428 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:57:31,428 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:57:31,428 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:57:31,428 INFO L87 Difference]: Start difference. First operand 220743 states and 915334 transitions. Second operand 3 states. [2019-12-07 18:57:31,558 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:57:31,559 INFO L93 Difference]: Finished difference Result 44700 states and 144997 transitions. [2019-12-07 18:57:31,559 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:57:31,559 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2019-12-07 18:57:31,560 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:57:31,626 INFO L225 Difference]: With dead ends: 44700 [2019-12-07 18:57:31,626 INFO L226 Difference]: Without dead ends: 44700 [2019-12-07 18:57:31,626 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:57:31,843 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44700 states. [2019-12-07 18:57:32,640 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44700 to 44700. [2019-12-07 18:57:32,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44700 states. [2019-12-07 18:57:32,719 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44700 states to 44700 states and 144997 transitions. [2019-12-07 18:57:32,719 INFO L78 Accepts]: Start accepts. Automaton has 44700 states and 144997 transitions. Word has length 27 [2019-12-07 18:57:32,719 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:57:32,720 INFO L462 AbstractCegarLoop]: Abstraction has 44700 states and 144997 transitions. [2019-12-07 18:57:32,720 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:57:32,720 INFO L276 IsEmpty]: Start isEmpty. Operand 44700 states and 144997 transitions. [2019-12-07 18:57:32,737 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2019-12-07 18:57:32,737 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:57:32,737 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:57:32,738 INFO L410 AbstractCegarLoop]: === Iteration 11 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:57:32,738 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:57:32,738 INFO L82 PathProgramCache]: Analyzing trace with hash -955256505, now seen corresponding path program 1 times [2019-12-07 18:57:32,738 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:57:32,738 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [851150060] [2019-12-07 18:57:32,738 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:57:32,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:57:32,771 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:57:32,771 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [851150060] [2019-12-07 18:57:32,771 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:57:32,771 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-07 18:57:32,772 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [340100938] [2019-12-07 18:57:32,772 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-07 18:57:32,772 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:57:32,772 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-07 18:57:32,772 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:57:32,772 INFO L87 Difference]: Start difference. First operand 44700 states and 144997 transitions. Second operand 4 states. [2019-12-07 18:57:32,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:57:32,806 INFO L93 Difference]: Finished difference Result 8211 states and 22128 transitions. [2019-12-07 18:57:32,806 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-07 18:57:32,806 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 39 [2019-12-07 18:57:32,807 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:57:32,814 INFO L225 Difference]: With dead ends: 8211 [2019-12-07 18:57:32,814 INFO L226 Difference]: Without dead ends: 8211 [2019-12-07 18:57:32,814 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-12-07 18:57:32,841 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8211 states. [2019-12-07 18:57:32,899 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8211 to 8071. [2019-12-07 18:57:32,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8071 states. [2019-12-07 18:57:32,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8071 states to 8071 states and 21728 transitions. [2019-12-07 18:57:32,909 INFO L78 Accepts]: Start accepts. Automaton has 8071 states and 21728 transitions. Word has length 39 [2019-12-07 18:57:32,909 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:57:32,909 INFO L462 AbstractCegarLoop]: Abstraction has 8071 states and 21728 transitions. [2019-12-07 18:57:32,909 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-07 18:57:32,910 INFO L276 IsEmpty]: Start isEmpty. Operand 8071 states and 21728 transitions. [2019-12-07 18:57:32,915 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2019-12-07 18:57:32,915 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:57:32,915 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:57:32,915 INFO L410 AbstractCegarLoop]: === Iteration 12 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:57:32,916 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:57:32,916 INFO L82 PathProgramCache]: Analyzing trace with hash 296426846, now seen corresponding path program 1 times [2019-12-07 18:57:32,916 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:57:32,916 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1799768180] [2019-12-07 18:57:32,916 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:57:32,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:57:32,958 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:57:32,958 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1799768180] [2019-12-07 18:57:32,958 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:57:32,958 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:57:32,959 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1533162762] [2019-12-07 18:57:32,959 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:57:32,959 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:57:32,959 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:57:32,959 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:57:32,959 INFO L87 Difference]: Start difference. First operand 8071 states and 21728 transitions. Second operand 5 states. [2019-12-07 18:57:32,990 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:57:32,990 INFO L93 Difference]: Finished difference Result 5424 states and 15553 transitions. [2019-12-07 18:57:32,990 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:57:32,990 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 51 [2019-12-07 18:57:32,990 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:57:32,996 INFO L225 Difference]: With dead ends: 5424 [2019-12-07 18:57:32,997 INFO L226 Difference]: Without dead ends: 5424 [2019-12-07 18:57:32,997 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:57:33,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5424 states. [2019-12-07 18:57:33,058 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5424 to 5011. [2019-12-07 18:57:33,058 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5011 states. [2019-12-07 18:57:33,064 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5011 states to 5011 states and 14436 transitions. [2019-12-07 18:57:33,065 INFO L78 Accepts]: Start accepts. Automaton has 5011 states and 14436 transitions. Word has length 51 [2019-12-07 18:57:33,065 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:57:33,065 INFO L462 AbstractCegarLoop]: Abstraction has 5011 states and 14436 transitions. [2019-12-07 18:57:33,065 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:57:33,065 INFO L276 IsEmpty]: Start isEmpty. Operand 5011 states and 14436 transitions. [2019-12-07 18:57:33,068 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:57:33,068 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:57:33,069 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:57:33,069 INFO L410 AbstractCegarLoop]: === Iteration 13 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:57:33,069 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:57:33,069 INFO L82 PathProgramCache]: Analyzing trace with hash -1256158932, now seen corresponding path program 1 times [2019-12-07 18:57:33,069 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:57:33,069 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [985309538] [2019-12-07 18:57:33,069 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:57:33,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:57:33,121 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:57:33,121 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [985309538] [2019-12-07 18:57:33,121 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:57:33,121 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-07 18:57:33,122 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1257464289] [2019-12-07 18:57:33,122 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:57:33,122 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:57:33,122 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:57:33,122 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:57:33,122 INFO L87 Difference]: Start difference. First operand 5011 states and 14436 transitions. Second operand 5 states. [2019-12-07 18:57:33,312 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:57:33,312 INFO L93 Difference]: Finished difference Result 7949 states and 22591 transitions. [2019-12-07 18:57:33,312 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-07 18:57:33,312 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 65 [2019-12-07 18:57:33,312 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:57:33,319 INFO L225 Difference]: With dead ends: 7949 [2019-12-07 18:57:33,319 INFO L226 Difference]: Without dead ends: 7949 [2019-12-07 18:57:33,319 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:57:33,348 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7949 states. [2019-12-07 18:57:33,402 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7949 to 6403. [2019-12-07 18:57:33,402 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6403 states. [2019-12-07 18:57:33,410 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6403 states to 6403 states and 18388 transitions. [2019-12-07 18:57:33,410 INFO L78 Accepts]: Start accepts. Automaton has 6403 states and 18388 transitions. Word has length 65 [2019-12-07 18:57:33,410 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:57:33,410 INFO L462 AbstractCegarLoop]: Abstraction has 6403 states and 18388 transitions. [2019-12-07 18:57:33,410 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:57:33,410 INFO L276 IsEmpty]: Start isEmpty. Operand 6403 states and 18388 transitions. [2019-12-07 18:57:33,415 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:57:33,415 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:57:33,415 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:57:33,415 INFO L410 AbstractCegarLoop]: === Iteration 14 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:57:33,415 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:57:33,416 INFO L82 PathProgramCache]: Analyzing trace with hash 343857822, now seen corresponding path program 2 times [2019-12-07 18:57:33,416 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:57:33,416 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [779146696] [2019-12-07 18:57:33,416 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:57:33,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:57:33,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:57:33,477 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [779146696] [2019-12-07 18:57:33,477 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:57:33,477 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:57:33,477 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [762211284] [2019-12-07 18:57:33,478 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:57:33,478 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:57:33,478 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:57:33,478 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:57:33,478 INFO L87 Difference]: Start difference. First operand 6403 states and 18388 transitions. Second operand 6 states. [2019-12-07 18:57:33,784 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:57:33,784 INFO L93 Difference]: Finished difference Result 10473 states and 29944 transitions. [2019-12-07 18:57:33,784 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:57:33,784 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 65 [2019-12-07 18:57:33,784 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:57:33,793 INFO L225 Difference]: With dead ends: 10473 [2019-12-07 18:57:33,794 INFO L226 Difference]: Without dead ends: 10473 [2019-12-07 18:57:33,794 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:57:33,828 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10473 states. [2019-12-07 18:57:33,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10473 to 7234. [2019-12-07 18:57:33,894 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7234 states. [2019-12-07 18:57:33,902 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7234 states to 7234 states and 20816 transitions. [2019-12-07 18:57:33,902 INFO L78 Accepts]: Start accepts. Automaton has 7234 states and 20816 transitions. Word has length 65 [2019-12-07 18:57:33,903 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:57:33,903 INFO L462 AbstractCegarLoop]: Abstraction has 7234 states and 20816 transitions. [2019-12-07 18:57:33,903 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:57:33,903 INFO L276 IsEmpty]: Start isEmpty. Operand 7234 states and 20816 transitions. [2019-12-07 18:57:33,908 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:57:33,908 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:57:33,908 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:57:33,908 INFO L410 AbstractCegarLoop]: === Iteration 15 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:57:33,908 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:57:33,908 INFO L82 PathProgramCache]: Analyzing trace with hash 1151551294, now seen corresponding path program 3 times [2019-12-07 18:57:33,909 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:57:33,909 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1463034081] [2019-12-07 18:57:33,909 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:57:33,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:57:33,970 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:57:33,970 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1463034081] [2019-12-07 18:57:33,971 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:57:33,971 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:57:33,971 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [269705492] [2019-12-07 18:57:33,971 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:57:33,971 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:57:33,971 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:57:33,971 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:57:33,971 INFO L87 Difference]: Start difference. First operand 7234 states and 20816 transitions. Second operand 6 states. [2019-12-07 18:57:34,256 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:57:34,256 INFO L93 Difference]: Finished difference Result 9395 states and 26435 transitions. [2019-12-07 18:57:34,257 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-07 18:57:34,257 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 65 [2019-12-07 18:57:34,257 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:57:34,265 INFO L225 Difference]: With dead ends: 9395 [2019-12-07 18:57:34,265 INFO L226 Difference]: Without dead ends: 9395 [2019-12-07 18:57:34,265 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2019-12-07 18:57:34,296 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9395 states. [2019-12-07 18:57:34,369 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9395 to 7883. [2019-12-07 18:57:34,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7883 states. [2019-12-07 18:57:34,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7883 states to 7883 states and 22375 transitions. [2019-12-07 18:57:34,379 INFO L78 Accepts]: Start accepts. Automaton has 7883 states and 22375 transitions. Word has length 65 [2019-12-07 18:57:34,380 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:57:34,380 INFO L462 AbstractCegarLoop]: Abstraction has 7883 states and 22375 transitions. [2019-12-07 18:57:34,380 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:57:34,380 INFO L276 IsEmpty]: Start isEmpty. Operand 7883 states and 22375 transitions. [2019-12-07 18:57:34,385 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2019-12-07 18:57:34,386 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:57:34,386 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:57:34,386 INFO L410 AbstractCegarLoop]: === Iteration 16 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:57:34,386 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:57:34,386 INFO L82 PathProgramCache]: Analyzing trace with hash 663923916, now seen corresponding path program 4 times [2019-12-07 18:57:34,386 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:57:34,386 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [238107526] [2019-12-07 18:57:34,386 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:57:34,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:57:34,422 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:57:34,422 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [238107526] [2019-12-07 18:57:34,422 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:57:34,422 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:57:34,423 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1481901725] [2019-12-07 18:57:34,423 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:57:34,423 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:57:34,423 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:57:34,423 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:57:34,423 INFO L87 Difference]: Start difference. First operand 7883 states and 22375 transitions. Second operand 3 states. [2019-12-07 18:57:34,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:57:34,444 INFO L93 Difference]: Finished difference Result 6881 states and 19309 transitions. [2019-12-07 18:57:34,444 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:57:34,444 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 65 [2019-12-07 18:57:34,444 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:57:34,450 INFO L225 Difference]: With dead ends: 6881 [2019-12-07 18:57:34,450 INFO L226 Difference]: Without dead ends: 6881 [2019-12-07 18:57:34,450 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:57:34,474 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6881 states. [2019-12-07 18:57:34,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6881 to 6545. [2019-12-07 18:57:34,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6545 states. [2019-12-07 18:57:34,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6545 states to 6545 states and 18377 transitions. [2019-12-07 18:57:34,530 INFO L78 Accepts]: Start accepts. Automaton has 6545 states and 18377 transitions. Word has length 65 [2019-12-07 18:57:34,530 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:57:34,530 INFO L462 AbstractCegarLoop]: Abstraction has 6545 states and 18377 transitions. [2019-12-07 18:57:34,530 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:57:34,530 INFO L276 IsEmpty]: Start isEmpty. Operand 6545 states and 18377 transitions. [2019-12-07 18:57:34,535 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 18:57:34,535 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:57:34,535 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:57:34,535 INFO L410 AbstractCegarLoop]: === Iteration 17 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:57:34,535 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:57:34,535 INFO L82 PathProgramCache]: Analyzing trace with hash -319017164, now seen corresponding path program 1 times [2019-12-07 18:57:34,535 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:57:34,535 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [460758580] [2019-12-07 18:57:34,536 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:57:34,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:57:34,594 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:57:34,594 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [460758580] [2019-12-07 18:57:34,594 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:57:34,594 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-07 18:57:34,594 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1351389086] [2019-12-07 18:57:34,595 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-07 18:57:34,595 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:57:34,595 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-07 18:57:34,595 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-12-07 18:57:34,595 INFO L87 Difference]: Start difference. First operand 6545 states and 18377 transitions. Second operand 6 states. [2019-12-07 18:57:34,836 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:57:34,836 INFO L93 Difference]: Finished difference Result 8971 states and 24871 transitions. [2019-12-07 18:57:34,837 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-07 18:57:34,837 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 66 [2019-12-07 18:57:34,837 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:57:34,844 INFO L225 Difference]: With dead ends: 8971 [2019-12-07 18:57:34,844 INFO L226 Difference]: Without dead ends: 8971 [2019-12-07 18:57:34,844 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 6 SyntacticMatches, 3 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2019-12-07 18:57:34,872 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8971 states. [2019-12-07 18:57:34,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8971 to 6895. [2019-12-07 18:57:34,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6895 states. [2019-12-07 18:57:34,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6895 states to 6895 states and 19349 transitions. [2019-12-07 18:57:34,939 INFO L78 Accepts]: Start accepts. Automaton has 6895 states and 19349 transitions. Word has length 66 [2019-12-07 18:57:34,939 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:57:34,939 INFO L462 AbstractCegarLoop]: Abstraction has 6895 states and 19349 transitions. [2019-12-07 18:57:34,939 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-07 18:57:34,939 INFO L276 IsEmpty]: Start isEmpty. Operand 6895 states and 19349 transitions. [2019-12-07 18:57:35,487 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2019-12-07 18:57:35,487 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:57:35,487 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:57:35,487 INFO L410 AbstractCegarLoop]: === Iteration 18 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:57:35,487 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:57:35,487 INFO L82 PathProgramCache]: Analyzing trace with hash 652438842, now seen corresponding path program 2 times [2019-12-07 18:57:35,487 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:57:35,488 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1205611410] [2019-12-07 18:57:35,488 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:57:35,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:57:35,534 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:57:35,534 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1205611410] [2019-12-07 18:57:35,534 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:57:35,534 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:57:35,534 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [844786740] [2019-12-07 18:57:35,535 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:57:35,535 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:57:35,535 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:57:35,535 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:57:35,535 INFO L87 Difference]: Start difference. First operand 6895 states and 19349 transitions. Second operand 3 states. [2019-12-07 18:57:35,577 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:57:35,577 INFO L93 Difference]: Finished difference Result 6895 states and 19348 transitions. [2019-12-07 18:57:35,577 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:57:35,577 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 66 [2019-12-07 18:57:35,577 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:57:35,583 INFO L225 Difference]: With dead ends: 6895 [2019-12-07 18:57:35,583 INFO L226 Difference]: Without dead ends: 6895 [2019-12-07 18:57:35,584 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:57:35,609 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6895 states. [2019-12-07 18:57:35,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6895 to 5310. [2019-12-07 18:57:35,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5310 states. [2019-12-07 18:57:35,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5310 states to 5310 states and 14971 transitions. [2019-12-07 18:57:35,660 INFO L78 Accepts]: Start accepts. Automaton has 5310 states and 14971 transitions. Word has length 66 [2019-12-07 18:57:35,660 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:57:35,660 INFO L462 AbstractCegarLoop]: Abstraction has 5310 states and 14971 transitions. [2019-12-07 18:57:35,660 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:57:35,661 INFO L276 IsEmpty]: Start isEmpty. Operand 5310 states and 14971 transitions. [2019-12-07 18:57:35,664 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2019-12-07 18:57:35,664 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:57:35,664 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:57:35,664 INFO L410 AbstractCegarLoop]: === Iteration 19 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:57:35,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:57:35,665 INFO L82 PathProgramCache]: Analyzing trace with hash -635838162, now seen corresponding path program 1 times [2019-12-07 18:57:35,665 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:57:35,665 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [951370379] [2019-12-07 18:57:35,665 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:57:35,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:57:35,703 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:57:35,704 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [951370379] [2019-12-07 18:57:35,704 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:57:35,704 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-12-07 18:57:35,704 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [757199420] [2019-12-07 18:57:35,704 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-07 18:57:35,704 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:57:35,705 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-07 18:57:35,705 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:57:35,705 INFO L87 Difference]: Start difference. First operand 5310 states and 14971 transitions. Second operand 3 states. [2019-12-07 18:57:35,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:57:35,727 INFO L93 Difference]: Finished difference Result 5074 states and 14097 transitions. [2019-12-07 18:57:35,727 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-07 18:57:35,727 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 67 [2019-12-07 18:57:35,727 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:57:35,731 INFO L225 Difference]: With dead ends: 5074 [2019-12-07 18:57:35,731 INFO L226 Difference]: Without dead ends: 5074 [2019-12-07 18:57:35,732 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-07 18:57:35,754 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5074 states. [2019-12-07 18:57:35,790 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5074 to 4934. [2019-12-07 18:57:35,790 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4934 states. [2019-12-07 18:57:35,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4934 states to 4934 states and 13711 transitions. [2019-12-07 18:57:35,796 INFO L78 Accepts]: Start accepts. Automaton has 4934 states and 13711 transitions. Word has length 67 [2019-12-07 18:57:35,796 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:57:35,796 INFO L462 AbstractCegarLoop]: Abstraction has 4934 states and 13711 transitions. [2019-12-07 18:57:35,797 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-07 18:57:35,797 INFO L276 IsEmpty]: Start isEmpty. Operand 4934 states and 13711 transitions. [2019-12-07 18:57:35,800 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 18:57:35,800 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:57:35,800 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:57:35,800 INFO L410 AbstractCegarLoop]: === Iteration 20 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:57:35,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:57:35,800 INFO L82 PathProgramCache]: Analyzing trace with hash -2084050195, now seen corresponding path program 1 times [2019-12-07 18:57:35,801 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:57:35,801 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2088622180] [2019-12-07 18:57:35,801 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:57:35,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:57:35,968 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:57:35,968 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2088622180] [2019-12-07 18:57:35,968 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:57:35,968 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2019-12-07 18:57:35,968 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1461643287] [2019-12-07 18:57:35,969 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2019-12-07 18:57:35,969 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:57:35,969 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2019-12-07 18:57:35,969 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=112, Unknown=0, NotChecked=0, Total=156 [2019-12-07 18:57:35,969 INFO L87 Difference]: Start difference. First operand 4934 states and 13711 transitions. Second operand 13 states. [2019-12-07 18:57:36,541 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:57:36,541 INFO L93 Difference]: Finished difference Result 14398 states and 39934 transitions. [2019-12-07 18:57:36,541 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2019-12-07 18:57:36,542 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 68 [2019-12-07 18:57:36,542 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:57:36,546 INFO L225 Difference]: With dead ends: 14398 [2019-12-07 18:57:36,546 INFO L226 Difference]: Without dead ends: 5438 [2019-12-07 18:57:36,546 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 89 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2019-12-07 18:57:36,567 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5438 states. [2019-12-07 18:57:36,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5438 to 4088. [2019-12-07 18:57:36,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4088 states. [2019-12-07 18:57:36,602 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4088 states to 4088 states and 11287 transitions. [2019-12-07 18:57:36,602 INFO L78 Accepts]: Start accepts. Automaton has 4088 states and 11287 transitions. Word has length 68 [2019-12-07 18:57:36,602 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:57:36,602 INFO L462 AbstractCegarLoop]: Abstraction has 4088 states and 11287 transitions. [2019-12-07 18:57:36,602 INFO L463 AbstractCegarLoop]: Interpolant automaton has 13 states. [2019-12-07 18:57:36,602 INFO L276 IsEmpty]: Start isEmpty. Operand 4088 states and 11287 transitions. [2019-12-07 18:57:36,604 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 18:57:36,604 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:57:36,604 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:57:36,604 INFO L410 AbstractCegarLoop]: === Iteration 21 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:57:36,605 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:57:36,605 INFO L82 PathProgramCache]: Analyzing trace with hash -293308025, now seen corresponding path program 2 times [2019-12-07 18:57:36,605 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:57:36,605 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1774799309] [2019-12-07 18:57:36,605 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:57:36,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-07 18:57:36,662 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-07 18:57:36,662 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1774799309] [2019-12-07 18:57:36,662 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-07 18:57:36,662 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-07 18:57:36,662 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1816024139] [2019-12-07 18:57:36,663 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-07 18:57:36,663 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-07 18:57:36,663 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-07 18:57:36,663 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-07 18:57:36,663 INFO L87 Difference]: Start difference. First operand 4088 states and 11287 transitions. Second operand 5 states. [2019-12-07 18:57:36,709 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-07 18:57:36,709 INFO L93 Difference]: Finished difference Result 5944 states and 16450 transitions. [2019-12-07 18:57:36,709 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-07 18:57:36,709 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 68 [2019-12-07 18:57:36,710 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-07 18:57:36,711 INFO L225 Difference]: With dead ends: 5944 [2019-12-07 18:57:36,711 INFO L226 Difference]: Without dead ends: 1897 [2019-12-07 18:57:36,711 INFO L630 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-07 18:57:36,725 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1897 states. [2019-12-07 18:57:36,736 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1897 to 1897. [2019-12-07 18:57:36,736 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1897 states. [2019-12-07 18:57:36,738 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1897 states to 1897 states and 5235 transitions. [2019-12-07 18:57:36,738 INFO L78 Accepts]: Start accepts. Automaton has 1897 states and 5235 transitions. Word has length 68 [2019-12-07 18:57:36,738 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-07 18:57:36,738 INFO L462 AbstractCegarLoop]: Abstraction has 1897 states and 5235 transitions. [2019-12-07 18:57:36,738 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-07 18:57:36,738 INFO L276 IsEmpty]: Start isEmpty. Operand 1897 states and 5235 transitions. [2019-12-07 18:57:36,739 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2019-12-07 18:57:36,739 INFO L402 BasicCegarLoop]: Found error trace [2019-12-07 18:57:36,740 INFO L410 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-07 18:57:36,740 INFO L410 AbstractCegarLoop]: === Iteration 22 === [P1Err0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, P1Err0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-07 18:57:36,740 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-07 18:57:36,740 INFO L82 PathProgramCache]: Analyzing trace with hash -1266757317, now seen corresponding path program 3 times [2019-12-07 18:57:36,740 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-07 18:57:36,740 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [543234011] [2019-12-07 18:57:36,740 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-07 18:57:36,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:57:36,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-07 18:57:36,832 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-07 18:57:36,832 INFO L475 BasicCegarLoop]: Counterexample might be feasible [2019-12-07 18:57:36,836 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [825] [825] ULTIMATE.startENTRY-->L810: Formula: (let ((.cse0 (store |v_#valid_57| 0 0))) (and (= 0 v_~__unbuffered_p2_EAX~0_23) (= v_~z~0_18 0) (= 0 v_~weak$$choice0~0_14) (= v_~x$flush_delayed~0_41 0) (= 0 v_~x$r_buff0_thd3~0_99) (= v_~x$r_buff1_thd1~0_192 0) (= 0 v_~x$w_buff0~0_203) (= v_~weak$$choice2~0_116 0) (< 0 |v_#StackHeapBarrier_17|) (= |v_#valid_55| (store .cse0 |v_ULTIMATE.start_main_~#t748~0.base_20| 1)) (= 0 v_~x$r_buff1_thd3~0_193) (= 0 v_~x$read_delayed_var~0.base_7) (= 0 v_~x$w_buff1~0_195) (= |v_#length_25| (store |v_#length_26| |v_ULTIMATE.start_main_~#t748~0.base_20| 4)) (= v_~x$mem_tmp~0_22 0) (= v_~__unbuffered_p2_EBX~0_23 0) (= (store |v_#memory_int_24| |v_ULTIMATE.start_main_~#t748~0.base_20| (store (select |v_#memory_int_24| |v_ULTIMATE.start_main_~#t748~0.base_20|) |v_ULTIMATE.start_main_~#t748~0.offset_17| 0)) |v_#memory_int_23|) (= 0 v_~x$r_buff0_thd2~0_205) (= v_~main$tmp_guard1~0_28 0) (= v_~x$r_buff0_thd0~0_335 0) (= 0 v_~x$read_delayed~0_7) (= v_~x$r_buff1_thd0~0_279 0) (= 0 v_~x$w_buff1_used~0_401) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t748~0.base_20|) (= v_~__unbuffered_cnt~0_145 0) (= |v_ULTIMATE.start_main_~#t748~0.offset_17| 0) (= 0 v_~x$r_buff1_thd2~0_186) (= 0 v_~x$w_buff0_used~0_743) (= |v_#NULL.offset_5| 0) (= 0 v_~x~0_213) (= 0 v_~x$read_delayed_var~0.offset_7) (= v_~main$tmp_guard0~0_22 0) (= 0 v_~x$r_buff0_thd1~0_88) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t748~0.base_20|)) (= 0 |v_#NULL.base_5|) (= v_~y~0_136 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_57|, #memory_int=|v_#memory_int_24|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_21|, ~x$w_buff0~0=v_~x$w_buff0~0_203, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_27|, ~x$flush_delayed~0=v_~x$flush_delayed~0_41, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_31|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_29|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_25|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_40|, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_192, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_99, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_39|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_25|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_46|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_36|, ULTIMATE.start_main_~#t749~0.offset=|v_ULTIMATE.start_main_~#t749~0.offset_17|, #length=|v_#length_25|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_23, ULTIMATE.start_main_~#t748~0.base=|v_ULTIMATE.start_main_~#t748~0.base_20|, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_335, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_23, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_9|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_43|, ~x$w_buff1~0=v_~x$w_buff1~0_195, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_46|, ULTIMATE.start_main_~#t750~0.offset=|v_ULTIMATE.start_main_~#t750~0.offset_17|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_401, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_186, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_50|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_111|, ~x$read_delayed_var~0.base=v_~x$read_delayed_var~0.base_7, ~weak$$choice0~0=v_~weak$$choice0~0_14, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_156|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_145, ~x~0=v_~x~0_213, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_88, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_21|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_33|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_27|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_25|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_193, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_28, ULTIMATE.start_main_~#t748~0.offset=|v_ULTIMATE.start_main_~#t748~0.offset_17|, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_33|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_17|, ~x$mem_tmp~0=v_~x$mem_tmp~0_22, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_273|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_41|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_34|, ~y~0=v_~y~0_136, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_10|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_23|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_27|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_54|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_22, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_279, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_205, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_59|, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_42|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_743, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_162|, ~x$read_delayed_var~0.offset=v_~x$read_delayed_var~0.offset_7, ULTIMATE.start_main_~#t749~0.base=|v_ULTIMATE.start_main_~#t749~0.base_21|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, #valid=|v_#valid_55|, #memory_int=|v_#memory_int_23|, ~z~0=v_~z~0_18, ULTIMATE.start_main_~#t750~0.base=|v_ULTIMATE.start_main_~#t750~0.base_21|, ~weak$$choice2~0=v_~weak$$choice2~0_116, ~x$read_delayed~0=v_~x$read_delayed~0_7} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ~x$w_buff0~0, ULTIMATE.start_main_#t~ite28, ~x$flush_delayed~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ~x$r_buff1_thd1~0, ~x$r_buff0_thd3~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ULTIMATE.start_main_~#t749~0.offset, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_~#t748~0.base, ~x$r_buff0_thd0~0, ~__unbuffered_p2_EBX~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ~x$w_buff1~0, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_~#t750~0.offset, ~x$w_buff1_used~0, ~x$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite33, ~x$read_delayed_var~0.base, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~__unbuffered_cnt~0, ~x~0, ~x$r_buff0_thd1~0, ULTIMATE.start_main_#t~nondet31, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~x$r_buff1_thd3~0, ~main$tmp_guard1~0, ULTIMATE.start_main_~#t748~0.offset, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ~x$mem_tmp~0, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite51, ~y~0, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ~x$r_buff1_thd0~0, ~x$r_buff0_thd2~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~x$w_buff0_used~0, ULTIMATE.start_main_#t~ite41, ~x$read_delayed_var~0.offset, ULTIMATE.start_main_~#t749~0.base, ULTIMATE.start_main_#res, #valid, #memory_int, ~z~0, ULTIMATE.start_main_~#t750~0.base, ~weak$$choice2~0, ~x$read_delayed~0] because there is no mapped edge [2019-12-07 18:57:36,836 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [809] [809] L810-1-->L812: Formula: (and (= (select |v_#valid_37| |v_ULTIMATE.start_main_~#t749~0.base_13|) 0) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t749~0.base_13| 4)) (= |v_#valid_36| (store |v_#valid_37| |v_ULTIMATE.start_main_~#t749~0.base_13| 1)) (not (= |v_ULTIMATE.start_main_~#t749~0.base_13| 0)) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t749~0.base_13| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t749~0.base_13|) |v_ULTIMATE.start_main_~#t749~0.offset_11| 1)) |v_#memory_int_15|) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t749~0.base_13|) (= |v_ULTIMATE.start_main_~#t749~0.offset_11| 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_37|, #memory_int=|v_#memory_int_16|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_6|, ULTIMATE.start_main_~#t749~0.offset=|v_ULTIMATE.start_main_~#t749~0.offset_11|, ULTIMATE.start_main_~#t749~0.base=|v_ULTIMATE.start_main_~#t749~0.base_13|, #valid=|v_#valid_36|, #memory_int=|v_#memory_int_15|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t749~0.offset, ULTIMATE.start_main_~#t749~0.base, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 18:57:36,837 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [803] [803] L812-1-->L814: Formula: (and (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t750~0.base_13| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t750~0.base_13|) |v_ULTIMATE.start_main_~#t750~0.offset_11| 2)) |v_#memory_int_13|) (= 0 (select |v_#valid_35| |v_ULTIMATE.start_main_~#t750~0.base_13|)) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t750~0.base_13|) (not (= 0 |v_ULTIMATE.start_main_~#t750~0.base_13|)) (= (store |v_#length_16| |v_ULTIMATE.start_main_~#t750~0.base_13| 4) |v_#length_15|) (= 0 |v_ULTIMATE.start_main_~#t750~0.offset_11|) (= (store |v_#valid_35| |v_ULTIMATE.start_main_~#t750~0.base_13| 1) |v_#valid_34|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_~#t750~0.offset=|v_ULTIMATE.start_main_~#t750~0.offset_11|, #length=|v_#length_15|, ULTIMATE.start_main_~#t750~0.base=|v_ULTIMATE.start_main_~#t750~0.base_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, ULTIMATE.start_main_~#t750~0.offset, #length, ULTIMATE.start_main_~#t750~0.base] because there is no mapped edge [2019-12-07 18:57:36,837 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [745] [745] P1ENTRY-->L4-3: Formula: (and (= |v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_8| (ite (not (and (not (= (mod v_~x$w_buff1_used~0_145 256) 0)) (not (= 0 (mod v_~x$w_buff0_used~0_300 256))))) 1 0)) (= v_P1Thread1of1ForFork1_~arg.offset_8 |v_P1Thread1of1ForFork1_#in~arg.offset_10|) (= v_~x$w_buff0~0_44 v_~x$w_buff1~0_51) (not (= 0 v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_10)) (= 2 v_~x$w_buff0~0_43) (= |v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_8| v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_10) (= v_P1Thread1of1ForFork1_~arg.base_8 |v_P1Thread1of1ForFork1_#in~arg.base_10|) (= 1 v_~x$w_buff0_used~0_300) (= v_~x$w_buff0_used~0_301 v_~x$w_buff1_used~0_145)) InVars {~x$w_buff0~0=v_~x$w_buff0~0_44, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_10|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_10|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_301} OutVars{P1Thread1of1ForFork1___VERIFIER_assert_~expression=v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_10, ~x$w_buff0~0=v_~x$w_buff0~0_43, P1Thread1of1ForFork1_~arg.offset=v_P1Thread1of1ForFork1_~arg.offset_8, P1Thread1of1ForFork1___VERIFIER_assert_#in~expression=|v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_8|, P1Thread1of1ForFork1_~arg.base=v_P1Thread1of1ForFork1_~arg.base_8, ~x$w_buff1~0=v_~x$w_buff1~0_51, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_10|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_10|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_145, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_300} AuxVars[] AssignedVars[P1Thread1of1ForFork1___VERIFIER_assert_~expression, ~x$w_buff0~0, P1Thread1of1ForFork1_~arg.offset, P1Thread1of1ForFork1___VERIFIER_assert_#in~expression, P1Thread1of1ForFork1_~arg.base, ~x$w_buff1~0, ~x$w_buff1_used~0, ~x$w_buff0_used~0] because there is no mapped edge [2019-12-07 18:57:36,839 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [784] [784] L787-2-->L787-4: Formula: (let ((.cse1 (= (mod ~x$w_buff1_used~0_In-173691359 256) 0)) (.cse0 (= 0 (mod ~x$r_buff1_thd3~0_In-173691359 256)))) (or (and (= |P2Thread1of1ForFork2_#t~ite15_Out-173691359| ~x$w_buff1~0_In-173691359) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= |P2Thread1of1ForFork2_#t~ite15_Out-173691359| ~x~0_In-173691359)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In-173691359, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-173691359, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-173691359, ~x~0=~x~0_In-173691359} OutVars{P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out-173691359|, ~x$w_buff1~0=~x$w_buff1~0_In-173691359, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-173691359, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-173691359, ~x~0=~x~0_In-173691359} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 18:57:36,839 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [709] [709] L787-4-->L788: Formula: (= v_~x~0_30 |v_P2Thread1of1ForFork2_#t~ite15_10|) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_10|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_9|, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_7|, ~x~0=v_~x~0_30} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, P2Thread1of1ForFork2_#t~ite16, ~x~0] because there is no mapped edge [2019-12-07 18:57:36,839 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L735-2-->L735-5: Formula: (let ((.cse0 (= (mod ~x$r_buff1_thd1~0_In453638749 256) 0)) (.cse1 (= (mod ~x$w_buff1_used~0_In453638749 256) 0)) (.cse2 (= |P0Thread1of1ForFork0_#t~ite3_Out453638749| |P0Thread1of1ForFork0_#t~ite4_Out453638749|))) (or (and (not .cse0) (= |P0Thread1of1ForFork0_#t~ite3_Out453638749| ~x$w_buff1~0_In453638749) (not .cse1) .cse2) (and (or .cse0 .cse1) .cse2 (= |P0Thread1of1ForFork0_#t~ite3_Out453638749| ~x~0_In453638749)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In453638749, ~x$w_buff1_used~0=~x$w_buff1_used~0_In453638749, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In453638749, ~x~0=~x~0_In453638749} OutVars{P0Thread1of1ForFork0_#t~ite3=|P0Thread1of1ForFork0_#t~ite3_Out453638749|, P0Thread1of1ForFork0_#t~ite4=|P0Thread1of1ForFork0_#t~ite4_Out453638749|, ~x$w_buff1~0=~x$w_buff1~0_In453638749, ~x$w_buff1_used~0=~x$w_buff1_used~0_In453638749, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In453638749, ~x~0=~x~0_In453638749} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite3, P0Thread1of1ForFork0_#t~ite4] because there is no mapped edge [2019-12-07 18:57:36,840 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L736-->L736-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff0_used~0_In-1681107126 256))) (.cse0 (= 0 (mod ~x$r_buff0_thd1~0_In-1681107126 256)))) (or (and (not .cse0) (= |P0Thread1of1ForFork0_#t~ite5_Out-1681107126| 0) (not .cse1)) (and (= |P0Thread1of1ForFork0_#t~ite5_Out-1681107126| ~x$w_buff0_used~0_In-1681107126) (or .cse1 .cse0)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-1681107126, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1681107126} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out-1681107126|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-1681107126, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1681107126} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 18:57:36,840 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [780] [780] L788-->L788-2: Formula: (let ((.cse1 (= (mod ~x$w_buff0_used~0_In1756290322 256) 0)) (.cse0 (= 0 (mod ~x$r_buff0_thd3~0_In1756290322 256)))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork2_#t~ite17_Out1756290322| ~x$w_buff0_used~0_In1756290322)) (and (not .cse1) (not .cse0) (= |P2Thread1of1ForFork2_#t~ite17_Out1756290322| 0)))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1756290322, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1756290322} OutVars{~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1756290322, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out1756290322|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1756290322} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 18:57:36,840 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L789-->L789-2: Formula: (let ((.cse0 (= 0 (mod ~x$r_buff0_thd3~0_In-103677559 256))) (.cse1 (= (mod ~x$w_buff0_used~0_In-103677559 256) 0)) (.cse2 (= (mod ~x$w_buff1_used~0_In-103677559 256) 0)) (.cse3 (= 0 (mod ~x$r_buff1_thd3~0_In-103677559 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P2Thread1of1ForFork2_#t~ite18_Out-103677559| ~x$w_buff1_used~0_In-103677559)) (and (= 0 |P2Thread1of1ForFork2_#t~ite18_Out-103677559|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-103677559, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-103677559, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-103677559, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-103677559} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-103677559, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-103677559, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-103677559, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out-103677559|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-103677559} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 18:57:36,841 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [786] [786] L737-->L737-2: Formula: (let ((.cse2 (= 0 (mod ~x$r_buff1_thd1~0_In915708631 256))) (.cse3 (= 0 (mod ~x$w_buff1_used~0_In915708631 256))) (.cse0 (= 0 (mod ~x$r_buff0_thd1~0_In915708631 256))) (.cse1 (= (mod ~x$w_buff0_used~0_In915708631 256) 0))) (or (and (= |P0Thread1of1ForFork0_#t~ite6_Out915708631| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |P0Thread1of1ForFork0_#t~ite6_Out915708631| ~x$w_buff1_used~0_In915708631) (or .cse2 .cse3) (or .cse0 .cse1)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In915708631, ~x$w_buff1_used~0=~x$w_buff1_used~0_In915708631, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In915708631, ~x$w_buff0_used~0=~x$w_buff0_used~0_In915708631} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out915708631|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In915708631, ~x$w_buff1_used~0=~x$w_buff1_used~0_In915708631, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In915708631, ~x$w_buff0_used~0=~x$w_buff0_used~0_In915708631} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 18:57:36,842 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [769] [769] L790-->L790-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff0_used~0_In-311688709 256))) (.cse0 (= 0 (mod ~x$r_buff0_thd3~0_In-311688709 256)))) (or (and (= |P2Thread1of1ForFork2_#t~ite19_Out-311688709| ~x$r_buff0_thd3~0_In-311688709) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= |P2Thread1of1ForFork2_#t~ite19_Out-311688709| 0)))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-311688709, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-311688709} OutVars{~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-311688709, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out-311688709|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-311688709} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 18:57:36,842 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [760] [760] L791-->L791-2: Formula: (let ((.cse0 (= 0 (mod ~x$r_buff0_thd3~0_In1732436677 256))) (.cse1 (= (mod ~x$w_buff0_used~0_In1732436677 256) 0)) (.cse2 (= (mod ~x$w_buff1_used~0_In1732436677 256) 0)) (.cse3 (= 0 (mod ~x$r_buff1_thd3~0_In1732436677 256)))) (or (and (or .cse0 .cse1) (= ~x$r_buff1_thd3~0_In1732436677 |P2Thread1of1ForFork2_#t~ite20_Out1732436677|) (or .cse2 .cse3)) (and (= 0 |P2Thread1of1ForFork2_#t~ite20_Out1732436677|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In1732436677, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1732436677, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1732436677, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1732436677} OutVars{P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out1732436677|, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In1732436677, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1732436677, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1732436677, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1732436677} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 18:57:36,842 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [791] [791] L791-2-->P2EXIT: Formula: (and (= v_~x$r_buff1_thd3~0_48 |v_P2Thread1of1ForFork2_#t~ite20_26|) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_56 1) v_~__unbuffered_cnt~0_55)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_26|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_56} OutVars{P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_25|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_48, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, ~x$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 18:57:36,843 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L765-->L765-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff0_used~0_In-37073091 256))) (.cse0 (= (mod ~x$r_buff0_thd2~0_In-37073091 256) 0))) (or (and (or .cse0 .cse1) (= ~x$w_buff0_used~0_In-37073091 |P1Thread1of1ForFork1_#t~ite11_Out-37073091|)) (and (not .cse1) (= 0 |P1Thread1of1ForFork1_#t~ite11_Out-37073091|) (not .cse0)))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-37073091, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-37073091} OutVars{P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out-37073091|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-37073091, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-37073091} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 18:57:36,844 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L766-->L766-2: Formula: (let ((.cse1 (= (mod ~x$w_buff1_used~0_In1520662730 256) 0)) (.cse0 (= (mod ~x$r_buff1_thd2~0_In1520662730 256) 0)) (.cse2 (= 0 (mod ~x$r_buff0_thd2~0_In1520662730 256))) (.cse3 (= 0 (mod ~x$w_buff0_used~0_In1520662730 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~x$w_buff1_used~0_In1520662730 |P1Thread1of1ForFork1_#t~ite12_Out1520662730|)) (and (= 0 |P1Thread1of1ForFork1_#t~ite12_Out1520662730|) (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3)))))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In1520662730, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In1520662730, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In1520662730, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1520662730} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In1520662730, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In1520662730, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out1520662730|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In1520662730, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1520662730} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 18:57:36,844 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L767-->L768: Formula: (let ((.cse1 (= (mod ~x$r_buff0_thd2~0_In-1916623562 256) 0)) (.cse0 (= 0 (mod ~x$w_buff0_used~0_In-1916623562 256))) (.cse2 (= ~x$r_buff0_thd2~0_Out-1916623562 ~x$r_buff0_thd2~0_In-1916623562))) (or (and (= ~x$r_buff0_thd2~0_Out-1916623562 0) (not .cse0) (not .cse1)) (and .cse1 .cse2) (and .cse0 .cse2))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1916623562, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1916623562} OutVars{P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out-1916623562|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_Out-1916623562, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1916623562} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13, ~x$r_buff0_thd2~0] because there is no mapped edge [2019-12-07 18:57:36,844 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [777] [777] L768-->L768-2: Formula: (let ((.cse2 (= 0 (mod ~x$r_buff1_thd2~0_In2113920738 256))) (.cse3 (= (mod ~x$w_buff1_used~0_In2113920738 256) 0)) (.cse0 (= 0 (mod ~x$r_buff0_thd2~0_In2113920738 256))) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In2113920738 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork1_#t~ite14_Out2113920738| 0)) (and (or .cse2 .cse3) (= |P1Thread1of1ForFork1_#t~ite14_Out2113920738| ~x$r_buff1_thd2~0_In2113920738) (or .cse0 .cse1)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In2113920738, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In2113920738, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In2113920738, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2113920738} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In2113920738, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In2113920738, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In2113920738, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out2113920738|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2113920738} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 18:57:36,844 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [796] [796] L768-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_75 1) v_~__unbuffered_cnt~0_74) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0) (= v_~x$r_buff1_thd2~0_68 |v_P1Thread1of1ForFork1_#t~ite14_40|)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_75, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_40|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_68, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_74, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_39|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~x$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 18:57:36,844 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L738-->L738-2: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff0_used~0_In1437096939 256))) (.cse1 (= 0 (mod ~x$r_buff0_thd1~0_In1437096939 256)))) (or (and (not .cse0) (not .cse1) (= |P0Thread1of1ForFork0_#t~ite7_Out1437096939| 0)) (and (or .cse0 .cse1) (= |P0Thread1of1ForFork0_#t~ite7_Out1437096939| ~x$r_buff0_thd1~0_In1437096939)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In1437096939, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1437096939} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In1437096939, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out1437096939|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1437096939} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7] because there is no mapped edge [2019-12-07 18:57:36,845 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [765] [765] L739-->L739-2: Formula: (let ((.cse2 (= 0 (mod ~x$r_buff0_thd1~0_In-1129599191 256))) (.cse3 (= (mod ~x$w_buff0_used~0_In-1129599191 256) 0)) (.cse1 (= (mod ~x$w_buff1_used~0_In-1129599191 256) 0)) (.cse0 (= (mod ~x$r_buff1_thd1~0_In-1129599191 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P0Thread1of1ForFork0_#t~ite8_Out-1129599191| 0)) (and (= |P0Thread1of1ForFork0_#t~ite8_Out-1129599191| ~x$r_buff1_thd1~0_In-1129599191) (or .cse2 .cse3) (or .cse1 .cse0)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-1129599191, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1129599191, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-1129599191, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1129599191} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-1129599191, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out-1129599191|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1129599191, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-1129599191, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1129599191} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 18:57:36,845 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L739-2-->P0EXIT: Formula: (and (= v_~x$r_buff1_thd1~0_40 |v_P0Thread1of1ForFork0_#t~ite8_18|) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_28 1) v_~__unbuffered_cnt~0_27)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_18|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_28} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_17|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_27, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_40} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, ~x$r_buff1_thd1~0] because there is no mapped edge [2019-12-07 18:57:36,845 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [712] [712] L814-1-->L820: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_6 256))) (= v_~main$tmp_guard0~0_6 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_13) 1 0)) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13} OutVars{ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_5|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 18:57:36,845 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [779] [779] L820-2-->L820-5: Formula: (let ((.cse1 (= |ULTIMATE.start_main_#t~ite25_Out2071808157| |ULTIMATE.start_main_#t~ite24_Out2071808157|)) (.cse0 (= 0 (mod ~x$r_buff1_thd0~0_In2071808157 256))) (.cse2 (= (mod ~x$w_buff1_used~0_In2071808157 256) 0))) (or (and (not .cse0) .cse1 (not .cse2) (= ~x$w_buff1~0_In2071808157 |ULTIMATE.start_main_#t~ite24_Out2071808157|)) (and (= ~x~0_In2071808157 |ULTIMATE.start_main_#t~ite24_Out2071808157|) .cse1 (or .cse0 .cse2)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In2071808157, ~x$w_buff1_used~0=~x$w_buff1_used~0_In2071808157, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In2071808157, ~x~0=~x~0_In2071808157} OutVars{~x$w_buff1~0=~x$w_buff1~0_In2071808157, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out2071808157|, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out2071808157|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In2071808157, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In2071808157, ~x~0=~x~0_In2071808157} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25] because there is no mapped edge [2019-12-07 18:57:36,846 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [782] [782] L821-->L821-2: Formula: (let ((.cse1 (= (mod ~x$w_buff0_used~0_In2045258832 256) 0)) (.cse0 (= 0 (mod ~x$r_buff0_thd0~0_In2045258832 256)))) (or (and (or .cse0 .cse1) (= ~x$w_buff0_used~0_In2045258832 |ULTIMATE.start_main_#t~ite26_Out2045258832|)) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite26_Out2045258832| 0) (not .cse0)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In2045258832, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2045258832} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In2045258832, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out2045258832|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2045258832} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 18:57:36,846 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L822-->L822-2: Formula: (let ((.cse2 (= 0 (mod ~x$r_buff1_thd0~0_In1979958401 256))) (.cse3 (= 0 (mod ~x$w_buff1_used~0_In1979958401 256))) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In1979958401 256))) (.cse0 (= (mod ~x$r_buff0_thd0~0_In1979958401 256) 0))) (or (and (or .cse0 .cse1) (= ~x$w_buff1_used~0_In1979958401 |ULTIMATE.start_main_#t~ite27_Out1979958401|) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= 0 |ULTIMATE.start_main_#t~ite27_Out1979958401|)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In1979958401, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1979958401, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1979958401, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1979958401} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In1979958401, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1979958401, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out1979958401|, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1979958401, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1979958401} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 18:57:36,846 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [774] [774] L823-->L823-2: Formula: (let ((.cse1 (= (mod ~x$r_buff0_thd0~0_In265075884 256) 0)) (.cse0 (= 0 (mod ~x$w_buff0_used~0_In265075884 256)))) (or (and (= ~x$r_buff0_thd0~0_In265075884 |ULTIMATE.start_main_#t~ite28_Out265075884|) (or .cse0 .cse1)) (and (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite28_Out265075884|) (not .cse0)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In265075884, ~x$w_buff0_used~0=~x$w_buff0_used~0_In265075884} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In265075884, ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out265075884|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In265075884} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 18:57:36,847 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L824-->L824-2: Formula: (let ((.cse1 (= (mod ~x$w_buff1_used~0_In-996875936 256) 0)) (.cse0 (= (mod ~x$r_buff1_thd0~0_In-996875936 256) 0)) (.cse2 (= 0 (mod ~x$w_buff0_used~0_In-996875936 256))) (.cse3 (= 0 (mod ~x$r_buff0_thd0~0_In-996875936 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite29_Out-996875936|)) (and (= ~x$r_buff1_thd0~0_In-996875936 |ULTIMATE.start_main_#t~ite29_Out-996875936|) (or .cse1 .cse0) (or .cse2 .cse3)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-996875936, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-996875936, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-996875936, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-996875936} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-996875936, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-996875936|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-996875936, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-996875936, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-996875936} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 18:57:36,849 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [719] [719] L836-->L837: Formula: (and (not (= (mod v_~weak$$choice2~0_27 256) 0)) (= v_~x$r_buff0_thd0~0_87 v_~x$r_buff0_thd0~0_86)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_87, ~weak$$choice2~0=v_~weak$$choice2~0_27} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_86, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_7|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_6|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_6|, ~weak$$choice2~0=v_~weak$$choice2~0_27} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 18:57:36,850 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [807] [807] L839-->L4: Formula: (and (= v_~x$flush_delayed~0_24 0) (= (mod v_~main$tmp_guard1~0_17 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (not (= (mod v_~x$flush_delayed~0_25 256) 0)) (= v_~x$mem_tmp~0_15 v_~x~0_173)) InVars {~x$flush_delayed~0=v_~x$flush_delayed~0_25, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_17, ~x$mem_tmp~0=v_~x$mem_tmp~0_15} OutVars{ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_18|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ~x$flush_delayed~0=v_~x$flush_delayed~0_24, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_17, ~x$mem_tmp~0=v_~x$mem_tmp~0_15, ~x~0=v_~x~0_173, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start___VERIFIER_assert_~expression, ~x$flush_delayed~0, ~x~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:57:36,850 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [801] [801] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_9 0) (= v_ULTIMATE.start___VERIFIER_assert_~expression_9 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_9, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 18:57:36,909 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.12 06:57:36 BasicIcfg [2019-12-07 18:57:36,909 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-07 18:57:36,909 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2019-12-07 18:57:36,909 INFO L271 PluginConnector]: Initializing Witness Printer... [2019-12-07 18:57:36,909 INFO L275 PluginConnector]: Witness Printer initialized [2019-12-07 18:57:36,909 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 06:55:05" (3/4) ... [2019-12-07 18:57:36,911 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2019-12-07 18:57:36,912 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [825] [825] ULTIMATE.startENTRY-->L810: Formula: (let ((.cse0 (store |v_#valid_57| 0 0))) (and (= 0 v_~__unbuffered_p2_EAX~0_23) (= v_~z~0_18 0) (= 0 v_~weak$$choice0~0_14) (= v_~x$flush_delayed~0_41 0) (= 0 v_~x$r_buff0_thd3~0_99) (= v_~x$r_buff1_thd1~0_192 0) (= 0 v_~x$w_buff0~0_203) (= v_~weak$$choice2~0_116 0) (< 0 |v_#StackHeapBarrier_17|) (= |v_#valid_55| (store .cse0 |v_ULTIMATE.start_main_~#t748~0.base_20| 1)) (= 0 v_~x$r_buff1_thd3~0_193) (= 0 v_~x$read_delayed_var~0.base_7) (= 0 v_~x$w_buff1~0_195) (= |v_#length_25| (store |v_#length_26| |v_ULTIMATE.start_main_~#t748~0.base_20| 4)) (= v_~x$mem_tmp~0_22 0) (= v_~__unbuffered_p2_EBX~0_23 0) (= (store |v_#memory_int_24| |v_ULTIMATE.start_main_~#t748~0.base_20| (store (select |v_#memory_int_24| |v_ULTIMATE.start_main_~#t748~0.base_20|) |v_ULTIMATE.start_main_~#t748~0.offset_17| 0)) |v_#memory_int_23|) (= 0 v_~x$r_buff0_thd2~0_205) (= v_~main$tmp_guard1~0_28 0) (= v_~x$r_buff0_thd0~0_335 0) (= 0 v_~x$read_delayed~0_7) (= v_~x$r_buff1_thd0~0_279 0) (= 0 v_~x$w_buff1_used~0_401) (< |v_#StackHeapBarrier_17| |v_ULTIMATE.start_main_~#t748~0.base_20|) (= v_~__unbuffered_cnt~0_145 0) (= |v_ULTIMATE.start_main_~#t748~0.offset_17| 0) (= 0 v_~x$r_buff1_thd2~0_186) (= 0 v_~x$w_buff0_used~0_743) (= |v_#NULL.offset_5| 0) (= 0 v_~x~0_213) (= 0 v_~x$read_delayed_var~0.offset_7) (= v_~main$tmp_guard0~0_22 0) (= 0 v_~x$r_buff0_thd1~0_88) (= 0 (select .cse0 |v_ULTIMATE.start_main_~#t748~0.base_20|)) (= 0 |v_#NULL.base_5|) (= v_~y~0_136 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_17|, #valid=|v_#valid_57|, #memory_int=|v_#memory_int_24|, #length=|v_#length_26|} OutVars{ULTIMATE.start_main_#t~nondet30=|v_ULTIMATE.start_main_#t~nondet30_21|, ~x$w_buff0~0=v_~x$w_buff0~0_203, ULTIMATE.start_main_#t~ite28=|v_ULTIMATE.start_main_#t~ite28_27|, ~x$flush_delayed~0=v_~x$flush_delayed~0_41, ULTIMATE.start_main_#t~ite24=|v_ULTIMATE.start_main_#t~ite24_31|, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_29|, #NULL.offset=|v_#NULL.offset_5|, ULTIMATE.start_main_#t~ite26=|v_ULTIMATE.start_main_#t~ite26_25|, ULTIMATE.start_main_#t~ite49=|v_ULTIMATE.start_main_#t~ite49_40|, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_192, ~x$r_buff0_thd3~0=v_~x$r_buff0_thd3~0_99, ULTIMATE.start_main_#t~ite43=|v_ULTIMATE.start_main_#t~ite43_39|, ULTIMATE.start_main_#t~ite45=|v_ULTIMATE.start_main_#t~ite45_25|, ULTIMATE.start_main_#t~ite50=|v_ULTIMATE.start_main_#t~ite50_46|, ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_36|, ULTIMATE.start_main_~#t749~0.offset=|v_ULTIMATE.start_main_~#t749~0.offset_17|, #length=|v_#length_25|, ~__unbuffered_p2_EAX~0=v_~__unbuffered_p2_EAX~0_23, ULTIMATE.start_main_~#t748~0.base=|v_ULTIMATE.start_main_~#t748~0.base_20|, ~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_335, ~__unbuffered_p2_EBX~0=v_~__unbuffered_p2_EBX~0_23, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_9|, ULTIMATE.start_main_#t~ite39=|v_ULTIMATE.start_main_#t~ite39_43|, ~x$w_buff1~0=v_~x$w_buff1~0_195, ULTIMATE.start_main_#t~ite35=|v_ULTIMATE.start_main_#t~ite35_46|, ULTIMATE.start_main_~#t750~0.offset=|v_ULTIMATE.start_main_~#t750~0.offset_17|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_401, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_186, ULTIMATE.start_main_#t~ite37=|v_ULTIMATE.start_main_#t~ite37_50|, ULTIMATE.start_main_#t~ite33=|v_ULTIMATE.start_main_#t~ite33_111|, ~x$read_delayed_var~0.base=v_~x$read_delayed_var~0.base_7, ~weak$$choice0~0=v_~weak$$choice0~0_14, #StackHeapBarrier=|v_#StackHeapBarrier_17|, ULTIMATE.start_main_#t~ite40=|v_ULTIMATE.start_main_#t~ite40_156|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_145, ~x~0=v_~x~0_213, ~x$r_buff0_thd1~0=v_~x$r_buff0_thd1~0_88, ULTIMATE.start_main_#t~nondet31=|v_ULTIMATE.start_main_#t~nondet31_21|, ULTIMATE.start_main_#t~ite29=|v_ULTIMATE.start_main_#t~ite29_33|, ULTIMATE.start_main_#t~ite25=|v_ULTIMATE.start_main_#t~ite25_27|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_25|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_193, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_28, ULTIMATE.start_main_~#t748~0.offset=|v_ULTIMATE.start_main_~#t748~0.offset_17|, ULTIMATE.start_main_#t~ite27=|v_ULTIMATE.start_main_#t~ite27_33|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_17|, ~x$mem_tmp~0=v_~x$mem_tmp~0_22, ULTIMATE.start_main_#t~ite42=|v_ULTIMATE.start_main_#t~ite42_273|, ULTIMATE.start_main_#t~ite44=|v_ULTIMATE.start_main_#t~ite44_41|, ULTIMATE.start_main_#t~ite51=|v_ULTIMATE.start_main_#t~ite51_34|, ~y~0=v_~y~0_136, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_10|, ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_23|, ULTIMATE.start_main_#t~ite36=|v_ULTIMATE.start_main_#t~ite36_27|, ULTIMATE.start_main_#t~ite38=|v_ULTIMATE.start_main_#t~ite38_54|, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_22, ~x$r_buff1_thd0~0=v_~x$r_buff1_thd0~0_279, ~x$r_buff0_thd2~0=v_~x$r_buff0_thd2~0_205, ULTIMATE.start_main_#t~ite32=|v_ULTIMATE.start_main_#t~ite32_59|, #NULL.base=|v_#NULL.base_5|, ULTIMATE.start_main_#t~ite34=|v_ULTIMATE.start_main_#t~ite34_42|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_743, ULTIMATE.start_main_#t~ite41=|v_ULTIMATE.start_main_#t~ite41_162|, ~x$read_delayed_var~0.offset=v_~x$read_delayed_var~0.offset_7, ULTIMATE.start_main_~#t749~0.base=|v_ULTIMATE.start_main_~#t749~0.base_21|, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_20|, #valid=|v_#valid_55|, #memory_int=|v_#memory_int_23|, ~z~0=v_~z~0_18, ULTIMATE.start_main_~#t750~0.base=|v_ULTIMATE.start_main_~#t750~0.base_21|, ~weak$$choice2~0=v_~weak$$choice2~0_116, ~x$read_delayed~0=v_~x$read_delayed~0_7} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet30, ~x$w_buff0~0, ULTIMATE.start_main_#t~ite28, ~x$flush_delayed~0, ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite47, #NULL.offset, ULTIMATE.start_main_#t~ite26, ULTIMATE.start_main_#t~ite49, ~x$r_buff1_thd1~0, ~x$r_buff0_thd3~0, ULTIMATE.start_main_#t~ite43, ULTIMATE.start_main_#t~ite45, ULTIMATE.start_main_#t~ite50, ULTIMATE.start_main_#t~ite52, ULTIMATE.start_main_~#t749~0.offset, #length, ~__unbuffered_p2_EAX~0, ULTIMATE.start_main_~#t748~0.base, ~x$r_buff0_thd0~0, ~__unbuffered_p2_EBX~0, ULTIMATE.start_main_#t~nondet22, ULTIMATE.start_main_#t~ite39, ~x$w_buff1~0, ULTIMATE.start_main_#t~ite35, ULTIMATE.start_main_~#t750~0.offset, ~x$w_buff1_used~0, ~x$r_buff1_thd2~0, ULTIMATE.start_main_#t~ite37, ULTIMATE.start_main_#t~ite33, ~x$read_delayed_var~0.base, ~weak$$choice0~0, ULTIMATE.start_main_#t~ite40, ~__unbuffered_cnt~0, ~x~0, ~x$r_buff0_thd1~0, ULTIMATE.start_main_#t~nondet31, ULTIMATE.start_main_#t~ite29, ULTIMATE.start_main_#t~ite25, ULTIMATE.start_main_#t~ite46, ~x$r_buff1_thd3~0, ~main$tmp_guard1~0, ULTIMATE.start_main_~#t748~0.offset, ULTIMATE.start_main_#t~ite27, ULTIMATE.start_main_#t~ite48, ~x$mem_tmp~0, ULTIMATE.start_main_#t~ite42, ULTIMATE.start_main_#t~ite44, ULTIMATE.start_main_#t~ite51, ~y~0, ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_#t~nondet23, ULTIMATE.start_main_#t~ite36, ULTIMATE.start_main_#t~ite38, ~main$tmp_guard0~0, ~x$r_buff1_thd0~0, ~x$r_buff0_thd2~0, ULTIMATE.start_main_#t~ite32, #NULL.base, ULTIMATE.start_main_#t~ite34, ~x$w_buff0_used~0, ULTIMATE.start_main_#t~ite41, ~x$read_delayed_var~0.offset, ULTIMATE.start_main_~#t749~0.base, ULTIMATE.start_main_#res, #valid, #memory_int, ~z~0, ULTIMATE.start_main_~#t750~0.base, ~weak$$choice2~0, ~x$read_delayed~0] because there is no mapped edge [2019-12-07 18:57:36,912 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [809] [809] L810-1-->L812: Formula: (and (= (select |v_#valid_37| |v_ULTIMATE.start_main_~#t749~0.base_13|) 0) (= |v_#length_17| (store |v_#length_18| |v_ULTIMATE.start_main_~#t749~0.base_13| 4)) (= |v_#valid_36| (store |v_#valid_37| |v_ULTIMATE.start_main_~#t749~0.base_13| 1)) (not (= |v_ULTIMATE.start_main_~#t749~0.base_13| 0)) (= (store |v_#memory_int_16| |v_ULTIMATE.start_main_~#t749~0.base_13| (store (select |v_#memory_int_16| |v_ULTIMATE.start_main_~#t749~0.base_13|) |v_ULTIMATE.start_main_~#t749~0.offset_11| 1)) |v_#memory_int_15|) (< |v_#StackHeapBarrier_12| |v_ULTIMATE.start_main_~#t749~0.base_13|) (= |v_ULTIMATE.start_main_~#t749~0.offset_11| 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_12|, #valid=|v_#valid_37|, #memory_int=|v_#memory_int_16|, #length=|v_#length_18|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_12|, ULTIMATE.start_main_#t~nondet21=|v_ULTIMATE.start_main_#t~nondet21_6|, ULTIMATE.start_main_~#t749~0.offset=|v_ULTIMATE.start_main_~#t749~0.offset_11|, ULTIMATE.start_main_~#t749~0.base=|v_ULTIMATE.start_main_~#t749~0.base_13|, #valid=|v_#valid_36|, #memory_int=|v_#memory_int_15|, #length=|v_#length_17|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet21, ULTIMATE.start_main_~#t749~0.offset, ULTIMATE.start_main_~#t749~0.base, #valid, #memory_int, #length] because there is no mapped edge [2019-12-07 18:57:36,912 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [803] [803] L812-1-->L814: Formula: (and (= (store |v_#memory_int_14| |v_ULTIMATE.start_main_~#t750~0.base_13| (store (select |v_#memory_int_14| |v_ULTIMATE.start_main_~#t750~0.base_13|) |v_ULTIMATE.start_main_~#t750~0.offset_11| 2)) |v_#memory_int_13|) (= 0 (select |v_#valid_35| |v_ULTIMATE.start_main_~#t750~0.base_13|)) (< |v_#StackHeapBarrier_11| |v_ULTIMATE.start_main_~#t750~0.base_13|) (not (= 0 |v_ULTIMATE.start_main_~#t750~0.base_13|)) (= (store |v_#length_16| |v_ULTIMATE.start_main_~#t750~0.base_13| 4) |v_#length_15|) (= 0 |v_ULTIMATE.start_main_~#t750~0.offset_11|) (= (store |v_#valid_35| |v_ULTIMATE.start_main_~#t750~0.base_13| 1) |v_#valid_34|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_11|, #valid=|v_#valid_35|, #memory_int=|v_#memory_int_14|, #length=|v_#length_16|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_11|, ULTIMATE.start_main_#t~nondet22=|v_ULTIMATE.start_main_#t~nondet22_5|, #valid=|v_#valid_34|, #memory_int=|v_#memory_int_13|, ULTIMATE.start_main_~#t750~0.offset=|v_ULTIMATE.start_main_~#t750~0.offset_11|, #length=|v_#length_15|, ULTIMATE.start_main_~#t750~0.base=|v_ULTIMATE.start_main_~#t750~0.base_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet22, #valid, #memory_int, ULTIMATE.start_main_~#t750~0.offset, #length, ULTIMATE.start_main_~#t750~0.base] because there is no mapped edge [2019-12-07 18:57:36,912 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [745] [745] P1ENTRY-->L4-3: Formula: (and (= |v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_8| (ite (not (and (not (= (mod v_~x$w_buff1_used~0_145 256) 0)) (not (= 0 (mod v_~x$w_buff0_used~0_300 256))))) 1 0)) (= v_P1Thread1of1ForFork1_~arg.offset_8 |v_P1Thread1of1ForFork1_#in~arg.offset_10|) (= v_~x$w_buff0~0_44 v_~x$w_buff1~0_51) (not (= 0 v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_10)) (= 2 v_~x$w_buff0~0_43) (= |v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_8| v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_10) (= v_P1Thread1of1ForFork1_~arg.base_8 |v_P1Thread1of1ForFork1_#in~arg.base_10|) (= 1 v_~x$w_buff0_used~0_300) (= v_~x$w_buff0_used~0_301 v_~x$w_buff1_used~0_145)) InVars {~x$w_buff0~0=v_~x$w_buff0~0_44, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_10|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_10|, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_301} OutVars{P1Thread1of1ForFork1___VERIFIER_assert_~expression=v_P1Thread1of1ForFork1___VERIFIER_assert_~expression_10, ~x$w_buff0~0=v_~x$w_buff0~0_43, P1Thread1of1ForFork1_~arg.offset=v_P1Thread1of1ForFork1_~arg.offset_8, P1Thread1of1ForFork1___VERIFIER_assert_#in~expression=|v_P1Thread1of1ForFork1___VERIFIER_assert_#in~expression_8|, P1Thread1of1ForFork1_~arg.base=v_P1Thread1of1ForFork1_~arg.base_8, ~x$w_buff1~0=v_~x$w_buff1~0_51, P1Thread1of1ForFork1_#in~arg.base=|v_P1Thread1of1ForFork1_#in~arg.base_10|, P1Thread1of1ForFork1_#in~arg.offset=|v_P1Thread1of1ForFork1_#in~arg.offset_10|, ~x$w_buff1_used~0=v_~x$w_buff1_used~0_145, ~x$w_buff0_used~0=v_~x$w_buff0_used~0_300} AuxVars[] AssignedVars[P1Thread1of1ForFork1___VERIFIER_assert_~expression, ~x$w_buff0~0, P1Thread1of1ForFork1_~arg.offset, P1Thread1of1ForFork1___VERIFIER_assert_#in~expression, P1Thread1of1ForFork1_~arg.base, ~x$w_buff1~0, ~x$w_buff1_used~0, ~x$w_buff0_used~0] because there is no mapped edge [2019-12-07 18:57:36,913 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [784] [784] L787-2-->L787-4: Formula: (let ((.cse1 (= (mod ~x$w_buff1_used~0_In-173691359 256) 0)) (.cse0 (= 0 (mod ~x$r_buff1_thd3~0_In-173691359 256)))) (or (and (= |P2Thread1of1ForFork2_#t~ite15_Out-173691359| ~x$w_buff1~0_In-173691359) (not .cse0) (not .cse1)) (and (or .cse1 .cse0) (= |P2Thread1of1ForFork2_#t~ite15_Out-173691359| ~x~0_In-173691359)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In-173691359, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-173691359, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-173691359, ~x~0=~x~0_In-173691359} OutVars{P2Thread1of1ForFork2_#t~ite15=|P2Thread1of1ForFork2_#t~ite15_Out-173691359|, ~x$w_buff1~0=~x$w_buff1~0_In-173691359, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-173691359, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-173691359, ~x~0=~x~0_In-173691359} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15] because there is no mapped edge [2019-12-07 18:57:36,913 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [709] [709] L787-4-->L788: Formula: (= v_~x~0_30 |v_P2Thread1of1ForFork2_#t~ite15_10|) InVars {P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_10|} OutVars{P2Thread1of1ForFork2_#t~ite15=|v_P2Thread1of1ForFork2_#t~ite15_9|, P2Thread1of1ForFork2_#t~ite16=|v_P2Thread1of1ForFork2_#t~ite16_7|, ~x~0=v_~x~0_30} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite15, P2Thread1of1ForFork2_#t~ite16, ~x~0] because there is no mapped edge [2019-12-07 18:57:36,914 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [776] [776] L735-2-->L735-5: Formula: (let ((.cse0 (= (mod ~x$r_buff1_thd1~0_In453638749 256) 0)) (.cse1 (= (mod ~x$w_buff1_used~0_In453638749 256) 0)) (.cse2 (= |P0Thread1of1ForFork0_#t~ite3_Out453638749| |P0Thread1of1ForFork0_#t~ite4_Out453638749|))) (or (and (not .cse0) (= |P0Thread1of1ForFork0_#t~ite3_Out453638749| ~x$w_buff1~0_In453638749) (not .cse1) .cse2) (and (or .cse0 .cse1) .cse2 (= |P0Thread1of1ForFork0_#t~ite3_Out453638749| ~x~0_In453638749)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In453638749, ~x$w_buff1_used~0=~x$w_buff1_used~0_In453638749, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In453638749, ~x~0=~x~0_In453638749} OutVars{P0Thread1of1ForFork0_#t~ite3=|P0Thread1of1ForFork0_#t~ite3_Out453638749|, P0Thread1of1ForFork0_#t~ite4=|P0Thread1of1ForFork0_#t~ite4_Out453638749|, ~x$w_buff1~0=~x$w_buff1~0_In453638749, ~x$w_buff1_used~0=~x$w_buff1_used~0_In453638749, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In453638749, ~x~0=~x~0_In453638749} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite3, P0Thread1of1ForFork0_#t~ite4] because there is no mapped edge [2019-12-07 18:57:36,914 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [764] [764] L736-->L736-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff0_used~0_In-1681107126 256))) (.cse0 (= 0 (mod ~x$r_buff0_thd1~0_In-1681107126 256)))) (or (and (not .cse0) (= |P0Thread1of1ForFork0_#t~ite5_Out-1681107126| 0) (not .cse1)) (and (= |P0Thread1of1ForFork0_#t~ite5_Out-1681107126| ~x$w_buff0_used~0_In-1681107126) (or .cse1 .cse0)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-1681107126, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1681107126} OutVars{P0Thread1of1ForFork0_#t~ite5=|P0Thread1of1ForFork0_#t~ite5_Out-1681107126|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-1681107126, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1681107126} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite5] because there is no mapped edge [2019-12-07 18:57:36,914 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [780] [780] L788-->L788-2: Formula: (let ((.cse1 (= (mod ~x$w_buff0_used~0_In1756290322 256) 0)) (.cse0 (= 0 (mod ~x$r_buff0_thd3~0_In1756290322 256)))) (or (and (or .cse0 .cse1) (= |P2Thread1of1ForFork2_#t~ite17_Out1756290322| ~x$w_buff0_used~0_In1756290322)) (and (not .cse1) (not .cse0) (= |P2Thread1of1ForFork2_#t~ite17_Out1756290322| 0)))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1756290322, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1756290322} OutVars{~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1756290322, P2Thread1of1ForFork2_#t~ite17=|P2Thread1of1ForFork2_#t~ite17_Out1756290322|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1756290322} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite17] because there is no mapped edge [2019-12-07 18:57:36,914 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [775] [775] L789-->L789-2: Formula: (let ((.cse0 (= 0 (mod ~x$r_buff0_thd3~0_In-103677559 256))) (.cse1 (= (mod ~x$w_buff0_used~0_In-103677559 256) 0)) (.cse2 (= (mod ~x$w_buff1_used~0_In-103677559 256) 0)) (.cse3 (= 0 (mod ~x$r_buff1_thd3~0_In-103677559 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= |P2Thread1of1ForFork2_#t~ite18_Out-103677559| ~x$w_buff1_used~0_In-103677559)) (and (= 0 |P2Thread1of1ForFork2_#t~ite18_Out-103677559|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In-103677559, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-103677559, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-103677559, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-103677559} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In-103677559, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In-103677559, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-103677559, P2Thread1of1ForFork2_#t~ite18=|P2Thread1of1ForFork2_#t~ite18_Out-103677559|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-103677559} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite18] because there is no mapped edge [2019-12-07 18:57:36,915 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [786] [786] L737-->L737-2: Formula: (let ((.cse2 (= 0 (mod ~x$r_buff1_thd1~0_In915708631 256))) (.cse3 (= 0 (mod ~x$w_buff1_used~0_In915708631 256))) (.cse0 (= 0 (mod ~x$r_buff0_thd1~0_In915708631 256))) (.cse1 (= (mod ~x$w_buff0_used~0_In915708631 256) 0))) (or (and (= |P0Thread1of1ForFork0_#t~ite6_Out915708631| 0) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))) (and (= |P0Thread1of1ForFork0_#t~ite6_Out915708631| ~x$w_buff1_used~0_In915708631) (or .cse2 .cse3) (or .cse0 .cse1)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In915708631, ~x$w_buff1_used~0=~x$w_buff1_used~0_In915708631, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In915708631, ~x$w_buff0_used~0=~x$w_buff0_used~0_In915708631} OutVars{P0Thread1of1ForFork0_#t~ite6=|P0Thread1of1ForFork0_#t~ite6_Out915708631|, ~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In915708631, ~x$w_buff1_used~0=~x$w_buff1_used~0_In915708631, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In915708631, ~x$w_buff0_used~0=~x$w_buff0_used~0_In915708631} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite6] because there is no mapped edge [2019-12-07 18:57:36,915 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [769] [769] L790-->L790-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff0_used~0_In-311688709 256))) (.cse0 (= 0 (mod ~x$r_buff0_thd3~0_In-311688709 256)))) (or (and (= |P2Thread1of1ForFork2_#t~ite19_Out-311688709| ~x$r_buff0_thd3~0_In-311688709) (or .cse0 .cse1)) (and (not .cse1) (not .cse0) (= |P2Thread1of1ForFork2_#t~ite19_Out-311688709| 0)))) InVars {~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-311688709, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-311688709} OutVars{~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In-311688709, P2Thread1of1ForFork2_#t~ite19=|P2Thread1of1ForFork2_#t~ite19_Out-311688709|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-311688709} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite19] because there is no mapped edge [2019-12-07 18:57:36,915 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [760] [760] L791-->L791-2: Formula: (let ((.cse0 (= 0 (mod ~x$r_buff0_thd3~0_In1732436677 256))) (.cse1 (= (mod ~x$w_buff0_used~0_In1732436677 256) 0)) (.cse2 (= (mod ~x$w_buff1_used~0_In1732436677 256) 0)) (.cse3 (= 0 (mod ~x$r_buff1_thd3~0_In1732436677 256)))) (or (and (or .cse0 .cse1) (= ~x$r_buff1_thd3~0_In1732436677 |P2Thread1of1ForFork2_#t~ite20_Out1732436677|) (or .cse2 .cse3)) (and (= 0 |P2Thread1of1ForFork2_#t~ite20_Out1732436677|) (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3)))))) InVars {~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In1732436677, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1732436677, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1732436677, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1732436677} OutVars{P2Thread1of1ForFork2_#t~ite20=|P2Thread1of1ForFork2_#t~ite20_Out1732436677|, ~x$r_buff1_thd3~0=~x$r_buff1_thd3~0_In1732436677, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1732436677, ~x$r_buff0_thd3~0=~x$r_buff0_thd3~0_In1732436677, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1732436677} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20] because there is no mapped edge [2019-12-07 18:57:36,915 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [791] [791] L791-2-->P2EXIT: Formula: (and (= v_~x$r_buff1_thd3~0_48 |v_P2Thread1of1ForFork2_#t~ite20_26|) (= 0 |v_P2Thread1of1ForFork2_#res.base_3|) (= |v_P2Thread1of1ForFork2_#res.offset_3| 0) (= (+ v_~__unbuffered_cnt~0_56 1) v_~__unbuffered_cnt~0_55)) InVars {P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_26|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_56} OutVars{P2Thread1of1ForFork2_#t~ite20=|v_P2Thread1of1ForFork2_#t~ite20_25|, ~x$r_buff1_thd3~0=v_~x$r_buff1_thd3~0_48, P2Thread1of1ForFork2_#res.base=|v_P2Thread1of1ForFork2_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_55, P2Thread1of1ForFork2_#res.offset=|v_P2Thread1of1ForFork2_#res.offset_3|} AuxVars[] AssignedVars[P2Thread1of1ForFork2_#t~ite20, ~x$r_buff1_thd3~0, P2Thread1of1ForFork2_#res.base, ~__unbuffered_cnt~0, P2Thread1of1ForFork2_#res.offset] because there is no mapped edge [2019-12-07 18:57:36,916 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [773] [773] L765-->L765-2: Formula: (let ((.cse1 (= 0 (mod ~x$w_buff0_used~0_In-37073091 256))) (.cse0 (= (mod ~x$r_buff0_thd2~0_In-37073091 256) 0))) (or (and (or .cse0 .cse1) (= ~x$w_buff0_used~0_In-37073091 |P1Thread1of1ForFork1_#t~ite11_Out-37073091|)) (and (not .cse1) (= 0 |P1Thread1of1ForFork1_#t~ite11_Out-37073091|) (not .cse0)))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-37073091, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-37073091} OutVars{P1Thread1of1ForFork1_#t~ite11=|P1Thread1of1ForFork1_#t~ite11_Out-37073091|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-37073091, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-37073091} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite11] because there is no mapped edge [2019-12-07 18:57:36,916 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [781] [781] L766-->L766-2: Formula: (let ((.cse1 (= (mod ~x$w_buff1_used~0_In1520662730 256) 0)) (.cse0 (= (mod ~x$r_buff1_thd2~0_In1520662730 256) 0)) (.cse2 (= 0 (mod ~x$r_buff0_thd2~0_In1520662730 256))) (.cse3 (= 0 (mod ~x$w_buff0_used~0_In1520662730 256)))) (or (and (or .cse0 .cse1) (or .cse2 .cse3) (= ~x$w_buff1_used~0_In1520662730 |P1Thread1of1ForFork1_#t~ite12_Out1520662730|)) (and (= 0 |P1Thread1of1ForFork1_#t~ite12_Out1520662730|) (or (and (not .cse1) (not .cse0)) (and (not .cse2) (not .cse3)))))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In1520662730, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In1520662730, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In1520662730, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1520662730} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In1520662730, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In1520662730, P1Thread1of1ForFork1_#t~ite12=|P1Thread1of1ForFork1_#t~ite12_Out1520662730|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In1520662730, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1520662730} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite12] because there is no mapped edge [2019-12-07 18:57:36,916 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [761] [761] L767-->L768: Formula: (let ((.cse1 (= (mod ~x$r_buff0_thd2~0_In-1916623562 256) 0)) (.cse0 (= 0 (mod ~x$w_buff0_used~0_In-1916623562 256))) (.cse2 (= ~x$r_buff0_thd2~0_Out-1916623562 ~x$r_buff0_thd2~0_In-1916623562))) (or (and (= ~x$r_buff0_thd2~0_Out-1916623562 0) (not .cse0) (not .cse1)) (and .cse1 .cse2) (and .cse0 .cse2))) InVars {~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In-1916623562, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1916623562} OutVars{P1Thread1of1ForFork1_#t~ite13=|P1Thread1of1ForFork1_#t~ite13_Out-1916623562|, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_Out-1916623562, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1916623562} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite13, ~x$r_buff0_thd2~0] because there is no mapped edge [2019-12-07 18:57:36,917 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [777] [777] L768-->L768-2: Formula: (let ((.cse2 (= 0 (mod ~x$r_buff1_thd2~0_In2113920738 256))) (.cse3 (= (mod ~x$w_buff1_used~0_In2113920738 256) 0)) (.cse0 (= 0 (mod ~x$r_buff0_thd2~0_In2113920738 256))) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In2113920738 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P1Thread1of1ForFork1_#t~ite14_Out2113920738| 0)) (and (or .cse2 .cse3) (= |P1Thread1of1ForFork1_#t~ite14_Out2113920738| ~x$r_buff1_thd2~0_In2113920738) (or .cse0 .cse1)))) InVars {~x$w_buff1_used~0=~x$w_buff1_used~0_In2113920738, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In2113920738, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In2113920738, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2113920738} OutVars{~x$w_buff1_used~0=~x$w_buff1_used~0_In2113920738, ~x$r_buff1_thd2~0=~x$r_buff1_thd2~0_In2113920738, ~x$r_buff0_thd2~0=~x$r_buff0_thd2~0_In2113920738, P1Thread1of1ForFork1_#t~ite14=|P1Thread1of1ForFork1_#t~ite14_Out2113920738|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2113920738} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#t~ite14] because there is no mapped edge [2019-12-07 18:57:36,917 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [796] [796] L768-2-->P1EXIT: Formula: (and (= 0 |v_P1Thread1of1ForFork1_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_75 1) v_~__unbuffered_cnt~0_74) (= |v_P1Thread1of1ForFork1_#res.offset_3| 0) (= v_~x$r_buff1_thd2~0_68 |v_P1Thread1of1ForFork1_#t~ite14_40|)) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_75, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_40|} OutVars{P1Thread1of1ForFork1_#res.offset=|v_P1Thread1of1ForFork1_#res.offset_3|, ~x$r_buff1_thd2~0=v_~x$r_buff1_thd2~0_68, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_74, P1Thread1of1ForFork1_#t~ite14=|v_P1Thread1of1ForFork1_#t~ite14_39|, P1Thread1of1ForFork1_#res.base=|v_P1Thread1of1ForFork1_#res.base_3|} AuxVars[] AssignedVars[P1Thread1of1ForFork1_#res.offset, ~x$r_buff1_thd2~0, ~__unbuffered_cnt~0, P1Thread1of1ForFork1_#t~ite14, P1Thread1of1ForFork1_#res.base] because there is no mapped edge [2019-12-07 18:57:36,917 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [767] [767] L738-->L738-2: Formula: (let ((.cse0 (= 0 (mod ~x$w_buff0_used~0_In1437096939 256))) (.cse1 (= 0 (mod ~x$r_buff0_thd1~0_In1437096939 256)))) (or (and (not .cse0) (not .cse1) (= |P0Thread1of1ForFork0_#t~ite7_Out1437096939| 0)) (and (or .cse0 .cse1) (= |P0Thread1of1ForFork0_#t~ite7_Out1437096939| ~x$r_buff0_thd1~0_In1437096939)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In1437096939, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1437096939} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In1437096939, P0Thread1of1ForFork0_#t~ite7=|P0Thread1of1ForFork0_#t~ite7_Out1437096939|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1437096939} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite7] because there is no mapped edge [2019-12-07 18:57:36,917 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [765] [765] L739-->L739-2: Formula: (let ((.cse2 (= 0 (mod ~x$r_buff0_thd1~0_In-1129599191 256))) (.cse3 (= (mod ~x$w_buff0_used~0_In-1129599191 256) 0)) (.cse1 (= (mod ~x$w_buff1_used~0_In-1129599191 256) 0)) (.cse0 (= (mod ~x$r_buff1_thd1~0_In-1129599191 256) 0))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= |P0Thread1of1ForFork0_#t~ite8_Out-1129599191| 0)) (and (= |P0Thread1of1ForFork0_#t~ite8_Out-1129599191| ~x$r_buff1_thd1~0_In-1129599191) (or .cse2 .cse3) (or .cse1 .cse0)))) InVars {~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-1129599191, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1129599191, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-1129599191, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1129599191} OutVars{~x$r_buff0_thd1~0=~x$r_buff0_thd1~0_In-1129599191, P0Thread1of1ForFork0_#t~ite8=|P0Thread1of1ForFork0_#t~ite8_Out-1129599191|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-1129599191, ~x$r_buff1_thd1~0=~x$r_buff1_thd1~0_In-1129599191, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-1129599191} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#t~ite8] because there is no mapped edge [2019-12-07 18:57:36,917 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [788] [788] L739-2-->P0EXIT: Formula: (and (= v_~x$r_buff1_thd1~0_40 |v_P0Thread1of1ForFork0_#t~ite8_18|) (= |v_P0Thread1of1ForFork0_#res.offset_3| 0) (= 0 |v_P0Thread1of1ForFork0_#res.base_3|) (= (+ v_~__unbuffered_cnt~0_28 1) v_~__unbuffered_cnt~0_27)) InVars {P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_18|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_28} OutVars{P0Thread1of1ForFork0_#res.offset=|v_P0Thread1of1ForFork0_#res.offset_3|, P0Thread1of1ForFork0_#t~ite8=|v_P0Thread1of1ForFork0_#t~ite8_17|, P0Thread1of1ForFork0_#res.base=|v_P0Thread1of1ForFork0_#res.base_3|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_27, ~x$r_buff1_thd1~0=v_~x$r_buff1_thd1~0_40} AuxVars[] AssignedVars[P0Thread1of1ForFork0_#res.offset, P0Thread1of1ForFork0_#t~ite8, P0Thread1of1ForFork0_#res.base, ~__unbuffered_cnt~0, ~x$r_buff1_thd1~0] because there is no mapped edge [2019-12-07 18:57:36,917 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [712] [712] L814-1-->L820: Formula: (and (not (= 0 (mod v_~main$tmp_guard0~0_6 256))) (= v_~main$tmp_guard0~0_6 (ite (= 0 (ite (= 3 v_~__unbuffered_cnt~0_13) 1 0)) 0 1))) InVars {~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13} OutVars{ULTIMATE.start_main_#t~nondet23=|v_ULTIMATE.start_main_#t~nondet23_5|, ~__unbuffered_cnt~0=v_~__unbuffered_cnt~0_13, ~main$tmp_guard0~0=v_~main$tmp_guard0~0_6} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet23, ~main$tmp_guard0~0] because there is no mapped edge [2019-12-07 18:57:36,917 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [779] [779] L820-2-->L820-5: Formula: (let ((.cse1 (= |ULTIMATE.start_main_#t~ite25_Out2071808157| |ULTIMATE.start_main_#t~ite24_Out2071808157|)) (.cse0 (= 0 (mod ~x$r_buff1_thd0~0_In2071808157 256))) (.cse2 (= (mod ~x$w_buff1_used~0_In2071808157 256) 0))) (or (and (not .cse0) .cse1 (not .cse2) (= ~x$w_buff1~0_In2071808157 |ULTIMATE.start_main_#t~ite24_Out2071808157|)) (and (= ~x~0_In2071808157 |ULTIMATE.start_main_#t~ite24_Out2071808157|) .cse1 (or .cse0 .cse2)))) InVars {~x$w_buff1~0=~x$w_buff1~0_In2071808157, ~x$w_buff1_used~0=~x$w_buff1_used~0_In2071808157, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In2071808157, ~x~0=~x~0_In2071808157} OutVars{~x$w_buff1~0=~x$w_buff1~0_In2071808157, ULTIMATE.start_main_#t~ite24=|ULTIMATE.start_main_#t~ite24_Out2071808157|, ULTIMATE.start_main_#t~ite25=|ULTIMATE.start_main_#t~ite25_Out2071808157|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In2071808157, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In2071808157, ~x~0=~x~0_In2071808157} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite24, ULTIMATE.start_main_#t~ite25] because there is no mapped edge [2019-12-07 18:57:36,918 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [782] [782] L821-->L821-2: Formula: (let ((.cse1 (= (mod ~x$w_buff0_used~0_In2045258832 256) 0)) (.cse0 (= 0 (mod ~x$r_buff0_thd0~0_In2045258832 256)))) (or (and (or .cse0 .cse1) (= ~x$w_buff0_used~0_In2045258832 |ULTIMATE.start_main_#t~ite26_Out2045258832|)) (and (not .cse1) (= |ULTIMATE.start_main_#t~ite26_Out2045258832| 0) (not .cse0)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In2045258832, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2045258832} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In2045258832, ULTIMATE.start_main_#t~ite26=|ULTIMATE.start_main_#t~ite26_Out2045258832|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In2045258832} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite26] because there is no mapped edge [2019-12-07 18:57:36,918 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [771] [771] L822-->L822-2: Formula: (let ((.cse2 (= 0 (mod ~x$r_buff1_thd0~0_In1979958401 256))) (.cse3 (= 0 (mod ~x$w_buff1_used~0_In1979958401 256))) (.cse1 (= 0 (mod ~x$w_buff0_used~0_In1979958401 256))) (.cse0 (= (mod ~x$r_buff0_thd0~0_In1979958401 256) 0))) (or (and (or .cse0 .cse1) (= ~x$w_buff1_used~0_In1979958401 |ULTIMATE.start_main_#t~ite27_Out1979958401|) (or .cse2 .cse3)) (and (or (and (not .cse2) (not .cse3)) (and (not .cse1) (not .cse0))) (= 0 |ULTIMATE.start_main_#t~ite27_Out1979958401|)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In1979958401, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1979958401, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1979958401, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1979958401} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In1979958401, ~x$w_buff1_used~0=~x$w_buff1_used~0_In1979958401, ULTIMATE.start_main_#t~ite27=|ULTIMATE.start_main_#t~ite27_Out1979958401|, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In1979958401, ~x$w_buff0_used~0=~x$w_buff0_used~0_In1979958401} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite27] because there is no mapped edge [2019-12-07 18:57:36,918 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [774] [774] L823-->L823-2: Formula: (let ((.cse1 (= (mod ~x$r_buff0_thd0~0_In265075884 256) 0)) (.cse0 (= 0 (mod ~x$w_buff0_used~0_In265075884 256)))) (or (and (= ~x$r_buff0_thd0~0_In265075884 |ULTIMATE.start_main_#t~ite28_Out265075884|) (or .cse0 .cse1)) (and (not .cse1) (= 0 |ULTIMATE.start_main_#t~ite28_Out265075884|) (not .cse0)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In265075884, ~x$w_buff0_used~0=~x$w_buff0_used~0_In265075884} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In265075884, ULTIMATE.start_main_#t~ite28=|ULTIMATE.start_main_#t~ite28_Out265075884|, ~x$w_buff0_used~0=~x$w_buff0_used~0_In265075884} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite28] because there is no mapped edge [2019-12-07 18:57:36,919 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [766] [766] L824-->L824-2: Formula: (let ((.cse1 (= (mod ~x$w_buff1_used~0_In-996875936 256) 0)) (.cse0 (= (mod ~x$r_buff1_thd0~0_In-996875936 256) 0)) (.cse2 (= 0 (mod ~x$w_buff0_used~0_In-996875936 256))) (.cse3 (= 0 (mod ~x$r_buff0_thd0~0_In-996875936 256)))) (or (and (or (and (not .cse0) (not .cse1)) (and (not .cse2) (not .cse3))) (= 0 |ULTIMATE.start_main_#t~ite29_Out-996875936|)) (and (= ~x$r_buff1_thd0~0_In-996875936 |ULTIMATE.start_main_#t~ite29_Out-996875936|) (or .cse1 .cse0) (or .cse2 .cse3)))) InVars {~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-996875936, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-996875936, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-996875936, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-996875936} OutVars{~x$r_buff0_thd0~0=~x$r_buff0_thd0~0_In-996875936, ULTIMATE.start_main_#t~ite29=|ULTIMATE.start_main_#t~ite29_Out-996875936|, ~x$w_buff1_used~0=~x$w_buff1_used~0_In-996875936, ~x$r_buff1_thd0~0=~x$r_buff1_thd0~0_In-996875936, ~x$w_buff0_used~0=~x$w_buff0_used~0_In-996875936} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite29] because there is no mapped edge [2019-12-07 18:57:36,921 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [719] [719] L836-->L837: Formula: (and (not (= (mod v_~weak$$choice2~0_27 256) 0)) (= v_~x$r_buff0_thd0~0_87 v_~x$r_buff0_thd0~0_86)) InVars {~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_87, ~weak$$choice2~0=v_~weak$$choice2~0_27} OutVars{~x$r_buff0_thd0~0=v_~x$r_buff0_thd0~0_86, ULTIMATE.start_main_#t~ite47=|v_ULTIMATE.start_main_#t~ite47_7|, ULTIMATE.start_main_#t~ite46=|v_ULTIMATE.start_main_#t~ite46_6|, ULTIMATE.start_main_#t~ite48=|v_ULTIMATE.start_main_#t~ite48_6|, ~weak$$choice2~0=v_~weak$$choice2~0_27} AuxVars[] AssignedVars[~x$r_buff0_thd0~0, ULTIMATE.start_main_#t~ite47, ULTIMATE.start_main_#t~ite46, ULTIMATE.start_main_#t~ite48] because there is no mapped edge [2019-12-07 18:57:36,922 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [807] [807] L839-->L4: Formula: (and (= v_~x$flush_delayed~0_24 0) (= (mod v_~main$tmp_guard1~0_17 256) |v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|) (not (= (mod v_~x$flush_delayed~0_25 256) 0)) (= v_~x$mem_tmp~0_15 v_~x~0_173)) InVars {~x$flush_delayed~0=v_~x$flush_delayed~0_25, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_17, ~x$mem_tmp~0=v_~x$mem_tmp~0_15} OutVars{ULTIMATE.start_main_#t~ite52=|v_ULTIMATE.start_main_#t~ite52_18|, ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_11, ~x$flush_delayed~0=v_~x$flush_delayed~0_24, ~main$tmp_guard1~0=v_~main$tmp_guard1~0_17, ~x$mem_tmp~0=v_~x$mem_tmp~0_15, ~x~0=v_~x~0_173, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~ite52, ULTIMATE.start___VERIFIER_assert_~expression, ~x$flush_delayed~0, ~x~0, ULTIMATE.start___VERIFIER_assert_#in~expression] because there is no mapped edge [2019-12-07 18:57:36,922 WARN L123 codingBacktranslator]: Skipped backtranslation of ATE [801] [801] L4-->ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: (and (= v_ULTIMATE.start___VERIFIER_assert_~expression_9 0) (= v_ULTIMATE.start___VERIFIER_assert_~expression_9 |v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|)) InVars {ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} OutVars{ULTIMATE.start___VERIFIER_assert_~expression=v_ULTIMATE.start___VERIFIER_assert_~expression_9, ULTIMATE.start___VERIFIER_assert_#in~expression=|v_ULTIMATE.start___VERIFIER_assert_#in~expression_4|} AuxVars[] AssignedVars[ULTIMATE.start___VERIFIER_assert_~expression] because there is no mapped edge [2019-12-07 18:57:36,977 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/run_dir_c6caa1d2-8da2-49a6-9013-ef55de0dbf83/bin/uautomizer/witness.graphml [2019-12-07 18:57:36,977 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2019-12-07 18:57:36,978 INFO L168 Benchmark]: Toolchain (without parser) took 151983.70 ms. Allocated memory was 1.0 GB in the beginning and 7.3 GB in the end (delta: 6.3 GB). Free memory was 934.4 MB in the beginning and 6.3 GB in the end (delta: -5.4 GB). Peak memory consumption was 897.0 MB. Max. memory is 11.5 GB. [2019-12-07 18:57:36,978 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 955.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:57:36,979 INFO L168 Benchmark]: CACSL2BoogieTranslator took 405.88 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 105.4 MB). Free memory was 934.4 MB in the beginning and 1.1 GB in the end (delta: -137.6 MB). Peak memory consumption was 18.4 MB. Max. memory is 11.5 GB. [2019-12-07 18:57:36,979 INFO L168 Benchmark]: Boogie Procedure Inliner took 39.00 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2019-12-07 18:57:36,979 INFO L168 Benchmark]: Boogie Preprocessor took 26.13 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2019-12-07 18:57:36,979 INFO L168 Benchmark]: RCFGBuilder took 408.55 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 48.7 MB). Peak memory consumption was 48.7 MB. Max. memory is 11.5 GB. [2019-12-07 18:57:36,979 INFO L168 Benchmark]: TraceAbstraction took 151032.64 ms. Allocated memory was 1.1 GB in the beginning and 7.3 GB in the end (delta: 6.2 GB). Free memory was 1.0 GB in the beginning and 6.4 GB in the end (delta: -5.4 GB). Peak memory consumption was 826.5 MB. Max. memory is 11.5 GB. [2019-12-07 18:57:36,980 INFO L168 Benchmark]: Witness Printer took 67.95 ms. Allocated memory is still 7.3 GB. Free memory was 6.4 GB in the beginning and 6.3 GB in the end (delta: 37.9 MB). Peak memory consumption was 37.9 MB. Max. memory is 11.5 GB. [2019-12-07 18:57:36,981 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 955.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 405.88 ms. Allocated memory was 1.0 GB in the beginning and 1.1 GB in the end (delta: 105.4 MB). Free memory was 934.4 MB in the beginning and 1.1 GB in the end (delta: -137.6 MB). Peak memory consumption was 18.4 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 39.00 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 26.13 ms. Allocated memory is still 1.1 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 408.55 ms. Allocated memory is still 1.1 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 48.7 MB). Peak memory consumption was 48.7 MB. Max. memory is 11.5 GB. * TraceAbstraction took 151032.64 ms. Allocated memory was 1.1 GB in the beginning and 7.3 GB in the end (delta: 6.2 GB). Free memory was 1.0 GB in the beginning and 6.4 GB in the end (delta: -5.4 GB). Peak memory consumption was 826.5 MB. Max. memory is 11.5 GB. * Witness Printer took 67.95 ms. Allocated memory is still 7.3 GB. Free memory was 6.4 GB in the beginning and 6.3 GB in the end (delta: 37.9 MB). Peak memory consumption was 37.9 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks LbeTime: 2.9s, 175 ProgramPointsBefore, 95 ProgramPointsAfterwards, 212 TransitionsBefore, 107 TransitionsAfterwards, 17074 CoEnabledTransitionPairs, 7 FixpointIterations, 32 TrivialSequentialCompositions, 42 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 37 ConcurrentYvCompositions, 29 ChoiceCompositions, 5405 VarBasedMoverChecksPositive, 232 VarBasedMoverChecksNegative, 72 SemBasedMoverChecksPositive, 228 SemBasedMoverChecksNegative, 0 SemBasedMoverChecksUnknown, SemBasedMoverCheckTime: 0.7s, 0 MoverChecksTotal, 79058 CheckedPairsTotal, 111 TotalNumberOfCompositions - CounterExampleResult [Line: 4]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L810] FCALL, FORK 0 pthread_create(&t748, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0, z=0] [L812] FCALL, FORK 0 pthread_create(&t749, ((void *)0), P1, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=0, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=0, z=0] [L814] FCALL, FORK 0 pthread_create(&t750, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=0, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=0, z=0] [L754] 2 x$r_buff1_thd0 = x$r_buff0_thd0 [L755] 2 x$r_buff1_thd1 = x$r_buff0_thd1 [L756] 2 x$r_buff1_thd2 = x$r_buff0_thd2 [L757] 2 x$r_buff1_thd3 = x$r_buff0_thd3 [L758] 2 x$r_buff0_thd2 = (_Bool)1 [L761] 2 y = 1 VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=0, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=1, z=0] [L778] 3 y = 2 [L781] 3 __unbuffered_p2_EAX = y [L784] 3 __unbuffered_p2_EBX = z VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=0, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=0] [L729] 1 z = 1 [L732] 1 x = 1 VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L787] 3 x$w_buff0_used && x$r_buff0_thd3 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd3 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L735] EXPR 1 x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) VAL [__unbuffered_cnt=0, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L735] 1 x = x$w_buff0_used && x$r_buff0_thd1 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd1 ? x$w_buff1 : x) [L788] 3 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : x$w_buff0_used [L736] 1 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$w_buff0_used [L737] 1 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd1 || x$w_buff1_used && x$r_buff1_thd1 ? (_Bool)0 : x$w_buff1_used [L789] 3 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd3 || x$w_buff1_used && x$r_buff1_thd3 ? (_Bool)0 : x$w_buff1_used [L790] 3 x$r_buff0_thd3 = x$w_buff0_used && x$r_buff0_thd3 ? (_Bool)0 : x$r_buff0_thd3 [L764] EXPR 2 x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) VAL [\result={0:0}, __unbuffered_cnt=1, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=1, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=1, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L764] 2 x = x$w_buff0_used && x$r_buff0_thd2 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd2 ? x$w_buff1 : x) [L765] 2 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd2 ? (_Bool)0 : x$w_buff0_used [L766] 2 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd2 || x$w_buff1_used && x$r_buff1_thd2 ? (_Bool)0 : x$w_buff1_used [L738] 1 x$r_buff0_thd1 = x$w_buff0_used && x$r_buff0_thd1 ? (_Bool)0 : x$r_buff0_thd1 [L820] EXPR 0 x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=0, weak$$choice2=0, x=2, x$flush_delayed=0, x$mem_tmp=0, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L820] 0 x = x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : (x$w_buff1_used && x$r_buff1_thd0 ? x$w_buff1 : x) [L821] 0 x$w_buff0_used = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used [L822] 0 x$w_buff1_used = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$w_buff1_used [L823] 0 x$r_buff0_thd0 = x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$r_buff0_thd0 [L824] 0 x$r_buff1_thd0 = x$w_buff0_used && x$r_buff0_thd0 || x$w_buff1_used && x$r_buff1_thd0 ? (_Bool)0 : x$r_buff1_thd0 [L827] 0 weak$$choice0 = __VERIFIER_nondet_bool() [L828] 0 weak$$choice2 = __VERIFIER_nondet_bool() [L829] 0 x$flush_delayed = weak$$choice2 [L830] 0 x$mem_tmp = x VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L831] EXPR 0 !x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff1) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L831] 0 x = !x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff1) [L832] EXPR 0 weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L832] 0 x$w_buff0 = weak$$choice2 ? x$w_buff0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff0 : x$w_buff0)) [L833] EXPR 0 weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff1 : x$w_buff1)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L833] 0 x$w_buff1 = weak$$choice2 ? x$w_buff1 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1 : (x$w_buff0_used && x$r_buff0_thd0 ? x$w_buff1 : x$w_buff1)) [L834] EXPR 0 weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L834] 0 x$w_buff0_used = weak$$choice2 ? x$w_buff0_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff0_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : x$w_buff0_used)) [L835] EXPR 0 weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L835] 0 x$w_buff1_used = weak$$choice2 ? x$w_buff1_used : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$w_buff1_used : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L837] EXPR 0 weak$$choice2 ? x$r_buff1_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff1_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] [L837] 0 x$r_buff1_thd0 = weak$$choice2 ? x$r_buff1_thd0 : (!x$w_buff0_used || !x$r_buff0_thd0 && !x$w_buff1_used || !x$r_buff0_thd0 && !x$r_buff1_thd0 ? x$r_buff1_thd0 : (x$w_buff0_used && x$r_buff0_thd0 ? (_Bool)0 : (_Bool)0)) [L838] 0 main$tmp_guard1 = !(x == 2 && y == 2 && __unbuffered_p2_EAX == 2 && __unbuffered_p2_EBX == 0) VAL [\result={0:0}, \result={0:0}, __unbuffered_cnt=3, __unbuffered_p2_EAX=2, __unbuffered_p2_EBX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=7, weak$$choice2=1, x=2, x$flush_delayed=1, x$mem_tmp=2, x$r_buff0_thd0=0, x$r_buff0_thd1=0, x$r_buff0_thd2=1, x$r_buff0_thd3=0, x$r_buff1_thd0=0, x$r_buff1_thd1=0, x$r_buff1_thd2=0, x$r_buff1_thd3=0, x$read_delayed=0, x$read_delayed_var={0:0}, x$w_buff0=2, x$w_buff0_used=0, x$w_buff1=0, x$w_buff1_used=0, y=2, z=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 166 locations, 2 error locations. Result: UNSAFE, OverallTime: 150.8s, OverallIterations: 22, TraceHistogramMax: 1, AutomataDifference: 27.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 3977 SDtfs, 3376 SDslu, 7763 SDs, 0 SdLazy, 5029 SolverSat, 177 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 3.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 168 GetRequests, 38 SyntacticMatches, 18 SemanticMatches, 112 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 173 ImplicationChecksByTransitivity, 0.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=254808occurred in iteration=7, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 103.6s AutomataMinimizationTime, 21 MinimizatonAttempts, 499027 StatesRemovedByMinimization, 18 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 0.7s InterpolantComputationTime, 931 NumberOfCodeBlocks, 931 NumberOfCodeBlocksAsserted, 22 NumberOfCheckSat, 842 ConstructedInterpolants, 0 QuantifiedInterpolants, 124996 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 21 InterpolantComputations, 21 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...